33689D

33689D FREESCALE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 31

Technical content

Features

• Full-Duplex SPI Interface at Frequencies up to 4.0 MHz
• LIN Transceiver Capable to 100 kbps with Waveshaping Capability
• 5.0 V Low Dropout Regulator Full Fault Detection and Protection
• One 50 mA and Two 150 mA Protected High-Side Switches
• Current Sense Operational Amplifier
• The 33689 is compatible with LIN 2.0 Specification Package.
• Pb-Free Packaging Designated by Suffix Code EW

Figure 1. 33689 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33689DDWB/R2 -40°C to 125°C 32 SOICW MCZ33689DEW/R2 DWB SUFFIX EW SUFFIX (PB-FREE) 98ARH99137A 32-PIN SOICW VPWR SPIMOSI SCK MISO 5.0 V MCU 33689 BUS VS1 VS2 VDD HS3 HS1 HS2 LIN INT RST MOSI SCLK MISO TXD RXD OUT GNDIN CS CS WDC TGND AGND VDD VCC

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Figure 2. 33689 Simplified Internal Block Diagram

5.0 V/50 mA

Figure 3. 33689 32-SOICW Pin Connections Table 1. 33689 32-SOICW Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 19. 1, 3, 14 NC No Connect N/A No internal connection to these pins. 2, 4 L1, L2 Level Inputs 1 and 2 Input Inputs from external switches or from logic circuitry. 8, 9, 24, 25 TGND Thermal Ground N/A Thermal ground pins for the device. 10 VS2 Voltage Supply 2 Input Supply pin for the high-side switches HS1, HS2, and HS3.

11 LIN LIN Bus Input / Output Bidirectional pin that represents the single-wire bus transmitter and

12 GND Ground N/A Electrical ground pin for the device. Output Output of the 5.0 V regulator.

16 AGND Analog Ground N/A Analog ground pin for voltage regulator and current sense operational

17 VCC Power Supply In Input 5.0 V supply for the internal current sense operational amplifier. 18 OUT Amplifier Output Output Output of the internal current sense operational amplifier.

19 E- Amplifier Inverted

Input Inverted input of the internal current sense operational amplifier.

20 E+ Amplifier Non-Inverted

Input Non-inverted input of the internal current sense operational amplifier.

21 WDC Watchdog

Reference Configuration pin for the watchdog timer.

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22 RST Reset Output

Output 5.0 V regulator and watchdog reset output pin. 23 IN PWM Input Control Input External input PWM control pin for high-side switches HS1 and HS2. 26 SCLK Serial Data Clock Input Clock input for the SPI of the 33689. 27 MOSI Master Out Slave In Input SPI data received by the 33689.

29 CS Chip Select

Input SPI control chip select input pin.

30 INT Interrupt Output

31 RXD Receiver Output Output Receiver output of the LIN interface and reports the state of the bus

32 TXD Transmitter Input Input Transmitter input of the LIN interface and controls the state of the bus

Table 1. 33689 32-SOICW Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33689

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device.

1. ESD1 testing is performed in accor dance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in

accordance with the Charge Device Model, Robotic (CZAP = 4.0 pF).

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• 40 to 125 - 40 to 150 Storage Temperature TSTG - 55 to 165 °C Thermal Resistance, Junction-to-Ambient RθJA 80 °C/ W Peak Package Reflow Temperature During Solder Mounting (2) TSOLDER 240 °C Notes 2. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause permanent damage to the device.

Figure 4. ISO 7637 Test Setup for LIN, L1, and L2 Pins Table 2. Maximum Ratings(continued) permanent damage to the device. Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33689 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

1. Device is fully functional. All features are operating. An overtemperature fault may occur.
2. Total current (I VS1 + IVS2) at VS1 and VS2 pins is measured at the ground pins.
3. Parameter guaranteed by design; however, it is not production tested.
4. Specification with external capacitor 2.0 µF < C < 10 µF and 200 mΩ ≤ ESR ≤ 10 Ω. Normal mode. Low ESR electrolytic capacitor values
5. Measured when the voltage has dropped 100 mV below its nominal value.

Digital outputs are supplied from VDD.

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STATIC ELECTRICAL CHARACTERISTICS VDD OUTPUT PIN (5.0 V OUTPUT FOR MCU USE) (CONTINUED) (9) Temperature Threshold Difference Normal Mode (TSD - TPRE) TDIFF 20 30 40 VSUP Range for Reset Active

0.5 V < VDD < VDD (V RSTTH)

4.0 — — V Line Regulation

5.5 V < VSUP < 27 V, IDD = 10 mA

— 20 150 mV Load Regulation 1.0 mA < IDD < 50 mA VLD1 — 10 150 mV VDD OUTPUT PIN IN STOP MODE Output Voltage (10) IDD ≤ 2.0 mA VDDS 4.75 5.0 5.25 V Output Current Capability (11) IDDS 4.0 8.0 14 mA Line Regulation 5.5 V < VSUP < 27 V, IDD = 2.0 mA VLRS — 10 100 mV Load Regulation 1.0 mA < IDD < 5.0 mA VLDS — 40 150 mV RST OUTPUT PIN IN NORMAL AND STOP MODES Reset Threshold Voltage V RSTTH 4.5 4.7 VDD - 0.2 V Low-Level Output Voltage IO = 1.5 mA, 4.5 V < VSUP < 27 V VOL 0.0 — 0.9 V High-Level Output Current 0.0 V < VOUT < 0.7 VDD IOH — - 275 — µA Reset Pulldown Current Internally Limited, VDD < 4.0 V, VRST = 4.6 V IPDRST 1.5 — 8.0 mA IN INPUT PIN Low-Level Input Voltage VIL - 0.3 — 0.3 VDD V High-Level Input Voltage VIH 0.7 VDD — VDD + 0.3 V Input Current

0.0 V < VIN < VDD

-10 — 10 µA Notes 9. Specification with external capacitor 2.0 µF < C < 10 µF and 200 mΩ ≤ ESR ≤ 10 Ω. Normal mode. Low ESR electrolytic capacitor values up to 47 µF can be used. 10. When switching from Normal mode to Stop mode or from Stop mode to Normal mode, the voltage can vary within the output voltage specification. 11. When I DD is above IDDS, the 33689 enters the Reset mode. Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33689 STATIC ELECTRICAL CHARACTERISTICS MISO SPI OUTPUT PIN Low-Level Output Voltage I OUT = 1.5 mA VOL 0.0 — 1.0 V High-Level Output Voltage I OUT = 250 µA VOH VDD - 0.9 — VDD V Tri-Stated MISO Output Leakage Current

0.0 V < VMISO < VDD

• 2.0 — 2.0 µA MOSI, SCLK, CS SPI INPUT PINS Low-Level Input Voltage VIL - 0.3 — 0.3 VDD V High-Level Input Voltage VIH 0.7 VDD — VDD + 0.3 V Pullup Input Current on CS VCS = 4.0 V IPUCS -100 — - 20 µA MOSI, SCLK Input Current

-10 — 10 µA INT OUTPUT PIN Low-Level Output Voltage IO = 1.5 mA VOL 0.0 — 0.9 V High-Level Output Voltage IO = - 250 µA VOH VDD - 0.9 — VDD V WDC PIN External Resistor Range R EXT 10 — 100 kΩ HS1 AND HS2 HIGH-SIDE OUTPUT PINS Output Clamp Voltage I OUT = -100 mA VCL - 6.0 — — V Output Drain-to-Source ON Resistance TA = 25°C, I OUT -150 mA TA = 125°C, I OUT -150 mA TA = 125°C, I OUT -120 mA RDS(ON) 2.0 3.0 2.5 4.5 4.0 Ω Output Current Limitation ILIM 300 430 600 mA Overtemperature Shutdown (12) TOTSD 155 — 190 °C Output Leakage Current ILEAK — — 10 µA Notes 12. When overtemperature occurs, switch is turned off and latc hed off. Flag is set in SPI Register. Refer to description on page 26. Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS HS3 HIGH-SIDE OUTPUT PIN Output Drain-to-Source ON Resistance TA = 25°C, I OUT - 50 mA TA = 125°C, I OUT - 50 mA TA = 125°C, I OUT - 30 mA RDS(ON) 5.5 7.0 Ω Output Current Limitation ILIM 60 100 200 mA Overtemperature Shutdown (13) TOTSD 155 — 190 °C Output Leakage Current ILEAK — — 10 µA OUT, E+, AND E- PINS AT CURRENT SENSE OPERATIONAL AMPLIFIER Input Voltage – Rail-to-Rail at E+ and E- VIMC - 0.1 — VCC + 0.1 V Output Voltage Range at OUT With ± 1.0 mA Output Load Current With ± 5.0 mA Output Load Current VOUT 0.1 0.3 VCC - 0.1 VCC - 0.3 V Input Bias Current I B — — 250 nA Input Offset Voltage V IO -15 — 15 mV Input Offset Current I O -100 — 100 nA L1 AND L2 INPUT PINS Low-Voltage Detection Input Threshold Voltage 5.5 V < VSUP < 6.0 V

6.0 V < VSUP < 18 V

18 V < VSUP < 27 V

2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.5 3.7 V High-Voltage Detection Input Threshold Voltage 5.5 V < VSUP < 6.0 V 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.5 4.7 V Input Hysteresis

5.5 V < VSUP < 27 V

0.5 — 1.3 V Input Current - 0.2 V < VIN < 40 V IIN -10 — 10 µA Notes 13. When overtemperature occurs, switch is turned off and latc hed off. Flag is set in SPI Register. Refer to description on page 26. Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33689 STATIC ELECTRICAL CHARACTERISTICS RXD OUTPUT PIN (LIN PHYSICAL LAYER) Low-Level Output Voltage I OUT ≤ 1.5 mA VOL 0.0 — 0.9 V High-Level Output Voltage I OUT ≤ 250 µA VOH 3.75 — 5.25 V TXD INPUT PIN (LIN PHYSICAL LAYER) Low-Level Input Voltage VIL — — 1.5 V High-Level Input Voltage VIH 3.5 — — V Input Hysteresis VINHYS 50 145 300 mV Pullup Current Source 1.0 V < VTXD < 3.5 V IPUTXD -100 — - 20 µA LIN PHYSICAL LAYER, TRANSCEIVER Transceiver Output Voltage Dominant State, TXD LOW, External Bus Pullup 500 Ω Recessive State, TXD HIGH, I OUT = 1.0 µA VLINDOM VLINREC VSUP -1.0 1.4 V Pullup Resistor to VSUP In Normal Mode and in Sleep and Stop Modes When Not Disabled by SPI RPU 20 30 47 kΩ Pullup Current Source In Sleep and Stop Modes When Pullup Disabled by SPI IPULIN — 1.3 — µA Output Current Shutdown Threshold IOUTSD 50 75 150 mA Leakage Output Current to GND VS1 and VS2 Disconnected, VLIN = 18 V Recessive State, 8.0 V < VSUP < 18 V, 8.0 V < VLIN < 18 V GND Disconnected, VGND = VSUP , VLIN = -18 V IBUSLEAK 0.0 -1.0 1.0 3.0 1.0 µA µA mA LIN PHYSICAL LAYER, RECEIVER Receiver Input Threshold Voltage Dominant State, TXD HIGH, RXD LOW Recessive State, TXD HIGH, RXD HIGH Center (VBUSDOM - VBUSREC) / 2 Hysteresis (VBUSDOM - VBUSREC) VBUSDOM VBUSREC VBUSCNT VBUSHYS 0.0 0.6 0.475 0.5 0.4 1.0 0.525 0.175 VSUP Bus Wake-Up Threshold VBUSWU — 0.5 — VSUP Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

1. Parameter guaranteed by design; however, it is not production tested.
2. Watchdog time period calculation formula: t WDC = 0.991 * R + 0.648 (R in kΩ and t WDC in ms).

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33689 DYNAMIC ELECTRICAL CHARACTERISTICS CURRENT SENSE OPERATIONAL AMPLIFIER Supply Voltage Rejection Ratio (16) SVR 60 — — dB Common Mode Rejection Ratio (16) CMR 70 — — dB Gain Bandwidth (16) GBP 1.0 — — MHz Output Slew Rate SR 0.5 — — V/µs Phase Margin PHMO 40 — — deg. Open Loop Gain (16) OLG — 85 — dB L1 AND L2 INPUT PINS Wake-Up Filter Time (16) t WUF 8.0 20 38 µs STATE MACHINE TIMING Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command) and Stop Mode Activation (16) Minimum Watchdog Period No Watchdog Selected Maximum Watchdog Period t STOP 1.4 6.0 5.0 µs Interrupt Low-Level Duration t INT 7.0 10 13 µs Internal Oscillator Frequency Accuracy (All Modes, for Information Only) fOSC - 35 — 35 % Normal Request Mode Time-Out (Normal Request Mode) t NRTOUT 97 150 205 ms Delay Between SPI Command and HS1 or HS2 Turn On (17), (18) Normal Mode, VSUP > 9.0 V, VHS ≥ 0.2 VVS2 t SHSON — — 20 µs Delay Between SPI Command and HS1 or HS2 Turn Off (17), (18) Normal Mode, VSUP > 9.0 V, VHS ≤ 0.8 VVS2 t SHSOFF — — 20 µs Delay Between SPI Command and HS3 Turn On (17), (19) Normal Mode, VSUP > 9.0 V, VHS ≥ 0.2 VVS2 tSHSON — — 20 µs Delay Between SPI Command and HS3 Turn Off (17), (19) Normal Mode, VSUP > 9.0 V, VHS ≤ 0.8 VVS2 tSHSOFF — — 20 µs Delay Between Normal Request and Normal Mode After a Watchdog Trigger Command (Normal Request Mode) (16) t SNR2N 7.0 15 30 µs Delay Between CS Wake-Up (CS LOW to HIGH) in Stop Mode and: Normal Request Mode, VDD ON and RST HIGH First Accepted SPI Command t WUCS t WUSPI N/A µs Delay Between Interrupt Pulse in Stop Mode After Wake-Up and First Accepted SPI Command t S1STSPI 30 — N/A µs Minimum Time Between Rising and Falling Edge on the CS t 2CS 15 — — µs Notes 16. Parameter guaranteed by design; however, it is not production tested. 17. When IN input is set to HIGH, delay starts at falling edge of clock cycle #8 of the SPI command and start of device activation/deactivation. 30 mA load on high-side switches. Excluding rise or fall time due to external load. 18. When IN is used to control the high-side switc hes, delays are measured between IN and HS1 or HS2 ON / OFF. 30 mA load on high-side switches, excluding rise or fall time due to external load. 19. Delay between turn on or turn off command and HS ON or HS OFF, excluding rise or fall time due to external load. Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

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DYNAMIC ELECTRICAL CHARACTERISTICS LIN PHYSICAL LAYER: BUS DRIVER TIMING CHARACTERISTICS FOR NORMAL SLEW RATE (20) Propagation Delay TXD to LIN (21) Dominant State Minimum Threshold (50% TXD to 58.1% VSUP) Dominant State Maximum Threshold (50% TXD to 28.4% VSUP) Recessive State Minimum Threshold (50% TXD to 42.2% VSUP) Recessive State Maximum Threshold (50% TXD to 74.4% VSUP) t DOMMIN t DOMMAX t RECMIN t RECMAX µs Propagation Delay Symmetry t DOMMIN - t RECMAX t DOMMAX - t RECMIN dt1s dt2s -10.44 µs LIN PHYSICAL LAYER: BUS DRIVER TIMING CHARACTERISTICS FOR SLOW SLEW RATE (20) Propagation Delay TXD to LIN (22) Dominant State Minimum Threshold (50% TXD to 61.6% VSUP) Dominant State Maximum Threshold (50% TXD to 25.1% VSUP) Recessive State Minimum Threshold (50% TXD to 38.9% VSUP) Recessive State Maximum Threshold (50% TXD to 77.8% VSUP) t DOMMIN t DOMMAX t RECMIN t RECMAX 100 100 100 100 µs Propagation Delay Symmetry t DOMMIN - t RECMAX t DOMMAX - t RECMIN dt1s dt2s - 22 µs LIN PHYSICAL LAYER: BUS DRIVER FAST SLEW RATE LIN High Slew Rate (Programming Mode) dv/dt Fast — 13 — V/µs LIN PHYSICAL LAYER, TRANSCEIVER Output Current Shutdown Delay (23) t OUTDLY — 10 — µs Notes Figure 5, page 16. 21. See Figure 7, page 17. 22. See Figure 8, page 17. 23. Parameter guaranteed by design; however, it is not production tested. Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 33689 DYNAMIC ELECTRICAL CHARACTERISTICS LIN PHYSICAL LAYER: RECEIVER CHARACTERISTICS AND WAKE-UP TIMINGS Propagation Delay LIN to RXD (24) Dominant State (LIN LOW to RXD LOW) Recessive State (LIN HIGH to RXD HIGH) Symmetry (t RDOM - t RREC) t RDOM t RREC t RSYM - 2.0 3.0 3.0 6.0 6.0 2.0 µs Bus Wake-Up Deglitcher (Sleep and Stop Modes) (25) t PROPWL 30 70 90 µs Bus Wake-Up Event Reported From Sleep Mode (26) From Stop Mode (27) t WU t WU µs Notes 24. Measured between LIN signal threshold VINL or VINH and 50% of RXD signal. 25. See Figures 9 and 10, page 18. 26. t WU is typically 2 internal clock cycles after a LIN rising edge is detected. In Sleep Mode, the measurement is done without a capacitor connected to the regulator. The delay is measured between the VSUP/2 rising edge of the LIN bus and when VDD reaches 3.0 V. The VDD rise time is strongly dependent upon the decoupling capacitor at VDD pin. See Figure 9, page 18. 27. t WU is typically 2 internal clock cycles after a LIN rising edge is detected. In Stop Mode, the delay is measured between the VSUP/2 rising edge of the LIN bus and the falling edge of the INT pin. See Figure 10, page 18. Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

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Figure 5. Test Circuit for Timing Measurements Figure 6. SPI Timing Characteristics at SCLK rising edge (after tVALID delay time).

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Figure 9. LIN Bus Wake-Up Behavior, Sleep Mode Figure 10. LIN Bus Wake-Up Behavior, Stop Mode

0.4 VSUP

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33689 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION A System Basis Chip (SBC) is a monolithic IC combining many functions found in standard microcontroller-based systems; e.g., power management, communication interface, system protection, and diagnostics. The 33689 is a SPI-controlled SBC combining many functions with a LIN transceiver for slave node applications. The 33689 has a 5.0 V, 50 mA regulator with undervoltage reset, output current limiting, overtemperature pre-warning, and thermal shutdown. An externally selectable timing Window Watchdog is also included. The LIN transceiver has waveshaping that can be disabled when high data rates are warranted. A single 50 mA and two 150 mA fully protected high-side switches with output clamping are available for switching inductive or resistive loads. The 150 mA switches are PWM capable. Two high-voltage inputs can be used to monitor switches or provide external wake-up. An internal current sense operational amplifier is available for load current monitoring. FUNCTIONAL PIN DESCRIPTION LEVEL 1 AND LEVEL 2 INPUT PINS (L1 AND L2) These pins are used to sense external switches and to wake up the 33689 from Sleep or Stop mode. During Normal mode, the state of these pins can be read through the SPI Register. (Refer to the section entitled SPI Interface and Register Description on page 24 for information on the SPI Register.) HIGH-SIDE DRIVER OUTPUT PINS 1 AND 2 (HS1 AND HS2) These two high-side switches are able to drive loads such as relays or lamps. They are protected against overcurrent and overtemperature and include internal clamp circuitry for inductive load protection. Switch control is done through selecting the correct bit in the SPI Register. HS1 and HS2 can be PWM-ed if required through the IN input pin. The internal circuitry that drives both high-side switches is an AND function between the SPI bit HS1 (or HS2) and the IN input pin. If no PWM control is required, the IN pin must be connected to the VDD pin. HIGH-SIDE DRIVER OUTPUT PIN 3 (HS3) This high-side switch can be used to drive small lamps, Hall sensors, or switch pullup resistors. Control is done through the SPI Register only. No direct PWM control is possible on this pin. This high-side switch features current limit to protect it against overcurrent and short circuit conditions. It is also protected against overtemperature. VOLTAGE SUPPLY PINS 1 AND 2 (VS1 AND VS2) The 33689 is supplied from a battery line or other supply source through the VS1 and VS2 pins. An external diode is required to protect against negative transients and reverse battery. The 33689 can operate from 4.5 V and under the jump start condition at 27 V DC. Device functionality is guaranteed down to 4.5 V at VS1 and VS2 pins. These pins sustain standard automotive voltage conditions such as load dump at 40 V. LIN BUS PIN (LIN) The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. VOLTAGE SOURCE PIN (VDD) The VDD pin is the 5.0 V supply pin for the MCU and the current sense operational amplifier. CURRENT SENSE OPERATIONAL AMPLIFIER PINS (E+, E- , VCC, AND OUT) These are the pins of the single-supply current sense operational amplifier.

• The E+ and the E- input pins are the non-inverting and inverting inputs of the current sense operational amplifier, respectively.
• The OUT pin is the output pin of the current sense operational amplifier.
• The VCC pin is the + 5.0 V single-supply connection for the current sense operational amplifier. The current sense operational amplifier is enabled in Normal mode only. WATCHDOG CONFIGURATION PIN (WDC) The WDC pin is the configuration pin for the internal watchdog. A resistor is connected to this pin. The resistor value defines the watchdog period. If the pin is left open, the watchdog period is fixed to its default value (150 ms typical). If no watchdog function is required, the WDC pin must be connected to GND.

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FUNCTIONAL PIN DESCRIPTION RESET OUTPUT PIN (RST) The RST pin is the 5.0 V regulator and Watchdog reset output pin. PWM INPUT CONTROL PIN (IN) The IN pin is the external PWM control pin for the HS1 and HS2 high-side switches. SERIAL DATA CLOCK PIN (SCLK) The SCLK pin is the SPI clock input pin. MISO data changes on the negative transition of the SCLK. MOSI is sampled on the positive edge of the SCLK. MASTER OUT SLAVE IN PIN (MOSI) The MOSI pin receives SPI data from the MCU. This data input is sampled on the positive edge of SCLK. MASTER IN SLAVE OUT PIN (MISO) The MISO pin sends data to an SPI-enabled MCU. Data on this output pin changes on the negative edge of the SCLK. When CS is HIGH, this pin enters the high-impedance state. CHIP SELECT PIN (CS) The CS pin is the chip select input pin for SPI use. When this signal is high, SPI signals are ignored. Asserting this pin LOW starts an SPI transaction. The transaction is completed when this signal returns HIGH. INTERRUPT OUTPUT PIN (INT) The INT pin is used to report 33689 faults to the MCU. Interrupt pulses are generated for:

• Voltage regulator temperature pre-warning
• HS1, HS2, or HS3 thermal shutdown
• VS1 or VS2 overvoltage (20 V typical)
• VS1 or VS2 undervoltage (6.0 V typical) If an interrupt is generated, then when the next SPI read operation is performed bit D7 in the SPI Register will be set to logic [1] and bits D6 : D0 will report the interrupt source. In cases of wake-up from the Stop mode, INT is set LOW in order to signal to the MCU that a wake-up event from the L1, L2, or LIN bus pin has occurred. RECEIVER OUTPUT PIN (RXD) The RXD pin is the receiver output of the LIN interface and reports the state of the bus voltage (RXD LOW when LIN bus is dominant, RXD HIGH when LIN bus is recessive). TRANSMITTER INPUT PIN (TXD) The TXD pin is the transmitter input of the LIN interface and controls the state of the bus output (dominant when TXD is LOW, recessive when TXD is HIGH). GROUND PINS (GND, TGND, AND AGND) The 33689 has three different types of ground pins.
• The GND pin is the electrical ground pin for the device.
• The AGND is the analog ground pin for the voltage regulator and current sense operational amplifier.
• The four TGND pins are the thermal ground pins for the device. Important The GND, the AGND, and the four TGND pins must be connected together to a ground external to the 33689.

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there are two transitional modes: Reset and Normal Request. 150 ms the 33689 goes in Sleep Mode. transmit and receive information. Figure 1. 33689 Modes State Diagram

33689 Power-Up

Watchdog Selected: External resistor between WDC pin and GND or WDC pin open. Watchdog Not Selected: WDC pin connected to GND. Watchdog Fail: Watchdog trigger occurs in closed window or no SPI Watchdog trigger command. Stop Command: SPI stop command. Sleep Command: SPI sleep request followed by SPI sleep command.

ON and the watchdog function can be enabled. command. Register bit D5 must be set accordingly. Table 1. Operational Modes and Associated Functions

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between two rising edges on the CS pin is 15 µs. Figure 2. Data Format Description showing reset values and reset conditions. Table 2. SPI Register Overview

1. D7 signals interrupt source. After interrupt occurs, if D7 is a logic [1] D6 : D0 indicate the interrupt source. If D7 is a logic [0] no interrupt

has occurred and D6 : D0 report real-time status.

1. The first SPI read after a 33689 reset returns the BATFAIL status flag bit D4.

Table 3. LIN Slew Rate Control and Device Low Power

Table 5. Reset clears the HSx bit. must be connected to the VDD pin. modes in accordance with Table 6. Table 7, must be sent twice. Table 8, must be sent twice. Table 4. LIN Pullup Termination Control Bit (D5) Table 5. High-Side Switches Control Bits (D4, D3, and D2)

0 HS3 OFF 0 HS2 OFF 0 HS1 OFF

1 HS3 ON 1 HS2 ON (if IN = 1) 1 HS1 ON (if IN = 1)

Table 6. Mode Control Bits (D1 and D0)

1. Special SPI command and sequence is implemented in

8-bit SPI command. Refer to Tables 7 and 8.

1. When a logic [0] is written to MODE1 bit while MODE2 bit

Normal Request mode (150 ms) has no window. Table 7. Sleep Command Bits Table 8. Stop Command Bits

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overcurrent/overtemperature in accordance with Table 10.

• VSOV flag is set on an overvoltage condition.
• VSUV/BATFAIL flag is set on an undervoltage condition.
• VDDT flag is set as pre-warning in case of an overtemperature condition on the voltage regulator.
• HSST flag is set on overtemperature conditions on one of the high-side outputs. L2 and L1 — Wake-Up Inputs L2 and L1 Status Flag Bit The L2 and L1 flags, as shown in Table 12, reflect the status of the L2 and L1 input pins and indicate the wake-up source.

Table 9. Interrupt Status (D7)

0 SPI word read reflects the flag state

1 SPI word read reflects the interrupt or wake-up

Table 10. LIN Bus Status (D6)

0 No LIN bus wake-up or failure

1 LIN bus wake-up occurred or LIN overcurrent /

Table 11. Over- and Undervoltage, VDD Voltage Regulator, and High-Side Status Flag Bits (D5, D4, D3, and D2)

1 HS1, HS2, or HS3

Table 12. Switch Input Wake-Up and Real Time Status (D1 and D0)

0 L2 input LOW 0 L1 input LOW

1 L2 input HIGH or wake-up by L2

1 L1 input HIGH or wake-up by L1

The 33689 can be configured in several applications. Figure 3 shows the 33689 in the typical master node application. Figure 3. 33689 in Typical Master Node Application

5.0 V/50 mAVDD VS1

1. L1 and R8 are external components to improve EMC and ESD performances.
2. Freescale does not assume liability, endorse, or warrant component s from external manufacturers that are referenced in circuit

Analog Integrated Circuit Device Data

28 Freescale Semiconductor

Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number below. DWB SUFFIX 32-PIN SOIC WIDE BODY PLASTIC PACKAGE 98ARH99137A ISSUE B EW SUFFIX (Pb-FREE)

Analog Integrated Circuit Device Data Freescale Semiconductor 29 33689 PACKAGING PACKAGING DIMENSIONS (CONTINUED) PACKAGING DIMENSIONS (CONTINUED) DWB SUFFIX 32-PIN SOIC WIDE BODY PLASTIC PACKAGE 98ARH99137A ISSUE B EW SUFFIX (Pb-FREE)

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 6.0 6/2006 • Implemented Revision History page

• Updated Outline Drawing to Revision “B”
• Eliminated all pages (pages 30 to 47) referring to the MC33689DWB/R2 device
• Removed MC33689DWB/R2 from the orderable parts information
• Updated to the prevailing form and style 7.0 8/2006 • Removed MC33689DEW/R2 and replaced with MCZ33689DEW/R2 in the Ordering Information block

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