MC33663 FREESCALE | Alldatasheet
Document overview
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Technical content
Features
- Operational from V SUP 7.0 to 18 V DC, functional up to 27 V DC, and handles 40 V during load dump
- Compatible with LIN protocol specification 2.1, and SAEJ2602-2
- Very high immunity against electromagnetic interference
- Low standby current in Sleep mode
- Over-temperature protection
- Permanent dominant state detection
- Fast baud rate mode selection reported by RXD
- Active bus waveshaping offering excellent radiated emission performance
- S u s t a i n s ±15.0 kV ESD IEC6100-4-2 on LIN BUS and VSUP pins
- 5.0 and 3.3 V compatible digital inputs without any external components required
Figure 1. 33663 Simplified Application Diagram
ORDERING INFORMATION
(add an R2 suffix for Tape and reel orders) Temperature Range (TA) Package MC33663ALEF - 40 to 125°C 14 SOICNMC33663AJEF MC33663ASEF VSUP EN1 RXD1 TXD1 EN2 RXD2 TXD2 GND WAKE1 WAKE2 INH1 INH2 LIN1 LIN2 VDD12 V 5.0 or 3.3 V 33663 MCURegulator VBAT LIN Interface 1 LIN Interface 2 1.0 k 1.0 k
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Table 1. Device Variations
Figure 2. 33663 Simplified Internal Block Diagram
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Figure 3. 33663 14-SOIC Pin Connections Table 2. 33663 Pin Definitions 1 WAKE1 Wake Input This pin is a high-voltage input used to wake-up the LIN1 from Sleep mode. 3 LIN1 LIN Bus This bidirectional pin represents the LIN1 single-wire bus transmitter and receiver. 4 LIN2 LIN Bus This bidirectional pin represents the LIN2 single-wire bus transmitter and receiver.
5 INH2 Inhibit Output This pin can have two main functions: controlling an external switchable voltage
the master node application. voltage to the MCU interface. 7 EN2 Enable Control This pin controls the operation mode of the LIN2 interface. 8 WAKE2 Wake Input This pin is a high-voltage input used to wake-up the LIN2 device from Sleep mode. 9 GND Ground This pin is the device ground pin. 11 VSUP Power Supply This pin is device battery level power supply.
12 INH1 Inhibit Output This pin can have two main functions: controlling an external switchable voltage
the master node application. voltage to the MCU interface. 14 EN1 Enable Control This pin controls the operation mode of the LIN1 interface.
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ELECTRICAL CHARACTERISTICS
Table 3. Maximum Ratings permanent damage to the device.
- Class A: All functions of a devic e/system perform as designed during and after exposure to disturbance.
- Class D: At least one function of the Transceiver stops worki ng properly during the test and will return into proper operation automatically
when the exposure to the disturbance has ended. No physical damage of the IC occurs.
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INH Voltage / Current (VINH1, VINH2) DC Voltage Transient (Coupled Through 1.0 nF Capacitor, according to ISO7637-2 & ISO7637-3 & “Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive Applications” specification Rev1.1 / December 2nd, 2009) (See Table 4 and Figure 7) - Pulse 1 (test up to the limit for Damage - Class D(3)) - Pulse 2a (test up to the limit for Damage - Class D(3)) - Pulse 3a (test up to the limit for Damage - Class D(3)) - Pulse 3b (test up to the limit for Damage - Class D(3)) VINH VINH(S1) VINH(S2a) VINH(S3a) VINH(S3b) - 0.3 to VSUP + 0.3 -100 +75 -150 +100 V Notes 3. Class D: At least one function of the Transceiver stops worki ng properly during the test and will return into proper operation automatically when the exposure to the disturbance has ended. No physical damage of the IC occurs. permanent damage to the device.
Analog Integrated Circuit Device Data Freescale Semiconductor 7 33663 Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 ) LIN1, LIN2 pins versus GND WAKE1, WAKE2 pins versus GND INH1, INH2 pins versus GND All other Pins Charge Device Model - JESD22/C101 (CZAP = 4.0 pF Corner pins (Pins 1, 7, 8 and 14) All other pins (Pins 2-6, 9-13) Machine Model - JESD22/A115 (CZAP = 220 pF, RZAP = 0 ) All pins According to “Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive Applications” specification Rev1.1 / December 2nd, 2009 (CZAP = 150 pF, RZAP = 330 ) Contact Discharge, Unpowered LIN1, LIN2 pins without capacitor LIN1, LIN2 pins with 220 pF capacitor VSUP (10 µF to ground) WAKE1, WAKE2 (2*18 k serial resistor) LIN1, LIN2 pins with 220 pF capacitor and indirect ESD coupling (according to ISO10605 - Annex F) According to ISO10605 - Rev 2008 test specification (2.0 k / 150 pF) - Unpowered - Contact discharge LIN1, LIN2 pins without capacitor LIN1, LIN2 pins with 220 pF capacitor VSUP (10 µF to ground) WAKE1, WAKE2 (2*18 k serial resistor) (2.0 k / 330 pF) - Powered - Contact discharge LIN1, LIN2 pins without capacitor LIN1, LIN2 pins with 220 pF capacitor VSUP (10 µF to ground) WAKE1, WAKE2 (2*18 k serial resistor) VESD1-1 VESD1-2 VESD1-3 VESD1-4 VESD2-1 VESD2-2 VESD3-1 VESD4-1 VESD4-2 VESD4-3 VESD4-4 VESD4-5 VESD5-1 VESD5-2 VESD5-3 VESD5-4 VESD6-1 VESD6-2 VESD6-3 VESD6-4 ± 10.0 k ± 8.0 k ± 8.0 k ± 4.0 k ± 750 ± 750 ± 200 ± 15 k ± 15 k ±25 k ±20 k ± 15 k ± 25 k ± 25 k ±25 k ±25 k ± 8 k ± 8 k ±25 k ±25 k V permanent damage to the device.
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Figure 4. Test Circuit for Transient Test Pulses (VSUP)
- Pin soldering temperature limit is for 10 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
- Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Table 4. Limits / Maximum test voltage for transient immunity tests permanent damage to the device.
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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics Characteristics noted under conditions 7.0 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
13.5 V < VSUP < 27 V
- Device is functional. All features are oper ating. Electrical parameters are not guaranteed.
Analog Integrated Circuit Device Data Freescale Semiconductor 11 33663 STATIC ELECTRICAL CHARACTERISTICS TXD1, TXD2 INPUT PINS (LOGIC) Low Level Input Voltage VIL – – 0.8 V High Level Input Voltage VIH 2.0 – – V Input Threshold Voltage Hysteresis VINHYST 100 300 600 mV Pull-up Current Source VEN = 5.0 V, 1.0 V < VTXD < 3.5 V IPU - 60 - 35 - 20 EN1, EN2 INPUT PINS (LOGIC) Low Level Input Voltage VIL – – 0.8 V High Level Input Voltage VIH 2.0 – – V Input Voltage Threshold Hysteresis VINHYST 100 400 600 mV Pull-down Resistor RPD 100 230 350 kohm LIN PHYSICAL LAYER - TRANSCEIVER LIN (LIN1, LIN2)(7) Operating Voltage Range(8) VBAT 8.0 – 18 V Supply Voltage Range VSUP 7.0 – 18 V Voltage Range (within which the device is not destroyed) VSUP_NON_OP -0.3 – 40 V Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V IBUS_LIM 40 90 200 mA Input Leakage Current at the Receiver Driver off; VBUS = 0 V; VBAT = 12 V IBUS_PAS_DOM -1.0 – – mA Leakage Output Current to GND Driver Off; 8.0 V VBAT 18 V; 8.0 V VBUS 18 V; VBUS VBAT; VBUS VSUP IBUS_PAS_REC – – 20 µA Control Unit Disconnected from Ground(9) GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V IBUS_NO_GND -1.0 – 1.0 mA VBAT Disconnected; VSUP_DEVICE = GND; 0 V < VBUS < 18 V(10) IBUSNO_BAT – – 10 µA Receiver Dominant State(11) VBUSDOM – – 0.4 VSUP Receiver Recessive State(12) VBUSREC 0.6 – – VSUP Notes 7. Parameters guaranteed for 7.0 V VSUP 18 V. 8. Voltage range at the battery level, including the reverse battery diode. 9. Loss of local ground must not affect communication in the residual network. 10. Node has to sustain the current that can flow under this c ondition. The bus must remain operational under this condition. 11. LIN threshold for a dominant state. 12. LIN threshold for a recessive state. Characteristics noted under conditions 7.0 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
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STATIC ELECTRICAL CHARACTERISTICS Receiver Threshold Center (VTH_DOM + VTH_REC)/2 VBUS_CNT 0.475 0.5 0.525 VSUP Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) VHYS – – 0.175 VSUP LIN dominant level with 500 680 and 1.0 k load on the LIN bus VLINDOM_LEVEL – – 0.3 VSUP VBAT_SHIFT VSHIFT_BAT 0.0 – 11.5% VBAT GND_SHIFT VSHIFT_GND 0.0 – 11.5% VBAT LIN Wake-up Threshold from Sleep Mode VBUSWU – 4.3 5.3 V LIN Pull-up Resistor to VSUP RSLAVE 20 30 60 k LIN internal capacitor(13) CLIN – – 30 pF Over-temperature Shutdown(14) TLINSD 150 160 200 °C Over-temperature Shutdown Hysteresis TLINSD_HYS – 20 – °C INH1, INH2 OUTPUT PINS Driver ON Resistance (Normal Mode) IINH = 50 mA INHON – – 50 Current load capability From 7.0 V < VSUP < 18 V IINH_load – – 30 mA Leakage Current (Sleep Mode) 0 < VINH < VSUP ILEAK -5.0 – 5.0 Over-temperature Shutdown(15) TINHSD 150 160 200 °C Over-temperature Shutdown Hysteresis TINHSD_HYS – 20 – °C Notes 13. This parameter is guaranteed by process monitoring but not production tested. 14. When an over-temperature shutdown occurs, the LIN transmitter and receiver are in recessive state and INH switched off. This parameter is tested with a test mode on ATE and characterized at laboratory. 15. When an over-temperature shutdown occurs, the INH1, INH2 high side are switched off and the LIN transmitter and receiver are in recessive state. This parameter is tested with a test mode on ATE and characterized at laboratory. Characteristics noted under conditions 7.0 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 13 33663 STATIC ELECTRICAL CHARACTERISTICS WAKE1, WAKE2 INPUT PINS High to Low Detection Threshold (5.5 V < VSUP < 7 V) VWUHL1 2.0 – 3.9 V Low to High Detection Threshold (5.5 V < VSUP < 7 V) VWULH1 2.4 – 4.3 V Hysteresis (5.5 V < VSUP < 7 V) VWUHYS1 0.2 – 0.8 V High to Low Detection Threshold (7 V VSUP < 27 V) VWUHL2 2.4 – 3.9 V Low to High Detection Threshold (7 V VSUP < 27 V) VWULH2 2.9 – 4.3 V Hysteresis (7 V VSUP < 27 V) VWUHYS2 0.2 – 0.8 V Wake-up Input Current (VWAKE < 27 V) IWU – – 5.0 µA Characteristics noted under conditions 7.0 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
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DYNAMIC ELECTRICAL CHARACTERISTIC DYNAMIC ELECTRICAL CHARACTERISTIC Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 7.0 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. threshold defined at each parameter. See Figure 8. signal to LIN signal threshold defined at each parameter. See Figure 8.
Analog Integrated Circuit Device Data Freescale Semiconductor 15 33663 DYNAMIC ELECTRICAL CHARACTERISTIC LIN1, LIN2 PHYSICAL LAYER - RECEIVERS CHARACTERISTICS ACCORDING LIN2.1(21) 33663L AND 33663J AND 33663S Propagation Delay and Symmetry(22) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR t REC_PD t REC_SYM - 2.0 6.0 2.0 LIN1, LIN2 PHYSICAL LAYER: RECEIVER CHARACTERISTICS WITH TIGHTEN LIMITS(21) 33663S DEVICE Propagation Delay and Symmetry(22) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR t REC_PD_S t REC_SYM_S - 1.3 5.0 1.3 LIN1, LIN2 PHYSICAL LAYER: RECEIVER CHARACTERISTICS - LIN SLOPE 1V/ns(21) 33663S DEVICE Propagation Delay and Symmetry(23) Propagation Delay of Receiver, tREC_PD _FAST= MAX (tREC_PDR_FAST, tREC_PDF_FAST) Symmetry of Receiver Propagation Delay, tREC_PDF_FAST - tREC_PDR_FAST t REC_PD_FAST t REC_SYM_FAST - 1.3 6.0 1.3 SLEEP MODE AND WAKE-UP TIMINGS Sleep Mode Delay Time(24) after EN High to Low to INH High to Low with 100µA load on INH t SD 50 — 91 µs WAKE-UP TIMINGS Bus Wake-up Deglitcher (Sleep Mode) (25) t WUF 40 70 100 s EN Wake-up Deglitcher (26) EN High to INH Low to High t LWUE — — 15 Wake-up Deglitcher (27) Wake state change to INH Low to High t WF 10 48 70 Notes signal to LIN signal threshold defined at each parameter. See Figure 8. 22. See Figure 12 23. See Figure 13 24. See Figures 22 and 23 25. See Figures 15 and 17 26. See Figures 14, 18, 22, and 23 27. See Figures 16, 22, and 23 Characteristics noted under conditions 7.0 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
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Figure 8. Test Circuit for Timing Measurements
- The LIN is in recessive state and the receiver is still active
Characteristics noted under conditions 7.0 V VSUP 18 V, - 40 C TA 125 C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
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Figure 11. LIN1, LIN2 Transmitter Timing for 33663S Figure 12. LIN1, LIN2 Receiver Timing Figure 13. LIN1, LIN2 Receiver Timing LIN Slope 1.0 V/ns
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Figure 16. LIN Module 1 Wake1 Pin Wake-up with TXD1
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Figure 20. Fast Baud Rate Mode Exit (Back to Normal or Slow Slew Rate) for LIN1 or LIN2 Figure 21. Power Up and Down Sequences
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Figure 23. Examples of Sleep Mode Sequences for LIN1 or LIN2
Analog Integrated Circuit Device Data Freescale Semiconductor 25 33663 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33663L and 33663J are both a Physical Layer component dedicated to automotive LIN sub-bus applications. The 33663L features include a 20 kbps baud rate and the 33663J a 10 kbps baud rate. Both integrate fast baud rate for test and programming modes, excellent ESD robustness, immunity against disturbance, and radiated emission performance. They have safe behavior, in case of a LIN bus short-to-ground, or a LIN bus leakage during low power mode. Digital inputs are 5.0 and 3.3 V compatible without any external required components. The INH1 and INH2 outputs may be used to control an external voltage regulator, or to drive a LIN bus pull-up resistor. FUNCTIONAL PIN DESCRIPTION POWER SUPPLY PIN (VSUP) The VSUP supply pin is the power supply pin for the 33663L or 33663J. In an application, the pin is connected to a battery through a serial diode, for reverse battery protection. The DC operating voltage is from 7.0 to 18 V. This pin sustains standard automotive condition, such as 40 V during load dump. To avoid a false bus message, an under-voltage on VSUP disables the transmission path (from TXD to LIN) when VSUP falls below 6.7 V. Supply current in the Sleep mode is typically 6.0 A for one LIN Module. GROUND PIN (GND) In case of a ground disconnection at the module level, the 33663L and 33663J do not have significant current consumption on the LIN bus pin when in the recessive state. LIN BUS PIN (LIN1, LIN2) The LIN1 and LIN2 pins represent the single-wire bus transmitter and receiver. It is suited for automotive bus systems, and is compliant to the LIN bus specification 1.3, 2.0, 2.1, and SAEJ2602-2. The LIN interface is only active during Normal mode. Transmitter Characteristics The LIN driver is a low side MOSFET with internal over-current thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated, so no external pull-up components are required for the application in a slave node. An additional pull-up resistor of 1.0 k must be added when the interface is used in the master node. The LIN pin exhibits no reverse current from the LIN bus line to VSUP, even in the event of a GND shift or VSUP disconnection. The 33663 is tested according to the application conditions (i.e. in normal mode and recessive state during communication). The transmitter has a 20 kbps baud rate (Normal baud rate) for the 33663L and 33663S devices, or 10 kbps baud rate (Slow baud rate) for the 33663J device. TXD RXD 35µA LIN Driver LIN VSUP EN_sleep INH_ON Slope Control Receiver 725 k30 k INH LIN Undervoltage LIN overtemperature TXD Dominant LIN Wake up EN X 1 INH overtemperature INH switched off & LIN transmitter and receiver disabled OR
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The receiver thresholds are ratiometric with the device supply pin. state even if communication is sent to TXD1 or TXD2. For the LIN Module 1, in case of LIN1 Thermal Shutdown, the transceiver and receiver are in recessive and INH1 turned off. Baud Rate entry (See Figure 19). turned OFF. TXD1/TXD2 pins thresholds are 3.3 V and 5.0 V compatible. These pins have an internal pull-up current source to force the recessive state if the input pins are left floating. automatically into recessive state. description is the same for both. RXD output pin is the MCU interface, which reports the state of the LIN bus voltage. a low voltage on RXD. The RXD output structure is a tristate output buffer. Figure 24. RXD interface RXD is pulled LOW to report the wake-up event. An external pull-up resistor may be needed.
Analog Integrated Circuit Device Data Freescale Semiconductor 27 33663 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION ENABLE INPUT PINS (EN1, EN2) EN1 (EN2) input pin controls the operation mode of the interface. If EN1 (EN2) = 1, the interface is in Normal mode, TXD1 (TXD2) to LIN1 (LIN2) after tFIRS_DOM delay and LIN1 (LIN2) to RXD1 (RXD2) paths are both active. EN1 (EN2) pin thresholds are 3.3 V and 5.0 V compatible. RXD1 (RXD2) VOH level follows EN1 (EN2) pin high level. One LIN Module enters the Sleep Mode by setting EN1 (EN2) LOW for a delay higher than tSD (70 µs typ. value) and if the WAKE1 (WAKE2) pin state doesn’t change during this delay. (see Figure 22). Both LIN Modules enter Sleep Mode if EN1 & EN2 LOW. A combination of the logic levels on EN1 (EN2) and TXD1 (TXD2) pins allows the device to enter in Fast Baud Rate mode of operation (see Figure 19). INHIBIT OUTPUT PINS (INH1, INH2) The INH1 (INH2) output pin is connected to an internal high side power MOSFET. The pin has two possible main functions. It can be used to control an external switchable voltage regulator having an inhibit input. It can also be used to drive the LIN bus external resistor in the master node application, thanks to its high drive capability. This is illustrated in Figure 26. In Sleep mode, INH1 (INH2) is turned OFF. If a voltage regulator inhibit input is connected to INH1 (INH2), the regulator will be disabled. If the master node pull-up resistor is connected to INH1 (INH2), the pull-up resistor will be unpowered and left floating. In case of a INH1 (INH2) thermal shutdown, the high side is turned off and the LIN1 (LIN2) transmitter and receiver are in recessive state. An external 10 to 100 pF capacitor on INH1 (INH2) pin is advised in order to improve EMC performances. WAKE INPUT PINS (WAKE1, WAKE2) The WAKE1 (WAKE2) pin is a high-voltage input used to wake-up the device from the Sleep mode. WAKE1 (WAKE2) is usually connected to an external switch in the application. The WAKE1 (WAKE2) pin has a special design structure and allows wake-up from both HIGH to LOW or LOW to HIGH transitions. When entering into Sleep mode, the corresponded LIN Module monitors the state of its WAKE pin and stores it as a reference state. The opposite state of this reference state will be the wake-up event used by the LIN Module to enter again into Normal mode. If the WAKE1 (WAKE2) pin state changes during the Sleep mode Delay Time (tSD) or before EN1 (EN2) goes low with a deglitcher lower than tWF, the LIN Module will not enter in Sleep mode, but will go into Awake mode (See Figure 23). An internal filter is implemented to avoid false wake-up event due to parasitic pulses (See Figure 16). WAKE1 (WAKE2) pin input structure exhibits a high-impedance, with extremely low input current when voltage at this pin is below 27 V. Two serial resistors should be inserted in order to limit the input current mainly during transient pulses and ESD. The total recommended resistor value is 33 k. An external 10 to 100 nF capacitor is advised for better EMC and ESD performances. Important The WAKE1 (WAKE2) pin should not be left open. If the wake-up function is not used, WAKE1 (WAKE2) should be connected to ground to avoid a false wake-up.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES As described by the following, the 33663L, 33663J, and 33663S have two operational modes, Normal and Sleep. In addition, there are two transitional modes: Awake mode which allows the device to go into Normal mode, and Preparation to Sleep mode which allows the device to go into Sleep mode. NORMAL OR SLOW BAUD RATE In the Normal mode, the LIN bus can transmit and receive information. The 33663L and 33663S (20 kbps) have a slew rate and timing compatible with Normal Baud Rate and LIN protocol The 33663J (10 kbps) has a slew rate and timing compatible with Low Baud Rate. From Normal mode, the three devices can enter into Fast Baud Rate (Toggle function). FAST BAUD RATE In fast baud rate, the slew rate is around 10 times faster than the normal baud rate. This allows very fast data transmission (> 100 kbps) -- for example, electronic control unit (ECU) tests and microcontroller program download. The bus pull-up resistor might be adjusted to ensure a correct RC time constant in line with the high baud rate used. The following sequence is applicable to both LIN Modules independently. Fast baud rate is entered via a special sequence (called toggle function) as follows: 1. EN1 pin set LOW while TXD1 is HIGH 2. TXD1 stays HIGH for 12.5 µs min 3. TXD1 set LOW for 12.5 µs min 4. TXD1 pulled HIGH for 12.5 µs min 5. EN1 pin set LOW to HIGH while TXD1 still HIGH The LIN Module enters into the fast baud rate if the delay between step 1 to step 5 is 45 µs maximum. The toggle function is described in Figures 19. Once in fast baud rate, the same toggle function just described previously is used to bring the LIN Module 1 back into normal baud rate. Fast baud rate selection is reported to the MCU by the RXD1 pin. Once the LIN Module 1 enters in this fast baud rate, the RXD1 pin goes at low level for t5. When LIN Module 1 returns to normal baud rate with the same toggle function, the RXD1 pin stays high. Both sequences are illustrated in Figures 19 and 20. PREPARATION TO SLEEP MODE The following sequence is applicable to both LIN Modules simultaneously or separately. Here it is detailed with the LIN Module To enter the Preparation to Sleep mode, EN1 must be low for a delay higher than tLWUE.
- If the WAKE1 pin state doesn’t change during tSD and tLWUE, then the LIN Module 1 goes in Sleep Mode.
- If the WAKE1 pin state changes during t SD and if tWF is reached after end of tSD, then the LIN Module 1 goes into Sleep mode after the end of tSD timing.
- If the WAKE1 pin stat e changes during tSD and tWF delay has been reached before end of tSD, then the LIN Module 1 goes into Awake Mode.
- If the WAKE1 pin state changes before t SD and the delay tWF ends during tSD, then the LIN Module 1 goes in Awake Mode.
- If EN1 goes high for a delay higher than t LWUE, the LIN Module 1 returns in Normal mode. SLEEP MODE The following Sleep mode paragraph is applicable to both LIN Modules simultaneously or separately. LIN Module 1 is an example. To enter into Sleep mode, EN1 must be low for a delay longer than tSD and the WAKE1 pin must stay in the same state (High or Low) during this delay. The LIN Module 1 conditions to not enter Sleep mode, but enter Awake mode are detailed in the Preparation into Sleep Mode chapter. See Figure 23.
Analog Integrated Circuit Device Data Freescale Semiconductor 29 33663 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES In Sleep mode, the transmission path is disabled and the LIN Module 1 is in Low Power mode. Supply current from VSUP is very low. Wake-up can occur from LIN1 bus activity, from the EN1 pin and from the WAKE1 input pin. If during the preparation to Sleep mode delay (tSD), the LIN1 bus goes low due to LIN1 network communication, the LIN Module 1 still enters Sleep mode. The LIN Module 1 can be awakened by a recessive to dominant start, followed by a dominant to recessive state after t > tWUF. After a wake-up event, the LIN Module 1 enters into Awake mode. In Sleep mode, the LIN Module 1 internal 725 kOhm pull- up resistor is connected and the 30 kOhm is disconnected. DEVICE POWER-UP (Awake Transitional Mode) At power-up (VSUP rises from zero), when VSUP is above the Power-On Reset voltage, both LIN Modules automatically switch after a 160 µs delay time to the Awake transitional mode. Both INH pins (INH1 and INH2) go to a HIGH state and RXD1and RXD2 to a LOW state. See Figure 21. DEVICE WAKE-UP EVENTS The 33663L, 33663J and 33663S can be awakened from Sleep mode by three wake-up events:
- Remote wake-up via LIN1 and/or LIN2 bus activity
- Via the EN1 and/or EN2 pin
- Toggling the WAKE1 and/or WAKE2 pin Remote Wake from LIN1, LIN2 Bus (Awake Transitional Mode) Each LIN Transceiver is awakened by its LIN dominant pulse longer than tWUF. Dominant pulse means: a recessive to dominant transition, wait for t > tWUF, then a dominant to recessive transition. This is illustrated in Figure 15. Once the wake-up is detected (during the dominant to recessive transition), the LIN Module waken up by its LIN enters into Awake mode, with its INH HIGH and RXD pulled LOW. Once in the Awake mode, its EN pin has to be set to 3.3 V or 5.0 V (depending on the system) to enter into Normal mode. Once in Normal mode, the LIN Module has to wait tFIRST_DOM delay before transmitting the first dominant bit. Wake-up from EN1, EN2 pins Each LIN Module can be awakened by a LOW to HIGH transition of its EN pin. When EN is switched from LOW to HIGH and stays HIGH for a delay higher than tLWUE, the LIN Module is awakened and enters into Normal mode. See Figure 14. Once in Normal mode, the LIN Module has to wait tFIRST_DOM delay before transmitting the first dominant bit. Wake-up from WAKE1, WAKE2 Pins (Awake Transitional Mode) Just before entering the Sleep mode, the WAKE pin state of the concerned LIN Module is stored. A change in the level longer than the deglitcher time (70 µs maximum) will generate a wake-up, and the LIN Module enters into the Awake Transitional mode, with its INH HIGH and RXD pulled LOW. See Figure 16. The LIN Module goes into Normal mode when its EN is switched from LOW to HIGH and stays HIGH for a delay higher than tLWUE. Once in Normal mode, the LIN Module has to wait tFIRST_DOM delay before transmitting the first dominant bit.
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Tables 7 describes the 33663 protections. Table 7. Fail Safe Features
Figure 25. Operational and Transitional Modes State Table 7. Explanation of Operational and Transitional Modes State Diagram (each transceiver)
- Low LIN bus dominant
- High LIN bus recessive X = Don’t care. Power-Up Awake Sleep Preparation to Sleep LIN1 Normal Baud Rate or Slow Baud Rate Fast Baud Rate (10x) EN1 HIGH TO LOW for t >tLWUE EN1 LOW TO HIGH for t> tLWUE EN1 LOW TO HIGH for t>tLWUE Toggle Function (4) Toggle Function (4 ) EN1 HIGH TO LOW for t >tLWUE EN1 LOW TO HIGH for t >tLWUE LIN MODULE 1 Sleep Preparation to Sleep LIN2 Normal Baud Rate or Slow Baud Rate Fast Baud Rate (10x) EN2 LOW TO HIGH for t > tLWUE EN2 HIGH TO LOW for t >tLWUE Toggle Function (4) Toggle Function (4) EN2 HIGH TO LOW for t >tLWUE EN2 LOW TO HIGH for t >tLWUE EN2 LOW TO HIGH for t >tLWUE LIN MODULE 2 Awake LIN1 bus dominant pulse for t>tWUF (2) Or WAKE1 pin state changes for t>tWF (3) Internal WAKE1 (1) State changes during tSD LIN2 bus dominant pulse for t>tWUF (2) Or WAKE2 pin state changes for t>tWF (3) Internal WAKE2 (1) State changes during tSD VSUP > VPOR Internal WAKE1 (1) state doesn’t change during tSD Internal WAKE2 (1) State doesn’t change during tSD (1):internal WAKE is the WAKE signal filtered by tWF (WAKE deglitcher) (2):see figures 15 and 18 (3):see figures 14 and 17 (4):the Toogle Function is guaranteed at ambiant and hot temperature
Analog Integrated Circuit Device Data
32 Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES COMPATIBILITY WITH LIN1.3 Following the Consortium LIN specification Package, Revision 2.1, November 24, 2006, Chapter 1.1.7.1 Compatibility with LIN1.3 page 15: The LIN 2.1 physical layer and is backward compatible with the LIN 1.3 physical layer, but not the other way around. The LIN
Figure 26. 33663 Typical Application
Analog Integrated Circuit Device Data
34 Freescale Semiconductor
Important For the most current revision of the package, visit www.Freescale.com and do a keyword search on the 98A. Dimensions shown are provided for reference ONLY. EF SUFFIX 14-PIN 98ASB42565B REVISION J
Analog Integrated Circuit Device Data Freescale Semiconductor 35 33663 PACKAGING PACKAGE DIMENSIONS EF SUFFIX 14-PIN 98ASB42565B REVISION J
Analog Integrated Circuit Device Data
36 Freescale Semiconductor
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 1.0 7/2012 • Initial Release.
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