MC33662 NXP | Alldatasheet
Document overview
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Technical content
Features
- Operational from a V SUP of 7.0 to 18 V DC, functional up to 27 V DC, and handles 40 V during Load Dump Compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A, SAE J2602 and ISO 17987-4:2016 (12 V) Active bus wave shaping, offering excellent radiated emission performance
- Sustains up to 15.0 kV minimum ESD IEC61000-4-2 on the LIN Bus, 20 kV on the WAKE pin, and 25 kV on the VSUP pin
- Very high immunity against electromagnetic interference
- Low standby current in Sleep mode
- Overtemperature pr otection
- Local and remote Wake-up capability reported by the RXD pin
- Fast baud rate selection reported by RXD pin
- 5.0 V and 3.3 V compatible digital inputs without any required external components
- Pin-to-pin compatible with TJA1021
Figure 1. 33662 Master LIN Bus Simplified Application Diagram
Applications
- Automotive Market:
- Body electronics (BCM, gateway, roof, door, lighting, HVAC)
- Powertrain (EMS, start & stop), BMS
- Safety & Chassis (TPMS, seat belt) 33662 WAKE EN TXD VSUP INH LIN GND MCU VDD 12 V 5.0 V or 3.3 V VBAT LIN Interface RXD Regulator CAN SBC or
Table 1. Device Variations
- In Sleep mode, the total module current consumption may be higher than ex pected if the external pull-up resistor on the RxD pin
is implemented. There may be an unexpected glitch on RxD as INH goes low.
Figure 2. 33662 Simplified Internal Block Diagram
Figure 3. 33662 8-SOICN Pin Connections Table 2. 33662 8-SOICN Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 21.
1 RXD Output Data Output This pin is the receiver output of the LIN interface which reports the state
of the bus voltage to the MCU interface. 2 EN Input Enable Control This pin controls the operation mode of the interface.
3 WAKE Input Wake Input This pin is a high-voltage input used to wake-up the device from Sleep
4 TXD Input Data Input This pin is the transmitter input of the LIN interface which controls the
5 GND Ground Ground This pin is the device ground pin.
6 LIN Input/Output LIN Bus This bidirectional pin represents the single-wire bus transmitter and
7 VSUP Power Power Supply This pin is the device battery level power supply.
8 INH Output Inhibit Output This pin can have two main functions: controlling an external switchable
resistor in the master node application.
ELECTRICAL CHARACTERISTICS
Table 3. Maximum Ratings permanent damage to the device.
- Class A: All functions of a dev ice/system perform as designed dur ing and after exposure to disturbance.
- Class D: At least one function of the transceiver stops worki ng properly dur ing the test, and will return to proper operation automatically
when the exposure to the disturbance has ended. No physical damage of the IC occurs.
ELECTRICAL RATINGS (CONTINUED) ESD Capability - AECQ100 Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 ) LIN pin versus GND Wake pin versus GND All other pins Charge Device Model - JESD22/C101 (CZAP = 4.0 pF Corner pins (Pins 1, 4, 5 and 8) All other pins (Pins 2, 3, 6 and 7) Machine Model - JESD22/A115 ( CZAP = 220 pF, RZAP = 0 ) All pins According to “Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive Applica tions” specification Rev1.1 / December 2nd, 2009 (CZAP = 150 pF, RZAP = 330 ) Contact Discharge, Unpowered LIN pin without capacitor LIN pin with 220 pF capacitor VSUP (10 µF to ground) WAKE (2*18 k serial resistor) INH pin LIN pin with 220 pF capacitor and indirect ESD coupling (according to ISO10605 - Annex F) According to ISO10605 - Rev 2008 test specification (2.0 k / 150 pF) - Unpowered - Contact discharge LIN pin without capacitor LIN pin with 220 pF capacitor VSUP (10 µF to ground) WAKE (2*18 k serial resistor) (2.0 k / 330 pF) - Powered - Contact discharge LIN pin without capacitor LIN pin with 220 pF capacitor VSUP (10 µF to ground) WAKE (2*18 k serial resistor) VESD1-1 VESD1-2 VESD1-4 VESD2-1 VESD2-2 VESD3-1 VESD4-1 VESD4-2 VESD4-3 VESD4-4 VESD4-5 VESD4-6 VESD5-1 VESD5-2 VESD5-3 VESD5-4 VESD6-1 VESD6-2 VESD6-3 VESD6-4 ± 10.0 k ± 8.0 k ± 4.0 k ± 750 ± 500 ± 200 ± 15 k ± 15 k ±25 k ±20 k ±2.0 k >± 15 k ± 20 k ± 25 k ±25 k ±25 k ± 8 k ± 10 k ±12 k ±15 k V THERMAL RATINGS Operating Temperature Ambient Junction TA TJ - 40 to 125 - 40 to 150 Storage Temperature TSTG - 40 to 150 C Thermal Resistance, Junction to Ambient RJA 150 °C/W Peak Package Reflow Temperature During Solder Mounting (4) TSOLDER 240 °C Thermal Shutdown Temperature TSHUT 150 to 200 °C Thermal Shutdown Hysteresis Temperature THYST 20 °C Notes 4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Table 3. Maximum Ratings (continued) permanent damage to the device.
STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Charac teristics flect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
13.5 V < VSUP < 27 V
- For the functional operating voltage, the device is functional and all features are operating. The electrical parameters are noted under
STATIC ELECTRICAL CHARACTERISTICS LIN PHYSICAL LAYER - TRANSCEIVER LIN(6) Operating Voltage Range(7) VBAT 8.0 – 18 V Supply Voltage Range VSUP 7.0 – 18 V Voltage Range (within which the device is not destroyed) VSUP_NON_OP -0.3 – 40 V Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V IBUS_LIM 40 90 200 mA Input Leakage Current at the Receiver Driver off; VBUS = 0 V; VBAT = 12 V IBUS_PAS_DOM -1.0 – – mA Leakage Output Current to GND Driver Off; 8.0 V VBAT 18 V; 8.0 V VBUS 18 V; VBUS VBAT; VBUS VSUP IBUS_PAS_REC – – 20 µA Control Unit Disconnected from Ground(8) GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V IBUS_NO_GND -1.0 – 1.0 mA VBAT Disconnected; VSUP_DEVICE = GND; 0 V < VBUS < 18 V(9) IBUSNO_BAT – – 10 µA Receiver Dominant State(10) VBUSDOM – – 0.4 VSUP Receiver Recessive State(11) VBUSREC 0.6 – – VSUP Receiver Threshold Center (VTH_DOM + VTH_REC)/2 VBUS_CNT 0.475 0.5 0.525 VSUP Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) VHYS – – 0.175 VSUP LIN dominant level with 500 680 and 1.0 k load on the LIN bus VLINDOM_LEVEL – – 0.25 VSUP VBAT_SHIFT VSHIFT_BAT 0 – 11.5% VBAT GND_SHIFT VSHIFT_GND 0 – 11.5% VBAT LIN Wake-up Threshold from Sleep Mode VBUSWU – 4.3 5.3 V LIN Pull-up Resistor to VSUP RSLAVE 20 30 60 k LIN Internal Capacitor(12) CLIN 30 pF Overtemperature Shutdown(13) TLINSD 150 160 200 °C Overtemperature Shutdown Hysteresis TLINSD_HYS – 20 – °C Notes 6. Parameters guaranteed for 7.0 V VSUP 18 V. 7. Voltage range at the battery level, including the reverse battery diode. . Loss of local ground must not affect communication in the residual network. 9. Node has to sustain the current that can flow under this c ondition. The bu s must remain operational under this condition. 10. LIN threshold for a dominant state. 11. LIN threshold for a recessive state. 12. This parameter is guaranteed by proc ess monitoring but not production tested. 13. When an overtemperature shutdown occurs, the LIN transmitter and receiver are in recessive state and INH switched off. This parameter is tested with a test mode on ATE and characterized at laboratory. Table 5. Static Electrical Characteristics (continued) values reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Driver ON Resistance (Normal Mode) IINH = 50 mA INHON — — 50 Current load capability From 7.0 V < VSUP < 18 V IINH_LOAD — — 30 mA Leakage Current (Sleep Mode) 0 < VINH < VSUP ILEAK -5.0 — 5.0 Overtemperature Shutdown(14) TINHSD 150 160 200 °C Overtemperature Shutdown Hysteresis TINHSD_HYS — 20 — °C WAKE INPUT PIN High to Low Detection Threshold (5.5 V < VSUP < 7 V) VWUHL1 2.0 — 3.9 V Low to High Detection Threshold (5.5 V < VSUP < 7 V) VWULH1 2.4 — 4.3 V Hysteresis (5.5 V < VSUP < 7 V) VWUHYS1 0.2 — 0.8 V High to Low Detection Threshold (7 V VSUP < 27 V) VWUHL2 2.4 — 3.9 V Low to High Detection Threshold (7 V VSUP < 27 V) VWULH2 2.9 — 4.3 V Hysteresis (7 V VSUP < 27 V) VWUHYS2 0.2 — 0.8 V Wake-up Input Current (VWAKE < 27 V) IWU — — 5.0 µA Notes 14. When an overtemperature shutdown occurs, the INH high side is switched off and the LIN transmitter and receiver are in recessive state. This parameter is tested with a test mode on ATE and characterized at laboratory. STATIC ELECTRICAL CHARACTERISTICS Characteristics under conditions 7.0 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V, unless otherwise noted. Typical values reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Charac teristics reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted. ach parameter. See Figure 8.
DYNAMIC ELECTRICAL CHARACTERISTICS LIN PHYSICAL LAYER RECEIVER CHARACTERISTICS ACCORDING to LIN 2.x and ISO 17987-4:2016 (12V) (20) 33662L AND 33662J AND 33662S DEVICES Propagation Delay and Symmetry(21) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR t REC_PD t REC_SYM - 2.0 6.0 2.0 s LIN PHYSICAL LAYER RECEIVER CHARACTERISTICS WITH TIGHTEN LIMITS(22) 33662S DEVICE Propagation Delay and Symmetry(23) Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR t REC_PD_S t REC_SYM_S - 1.3 5.0 1.3 s LIN PHYSICAL LAYER RECEIVER CHARACTERISTICS - LIN SLOPE 1.0 V/ns(22) 33662S DEVICE Propagation Delay and Symmetry(24) Propagation Delay of Receiver, tREC_PD _FAST= MAX (tREC_PDR_FAST, tREC_PDF_FAST) Symmetry of Receiver Propagation Delay, tREC_PDF_FAST - tREC_PDR_FAST t REC_PD_FAST t REC_SYM_FAST - 1.3 6.0 1.3 SLEEP MODE AND WAKE-UP TIMINGS Sleep Mode Delay Time (25) after EN High to Low to INH High to Low with 100 µA load on INH t SD 50 — 91 µs WAKE-UP TIMINGS Bus Wake-up Deglitcher (Sleep Mode) (26) t WUF 40 70 100 s EN Wake-up Deglitcher (27) EN High to INH Low to High t LWUE — — 15 Wake-up Deglitcher (28) Wake state change to INH Low to High t WF 10 48 70 TXD TIMING TXD Permanent Dominant State Delay(29) t TXDDOM 3.75 5.0 6.25 ms FIRST DOMINANT BIT VALIDATION First dominate bit validation delay when device in Normal Mode(30) t FIRST_DOM — 50 80 µs Notes signal to LIN signal threshold defined at each parameter. See Figure 8. 21. See Figure 12. signal to LIN signal threshold defined at each parameter. See Figure 8. 23. See Figure 12 24. See Figure 13 25. See Figure 25 and 26 26. See Figure 16, 19, and Figure 20 27. See Figure 14, 17, Figure 21, Figure 25 and Figure 26 28. See Figure 15, 18, Figure 25 and Figure 26 29. The LIN is in recessive state and the receiver is still active. 30. See Figure 14, 17, 15, 18, 16, 19 and Figure 24 Table 6. Dynamic Electrical Characteristics (continued) values reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Figure 8. Test Circuit for Timing Measurements values reflect the approximate parameter means at TA = 25°C under nominal conditions, unless otherwise noted.
Figure 26. Examples of Sleep Mode Sequences
regulator, or to drive a LIN bus pull-up resistor. Sleep mode is typically 6.0 µA. consumption on the LIN bus pin when in the recessive state. Figure 27. LIN Interface the device is used in the master node. state during communication). to send the first dominant bit only after the tFIRST_DOM delay. will be enabled as soon as the device enters in Normal mode.
FUNCTIONAL PIN DESCRIPTION WAKE INPUT PIN (WAKE) The WAKE pin is a high voltage input used to wake-up the devi ce from the Sleep mode. WAKE is usually connected to an external switch in the application. The WAKE pin has a special design structure and allows wake-u p from both HIGH to LOW or LOW to HIGH transitions. When entering into Sleep mode, the device monitors the state of the WAKE pin and stores it as a reference state. The opposite state of this reference state will be the wake-up event used by the device to enter again into Normal mode. If the Wake pin state changes during the Sleep mode Dela y Time (tSD) or before EN goes low with a deglitcher lower than tWF, the device will not enter the Sleep mode, but will go into Awake mode (See Figure 26). An internal filter is implemented to avoid a false wake-up even t due to parasitic pulses (See Figure 15 and 18). WAKE pin input structure exhibits a high-impedance, with extremely low input current when voltage at this pin is below 27 V. Two seria l resistors should be inserted in order to limit the input current mainly during transient pulses and ESD. The total recommended resistor value is 33 k. An external 10 to 0 nF capacitor is advised for better EMC and ESD p erformances. Important The WAKE pin should not be left open. If the wake -up function is not used, WAKE should be connected to ground to avoid a false wake-up.
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES As described below and depicted in Figure 29 and Table 7, the 33662L, 33662J, and 33662S have two operational modes, Normal and Sleep. In addition, there are two transitional modes: Awake mode and Preparation to Sleep mode. The Awake mode allows the device to go into Normal mode. The Preparation to Sleep mode allows the devic e to go into Sleep mode. NORMAL OR SLOW BAUD RATE In the Normal mode, the LIN bus can transmit and receive information. Th e 33662L and 33662S (20 kbps) have a slew rate and timing compatible with Normal Baud Rate and LIN protocol The 33662J (10 kbps) has a slew rate and timing compatible with Low Baud Rate. From Normal mode, the three devices can enter into Fast Baud Rate (Toggle function). FAST BAUD RATE In Fast Baud Rate, the slew rate is around 10 times faster than the Normal Baud Rate. This allows very fast data transmission (> 100 kbps) -- for instance, for electronic control unit (ECU) tests and microcontroller program download. The bus pull-up resistor might be adjusted to ensure a correct RC time constant in line with the high baud r ate used. Fast Baud Rate is entered via a special sequence (called toggle function) as follows: 1- EN pin set LOW while TXD is HIGH 2- TXD stays HIGH for 12.5 µs min 3- TXD set LOW for 12.5 µs min 4- TXD pulled HIGH for 12.5 µs min 5- EN pin set LOW to HIGH while TXD still HIGH The device enters into the Fast Baud Rate if the delay betwe en Step 1 to Step 5 is 45 µs maximum. The toggle function is described in Figures 22. Once in Fast Baud Rate, the same toggle function just described prev iously is used to bring the device back into Normal Baud Rate. Fast Baud Rate selection is reported to the MCU by RXD pin. Once the devi ce enters in this Fast Baud Rate, the RXD pin goes at low level for t5. When the device returns in Normal Baud Rate with the same toggle function, the RXD pin stays high. Both sequences are illustrated in Figures 22 and 23. PREPARATION TO SLEEP MODE To enter the Preparation to Sleep mode, EN must be low for a delay higher than tLWUE. If the WAKE pin state doesn’t change during tSD and tLWUE then the 33662 goes into Sleep mode. If the WAKE pin state changes during tSD and if tWF is reached after end of tSD then the device goes into Sleep mode after the end of tSD timing. If the WAKE pin state changes during tSD and tWF delay has been reached before the end of tSD then the device goes into Awake mode. If the WAKE pin state changes before tSD and the delay tWF ends during tSD then the device goes into Awake mode. If EN goes high for a delay higher than tLWUE, the 33662 returns to Normal mode. SLEEP MODE To enter into Sleep mode, EN must be low for a delay longer than tSD and the Wake pin must stay in the same state (High or Low) during this delay. The device conditions to not enter in Sleep mode but enter in Awake mode are detailed in the Preparation into Sleep mode chapter. See Figure 26. In Sleep mode, the transmission path is disabled and the device is in Low Power mode. Supply current from VSUP is very low (6.0 µA typical value). Wake-up can occur from LIN bus activity, from the EN pin and from the WAKE input pin. If during the preparation to Sleep mode delay (tSD), the LIN bus goes low due to LIN network communication, the device still enters into the Sleep mode. The device can be awakened by a recessive to dominant start, followed by a dominant to recessive state after t > tWUF. After a Wake-up event, the device enters into Awake mode. In the Sleep mo de, the internal 725 kOhm pull-up resistor is connected and the 30 kOhm is disconnected. DEVICE POWER-UP (Awake Transitional Mode) At power-up (VSUP rises from zero), when VSUP is above the Power On Reset voltage, the device automatically switches after a 160 µs delay time to the Awake transitional mode. It switches the INH pin to a H IGH state and RXD to a LOW state. See Figure 24. DEVICE WAKE-UP EVENTS The 33662L, 33662J, and 33662S can be awakened from Sleep mode by three wake-up events:
- Remote wake-up via LIN bus activity
- Via the EN pin
- Toggling the WAKE pin Remote Wake from LIN Bus (Awake Transitional Mode) The device is awakened by a LIN dominant pulse longer than tWUF. Dominant pulse means: a recessive to dominant transition, wait for t > tWUF, then a dominant to recessive
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES transition. This is illustrated in Figure 16 and 19. Once the wake-up is detected (during the dominant to recessive transition), the device enters into Awake mode, with INH HIGH and RXD pulled LOW. Once in the Awake mode, the EN pin has to be set to 3.3 V or 5.0 V (depending on the system) to enter into Normal mode. Once in Normal mode, the device has to wait tfirst_dom delay before transmitting the first dominant bit. Wake-up from EN pin The device can be waked-up by a LOW to HIGH transition of th e EN pin. When EN is switched from LOW to HIGH and stays HIGH for a delay higher than tLWUE, the device is awakened and enters into Normal mode. See Figure 14 and 17. Once in Normal mode, the device has to wait tFIRST_DOM delay before transmitting the first dominant bit. Wake-up from WAKE Pin (Awake Transitional Mode) Just before entering the Sleep mode, the WAKE pin state is stor ed. A change in the level longer than the deglitcher time (70 µs maximum) will generate a wake-up, and the device enters i nto the Awake Transitional mode, with INH HIGH and RXD pulled LOW. See Figure 15 and 18. The device goes into Normal mode when EN is switched from LOW to HIGH and stays HIGH for a delay higher than tLWUE. Once in Normal mode, the device has to wait tFIRST_DOM delay before transmitting the first dominant bit. FAIL-SAFE FEATURES The table below describes the 33662 protections. BLOCK FAULT FUNCTIONAL MODE CONDITION RESPONSE RECOVERY CONDITION RECOVERY FUNCTIONALITY MODE Power Supply Power on Reset (POR) All modes VSUP < 3.5 V (min) then power up No internal supplies Condition gone Device goes in Awake mode whatever the previous device mode INH INH Thermal Shutdown Normal, Awake & Preparation to Sleep modes Temperature > 160 °C (typ) INH high side turned off. LIN transmitter and receiver in recessive state Condition gone Device returns in same functional mode LIN VSUP undervoltage Normal VSUP < VUVL LIN transmitter in recessive state Condition gone Device returns in same functional mode TXD Pin Permanent Dominant TXD pin low for more than 5.0 ms (typ) LIN transmitter in recessive state Condition gone Device returns in same functional mode LIN Thermal Shutdown Normal mode Temperature > 160 °C (typ) LIN tr ansmitter and receiver in recessive state INH high side turned off Condition gone Device returns in same functional mode
Figure 29. Operational and Transitional Modes State Diagram Compatibility with LIN1.3, page 15. Table 7. Explanation of Operational and Transitional Modes State Diagram
- Low LIN bus dominant
- High LIN bus recessive X = Don’t care. Notes 36. Only applies to 33662B. The 33662 will have a leakage current of typically 95 A if a pull-up resistor is implemented. Power Up Awake Sleep Preparation to Sleep Fast Baud Rate (10x) Normal Baud Rate for 33662L and 33662S or Slow Baud Rate for 33662J VSUP > VPOR LIN bus dominant pulse for t > tWUF (31) or WAKE pin state changes for t > tWF (32) EN HIGH to LOW for t > tLWUE EN LOW to HIGH for t > tLWUE EN HIGH to LOW for t > tLWUE EN LOW to HIGH for t > tLWUE EN LOW to HIGH for t > tLWUE Toggle Function(33) Toggle Function(33) Internal WAKE(30) state changes during tSD Internal WAKE(30) state doesn’t change during tSD Notes 32. Internal WAKE is the WAKE signal filtered by t WF (WAKE deglitcher) 33. See Figure 15 and Figure 18 34. See figures Figure 14 and Figure 17 35. The Toggle Function is guaranteed at ambient and hot temperature
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 3.0 8/2011 Initial release 4.0 9/2011 Changed the PC part numbers in the Ordering Information Table to MC 5.0 1/2014 • Added MC33662BLEF, MC33662BJEF, and MC33662BSEF to the ordering information.
- Updated Device Variations table
- Changed LIN dominant level with 500 680 and 1.0 k load on the LIN bus from 0.3 to 0.25
- Changed LIN Wake-up Threshold from Sleep Mode from 5.0 to 5.3
- MC33662LEF/MC33662SEF/MC33662JEF INH pin HBM level 8.0 KV removed to reflect performance 6.0 1/2014 • Corr ected MC33662 BLEF, MC33662BJEF, and MC33662BSEF to PC in the ordering information.
- Minor corre ctions to format 7.0 1/2014 • Changed MC33662BLEF, MC33662BJEF, and MC33662BSEF to MC in the ordering information. Now qualified. (12 V).
Document Number: MC33662 Rev. 8.0 Information in this document is provided solely to enable system and software implementers to use NXP products. There are no ex press or implied copyright licenses granted hereunder to design or fabric ate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: www.nxp.com. NXP and the NXP logo are trademarks of n NXP Semiconductor. All other product or service names are the property of their respective owners. © NXP B.V. 2018. How to Reach Us: Home Page: http:www.nxp.com Sales Support: salesaddresses@nxp.com