MC33660 NXP | Alldatasheet
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 13
Technical content
Features
- Operates over a wide supply voltage of 8.0 V to 18 V
- Operating temperature of -40 °C to 125 °C
- Interfaces directly to st anda rd CMOS microprocessors
- ISO K line pin protected against shorts to battery
- Thermal shutdown with hysteresis
- ISO K line pin capable of high currents
- ISO K line can be driven with up to 10 nF of parasitic capacitance
- 8 . 0 kV ESD protection attainable with few additional components
- Standby mode: no V BAT current drain with VDD at 5.0 V
- Low current drain during operation with V DD at 5.0 V
Figure 1. 33660 simplified application diagram
Applications
- Farm equipment
- Automotive systems
- Industrial equipment
- Robotic equipment
- Applications where module-to-module communications are required
- Marine and aircraft networks VDD ISO K-LINE TXD RXD VDD VDD RX TX GND ISOCEN VBB MCU 33660 Dx SCIRxD SCITxD +VBAT
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1 Orderable parts
Table 1. Orderable part variations
33 V zener diode and 470 pF
- To order parts in tape & reel, add the R2 suffix to the part number.
- Recommended for all new designs
2 Internal block diagram
Figure 2. 33660 simplified internal block diagram
10 V 125 kΩ
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3 Pin connections
3.1 Pinout diagram
Figure 3. 33660 pin connections
3.2 Pin definitions
Table 2. 33660 pin definitions 1 VBB Battery power through external resistor and diode. 3 GND Common signal and power return. 5 TX Logic level input for data to be transmitted on the bus. 6 RX Logic output of data received on the bus. 7 VDD Logic power source input. 8 CEN Chip enable. Logic “1” for active state. Logic “0” for sleep state.
- NC pins should not have any connect ions made to them . NC pins are not guaranteed to be open circuits.
4 Electrical characteristics
4.1 Maximum ratings
Table 3. Maximum ratings
- Pulse 5a - 33660B only
- Pulse 5b V V ISO ISO Pin Load Dump Peak Voltage 40 V (4) VESD1 VESD2 VESD3-1 VESD3-2 VESD4 ESD Voltage
- Human Body Model
- Machine Model 33660 33660B
- Charge Device Model Corner Pins All other Pins
- Module Level ESD (Air Discharge, Powered) 33660B only ISO pin with 33 V zener diode and 470 pF capacitor to GND - ±2000 ±150 ±200 ±750 ±500 ±25000 V (5) (6) (6) (6) (7) ECLAMP ISO Clamp Energy 10 mJ (8) TSTG Storage Temperature -55 to +150 °C TC Operating Case Temperature -40 to +125 °C TJ Operating Junction Temperature -40 to +150 °C PD Power Dissipation TA = 25 °C 100 mW TPPRT Peak Package Reflow Temperature During Reflow Note 10. °C (9), (10) RθJA Thermal Resistance: Junction-to-Ambient 150 °C/W Notes 4. Device will survive double battery jump st ar t conditions in typical applications for 10 minutes duration, but is not guaranteed to remain within specified parametric limits during this duration. 5. ESD data available upon request. 6. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance wit h the Machine Model (CZAP = 200 pF, RZAP = 0 Ω), ESD3 testing is performed in accor dance with the Charge Device Model (CZAP = 4.0 pF). 7. ESD4 testing is performed in accordance with ISO 10605 ESD model (C = 330 pF, R = 2.0 kΩ). ESD discharges start at ±5.0 kV and go up to ±25 kV in increments of 5.0 kV. There are two positions for discharges: 8.0 cm cable from ISO connector, 85 cm cable from ISO connector. There are 10 ESD discharges per voltage at each cable position at a minimum of 1.0 s intervals. Remaining charge is not bled off after every discharge. 8. Nonrepetitive clamping capability at 25 °C. 9. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 10. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www .freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 3 3xxx), and review parametrics.
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4.2 Static electrical characteristics
Table 4. Static electrical characteristics Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted.
- Tx = 0.8 VDD, CEN = 0.3 VDD – – 0.1 mA IDD(Q) VDD Quiescent Operating Current
- Tx = 0.2 VDD, CEN = 0.7 VDD – – 1.0 mA IBB(SS) VBB Sleep State Current
- VBB = 16 V, Tx = 0.8 VDD, CEN = 0.3 VDD – – 50 µA IBB(Q) VBB Quiescent Operating Current
- TX = 0.2 VDD, CEN = 0.7 VDD – – 1.0 mA VIH(CEN) VIL(CEN) Chip Enable
- Input High Voltage Threshold
- Input Low Voltage Threshold
0.7 VDD
- RISO = 510 Ω – – 0.3 x VDD V (14) VIH(TX) TX Input High Voltage Threshold
- RISO = 510 Ω 0.7 x VDD – – V (15) IPU(TX) TX Pull-up Current -40 – -2.0 µA (16) VOL(RX) RX Output Low Voltage Threshold
- RISO = 510 Ω, TX = 0.2 VDD, Rx Sinking 1.0 mA – – 0.2 VDD V VOH(RX) RX Output High Voltage Threshold
- RISO = 510 Ω, TX = 0.8 VDD, RX Sourcing 250 µA 0.8 VDD – – V TLIM Thermal Shutdown 150 170 – °C (17) ISO I/O VIL(ISO) Input Low Voltage Threshold
- RISO = 510 Ω, TX = 0.8 VDD – – 0.4 x VBB V VIH(ISO) Input High Voltage Threshold
- RISO = 510 Ω, TX = 0.8 VDD 0.7 x VBB – – V VHYS(ISO) Input Voltage Hysteresis 0.05 x VBB – 0.1 x VBB V IPU(ISO) Internal Pull-up Current
- RISO = ∞ Ω, TX = 0.8 VDD, VISO = 9.0 V, VBB = 18 V -5.0 – -140 µA ISC(ISO) Short-circuit Current Limit
- RISO = 0 Ω, TX = 0.4 VDD, VISO = VBB 50 – 200 mA Notes 11. When I BB transitions to >100 µA. 12. When I BB transitions to <100 µA. 13. Enable pin has an internal current pull-down. Pu ll-do wn current is measured with CEN pin at 0.3 VDD. 14. Measured by ramping T X down from 0.8 VDD and noting TX value at which ISO falls below 0.2 VBB. 15. Measured by ramping T X up from 0.2 VDD and noting the value at which ISO rises above 0.9 VBB. 16. T x pin has internal current pull-up. Pull-up current is measured with TX pin at 0.7 VDD. 17. Thermal Shutdown performance (T LIM) is guaranteed by design, but not production tested.
4.3 Dynamic electrical characteristics
4.4 Electrical performance curves
Figure 4. ISO input threshold/VBB vs. temperature
- RISO = 510 Ω, TX = 0.2 VDD – – 0.1 x VBB V VOH(ISO) Output High Voltage
- RISO = ∞ Ω, TX = 0.8 VDD 0.95 x VBB – – V
Table 5. Dynamic electrical characteristics Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted.
- RISO = 510 Ω to VBB, CISO = 10 nF to Ground – – 2.0 µs (18) tPD(ISO) ISO Propagation Delay
- High to Low: RISO = 510 Ω, CISO = 500 pF
- Low to High: RISO = 510 Ω, CISO = 500 pF 2.0 2.0 µs (19) (20) (21) Notes 18. Time required ISO voltage to transition from 0.8 VBB to 0.2 VBB. 19. Changes in the value of C ISO affect the rise and fall time but have minimal effect on Propagation Delay.
Table 4. Static electrical characteristics (continued) Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted.
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Figure 5. ISO output/VBB vs. temperature Figure 6. ISO fall time vs. temperature Figure 7. ISO propagation delay vs. temperature
5 Typical applications
5.1 Introduction
miconductor’s SMARTMOS process and is packaged in an 8-pin plastic SOIC.
5.2 Functional description
voltage range of 8.0 V to 18 V. passive pull-up to VDD, while the CEN input has an internal passive pull-down to ground. an external 510 Ω pull-up resistor and a diode to battery. use of the capacitor connected to the VBB device pin, and the capacitor used in conjunction with the 27 V zener connected to the ISO pin. Figure 8. Typical application diagram ESD Protection (3) in a metal module case.
45 V(2)
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6 Packaging
6.1 Package mechanical dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.NXP.com and perform a keyword search for the drawing’s document number. Package Suffix Package outline drawing number 8-Pin SOICN EF 98ASB42564B
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7 Revision history
Revision Date Description of changes 1.0 1/2011 • Initial release 2.0 9/2011 • Adjusted format to meet current compliance standards. No data was altered. 3.0 10/2011 • Updated the PC part number to MC. 4.0 2/2013
- Added PC33660BEF to the ordering information
- Redefined VBB Load Dump Peak Voltage (in accordance with ISO 7637-2 & ISO 7637-3) for the 33660B
- Added Module Level ESD (Air Discharge, Powered) for the 33660B
- Added note (7)
- Increased ESD structure voltage for 33660B, and added bleed-off circuit on VBB pin in Figure 2 5.0 10/2013 • Clarified machine model limits for MC33660 and MC33660B, page 5 6.0 1/2016 • Changed document classification to Technical Data
- Updated format and style 7/2016 • Updated to NXP document form and style
Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP , the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © 2016 NXP B.V. Document Number: MC33660 Rev 6.0