33480 FREESCALE | Alldatasheet
Document overview
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Technical content
Features
Triple 10 mΩ and Dual 35 mΩ High-Side Switches 16-bit SPI Communication Interface with Daisy Chain Capability Current Sense Output with SPI-Programmable Multiplex Switch Digital Diagnosis Feature PWM Module with Multiphase Feature Fully Protected Switches Overcurrent Shutdown detection Power Net and Reverse Polarity Protection Low-Power Mode Fail Mode Functions including Autorestart feature External smart power switch co ntrol including current recopy Figure 1. 33480 Simplified Application DiagraM
ORDERING INFORMATION
Range (TA) Package PC33480PNA/R2 -40°C to 125°C 24 PQFN Bottom View 33480 GND CSNS FETOUT FETIN OUT5 OUT4 OUT3 OUT2 OUT1 CP MCU LIMP CS SO SI SCLK IGN VBATVCC 12 V5.0 V12 V FLASHER RSTB CLOCK Watchdog Smart Switch
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Figure 2. 33480 Simplified Internal Block Diagram
3.0 MHz
Figure 3. 33480 Terminal Connections (Transparent Top View Of Package) Table 1. 33480 Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on Page 17. 1 FETIN Input External FET Input This terminal is the current sense recopy of the external SMART MOSFET.
2 IGN Input Ignition Input
mode activation. This terminal has a passive internal pulldown.
4 FLASHER Input Flasher Input
This input wakes the device. The Fail mode can be activated by this digital input. This terminal has a passive internal pulldown.
5 CLOCK Input Clock Input The PWM frequency and timing are generated from this digital clock input by
the PWM module. This terminal has an active internal pulldown current source.
6 LIMP Input Limp Home Input
internal pulldown current source. 7 NC NC No Connect No internal connection to this terminal.
8 CS Input Chip Select
internal pulldown current source.
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- The pins 14, 17 and 23 must be shorted on the board.
10 SI Input Master-Out Slave-
an active internal pulldown current source. 11 VCC Power Logic Supply SPI Logic power supply.
12 SO Output Master-In Slave-
negative edge of SCLK and when CS is high, this terminal is high impedance. 14,17,23 GND Ground Ground This terminal is the ground for the logic and analog circuitry of the device(1). 15 VBAT Power Battery Input Power supply terminal. Protected 35 mΩ high-side power output to the load. Protected 10 mΩ high-side power output to the load.
24 CSNS Output Current Sense
Table 1. 33480 Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on Page 17.
Table 2. Maximum Ratings permanent damage to the device.
2.0 Hours @ 25°C
1.0 Min @ 25°C
2.0 Min @ 25°C
- ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device
- Terminal soldering temperature limit is for 10 seconds maximu m duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device. If the qualification fails, TSOLDER will be changed for 240°C.
- Typical value guaranteed per design.
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Table 3. Static Electrical Characteristics
3.0 MHz SPI Communication
0.8 TBD Vcc
- In extended mode, the functionality is guar anteed but not the electrical parameters.
- Valid for RSTB, SI, SCLK, CLOCK, FLASHER and LIMP terminals.
- Valid for FLASHER, IGN and RSTB terminals.
0.75 FSR
0.50 FSR
0.25 FSR
0.10 FSR
- T A = 25°C. δICS / ICS= (measured ICS - targeted ICS)/ targeted ICS with targeted ICS=5mA
- Based on statistical data. Not production tested. ∆ ICS /∆T= [(measured ICS at T1 - measured ICS at T2) / measured ICS at room] / (T1 - T2)
- Parameter guaranteed by design; however, it is not production tested.
- Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT.
Table 3. Static Electrical Characteristics (continued)
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- OLLED1, bit D0 in SI data is set to [0].
- OLLED1, bit D0 in SI data is set to [1].
- For typical value of I CS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed.
- Parameter guaranteed by design; however, it is not production tested.
- Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT..
- OLLED2, bit D1 in SI data is set to [0].
- OLLED2, bit D1 in SI data is set to [1].
- For typical value of I CS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed
- Parameter guaranteed by design; however, it is not production tested.
- Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT.
- OLLED3, bit D2 in SI data is set to [0].
- OLLED3, bit D2 in SI data is set to [1].
- For typical value of I CS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed.
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- Parameter guaranteed by design; however, it is not production tested.
- Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT.
- OLLED4, bit D3 in SI data is set to [0].
- OLLED4, bit D3 in SI data is set to [1].
- For typical value of I CS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed.
- Parameter guaranteed by design; however, it is not production tested.
- Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT.
- OLLED5, bit D4 in SI data is set to [0].
- OLLED5, bit D4 in SI data is set to [1].
- For typical value of I CS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is no more guaranteed.
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Table 4. Dynamic Electrical Characteristics
- The PWM ratio is measured at Vout = 50% of V BAT in nominal range of PWM frequency (from 60Hz to 200Hz). It is possible to put the
- Linear range is defined by output duty c ycle to SPI duty cycle configuration +/-1 LSB. For values outside linear duty cycle range, a
calibration curve is available.
- IOLLEDn bit (where n corresponds to respective outputs 1 through 5) in SI data is set to logic [1]. Refer to Table 8, Serial Input Address
and Configuration Bit Map, page 28.
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- Maximum setup time required for the 33480 is the mi nimum guaranteed time needed from the microcontroller.
- Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
- Time required for output status data to be available for use at SO. 1.0 kΩ on pullup on CS.
- Time required for output status data to be terminated at SO. 1.0 kΩ on pullup on CS.
- Time required to obtain valid data out from SO following the rise of SCLK.
Figure 4. Input Timing Switching Characteristics Figure 5. SCLK Waveform and Valid SO Data Delay Time
0.7 VDD
0.2 VDD
0.2 Vcc
0.7 Vcc
Analog Integrated Circuit Device Data
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The 33480 is designed for low-voltage automotive and industrial lighting applications. Its five low RDS(ON) MOSFETs (three 10 mΩ and two 35 mΩ) can control the high sides of five separate resistive loads (bulbs). Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. FUNCTIONAL TERMINAL DESCRIPTION SUPPLY VOLTAGE (VBAT) The VBAT terminal of the 33480 is the power supply of the device. In addition to its supply function, this tab contributes to the thermal behavior of the device by conducting the heat from the switching MOSFETs to the printed circuit board. SUPPLY VOLTAGE (VCC) This is an external voltage input terminal used to supply the SPI digital portion of the circuit and the gate driver of the external SMART MOSFET. GROUND (GND) This terminal is the ground of the device. CLOCK INPUT (CLOCK) The PWM frequency and timing are generated from clock input by the PWM module. The clock input frequency is the factor 27 = 128 of the PWM frequency (60 Hz to 240 Hz). The OUT1:6 can be controlled in the range of 4% to 96% with a resolution of 7 bits of duty cycle (bits D[6:0]). The following table describes the PWM resolution. The timing includes four programmable PWM switching phases (0°, 90°, 180°, and 270°) to improve overall EMC behavior of the light module. The amplitude of the input current is divided by four while the frequency is 4 times the original one. The two following pictures illustrate this behavior. The synchronization of the switching phases between different corner light IC is provided by an SPI command in combination with the CS input. The bit in the SPI is called PWM sync (initialization register). In Normal Mode, no PWM feature (100% duty cycle) is provided in the following instances: with the following SPI co nfiguration: D7:D0=FF. In case of clock input signal failure (out of f PWM), the outputs state depends of D7 bit value (D7=1=ON) in Normal Mode. In Fail mode. The ouputs state depends of IGN and Flasher terminals. LIMP HOME INPUT (LIMP) The Fail mode of the component can be activated by this digital input port. The signal is high active, meaning the Fail mode can be activated by a logic high signal at the input. On/Off (Bit D7) Duty cycle (7 bits resolution) Output state 0X O F F 1 0000000 PWM (1/128 duty cycle) 1 0000001 PWM (2/128 duty cycle) 1 0000010 PWM (3/128 duty cycle) 1 1111111 fully ON
Analog Integrated Circuit Device Data
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FUNCTIONAL TERMINAL DESCRIPTION SERIAL INPUT (SI) The SI terminal is a serial interface command data input terminal. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI terminal, starting with D15 to D0. SI has an internal pulldown, Idown. SERIAL OUTPUT (SO) The SO data terminal is a tri-stateable output from the shift register. The SO terminal remains in a high-impedance state until the CS terminal is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO terminal changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. CHIP SELECT (CS) The CS terminal enables communication with the master device. When this terminal is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the master device. The 33480 device latches in data from the Input Shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the Shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an internal pullup, IUP.
wake and fail signals (see Fig13). controlled by the programmable PWM module. double window and overtemperature shutdown circuit. feature) can be routed by SPI. The SPI reports NM=1 in this mode. overcurrent behavior in Normal Mode. overtemperature and undervoltage (on Vbat or on Vcc). current sense are available. Output 2 is configured in Xenon mode. Table 5. Limp Home Output State
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supervising intelligence of the microcontroller is available. or OCLO) or undervoltage condition on VBat (see Fig10). after the output is protected by OCLO. Figure 7. Overcurrent window in case of Autorestart The Autorestart is not limited in time. by the transition into Normal mode.
Figure 8. Operating Modes State Machine undervoltage thresholds (Sleep mode). generate wake up event (wake=1) from 0 to 1 on RSTB. The device switches to normal mode. apply PWM clock after maximum 200us (min 50us). The following figure describes the wake-up block diagram.
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Figure 9. Wake-up block diagram
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management in Normal Mode and Fail Mode . Figure 11. Faults management in Normal Mode (for OUT[1:5] only)
Figure 12. Faults management in Fail Mode (for OUT[1:5] only) (OUT1:OUT5 ) when the output terminal is in the ON state. detected, the output stays ON. on Reset on Vbat, the fault will be reset. SPI programmable (MUX[2,0] bits). Note: * See Autorestart strategy chapter.
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output switch without overshoot (aperiodic settling). The current recopy is not active in Fail Mode. of Power on Reset, the fault will be reset. CLOCK terminals via SPI in real time and in Normal Mode. overload and no protections are available. the 33480 in case of reverse polarity. The bit D7 must be rewritten to logic [1] in Normal Mode. returns in the configuration it was just before the failure. by the Autorestart feature periodically. by signal plausibility check according to Table 6. Table 6. Logic I / O Plausibility Check
33480 is switched into Fail mode (see Fig13). Figure 13. Watchdog window
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interpreted using the bit assignment described in Table 7. equal 0 or fail mode (Fail=1). section. Table 8 summarizes the SI registers. D[15:11]=01111 with RSTB voltage higher than 8V typ. Table 7. SI Message Bit Assignment MSB D15 : D11 Register address bits. protection features, and SO status content. Table 8. Serial Input Address and Configuration Bit Map
Table 9. Initialization Register bulbs is activated for output 1. duty cycle resolution is given by bits D6 : D0. D7 = 1, D6 : D0 = 7F output continuous ON (no PWM). Table 10. Switching Phases
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SPI during normal operation. (SOA1 and SOA0 defined in the last SPI initialization word). logic [0]. This feature is useful for daisy chaining devices. to accept new fault status information. though the invalid SPI communication never occurred. data loaded into the status register. Table 11. Serial Output Bit Map Description
reflect the temperature status (Table 13). status of the 33480 (Table 14). received, so bits OD9 : OD0 are null. Table 12. Output Status Flag at Outputs 5 through 1, respectively. to overtemperature or OCHI or OCLO faults. A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0]. Table 13. Overload Status A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0]. Table 14. Device Status
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substitution mode, and Fail mode. Figure 14. Typical Application
Analog Integrated Circuit Device Data Freescale Semiconductor 33 33480 TYPICAL APPLICATION PROTECTION AND DIAGNOSIS FEATURES EMC & EMI PERFORMANCES The 33480 must pass successfully the Class5 of the norm CISPR25. The evaluation will be done on the Freescale board rev1.1. Conditions to be defined. RELIABILITY TESTS See document SCLS_reliability test spec_V22.doc, RevisionV2.2, Date September,23rd,2005.
Analog Integrated Circuit Device Data
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Analog Integrated Circuit Device Data Freescale Semiconductor 35 33480 PACKAGING PACKAGING DIMENSIONS
Analog Integrated Circuit Device Data
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Analog Integrated Circuit Device Data Freescale Semiconductor 37 33480 PACKAGING PACKAGING DIMENSIONS
Analog Integrated Circuit Device Data
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REVISION HISTORY
Revision Date Description of Changes 2.0 12/2005 Implemented Revision History page Converted to Freescale format
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