33394

33394 FREESCALE | Alldatasheet

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/C0051/C0051/C0051/C0057/C0052 SEMICONDUCTOR TECHNICAL DATA MULTI–OUTPUT POWER SUPPLY PIN CONNECTIONS Order this document from Analog Marketing Rev. 2.5, 11/2002 44–Lead HSOP DH SUFFIX CASE 1291 44–Lead QFN FC SUFFIX CASE 1310 (BOTTOM VIEW) GND CANTXD CANL CANRXD CANH /PORESET HRT /HRESET /SLEEP /PRERESET N/C N/C CS VDDL_FB DI VDDL_B SCLK VDDL_X DO VDD3_3FB N/C VDD3_3 VREF3 VPP VREF2 VPP_EN VDDH VREF1 VPRE_S WAKEUP VPRE REGON VCOMP VSEN INV VKAM_FB GND VKAM SW2G VIGN BOOT N/C N/C KA_VBAT 54–Lead SOICW–EP DWB SUFFIX CASE 1377 SW1 SW1 SW1 SW1 SW1 VBAT VBAT VBAT VBAT VBAT SOICW 1MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA /C0083/C0119/C0105/C0116/C0099/C0104 /C0077/C0111/C0100/C0101 /C0080/C0111/C0119/C0101/C0114 /C0083/C0117/C0112/C0112/C0108/C0121/C0119/C0105/C0116/C0104 /C0077/C0117/C0108/C0116/C0105/C0112/C0108/C0101 /C0076/C0105/C0110/C0101/C0097/C0114 /C0082/C0101/C0103/C0117/C0108/C0097/C0116/C0111/C0114/C0115 /C0097/C0110/C0100 /C0072/C0105/C0103/C0104 /C0083/C0112/C0101/C0101/C0100 /C0067/C0065/C0078 /C0084/C0114/C0097/C0110/C0115/C0099/C0101/C0105/C0118/C0101/C0114 The 33394 is a multi–output power supply integrated circuit with high speed CAN transceiver. The IC incorporates a switching pre–regulator operating over a wide input voltage range from +4.0V to +26.5V (with transients up to 45V). The switching regulator has an internal 3.0A current limit and runs in both buck mode or boost mode to always supply a pre–regulated output followed by Low Drop Out (LDO) regulators: VDDH / 5.0V @ 400mA; VDD3_3 / 3.3V @ 120mA; VDDL / 2.6V (User scalable between 3.3V – 1.25V) @ 400mA typically, using an external NPN pass transistor. The Keep Alive regulator VKAM (scalable) @ 50mA; FLASH memory programming voltage VPP / 5.0V or 3.3V @ 150mA; three sensor supply outputs VREF(1,2,3) / 5.0V (tracking VDDH) @ 100mA each; and a switched battery output (VSEN) to supply 125mA clamped to 17V. Additional features include Active Reset circuitry watching VDDH, VDD3_3, VDDL and VKAM, user selectable Hardware Reset Timer (HRT), Power Sequencing circuitry guarantees the core supply voltages never exceed their limits or polarities during system power up and power down. A high speed CAN transceiver physical layer interfaces between the microcontroller CMOS outputs and differential bus lines. The CAN driver is short circuit protected and tolerant of loss of battery or ground conditions. 33394 is designed specifically to meet the needs of modules, which use the MPC565 microcontroller, though it will also support others from the MPC5XX family of Motorola microcontrollers. Features:

• Wide operating input voltage range: +4.0V to +26.5V (+45V transient).
• Provides all regulated voltages for MPC5XX MCUs and other ECU’s logic and analog functions.
• Accurate power up/down sequencing.
• Provides necessary MCU support monitoring and fail–safe support.
• Provides three 5.0 V buffer supplies for internal & external (short–circuit protected) sensors.
• Includes step–down/step–up switching regulator to provide supply voltages during different battery conditions.
• Interfaces Directly to Standard 5.0V I/O for CMOS Microprocessors by means of Serial Peripheral Interface. PIN CONNECTIONS VBAT VBAT KA_VBAT VIGN VKAM SW1 SW1 SW1 BOOT SW2G GND /SLEEP HRT CANH CANL GND VKAM_FB VSEN REGON WAKEUP VREF1 VPP_EN VPP VDD3_3 VDD3_3FB VDDL_X VDDL_B CANTXD CANRXD /PORESET /HRESET /PRERESET VDDL_FB CS DI SCLK DO VREF3 VREF2 VDDH VPRE_S VPRE VCOMP INV VBAT SW1 VBAT SW1 KA_VBAT SW1 VIGN BOOT VKAM SW2G VKAM_FB GND VSEN INV REGON VCOMP WAKEUP VPRE VREF1 VPRE_S VPP_EN VDDH VPP VREF2 VDD3_3 VREF3 VDD3_3FB DO VDDL_X SCLK VDDL_B DI VDDL_FB CS /PRERESET /SLEEP /HRESET HRT /PORESET CANH CANRXD CANL CANTXD GND HSOPQFN TOP VIEW  Motorola, Inc. 2002 This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 1. 33394DH – Simplified Block Diagram and Typical Application

16 Bit

Notes: 1. In this configuration the device can operate with a minimum input voltage VBAT of 4.0 V (voltage at 33394 VBAT pins). Notes: 2.VDDL and VKAM are adjustable to support current microprocessor technology (1.25 V to 3.3 V) by means of an external resistor divider. Notes: 3. When the 33394 CAN transceiver is not used, CANL and CANH pins can be shorted together. Notes: 4. Dp1 = reverse battery protection diode. Dp2 = load dump protection diode. Dp1, Dp2 can be ommitted in those applications which do not require such protection. Freescale Semiconductor, Inc.

3MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PIN FUNCTION DESCRIPTION (44–HSOP Package) PIN NO. NAME DESCRIPTION

1 VBAT Battery supply to IC (external reverse battery protection needed in some applications)

2 VBAT Battery supply to IC (external reverse battery protection needed in some applications)

3 KA_VBAT Keep alive supply (with internal protection diode)

4 VIGN Turn–On control through ignition switch (with internal protection diode)

5 VKAM VDDL tracking Keep Alive Memory (Standby) supply

6 VKAM_FB VKAM output feedback

7 VSEN Switched battery output

8 REGON Regulator “Hold On” input

9 WAKEUP CAN wake up event output

10 VREF1 VDDH tracking linear regulator 1

11 VPP_EN VPP enable

12 VPP 5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3 13 VDD3_3 3.3 V regulated supply output, base drive for optional external pass transistor

14 VDD3_3FB VDD3_3 output feedback

15 VDDL_X VDDL optional external pass transistor base drive, operating in Boost Mode only

16 VDDL_B VDDL external pass transistor base drive

17 VDDL_FB VDDL output feedback

18 /PRERESET Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset) 19 /HRESET Open drain / HRESET (Hardware Reset) output 20 /PORESET Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor.

21 CANRXD CAN receive data (DOUT)

22 CANTXD CAN transmit data (DIN)

23 GND Ground

24 CANL CAN differential bus drive low line

25 CANH CAN differential bus drive high line

26 HRT Hardware Reset Timer pin (programmed with external capacitor and resistor)

27 /SLEEP Sleep Mode & Power Down control

28 CS SPI chip select

29 DI SPI serial data in

30 SCLK SPI clock input

31 DO SPI serial data out

32 VREF3 VDDH tracking linear regulator 3

33 VREF2 VDDH tracking linear regulator 2

34 VDDH 5.0 V regulated supply output

35 VPRE_S Switching pre–regulator output sense

36 VPRE Switching pre–regulator output

37 VCOMP Switching pre–regulator compensation (error amplifier output)

38 INV Switching pre–regulator error amplifier inverting input

39 GND Ground

40 SW2G External power switch (MOSFET) gate drive — Boost regulator

41 BOOT Bootstrap capacitor

42 SW1 Source of the internal power switch (n–channel MOSFET)

43 SW1 Source of the internal power switch (n–channel MOSFET)

44 SW1 Source of the internal power switch (n–channel MOSFET)

NOTE: The exposed pad of the 44 HSOP package is electrically and thermally connected with the IC ground. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

4 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

PIN FUNCTION DESCRIPTION (44–QFN Package) PIN NO. NAME DESCRIPTION

1 GND Ground

2 SW2G External power switch (MOSFET) gate drive — Boost Reg.

3 BOOT Bootstrap capacitor

4 SW1 Source of the internal power switch (n–channel MOSFET)

5 SW1 Source of the internal power switch (n–channel MOSFET)

6 SW1 Source of the internal power switch (n–channel MOSFET)

7 VBAT Battery supply to IC (external reverse battery protection needed in some applications)

8 VBAT Battery supply to IC (external reverse battery protection needed in some applications)

9 KA_VBAT Keep alive battery supply (with internal protection diode)

10 VIGN Turn on control through ignition switch (with internal protection diode)

11 VKAM VDDL tracking Keep Alive Memory (Standby) supply

12 VKAM_FB VKAM output feedback

13 VSEN Switched battery output

14 REGON Regulator “Hold On” input

15 WAKEUP CAN wake up event output

16 VREF1 VDDH tracking linear regulator 1

17 VPP_EN VPP enable

18 VPP 5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3 19 VDD3_3 3.3 V regulated supply output, base drive for optional external pass transistor

20 VDD3_3FB VDD3_3 output feedback

21 VDDL_X VDDL optional external pass transistor base drive, operating in Boost Mode only

22 VDDL_B VDDL external pass transistor base drive

23 VDDL_FB VDDL output feedback

24 /PRERESET Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset) 25 /HRESET Open drain / HRESET (Hardware Reset) output 26 /PORESET Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor.

27 CANRXD CAN receive data (DOUT)

28 CANTXD CAN transmit data (DIN)

29 GND Ground

30 CANL CAN differential bus drive low line

31 CANH CAN differential bus drive high line

32 HRT Hardware Reset Timer pin (programmed with external capacitor and resistor)

33 /SLEEP Sleep Mode & Power Down control

34 CS SPI chip select

35 DI SPI serial data in

36 SCLK SPI clock input

37 DO SPI serial data out

38 VREF3 VDDH tracking linear regulator 3

39 VREF2 VDDH tracking linear regulator 2

40 VDDH 5.0 V regulated supply output

41 VPRE_S Switching pre–regulator output sense

42 VPRE Switching pre–regulator output

43 VCOMP Switching pre–regulator compensation (error amplifier output)

44 INV Switching pre–regulator error amplifier inverting input

NOTE: The exposed pad of the 44 QFN package is electrically and thermally connected with the IC ground. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

5MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PIN FUNCTION DESCRIPTION (54 SOICW–EP Package) PIN NO. NAME DESCRIPTION

2 CANL CAN differential bus drive low line

3 CANH CAN differential bus drive high line

4 HRT Hardware Reset Timer pin (programmed with external capacitor and resistor)

5 /SLEEP Sleep Mode & Power Down control

6 N/C No Connect

7 CS SPI chip select

8 DI SPI serial data in

9 SCLK SPI clock input

10 DO SPI serial data out

11 N/C No Connect

12 VREF3 VDDH tracking linear regulator 3

13 VREF2 VDDH tracking linear regulator 2

14 VDDH 5.0 V regulated supply output

15 VPRE_S Switching pre–regulator output sense

16 VPRE Switching pre–regulator output

17 VCOMP Switching pre–regulator compensation (error amplifier output)

18 INV Switching pre–regulator error amplifier inverting input

19 GND Ground

20 SW2G External power switch (MOSFET) gate drive — Boost regulator

21 BOOT Bootstrap capacitor

23 SW1 Source of the internal power switch (n–channel MOSFET)

24 SW1 Source of the internal power switch (n–channel MOSFET)

25 SW1 Source of the internal power switch (n–channel MOSFET)

26 SW1 Source of the internal power switch (n–channel MOSFET)

27 SW1 Source of the internal power switch (n–channel MOSFET)

28 VBAT Battery supply to IC (external reverse battery protection needed in some applications)

29 VBAT Battery supply to IC (external reverse battery protection needed in some applications)

30 VBAT Battery supply to IC (external reverse battery protection needed in some applications)

31 VBAT Battery supply to IC (external reverse battery protection needed in some applications)

32 VBAT Battery supply to IC (external reverse battery protection needed in some applications)

33 KA_VBAT Keep alive supply (with internal protection diode)

34 N/C No Connect

35 VIGN Turn–On control through ignition switch (with internal protection diode)

36 VKAM VDDL tracking Keep Alive Memory (Standby) supply

37 VKAM_FB VKAM output feedback

38 VSEN Switched battery output

39 REGON Regulator “Hold On” input

40 WAKEUP CAN wake up event output

41 VREF1 VDDH tracking linear regulator 1

42 VPP_EN VPP enable

43 VPP 5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3 44 VDD3_3 3.3 V regulated supply output, base drive for optional external pass transistor

45 VDD3_3FB VDD3_3 output feedback

46 VDDL_X VDDL optional external pass transistor base drive, operating in Boost Mode only

47 VDDL_B VDDL external pass transistor base drive

48 VDDL_FB VDDL output feedback

49 N/C No Connect

50 /PRERESET Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset) 51 /HRESET Open drain / HRESET (Hardware Reset) output 52 /PORESET Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor.

53 CANRXD CAN receive data (DOUT)

54 CANTXD CAN transmit data (DIN)

NOTE: The exposed pad of the 54 SOICW–EP package is electrically and thermally connected with the IC ground. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

6 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

1. MAXIMUM RATINGS (Maximum Ratings indicate sustained limits beyond which damage to the device may occur. Voltage parameters are absolute voltages referenced to ground.) Parameter Min. Max. Unit Supply Voltage (VBAT), Load Dump –0.3 +45 V Supply Voltage (KA_VBAT, VIGN), Load Dump –18 +45 V Supply Voltages (VDDH, VPP, VDD3_3, VDDL, VKAM) –0.3 +5.8 V Supply Voltages (VREF1, VREF2, VREF3, VSEN) –2.0 +18 V CANL, CANH (0<VBAT<18 VDC no time limit) –18 +26.5 V ESD Voltage Human Body Model all pins (Note 1) Machine Model all pins (Note 2) –2.0 –200 +2.0 +200 kV V CANLesd, CANHesd (Note 1) –4.0 +4.0 kV CANLesd, CANHesd (Note 2) –200 +200 V CANLtransient, CANHtransient (Note 3) –200 +200 V /SLEEP –18 +45 V REGON, VPP_EN, /HRESET, /PORESET, /PRERESET, HRT, DO, DI, CS, SCLK –0.3 +7.0 V CANTXD, CANRXD –0.3 +7.0 V Operational Package Temperature [Ambient Temperature] –40 +125 °C Storage Temperature –65 +150 °C Power Dissipation (TA = 125/C0095C)

44 HSOP (Note 4)

44 QFN (Note 4)

54 SOICW–EP (Note 4)

8.3 5.0 5.0 W W W Lead Soldering Temperature (Note 5) 260 /C0095C Maximum Junction Temperature +150 °C R θJA, Thermal Resistance, Junction to Ambient (44 HSOP) (Note 6) 41 °C/W R θJC, Thermal Resistance, Junction to Case (44 HSOP) (Note 7) 0.2 °C/W R θJB, Thermal Resistance, Junction to Base (44 HSOP) (Note 8) 3 °C/W R θJA, Thermal Resistance, Junction to Ambient (44 QFN) (Note 6) 77 °C/W R θJC, Thermal Resistance, Junction to Case (44 QFN) (Note 7) 1.7 °C/W R θJB, Thermal Resistance, Junction to Base (44 QFN) (Note 8) 5.0 °C/W R θJA, Thermal Resistance, Junction to Ambient (54 SOICW–EP) (Note 6) 52 °C/W R θJC, Thermal Resistance, Junction to Case (54 SOICW–EP) (Note 7) 1.2 °C/W R θJB, Thermal Resistance, Junction to Base (54 SOICW–EP) (Note 8) 8.1 °C/W 1. Human body model: C = 100 pF, R = 1.5 kΩ . 2. Machine model: C = 200 pF, R = 10 Ω and L = 0.75 µH. In case of a discharge from pin CANL to pin GND: – 100 V < CANL transient < +100 V; in case of a discharge from pin CANH to Vcc: –150 V < CANH transient < +150 V. 3. The waveforms of the applied transients is in accordance with ”ISO 7637 part 1” test pulses 1, 2, 3a and 3b. 4. Maximum power dissipation at indicated junction temperature. 5. Lead soldering temperature limit is for 10 seconds maximum duration; contact Motorola Sales Office for device immersion soldering time/temperature limits. 6. Thermal resistance measured in accordance with EIA/JESD51–2. 7. Theoretical thermal resistance from the die junction to the exposed pad. 8. Thermal resistance measured in accordance with JESD51–8. 2. RECOMMENDED OPERATING CONDITIONS (All voltages are with respect to ground unless otherwise noted) Parameter Value Unit Supply Voltages (VBAT, KA_VBAT) 4.0 to 26.5 V Switching Regulator Output Current (IVPRE ) (Note 1) 0 to 1.2 A VDDH Output Current 0 to 400 mA VDD3_3 Output Current 0 to 120 mA VDDL_B Pass Transistor Base Drive Current 0 to 40 mA VPP Output Current 0 to 150 mA VREF Output Current 0 to 100 mA VSEN Output Current 0 to 125 mA VKAM Standby Output Current (normal mode of operation) 0 to 60 mA VKAM Standby Output Current (standby mode of operation) 0 to 12 mA 1. See Typical Application Diagram in Figure 1. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

7MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit DC CHARACTERISTICS: GENERAL Start Up Voltage VBAT start 6.2 V Power Dissipation, VBAT = 13.3 V (Buck Mode) 1.8 W Undervoltage Shut Down VBAT UV 3.4 3.9 V Battery Input Current, Power Down Mode, VIGN = 0 V; REGON = 0 V; IVKAM = 0 mA, VBAT = 13.3 V; Battery Voltage = 14 V IVBAT(sleep) 750 1000 µA Battery Input Current, Keep Alive Mode VIGN = 0; IVKAM = –10 mA 12 mA Power On Current, Regulator ON with no load on VDDH, VDD3_3, VDDL, VKAM, VREF, VPP, VSEN; VBAT = 13.3 V IVBAT(no load) 27 mA Battery Input Current, VPRE = –1.0 A, VBAT = 9 V IVBAT(9) 1.5 A Battery Input Current, VPRE = –1.0 A, VBAT = 13.3 V IVBAT(13.3) 1.2 A Battery Input Current, VPRE = –1.0 A, VBAT = 18 V IVBAT(18) 1.1 A MODE CONTROL VIGN Input Voltage Threshold, REGON = 0 V VBAT = 13.3 V; Battery Voltage = 14 V VIH VIL 2.8 1.7 3.15 2.0 3.4 2.3 V VIGN Hysteresis 0.7 1.0 1.5 V VIGN Pull–Down Current, REGON = 0V VBAT = 13.3 V, Battery Voltage = 14 V, VIGN = 14 V R PD 40 100 150 µA REGON Input High Voltage Threshold VIH 1.3 1.65 2.1 V REGON Input Low Voltage Threshold VIL 0.8 1.35 1.5 V REGON Input Voltage Threshold Hysteresis VIhys 0.2 0.3 0.4 V REGON Pull–Down Current, REGON = VDDH to VIL(min) R PD 10 20 50 µA /SLEEP Input High Voltage Threshold VIH 1.7 2.2 2.6 V /SLEEP Input Low Voltage Threshold VIL 1.4 1.9 2.2 V /SLEEP Input Voltage Threshold Hysteresis VIhys 0.2 0.3 0.4 V /SLEEP Pull–Down Current, /SLEEP = VDDH to VIL(min) R PD 10 20 50 µA VPP_EN Input High Voltage Threshold VIH 1.3 1.65 2.1 V VPP_EN Input Voltage Low Threshold VIL 0.8 1.35 1.5 V VPP_EN Pull–Down Current, VPP_EN = VDDH to VIL(min) R PD 10 20 50 µA Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

8 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

1. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit DC CHARACTERISTICS: BUCK CONVERTER Buck Converter Output Voltage, VBAT = 7.5V to 18V; ILOAD =500mA VPRE 5.4 5.6 5.8 V Buck to Boost Mode Threshold Voltage (Note 1) VBAT thd 6.7 V Boost to Buck Mode Threshold Voltage (Note 1) VBAT thu 7.2 V N–channel power MOSFET SW1 SW1 Drain–Source Breakdown Voltage (Note 1) BV DSS 50 V SW1 Continuous Drain Current IDSW1 –2.75 A SW1 Drain–Source Current Limit IscSW1 –2.5 –3.0 –3.5 A SW1 Drain–Source On–Resistance; ID = 1.0 A, VBAT = 9.0 V R DS(on) 300 m Ω Error Amplifier (Design Information Only) Input Offset Voltage (Note 1) VOS 20 mV DC Open Loop Gain (Note 1) AVOL 80 dB Unity Gain Bandwidth (Note 1) BW 1.5 MHz Output Voltage Swing — High Level (Note 1) VOH 4.2 V Output Voltage Swing — Low Level (Note 1) VOL 0.4 V Output Source Current (Note 1) IOUT 1.0 mA Output Sink Current (Note 1) IOUT 200 µA Ramp Generator Sawtooth Peak Voltage (Note 1) VOSC 3.5 V Sawtooth Peak–to–Peak Voltage (Note 1) VOSCp–p 3.0 V BOOST CONVERTER External Power MOSFET Gate Drive SW2G SW2G Output Voltage, Power MOSFET On (Note 1) Vg VPRE V SW2G Source Continuous Current (Note 1) Isource TBD mA SW2G Sink Continuous Current Isink 200 300 400 mA AC CHARACTERISTICS: BUCK CONVERTER Oscillator Frequency Freq 180 200 220 kHz SW1 Switch Turn–ON Time (Note 1) tT–ON TBD ns SW1 Switch Turn–OFF Time (Note 1) tT–OFF TBD ns SW2G Switch Turn–ON Time, Cgate = pF (Note 1) tT–ON TBD ns SW2G Switch Turn–OFF Time, Cgate = pF (Note 1) tT–OFF TBD ns OFF Time (Note 1) tOFF 1.25 µs Duty cycle (Note 1) d 75 % NOTE: 1. Guaranteed by design but not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

9MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit DC CHARACTERISTICS: VDDH VDDH Output Voltage, IVDDH = –400 mA; VDDH 4.9 5.0 5.1 V VDDH Load Regulation, VBAT = 13.3 V; IVDDH = 0 to –400 mA; LoadRg VDDH –40 40 mV VDDH Line Regulation, VBAT = 4.0 V to 26.5 V; IVDDH = –400 mA; LineRgVDDH –20 20 mV VDDH Drop Out Voltage, VPRE – VDDH, IVDDH = –400 mA; Decrease VBAT until Resets asserted VDOV 450 mV VDDH Output Current, VBAT = 4.0 V to 26.5 V IVDDH –400 mA VDDH Short Circuit Current, VDDH = 0 V ISC –750 –440 mA VDDH Maximum Allowed Feedback Current (Note 1) (Power Up Sequence Guaranteed) (Note 2) 135 µA VDDH Reset Voltage, Range of VDDH where Resets must remain asserted VVDDH_HRST 0.5 4.8 V Thermal Shutdown Junction Temperature (Note 1) TS DIS 150 190 °C Thermal Shutdown Hysteresis (Note 1) TS HYS 5.0 20 °C VDD3_3 VDD3_3 Output Voltage, IVDD3_3 = –120 mA; VDD3_3 3.21 3.3 3.36 V VDD3_3 Load Regulation, VBAT = 13.3 V; IVDD3_3 = 0 to –120 mA LoadRg VDD3 –40 40 mV VDD3_3 Line Regulation, VBAT = 4.0V to 26.5V; IVDD3_3 = –120mA LineRgVDD3 –20 20 mV VDD3_3 Drop Out Voltage, VPRE – VDD3_3 IVDD3_3 = –120 mA; Decrease VBAT until Resets asserted VDOV 2.04 V VDD3_3 Output Current, VBAT = 4.0 V to 26.5 V IVDD3_3 –120 mA VDD3_3 Short Circuit Current, VDD3_3 = 0 V ISC –320 –130 mA VDD3_3 Maximum Allowed Feedback Current (Note 1) (Power Up Sequence Guaranteed) (Note 2) 135 µA VDD3_3 Reset Voltage Range of VDD3_3 where Resets must remain asserted VVDD3_HRST 0.5 3.1 V Thermal Shutdown Junction Temperature (Note 1) TS DIS 150 190 °C Thermal Shutdown Hysteresis (Note 1) TS HYS 5.0 20 °C VDDL VDDL Feedback Reference Voltage, pin VDDL_FB IVDDL_B = 0 to –40 mA VDDL REF 1.242 1.267 1.292 V VDDL Load Regulation, VBAT = 13.3 V; IVDDL_B = 0 to –40 mA LoadRg VDDL –1.6 0 % VDDL Line Regulation VBAT = 4.0 V to 26.5 V; IVDDL_B = –40 mA LineRgVDDL –0.8 0.8 % VDDL Drop Out Voltage, VPRE – VDDL IVDDL = –400 mA; VBAT decreases until Resets asserted VDOV 1.3 V VDDL Reset Voltage, (Note 1) Range of VDDL where Resets must remain asserted VVDDL_HRST 0.5 VDDL –5% V VDDL Susceptibility to Feeding Back (Note 3) (Power Up Sequence Guaranteed) VDDL REF 0.187 V VDDL_B Drive Output Current, VBAT = 7.5V to 26.5V IVDDL_B –40 mA VDDL_B Drive Short Circuit Current VDDL_B = 0V, VBAT = 7.5V to 26.5V IscVDDL_B –100 –45 mA VDDL_X Drive Output Current, VBAT = 4.0 V to 6 V IVDDL_B –40 mA VDDL_X Drive Short Circuit Current, VDDL_X = 0V, VBAT = 4.0V to 6VIscVDDL_X –100 –45 mA VDDL Feedback VDDL_FB Input Current, VDDL_FB = 5.0 V IVDDL_FB 0 2.0 µA NOTE: 1. Guaranteed by design but not production tested. 2. Maximum allowed current flowing back into the regulator output. 3. Voltage fed back into the VDDL output, which still guaranties proper Power Up sequencing. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

10 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

1. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit DC CHARACTERISTICS: VKAM VKAM Feedback Reference Voltage, pin VKAM_FB Normal Mode (switcher running), IVKAM = 0 to –50mA VKAM REF 1.242 1.267 1.292 V VKAM Load Regulation, VBAT = 13.3 V; IVKAM = –0 to –50 mA LoadRg VKAM –1.6 0 % VKAM Line Regulation, VBAT = 4.0 V to 26.5 V; IVKAM = –50 mA LineRgVKAM –0.8 0.8 % VKAM Tracking to VDDL Voltage, VDDL – VKAM VBAT = 4.0 V to 26.5 V; IVKAM = 0 to –50 mA, IVDDL = 0 to –400mA VT VKAM –1.6 0.8 % VKAM Feedback Voltage — Power Down Mode 3.0 V ≤ Battery Voltage ≤ 26.5 V, IVKAM = –12 mA VKAM 0.675 V VKAM Reset Voltage (/PORESET) Range of VKAM where Resets must remain asserted VVKAM_HRST 0.5 VKAM –5% V VKAM Output Current (Normal Mode), VBAT = 4.0 V to 26.5 V IVKAM –50 mA VKAM Output Current (Sleep Mode and when VBAT ≤ 4.0 V) IVKAM(sleep) –12 mA VKAM Short Circuit Current, VKAM = 0 V ISC –140 –50 mA VKAM Feedback VKAM_FB Input Current, VKAM_FB = 5.0 V IVKAM_FB 0 2.0 µA VKAM Output Capacitance Required, Capacitor Initial Tolerance 10% 22 100 µF VPP VPP 5.0V Output Voltage (Default), IVPP = –150 mA VPP 5 4.86 5.0 5.12 V VPP 3.3 V Output Voltage (Programmed by SPI) IVPP = –150 mA VPP 3 3.22 3.3 3.38 V VPP Load Regulation, VBAT = 13.3 V; IVPP = 0 to –150 mA LoadRg VPP –0.8 0.8 % VPP Line Regulation, VBAT = 4.0 V to 26.5 V; IVPP = –150 mA LineRgVPP –0.4 0.4 % VPP Tracking to VDDH Voltage, VDDH – VPP, VBAT = 4.0 V to 26.5 V; IVPP = 0 to –150 mA; IVDDH = 0 to –400 mA VT VPP –0.8 0.8 % VPP Drop Out Voltage, VPRE — VPP (VPP set to default 5.0V) IVPP = –150 mA; Decrease VBAT until VPP is out of specification (less than 4.86 V) VDOV 0.4 V VPP Output Current, VBAT = 4.0 V to 26.5 V IVPP –150 mA VPP Short Circuit Current, VPP = 0 V ISC –360 –165 mA Thermal Shutdown Junction Temperature (Note 1) TS DIS 150 190 °C Thermal Shutdown Hysteresis (Note 1) TS HYS 5.0 20 °C NOTE: 1. Guaranteed by design but not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

11MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit DC CHARACTERISTICS: VREF1, 2, 3 VREF Output Voltage, IVREF = –100 mA VREF 4.86 5.0 5.12 V VREF Load Regulation, VBAT = 13.3 V; IVREF = 0 to –100 mA LoadRg VREF –40 40 mV VREF Line Regulation, VBAT = 4.0 V to 26.5 V; IVREF = –100 mA LineRgVREF –20 20 mV VREF Tracking to VDDH Voltage, VDDH – VREF, VBAT = 4.0 V to 26.5 V, IVREF = 0 to –100 mA; IVDDH = 0 to –400 mA VT VREF –40 20 mV VREF Drop Out Voltage, VPRE–VREF IVREF = –100 mA; Decrease VBAT until VREF is out of specification (less than 4.86 V) VDOV 0.4 V VREF Output Current, VBAT = 4.0 V to 26.5 V IVREF –100 mA VREF Short Circuit Current, VREF = –2.0 V ISC –260 –110 mA VREF Short to Battery Load Current, VBAT = 18 V, VREF = 18 V IstbVREF 40 mA VREF Leakage Current, VREF disabled, VREF = –2.0 V ILKVREF –2.0 mA Thermal Shutdown Junction Temperature (Note 1) TS DIS 150 190 °C Thermal Shutdown Hysteresis (Note 1) TS HYS 5.0 20 °C VSEN VSEN Saturation Voltage, IVSEN = 0 to –125 mA, VBAT= 8 to 16 V VSEN sat 0.2 V VSEN Output Voltage Limit, IVSEN = 0 to –125mA, VBAT= 16 to 26.5VVSEN limit 16 17 21 V VSEN Short Circuit Current, VSEN = –2.0 V IscVSEN –290 –140 mA VSEN Short to Battery Load Current, VBAT = 18 V, VSEN = 18 V IstbVSEN 40 mA VSEN Leakage Current, VSEN disabled, VSEN = –2.0 V ILKVSEN 200 µA Thermal Shutdown Junction Temperature (Note 1) TS DIS 150 190 °C Thermal Shutdown Hysteresis (Note 1) TS HYS 5.0 20 °C NOTE: 1. Guaranteed by design but not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

12 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

1. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit DC CHARACTERISTICS: SUPERVISORY OUTPUTS Reset Voltage Thresholds /HRESET to follow /PRERESET by 0.7 µs VDDH Reset Upper Threshold Voltage (Note 1) 5.2 V VDDH Reset Lower Threshold Voltage (Note 1) 4.8 V VDD3_3 Reset Upper Threshold Voltage (Note 1) 3.43 V VDD3_3 Reset Lower Threshold Voltage (Note 1) 3.17 V VDDL Reset Upper Threshold Voltage (Notes 1, 4) 1.35 V VDDL Reset Lower Threshold Voltage (Notes 1, 4) 1.2 V /PORESET Voltage Threshold VKAM Reset Upper Threshold Voltage (Notes 2, 5) 1.35 V VKAM Reset Lower Threshold Voltage (Notes 2, 5) 1.2 V /PRERESET, /HRESET, /PORESET Open Drain Maximum Voltage (Note 3) 7.0 V /PRERESET, /HRESET, /PORESET Open Drain Pull–Down Current, Vreset< 0.4 V 1.0 mA /PRERESET, /HRESET, /PORESET Low–Level Output Voltage, IOL = 1.0 mA 0.5 V /PRERESET /HRESET /PORESET Leakage Current 15 µA WAKEUP High–Level Output Voltage, IOH = –800µA VDDH–0.8 V WAKEUP Low–Level Output Voltage, IOL = 1.6 mA 0.4 V HRT Voltage Threshold 2.49 2.53 2.57 V HRT Sink Current 1.0 mA HRT Leakage Current 5.0 µA HRT Saturation Voltage, HRT Current = 1 mA 0.4 V AC CHARACTERISTICS: SUPERVISORY OUTPUTS /PORESET Delay Delay time from VKAM in regulation and stable to the release of /PORESET 7.0 10 15 ms Reset Delay Time Time from fault on VDDH, VDD3_3, VDDL or VKAM to Reset (/PORESET, /PRERESET) 10 20 50 µs /HRESET Delay Time Time From /PRERESET low to /HRESET low 0.5 0.7 1.0 µs VDDH, VDDL, VREF Power Up Sequence Max Power Up Sequence Time Dependent on Output Load Characteristics. (Note 3) 800 µs NOTE: 1. VDDH, VDD3_3, VDDL regulator outputs supervised by /PRERESET and /HRESET. 2. VKAM regulator output supervised by /PORESET. 3. Guaranteed by design but not production tested. 4. Measured at the VDDL_FB pin. 5. Measured at the VKAM_FB pin. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

13MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 3. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application circuit – see Figure 1, unless otherwise noted.) Characteristic Symbol Min. Typ. Max. Unit DC CHARACTERISTICS: CAN Transceiver (Bus Load CANH to CANL RL = 60 Ω ; Vdiff = VCANH – VCANL ) CAN Transceiver Supply Current (dominant), VCANTXD = 0V IDD(CAN) 30 50 70 mA CAN Transceiver Supply Current (recessive), VCANTXD = VDDH IDD(CAN) 2.5 5 10 mA Transmitter Data Input CANTXD High–Level Input Voltage Threshold (recessive), Vdiff<0.5V VIH 1.4 2.0 V Low–Level Input Voltage Threshold (dominant), Vdiff>1.0V VIL 0.8 1.4 V High–Level Input Current, VCANTXD = VDDH IIH –5 0 +5 µA Low–Level Input Current, VCANTXD = 0V IIL –10 –15 –30 µA CANTXD Pull–up Current, VCANTXD = 0V to VIH(max) IPU –10 –60 µA CANTXD Input Capacitance (Note 1) C I(TXD) 5 10 pF Receiver Data Output CANRXD High–Level Output Voltage VCANTXD = VDDH, ICANRXD = –0.8 mA VOH VDDH –0.8 VDDH V Low–Level Output Voltage, VCANTXD = 0, ICANRXD = 1.6 mA VOL 0.4 V High–Level Output Current, VCANRXD = 0.7VDDH IOH –800 µA Low–Level Output Current, VCANRXD = 0.4V IOL 1.6 mA BUS Lines CANH, CANL Output Voltage CANH (recessive) VCANTXD = VDDH; RL = open VCANH(r) 2.0 2.5 3.0 V Output Voltage CANL (recessive) VCANTXD = VDDH; RL = open VCANL(r) 2.0 2.5 3.0 V Output Current CANH (recessive) VCANTXD = VDDH; VCANH , VCANL = 2.5V IO(CANH)(r) 100 µA Output Current CANL (recessive) VCANTXD = VDDH; VCANH , VCANL = 2.5V IO(CANL)(r) –100 µA Output Voltage CANH (dominant), VCANTXD = 0V VCANH(d) 2.75 3.5 4.5 V Output Voltage CANL (dominant), VCANTXD = 0V VCANL(d) 0.5 1.5 2.25 V Differential Output Voltage (dominant) VCANH(d) – VCANL(d) VCANTXD = 0V VOdiff(d) 1.5 2.0 3.0 V Differential Output Voltage (recessive) VCANH(r) – VCANL(r) VCANTXD = VDDH VOdiff(r) 0 0.5 V Differential Input Common Mode Voltage Range VCM –2.0 7.0 V Differential Receiver Threshold Voltage (recessive) VCANTXD = VDDH, VCANRXD < 0.4V, – 2.0V < VCM < 7.0V VRXDdiff(th) 0.5 0.75 1.0 V Differential Receiver Input Voltage Hysteresis VIdiff(hys) 0.10 0.2 0.30 V Short Circuit Output Current CANH VCANH = – 8.0V, VCANTXD = 0V ISC(CANH) –70 –200 mA Short Circuit Output Current CANL VCANL = VBAT = 18V, VCANTXD = 0V ISC(CANL) 70 200 mA Loss of Ground — see Figure 11. Refer to Figure 10 for loading considerations. Output Leakage Current CANH, VCANH = –18V IOLKG(CANH) –2.0 2.0 mA Output Leakage Current CANHL, VCANL = –18V IOLKG(CANL) –2.0 2.0 mA Loss of Battery — see Figure 12. Refer to Figure 10 for loading considerations. Input Leakage Current CANH, VCANH = 6.0V IILKG(CANH) –800 800 µA Input Leakage Current CANHL, VCANL = 6.0V IILKG(CANL) –800 800 µA NOTE: 1. Guaranteed by design but not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

14 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

1. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application

See Figure 2, CANTXD = 250 kHz square wave; CANH & CANL Load RL = 60 Ω differential.

1. Guaranteed by design but not production tested.

Figure 2. CAN Delay Timing Waveform

2.5 VVdiff

Freescale Semiconductor, Inc.

1. ELECTRICAL CHARACTERISTICS (–40°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application

1 SCLK Period tsck 200 – ns

2 Enable Lead Time tlead 105 – ns

3 Enable Lag Time tlag 50 – ns

4 SCLK High Time* tsckhs 70 – ns

5 SCLK Low Time* tsckls 70 – ns

6 SDI Input Setup Time tsus 16 – ns

7 SDI Input Hold Time ths 20 – ns

8 SDO Access Time ta – 75 ns

9 SDO Disable Time tdis – 100 ns

10 SDO Output Valid Time tvs – 75 ns

11 SDO Output Hold Time tho 0 – ns

12 Rise Time (Design Information) (Note 1) tro – 30 ns

13 Fall Time (Design Information) (Note 1) tfo – 30 ns

14 CS Negated Time (Note 1) tcsn 500 – ns

1. Guaranteed by design but not production tested.

Figure 3. SPI Timing Diagram Freescale Semiconductor, Inc.

16 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

1. FUNCTIONAL DESCRIPTION The 33394 is an integrated buck regulator/linear supply specifically designed to supply power to the Motorola MPC55x/MPC56x microprocessors. A detailed functional description of the Buck Regulator, Linear Regulators, Power Up/Down Sequences, Thermal Shutdown Protection, Can Transceiver Reset Functions and Reverse Battery Function are given below. Block diagram of the 33394 is given in Figure 1. The 33394 is packaged in a 44 pin HSOP, 54 pin SOICW and the 44 pin QFN. 4.1. Input Power Source (VBAT, KA_VBAT & VIGN) The VBAT and KA_VBAT pins are the input power source for the 33394. The VBAT pins must be externally protected from vehicle level transients greater than +45 V and reverse battery. See typical application diagram in Figure 1. The VBAT pins directly supply the pre–regulator switching power supply. All power to the linear regulators (except VKAM in the power down mode) is supplied from VBAT through the switching regulator. VKAM power is supplied through VBAT input pins and switching regulator when the 33394 is awake. When the microprocessor is in a power down mode (no VDDH or VDDL supply), the current requirement on VKAM falls to less than 12 mA. During this period the VKAM current is supplied from the reverse battery protected KA_VBAT input. The KA_VBAT supply pin is the power source to the Keep Alive Memory regulator (VKAM) in power down mode. Power is continuously supplied regardless of the state of the ignition switch (VIGN input). The KA_VBAT input is reverse battery protected but requires external load dump protection (refer to Figure 1). The VIGN pin is used as a control input to the 33394. The regulation circuits will function and draw current from VBAT when VIGN is high (active) or REGON is high (active) or on CAN bus activity (WAKEUP active). To keep the VIGN input from floating, a 10k/C0087 pull–down resistor to GND should be used. The VIGN pin has a 3.0 V threshold and 1.0 volt of hysteresis. VIGN is designed to operate up to +26.5 volt battery while providing reverse battery and +45 volt load dump protection. The input requires ESD, and transient protection. See Figure 1 for external component required. 4.2. Switching Regulator Functional Description A block diagram of the internal switching regulator is shown in Figure 4. The switching regulator incorporates circuitry to implement a Buck or a Buck/Boost regulator with additional external components. A high voltage, low RDS(on) power MOSFET is included on chip to minimize the external components required to implement a Buck regulator. The power MOSFET is a sense FET to implement current limit. For low voltage operation, a low side driver is provided that is capable of driving external logic level MOSFETs. This allows a switching regulator utilizing Buck/Boost topology to be implemented. Two independent control schemes are utilized in the switching regulator. In Buck mode, voltage mode pulse–width modulation (PWM) control is used. The switcher output voltage divided by an internal resistor divider is sensed by an Error Amplifier and compared with the bandgap reference voltage. The PWM Comparator uses the output signal from the Error Amplifier as the threshold level. The PWM Comparator compares the sawtooth voltage from the Ramp Generator with the output signal from the Error Amplifier thus creating a PWM signal to the control logic block. The Error Amplifier inverting input and output are brought out to enable the control loop to be externally compensated. The compensation technique is described in paragraph 5.2.3. Buck Converter Feedback Compensation in the Application Information section. In order to improve line rejection, feed forward is implemented in the ramp generator. The feed forward modifies the ramp slope in proportion to the VBAT voltage in a manner to keep the loop gain constant, thus simplifying loop compensation. At startup, a soft start circuit lowers the current limit value to prevent potentially destructive in–rush current. In Boost mode, pulse–frequency modulation (PFM) control is utilized. The duty cycle is set to 75% and the switching action is stopped either by the Boost Comparator, sensing the switcher output voltage VPRE, or by the Current Limit circuit when the switching current reaches its predetermined limit value. This control method requires no external components. The selection of the control method is determined by the control logic based on the VBAT input voltage. 4.2.1. Switching Transistor (SW1) The internal switching transistor is an n–channel power MOSFET. The R DS(on) of this internal power FET is approximately 0.25 ohm at +125/C0095C. The 33394 has a nominal instantaneous current limit of 3.0 A (well below the saturation current of the MOSFET and external surface mounted inductor) in order to supply 1.2 A of current for the linear regulators that are connected to the VPRE pin (see Figure 1). The input to the drain of the internal N—channel MOSFET must be protected by an external series blocking diode, for reverse battery protection (see Figure 1). 4.2.2. Bootstrap Pin (BOOT) An external bootstrap 0.1 µF capacitor connected between SW1 and the BOOT pin is used to generate a high voltage supply for the high side driver circuit of the buck controller. The capacitor is pre charged to approximately 10V while the internal FET is off. On switching, the SW1 pin is pulled up to VBAT, causing the BOOT pin to rise to approximately VBAT+10V — the highest voltage stress on the 33394. 4.2.3. External MOSFET Gate Drive (SW2G) This is an output for driving an external FET for boost mode operation. Due to the fact that the gate drive supply voltage is VPRE the external power MOSFET should be a logic level device. It also has to have a low RDS(on) for acceptable efficiency. During buck mode, this gate output is held low. 4.2.4. Compensation (INV, VCOMP) The PWM error amplifier inverting input and output are brought out to allow the loop to be compensated. The recommended compensation network is shown in Figure 18 and its Bode plot is in Figure 19. The use of external compensation components allows optimization of the buck converter control loop for the maximum bandwidth. Refer to the paragraph 5.2.3. Buck Converter Feedback Compensation in the Application Information section for further details of the buck controller compensation. 4.2.5. Switching Regulator Output Voltage (VPRE) The output of the switching regulator is brought into the chip at the VPRE pin. This voltage is required for both the switching regulator control and as the supply voltage for all the linear regulators. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

This is the switching regulator output voltage sense input. description of the switching regulator operation. Figure 4. Switching Regulator Block Diagram output capacitor parameters. allowed backfed current into the VDDH output. Table 1 for recommended output capacitor parameters. corrupt the proper power sequencing of the IC. Freescale Semiconductor, Inc.

18 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

battery (+18 V) and short to –2.0 V. Precautions must be taken to protect the VREF pins from exposure to transients. See Table 1 for recommended output capacitor parameters. 4.5.1. VREF Over Temperature Latch Off Feature If either the VREF1, VREF2 or VREF3 outputs is shorted to ground for any duration of time, an over temperature shut down circuit disables the output source transistor once the local die temperature exceeds +150°C to +190°C. The output transistor remains off until the locally sensed temperature is 5°C to 20°C. below the trip off temperature. The output(s) will periodically turn on and off until either the die temperature decreases or until the fault condition is removed. If one of these outputs goes into over—temperature shutdown, it will not impact the operation of any of the other outputs (assuming that no other package thermal or VPRE current limit specifications are violated). Fault information is reported through the SPI communication interface (see Figure 8). 4.6. Voltage Regulator (VDD3_3) This linearly regulated +3.3 V +/–0.06 V voltage supply is capable of sourcing 120 mA of steady state current from VPRE (+5.6 V) for VBAT voltage from +4.0 V to +26.5 V (+45V transient). This regulator incorporates current limit short circuit protection and thermal protection. When no external pass transistor is used the VDD3_3 and the VDD3_3FB pins must be shorted together — see Figure 22. The current capability of the VDD3_3 output can be increased by means of an external pass transistor — see Figure 1. When the external pass transistor is used the VDD3_3 internal short circuit current limit does not provide the short circuit protection. The voltage output is stable under all load/line conditions. However, the designer must consider ripple and high frequency filtering as well as regulator response when choosing external components. See Table 1 in the Applications Information section for recommended output capacitor parameters. NOTE : Backfeeding into the VDD3_3 output can cause problems during the power up sequence. Refer to the Electrical Characteristics VDD3_3 Regulator Section for the maximum allowed backfed current into the VDD3_3 output. 4.7. Voltage Regulator (VDDL) The output voltage of the VDDL linear regulator is adjustable by means of an external resistor divider. This linearly regulated +/–2% core voltage supply uses an external pass transistor and is capable of sourcing 40 mA base drive current typically (see application circuit, Figure 1) of steady state current. The collector of the external NPN pass transistor is connected to VPRE (+5.6 V) for a VBAT voltage from +7.5 V to +26.5 V (+45V transient). The voltage output is stable under all load/line conditions. However, the designer must consider ripple and high frequency filtering as well as regulator response when choosing external components. Also, the dynamic load characteristics of the microprocessor, relative to CPU clock frequency changes must be considered. An additional external pass transistor, for VDDL regulation in the Boost mode, can be added between protected battery voltage (see Figure 1) and VDDL, with its base driven by VDDL_X. In that arrangement the 33394’s core voltage supply operates over the whole input voltage range VBAT = +4.0 V to +26.5 V (up to +45V transient). See Table 1 in the Applications Information section for recommended output capacitor parameters. NOTES: 1. The use of an EXTERNAL pass device allows the power dissipation of the 33394 to be reduced by approximately 50% and thereby allows the use of a thermally efficient package such as an HSOP 44 or QFN 44. The base drive control signal (VDDL_B) is provided by on chip circuitry. The regulated output voltage sense signal is fed back into the on chip differential amplifier through pin VDDL_FB. The collector of this external pass device should be connected to VPRE to minimize power dissipation and adequately supply 400 mA. Proper thermal mounting considerations must be accounted for in the PCB design. 2. Backfeeding into the VDDL output can cause problems during the power up sequence. Refer to the Electrical Characteristics VDDL Regulator Section for the maximum allowed backfed current into the VDDL output. 4.8. Keep–Alive/Standby Supply (VKAM) This linearly regulated Keep Alive Memory voltage supply tracks the VDDL (+1.25 V to +3.3 V) core voltage, and is capable of sourcing 50 mA of steady state current from VPRE during normal microprocessor operation and 12 mA through KA_VBAT pin during stand–by/sleep mode. The VKAM regulator output incorporates a current limit short circuit protection. The output requires a specific range of capacitor values to be stable under all load/line conditions. See Table 1 in the Applications Information section for recommended output capacitor parameters. NOTE : The source current for the VKAM supply output depends on the sleep/wake state of the 33394. 4.9. Switched Battery Output (VSEN) This is a saturated switch output, which tracks the VBAT and is capable of sourcing 125 mA of steady state current from VBAT. This regulator will track the voltage VBAT to less than 200 mV, and its output voltage is clamped at +17 V. The gate voltage of the internal N—channel MOSFET is provided by a charge pump from VBAT. There is an internal gate–to–source voltage clamp. This regulator is short circuit protected and has independent over—temperature protection. If this output is shorted and goes into thermal shutdown, the normal operation of all other voltage outputs is not impacted. This output is controlled by the SPI VSEN bit. NOTE: A short to VBAT on VREF1, VREF2, VREF3 or VSEN will not result in additional current being drawn from the battery under normal (+8 V to +18 V) voltage levels. Under jumpstart condition (VBAT = +26.5 V) and during load dump condition, the device will survive this condition, but additional current may be drawn from the battery. 4.9.1. VSEN Over Temperature Latch Off Feature If the VSEN output is shorted to ground for any duration of time, an over temperature shut down circuit disables the output source transistor once the local die temperature exceeds +150°C to +190°C. The output transistor remains off until the locally sensed temperature drops 5°C to 20°C below Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

19MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA the trip–off temperature. The output will periodically turn on and off until either the die temperature decreases or until the fault condition is removed. If the VSEN output goes into over—temperature shutdown, it does not impact the operation of any of the other outputs (assuming that no other package thermal or VPRE current limit specifications are violated). Fault information is reported through the SPI communication interface (see Figure 8). 4.10. Resets To Microprocessor /PORESET – Power On Reset, /PRERESET — Pre Reset, /HRESET– Hardware Reset. All the Reset pins are open drain ‘active low’ outputs, capable of sinking 1.0 mA current and able to withstand +7.0 V. See Figure 1 and Figure 20 for recommended pull–up resistor values and their connection. The /PORESET pin is pulled up to the VKAM voltage by a pull up resistor. It is connected to the microprocessor Power On Reset (POR) pin, and is normally high. During initial battery connect the /PORESET is held to ground by the 33394. After the VKAM supply is in regulation and an internal 10 ms timer has expired, the /PORESET is released. If VKAM goes out of regulation the device will first pull the /PORESET and /PRERESET followed by a 0.7 µs delay then /HRESET. By /HRESET low VDDH, VDD3_3 and VDDL will start a power down sequence. When the fault is removed a standard power up sequence is initiated. The VKAM linear regulator output must be out of regulation for greater than 20 µs before /PORERSET and /PRERESET (with /HRESET 0.7 µs delayed) are pulled low. If a fault occurs on VKAM in the Key–Off Mode (when the VIGN is off) and the fault is then removed the VKAM will regulate but /PORESET will not be released until Key–On (asserting VIGN pin) allows the 10 ms timer to run. The Reset signals (/PRERESET, /HRESET) are not asserted when the 33394 enters Sleep Mode by asserting the /SLEEP pin. When exiting out of Sleep Mode the 33394 asserts the Resets (/PRERESET, /HRESET) during the power up sequence. The /PRERESET and /HRESET pins are pulled up to the VKAM (see Figure 1) or to VDDL (see Figure 20). Refer to section 5. Application Information, paragraph 5.3. Selecting Pull–Up Resistors for detailed description of these two connection scenarios. The 33394 monitors the main supply voltages VDDH, VDD3_3 and VDDL. If any of these voltages falls out of regulation limits the /PRERESET will be pulled down followed by the /HRESET after 0.7 µs delay, and the power down sequence will be initiated. There are several different scenarios how to connect the /PRERESET and /HRESET pins to the microprocessor. Typically the /PRERESET pin will be connected to the IRQ0 pin of the microprocessor, and the /HRESET to the microprocessor /HRESET pin (see Figure 5). The VDDH, VDD3_3 and VDDL linear regulator outputs must be out of regulation for greater than 20 µs before /PRERESET (with /HRESET 0.7 µs delayed) are pulled low. 4.11. Hardware Reset Timer (HRT) The HRT pin is used to set the delay between VDDH, VDD3_3 and VDDL active and stable and the release of the /HRESET and /PRERESET outputs. An external resistor and capacitor is used to program the timer. To minimize quiescent current during power down modes, the RC timer current should be drawn from one of the VDD supplies (see Figure 1). The threshold on the HRT pin has zero temperature coefficient and is set at 2.5 V. 4.12. Power Up/Down Sequencing The 33394 power up sequence is specifically designed to meet the power up and power down requirements of the MPC565 microprocessor. The MPC565 processor requires that VDDH remain within 3.1 volts of VDDL during power up and can not lag VDDL by more than 0.5 volts. This condition is met by the 33394 regardless of load impedance. It is critical to note that the 33394 under normal conditions is designed to supply VKAM prior to the power up sequence on VDDH, VDD3_3 and VDDL. During power up and power down sequencing /PRERESET and /HRESET are held low. Power up and power down sequencing is implemented in six steps. During this process the reference voltage for VDDH, VDD3_3 and VDDL is ramped up in six steps. Minimum power up/down time is dependent on the internal clock and is 800 µs. Maximum power up/down time is also dependent on load impedance. During the power up/down cycle, voltage level requirements for each step of VDDH, VDD3_3 and VDDL must be met before the supply may advance to the next voltage level. Hence VDDH and VDDL will remain within the 3.1/0.5 V window. Figure 6 illustrates a typical power up and down sequence. 4.13. Regulator Enable Function (REGON) This feature allows the microcontroller to select the delayed shut down of the 33394 device. It holds off the activation of the Reset signals, to the microcontroller, after the VIGN signal has transitioned and signals the request to shutdown the VDDH, VDD3_3, VDDL, VSEN and the VREFn supplies. This allows the microcontroller to delay a variable amount of time, after sensing that the VIGN signal has transitioned and signaled the request to shutdown the regulated supplies. This time can be used to store data to EPROM memory, schedule an orderly shutdown of peripherals, etc. The microcontroller can then drive the REGON signal, to the 33394, to the low logic state, to turn off the regulators (except for the VKAM supply). 4.14. Regulator Shutdown Function (/SLEEP) This feature allows for an external control element (e.g. microprocessor) to shut down the 33394 regulators, even if the VIGN signal (or REGON) is active, by asserting the /SLEEP pin from high to low (falling edge transition). In this case the 33394 initiates the power down sequence, but the Reset signals (/PRERESET, /HRESET) are not asserted. This allows the microprocessor to continue to execute code when it is supplied only from the Keep Alive supply VKAM. When the microprocessor exits sleep state by pulling /SLEEP pin high the Resets (/PRERESET, /HRESET) are asserted during the power up sequence. The /SLEEP pin has an internal pull down, therefore when its functionality is not used this pin can be either pulled up to VKAM, VBAT, pulled down to ground or left open. The /SLEEP pin should not be pulled up to VDDH. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

20 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 5. 33394 Timing Diagram 1 Module connected to the battery, VKAM starts to regulate, /PORESET is released after VKAM is in regulation for 10 ms. 2 VIGN is applied, 33394 starts power up sequence. programmable by an external capacitor and resistor, HRT pin). 4 Any of VDDH, VDD3_3, VDDL voltages out of regulation initiate /PRERESET asserted. Power down sequence initiated. with 0.7 /C0109s delay) are asserted – see Note 1. 8 33394 initiates power down sequence. 9 Fault on VKAM removed, the 33394 initiates the start up sequence. 11 /PORESET is released with a 10 ms delay after the fault on VKAM was removed. Figure 6. 33394 Power Up/Down Sequence

• VKAM voltage level for MPC55x devices is 3.3 V and for MPC56x devices is 2.6 V.

Freescale Semiconductor, Inc.

VREFn fault reporting and CAN wake up feature activation. assignments for the 16 bit SPI data word exchange. SCLK transitions from a low to high logic state. positive transition will make LSB status available on DO pin. transferring the Least Significant Bit (LSB) first.

33394 SPI Registers:

Figure 7. SPI Input Data/ Control Register Freescale Semiconductor, Inc.

22 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 8. SPI Output Data/ Status Register recessive bit), CANH and CANL are set to +2.5 V (nominal). The corresponding digital output is also asserted. the network cabling). Refer to Figure 9. Figure 9. CAN Load Characteristics

1. A summary of the network topology is shown in Figure 9.

quiescent mode by pulling the /SLEEP pin from high to low. Freescale Semiconductor, Inc.

common mode choke may be required in some applications. CANL should be shorted together. CANL output. The sink type output is short circuit protected. CANL transmitter’s output stage is disabled. the CAN bus pins, CANH and CANL, to the microprocessor. Figure 10. CAN Transceiver Block Diagram corrupt the bus. Refer to Figure 12. Freescale Semiconductor, Inc.

24 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 11. CAN Loss of Ground Test Circuit Figure 12. CAN Loss of Battery Test Circuit Freescale Semiconductor, Inc.

25MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 5. APPLICATION INFORMATION This section provides information on external components that are required by the 33394. The IC is designed to operate in an automotive environment. Conducted immunity and radiated emissions requirements have been addressed during the design. However, the IC requires some external protection. Protection is required for all pins connected directly to battery. The module designer should use an MOV or another transient voltage suppressor in all cases, when the load dump transition exceeds + 45 volts with respect to ground. Protection should also include a reverse battery protection diode (or relay) and input filter. This is required to protect the 33394 from ESD and +/– 300V ignition transients. Typical configurations are shown in Figure 1. Outputs and inputs connected directly to connector pins require module level ESD protection. 5.1. Selecting Components for Linear Regulators The output capacitor of the linear regulator serves two different purposes. It maintains the linear regulator loop stability, and it provides an energy reservoir to supply current during very fast load transients. This is especially true when supplying highly modulated loads like microcontrollers and other high–speed digital circuits. Due to the limited bandwidth of the linear regulators, the output capacitor is selected to limit the ripple voltage caused by these abrupt changes in the load current. During the fast load current transients, the linear regulator output capacitor alone controls the initial output voltage deviation. Hence, the output capacitor’s equivalent series resistance (ESR) is the most critical parameter. The outputs, which do not experience such severe conditions (the VREF e.g.), use the output capacitor mainly for stability purpose, and therefore its capacitance value can be significantly smaller. The typical output capacitor parameters are: C = 1.0 µF; ESR = 2.0 ohms. When a ceramic 1 µF capacitor is used, the ESR can be provided by a discrete serial resistor (see Figure 20). The following example shows how to determine the output capacitance for a heavily loaded output supplying digital circuits. 5.1.1. Selecting the Output Capacitor Example: The output capacitance must be selected to provide sufficiently low ESR. The selected capacitor must have an adequate voltage, temperature and ripple current rating for the particular application. In order to calculate the proper output capacitor parameters, several assumptions will be made. 1) During the very fast load current transients, the linear regulator can not supply the required current fast enough, and therefore for a certain time the entire load current is supplied by the output capacitor. 2) The capacitor’s equivalent series inductance (ESL) is neglected. These assumptions can greatly simplify the calculations, and are reasonable for most of practical applications. Then the ESR of the output capacitor has to satisfy the following condition: ESR /C0118/C0068Vo /C0068Io Where: ΔVo is the maximum allowed linear regulator voltage drop caused by the load current transient. ΔIo is the maximum current transient, which can occur due to the abrupt step in the linear regulator load current. In this example the VDDH output with the 400 mA load step is considered with the maximum voltage drop of 100mV. This gives the output capacitor’s maximum ESR value of: ESR /C0043100 mV 400 mA /C0043250 m /C0087 This level of ESR requires a relatively large capacitance. In order to maintain the linear regulator stability and to satisfy large load current steps requirements the solid tantalum capacitor 100µF/10V with ESR = 200 mΩ . One device that meets these requirements is the TPSC107K010S020 tantalum capacitor from the AVX Corporation. /C0068VESR /C0043ESR /C0032/C0068Io /C0043200 m /C0087/C0032400 mA /C004380 mV In the next step, the voltage drop associated with the capacitance can be calculated: /C0068VC /C0043/C0068Io /C0032/C0068t C /C00430.4 A/C00325 /C0109s 100 /C0109F /C004320 mV Where: C is the output capacitance. /C0068t is the linear regulator response time. ΔIo is the maximum current transient, which can occur due to the abrupt step in the linear regulator load current. Assuming that the capacitor ESL is negligible, the total voltage drop in the voltage regulator output caused by the current fast transient can be calculated as: /C0068Vtotal/C0043/C0068VESR /C0041/C0068VC /C004380 mV /C004120 mV /C0043100 mV A ceramic capacitor with capacitance value 10nF should be placed in parallel to provide filtering for the high frequency transients caused by the switching regulator. Properly sized decoupling ceramic capacitor close to the microprocessor supply pin should be used as well. Table 1 shows the suggested output capacitors for the 33394 IC linear regulator outputs. Other factors to consider when selecting output capacitors include key off timing for memory retention. Though the VKAM is not a heavily loaded output, the VKAM output capacitor has to have a sufficiently large capacitance value to supply current to the microcontroller for a certain time after battery voltage is disconnected. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

26 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Table 1. Linear Regulator Output Capacitor Examples principles of the two converters operation. ton is the on–time of the power switch. iL(on) is the inductor current during the on–time. L is the inductance of the inductor L. stores energy in the inductor core. toff is the off–time of the power switch. iL(off) is the inductor current during the off time. Vfwrd is forward voltage drop across the rectifier. d is the duty cycle, and d = ton/T. T is switching period, T = 1/f. f is the frequency of operation. Io is the average output current. Freescale Semiconductor, Inc.

Figure 13. Basic Buck Converter Operation and its Waveforms ton is the on–time of the power switch. iL(on) is the inductor current during the on–time. L is the inductance of the inductor L.

2 LI2

forward biased rectifier at the output voltage. toff is the off–time of the power switch. d is the duty cycle, and d = ton/T. T is switching period, T = 1/f. f is the frequency of operation. VppCo is the ripple caused by output current. Freescale Semiconductor, Inc.

28 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Where Io is the average output current. Figure 14. Basic Boost Converter Operation and its Waveforms Figure 15. 33394 Switcher Topology Freescale Semiconductor, Inc.

µH, which gives 47 µH standard component value. The peak–to peak ripple current value is: ΔIL = 0.345 A. of the 33394 internal switch current limit Ilim(max) = 3.0 A. inductor from Pulse Engineering, Inc. calculated average current value. TPSV107K020R0085 tantalum capacitor from AVX Corp. able to deliver the required power. Figure 16. 33394 Switcher Topology – Boost Mode meets the required criteria. Freescale Semiconductor, Inc.

30 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

breakdown voltage parameter is not critical. harsh automotive environment with low thermal resistance. MTD20N03HDL power MOSFET from ON Semiconductor. is the 33394 internal switch upper current limit Ilim(max). transition between the buck and boost modes. schottky rectifier from Microsemi, Inc. sufficient energy reservoir for proper switcher operation. the switcher in the normal operating mode (buck mode). close to the VBAT pins as possible. Figure 17. The loop consists of a power processing block — Figure 17. The Buck Converter Control Loop Freescale Semiconductor, Inc.

32 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Table 2. Part number (Figure 18) Application diagram part number (Figure 1) Component value R1 33394 internal resistor 39.6kΩ R2 R2 100kΩ R3 R1 430Ω C1 C6 100pF C2 C7 1.0nF C3 C5 3.3nF 5.3. Selecting Pull–Up Resistors All the Resets (/PORESET, /PRERESET and /HRESET) are open drain outputs, which can sink a maximum of 1 mA drain current. This determines the pull–up resistor minimum value. VKAM should be used as the pull–up source for the /PORESET output. /PORESET is pulled low only during initial battery connect or when VKAM is below 2.5 volts (for VDDL = 2.6 V). To select the /PRERESET and /HRESET pull–up resistor connections, consider current draw during sleep modes. For example, the pull up resistor on /PRERESET and /HRESET should receive its source from VDDL, if the sleep mode or low power mode of the module is initiated primarily by the state of the VIGN pin. Refer to Figure 20 for recommended pull–up resistor values. Another way to connect the /PRERESET and /HRESET pull–up resistors is to connect them to the VKAM output together with the /PORESET pull–up resistor (see Figure 1). This is the preferable solution when the sleep or low power mode is initiated primarily by the microprocessor. In that case, when the 33394 is shut down by pulling the /SLEEP pin down, all three Resets (/PORESET, /PRERESET and /HRESET) stay high. Since they are pulled–up to the supply voltage (VKAM) they draw no current from the VKAM and the module quiescent current is minimized. 5.4. Selecting Hardware Reset Timer Components The HRT input sets the delay time from VDDH, VDD3_3 and VDDL stable to the release of /PRERESET and /HRESET. When sizing the delay time the module design engineer must consider capacitor leakage, printed board leakage and HRT pin leakage. Resistor selection should be low enough to make the leakage currents negligible. The Hardware Reset (/HRESET) delay can be calculated as follows: Delay time: tD /C0043/C0042RC /C0032ln[(VB /C0042VSAT )/C0042Vth (VB /C0042VSAT ) ] Where R is the HRT timer pull–up resistor, C is the HRT timer capacitor VB is the pull–up voltage, Vth is the HRT timer threshold voltage (Vth = 2.5V nominal value), VSAT is the saturation voltage of the internal pull–down transistor. If the HRT timer pull–up resistor is connected to VDDH (see Figure 1) and the resistor value is ≥ 47 k/C0087, therefore the VSAT can be neglected, the formula for calculating the time delay can be simplified to: tD /C00430.7/C0032RC 5.5. Selecting the VKAM Resistor Divider The VKAM linear regulator output voltage is divided by an external resistor divider and compared with the bandgap reference voltage (Vbg) in the input of the VKAM error amplifier. The resistor divider can be designed according to the following formula: VKAM /C0043VKAMref /C0032/C04661 /C0041 R upper R lower /C0467 VKAMref = 1.267 V Where VKAMref is the bandgap reference voltage. Since the VKAM feedback pin (VKAM_FB) input current is only a few nA, the resistor value can be selected sufficiently high in order to minimize the quiescent current of the module. See Figure 20 for the VKAM resistor divider recommended values. 5.6. Selecting the VDDL Resistor Divider The VDDL regulator resistor divider is designed according to the same formula as described in the paragraph above (see Figure 20). VDDL /C0043VDDLref/C0032/C04661 /C0041 R upper R lower /C0467 Where VDDLref = 1.267 V Nonetheless, the actual resistor values should be chosen several decades lower than in the previous example. This is due to the fact that the VDDL linear regulator needs to be pre–loaded by a minimum of 10 mA current in order to guarantee stable operation. See Figure 20 for the VDDL resistor divider recommended values. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 20. 33394 Application Circuit Schematic Diagram

2 VDDH

*Notes: 1. D2 is a protection diode against reverse battery fault condition. In those applications, which do not require this type of protection, diode D2 can be ommitted. Notes: 2. Capacitors C25, C27 are optional and may be used for CAN tranceiver evaluation. Table 3. 33394 Evaluation Board Performance Freescale Semiconductor, Inc.

34 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Table 4. 33394DWB Evaluation Board Bill of Material 11 1 C13 10µF/16V, Tantalum TPSB106K016R0800, AVX Corp. Freescale Semiconductor, Inc.

Figure 21. 33394 Application Circuit with Increased 3.3V Output Current Capability

1 U1R4

*Notes: 1. D2 is a protection diode against reverse battery fault condition. In those applications, which do not require this type of protection, diode D2 can be ommitted. Notes: 2. Capacitors C25, C27 are optional and may be used for CAN tranceiver evaluation. Freescale Semiconductor, Inc.

36 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Table 5. 33394FC Evaluation Board Bill of Material 12 1 C13 33µF/10V Tantalum TPSB336K010R0500, AVX Corp. Freescale Semiconductor, Inc.

Figure 22. 33394 Buck–Only Application Freescale Semiconductor, Inc.

38 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 23. 33394 Flyback Converter Provides Symmetrical Voltages Freescale Semiconductor, Inc.

39MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PACKAGE DIMENSIONS DH SUFFIX 44–LEAD HSOP PLASTIC PACKAGE CASE 1291–01 ISSUE O SEATING PLANE DATUM PLANE BOTTOM VIEW A X 45 E D h e 42X BMbbb C 2322 /C0095 ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÉÉÉ ÉÉÉ SECTION W–W b c AMaaa C EXPOSED HEATSINK AREA A B C H PIN ONE ID 22X Y GAUGE PLANE DETAIL Y (1.600) L W W /C0113bbb C 0.325 NOTES: 1. CONTROLLING DIMENSION: MILLIMETER. 2. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.150 PER SIDE. DIMENSIONS D AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. DATUMS –A– AND –B– TO BE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION D DOES NOT INCLUDE TIEBAR PROTRUSIONS. ALLOWABLE TIEBAR PROTRUSIONS ARE 0.150 PER SIDE. DIM MIN MAX MILLIMETERS A 3.000 3.400 A1 0.025 0.125 A2 2.900 3.100 D 15.800 16.000 D1 11.700 12.600 D2 0.900 1.100 E 13.950 14.450 E1 10.900 11.100 E2 2.500 2.700 E3 6.400 7.300 E4 2.700 2.900 L 0.840 1.100 L1 0.350 BSC b 0.220 0.350 b1 0.220 0.320 c 0.230 0.320 c1 0.230 0.280 e 0.650 BSC h ––– 0.800 /C01130 8 aaa 0.200 bbb 0.100 /C0095/C0095 E5 ––– 1.000 D3 ––– 1.000 D34X E54X Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

40 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

44–LEAD QFN PLASTIC PACKAGE CASE 1310–01 ISSUE D N PIN 1 INDEX AREA EXPOSED DIE ATTACH PAD 6.55 6.85 44X 0.23 G B C0.1 C0.1 A 9 22 12 0.65 M0.1 C M0.05 C A B 44X 0.75 C0.1 A B C0.1 A B M M VIEW M–M NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF–PQFP–N. 4. CORNER CHAMFER MAY NOT BE PRESENT. DIMENSIONS OF OPTIONAL FEATURES ARE FOR REFERENCE ONLY. 5. COPLANARITY APPLIES TO LEADS, CORNER LEADS AND DIE ATTACH PAD. 6. FOR ANVIL SINGULATED QFN PACKAGES, MAXIMUM DRAFT ANGLE IS 12°. 40X DETAIL M PIN 1 IDENTIFIER 1.0 1.00 0.05 C0.1 C0.05 C SEATING PLANE DETAIL G VIEW ROTATED 90 CLOCKWISE° (0.65) (0.325) 0.8 0.75 0.00 6.55 6.85 0.50 0.37 (3.53) PREFERRED CORNER CONFIGURATION DETAIL N (0.25) DETAIL N CORNER CONFIGURATION OPTION 0.60 0.60 DETAIL M PREFERRED BACKSIDE PIN 1 INDEX DETAIL T DETAIL T PREFERRED BACKSIDE PIN 1 INDEX (90 ) DETAIL M BACKSIDE PIN 1 INDEX OPTION 0.06544X (45 )° 0.015 2X 0.39 0.31 0.24 0.24 0.1 0.0 3.4 0.475 0.425

3.3 BACKSIDE

0.25 0.15R Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

41MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA PACKAGE DIMENSIONS DWB SUFFIX 54–LEAD SOICW–EP PLASTIC PACKAGE CASE 1377–01 ISSUE B NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER–LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. CL17.8 7.4 27 28 0.10 A 2.35 SEATING PLANE 0.9 SECTION B–B 0.65 R0.08 MIN B A (0.29) 0.38 0.30 (0.25) ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ PLATING BASE METAL SECTION A–A ROTATED 90 CLOCKWISE/C0095 0.25 0.22

0.13 M CAB

A C7.6 18.0 10.3 5.15 A 54X 52X 2.65 0.3 A 2X 27 TIPS B C BB 0.1 0.00.50° 0.25 GAUGE PLANE MIN PIN 1 INDEX CC (1.43) 6.6 5.9

0.30 CAB

4.8 4.3 VIEW C–C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

42 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

43MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

44 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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