33291L

33291L FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• Designed to Operate Over Wide Supply Voltages of 5.5 V to 26.5 V
• Interfaces to Microprocessor Using 8-Bit SPI I/O Protocol up to 3.0 MHz
• 1 . 0 A Peak Current Outputs with Maximum RDS(ON) of 1.6 Ω at TJ - 150°C
• Outputs Current-Limited to Accommodate In-Rush Currents Associated with Switching Incandescent Loads
• Output Voltages Clamped to 53 V During Inductive Switching
• Maximum Sleep Current (I PWR) of 25 µA
• Maximum of 4.0 mA IDD During Operation
• Pb-Free Packaging Designated by Suffix Code EG

Figure 1. 33291L Simplified Application Schematic

ORDERING INFORMATION

Range (TA) Package MC33291LDW/R2 -40°C to 125°C 24 SOICW MCZ33291LEG/R2 MCU 33291L VDD V PWR SFPD CS SCLK SI RESET SO VDD VPWR OP 0 OP 1 OP 2 OP 3 OP 4 OP 5 OP 6 OP 7 GND

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Figure 2. 33291L Simplified Block Diagram Table 1. Fault Operation Overvoltage Overvoltage condition reported. Overtemperature Fault reported by Serial Output (SO) pin. Overcurrent SO pin reports short to battery/supply or overcurrent condition. Output ON, Open Load Fault Not reported. Output OFF, Open Load Fault SO pin reports output OFF open load condition. (cleared). Outputs can be turned back on with a new SPI command after VPWR has decayed below 26.5 V. Overtemperature Only the output experiencing an overtemperature condition turns OFF. SFPD pin is at 5.0 V (so long as the individual outputs are not experiencing thermal limit conditions).

Figure 3. 33291L Pin Connections Table 2. 33291L Pin Definitions 1 OP7 Output 7 Connection to drain of output MOSFET number seven. 2 OP6 Output 6 Connection to drain of output MOSFET number six. 3 SCLK System Clock Clocks the internal Shift registers of the 33291L. 5 – 8, 17 – 20 GND Ground Connection to IC Power Ground and functions as part of heat sinking path. 9 SO Serial Output Tri-stateable output from the Shift register.

10 CS Chip Select Whenever this pin is in a logic low state, data can be transferred from the MCU to

the 33291L through the SI pin and from the 33291L to the MCU through the SO pin. 11 OP5 Output 5 Connection to drain of output MOSFET number five. 12 OP4 Output 4 Connection to drain of output MOSFET number four. 13 OP3 Output 3 Connection to drain of output MOSFET number three. 14 OP2 Output 2 Connection to drain of output MOSFET number two.

15 SFPD Short Fault

16 VDD Logic Supply Plus supply for logic.

21 VPWR Output MOSFET

23 OP1 Output 1 Connection to drain of output MOSFET number one. 24 OP0 Output 0 Connection to drain of output MOSFET number zero.

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ELECTRICAL CHARACTERISTICS

Table 3. Maximum Ratings permanent damage to the device.

1. Transient capability with external 100 Ω resistor in series with VPWR pin and supply.
2. Exceeding these limits may cause a malf unction or permanent damage to the device.
3. Exceeding the limits on SCLK, SI, CS, SFPD, or RST pins may cause permanent damage to the device.
4. Continuous output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature

will require maximum output current computation using package RθJA.

1. ESD data available upon request.
2. ESD1 testing is performed in acco rdance with the Human Body Model (CZAP = 200 pF, RZAP = 1500 Ω), ESD2 testing is performed in

accordance with the Machine Model (CZAP = 200pF, RZAP = 0 Ω).

1. Maximum output clamp energy capability at 150 °C junction temperature using a single non-repetitive pulse method.
2. Maximum power dissipation at indicated j unction temperature with no heat sink used.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33291L Peak Package Reflow Temperature During Reflow (10), (11) TPPRT Note 11. °C Thermal Resistance All Outputs ON(12) Single Output ON(13) RθJA °C/W Notes 10. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 11. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), MC33xxxD enter 33xxx), and review parametrics. 12. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 13. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal. Table 3. Maximum Ratings (continued) permanent damage to the device.

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate value with VBAT = 13 V, TA = 25°C.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33291L STATIC ELECTRICAL CHARACTERISTICS Notes 14. SPI inputs and outputs operational. Fault status reporting ma y not be fully operational within this voltage range. Outputs remain operational somewhat below this VPWR range, but RDS(ON) will increase, causing power dissipation to increase. Outputs will re- establish their instructed state following a VPWR interruption as long as VDD remains non-interrupted. 15. This parameter is guaranteed by de sign, but it is not production tested. 16. Measured with the RST pin held at a logic high state. Outputs can be OFF or ON or in any combination thereof. 17. Device incorporates a power-ON reset function. For V DD less than the Undervoltage Lockout Threshold voltage, all data registers are reset and all outputs are disabled. 18. Output Fault Detect Threshold with outputs programmed OFF. Ou tput fault detect thresholds are the same for output opens and shorts. 19. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded to be OFF. Output Clamp Voltage 2.0 mA < IOUT < 200 mA VOK 45 53 65 V Output Leakage Current (VDD < 2.0 V) (20) IOUT(LKG) -25 0 25 µA Overtemperature Shutdown (Outputs OFF) (21) TLIM 155 180 – °C Overtemperature Shutdown Hysteresis (21) TLIM(HYS) – 10 20 °C DIGITAL INTERFACE Input Logic High Voltage (22) V IH 0.7 – 1.0 VDD Input Logic Low Voltage (22) V IL 0 – 0.2 VDD Input Logic Threshold Hysteresis (SCLK, RST, and SFPD) (23) VI (HYS) 50 100 500 mV SI Pull-Up Current (SI = 0 V) ISI 0 10 20 µA CS Pull-Up Current (CS = 0 V) ICS 0 10 20 µA SCLK Pull-Down Current (SCLK = 5.0 V) ISCLK 0 10 20 µA RST Pull-Down Current (RST = 5.0 V) I RST 5.0 25 50 µA SFPD Pull-Down Current (SFPD = 5.0 V) ISFPD 5.0 10 25 µA SO High-State Output Voltage (IOH = 1.0 mA) VSOH VDD - 0.4 V VDD - 0.2 V – V SO Low-State Output Voltage (IOL = -1.6 mA) VSOL – 0.2 0.4 V SO Tri-State Leakage Current (CS = 0.7 VDD, 0 V < VSO < VDD) ISOT -10 0 10 µA Input Capacitance (0 V < VDD < 5.5 V) (24) CIN – – 12 pF SO Tn-State Capacitance (0 V < VDD < 5.5 V) (25) CSOT – – 20 pF Notes 20. Output leakage current measured with the output OFF and at 16 V. 21. This parameter is guaranteed by de sign, but it is not production tested. 22. Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, RST, and SFPD inputs. 23. Hysteresis is characterized, but it is not production tested. 24. Input capacitance of SI CS, SCLK, RST, and SFPD for 0 V < VDD < 5.5 V. This parameter is guaranteed by design, but it is not production tested. 25. Tri-state capacitance of SO for 0 V < VDD < 5.5 V. This parameter is guaranteed by design, but it is not production tested. Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate value with VBAT = 13 V, TA = 25°C.

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

1. Output Rise and Fall time res pectively measured across a 26 Ω resistive load at 10% to 90% and 90% to 10% voltage points.
2. Output Turn-ON Delay time measured from 50% rising edge of CS to 90% of Output OFF voltage (VPWR) with RL = 26 Ω resistive load.
3. Output Turn-OFF Delay time measured from 50% rising edge of CS to 10% of Output OFF voltage (VPWR) with RL = 26 Ω resistive load.
4. Propagation time of Short Fault Disable Report measured from 50% rising edge of CS to 10% Output OFF voltage (VPWR), VPWR =
5. Output OFF Fault Report Delay measured from 50% rising edge of CS to 10% rising edge of Output OFF voltage (VPWR).
6. RST Low duration measured with outputs enabled and going to OFF or disabled condition.
7. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
8. Time required for output status data to be available for use at the SO pin.
9. Time required for output status data to be terminated at the SO pin.
10. Time required to obtain valid data out from SO following the rise of SCLK. See Figure 6, page 9.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33291L ELECTRICAL PERFORMANCE CURVES ELECTRICAL PERFORMANCE CURVES Figure 4. Valid Data Delay Time and Figure 5. Enable and Disable Time Test Circuit Figure 6. Valid Data Delay Time and Figure 7. Enable and Disable Time Waveforms CL represents the total capacitance of the test fixture and probe. CL represents the total capacitance of the test fixture and probe.

0.2 VDD

0.7 VDD

0.2 VDD 0

1. SO (high-to-low) waveform is for SO output with internal conditions such

tecting a circuit fault with CS in a High Logic state; e.g., open load.

1. SO (low-to-high) waveform is for SO output with internal conditions such

tecting a circuit fault with CS in a High Logic state; e.g., shortened load.

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ELECTRICAL PERFORMANCE CURVES Figure 8. Switching Time Test Circuit Figure 9. Output Fault Unlatch Disable Figure 10. Turn-On/-Off Waveforms Figure 11. Output Fault Unlatch Disable CL represents the total capacitance of the test fixture and probe. CL represents the total capacitance of the test fixture and probe.

1. tDLY(ON) and TDLY(OFF) are turn-ON and turn-OFF propagation delay
2. Turn-OFF is an output programmed from an ON to an OFF state.
3. Turn-ON is an output programmed from and OFF to an ON state.
4. tPDLY(OFF) is the output fault unlatch disable propagation delay time re-

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Figure 13. 33291L SPI System Daisy Chain three dedicated parallel MCU ports used for chip select. Figure 14. Parallel Input SPI Control become a slave when it detects a logic low state on its SS pin. communicate efficiently with the MCU. receives one data-bit of information per system clock cycle.

• Full duplex, three-wire synchronous data transfer
• Each microcontroller can be a master or a slave
• Provides write collision flag protection
• Provides end of message interrupt flag
• Four I/Os associated with SPI (MOSI, MISO, SCLK, SS) Drawbacks to SPI are as follows:
• An MCU is required for efficient operational control
• In contrast to parallel input control it is slower at performing pulse width modulating (PWM) functions. SCLK Parallel Port MISO MOSI IRQ MC68XX Microcontroller SPI SO SOSOSO CS CSCSCSSCLK SCLKSCLK SCLK SI SISISI 33291 33291 3329133291

8 Outputs 8 Outputs8 Outputs8 Outputs

8 Outputs

Figure 15. Multiple MCU SPI Control and from the 33291L to the MCU through the SO pin. also controls the output driver of the serial output (SO) pin. out of the SO line driver on the rising edge of the SCLK signal. from a low-to-high logic state.

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low to shut down the outputs and clear the input data register. Figure 16. Power ON Reset

Analog Integrated Circuit Device Data Freescale Semiconductor 15 33291L FUNCTIONAL DESCRIPTION POWER CONSUMPTION The 33291L has extremely low power consumption in both the operating and standby modes. In the standby, or Sleep, mode, with VDD ≤ 2.0 V, the current consumed by the VPWR pin is less than 25 µA. In the operating mode, the current drawn by the VDD pin is less than 4.0 mA (1.0 mA typical) while the current drawn at the VPWR pin is 2.0 mA maximum (1.0 mA typical). During normal operation, turning outputs ON increases IPWR by only 20 µA per output. Each output experiencing a soft short (overcurrent conditions just under the current limit) adds 0.5 mA to the IPWR current PARALLELING OF OUTPUTS Using MOSFETs as output switches permits connecting any combination of outputs together. RDS(ON) of MOSFETs have an inherent positive temperature coefficient providing balanced current sharing between outputs without destructive operation (bipolar outputs could not be paralleled in this fashion as thermal run-away would likely occur). The device can even be operated with all outputs tied together. This mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in RDS(ON) while the Output OFF Open Load Detect Currents and the Output Current Limits increase correspondingly (by a factor of eight if all outputs are paralleled). Less than 125 mΩ RDS(ON) at 25°C with current limiting of 8 A to 24 A will result if all outputs are paralleled together. There will be no change in the overvoltage detect or the OFF output threshold voltage range. The advantage of paralleling outputs within the same 33291L affords the existence of minimal RDS(ON) and output clamp voltage variation between outputs. Typically, the variation of RDS(ON) between outputs of the same device is less than 0.5 percent. The variation in clamp voltages, potentially affecting dynamic current sharing, is less than five percent. Paralleling outputs from two or more different devices is possible, but it is not recommended. There is no guarantee the R DS(ON) and clamp voltage of the two devices will match. System level thermal design analysis and verification should be conducted whenever paralleling outputs, particularly where different devices are involved.

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Figure 17. Data Transfer Timing NOTES: 1.RST pin is in a logic high-state during the above operation. 4.OD* corresponds to Old Databits. 5.For brevity, only DO7 and DO0 are shown which respectively correspond to Output 7 and Output 0. SO pin is enabled. Output Status information transferred to Output Shift Register. Data from the Shift Register is transferred to the Output Power Switches. Will change state on the rising edge of the SCLK pin signal. Will accept data on the falling edge of the SCLK pin signal.

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Figure 18. Output OFF Open Load Fault the 33291L will declare the condition to be an open load fault. causing the Open Load Fault is removed. experiencing a current greater than the current limit. during load short conditions providing system protection.

1. The output current of the de vice is monitored in an
2. The output current of t he device is sensed by

monitoring the MOSFET drain voltage.

1. The output thermal limit of the device is sensed and

output, affording robust independent output operation.

3.0 A will never be seen for more than 20 µs (a typical

Figure 19. Short Circuit Detect and condition is removed or thermal shutdown is reached.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33291L FUNCTIONAL DESCRIPTION Grounding the SFPD pin will enable the short fault protection shutdown circuitry. Consider a load short (output short to supply) occurring on an output before, during, and after output turn ON. When the CS signal rises to the high logic state, the corresponding output is turned ON and a delay timer is activated. The duration of the delay timer is 70 µs to 250 µs. If the short circuit takes place before the output is turned ON, the delay experienced is the entire 70 µs to 250 µs followed by shutdown. If the short occurs during the delay time, the shutdown still occurs after the delay time has elapsed. However, if the short circuit occurs after the delay time, shutdown is immediate (within 20 µs after sensing). The purpose of the delay timer is to prevent false faults from being reported when switching capacitive loads. If the SFPD pin is at 5.0 V (or VDD), an output will not be disabled when an overcurrent is detected. The specific output will, within 5.0 µs to 10 µs of encountering the short circuit, go into an analog current limited mode. This feature is especially useful when switching incandescent lamp loads, where high in-rush currents experienced during startup last for 10 ms to 20 ms. Each output of the 33291L has its own overcurrent shutdown circuitry. Overtemperature faults and overvoltage faults are not affected by the SFPD pin’s state. Both load current sensing and output voltage sensing are incorporated for Short Fault detection with actual detection occurring slightly after the onset of current limit. The current limit circuitry incorporates a SENSEFET approach to measure the total drain current. This calls for the current through a small number of cells in the power MOSFET to be measured and the result multiplied by a constant, giving the total current. Whereas an output shutdown circuitry measures the drain-to-source voltage, shutting down the output if its threshold (VTHRES) will be exceeded. Short fault detection is accomplished by sensing the output voltage and comparing it to VThres. The lowest VThres requires a voltage of 2.5 V to be sensed. For an enabled output, with VDD = 5.0 ± 0.5 V, an output voltage in excess of

3.5 V will be detected as a short (overcurrent condition), while

voltages less than 2.5 V will not be detected as shorts. OVERCURRENT RECOVERY If the SFPD pin is in a high logic state, the circuit returns to normal operation automatically after the short circuit is removed (unless thermal shutdown has occurred). If the SFPD pin is grounded and overcurrent shutdown occurs, removing the short circuit will result in the output remaining OFF until the next write cycle. If the short circuit is not removed, the output will turn ON for the delay time (70 µs to 250 µs) and then turn OFF for every write cycle commanding a turn ON. SFPD PIN VOLTAGE SELECTION Since the voltage condition of the SFPD pin controls the activation of the short fault protection (i.e., shutdown) mode equally for all eight outputs, the load having the longest duration of in-rush current determines what voltage (state) the SFPD pin should be. Usually if at least one load is, say an incandescent lamp, the in-rush current on that input will be milliseconds in duration. Therefore, setting SFPD at 5.0 V will prevent shutdown of the output due to the in-rush current. The system relies only on the overtemperature shutdown to protect the outputs and the loads. The 33291L was designed to switch GE194 incandescent lamps (or equivalents) with the SFPD pin in a grounded state. Considerably larger lamps can be switched with the SFPD pin held in a high logic state. Sometimes both a delay period greater than 70 µs to 250 µs (current limiting of the output) followed by an immediate overcurrent shutdown is necessary. This can be accomplished by programming the SFPD pin to 5.0 V for the extended delay period, allowing the outputs to remain ON in a current limited mode, then grounding it to accomplish the immediate shutdown after a period of time. Additional external circuitry is required to implement this type of function. An MCU parallel output port can be devoted to controlling the SFPD voltage during and after the delay period; this is often a much better method. In either case, care should be taken to execute the SFPD start-up routine every time startup or reset occurs. UNDERVOLTAGE SHUTDOWN An undervoltage VDD condition will result in the global shutdown of all outputs. The undervoltage threshold is between 2.5 V and 3.5 V. When VDD goes below the threshold, all outputs are turned OFF and the Serial Output data register is reset to indicate the same. An undervoltage condition at the VPWR pin will not cause output shutdown and reset. When VPWR is between 5.5 V and 9.0 V, the outputs will operate per the command word. However, the status as reported by the SO pin may not be accurate below 9.0 V VPWR. Proper operation at VPWR voltages below 5.5 V are not be guaranteed. DECIPHERING FAULT TYPE The 33291L SO pin can be used to determine what kind of system fault has occurred. With eight outputs having open load, overcurrent, overtemperature, and overvoltage faults, a total of 25 different faults are possible. The SO status word received by the MCU will be compared with the word sent to the 33291L during the previous write cycle. For a specific output, if the SO bit compares with the corresponding SI bit of the previous word, the output is operating normal with no fault. Only when the SO bit and previous word SI bit differ is there a fault indicated. If the two words are not the same, the MCU should be programmed to determine which output or outputs are faulted. If for a specific output the initial SI command bit were logic high, the output would be programmed to be off ; if upon the next command word being entered, a logic low came back on SO, for that specific output’s corresponding bit an output-off open-load fault would be indicated. The resulting SO bit for that specific output would be different from that entered during the previous word for that SI bit, indicating the fault.

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an overcurrent condition will be reported on the SO pin. effected for the duration of the overtemperature condition. Overcurrent and overtemperature faults are often related. following an overvoltage condition. energy to be dissipated in the linear mode (see Figure 20). energy to be 50 mJ at 150°C junction temperature per output. Figure 20. Output Voltage Clamping capacitance of the silicone die translator outputs and plastic.

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Figure 22. Maximum DIP Package Steady State Output Figure 23. Maximum SOP Package Steady State Output Figure 24. Maximum Output ON Resistance vs. Junction

1 Output ON (37°C/W)

4 Outputs ON (32°C/W)

8 Outputs ON (31°C/W)

4 Outputs ON (35°C/W)

8 Outputs ON (34°C/W)

1 Output ON (40°C/W)

Analog Integrated Circuit Device Data Freescale Semiconductor 23 33291L PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. DW SUFFIX EG SUFFIX (PB-FREE) 20-PIN PLASTIC PACKAGE 98ASB42344B ISSUE F

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REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 3.0 8/2006 • Implemented Revision History page

• Converted to Freescale format
• Added EPP prefix Z to EG suffix device
• Removed MC33291LEG/R2 and replaced with MCZ33291LEG/R2 in the Ordering Information block 4.0 11/2006 • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum ratings on page page 5. Added note with instructions to obtain this information from www.freescale.com.

Rev. 4.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007. All rights reserved. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http:// www.freescale.com/epp. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

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