33285_07 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

  • PWM Capability
  • Power TMOS Number One (OUT1) Short-Circuit Detection and Short-Circuit Protection
  • Voltage Range 7.0 V ≤ 40 V
  • Extended Temperature Range from -40 °C ≤ 125°C
  • Load Dump Protected
  • Overvoltage Detection and Activation of OUT2 During Overvoltage
  • Single Input Control for Both Output Stages
  • Capacitor Value of 100 nF Connected to Pin CP
  • Analog Input Control Measurement Detection
  • OUT1 LOAD Leakage Measurement Detection
  • Pb-Free Packaging Designated by Suffix Code EF

Figure 1. 33285 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33285D/R2 -40°C to 125°C 8 SOICN MCZ33285EF/R2 SRC OUT1 OUT2 DRN GND 33285 IN CP VCC VPWR Motor VCC Input Control

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Figure 2. 33285 Simplified Internal Block and Typical Applications Diagram

Figure 3. 33285 Pin Connections Table 1. 33285 Pin Definitions

1 SRC Source OUT2 external FET Source connection

2 OUT1 Output 1 This pin is output number 1

3 DRN Drain OUT1 and OUT2 external FET Drain connection

4 OUT2 Output 2 This pin is output number 2

5 CP Charge Pump External capacitor connection for internal the Charge Pump

6 VCC Voltage Power Supply Battery supply voltage

7 GND Ground This is the ground pin.

8 IN Input Voltage level sensitive input for OUT1 and OUT2

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ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device.

  1. Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

  1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 33285 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.

capacities with a current flowing out of pins OUT1 and OUT2. Figure 4. Turn On Behavior flowing through the external or the internal zener diode. (VCC + VTH) is reached, the current sources are turned OFF.

  • Threshold V TH1 for OUT1 output voltage control is

7.0 V < VTH1 < VZ

  • Threshold V TH2 for OUT2 output voltage control is

7.0 V < VTH2 < 15 V

  • Discharge current I OUTxOFF is IOUTxOFF = 110 µA condition: VOUT x > 0.5 V ( VIN < VTHRxIN )
  • Test conditions for switching OFF the power FETs: 1. IN open 2. Stages disabled via pin IN 3. Stage OUT1 disabled by an over current error 20 ms 2.5 V 5.0 V IN VCCP THRIN1 THRIN2 IN VOUT1 0 V 0 V 2.5 V IN 2.5 V 0 V 5.0 V VOUT2 IN tON1 VVCC + 7.0 VOUT2 VOUT2MAX tON2 tON3 VOUT1MAX VOUT1 VOUT2 tON1 tON2 tON3 VOLTAGE VVCC MINIMUM VOUT1, OUT2 AFTER TON1 = 100 µSEC MINIMUM VOUT1,OUT2 AFTER TON2 = 1.0 µSEC MINIMUM VOUT1,OUT2 AFTER TON3 = 1.5 µSEC

7.0 V < VVCC < 10 V

10 V < VVCC < 20 V

20 V < VVCC < 40 V

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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES INTRODUCTION The 33285 contains only one charge pump for two outputs.The outputs, OUT1 and OUT2, are switched ON and OFF by the input (IN) .There are three ways to control the outputs: OUT1 can be switched alone OUT1 and OUT2 can be switched together OUT2 can be switched when OUT1 is already on In the last case, the voltage drop on OUT1 when charging OUT2 is limited. The external capacitor (CCP) connected to the CHARGE PUMP (CP) pin is used to store the charge continuously delivered by the charge pump. The voltage on this pin is limited to a maximum value VCPMAX. Both outputs are sourced with a constant current from CCP to switch them ON. Additionally, the gates of the power FETs are precharged from voltage power supply (VCC) to prevent CCP from being discharged by a voltage on OUT1 or OUT2, is still lower than VVCC. The values of the output voltages are limited to VOUT1MAX and VOUT2MAX. The power FET on OUT1 is protected against an exceeded gate-source voltage by an internal zener diode. Channel One protects the N-Channel power FET on OUT1 undercurrent and short-circuit conditions. The drain-source voltage of the FET on OUT1 is checked if Channel One is switched ON. The internal error voltage threshold determines the maximum drain-source voltage allowing the power FET to stay in the ON state. If the measured drain-source voltage exceeds the internal error voltage threshold, the output of the short-circuit protection comparator (SCPC) is enabled. If the output of the SCPC is active longer than tOCDET, output OUT1 is switched OFF. After switching OFF the power FET on OUT1 by an short- circuit condition, the power FET can only be turned ON again by the input IN. When switching OFF the power FETs their gate capacities are discharged by a constant current, IOUTOFF. If the input IN is disconnected, the 33285 outputs, OUT1 and OUT2, are in the OFF state. If overvoltage occurs on the DRAIN (DRN) pin for a time period longer than tLDDET, OUT2 is switched ON for the time tOUT2ACT. In an overvoltage condition OUT1 is OFF if IN is below VIH. INTERNAL ZENER DIODE An on-chip zener diode is placed between OUT1 and The SOURCE (SRC). Design guarantees VZ > VTH1. Zener clamping voltage between OUT1 and SRC is VTH1 < VZ < 20 V PWM CAPABILITY The CPIC2 is PWM capable on OUT2. The loss of charge ON CCP when switching ON OUT2 is refreshed until the Start on the next PWM cycle to a value sufficient to guarantee the specified turn ON behavior. The PWM capability is measured with a test circuit and load conditions:

  • PWM cycle is period T = 20 ms ; OUT2 is switched ON from 10 to 90 percent of T
  • Test condition V IN ramps 2.5 V ≤ 5.0 V according to PWM cycle defined above CROSS TALK BETWEEN OUT1 AND OUT2 If output OUT2 is switched ON while OUT1 is already ON, the voltage drop occurring on OUT1 is limited. Voltage drop on OUT1:
  • 1 0 V < VVCC < 20 V : OUT1 not below VVCC + 7.0 V
  • 7.0 V < V VCC < 20 V : OUT1 not below VVCC + 7.0 V Each time OUT1 is switched ON, a current ILCDET is sourced out of the SRC pin for the time tLCDET to check if there is an external leakage current on that node in the application. The high-side switch on OUT1 is turned ON only if the test is successful.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33285 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. D SUFFIX EF SUFFIX (PB-FREE) PLASTIC PACKAGE 98ASB42564B ISSUE U

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REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 4.0 9/2006 • Implemented Revision History page

  • Converted to Freescale format
  • Added part number MCZ33285EF (Pb-FREE) to Ordering Information 5.0 2/2007 • Added Peak Package Reflow Temperature During Reflow (1), (2) to Maximum Ratings
  • Added notes (1) and (2)

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33285

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