MC33077 ONSEMI | Alldatasheet

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/C0077/C0067/C0051/C0051/C0048/C0055/C0055 SEMICONDUCTOR TECHNICAL DATA DUAL, LOW NOISE OPERATIONAL AMPLIFIER

ORDERING INFORMATION

TA = – 40° to +85°C SO–8 Plastic DIP Order this document by MC33077/D VEE D SUFFIX PLASTIC PACKAGE CASE 751 (SO–8) P SUFFIX PLASTIC PACKAGE CASE 626 PIN CONNECTIONS 8V CC Output 2 Inputs 2 Inputs 1 (Dual, Top View) Output 1 1MOTOROLA ANALOG IC DEVICE DATA /C0068/C0117/C0097/C0108/C0044 /C0076/C0111/C0119 /C0078/C0111/C0105/C0115/C0101 /C0079/C0112/C0101/C0114/C0097/C0116/C0105/C0111/C0110/C0097/C0108 /C0065/C0109/C0112/C0108/C0105/C0102/C0105/C0101/C0114 The MC33077 is a precision high quality, high frequency, low noise monolithic dual operational amplifier employing innovative bipolar design techniques. Precision matching coupled with a unique analog resistor trim technique is used to obtain low input offset voltages. Dual–doublet frequency compensation techniques are used to enhance the gain bandwidth product of the amplifier. In addition, the MC33077 offers low input noise voltage, low temperature coefficient of input offset voltage, high slew rate, high AC and DC open loop voltage gain and low supply current drain. The all NPN transistor output stage exhibits no deadband cross–over distortion, large output voltage swing, excellent phase and gain margins, low open loop output impedance and symmetrical source and sink AC frequency performance. The MC33077 is tested over the automotive temperature range and is available in plastic DIP and SO–8 packages (P and D suffixes).

  • Low Voltage Noise: 4.4 nV/ Hz/C0504@ 1.0 kHz
  • Low Input Offset Voltage: 0.2 mV
  • Low TC of Input Offset Voltage: 2.0 µV/°C
  • High Gain Bandwidth Product: 37 MHz @ 100 kHz
  • High AC Voltage Gain: 370 @ 100 kHz High AC Voltage Gain: 1850 @ 20 kHz
  • Unity Gain Stable: with Capacitance Loads to 500 pF
  • High Slew Rate: 11 V/µs
  • Low Total Harmonic Distortion: 0.007%
  • Large Output Voltage Swing: +14 V to –14.7 V
  • High DC Open Loop Voltage Gain: 400 k (112 dB)
  • High Common Mode Rejection: 107 dB
  • Low Power Supply Drain Current: 3.5 mA
  • Dual Supply Operation: ±2.5 V to ±18 V R1 R6 R8 R11 R16 Q17 Q19 Q13 Q11 D 1 R4 R7 R5 C2 PosQ7 Q9 Q10 Q12 VCC Q21 Vout R19 Q22 R20Q20 R17 R18 Q14 R13 R14 Q16 Neg R10 R12 R15 VEE Bias Network Representative Schematic Diagram (Each Amplifier)  Motorola, Inc. 1996 Rev 0

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Supply Voltage (VCC to VEE ) VS +36 V Input Differential Voltage Range VIDR (Note 1) V Input Voltage Range VIR (Note 1) V Output Short Circuit Duration (Note 2) tSC Indefinite sec Maximum Junction Temperature TJ +150 °C Storage Temperature Tstg –60 to +150 °C Maximum Power Dissipation PD (Note 2) mW NOTES: 1. Either or both input voltages should not exceed VCC or VEE (See Applications Information). 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (See power dissipation performance characteristic, Figure 1). DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Input Offset Voltage (RS = 10 Ω , VCM = 0 V, VO = 0 V) TA = +25°C TA = –40° to +85°C |VIO| 0.13 1.0 1.5 mV Average Temperature Coefficient of Input Offset Voltage R S = 10 Ω , VCM = 0 V, VO = 0 V, TA = –40° to +85°C ΔVIO/ΔT — 2.0 — µV/°C Input Bias Current (VCM = 0 V, VO = 0 V) TA = +25°C TA = –40° to +85°C IIB 280 1000 1200 nA Input Offset Current (VCM = 0 V, VO = 0 V) TA = +25°C TA = –40° to +85°C IIO 180 240 nA Common Mode Input Voltage Range (ΔVIO ,= 5.0 mV, VO = 0 V) VICR ±13.5 ±14 — V Large Signal Voltage Gain (VO = ±1.0 V, RL = 2.0 kΩ ) TA = +25°C TA = –40° to +85°C AVOL 150 k 125 k 400 k V/V Output Voltage Swing (VID = ±1.0 V) R L = 2.0 kΩ R L = 2.0 kΩ R L = 10 kΩ R L = 10 kΩ VO+ VO– VO+ VO– +13.0 +13.4 +13.6 –14.1 +14.0 –14.7 –13.5 –14.3 V Common Mode Rejection (Vin = ±13 V) CMR 85 107 — dB Power Supply Rejection (Note 3) VCC /VEE = +15 V/ –15 V to +5.0 V/ –5.0 V PSR 80 90 — dB Output Short Circuit Current (VID = ±1.0 V, Output to Ground) Source Sink ISC +10 –20 +26 –33 +60 +60 mA Power Supply Current (VO = 0 V, All Amplifiers) TA = +25°C TA = –40° to +85°C ID 3.5 4.5 4.8 mA NOTE: 3. Measured with VCC and VEE simultaneously varied.

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Figure 3. Input Bias Current Figure 4. Input Offset Voltage Figure 5. Input Bias Current versus Figure 6. Input Common Mode Voltage Range Figure 7. Output Saturation Voltage versus Figure 8. Output Short Circuit Current

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Figure 15. Output Voltage Figure 16. Open Loop Voltage Gain Figure 17. Open Loop Voltage Gain Figure 18. Output Impedance Figure 19. Channel Separation Figure 20. Total Harmonic Distortion

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Figure 27. Phase Margin versus Figure 28. Overshoot versus Figure 29. Input Referred Noise Voltage Figure 30. Total Input Referred Noise Voltage Figure 31. Phase Margin and Gain Margin

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The MC33077 is designed primarily for its low noise, low offset voltage, high gain bandwidth product and large output swing characteristics. Its outstanding high frequency gain/phase performance make it a very attractive amplifier for high quality preamps, instrumentation amps, active filters and other applications requiring precision quality characteristics. The MC33077 utilizes high frequency lateral PNP input transistors in a low noise bipolar differential stage driving a compensated Miller integration amplifier. Dual–doublet frequency compensation techniques are used to enhance the gain bandwidth product. The output stage uses an all NPN transistor design which provides greater output voltage swing and improved frequency performance over more conventional stages by using both PNP and NPN transistors (Class AB). This combination produces an amplifier with superior characteristics. Through precision component matching and innovative current mirror design, a lower than normal temperature coefficient of input offset voltage (2.0 µV/°C as opposed to 10 µV/°C), as well as low input offset voltage, is accomplished. The minimum common mode input range is from 1.5 V below the positive rail (VCC ) to 1.5 V above the negative rail (VEE ). The inputs will typically common mode to within 1.0 V of both negative and positive rails though degradation in offset voltage and gain will be experienced as the common mode voltage nears either supply rail. In practice, though not recommended, the input voltage may exceed VCC by approximately 30 V and decrease below the VEE by approximately 0.6 V without causing permanent damage to the device. If the input voltage on either or both inputs is less than approximately 0.6 V, excessive current may flow, if not limited, causing permanent damage to the device. The amplifier will not latch with input source currents up to 20 mA, though in practice, source currents should be limited to 5.0 mA to avoid any parametric damage to the device. If both inputs exceed VCC , the output will be in the high state and phase reversal may occur. No phase reversal will occur if the voltage on one input is within the common mode range and the voltage on the other input exceeds VCC . Phase reversal may occur if the input voltage on either or both inputs is less than 1.0 V above the negative rail. Phase reversal will be experienced if the voltage on either or both inputs is less than VEE . Through the use of dual–doublet frequency compensation techniques, the gain bandwidth product has been greatly enhanced over other amplifiers using the conventional single pole compensation. The phase and gain error of the amplifier remains low to higher frequencies for fixed amplifier gain configurations. With the all NPN output stage, there is minimal swing loss to the supply rails, producing superior output swing, no crossover distortion and improved output phase symmetry with output voltage excursions (output phase symmetry being the amplifiers ability to maintain a constant phase relation independent of its output voltage swing). Output phase symmetry degradation in the more conventional PNP and NPN transistor output stage was primarily due to the inherent cut–off frequency mismatch of the PNP and NPN transistors used (typically 10 MHz and 300 MHz, respectively), causing considerable phase change to occur as the output voltage changes. By eliminating the PNP in the output, such phase change has been avoided and a very significant improvement in output phase symmetry as well as output swing has been accomplished. The output swing improvement is most noticeable when operation is with lower supply voltages (typically 30% with ± 5.0 V supplies). With a 10 k load, the output of the amplifier can typically swing to within 1.0 V of the positive rail (VCC ), and to within 0.3 V of the negative rail (VEE ), producing a 28.7 Vpp signal from ±15 V supplies. Output voltage swing can be further improved by using an output pull–up resistor referenced to the VCC . Where output signals are referenced to the positive supply rail, the pull–up resistor will pull the output to VCC during the positive swing, and during the negative swing, the NPN output transistor collector will pull the output very near VEE . This configuration will produce the maximum attainable output signal from given supply voltages. The value of load resistance used should be much less than any feedback resistance to avoid excess loading and allow easy pull–up of the output. Output impedance of the amplifier is typically less than 50 Ω at frequencies less than the unity gain crossover frequency (see Figure 18). The amplifier is unity gain stable with output capacitance loads up to 500 pF at full output swing over the –55° to +125°C temperature range. Output phase symmetry is excellent with typically 4°C total phase change over a 20 V output excursion at 25°C with a 2.0 kΩ and 100 pF load. With a 2.0 kΩ resistive load and no capacitance loading, the total phase change is approximately one degree for the same 20 V output excursion. With a 2.0 kΩ and 500 pF load at 125°C, the total phase change is typically only 10°C for a 20 V output excursion (see Figure 27). As with all amplifiers, care should be exercised to insure that one does not create a pole at the input of the amplifier which is near the closed loop corner frequency. This becomes a greater concern when using high frequency amplifiers since it is very easy to create such a pole with relatively small values of resistance on the inputs. If this does

amplifiers input capacitance. BW = Upper and lower frequency limit in Hertz. ground without exceeding the temperature rating. Figure 36. Voltage Noise Test Circuit Note: All capacitors are non–polarized.

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CASE 626–05 ISSUE K D SUFFIX PLASTIC PACKAGE CASE 751–05 (SO–8) ISSUE R OUTLINE DIMENSIONS NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. F NOTE 2 –A– –B– –T– SEATING PLANE H J G D K N C L M MAM0.13 (0.005) B MT DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.40 10.16 0.370 0.400 B 6.10 6.60 0.240 0.260 C 3.94 4.45 0.155 0.175 D 0.38 0.51 0.015 0.020 F 1.02 1.78 0.040 0.070 G 2.54 BSC 0.100 BSC H 0.76 1.27 0.030 0.050 J 0.20 0.30 0.008 0.012 K 2.92 3.43 0.115 0.135 L 7.62 BSC 0.300 BSC N 0.76 1.01 0.030 0.040 /C0095/C0095 SEATING PLANE A0.25 M CB SS

0.25 M B M

h /C0113 C X 45/C0095 L DIM MIN MAX MILLIMETERS A 1.35 1.75 A1 0.10 0.25 B 0.35 0.49 C 0.18 0.25 D 4.80 5.00 E

1.27 BSCe

3.80 4.00 H 5.80 6.20 h 0 7 L 0.40 1.25 /C0113 0.25 0.50 /C0095/C0095 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. D E H A B e BA1 C A 0.10 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;JAPAN : Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–54543–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 INTERNET : http://Design–NET.com 51 Ting Kok R oad, Tai Po, N.T., Hong Kong. 852–26629298 MC33077/D /C0042/C0077/C0067/C0051/C0051/C0048/C0055/C0055/C0047/C0068/C0042