32G431

STM32G431X6 STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 198

Technical content

Datasheet sections

• 1 Introduction
• 2 Description
• 3 Functional overview
• 3.1 Arm ® Cortex®-M4 core with FPU
• 3.2 Adaptive real-time memory accelerator (ART accelerator)
• 3.3 Memory protection unit
• 3.4 Embedded Flash memory
• 3.5 Embedded SRAM
• 3.6 Multi-AHB bus matrix
• 3.7 Boot modes
• 3.8 CORDIC
• 3.9 Filter mathematical accelerator (FMAC)
• 3.10 Cyclic redundancy check calculation unit (CRC )
• 3.11 Power supply management
• 3.11.1 Power supply schemes
• 3.11.2 Power supply supervisor
• 3.11.3 Voltage regulator
• 3.11.4 Low-power modes
• 3.11.5 Reset mode
• 3.11.6 VBAT operation
• 3.12 Interconnect matrix
• 3.13 Clocks and startup
• 3.14 General-purpose inputs/outputs (GPIOs)
• 3.15 Direct memory access controller (DMA)
• 3.16 DMA request router (DMAMUX)
• 3.17 Interrupts and events
• 3.17.1 Nested vectored interrupt controller (NVIC)
• 3.17.2 Extended interrupt/event controller (EXTI)
• 3.18 Analog-to-digital converter (ADC)
• 3.18.1 Temperature sensor

Datasheet sections

• 3.18.2 Internal voltage reference (VREFINT)
• 3.18.3 VBAT battery voltage monitoring
• 3.19 Digital to analog converter (DAC)
• 3.20 Voltage reference buffer (VREFBUF)
• 3.21 Comparators (COMP)
• 3.22 Operational amplifier (OPAMP)
• 3.23 Random number generator (RNG)
• 3.24 Timers and watchdogs
• 3.24.1 Advanced motor control timer (TIM1, TIM8)
• 3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16,
• 3.24.3 Basic timers (TIM6 and TIM7)
• 3.24.4 Low-power timer (LPTIM1)
• 3.24.5 Independent watchdog (IWDG)
• 3.24.6 System window watchdog (WWDG)
• 3.24.7 SysTick timer
• 3.25 Real-time clock (RTC) and backup registers
• 3.26 Tamper and backup registers (TAMP)
• 3.27 Infrared transmitter
• 3.28 Inter-integrated circuit interface (I
• 3.29 Universal synchronous/asynchronous re ceiver transmitter (USART)
• 3.30 Low-power universal asynchronous rece iver transmitter (LPUART)
• 3.31 Serial peripheral interface (SPI)
• 3.32 Serial audio interfaces (SAI)
• 3.32.1 SAI peripheral supports
• 3.33 Controller area network (FDCAN1)
• 3.34 Universal serial bus (USB)
• 3.35 USB Type-C™ / USB Power Delivery controller (UCPD)
• 3.36 Clock recovery system (CRS)
• 3.37 Development support
• 3.37.1 Serial wire JTAG debug port (SWJ-DP)
• 3.37.2 Embedded trace macrocell™
• 4 Pinouts and pin description
• 4.1 UFQFPN32 pinout description

Datasheet sections

• 5.3.14 I/O port characteristics
• 5.3.15 NRST pin characteristics
• 5.3.17 Analog switches booster
• 5.3.18 Analog-to-digital converter characteristics
• 5.3.19 Digital-to-Analog converter characteristics
• 5.3.20 Voltage reference buffer ch aracteristics
• 5.3.21 Comparator characteristics
• 5.3.22 Operational amplifiers characteristics
• 5.3.23 Temperature sensor characteristics
• 5.3.25 Timer characteristics
• 5.3.26 Communication interfaces characteristics
• 5.3.27 UCPD characteristics
• 6 Package information
• 6.1 UFQFPN32 package information
• 6.2 LQFP32 package information
• 6.3 UFQFPN48 package information
• 6.4 LQFP48 package information
• 6.5 WLCSP49 package information
• 6.6 LQFP64 package information
• 6.7 UFBGA64 package information
• 6.8 LQFP80 package information
• 6.9 LQFP100 package information
• 6.10 Thermal characteristics
• 6.10.1 Reference document
• 6.10.2 Selecting the product temperature range
• 7 Ordering information
• 8 Revision history

Features

Includes ST state-of-the-art patented technology

• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions
• Operating conditions: DD, VDDA voltage range: 1.71 V to 3.6 V
• Mathematical hardware accelerators – CORDIC for trigonometric functions acceleration – FMAC: filter mathematical accelerator
• Memories – 128 Kbytes of Flash memory with ECC support, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP – 22 Kbytes of SRAM, with hardware parity check implemented on the first 16 Kbytes – Routine booster: 10 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM)
• Reset and supply management – Power-on/power-down reset (POR/PDR/BOR) – Programmable voltage detector (PVD) – Low-power modes: sleep, stop, standby and shutdown BAT supply for RTC and backup registers
• Clock management –4 to 48 MHz crystal oscillator – 32 kHz oscillator with calibration – Internal 16 MHz RC with PLL option (± 1%) – Internal 32 kHz RC oscillator (± 5%)
• Up to 86 fast I/Os – All mappable on external interrupt vectors – Several I/Os with 5 V tolerant capability
• Interconnect matrix
• 12-channel DMA controller
• 2 x ADCs 0.25 µs (up to 23 channels). Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range
• 4 x 12-bit DAC channels – 2 x buffered external channels 1 MSPS – 2 x unbuffered internal channels 15 MSPS
• 4 x ultra-fast rail-to-rail analog comparators
• 3 x operational amplifiers that can be used in PGA mode, all terminals accessible
• Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.9 V)
• 14 timers: – 1 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input – 2 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop LQFP48 (7 x 7 mm) LQFP64 (10 x 10 mm) LQFP80 (12 x 12 mm) LQFP32 (7 x 7 mm) UFBGA64 (5 x 5 mm) UFQFPN32 (5 x 5 mm) UFQFPN48 (7 x 7 mm) WLCSP49 (Pitch 0.4) FBGA LQFP100 (14 x 14 mm)

• Calendar RTC with alarm, periodic wakeup from stop/standby
• Communication interfaces – 1 x FDCAN controller supporting flexible data rate – 3 x I 2C Fast mode plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus, wakeup from stop – 4 x USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control) –1 x L P U A R T – 3 x SPIs, 4 to 16 programmable bit frames, 2 x with multiplexed half duplex I interface – 1 x SAI (serial audio interface) – USB 2.0 full-speed interface with LPM and BCD support – IRTIM (infrared interface) – USB Type-C™ /USB power delivery controller (UCPD)
• True random number generator (RNG)
• CRC calculation unit, 96-bit unique ID
• Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™

Table 1. Device summary

STM32G431x6 STM32G431x8 STM32G431xB Contents

5.3.6 Wakeup time from low-power modes and voltage scaling

Table 21. Current consumption in Run and Low-power run modes, code with data Table 22. Current consumption in Run and Low-power run modes, Table 23. Typical current consumption in Run a nd Low-power run modes, with different codes Table 24. Typical current consumption in Run a nd Low-power run modes, with different codes Table 25. Typical current consumption in Run a nd Low-power run modes, with different codes Table 26. Typical current consumption in Run a nd Low-power run modes, with different codes Table 41. LSE oscillator characteristics (f

Introduction STM32G431x6 STM32G431x8 STM32G431xB 12/198 DS12589 Rev 6

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32G431x6/x8/xB microcontrollers. This document should be read in conjunction with the reference manual RM0440 “STM32G4 Series advanced Arm® 32-bit MCUs”. The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 technical reference manual, available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (o r its subsidiaries) in the US and/or elsewhere.

STM32G431x6 STM32G431x8 STM32G431xB Description

2 Description

The STM32G431x6/x8/xB devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 170 MHz. The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security. These devices embed high-speed memories (up to 128 Kbytes of Flash memory, and

32 Kbytes of SRAM), an extensive range of enhanced I/Os and peripherals connected to

two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. The devices also embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, securable memory area and proprietary code readout protection. The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC for trigonometric functions and FMAC unit for filter functions). They offer two fast 12-bit ADCs (4 Msps), four comparators, three operational amplifiers, four DAC channels (2 external and 2 internal), an internal voltage reference buffer, a low- power RTC, one general-purpose 32-bit timers, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and one 16-bit low-power timer. They also feature standard and advanced communication interfaces such as: - Three I2Cs - Three SPIs multiplexed with two half duplex I2Ss - Three USARTs, one UART and one low-power UART. - One FDCAN - One SAI - USB device - UCPD The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications. Some independent power supplies are supported including an analog independent supply input for ADC, DAC, OPAMPs and comparators. A V BAT input allows backup of the RTC and the registers. The STM32G431x6/x8/xB family offers 9 packages from 32-pin to 100-pin.

Table 2. STM32G431x6/x8/xB features and peripheral counts

1. The SPI2/3 interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.

Table 2. STM32G431x6/x8/xB features and peripheral counts (continued)

Figure 1. STM32G431x6/x8/xB block diagram

1. AF: alternate function on I/O pins.

4 CH, ETR as AFTIMER2

4 CH, ETR as AFTIMER3&4

6 Chan

4 PWM,4PWM,

STM32G431x6 STM32G431x8 STM32G431xB Functional overview

3 Functional overview

3.1 Arm ® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of the MCU implementation, with a reduced pin count and with low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The Arm ® Cortex®-M4 with FPU 32-bit RISC processor features an exceptional code- efficiency, delivering the expected high-performance from an Arm core in a memory size usually associated with 8-bit and 16-bit devices. The processor supports a set of DSP instructions which allows an efficient signal processing and a complex algorithm execution. Its single precision FPU speeds up the software development by using metalanguage development tools to avoid saturation. With its embedded Arm core, the STM32G431x6/x8/xB family is compatible with all Arm tools and software. Figure 1 shows the general block diagram of the STM32G431x6/x8/xB devices.

3.2 Adaptive real-time memory accelerator (ART accelerator)

The ART accelerator is a memory accelerator that is optimized for the STM32 industry- standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory and to prevent one task to accidentally corrupt the memory or the resources used by any other active task. This memory area is organized into up to 8 protected areas, which can be divided in up into 8 subareas each. The protection area sizes range between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real- time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it.

3.4 Embedded Flash memory

The STM32G431x6/x8/xB devices feature up to 128 Kbytes of embedded Flash memory which is available for storing programs and data. Flexible protections can be configured thanks to the option bytes:

Functional overview STM32G431x6 STM32G431x8 STM32G431xB 18/198 DS12589 Rev 6

• Readout protection (RDP) to protect the whole memory. Three levels of protection are available: – Level 0: no readout protection – Level 1: memory readout prot ection; the Flash memory cannot be read from or written to if either the debug features are connected or the boot in RAM or bootloader are selected – Level 2: chip readout protection; the d ebug features (Cortex-M4 JTAG and serial wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This selection is irreversible.
• Write protection (WRP): the protected area is protected against erasing and programming.
• Proprietary code readout protection (PCROP): a part of the Flash memory can be protected against read and write from third parties. The protected area is execute-only and it can only be reached by the STM32 CPU as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.
• Securable memory area: a part of Flash memory can be configured by option bytes to be securable. After reset this securable memory area is not secured and it behaves like the remainder of main Flash memory (execute, read, write access). When secured, any access to this securable memory area generates corresponding read/write error. Purpose of the Securable memory area is to protect sensitive code and data (secure keys storage) which can be executed only once at boot, and never again unless a new reset occurs. The Flash memory embeds the error correction code (ECC) feature supporting:
• Single error detection and correction
• Double error detection
• The address of the ECC fail can be read in the ECC register
• 1 Kbyte (128 double word) OTP (one-time programmable) for user data. The OTP area is available in Bank 1 only. The OTP data cannot be erased and can be written only once.

3.5 Embedded SRAM

STM32G431x6/x8/xB devices feature 32 Kbytes of embedded SRAM. This SRAM is split into three blocks:

• 16 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the SRAM1 through the System Bus (or through the I-Code/D-Code buses when boot from SRAM1 is selected or when physical remap is selected by SYSCFG_MEMRMP register). Whole SRAM1 supports hardware parity check.
• 6 Kbytes mapped at address 0x2000 4000 (SRAM2). The CM4 can access the SRAM2 through the System bus. SRAM2 can be kept in stop and standby modes.
• 10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU through I-Code/D-Code bus for maximum performance. It is also aliased at 0x2000 5800 address to be accessed by all masters (CPU, DMA1, DMA2) through SBUS contiguously to SRAM1 and SRAM2. The CCM SRAM supports hardware parity check and can be write-protected with 1-Kbyte granularity.
• The memory can be accessed in read/write at max CPU clock speed with 0 wait states.

3.6 Multi-AHB bus matrix

operation even when several high-speed peripherals work simultaneously. Figure 2. Multi-AHB bus matrix

3.7 Boot modes

• Boot from user Flash
• Boot from system memory
• Boot from embedded SRAM The BOOT0 value may come from the PB8-BOOT0 pin or from an nBOOT0 option bit depending on the value of a user nBOOT_SEL option bit to free the GPIO pad if needed. The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, and USB through the DFU (device firmware upgrade). MS47544V1 Cortex®-M4 with FPU DMA1 DMA2 CCM SRAM AHB1 peripherals AHB2 peripherals SRAM1 FLASH 128 KB ACCEL S-bus D-bus ICode DCode I-bus BusMatrix-S SRAM2

Functional overview STM32G431x6 STM32G431x8 STM32G431xB 20/198 DS12589 Rev 6

3.8 CORDIC

The CORDIC provides hardware acceleration of certain mathematical functions, notably trigonometric, commonly used in motor control, metering, signal processing and many other applications. It speeds up the calculation of these functions compared to a software implementation, allowing a lower operating frequency, or freeing up processor cycles in order to perform other tasks. Cordic features

• 24-bit CORDIC rotation engine
• Circular and Hyperbolic modes
• Rotation and Vectoring modes
• Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root, Natural logarithm
• Programmable precision up to 20-bit
• Fast convergence: 4 bits per clock cycle
• Supports 16-bit and 32-bit fixed point input and output formats
• Low latency AHB slave interface
• Results can be read as soon as ready without polling or interrupt
• DMA read and write channels

3.9 Filter mathematic al accelerator (FMAC)

The filter mathematical accelerator unit performs arithmetic operations on vectors. It comprises a multiplier/accumulator (MAC) unit, together with address generation logic, which allows it to index vector elements held in local memory. The unit includes support for circular buffers on input and output, which allows digital filters to be implemented. Both finite and infinite impulse response filters can be realized. The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing up the processor for other tasks. In many cases it can accelerate such calculations compared to a software implementation, resulting in a speed-up of time critical tasks.

STM32G431x6 STM32G431x8 STM32G431xB Functional overview FMAC features

• 16 x 16-bit multiplier
• 24+2-bit accumulator with addition and subtraction
• 16-bit input and output data
• 256 x 16-bit local memory
• Up to three areas can be defined in memory for data buffers (two input, one output), defined by programmable base address pointers and associated size registers
• Input and output sample buffers can be circular
• Buffer “watermark” feature reduces overhead in interrupt mode
• Filter functions: FIR, IIR (direct form 1)
• AHB slave interface
• DMA read and write data channels

3.10 Cyclic redundancy che ck calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator with polynomial value and size. Among other applications, the CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify the Flash memory integrity. The CRC calculation unit helps to compute a signature of the software during runtime, which can be ulteriorly compared with a reference signature generated at link-time and which can be stored at a given memory location.

3.11 Power supply management

3.11.1 Power supply schemes

The STM32G431x6/x8/xB devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent supplies, can be provided for specific peripherals:

• VDD = 1.71 V to 3.6 V VDD is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through the VDD pins.
• V DDA = 1.62 V to 3.6 V (see Section 5: Electrical characteristics for the minimum VDDA voltage required for ADC, DAC, COMP , OPAMP, VREFBUF operation). VDDA is the external analog power supply for A/D converters, D/A converters, voltage reference buffer, operational amplifiers and comparators. The VDDA voltage level is independent from the VDD voltage and should preferably be connected to VDD when these peripherals are not used.
• VBAT = 1.55 V to 3.6 V VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

Functional overview STM32G431x6 STM32G431x8 STM32G431xB 22/198 DS12589 Rev 6

• VREF-, VREF+ VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer when enabled. When VDDA < 2 V VREF+ must be equal to VDDA. When VDDA ≥ 2 V VREF+ must be between 2 V and VDDA. The internal voltage reference buffer supports three output voltages, which are configured with VRS bits in the VREFBUF_CSR register: –V REF+ = 2.048 V –V REF+ = 2.5 V –V REF+ = 2.9 V VREF- is double bonded with VSSA.

3.11.2 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes (except for Shutdown mode). The BOR ensures proper operation of the device after power- on and during power down. The device remains in reset mode when the monitored supply voltage V DD is below a specified threshold, without the need for an external reset circuit. The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. In addition, the device embeds a peripheral voltage monitor which compares the independent supply voltages V DDA, with a fixed threshold in order to ensure that the peripheral is in its functional supply range.

3.11.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator (LPR), supply most of digital circuitry in the device. The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby and Shutdown modes, both regulators are powered down and their outputs set in high- impedance state, such as to bring their current consumption close to zero. The device supports dynamic voltage scaling to optimize its power consumption in Run mode. the voltage from the main regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency. The main regulator (MR) operates in the following ranges:

• Range 1 boost mode with the CPU running at up to 170 MHz.
• Range 1 normal mode with CPU running at up to 150 MHz.
• Range 2 with a maximum CPU frequency of 26 MHz.

STM32G431x6 STM32G431x8 STM32G431xB Functional overview

3.11.4 Low-power modes

By default, the microcontroller is in Run mode after system or power Reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode: In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
• Low-power run mode: This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.
• Low-power sleep mode: This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the Low power run mode.
• Stop mode: In Stop mode, the device achieves the lowest power consumption while retaining the SRAM and register contents. All clocks in the VCORE domain are stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event.
• Standby mode: The Standby mode is used to achieve the lowest power consumption with brown-out reset, BOR. The internal regulator is switched off to power down the VCORE domain. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are also powered down. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The BOR always remains active in Standby mode. For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode. Upon entering Standby mode, SRAM and register contents are lost except for registers in the RTC domain and standby circuitry. The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE (CSS on LSE).
• Shutdown mode: The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off to power down the VCORE domain. The PLL, as well as the HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode. Therefore, switching to RTC domain is not supported. SRAM and register contents are lost except for registers in the RTC domain. The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper).

3.11.5 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disabled). In addition, the internal reset pull-up is deactivated when the reset source is internal.

Functional overview STM32G431x6 STM32G431x8 STM32G431xB 24/198 DS12589 Rev 6

3.11.6 V BAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when there is no external battery and when an external supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-tamper detection pins are available in VBAT mode. The VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC alarm/events exit the microcontroller from the VBAT operation.

3.12 Interconnect matrix

consumption. In addition, these hardware connections allow fast and predictable latency. Table 3. STM32G431x6/x8/xB peripherals interconnect matrix

Functional overview STM32G431x6 STM32G431x8 STM32G431xB 26/198 DS12589 Rev 6

3.13 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.
• System clock source: three different sources can deliver SYSCLK system clock: – 4 - 48 MHz high-speed oscillator with ex ternal crystal or ceramic resonator (HSE). It can supply clock to system PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (H SI16), trimmable by software. It can supply clock to system PLL. – System PLL with maximum output frequen cy of 170 MHz. It can be fed with HSE or HSI16 clocks.
• RC48 with clock recovery system (HSI48): internal HSIRC48 MHz clock source can be used to drive the USB or the RNG peripherals.
• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock (RTC): – 32.768 kHz low-speed oscillator with exte rnal crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for using an external clock. – 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to clock an independent watchdog.
• Peripheral clock sources: several peripherals (I2S, USART, I2C, LPTimer, ADC, SAI, RNG) have their own clock independent of the system clock.
• Clock security system (CSS): in the event of HSE clock failure, the system clock is automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected and generate an interrupt.
• Clock-out capability: – MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application – LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes. Several prescalers allow to configure the AHB frequency, the High-speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 170 MHz.

3.14 General-purpose in puts/outputs (GPIOs)

achieved thanks to their mapping on the AHB2 bus. sequence in order to avoid spurious writing to the I/Os registers.

3.15 Direct memory a ccess controller (DMA)

the priority between DMA requests.

• 12 independently configurable channels (requests) – Each channel is connected to a dedicated hardware DMA request, a software trigger is also supported on each channel. This configuration is done by software.
• Priorities between requests from channels of one DMA are both software programmable (4 levels: very high, high, medium, low) or hardware programmable in case of equality (request 1 has priority over request 2, etc.)
• Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size.
• Support for circular buffer management
• 3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed together in a single interrupt request for each channel
• Memory-to-memory transfer
• Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers
• Access to Flash, SRAM, APB and AHB peripherals as source and destination
• Programmable number of data to be transferred: up to 65536.

Table 4. DMA implementation

Functional overview STM32G431x6 STM32G431x8 STM32G431xB 28/198 DS12589 Rev 6

3.16 DMA request router (DMAMUX)

When a peripheral indicates a request for DMA transfer by setting its DMA request line, the DMA request is pending until it is served and the corresponding DMA request line is reset. The DMA request router allows to route the DMA control lines between the peripherals and the DMA controllers of the product. An embedded multi-channel DMA request generator can be considered as one of such peripherals. The routing function is ensured by a multi-channel DMA request line multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or synchronously with events on synchronization inputs. For simplicity, the functional description is limited to DMA request lines. The other DMA control lines are not shown in figures or described in the text. The DMA request generator produces DMA requests following events on DMA request trigger inputs.

3.17 Interrupts and events

3.17.1 Nested vectored inte rrupt controller (NVIC)

The STM32G431x6/x8/xB devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and to handle up to 71 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4. The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

3.17.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 39 edge detector lines used to generate interrupt/event requests and to wake-up the system from the Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 86 GPIOs can be connected to the 16 external interrupt lines.

STM32G431x6 STM32G431x8 STM32G431xB Functional overview

3.18 Analog-to-digital converter (ADC)

The device embeds two successive approximation analog-to-digital converters with the following features:

• 12-bit native resolution, with built-in calibration
• 4 Msps maximum conversion rate with full resolution – Down to 41.67 ns sampling time – Increased conversion rate for lower resolution (up to 6.66 Msps for 6-bit resolution)
• One external reference pin is available on all packages, allowing the input voltage range to be independent from the power supply
• Single-ended and differential mode inputs
• Low-power design – Capable of low-current operation at low conversion rate (consumption decreases linearly with speed) – Dual clock domain architecture: ADC speed independent from CPU frequency
• Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions – Each ADC support multiple trigger inputs for synchronization with on-chip timers and external signals – Results stored into a data register or in RAM with DMA controller support – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast context switching – Flexible sample time control – Hardware gain and offset compensation

3.18.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

3.18.2 Internal voltage reference (V REFINT)

3.18.3 V BAT battery voltage monitoring

1. As a consequence, the converted digital value is one third of the VBAT voltage.

3.19 Digital to anal og converter (DAC)

composed of integrated resistor strings and an amplifier in inverting configuration. Table 5. Temperature sensor calibration values Table 6. Internal voltage reference calibration values

• Up to two DAC output channels
• 8-bit or 12-bit output mode
• Buffer offset calibration (factory and user trimming)
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Saw tooth wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• External triggers for conversion
• Sample and hold low-power mode, with internal or external capacitor
• Up to 1 Msps for external output and 15 Msps for internal output The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

3.20 Voltage refe rence buffer (VREFBUF)

• 2.048 V
• 2.5 V
• 2.9 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available.

Figure 3. Voltage reference buffer

3.21 Comparators (COMP)

reference voltage (internal or external), hysteresis.

• External I/O
• DAC output channels
• Internal reference voltage or submultiple (1/4, 1/2, 3/4). All comparators can wake up from Stop mode, generate interrupts and breaks for the timers.

3.22 Operational amplifier (OPAMP)

internal follower routing and PGA capability.

• 13 MHz bandwidth
• Rail-to-rail input/output
• PGA with a non-inverting gain ranging of 2, 4, 8, 16, 32 or 64 or inverting gain ranging

3.23 Random number generator (RNG)

3.24 Timers and watchdogs

general purpose and basic timers. Table 7. Timer feature comparison

3.24.1 Advanced motor cont rol timer (TIM1, TIM8)

• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0-100%)
• One-pulse mode output In debug mode, the advanced motor control timer counter can be frozen and the PWM outputs disabled in order to turn off any power switches driven by these outputs. Many features are shared with the general-purpose TIMx timers (described in Section 3.24.2) using the same architecture, so the advanced motor control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. General- purpose TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 General- purpose TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No

Table 7. Timer feature comparison (continued)

Functional overview STM32G431x6 STM32G431x8 STM32G431xB 34/198 DS12589 Rev 6

3.24.2 General-purpose timers (TIM 2, TIM3, TIM4, TIM15, TIM16,

TIM17) There are up to six synchronizable general-purpose timers embedded in the STM32G431x6/x8/xB devices (see Table 7 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.

• TIM2, TIM3, and TIM4 They are full-featured general-purpose timers: – TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler – TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler. These timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in debug mode. All have independent DMA request generation and support quadrature encoders.
• TIM15, 16 and 17 They are general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. – TIM15 has 2 channels and 1 complementary channel – TIM16 and TIM17 have 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode.

3.24.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases.

STM32G431x6 STM32G431x8 STM32G431xB Functional overview

3.24.4 Low-power timer (LPTIM1)

The devices embed a low-power timer. This timer has an independent clock and are running in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the system from Stop mode. LPTIM1 is active in Stop mode. This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous/ one shot mode
• Selectable software/hardware input trigger
• Selectable clock source – Internal clock sources: L SE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock source running, used by pulse counter application).
• Programmable digital glitch filter
• Encoder mode

3.24.5 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

3.24.6 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.24.7 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0.
• Programmable clock source

Functional overview STM32G431x6 STM32G431x8 STM32G431xB 36/198 DS12589 Rev 6

3.25 Real-time clock (RTC ) and backup registers

The RTC supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy.
• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode.
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC is supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The RTC clock sources can be:
• A 32.768 kHz external crystal (LSE)
• An external resonator or oscillator (LSE)
• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
• The high-speed external clock (HSE) divided by 32. The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode. All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup the device from the low-power modes.

3.26 Tamper and backu p registers (TAMP)

• 16 32-bit backup registers, retained in all low-power modes and also in VBAT mode. They can be used to store sensitive data as their content is protected by an tamper detection circuit. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode.
• Up to three tamper pins for external tamper detection events. The external tamper pins can be configured for edge detection, edge and level, level detection with filtering.
• Five internal tampers events.
• Any tamper detection can generate a RTC timestamp event.
• Any tamper detection erases the backup registers.
• Any tamper detection can generate an interrupt and wake-up the device from all low- power modes.

3.27 Infrared transmitter

based on internal connections between TIM16 and TIM17 as shown in the figure below. sent. The infrared output signal is available on PB9 or PA13. modes can be obtained by programming the two timers output compare channels. Figure 4. Infrared transmitter

3.28 Inter-integrated circuit interface (I2C)

I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

• I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes , multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching
• System management bus (SMBus) specification rev 2.0 compatibility: – Hardware PEC (packet error checking) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert
• Power system management protocol (PMBus TM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming.
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

Table 8. I2C implementation

3.29 Universal synchronous/asynch ronous receiver transmitter

signals, and RS485 driver enable. and an SPI-like communication capability. mode is enabled by software and is disabled by default.

• Start bit detection
• Any received data frame
• A specific programmed data frame
• Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled All USART interfaces can be served by the DMA controller.

Table 9. USART/UART/LPUART features

3.30 Low-power universal asynchr onous receiver transmitter

multiprocessor communication.

• Start bit detection
• Any received data frame
• A specific programmed data frame
• Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. The LPUART interface can be served by the DMA controller.

3.31 Serial peripheral interface (SPI)

support NSS pulse mode, TI mode and hardware CRC calculation. a clock for an external audio component at 256 times the sampling frequency. All SPI interfaces can be served by the DMA controller. Table 9. USART/UART/LPUART features (continued)

3.32 Serial audio interfaces (SAI)

microcontroller and the serial audio protocol.

3.32.1 SAI peripheral supports

• Two independent audio sub-blocks which can be transmitters or receivers with their respective FIFO.
• 8-word integrated FIFOs for each audio sub-block.
• Synchronous or asynchronous mode between the audio sub-blocks.
• Master or slave configuration independent for both audio sub-blocks.
• Clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode.
• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
• Peripheral with large configurability and flexibility allowing to target as example the following audio protocol: I2S, LSB or MSB-justified, PCM/DSP , TDM, AC’97 and SPDIF out.
• Up to 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame.
• Number of bits by frame may be configurable.
• Frame synchronization active level configurable (offset, bit length, level).
• First active bit position in the slot is configurable.
• LSB first or MSB first for data transfer.
• Mute mode.
• Stereo/Mono audio frame capability.
• Communication clock strobing edge configurable (SCK).
• Error flags with associated interrupts if enabled respectively. – Overrun and underrun detection. – Anticipated frame synchronization signal detection in slave mode. – Late frame synchronization signal detection in slave mode. – Codec not ready for the AC’97 mode in reception.
• Interruption sources when enabled: – Errors. – FIFO requests.
• DMA interface with 2 dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub-block.

Table 10. SAI features implementation

3.33 Controller area network (FDCAN1)

version 2.0 part A, B) and CAN FD protocol specification version 1.0. transmit event FIFOs, transmit buffers.

3.34 Universal serial bus (USB)

USB data stream itself (SOF signalization) which allows crystal less operation.

3.35 USB Type-C™ / USB Powe r Delivery controller (UCPD)

Power Delivery Rev. 3.0 specifications.

• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
• “Dead battery” support
• USB Power Delivery message transmission and reception
• FRS (fast role swap) support Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X FIFO size X (8 word) SPDIF X 1. X: supported.

Table 10. SAI features implementation (continued)

STM32G431x6 STM32G431x8 STM32G431xB Functional overview The digital controller handles notably:

• USB Type-C level detection with de-bounce, generating interrupts
• FRS detection, generating an interrupt
• Byte-level interface for USB Power Delivery payload, generating interrupts (DMA compatible)
• USB Power Delivery timing dividers (including a clock pre-scaler)
• CRC generation/checking
• 4b5b encode/decode
• Ordered sets (with a programmable ordered set mask at receive)
• Frequency recovery in receiver during preamble The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages and FRS signaling.

3.36 Clock recover y system (CRS)

The devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.

3.37 Development support

3.37.1 Serial wire JT AG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP .

3.37.2 Embedded trace macrocell™

The Arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32G431x6/x8/xB devices through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded trace macrocell operates with third party debugger software tools.

4 Pinouts and pin description

4.1 UFQFPN32 pinout description

Figure 5. STM32G431x6/x8/xB UFQFPN32 pinout

1. The above figure shows the package top view.

4.2 LQFP32 pinout description

Figure 6. STM32G431x6/x8/xB LQFP32 pinout

1. The above figure shows the package top view.

4.3 UFQFPN48 pinout description

Figure 7. STM32G431x6/x8/xB UFQFPN48 pinout

1. The above figure shows the package top view.
2. VSS pads are connected to the exposed pad.

4.4 LQFP48 pinout description

Figure 8. STM32G431x6/x8/xB LQFP48 pinout

1. The above figure shows the package top view.

4.5 WLCSP49 ballout description

Figure 9. STM32G431x6/x8/xB WLCSP49 ballout

1. The above figure shows the package top view.

4.6 LQFP64 pinout description

Figure 10. STM32G431x6/x8/xB LQFP64 pinout

1. The above figure shows the package top view.

4.7 UFBGA64 ballout description

Figure 11. STM32G431x6/x8/xB UFBGA64 ballout

1. The above figure shows the package top view.

4.8 LQFP80 pinout description

Figure 12. STM32G431x6/x8/xB LQFP80 pinout

1. The above figure shows the package top view.

60 PA12

59 PA11

58 PA10

63 PA13

62 VDD

61 VSS

4.9 LQFP100 pinout description

Figure 13. STM32G431x6/x8/xB LQFP100 pinout

1. The above figure shows the package top view.

4.10 Pin definition

Table 11. Legend/abbreviations used in the pinout table

1. The related I/O structures in Table 12 are: FT_a, FT_fa, TT_a.
2. The related I/O structures in Table 12 are: FT_f, FT_fa.
3. The related I/O structures in Table 12 are FT_u.

Table 12. STM32G431x6/x8/xB pin definition(1)

Table 12. STM32G431x6/x8/xB pin definition(1) (continued)

1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Si nce the switch only sinks a limited amount of current (3

• These GPIOs must not be used as current sources (for instance to drive an LED).

1. After a Backup domain power-up, PC13, PC14 and PC15 oper ate as GPIOs. Their function then depends on the content of
2. PG10-NRST pin is FT tolerant if it is configured as PG10 GPIO by option bytes except for the startup time until option bytes
3. After reset, these pins are configur ed as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4

pins and the internal pull-down on PA14 pin are activated.

1. After reset, a pull-down resistor (Rd = 5.1k Ω from UCPD peripheral) can be activated on PB6, PB4 (UCPD1_CC1,

battery disable) in the PWR_CR3 register.

1. It is recommended to set PB8 in another mode than analog mode after startup to limit consumption if the pin is left

4.11 Alternate functions

Table 13. Alternate function

Table 13. Alternate function (continued)

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

the selected temperature range). mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

are given only as design guidelines and are not tested. error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 14.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 15. Figure 14. Pin loading conditions Figure 15. Pin input voltage

5.1.6 Power supply scheme

Figure 16. Power supply scheme

5.1.7 Current consumption measurement

Figure 17. Current consumption measurement including the current supplying VDD, VDDA and VBAT.

5.2 Absolute maximum ratings

Table 14. Voltage characteristics(1)

1. All main power (V DD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external

power supply, in the permitted range.

1. V IN maximum must always be respected. Refer to Table 15: Current characteristics for the maximum

allowed injected current values.

1. This formula has to be applied only on the power suppl ies related to the IO structure described in the pin
2. To sustain a voltage higher than 4 V the intern al pull-up/pull-down resistors must be disabled.

Table 15. Current characteristics

1. All main power (V DD, VDDA, VBAT) and ground (VSS, VSSA) pins must always be connected to the external

power supplies, in the permitted range.

1. This current consumption must be correctly distri buted over all I/Os and control pins. The total output
2. Positive injection (when V IN > VDD) is not possible on these I/Os and does not occur for input voltages

lower than the specified maximum value.

1. A negative injection is induced by VIN < VSS. IIN J(PIN) must never be exceeded. Refer also to Table 14:

Voltage characteristics for the minimum allowed input voltage values.

1. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of

the negative injected currents (instantaneous values). Table 16. Thermal characteristics

5.3 Operating conditions

5.3.1 General operating conditions

Table 17. General operating conditions

5.5 V)(2)(3)

appropriate thermal resistance and package. selected thermal resistance.

1. When RESET is released func tionality is guaranteed down to VBOR0 Min.
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.

Maximum I/O input voltage is the smallest value between MIN(VDD, VDDA)+3.6 V and 5.5V.

1. For operation with voltage higher than Min (V DD, VDDA) +0.3 V, the internal Pull-up and Pull-Down resistors must be
2. In low-power dissipation state, T A can be extended to this range as long as TJ does not exceed TJmax (see Section 6.10:

5.3.2 Operating conditions at power-up / power-down

temperature condition summarized in Table 17.

5.3.3 Embedded reset and power control block characteristics

temperature conditions summarized in Table 17: General operating conditions. Table 18. Operating conditions at power-up / power-down Table 19. Embedded reset and power control block characteristics

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
2. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply

current characteristics tables. Table 19. Embedded reset and power control block characteristics (continued)

5.3.4 Embedded voltage reference

Table 20. Embedded internal voltage reference

1. The shortest sampling time is determined in the application by multiple iterations.

Figure 18. VREFINT versus temperature

5.3.5 Supply current characteristics

• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “number of wait states according to CPU clock (HCLK) frequency” available in the reference manual RM0440 "STM32G4 Series advanced Arm ®-based 32-bit MCUs").
• When the peripherals are enabled fPCLK = fHCLK
• The voltage scaling Range 1 is adjusted to fHCLK frequency as follows: – Voltage Range 1 Boost mode for 150 MHz < f HCLK ≤ 170 MHz – Voltage Range 1 Normal mode for 26 MHz < f HCLK ≤ 150 MHz The parameters given in Table 21 to Table 24 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 17: General operating conditions. MSv40169V2 1.185 1.19 1.195 1.2 1.205 1.21 1.215 1.22 1.225 1.23 1.235 -40 -20 0 20 40 60 80 100 120 V Mean Min Max

48 MHz included,

2 MHz 350 525 990 1600 2650 970 2200 3900 6700 11000

1 MHz 255 410 860 1500 2550 830 2100 3800 6600 11000

250 KHz 145 300 750 1400 2450 690 1900 3700 6500 11000

2 MHz 865 1050 1500 2150 3200 1600 2800 4500 7600 12000

1 MHz 820 965 1400 2050 3100 1500 2700 4400 7400 12000

250 KHz 725 875 1300 1950 3000 1400 2600 4400 7400 12000

62.5 KHz 685 860 1300 1900 2950 1300 2600 4400 7400 12000

78/198 DS12589 Rev 6 Table 22. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 Symbol Parameter Condition fHCLK Typ Max Unit - Voltage scaling 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C IDD (Run) Supply current in Run mode fHCLK = fHSE up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable Range 2 mA Range 1 Boost mode Range 1

2 MHz 350 495 965 1600 2650 900 2100 3900 6700 12000

1 MHz 210 370 845 1500 2550 780 2000 3800 6600 11000

250 KHz 115 275 755 1400 2450 680 1900 3700 6800 12000

2 MHz 850 1000 1500 2100 3150 1500 2700 4500 7500 12000

1 MHz 770 900 1400 2000 3050 1500 2700 4500 7600 13000

250 KHz 720 840 1300 1950 3000 1400 2600 4400 7300 12000

62.5 KHz 665 830 1300 1900 2950 1400 2600 4400 7300 12000

Table 23. Typical current consumption in Run and Low-power run modes, with different codes

48 MHz all peripherals

Table 24. Typical current consumption in Run and Low-power run modes, with different codes

Table 25. Typical current consumption in Run and Low-power run modes, with different codes

Table 26. Typical current consumption in Run and Low-power run modes, with different codes

Table 27. Current consumption in Sleep and Low-power sleep mode Flash ON

2 MHz 180 335 810 1450 2500 1600 2900 4600 7700 13000

1 MHz 135 300 770 1400 2450 1200 2400 4100 7100 12000

250 KHz 115 265 740 1350 2400 670 2000 3600 6300 11000

2 MHz 730 875 1350 1950 3000 1400 2600 4300 7200 12000

1 MHz 675 830 1300 1950 3000 1400 2600 4300 7200 12000

250 KHz 655 820 1300 1950 3000 1400 2600 4300 7200 12000

62.5 KHz 680 850 1300 1950 3000 1400 2600 4300 7200 12000

Table 27. Current consumption in Sleep and Low-power sleep mode Flash ON (continued) Table 28. Current consumption in low-power sleep modes, Flash in power-down

2 MHz 175 290 805 1450 2500 750 2000 3700 6400 11000

1 MHz 125 280 765 1400 2450 700 2000 3700 6400 11000

250 KHz 105 240 735 1350 2400 670 1900 3700 6400 11000

62.5 KHz 105 245 725 1350 2400 660 1900 3700 6400 11000

2 MHz 670 830 1350 1950 3000 1400 2600 4300 7200 12000

1 MHz 655 825 1300 1950 3000 1400 2600 4300 7200 12000

250 KHz 635 825 1300 1900 2950 1400 2600 4300 7100 12000

62.5 KHz 640 840 1300 1900 2950 1200 2200 3700 6200 11000

Table 29. Current consumption in Stop 1 mode

1. Guaranteed by characterization re sults, unless otherwise specified.

Table 30. Current consumption in Stop 0 mode

1.8 V 150 280 680 1200 2100 560 1600 4000 7100 12000

2.4 V 150 280 680 1200 2100 560 1600 4000 7100 12000

3 V 155 280 685 1200 2150 560 1600 4000 7100 12000

3.6 V 155 285 685 1200 2150 560 1600 4000 7200 12000

1. Guaranteed by characterization re sults, unless otherwise specified.

Table 31. Current consumption in Standby mode

2.4 V 100 240 1000 2600 6450 250 1100 3600 9000 23000

3 V 120 280 1200 3050 7400 280 1300 4200 11000 26000

3.6 V 175 385 1550 3800 9200 370 1500 4900 12000 30000

1.8 V 490 605 1300 2650 5950 670 1400 3600 8200 20000

2.4 V 630 765 1550 3100 6950 850 1700 4200 9400 23000

3 V 785 955 1850 3700 8050 1100 1900 4900 11000 26000

3.6 V 1000 1200 2350 4600 9950 1400 2400 5800 13000 30000

1.8 V 360 470 1100 2450 5750 - - - - -

2.4 V 480 625 1400 3000 6800 - - - - -

3 V 825 1100 2200 4200 8700 - - - - -

3.6 V 2550 3400 5250 8000 13500 - - - - -

1.8 V 355 490 990 2150 4800 - - - - -

2.4 V 455 605 1200 2550 5550 - - - - -

3 V 595 775 1450 3100 6400 - - - - -

3.6 V 810 1200 2050 3900 7750 - - - - -

1.8 V 218 530 1680 3500 6900 - - - - -

2.4 V 220 525 1700 3500 7050 - - - - -

3 V 215 530 1650 3500 7100 - - - - -

3.6 V 220 545 1700 3600 6800 - - - - -

Table 31. Current consumption in Standby mode (continued)

1. Guaranteed by characterization re sults, unless otherwise specified.
2. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IIDD_ALL(Standby
3. Wakeup with code execution from Fl ash. Average value given for a typical wakeup time as specified in Table 35: Low-power mode wakeup timings.

Table 32. Current consumption in Shutdown mode

1.8 V 280 355 800 1800 4500 - - - - -

2.4 V 400 500 1050 2250 5350 - - - - -

3 V 745 985 1850 3400 7100 - - - - -

3.6 V 2450 3250 4850 7100 11500 - - - - -

1.8 V 275 375 775 1650 - - - - - -

2.4 V 375 495 950 2050 - - - - - -

3 V 515 640 1200 2550 - - - - - -

3.6 V 710 925 1750 3300 - - - - - -

16 MHz

1. Guaranteed by characterization re sults, unless otherwise specified.
2. Wakeup with code execution from Flash. Average val ue given for a typical wakeup time as specified in Table 35: Low-power mode wakeup timings.

Table 32. Current consumption in Shutdown mode (continued)

Table 33. Current consumption in VBAT mode

3 V 4 8 0 5 4 5 7 1 0 1 0 5 0 1 2 5 0 -----

1. Guaranteed by characterization re sults, unless otherwise specified.

I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 53: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC, OPAMP, COMP input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This is done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 35: Low-power mode wakeup timings), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where I SW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. ISW VDDIOx fSW C××=

• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions: – when the peripheral is clocked on – when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 14: Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in

Table 34. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. Table 34. Peripheral current consumption

Table 34. Peripheral current consumption (continued)

The device goes in low-power mode after the WFE (Wait For Event) instruction. Table 35. Low-power mode wakeup timings(1)

1. Guaranteed by characterization results.
2. Characterization results for temperature range from 0°C to 125°C.
3. Time until REGLPF flag is cleared in PWR_SR2.

5.3.7 External clock source characteristics

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. Table 36. Regulator modes transition times(1)

1. Guaranteed by characterization results.
2. Time until VOSF flag is cleared in PWR_SR2.

Table 37. Wakeup time using USART/LPUART(1) Table 38. High-speed external user clock characteristics(1)

(frequency, package, accuracy). Table 40. HSE oscillator characteristics(1)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
3. t SU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

design guide for ST microcontrollers” available from the ST website www.st.com. Figure 21. Typical application with an 8 MHz crystal

1. R EXT value depends on the crystal characteristics.

8 MHz

design guide for ST microcontrollers” available from the ST website www.st.com. Figure 22. Typical application with a 32.768 kHz crystal Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator

design guide for ST microcontrollers”.

1. t SU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized

5.3.8 Internal clock source characteristics

conditions. The provided curves are characterization results, not tested in production. Table 42. HSI16 oscillator characteristics(1)

1. Guaranteed by characterization results.

Figure 23. HSI16 frequency versus temperature Table 43. HSI48 oscillator characteristics(1)

Figure 24. HSI48 frequency versus temperature

1. V DD = 3 V, TA = –40 to 125°C unless otherwise specified.
2. Guaranteed by characterization results.
3. Jitter measurement are performed without clock source activated in parallel.

Table 44. LSI oscillator characteristics(1) Table 43. HSI48 oscillator characteristics(1) (continued)

5.3.9 PLL characteristics

VDD supply voltage conditions summarized in Table 17: General operating conditions.

1. Guaranteed by characterization results.

Table 44. LSI oscillator characteristics(1) (continued) Table 45. PLL characteristics(1)

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock

5.3.10 Flash memory characteristics

Table 46. Flash memory characteristics(1) Table 47. Flash memory endurance and data retention

1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.

5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization. While a simple application is executed on the device (toggling 2 LEDs through I/O ports).

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V DD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 48. They are based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

Table 48. EMS characteristics

to prevent unrecoverable errors occurring (see application note AN1015). IEC 61967-2 standard which specifies the test board and the pin loading.

5.3.12 Electrical sens itivity characteristics

stressed in order to determine its performance in terms of electrical sensitivity. conforms to the ANSI/JEDEC standard. Table 49. EMI characteristics

8 MHz / 170 MHz

0.1 MHz to 30 MHz 3

30 MHz to 130 MHz -2

130 MHz to 1 GHz 25

1 GHz to 2 GHz 18

Table 50. ESD absolute maximum ratings

1. Guaranteed by characterization results.

• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78E IC latch-up standard.

5.3.13 I/O current in jection characteristics

sample basis during device characterization. the I/O pin, one at a time, the device is checked for functional failures. oscillator frequency deviation). The characterization results are given in Table 52. leakage current is caused by positive injection. Table 51. Electrical sensitivities Table 52. I/O current injection susceptibility

1. Guaranteed by characterization.

5.3.14 I/O port characteristics

I/Os are designed as CMOS- and TTL-compliant. Table 53. I/O static characteristics

1. Refer to Figure 25: I/O input characteristics

Figure 25. I/O input characteristics source up to ± 20 mA (with a relaxed VOL/VOH).

1. Data based on characterization results, not tested in production
2. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula:

Total_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).

1. Pull-up and pull-down resistors are des igned with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

• The sum of the currents sourced by all the I/Os on VDD, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 14: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see Table 14: Voltage characteristics). Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 17: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified). Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 26 and Table 55, respectively. Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 17: General operating conditions.

Table 54. Output voltage characteristics(1)(2)

1. The I IO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 14:

respect the absolute maximum ratings ΣIIO.

1. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

Table 55. I/O (except FT_c) AC characteristics(1) (2)

1. The I/O speed is configured using the OSPEEDRy[1 :0] bits. The Fm+ mode is configured in the

based 32-bit MCUs" for a description of GPIO Port configuration register.

1. This value represented the I/O capability but maximum system frequency is 170 MHz.
2. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
3. The maximum frequency is defined with the following conditions:

Table 56. I/O FT_c AC characteristics(1) (2)

1. The I/O speed is configured using the OSPEEDRy[1 :0] bits. The Fm+ mode is configured in the

based 32-bit MCUs" for a description of GPIO Port configuration register. Table 55. I/O (except FT_c) AC characteristics(1) (2) (continued)

Figure 26. I/O AC characteristics definition(1)

1. Refer to Table 55: I/O (except FT_c) AC characteristics.

5.3.15 NRST pin characteristics

Table 17: General operating conditions. when loaded by the specified capacitance. Table 57. NRST pin characteristics(1)

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

the series resistance is minimal (~10% order).

1.71 V ≤ VDD

Figure 27. Recommended NRST pin protection

1. The reset network protects t he device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V IL(NRST) max level specified in

Table 57: NRST pin characteristics. Otherwise the reset is not taken into account by the device.

1. The external capacitor on NRST must be placed as close as possible to the device.

5.3.16 Extended interrupt and event cont roller input (EXTI) characteristics

detected by the event controller.

5.3.17 Analog switches booster

Table 58. EXTI input characteristics(1) Table 59. Analog switches booster characteristics(1)

5.3.18 Analog-to-digital converter characteristics

conditions summarized in Table 17: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 60. ADC characteristics(1) (2)

Table 60. ADC characteristics(1) (2) (continued)

1. The I/O analog switch voltage booster is enabled when V DDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4V). It is disabled when VDDA ≥ 2.4 V. 3. VREF+ can be internally connected to VDDA, depending on the package. Refer to Section 4: Pinouts and pin description for further details. 4. The maximum value of RAIN can be found in Table 61: Maximum ADC RAIN.

The maximum value of RAIN can be found in Table 61: Maximum ADC RAIN. Table 61. Maximum ADC RAIN

1. Guaranteed by design. 2. The I/O analog switch voltage booster is enabled when V DDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when VDDA < 2.4V). It is disabled when VDDA ≥ 2.4 V. 3. Fast channels are: ADCx_IN1 to ADCx_IN5. 4. Slow channels are: all ADC inputs except the fast channels.

Table 62. ADC accuracy - limited test conditions 1(1)(2)(3)

1. Evaluated by characteriza tion – Not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negativ e current on any analog input pins should be avoided as this

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

1. The I/O analog switch voltage booster is enabled when V

Table 62. ADC accuracy - limited test conditions 1(1)(2)(3) (continued)

Table 63. ADC accuracy - limited test conditions 2(1)(2)(3)

1. Evaluated by characterization – Not tested in production.
2. ADC DC accuracy values are meas ured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negativ e current on any analog input pins should be avoided as this

Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

1. The I/O analog switch voltage booster is enabled when V DDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

Table 63. ADC accuracy - limited test conditions 2(1)(2)(3) (continued)

Table 64. ADC accuracy - limited test conditions 3(1)(2)(3)

60 MHz,

1.62 V ≤ V

1. Evaluated by characterizati on – Not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided

recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

1. The I/O analog switch voltage booster is enabled when V DDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when

Table 64. ADC accuracy - limited test conditions 3(1)(2)(3) (continued)

Table 65. ADC accuracy (Multiple ADCs operation) - limited test conditions 1(1)(2)(3)

1. Data based on characterization result, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided

recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

1. The I/O analog switch voltage booster is enabled when V

Table 66. ADC accuracy (Multiple ADCs operation) - limited test conditions 2(1)(2)(3)

1. Data based on characterization result, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided

recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

1. The I/O analog switch voltage booster is enabled when V

Table 67. ADC accuracy (Multiple ADCs operation) - limited test conditions 3(1)(2)(3)

1. Data based on characterization result, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided

recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

1. The I/O analog switch voltage booster is enabled when V

Figure 28. ADC accuracy characteristics Figure 29. Typical connection diagram when using the ADC with FT/TT pins

1. Refer to Table 60: ADC characteristics for the values of RAIN and CADC.
2. C parasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced.

1. Refer to Table 53: I/O static characteristics for the values of Ilkg.
2. Refer to Figure 16: Power supply scheme.

Power supply decoupling must be performed as shown in Figure 16: Power supply scheme. close as possible to the chip.

1 LSB ideal

5.3.19 Digital-to-Analog converter characteristics

Table 68. DAC 1MSPS characteristics(1)

Table 68. DAC 1MSPS characteristics(1) (continued)

Figure 30. 12-bit buffered / non-buffered DAC

1. The DAC integrates an output buffer to reduce th e output impedance and to drive external loads directly
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 53: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to the reference manual RM0440 "STM32G4

Series advanced Arm®-based 32-bit MCUs" for more details.

Table 69. DAC 1MSPS accuracy(1)

1. Difference between two consecutive codes - 1 LSB.
2. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
3. Difference between the value measured at Code (0x001) and the ideal value.
4. Difference between ideal slope of the transfer functi on and measured slope computed from code 0x000 and 0xFFF when

REF+ – 0.2) V when buffer is ON. Table 69. DAC 1MSPS accuracy(1) (continued) Table 70. DAC 15MSPS characteristics(1)

1. In buffered mode, the output can overshoot above the fi nal value for low input code (starting from min value).
2. Worst case consumpt ion is at code 0x800.

Table 70. DAC 15MSPS characteristics(1) (continued)

Table 71. DAC 15MSPS accuracy(1)

1. Difference between two c onsecutive codes - 1 LSB.
2. Difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095.

5.3.20 Voltage referenc e buffer characteristics

Table 72. VREFBUF characteristics(1)

Figure 31. VREFOUT_TEMP in case VRS = 00

1. Guaranteed by design, unl ess otherwise specified.
2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which follows (V DDA - drop
3. Line regulation is given for overal l supply variation, in normal mode.
4. Tcoeff_vrefint refer to Tcoeff parameter in the embedded voltage reference section.
5. The capacitive load must include a 100 nF low ESR c apacitor in order to cut-off the high frequency noise.
6. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the V

Table 72. VREFBUF characteristics(1) (continued)

5.3.21 Comparator characteristics

Table 73. COMP characteristics(1)

1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 20: Embedded internal voltage reference.
3. Guaranteed by characterization results.
4. Typical value (3V) is an average for all comparators propagation delay.

5.3.22 Operational ampl ifiers characteristics

Table 74. OPAMP characteristics(1) (2) Iload = max or Rload = min Input at VDDA. (3) Low saturation voltage Iload = max or Rload = min Input at 0.

current See lleak parameter in Table 53: I/O static characteristics for given pin. Table 74. OPAMP characteristics(1) (2) (continued)

Figure 34. OPAMP noise density @ 25°C

1. Guaranteed by design, unless otherwise specified.
2. Data guaranteed on normal and high speed mode unless otherwise specified.
3. Guaranteed by characterization results.
4. Valid also for inverting gain configuration with external bias.
5. R2 is the internal resistance between OPAMP output and OPAM P inverting input. R1 is the internal resistance between

5.3.23 Temperature sensor characteristics

5.3.24 V BAT monitoring characteristics

Table 75. TS characteristics

1. Measured at V DDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer

to Table 5: Temperature sensor calibration values.

1. Continuous mode means RUN mode or Temperature Sensor ON.

Table 76. VBAT monitoring characteristics(1) Table 77. VBAT charging characteristics

5.3.25 Timer characteristics

The parameters given in the following tables are guaranteed by design. function characteristics (output compare, input capture, external clock, PWM output). Table 78. TIMx(1) characteristics(2)

1. TIMx , is used as a general term in which x stands for 1,2,3,4,6,7,8,15,16, or 17.

5.3.26 Communication interfaces characteristics

• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to reference manual RM0440 "STM32G4 Series advanced Arm®-based 32-bit MCUs") and when the I2CCLK frequency is greater than the minimum shown in the table below.

Table 79. IWDG min/max timeout period at 32 kHz (LSI)

1. The exact timings still depend on the phasing of the APB in terface clock versus the LSI clock so that there

is always a full RC period of uncertainty. Table 80. WWDG min/max timeout value at 170 MHz (PCLK)(1)

• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present.
• The 20mA output drive requirement in Fast-mode Plus is supported partially. This limits the maximum load Cload supported in Fm+, which is given by these formulas: –t r(SDA/SCL)=0.8473 x Rp x Cload –R p(min)= (VDD - VOL(max)) / IOL(max) Where Rp is the I2C lines pull-up. Refer to Section 5.3.14: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 82 below for the analog filter characteristics: SPI characteristics Unless otherwise specified, the parameters given in Table 83 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 17: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 x VDD Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 81. Minimum I2CCLK frequency in all I2C modes Table 82. I2C analog filter characteristics(1)

1. Spikes with widths below t AF(min) are filtered.
2. Spikes with widths above t AF(max) are not filtered

Table 83. SPI characteristics(1)

Figure 35. SPI timing diagram - slave mode and CPHA = 0

1. Guaranteed by characterization results.
2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into

master having tsu(MI) = 0 while Duty(SCK) = 50%. Table 83. SPI characteristics(1) (continued)

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C=30pF
• Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CK,SD,WS). Note: Refer to the reference manual RM0440 "STM32G4 Series advanced Arm ®-based 32-bit MCUs" I2S section for more details about the sampling frequency (Fs), fMCK, fCK, DCK values reflect only the digital peripheral behavior, source clock precision might slightly change the values DCK depends mainly on ODD bit value. Digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max (I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max supported for each mode/condition.

Table 84. I2S characteristics(1)

1. Guaranteed by characterization re sults, not tested in production.
2. 256xFs maximum is 49.152 MHz.

Unless otherwise specified, the parameters given in Table 85 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage condi- tions summarized inTable 17: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 x VDD Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CK,SD,FS).

Table 85. SAI characteristics(1)

USB-IF certified (for Full-speed device operation).

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C=30 pF
• Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, RX for USART).

Table 86. USB electrical characteristics(1)

1. TA = -40 to 125 °C unless otherwise specified.
2. The device USB functionality is ensured down to 2.7 V but not th e full USB electrical characteristics, which are degraded in

the 2.7-to-3.0 V voltage range.

1. No external termination series resistors are required on USB_PD (D+) and USB_DM (D-); the matching impedance is

already included in the embedded driver. Table 87. USART electrical characteristics(1)

5.3.27 UCPD characteristics

1. Based on characterization, not tested in production.

Table 87. USART electrical characteristics(1) (continued) Table 88. UCPD characteristics

6 Package information

specifications, grade definitions and product status are available at: www.st.com.

6.1 UFQFPN32 package information

This UFQFPN is a 32-pin, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package. Figure 40. UFQFPN32 - Outline

1. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
2. There is an exposed die pad on the underside of t he UFQFPN package. It is recommended to connect and

solder this backside pad to PCB ground.

Figure 41. UFQFPN32 - Recommended footprint

1. Dimensions are expr essed in millimeters.

Table 89. UFQFPN32 - Mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 42. UFQFPN32 top view example

1. Parts marked as ES or E or accompanied by an engin eering sample notification letter are not yet qualified

samples to run a qualification activity.

6.2 LQFP32 package information

This LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package. Figure 43. LQFP32 - Outline

Figure 44. LQFP32 - Recommended footprint

1. Dimensions are expr essed in millimeters.

Table 90. LQFP32 - Mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 45. LQFP32 top view example

1. Parts marked as ES or E or accompanied by an engin eering sample notification letter are not yet qualified

samples to run a qualification activity.

6.3 UFQFPN48 package information

This UFQFPN is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package. Figure 46. UFQFPN48 - Outline

1. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
2. There is an exposed die pad on the underside of the UFQFPN48 package. It is recommended to connect

and solder this back-side pad to PCB ground.

Figure 47. UFQFPN48 - Recommended footprint

1. Dimensions are expr essed in millimeters.

Table 91. UFQFPN48 - Mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 48. UFQFPN48 top view example

1. Parts marked as ES or E or accompanied by an engin eering sample notification letter are not yet qualified

samples to run a qualification activity.

6.4 LQFP48 package information

This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package. Figure 49. LQFP48 - Outline

Table 92. LQFP48 - Mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 50. LQFP48 - Recommended footprint

1. Dimensions are expr essed in millimeters.

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 51. LQFP48 top view example

1. Parts marked as ES or E or accompanied by an engin eering sample notification letter are not yet qualified

samples to run a qualification activity.

6.5 WLCSP49 package information

This WLCSP49 is a 49-ball, 3.15 x 3.13 mm, 0.4 mm pitch, wafer level chip scale package. Figure 52. WLCSP49 - Outline

1. Dimension is measured at the maximum bum p diameter parallel to primary datum Z.
2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
3. Bump position designation per JESD 95-1, SPP-010.

Table 93. WLCSP49 - Mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal

and tolerances values of A1 and A2.

1. Back side coating. Nominal dimens ion is rounded to the 3rd decimal place resulting from process capabiliy.
2. Dimension is measured at the maximum bum p diameter parallel to primary datum Z.
3. Calculated dimensions are rounded to the 3rd decimal place

Figure 53. WLCSP49 - Recommended footprint

1. Dimensions are expr essed in millimeters.

Table 94. WLCSP49 - Recommended PCB design rules

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 54. WLCSP49 top view example

1. Parts marked as ES or E or accompanied by an engin eering sample notification letter are not yet qualified

samples to run a qualification activity.

6.6 LQFP64 package information

This LQFP is a 64-pin, 10 x 10 mm low-profile quad flat package. Figure 55. LQFP64 - Outline Table 95. LQFP64 - Mechanical data

Figure 56. LQFP64 - Recommended footprint

1. Dimensions are expr essed in millimeters.
2. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 95. LQFP64 - Mechanical data (continued)

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 57. LQFP64 top view example

1. Parts marked as ES or E or accompanied by an engin eering sample notification letter are not yet qualified

samples to run a qualification activity.

6.7 UFBGA64 package information

Figure 58. UFBGA64 - Outline Table 96. UFBGA64 - Mechanical data

Figure 59. UFBGA64 - Recommended footprint

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 96. UFBGA64 - Mechanical data (continued) Table 97. UFBGA64 - Recommended PCB design rules (0.5 mm pitch BGA)

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 60. UFBGA64 top view example

1. Parts marked as ES or E or accompanied by an engin eering sample notification letter are not yet qualified

samples to run a qualification activity.

6.8 LQFP80 package information

This LQFP is a 80-pin, 12 x 12 mm low-profile quad flat package. Figure 61. LQFP80 - Outline Table 98. LQFP80 - Mechanical data

Figure 62. LQFP80 - Recommended footprint

1. Dimensions are expr essed in millimeters.
2. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 98. LQFP80 - Mechanical data (continued)

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 63. LQFP80 top view example

1. Parts marked as ES or E or accompanied by an engin eering sample notification letter are not yet qualified

samples to run a qualification activity.

6.9 LQFP100 pac kage information

This LQFP is a 100-pin, 14 x 14 mm low-profile quad flat package. Figure 64. LQFP100 - Outline Table 99. LQPF100 - Mechanical data

Figure 65. LQFP100 - Recommended footprint

1. Dimensions are expr essed in millimeters.
2. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 99. LQPF100 - Mechanical data (continued)

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 66. LQFP100 top view example

1. Parts marked as ES or E or accompanied by an engin eering sample notification letter are not yet qualified

samples to run a qualification activity.

6.10 Thermal characteristics

• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Table 100. Package thermal characteristics

6.10.1 Reference document

1. Thermal resistance junction-case where the case is the bottom thermal pad on the UFQFPN package.

Table 100. Package thermal characteristics (continued)

6.10.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 7: Ordering information. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32G431xB at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range is best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Using the values obtained in TJmax is calculated as follows: – For LQFP100, 42 °C/W T Jmax = 82 °C + (42 °C/W × 447 mW) = 82 °C + 18.774 °C = 100.774 °C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Section 7: Ordering information. In this case, parts must be ordered at least with the temperature range suffix 6 (see Section 7: Ordering information). Note: With this given P Dmax we can find the TAmax allowed for a given device temperature range (order code suffix 6 or 7). Suffix 6: TAmax = TJmax - (42°C/W × 447 mW) = 105-18.774 = 86.226 °C Suffix 3: TAmax = TJmax - (42°C/W × 447 mW) = 130-18.774 = 111.226 °C Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range.

STM32G431x6 STM32G431x8 STM32G431xB Package information 193 Assuming the following application conditions: Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA × 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW Using the values obtained in TJmax is calculated as follows: – For LQFP100, 42 °C/W T Jmax = 100 °C + (42 °C/W × 134 mW) = 100 °C + 5.628 °C = 105.628 °C This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 3 (see Section 7: Ordering information) unless we reduce the power dissipation in order to be able to use suffix 6 parts.

7 Ordering information

aspect of this device, contact the nearest ST sales office. Table 101. Ordering information scheme

8 Revision history

Table 102. Document revision history 10-May-2019 1 Initial release. and peripheral counts removing “-40 to 105°C (+ 125°C junction)”. – Figure 1: STM32G431x6/x8/xB block diagram with 170 MHz. – Section 3.5: Embedded SRAM. – Section 3.20: Voltage reference buffer (VREFBUF). – Table 3: STM32G431x6/x8/xB peripherals interconnect matrix. – Table 17: General operating conditions. – Table 34: Peripheral current consumption. – Table 60: ADC characteristics. – Table 83: SPI characteristics. – Table 100: Package thermal characteristics. – Table 101: Ordering information scheme. – Section 6: Package information.

– Section 3.5: Embedded SRAM. – Table 12: STM32G431x6/x8/xB pin definition. – Figure 11: STM32G431x6/x8/xB UFBGA64 ballout. Table 31 Table 32 max current consumptions. – Table 35: Low-power mode wakeup timings adding note. and IDDA(DAC) characteristics. – Table 73: COMP characteristics IDDA(COMP). – Table 74: OPAMP characteristics PSRR. – Table 76: VBAT monitoring characteristics. – Table 100: Package thermal characteristics. – Internal voltage reference buffer (VREFBUF) at 2.9 V. with different codes running from Flash, ART disable table. – Section 3.11.4: Low-power modes. – Table 29: Current consumption in Stop 1 mode. – Table 30: Current consumption in Stop 0 mode. – Table 31: Current consumption in Standby mode. – Table 32: Current consumption in Shutdown mode. Table 102. Document revision history (continued)