32G071CBT6

STM32G071X8_V01 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Introduction
• 2 Description
• 3 Functional overview
• 3.1 Arm ® Cortex®-M0+ core with MPU
• 3.2 Memory protection unit
• 3.3 Embedded Flash memory
• 3.3.1 Securable area
• 3.4 Embedded SRAM
• 3.5 Boot modes
• 3.6 Cyclic redundancy check calculation unit (CRC)
• 3.7 Power supply management
• 3.7.1 Power supply schemes
• 3.7.2 Power supply supervisor
• 3.7.3 Voltage regulator
• 3.7.4 Low-power modes
• 3.7.5 Reset mode
• 3.7.6 VBAT operation
• 3.8 Interconnect of peripherals
• 3.9 Clocks and startup
• 3.10 General-purpose inputs/outputs (GPIOs)
• 3.11 Direct memory access controller (DMA)
• 3.12 DMA request multiplexer (DMAMUX)
• 3.13 Interrupts and events
• 3.13.1 Nested vectored interrupt controller (NVIC)
• 3.13.2 Extended interrupt/event controller (EXTI)
• 3.14 Analog-to-digital converter (ADC)
• 3.14.1 Temperature sensor
• 3.14.2 Internal volt age reference (VREFINT)
• 3.14.3 V BAT battery voltage monitoring
• 3.15 Digital-to-analog converter (DAC)
• 3.16 Voltage reference buffer (VREFBUF)

Datasheet sections

• 5.3.6 Wakeup time from low-power modes and voltage scaling
• 5.3.7 External clock source characteristics
• 5.3.8 Internal clock source charac teristics
• 5.3.9 PLL characteristics
• 5.3.10 Flash memory characteristics
• 5.3.11 EMC characteristics
• 5.3.12 Electrical sensitivity characteristics
• 5.3.13 I/O current injection characteristics
• 5.3.14 I/O port characteristics
• 5.3.15 NRST input characteristics
• 5.3.16 Analog switch booster
• 5.3.17 Analog-to-digital converter characteristics
• 5.3.18 Digital-to-analog converter characteristics
• 5.3.19 Voltage reference buffer characteristics
• 5.3.20 Comparator characteristics
• 5.3.21 Temperature sensor characteristics
• 5.3.23 Timer characteristics
• 5.3.24 Characteristics of communication interfac es
• 5.3.25 UCPD characteristics
• 6 Package information
• 6.1 WLCSP25 package information
• 6.2 UFQFPN28 package information
• 6.3 UFQFPN32 package information
• 6.4 LQFP32 package information
• 6.5 UFQFPN48 package information
• 6.6 LQFP48 package information
• 6.7 UFBGA64 package information
• 6.8 LQFP64 package information
• 6.9 Thermal characteristics
• 6.9.1 Reference document
• 6.9.2 Selecting the product temperature range
• 7 Ordering information

Features

• Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 64 MHz
• -40°C to 85°C/105°C/125°C operating temperature
• Memories – Up to 128 Kbytes of Flash memory with protection and securable area – 36 Kbytes of SRAM (32 Kbytes with HW parity check)
• CRC calculation unit
• Reset and power management – Voltage range: 1.7 V to 3.6 V – Power-on/Power-down reset (POR/PDR) – Programmable Brownout reset (BOR) – Programmable voltage detector (PVD) – Low-power modes: Sleep, Stop, Standby, Shutdown BAT supply for RTC and backup registers
• Clock management – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator with calibration – Internal 16 MHz RC with PLL option (±1 %) – Internal 32 kHz RC oscillator (±5 %)
• Up to 60 fast I/Os – All mappable on external interrupt vectors – Multiple 5 V-tolerant I/Os
• 7-channel DMA controller with flexible mapping
• 12-bit, 0.4 µs ADC (up to 16 ext. channels) – Up to 16-bit with hardware oversampling – Conversion range: 0 to 3.6V
• Two 12-bit DACs, low-power sample-and-hold
• Two fast low-power analog comparators, with programmable input and output, rail-to-rail
• 14 timers (two 128 MHz capable): 16-bit for advanced motor control, one 32-bit and five 16- bit general-purpose, two basic 16-bit, two low- power 16-bit, two watchdogs, SysTick timer
• Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown
• Communication interfaces –T w o I 2C-bus interfaces supporting Fast- mode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode – Four USARTs with master/slave synchronous SPI; two supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature – One low-power UART – Two SPIs (32 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I 2S interface – HDMI CEC interface, wakeup on header
• USB Type-C™ Power Delivery controller
• Development support: serial wire debug (SWD)
• 96-bit unique ID
• All packages ECOPACK 2 compliant

Table 1. Device summary

3.21 Universal synchronous/asynchronous re ceiver transmitter (USART) . . . 32

Table 25. Current consumption in Run and Low-power run modes Table 26. Typical current consumption in Run and Low-power run modes, Table 40. LSE oscillator characteristics (f

Introduction STM32G071x8/xB 10/135 DS12232 Rev 4

1 Introduction

This document provides information on STM32G071x8/xB microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering codes. Information on memory mapping and control registers is object of reference manual. Information on Arm®(a) Cortex®-M0+ core is available from the www.arm.com website. a. Arm is a registered trademark of Arm Limited (o r its subsidiaries) in the US and/or elsewhere.

2 Description

and appliance domains and ready for the Internet of Things (IoT) solutions. two basic timers, two low-power 16-bit timers, two watchdog timers, and a SysTick timer. The devices provide a fully integrated USB Type-C Power Delivery controller. the design of low-power applications. VBAT direct battery input allows keeping RTC and backup registers powered. The devices come in packages with 28 to 64 pins. Table 2. STM32G071x8/xB family device features and peripheral counts

1. The numbers in brackets denote the count of SPI interfaces configurable as I2S interface.
2. One port with only one CC line available (supporting limited number of use cases).
3. Depends on order code. Refer to Section 7: Ordering information for details.

Table 2. STM32G071x8/xB family device features and peripheral counts (continued)

Figure 1. Block diagram

Functional overview STM32G071x8/xB 14/135 DS12232 Rev 4

3 Functional overview

3.1 Arm ® Cortex®-M0+ core with MPU

The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:

• a simple architecture, easy to learn and program
• ultra-low power, energy-efficient operation
• excellent code density
• deterministic, high-performance interrupt handling
• upward compatibility with Cortex-M processor family
• platform security robustness, with integrated Memory Protection Unit (MPU). The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers. Owing to embedded Arm core, the STM32G071x8/xB devices are compatible with Arm tools and software. The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC) described in Section 3.13.1.

3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real- time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it.

3.3 Embedded Flash memory

STM32G071x8/xB devices feature up to 128 Kbytes of embedded Flash memory available for storing code and data.

• Readout protection (RDP) to protect the whole memory. Three levels are available: – Level 0: no readout protection – Level 1: memory readout protection: th e Flash memory cannot be read from or written to if either debug features are connected, boot in RAM or bootloader is selected – Level 2: chip readout protection: debug fe atures (Cortex-M0+ serial wire), boot in RAM and bootloader selection are disabled. This selection is irreversible.
• Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity.
• Proprietary code readout protection (PCROP): a part of the Flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU as instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional option bit (PCROP_RDP) determines whether the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0. The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
• single error detection and correction
• double error detection
• readout of the ECC fail address from the ECC register

3.3.1 Securable area

Table 3. Access status versus readout protection level and execution modes

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

1 Yes Yes Yes Yes Yes Yes

1. Erased upon RDP change from Level 1 to Level 0.

2 Yes Yes N/A N/A N/A N/A

Functional overview STM32G071x8/xB 16/135 DS12232 Rev 4

3.4 Embedded SRAM

STM32G071x8/xB devices have 32 Kbytes of embedded SRAM with parity. Hardware parity check allows memory data errors to be detected, which contributes to increasing functional safety of applications. When the parity protection is not required because the application is not safety-critical, the parity memory bits can be used as additional SRAM, to increase its total size to 36 Kbytes. The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

3.5 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot options:

• boot from User Flash memory
• boot from System memory
• boot from embedded SRAM The boot pin is shared with a standard GPIO and can be enabled through the boot selector option bit. The boot loader is located in System memory. It manages the Flash memory reprogramming through one of the following interfaces:
• USART on pins PA9/PA10, PC10/PC11, or PA2/PA3
• I2C-bus on pins PB6/PB7 or PB10/PB11
• SPI on pins PA4/PA5/PA6/PA7 or PB12/PB13/PB14/PB15

3.6 Cyclic redundancy che ck calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location.

STM32G071x8/xB Functional overview

3.7 Power supply management

3.7.1 Power supply schemes

The STM32G071x8/xB devices require a 1.7 V to 3.6 V operating supply voltage (VDD). Several different power supplies are provided to specific peripherals: VDD is the external power supply for the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through VDD/VDDA pin. The minimum voltage of 1.7 V corresponds to power-on reset release threshold VPOR(max). Once this threshold is crossed and power-on reset is released, the functionality is guaranteed down to power-down reset threshold VPDR(min).

• VDDA = 1.62 V (ADC and COMP) / 1.8 V (DAC) / 2.4 V (VREFBUF) to 3.6 V VDDA is the analog power supply for the A/D converter, D/A converter, voltage reference buffer and comparators. VDDA voltage level is identical to VDD voltage as it is provided externally through VDD/VDDA pin.
• VDDIO1 = VDD VDDIO1 is the power supply for the I/Os. VDDIO1 voltage level is identical to VDD voltage as it is provided externally through VDD/VDDA pin.
• VBAT = 1.55 V to 3.6 V. VBAT is the power supply (through a power switch) for RTC, TAMP, low-speed external 32.768 kHz oscillator and backup registers when VDD is not present. VBAT is provided externally through VBAT pin. When this pin is not available on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin.
• VREF+ is the analog peripheral input reference voltage, or the output of the internal voltage reference buffer (when enabled). When VDDA < 2 V, VREF+ must be equal to VDDA. When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA. It can be grounded when the analog peripherals using VREF+ are not active. The internal voltage reference buffer supports two output voltages, which is configured with VRS bit of the VREFBUF_CSR register: –V REF+ around 2.048 V (requiring VDDA equal to or higher than 2.4 V) –V REF+ around 2.5 V (requiring VDDA equal to or higher than 2.8 V) VREF+ is delivered through VREF+ pin. On packages without VREF+ pin, VREF+ is internally connected with VDD, and the internal voltage reference buffer must be kept disabled (refer to datasheets for package pinout description).
• VCORE An embedded linear voltage regulator is used to supply the VCORE internal digital power. VCORE is the power supply for digital peripherals, SRAM and Flash memory. The Flash memory is also supplied with VDD.

Figure 2. Power supply overview

3.7.2 Power supply supervisor

rising VDD and other four for falling VDD. put the MCU into a safe state. The PVD is enabled by software.

3.7.3 Voltage regulator

(LPR), supply most of digital circuitry in the device. and it only supplies the SRAM.

STM32G071x8/xB Functional overview

3.7.4 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
• Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.
• Low-power sleep mode This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the Low- power run mode.
• Stop 0 and Stop 1 modes In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while retaining the SRAM and register contents. All clocks in the V CORE domain are stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event. The main regulator remains active in Stop 0 mode while it is turned off in Stop 1 mode.
• Standby mode The Standby mode is used to achieve the lowest power consumption, with POR/PDR always active in this mode. The main regulator is switched off to power down V CORE domain. The low-power regulator is either switched off or kept active. In the latter case, it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are also powered down. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode. Upon entering Standby mode, register contents are lost except for registers in the RTC domain and standby circuitry. The SRAM contents can be retained through register setting. The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE (CSS on LSE).
• Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off to power down the VCORE domain. The PLL, as well as the

Functional overview STM32G071x8/xB 20/135 DS12232 Rev 4 HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode. Therefore, switching to RTC domain is not supported. SRAM and register contents are lost except for registers in the RTC domain. The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper).

3.7.5 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce power consumption. In addition, when the reset source is internal, the built-in pull-up resistor on NRST pin is deactivated.

3.7.6 VBAT operation

The VBAT power domain, consuming very little energy, includes RTC, and LSE oscillator and backup registers. In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for example, an external battery or an external supercapacitor. Two anti-tamper detection pins are available. The RTC domain can also be supplied from VDD/VDDA pin. By means of a built-in switch, an internal voltage supervisor allows automatic switching of RTC domain powering between V DD and voltage from VBAT pin to ensure that the supply voltage of the RTC domain (VBAT) remains within valid operating conditions. If both voltages are valid, the RTC domain is supplied from VDD/VDDA pin. An internal circuit for charging the battery on VBAT pin can be activated if the VDD voltage is within a valid range. Note: External interrupts and RTC alarm/events can not cause the microcontroller to exit the VBAT mode, as in that mode the VDD is not within a valid range.

3.8 Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes.

Table 4. Interconnect of peripherals

Functional overview STM32G071x8/xB 22/135 DS12232 Rev 4

3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.
• System clock source: three different sources can deliver SYSCLK system clock: – 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It can supply clock to system PLL. The HSE can also be configured in bypass mode for an external clock. – 16 MHz high-speed internal RC oscillator (H SI16), trimmable by software. It can supply clock to system PLL. – System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or HSI16 clocks.
• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock (RTC): – 32.768 kHz low-speed oscillator with exte rnal crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for using an external clock. – 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to clock an independent watchdog.
• Peripheral clock sources: several peripherals ( I2S, USARTs, I2Cs, LPTIMs, ADC) have their own clock independent of the system clock.
• Clock security system (CSS): in the event of HSE clock failure, the system clock is automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected and generate an interrupt. The CCS feature can be enabled by software.
• Clock output: – MCO (microcontroller clock output) provides one of the internal clocks for external use by the application – LSCO (low speed clock output) provides LSI or LSE in all low-power modes (except in VBAT operation). Several prescalers allow the application to configure AHB and APB domain clock frequencies, 64 MHz at maximum.

3.10 General-purpose in puts/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital or analog functions.

STM32G071x8/xB Functional overview Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious writing to I/O control registers.

3.11 Direct memory a ccess controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with single-AHB architecture. With 7 channels, it performs data transfers between memory-mapped peripherals and/or memories, to offload the CPU. Each channel is dedicated to managing memory access requests from one or more peripherals. The unit includes an arbiter for handling the priority between DMA requests. Main features of the DMA controller:

• Single-AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to- peripheral data transfers
• Access, as source and destination, to on-chip memory-mapped devices such as Flash memory, SRAM, and AHB and APB peripherals
• All DMA channels independently configurable: – Each channel is associated either with a DMA request signal coming from a peripheral, or with a software trigger in memory-to-memory transfers. This configuration is done by software. – Priority between the requests is programmable by software (four levels per channel: very high, high, medium, low) and by hardware in case of equality (such as request to channel 1 has priority over request to channel 2). – Transfer size of source and destination are independent (byte, half-word, word), emulating packing and unpacking. Source and destination addresses must be aligned on the data size. – Support of transfers from/to peripherals to/from memory with circular buffer management – Programmable number of data to be transferred: 0 to 2 16 - 1
• Generation of an interrupt request per channel. Each interrupt request originates from any of the three DMA events: transfer complete, half transfer, or transfer error.

3.12 DMA request mu ltiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA controller. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs. DMAMUX may also be used as a DMA request generator from programmable events on its input trigger signals.

3.13 Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)

Functional overview STM32G071x8/xB 24/135 DS12232 Rev 4 and an extended interrupt/event controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events such as, for example, a division by zero and, core-external events such as logical level changes on physical lines. Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the original program flow. The processor context (contents of program pointer and status registers) is stacked upon program interrupt and unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-multiple and store-multiple operations significantly increases the device’s responsiveness in processing exceptions.

3.13.1 Nested vectored inte rrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex-M0+ exceptions. It provides flexible priority management. The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the NVIC at a base address. The vector address of an ISR to execute is hardware-built from the vector table base address and the ISR order number used as offset. If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-chaining. Upon a return from a higher-priority ISR then start of a pending lower-priority ISR, the unnecessary processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency. Features of the NVIC:

• Low-latency interrupt processing
• 4 priority levels
• Handling of a non-maskable interrupt (NMI)
• Handling of 32 maskable interrupt lines
• Handling of 10 Cortex-M0+ exceptions
• Later-arriving higher-priority interrupt processed first
• Tail-chaining
• Interrupt vector retrieval by hardware

3.13.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying wake-up events at processor wakeup from Stop mode. The EXTI controller has a number of channels, of which some with rising, falling or rising, and falling edge detector capability. Any GPIO and a few peripheral signals can be connected to these channels. The channels can be independently masked. The EXTI controller can capture pulses shorter than the internal clock period.

GPIO and the edge event having caused an interrupt.

3.14 Analog-to-digital converter (ADC)

conversion is performed on a selected group of analog inputs. the ADC is powered off except during the active conversion phase. outside the programmed thresholds. the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

3.14.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. output voltage into a digital value. is suitable only for relative temperature measurements. accessible in read-only mode. Table 5. Temperature sensor calibration values

3.14.2 Internal voltage reference (V REFINT)

stored in the part’s engineering bytes. It is accessible in read-only mode.

3.14.3 V BAT battery voltage monitoring

3.15 Digital-to-analog converter (DAC)

string and an inverting amplifier. The digital circuitry is common for both channels.

• Two DAC output channels
• 8-bit or 12-bit output mode
• Buffer offset calibration (factory and user trimming)
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Independent or simultaneous conversion for DAC channels
• DMA capability for either DAC channel
• Triggering with timer events, synchronized with DMA
• Triggering with external events
• Sample-and-hold low-power mode, with internal or external capacitor

Table 6. Internal voltage reference calibration values

3.16 Voltage referen ce buffer (VREFBUF)

3.17 Comparators (COMP)

(internal or external), hysteresis, speed (low for low-power) and output polarity.

• external, from an I/O
• internal, from DAC
• internal reference voltage (VREFINT) or its submultiple (1/4, 1/2, 3/4) The comparators can wake up the device from Stop mode, generate interrupts, breaks or triggers for the timers and can be also combined into a window comparator.

3.18 Timers and watchdogs

features of the advanced-control, general-purpose and basic timers. blocks (for example ADC) and to VREF+ pin for external components.

• 2.048 V
• 2.5 V An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is disabled. On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to common VDD/VDDA pin and so the internal voltage reference buffer cannot be used.

Table 7. Timer feature comparison

3.18.1 Advanced-control timer (TIM1)

• input capture
• output compare
• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)
• one-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled, so as to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIMx timers (described in Section 3.18.2) using the same architecture, so the advanced-control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. General- purpose TIM2 32-bit Up, down, up/down 64 MHz Integer from 1 to 216 Yes 4 - TIM3 16-bit Up, down, up/down 64 MHz Integer from 1 to 216 Yes 4 - TIM14 16-bit Up 64 MHz Integer from 1 to 216 No 1 - TIM15 16-bit Up 128 MHz Integer from 1 to 216 Yes 2 1 TIM16 TIM17 16-bit Up 64 MHz Integer from 1 to 216 Yes 1 1 Basic TIM6 TIM7 16-bit Up 64 MHz Integer from 1 to 216 Yes - - Low-power LPTIM1 LPTIM2 16-bit Up 64 MHz 2n where n=0 to 7 No N/A -

Table 7. Timer feature comparison (continued)

STM32G071x8/xB Functional overview

3.18.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17)

There are six synchronizable general-purpose timers embedded in the device (refer to Table 7 for comparison). Each general-purpose timer can be used to generate PWM outputs or act as a simple timebase.

• TIM2, TIM3 These are full-featured general-purpose timers: – TIM2 with 32-bit auto-reload up/downcounter and 16-bit prescaler – TIM3 with 16-bit auto-reload up/downcounter and 16-bit prescaler They have four independent channels for input capture/output compare, PWM or one- pulse mode output. They can operate together or in combination with other general- purpose timers via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request and support quadrature encoders. Their counters can be frozen in debug mode.
• TIM14 This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one channel for input capture/output compare, PWM output or one-pulse mode output. Its counter can be frozen in debug mode.
• TIM15, TIM16, TIM17 These are general-purpose timers featuring: – 16-bit auto-reload upcounter and 16-bit prescaler – 2 channels and 1 complementary channel for TIM15 – 1 channel and 1 complementary channel for TIM16 and TIM17 All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can operate together via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request. Their counters can be frozen in debug mode.

3.18.3 Basic timers (TIM6 and TIM7)

3.18.4 Low-power timers (LPTIM1 and LPTIM2)

These timers have an independent clock. When fed with LSE, LSI or external clock, they keep running in Stop mode and they can wake up the system from it. These timers are mainly used for triggering DAC conversions. They can also be used as generic 16-bit timebases.

Functional overview STM32G071x8/xB 30/135 DS12232 Rev 4 Features of LPTIM1 and LPTIM2:

• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output (pulse, PWM)
• Continuous/one-shot mode
• Selectable software/hardware input trigger
• Selectable clock source: – Internal: LSE, LSI, HSI16 or APB clocks – External: over LPTIM input (working ev en with no internal clock source running, used by pulse counter application)
• Programmable digital glitch filter
• Encoder mode

3.18.5 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI). Independent of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Its counter can be frozen in debug mode.

3.18.6 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked by the system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug mode.

3.18.7 SysTick timer

This timer is dedicated to real-time operating systems, but it can also be used as a standard down counter. Features of SysTick timer:

• 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source

3.19 Real-time clock (RTC), tamp er (TAMP) and backup registers

The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of the silicon die. The ways of powering the RTC domain are described in Section 3.7.6. The RTC is an independent BCD timer/counter.

STM32G071x8/xB Functional overview Features of the RTC:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Programmable alarm
• On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with a master clock
• Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be used to improve the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy
• Two anti-tamper detection pins with programmable filter
• Timestamp feature to save a calendar snapshot, triggered by an event on the timestamp pin or a tamper event, or by switching to VBAT mode
• 17-bit auto-reload wakeup timer (WUT) for periodic events, with programmable resolution and period
• Multiple clock sources and references: – A 32.768 kHz external crystal (LSE) – An external resonator or oscillator (LSE) – The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz) – The high-speed external clock (HSE) divided by 32 When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When clocked by LSI, the RTC does not operate in VBAT mode, but it does in low-power modes except for the Shutdown mode. All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wake the device up from the low-power modes. The backup registers allow keeping 20 bytes of user application data in the event of V DD failure, if a valid backup supply voltage is provided on VBAT pin. They are not affected by the system reset, power reset, and upon the device’s wakeup from Standby or Shutdown modes.

3.20 Inter-integrated ci rcuit interface (I2C)

The device embeds two I2C peripherals. Refer to Table 8 for the features. The I2C-bus interface handles communication between the microcontroller and the serial I2C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing.

• I2C-bus specification and user manual rev. 5 compatibility: – Slave and master modes , multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Clock stretching
• SMBus specification rev 3.0 compatibility: – Hardware PEC (packet error checking) generation and verification with ACK control – Command and data acknowledge control – Address resolution protocol (ARP) support – Host and Device support – SMBus alert – Timeouts and idle condition detection
• PMBus rev 1.3 standard compatibility
• Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent of the PCLK reprogramming
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

3.21 Universal synchronous/asynch ronous receiver transmitter

communicate at speeds of up to 8 Mbit/s. Table 8. I2C implementation

• start bit detection
• any received data frame
• a specific programmed data frame All USART interfaces can be served by the DMA controller.

3.22 Low-power universal asynchr onous receiver transmitter

• start bit detection
• any received data frame
• a specific programmed data frame Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while

Table 9. USART implementation

The LPUART interface can be served by the DMA controller.

3.23 Serial peripheral interface (SPI)

peripherals support NSS pulse mode, TI mode and hardware CRC calculation. The SPI peripherals can be served by the DMA controller.

3.24 USB Type-C™ Power Delivery controller

The device embeds two controllers (UCPD1 and UCPD2) compliant with USB Type-C Rev. 1.2 and USB Power Delivery Rev. 3.0 specifications.

• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
• “Dead battery” support
• USB Power Delivery message transmission and reception
• FRS (fast role swap) support

Table 10. SPI/I2S implementation

STM32G071x8/xB Functional overview The digital controller handles notably:

• USB Type-C level detection with de-bounce, generating interrupts
• FRS detection, generating an interrupt
• byte-level interface for USB Power Delivery payload, generating interrupts (DMA compatible)
• USB Power Delivery timing dividers (including a clock pre-scaler)
• CRC generation/checking
• 4b5b encode/decode
• ordered sets (with a programmable ordered set mask at receive)
• frequency recovery in receiver during preamble The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages and FRS signaling.

3.25 Development support

3.25.1 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

4 Pinouts, pin description and alternate functions

Features and peripheral counts for differences. Figure 3. STM32G071RxT LQFP64 pinout

Figure 8. STM32G071KxU UFQFPN32 pinout

Table 11. Terms and symbols used in Table 12 parenthesis under the pin name. Note Upon reset, all I/Os are set as analog inputs, unless otherwise specified. Table 12. Pin assignment and description

Table 12. Pin assignment and description (continued)

1. PC13, PC14 and PC15 are supplied through the power switch. Sinc e the switch only sinks a limited amount of current (3

• These GPIOs must not be used as current sources (for example to drive a LED).

1. After an RTC domain power-up, PC13, PC14 and PC15 operat e as GPIOs. Their function then depends on the content of

the RTC domain and RTC register descriptions in the RM0444 reference manual.

1. Upon reset, a pull-down resistor might be present on PB15, PA8, PD0, or PD2, depending on the voltage level on PB0,

register during start-up sequence.

1. Pins PA9/PA10 can be remapped in place of pins PA11 /PA12 (default mapping), using SYSCFG_CFGR1 register.
2. Upon reset, these pins are configur ed as SW debug alternate functions, and the internal pull-up on PA13 pin and the

internal pull-down on PA14 pin are activated.

Table 13. Port A alternate function mapping

Table 14. Port B alternate function mapping

Table 15. Port C alternate function mapping

Table 16. Port D alternate function mapping Table 17. Port F alternate function mapping

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS. information scope are to be ignored. commercial packages as per the ordering information.

5.1.1 Minimum and maximum values

the selected temperature range). mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

are given only as design guidelines and are not tested. error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 11.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12. Figure 11. Pin loading conditions Figure 12. Pin input voltage

5.1.6 Power supply scheme

Figure 13. Power supply scheme functionality of the device.

5.1.7 Current consumption measurement

5.2 Absolute maximum ratings

conditions for extended periods may affect device reliability. Figure 14. Current consumption measurement scheme Table 18. Voltage characteristics

1. Refer to Table 19 for the maximum allowed injected current values.
2. To sustain a voltage higher than 4 V the inte rnal pull-up/pull-down resistors must be disabled.

5.3 Operating conditions

5.3.1 General operating conditions

Table 19. Current characteristics

1. All main power (VDD/VDDA, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power

supplies, in the permitted range.

1. A positive injection is induced by V IN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be

exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.

1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
2. On these I/Os, any current injection di sturbs the analog performances of the device.
3. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative

injected currents (instantaneous values). Table 20. Thermal characteristics Table 21. General operating conditions

5.3.2 Operating conditions at power-up / power-down

temperature condition summarized in Table 21.

5.3.3 Embedded reset and power control block characteristics

temperature conditions summarized in Table 21: General operating conditions.

1. When RESET is released func tionality is guaranteed down to VPDR min.
2. For operation with voltage higher than V DD +0.3 V, the internal pull-up and pull-down resistors must be disabled.
3. The T A(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided

that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.9: Thermal characteristics.

1. Temperature range digit in the order code. See Section 7: Ordering information.

Table 21. General operating conditions (continued) Table 22. Operating conditions at power-up / power-down Table 23. Embedded reset and power control block characteristics

1. Continuous mode means Run/Sleep modes, or temperatur e sensor enable in Low-power run/Low-power sleep modes.

Table 23. Embedded reset and power control block characteristics (continued)

5.3.4 Embedded voltage reference

Figure 15. VREFINT vs. temperature Table 24. Embedded internal voltage reference

1. The shortest sampling time can be determined in the application by multiple iterations.

STM32G071x8/xB Electrical characteristics 107

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 14: Current consumption measurement scheme. Typical and maximum current consumption The MCU is placed under the following conditions:

• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted with the minimum wait states number, depending on the fHCLK frequency (refer to the table “Number of wait states according to CPU clock (HCLK) frequency” available in the RM0444 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
• For Flash memory and shared peripherals fPCLK = fHCLK = fHCLKS Unless otherwise stated, values given in Table 25 through Table 33 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

64 MHz

16 MHz

2 MHz

1 MHz 105 155 320 505 770 1200

1 MHz 95 140 290 430 660 1140

1. Based on characterization results, not tested in production.
2. Prefetch and cache enabled when fetching from Flash memory . Code compiled with high optimization for space in SRAM.
3. V DD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.

64 MHz;

16 MHz,

2 MHz;

1. Prefetch and cache enabled when fetching from Flash. Code compiled with high optimization for space in SRAM.
2. VDD = 3.3 V, all peripherals disabled, cache enabled, prefetch disabled for execution in Flash and enabled in SRAM
3. Reduced code used for characterization results provided in Table 25.

Table 27. Current consumption in Sleep and Low-power sleep modes

2 MHz 60 99 265 150 360 1110

1 MHz 33 75 240 130 330 1010

1. Based on characterization results, not tested in production.

Table 28. Current consumption in Stop 0 mode

1.8 V 275 305 430 330 425 750

2.4 V 280 310 435 330 450 850

3 V 280 315 435 350 490 950

3.6 V 285 315 440 375 500 1020

1.8 V 95 140 270 120 180 490

2.4 V 100 145 275 125 220 610

3 V 100 145 280 125 240 720

3.6 V 105 150 285 130 250 840

1. Based on characterization results, not tested in production.

Table 29. Current consumption in Stop 1 mode

1. Based on characterization results, not tested in production.

Table 30. Current consumption in Standby mode

1. Based on characterization results, not tested in production.
2. Without SRAM retention and with ULPEN bit set
3. To be added to I DD(Standby) as appropriate

Table 30. Current consumption in Standby mode (continued) Table 31. Current consumption in Shutdown mode

1.8 V 17 515 4500 250 3000 32600

2.4 V 23 600 5150 450 3500 33600

3.0 V 33 730 6450 1075 4250 37400

3.6 V 53 940 7700 1250 5300 43600

1.8 V 205 710 4700 900 4500 27300

2.4 V 300 890 5500 1550 5500 34800

3.0 V 420 1150 6800 2475 6000 40900

3.6 V 565 1450 8100 3250 7000 48500

1. Based on characterization results, not tested in production.

Table 32. Current consumption in VBAT mode

1.8 V 165 170 620

2.4 V 260 355 970

3.0 V 365 475 1200

3.6 V 505 655 2070

1.8 V 290 390 960

2.4 V 370 480 1150

3.0 V 470 600 1650

3.6 V 600 815 2250

1.8 V 1 80 660

2.4 V 2 90 750

3.0 V 2 105 1200

3.6 V 6 200 1700

STM32G071x8/xB Electrical characteristics 107 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 51: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 33: Current consumption of peripherals), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where I SW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDIO1 is the I/O supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS CS is the PCB board capacitance including the pad pin. The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. ISW VDDIO1 fSW C××=

• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions: – when the peripheral is clocked on – when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 18: Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in the following table. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet.

Table 33. Current consumption of peripherals

5.3.6 Wakeup time from low-power modes and voltage scaling

1. The AHB to APB Bridge is automatically active when at least one peripheral is ON on the APB.
2. UCPDx are always clocked by HSI16.

Table 33. Current consumption of peripherals (continued) Table 34. Low-power mode wakeup times(1)

1. Based on characterization results, not tested in production.
2. Time until REGLPF flag is cleared in PWR_SR2.

Table 34. Low-power mode wakeup times(1) (continued) Table 35. Regulator mode transition times(1)

1. Based on characterization results, not tested in production.
2. Time until VOSF flag is cleared in PWR_SR2.

5.3.7 External clock source characteristics

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. Figure 16 for recommended clock input waveform. Figure 16. High-speed external clock source AC timing diagram Table 36. Wakeup time using LPUART(1) Table 37. High-speed external user clock characteristics(1)

design guide for ST microcontrollers” available from the ST website www.st.com.

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. This consumption level occurs during the first 2/3 of the t SU(HSE) startup time
3. t SU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is

Table 39. HSE oscillator characteristics(1) (continued)

Figure 18. Typical application with an 8 MHz crystal

1. R EXT value depends on the crystal characteristics.

8 MHz

Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

design guide for ST microcontrollers” available from the ST website www.st.com. Figure 19. Typical application with a 32.768 kHz crystal

5.3.8 Internal clock source characteristics

conditions. The provided curves are characterization results, not tested in production.

1. t SU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

Table 41. HSI16 oscillator characteristics(1)

Figure 20. HSI16 frequency vs. temperature

1. Based on characterization results, not tested in production.

Table 41. HSI16 oscillator characteristics(1) (continued) Table 42. LSI oscillator characteristics(1)

1. Based on characterization results, not tested in production.

5.3.9 PLL characteristics

VDD supply voltage conditions summarized in Table 21: General operating conditions.

5.3.10 Flash memory characteristics

Table 43. PLL characteristics(1)

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values.

Table 44. Flash memory characteristics(1)

5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization. While a simple application is executed on the device (toggling 2 LEDs through I/O ports).

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V DD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 46. They are based on the EMS levels and classes defined in application note AN1709. IDD(FlashA) Average consumption from VDD Programming 3 - mAPage erase 3 - Mass erase 3 - IDD(FlashP) Maximum current (peak) Programming, 2 µs peak duration 7- mA Erase, 41 µs peak duration 7 - 1. Guaranteed by design. 2. Values provided also apply to devices with less Flash memory than one 128 Kbyte bank

Table 44. Flash memory characteristics(1) (continued) Table 45. Flash memory endurance and data retention

1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.

performance is highly dependent on the user application and the software in particular. prequalification tests in relation with the EMC level requested for his application.

• corrupted program counter
• unexpected reset
• critical data corruption (for example control registers) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading.

Table 46. EMS characteristics

5.3.12 Electrical sens itivity characteristics

stressed in order to determine its performance in terms of electrical sensitivity. conforms to the ANSI/JEDEC standard.

• A supply overvoltage is applied to each power supply pin.
• A current is injected to each input, output and configurable I/O pin. These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 47. EMI characteristics

8 MHz / 64 MHz

0.1 MHz to 30 MHz 7

30 MHz to 130 MHz -1

130 MHz to 1 GHz 8

1 GHz to 2 GHz 7

Table 48. ESD absolute maximum ratings

1. Based on characterization results, not tested in production.

Table 49. Electrical sensitivity

5.3.13 I/O current in jection characteristics

are performed on a sample basis during device characterization. the I/O pin, one at a time, the device is checked for functional failures. oscillator frequency deviation). leakage current is caused by positive injection. Table 50. I/O current injection susceptibility(1)

1. Based on characterization results, not tested in production.

5.3.14 I/O port characteristics

I/Os are designed as CMOS- and TTL-compliant. Table 51. I/O static characteristics

1.62 V < V

1. Refer to Figure 21: I/O input characteristics.

Figure 21. I/O input characteristics ±15 mA with relaxed VOL/VOH.

• The sum of the currents sourced by all the I/Os on VDDIO1, plus the maximum consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 18: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see Table 18: Voltage characteristics). Output voltage levels Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in 4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula: ITotal_Ileak_max = 10 µA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max). 5. Pull-up and pull-down resistor s are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). MSv47925V1 0.5 1.5 2.5 Minimum required logic level 1 zone Minimum required logic level 0 zone VIHmin = 0.7 V DDIO (CMOS standard requirement) VILmax = 0.3 VDDIO (CMOS standard requirement) Undefined input range VIHmin = 0.49 VDDIO + 0.26 VILmax = 0.39 VDDIO - 0.06 VIN (V) VDDIO (V) TTL standard requirement TTL standard requirement Device characteristics Test thresholds

unless otherwise specified). Table 52. Output voltage characteristics(1)

1. The I IO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18:

respect the absolute maximum ratings ΣIIO.

1. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

Table 53. I/O AC characteristics(1)(2)

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.

Refer to the RM0444 reference manual for a description of GPIO Port configuration register.

1. This value represents the I/O c apability but the maximum system frequency is limited to 64 MHz.
2. The fall time is defined between 70% and 30% of the output waveform, according to I 2C specification.

Table 53. I/O AC characteristics(1)(2) (continued)

Figure 22. I/O AC characteristics definition(1)

1. Refer to Table 53: I/O AC characteristics.

5.3.15 NRST input characteristics

in Table 21: General operating conditions. when loaded by the specified capacitance. Table 54. NRST pin characteristics(1)

1. The pull-up is designed with a true re sistance in series with a switchable PMOS. This PMOS contribution to the series

resistance is minimal (~10% order).

Figure 23. Recommended NRST pin protection

1. The reset network protects t he device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V IL(NRST) max level specified in

Table 54: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.

1. The external capacitor on NRST must be placed as close as possible to the device.

5.3.16 Analog switch booster

5.3.17 Analog-to-digital converter characteristics

conditions summarized in Table 21: General operating conditions. Note: It is recommended to perform a calibration after each power-up. Table 55. Analog switch booster characteristics(1) Table 56. ADC characteristics(1)

Table 56. ADC characteristics(1) (continued)

1. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when V DDA < 2.4 V and
2. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate

functions for further details. Table 57. Maximum ADC RAIN .

1. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when V DDA < 2.4 V and
2. Only allowed with V DDA > 2 V

Table 57. Maximum ADC RAIN . (continued) Table 58. ADC accuracy(1)(2)(3)

Table 58. ADC accuracy(1)(2)(3) (continued)

1. Based on characterization results, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. Injecting negative current on any analog i nput pin significantly reduces the accuracy of A-to-D conversion of signal on
4. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when V

Figure 24. ADC accuracy characteristics Figure 25. Typical connection diagram using the ADC

1. Refer to Table 56: ADC characteristics for the values of RAIN and CADC.
2. C parasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

1. Refer to Table 51: I/O static characteristics for the values of Ilkg.

close as possible to the chip.

1 LSB ideal

between the actual and ideal transfer curves. transition and the last actual one. between actual steps and the ideal ones. any actual transition and the end point correlation line. first actual transition and the first ideal one.

5.3.18 Digital-to-analog converter characteristics

Table 59. DAC characteristics(1)

Table 59. DAC characteristics(1) (continued)

Figure 26. 12-bit buffered / non-buffered DAC

1. The DAC integrates an output buffer that can be used to r educe the output impedance and to drive external loads directly
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 51: I/O static characteristics.
4. T on is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0444 reference manual for more details.

Table 60. DAC accuracy(1)

5.3.19 Voltage referenc e buffer characteristics

1. Difference between two consecutive codes - 1 LSB.
2. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
3. Difference between the value measured at Code (0x001) and the ideal value.
4. Difference between ideal slope of the transfer functi on and measured slope computed from code 0x000 and 0xFFF when

REF+ – 0.2) V when buffer is ON. Table 60. DAC accuracy(1) (continued) Table 61. VREFBUF characteristics(1)

5.3.20 Comparator characteristics

1. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (V DDA -
2. The temperature coefficient at VREF+ output is the sum of T Coeff_vrefint and TCoeff_vrefbuf.
3. The capacitive load must include a 100 nF capac itor in order to cut-off the high frequency noise.
4. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the V DDA voltage should be in

Table 61. VREFBUF characteristics(1) (continued) Table 62. COMP characteristics(1)

5.3.21 Temperature sensor characteristics

1. Refer to Table 24: Embedded internal voltage reference.

Table 62. COMP characteristics(1) (continued) Table 63. TS characteristics

5.3.22 V BAT monitoring characteristics

5.3.23 Timer characteristics

characteristics (output compare, input capture, external clock, PWM output).

1. Based on characterization results, not tested in production.
2. Measured at V DDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.
3. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

Table 63. TS characteristics (continued) Table 64. VBAT monitoring characteristics Table 65. VBAT charging characteristics Table 66. TIMx(1) characteristics

5.3.24 Characteristics of communication interfaces

• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s. The timings are guaranteed by design as long as the I2C peripheral is properly configured (refer to the reference manual RM0444) and when the I2CCLK frequency is greater than the minimum shown in the following table. tCOUNTER 16-bit counter clock period - 1 65536 t TIMxCLK fTIMxCLK = 64 MHz 0.015625 1024 µs tMAX_COUNT Maximum possible count with 32-bit counter - - 65536 × 65536 t TIMxCLK fTIMxCLK = 64 MHz - 67.10 s 1. TIMx , is used as a general term in which x stands for 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17.

Table 66. TIMx(1) characteristics (continued) Table 67. IWDG min/max timeout period at 32 kHz LSI clock(1)

1. The exact timings further depend on the phase of the APB inte rface clock versus the LSI clock, which causes an

uncertainty of one RC period.

port characteristics for the I2C I/Os characteristics.

• OSPEEDRy[1:0] set to 11 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 x VDD Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 68. Minimum I2CCLK frequency Table 69. I2C analog filter characteristics(1)

1. Based on characterization results, not tested in production.
2. Spikes shorter than the limiting duration are suppressed.

Table 70. SPI characteristics(1)

Figure 29. SPI timing diagram - master mode

1. Measurement points are set at CMOS levels: 0.3 V DD and 0.7 VDD.

Table 71. I2S characteristics(1)

Figure 30. I2S slave timing diagram (Philips protocol)

1. Measurement points are done at CMOS levels: 0.3 V DDIO1 and 0.7 VDDIO1.
2. LSB transmit/receive of the previ ously transmitted byte. No LSB transmit/receive is sent before the first
3. Based on characterization results, not tested in production.

Table 71. I2S characteristics(1) (continued)

Figure 31. I2S master timing diagram (Philips protocol)

1. Based on characterization results, not tested in production.
2. LSB transmit/receive of the previ ously transmitted byte. No LSB transmit/receive is sent before the first

• OSPEEDRy[1:0] set to 10 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 x VDD Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, CK, TX, and RX for USART). MSv39720V1 CK output CPOL = 0 CPOL = 1 tc(CK) WS output SDreceive SDtransmit tw(CKH) tw(CKL) tsu(SD_MR) tv(SD_MT) th(SD_MT) th(WS) th(SD_MR) MSB receive Bitn receive LSB receive MSB transmit Bitn transmit LSB transmit tf(CK) tr(CK) tv(WS) LSB receive(2) LSB transmit(2) 10% 90%

Table 72. USART characteristics

5.3.25 UCPD characteristics

Table 73. UCPD operating conditions

6 Package information

specifications, grade definitions and product status are available at: www.st.com.

6.1 WLCSP25 package information

WLCSP25 is a 25-ball, 2.30 x 2.48 mm wafer-level chip-scale package with 0.4 mm pitch. Figure 32. WLCSP25 chip-scale package outline

1. Dimension is measured at the maximum bum p diameter parallel to primary datum Z.
2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
3. Bump position designation per JESD 95-1, SPP-010.

Figure 33. Recommended PCB pad design for WLCSP25 package Table 74. WLCSP25 mechanical data

1. Values in inches are converted from mm and rounded to 3 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal

values and tolerances of A1 and A2.

1. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
2. Calculated dimensions are rounded to the 3rd decimal place

The printed markings may differ depending on the supply chain. operations, are not indicated below. Figure 34. WLCSP25 package marking example

1. Parts marked as ES or E or accompanied by an Engi neering Sample notification letter are not yet qualified

samples to run a qualification activity. Table 75. Recommended PCB pad design rules for WLCSP25 package

1. Depends on the solder mask registration tolerance

6.2 UFQFPN28 package information

UFQFPN is a 28-lead, 4x4 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package. Figure 35. UFQFPN28 package outline Table 76. UFQFPN28 package mechanical data(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

6.3 UFQFPN32 package information

UFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package. Figure 38. UFQFPN32 package outline

1. There is an exposed die pad on the underside of t he UFQFPN package. It is recommended to connect and

solder this backside pad to PCB ground. Table 77. UFQFPN32 package mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm.

6.4 LQFP32 package information

LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package. Figure 41. LQFP32 package outline Table 78. LQFP32 mechanical data

Figure 42. Recommended footprint for LQFP32 package

1. Dimensions are expr essed in millimeters.
2. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 78. LQFP32 mechanical data (continued)

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 43. LQFP32 package marking example

1. Parts marked as ES or E or accompanied by an Engi neering Sample notification letter are not yet qualified

samples to run a qualification activity.

6.5 UFQFPN48 package information

Figure 44. UFQFPN48 package outline

1. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
2. There is an exposed die pad on the underside of t he UFQFPN package. It is recommended to connect and

solder this back-side pad to PCB ground. Table 79. UFQFPN48 package mechanical data

Figure 45. Recommended footprint for UFQFPN48 package

1. Dimensions are expr essed in millimeters.
2. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 79. UFQFPN48 package mechanical data (continued)

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 46. UFQFPN48 package marking example

1. Parts marked as ES or E or accompanied by an Engi neering Sample notification letter are not yet qualified

samples to run a qualification activity.

6.6 LQFP48 package information

LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package. Figure 47. LQFP48 package outline Table 80. LQFP48 mechanical data

Figure 48. Recommended footprint for LQFP48 package

1. Dimensions are expr essed in millimeters.
2. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 80. LQFP48 mechanical data (continued)

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 49. LQFP48 package marking example

1. Parts marked as ES or E or accompanied by an Engi neering Sample notification letter are not yet qualified

samples to run a qualification activity.

6.7 UFBGA64 package information

Figure 50. UFBGA64 package outline Table 81. UFBGA64 package mechanical data

Figure 51. Recommended footprint for UFBGA64 package

1. Values in inches are converted fr om mm and rounded to 4 decimal digits.

Table 81. UFBGA64 package mechanical data (continued) Table 82. Recommended PCB design rules for UFBGA64 package

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 52. UFBGA64 package marking example

1. Parts marked as ES or E or accompanied by an Engi neering Sample notification letter are not yet qualified

samples to run a qualification activity.

6.8 LQFP64 package information

LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package. Figure 53. LQFP64 package outline Table 83. LQFP64 package mechanical data

Figure 54. Recommended footprint for LQFP64 package

1. Dimensions are expr essed in millimeters.
2. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 83. LQFP64 package mechanical data (continued)

The printed markings may differ depending on the supply chain. chain operations, are not indicated below. Figure 55. LQFP64 package marking example

1. Parts marked as ES or E or accompanied by an Engi neering Sample notification letter are not yet qualified

samples to run a qualification activity.

6.9 Thermal characteristics

• TA(max) is the maximum operating ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD = PINT + PI/O, –P INT is power dissipation contribution from product of IDD and VDD –P I/O is power dissipation contribution from output ports where: PI/O = Σ (VOL × IOL) + Σ ((VDDIO1 – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

6.9.1 Reference document

Convection (still air). Available from www.jedec.org.

6.9.2 Selecting the product temperature range

maximum dissipation and to a specific maximum junction temperature. to determine which temperature range best suits the application. Table 21: General operating conditions. Table 84. Package thermal characteristics

The following example shows how to calculate the temperature range needed for a given application. Example: Assuming the following worst application conditions:

• ambient temperature TA = 50 °C (measured according to JESD51-2)
• IDD = 50 mA; VDD = 3.6 V
• 20 I/Os simultaneously used as output at low level with IOL = 8 mA (VOL= 0.4 V), and
• 8 I/Os simultaneously used as output at low level with IOL = 20 mA (VOL= 1.3 V), the power consumption from power supply PINT is: PINT = 50 mA × 3.6 V= 118 mW, the power loss through I/Os PIO is PIO = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW, and the total power PD to dissipate is: PD = 180 mW + 272 mW = 452 mW For a package with ΘJA= 65 °C/W, the junction temperature stabilizes at: As a conclusion, product version with suffix 6 (maximum allowed TJ = 105° C) is sufficient for this application. If the same application was used in a hot environment with maximum TA greater than 75.5 °C, the junction temperature would exceed 105°C and the product version allowing higher maximum T J would have to be ordered.

7 Ordering information

For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Example STM32 G 071 K 8 T 6 xyy Device family STM32 = Arm® based 32-bit microcontroller Product type G = general-purpose Device subfamily 071 = STM32G071 Pin count E = 25 G = 28 K = 32 C = 48 R = 64 Flash memory size 8 = 64 Kbytes B = 128 Kbytes Package type I = UFBGA T = LQFP U = UFQFPN Y = WLCSP Temperature range 6 = -40 to 85°C (105°C junction) 7 = -40 to 105°C (125°C junction) 3 = -40 to 125°C (130°C junction) Options xTR = tape and reel packing; x = N (“N” product version), otherwise blank x˽˽ = tray packing; x = N (“N” product version) or blank other = 3-character ID incl. custom Flash code and packing information; x = N for “N” product version

8 Revision history

Table 85. Document revision history 8-Nov-2018 1 Initial release. Figures with package marking examples corrected.

Table 85. Document revision history (continued)