32192

32192 RENESAS | Alldatasheet

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M32R FAMIL Y / M32R/ECU SERIES Rev. 1.10 Revision date: Apr. 06, 2007 www.renesas.com All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). REJ09B0123-0110 32192/32195/32196 Group Hardware Manual

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Notes regarding these materials

General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

REVISION HISTORY

Rev. Date Description Page Summary (REVISION HISTORY-1) 32192/32195/32196 Group Hardware Manual

1.01 Jul 22, 2005 - First edition issued

1.10 Apr 06, 2007 - Add the 32195 Group

Add M32192F8VWG, M32192F8UWG, and M32192F8TWG 2-3 Add Note 1 to IE bit of PSW register 5-6 Correct notes of IMASK register Incorrect) the Interrupt Request Mask Register (IMASK) in the EIT handler → Correct) the Interrupt Request Mask Register (IMASK) 5-7 Add a note for SBI Control Register 6-15 Add a description for FAENS bit of FMOD Register 6-16 Add descriptions for ERASE bit and WRERR bit. 6-19 to 21 Correct descriptions of FCNOT3 Register Add Table 6.5.2 and correct Figure 6.5.2 6-34 Add Figure 6.6.7 6-36 Correct the description of 4 Halfword Program command 6-55 Add a note to 6.11 Notes on the Internal RAM 8-33 Correct functions of b4 (12) WFnSEL bit in the Port Group n Input Level Setting Regsiter 8-35 Correct R/W status of GnDSEL bits in the Port Group n Output Drive Capability Setting Register 8-39 Replace Figure 8.7.1 8-40 Replace Figure 8.7.2 8-41 Replace Figure 8.7.3 8-42 Replace Figure 8.7.4 8-43 Replace Figure 8.7.5 8-44 Add a note about using input/output ports in input mode Add a note about the peripheral function input when it is set to the general- purpose port 9-26 Correct functions of RINGSEL bit 9-27 Correct descriptions of TREQFn bit and TENLn bit 9-28 Correct the description of SELFEN bit 10-114 Add descriptions to Reload register uptdates in TIO PWM output mode 10-157 Correct a note of TOU Counters 10-160 Correct a note of TOU Registers 10-171 Correct read status of PO0LVSELGA bit and PO1LVSELGA bit 10-176 Add descriptions to Reload register updates in TOUP PWM output mode 11-21 Add Note 3 to ADSEL2 bit 12-4 Replace Figure 12.1.1 12-8 Correct the description of notes on using transmit interrupts 12-45,62 Add a note about switching from general-purpose to serial interface pin 13-27 Correct the description of RBO bit 13-28 Add descriptions to LBM bit and RST bit

Rev. Date Description Page Summary (REVISION HISTORY-2) 32192/32195/32196 Group Hardware Manual

1.10 Apr 06, 2007 13-31 Add a description to CRS bit

13-118 Add Note 1 to Figure 13.3.4 14-3 Replace Figure 14.1.1 14-24 Replace Figure 14.2.7 14-27 Correct the decription of DRI Transfer Counter 14-35 Add notes to Continuous Operation Mode 14-36 Correct the description of DRI Event Counters 19-2 Replace Figure 19.1.1 20-2 Replace Figure 20.1.1 20-3 Correct the description of XIN Oscillation Stoppage Detection Circuit Replace Figure 20.1.2 Chap. 23 Add electrical characteristics of the 32195 and 32196 23-3, 4, Correct parameters of VIH and VIL 7, 8, 11, 12, 15, 16 23-5, 9, Correct parameters of VT+ and VT- (hysteresis) 13, 17 23-24 Add Note 1 to TIN 23-25, 47 Correct rated values of TCLK Add Note 1 to TCLK 23-29, 51 Add Note 1 to tw(WAITH) and tw(WAITL) 23-30, 52 Correct the note of Read Timing 23-46 Correct Note 1 of TIN Appendix Replace Dimensional Outline Drawing 1-2 Appendix Add 224 pin FBGA (PLBG0224GA-A) 1-3 Appendix4 Add correction of notes

 Guide to Understanding the Register Table (1) Bit number: Indicates a register’s bit number. (2) Register border: The registers enclosed with thick border lines must be accessed in halfwords or words. (3) Status after reset: The initial state of each register after reset is indicated in hexadecimal or binary. (4) Status after reset: The initial state of each register after reset is indicated bitwise. 0: This bit is “0” after reset. 1: This bit is “1” after reset. ?: This bit is undefined after reset. (5) The shaded bits mean that they have no functions assigned. (6) Read conditions: R: This bit can be accessed for read. ?: The value read from this bit is undefined. (Reading this bit has no effect.) 0: The value read from this bit is always “0”. 1: The value read from this bit is always “1”. (7) Write conditions: W: This bit can be accessed for write. N: This bit is write protected. 0: To write to this bit, always write “0”. 1: To write to this bit, always write “1”. –: Writing to this bit has no effect. (It does not matter whether this bit is set to “0” or “1” by writing in software.) Note: Care must be taken when writing to this bit. See Note in each register table. XXXRegister(XXX) <Address: H’XXXX XXXX> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 AAA BBB CCC 000 0 0 0 0 0 0 0 0 0 0 0 0 0 <After reset: H’0000> b Bit name Function R W 3–15 No function assigned. Fix to “0”. 0 0 Note 1: Only writing “0” is effective. Writing “1” has no effect, in which case the bit retains the value it had before the write.  Notation of active-low pins (signals) The symbol “#” suffixed to the pin (or signal) names means that the pins (or signals) are active-low. Before Use (2) (4) (6) (7) (3) (1) (5)

Contents-132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table of Contents CHAPTER 1 OVERVIEW CHAPTER 2 CPU CHAPTER 3 ADDRESS SPACE

Contents-232192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CHAPTER 4 EIT CHAPTER 5 INTERRUPT CONTROLLER (ICU)

Contents-332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CHAPTER 6 INTERNAL MEMORY CHAPTER 7 RESET CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

Contents-432192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CHAPTER 9 DMAC CHAPTER 10 MULTIJUNCTION TIMERS

Contents-532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

Contents-632192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 10.8.19 0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes ---10-188 CHAPTER 11 A/D CONVERTER

Contents-732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CHAPTER 12 SERIAL INTERFACE

Contents-832192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CHAPTER 13 CAN MODULE

Contents-932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CHAPTER 14 DIRECT RAM INTERFACE (DRI) CHAPTER 15 REAL TIME DEBUGGER (RTD) CHAPTER 16 NON-BREAK DEBUG (NBD)

Contents-1032192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CHAPTER 17 EXTERNAL BUS INTERFACE CHAPTER 18 WAIT CONTROLLER CHAPTER 19 RAM BACKUP MODE CHAPTER 20 OSCILLATOR CIRCUIT

Contents-1132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CHAPTER 21 JTAG CHAPTER 22 POWER SUPPLY CIRCUIT CHAPTER 23 ELECTRICAL CHARACTERISTICS

Contents-1232192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 APPENDIX 1 MECHANICAL SPECIFICAITONS APPENDIX 2 INSTRUCTION PROCESSING TIME APPENDIX 3 PROCESSING OF UNUSED PINS APPENDIX 4 SUMMARY OF PRECAUTIONS Appendix 4.9.16 0% or 100% Duty-Cycle Wave Output during PWM Output and

Contents-1332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

Contents-1432192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 To be written at a later time.

1.1 Outline of the 32192/32195/32196 Group

1.2 Block Diagram

1.3 Pin Functions

1.4 Pin Assignments

32192/32195/32196 Group Hardware Manual OVERVIEW Rev.1.10 REJ09B0123-0110 Apr.06.07 The 32192/32195/32196 Group (hereinafter simply the 32192/32195/32196) belongs to the M32R/ECU Series in the M32R Family of Renesas microcomputers. For details about the current development status of the 32192/32195/32196, please contact your nearest office of Renesas or its distributor. Table 1.1.1 Product List Type Name ROM RAM Frequency Power supply voltage Temperature Range capacity capacity at single-supply at double-supply (Note 1) M32192F8VFP 1 Mbytes 176 Kbytes 128 MHz 3.3V 5V, 3.3V –40°C to 125°C M32192F8UFP 1 Mbytes 176 Kbytes 160 MHz 3.3V 5V, 3.3V –40°C to 105°C M32192F8TFP 1 Mbytes 176 Kbytes 160 MHz 5V or 3.3V 5V, 3.3V –40°C to 85°C M32192F8VWG 1 Mbytes 176 Kbytes 128 MHz 3.3V 5V, 3.3V –40°C to 125°C M32192F8UWG 1 Mbytes 176 Kbytes 160 MHz 3.3V 5V, 3.3V –40°C to 105°C M32192F8TWG 1 Mbytes 176 Kbytes 160 MHz 5V or 3.3V 5V, 3.3V –40°C to 85°C M32195F4VFP 512 Kbytes 32 Kbytes 128 MHz 3.3V 5V, 3.3V –40°C to 125°C M32195F4UFP 512 Kbytes 32 Kbytes 160 MHz 3.3V 5V, 3.3V –40°C to 105°C M32195F4TFP 512 Kbytes 32 Kbytes 160 MHz 5V or 3.3V 5V, 3.3V –40°C to 85°C M32196F8VFP 1 Mbytes 64 Kbytes 128 MHz 3.3V 5V, 3.3V –40°C to 125°C M32196F8UFP 1 Mbytes 64 Kbytes 160 MHz 3.3V 5V, 3.3V –40°C to 105°C M32196F8TFP 1 Mbytes 64 Kbytes 160 MHz 5V or 3.3V 5V, 3.3V –40°C to 85°C Note 1: This does not guarantee continuous operation and there is a limitation on the length of use (temperature profile).

1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU)

(1) Based on a RISC architecture

• The 32192/32195/32196 is a group of 32-bit RISC single-chip microcomputers. The M32R-FPU in this group of microcomputers incorporates a fully IEEE 754-compliant, single-precision FPU in order to materialize the common instruction set and the high-precision arithmetic operation of the M32R CPU. The 32192/32195/32196 products listed in the above table are built around the M32R-FPU and incorporates flash memory, RAM and various peripheral functions, all integrated into a single chip.
• The M32R-FPU is constructed based on a RISC architecture. Memory is accessed using load/store instruc- tions, and various arithmetic/logic operations are executed using register-to-register operation instructions.
• The M32R-FPU internally contains sixteen 32-bit general-purpose registers. The instruction set con- sists of 100 discrete instructions in total (83 instructions common to the M32R Family plus 17 FPU and extended instructions). These instructions are either 16 bits or 32 bits long.
• In addition to the ordinary load/store instructions, the M32R-FPU supports compound instructions such as Load & Address Update and Store & Address Update. These instructions help to speed up data transfers. (2) Six-stage pipelined processing
• The M32R-FPU supports six-stage pipelined instruction processing. Not just load/store instructions and register-to-register operation instructions, but also floating-point arithmetic instructions and compound instructions such as Load & Address Update and Store & Address Update are executed in one CPUCLK period (which is equivalent to 6.25 ns when f(CPUCLK) = 160 MHz).
• Although instructions are supplied to the execution stage in the order in which they were fetched, it is possible that if the load/store instruction supplied first is extended by wait cycles inserted in memory access, the subsequent register-to-register operation instruction will be executed before that instruction. Using such a facility, which is known as the “out-of-order-completion” mechanism, the M32R-FPU is able to control instruction execution without wasting clock cycles.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (3) Compact instruction code

• The M32R-FPU supports two instruction formats: one 16 bits long, and one 32 bits long. Use of the 16-bit instruction format especially helps to suppress the code size of a program.
• Moreover, the availability of 32-bit instructions makes programming easier and provides higher per- formance at the same clock speed than in architectures where the address space is segmented. For example, some 32-bit instructions allow control to jump to an address 32 Mbytes forward or back- ward from the currently executed address in one instruction, making programming easy.

1.1.2 Built-in Multiplier/Accumulator

(1) Built-in high-speed multiplier

• The M32R-FPU contains a 32 bits × 16 bits high-speed multiplier which enables the M32R-FPU to execute a 32 bits × 32 bits integral multiplication instruction in three CPUCLK periods. (2) DSP-comparable multiply-accumulate instructions
• The M32R-FPU supports the following four types of multiply-accumulate instructions (or multiplication instructions) which each can be executed in one CPUCLK period using a 56-bit accumulator. (1) 16 high-order bits of register × 16 high-order bits of register (2) 16 low-order bits of register × 16 low-order bits of register (3) All 32 bits of register × 16 high-order bits of register (4) All 32 bits of register × 16 low-order bits of register
• The M32R-FPU has some special instructions to round the value stored in the accumulator to 16 or 32 bits or shift the accumulator value before storing in a register to have its digits adjusted. Because these instructions too are executed in one CPUCLK period, when used in combination with high- speed data transfer instructions such as Load & Address Update or Store & Address Update, they enable the M32R-FPU to exhibit superior data processing capability comparable to that of a DSP.

1.1.3 Built-in Single-precision FPU

• The M32R-FPU supports single-precision floating-point arithmetic fully compliant with IEEE 754 standards. Specifically, five exceptions specified in IEEE 754 standards (Inexact, Underflow, Divi- sion by Zero, Overflow and Invalid Operation) and four rounding modes (round to nearest, round toward 0, round toward + Infinity and round toward – Infinity) are supported. What’s more, because general-purpose registers are used to perform floating-point arithmetic, the overhead associated with transferring the operand data can be reduced.

1.1.4 Built-in Flash Memory and RAM

• The 32192/32195/32196 contains a RAM that can be accessed with zero wait state, allowing to design a high-speed embedded system.
• The internal flash memory can be written to while mounted on a printed circuit board (on-board writing). Use of flash memory facilitates development work, because the chip used at the develop- ment stage can be used directly in mass-production, allowing for a smooth transition from prototype to mass-production without the need to change the printed circuit board.
• The internal flash memory can be rewritten as many as 100 times.

32192/32195/32196 Group Hardware Manual OVERVIEW Rev.1.10 REJ09B0123-0110 Apr.06.07

• The internal flash memory has a virtual flash emulation function, allowing the internal RAM to be superficially mapped into part of the internal flash memory. When combined with the internal Real- Time Debugger (RTD) and the M32R family’s common debug interface (Scalable Debug Interface or SDI), this function makes the ROM table data tuning easy.
• The internal RAM can be accessed for reading or rewriting data from an external device indepen- dently of the M32R-FPU by using the Real-Time Debugger. The external device is communicated using the Real-Time Debugger’s exclusive clock-synchronous serial interface.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

1.1.5 Built-in Clock Frequency Multiplier

• The 32192/32195/32196 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1 below. PLL CLKO SEL CLKOUT(external bus clock) (32MHz-40MHz or 16MHz-20MHz) XIN pin (16MHz-20MHz) BCLK (peripheral clock) (32MHz-40MHz) CPUCLK (CPU clock) (128MHz-160MHz) Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier Table 1.1.2 Clock Functional Block Features CPUCLK • CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for the M32R-FPU core, internal flash memory and internal RAM. BCLK • Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency for the internal peripheral I/O and external data bus. Clock output • BCLK pin output: A clock with the same frequency as f(BCLK) is output from this pin.
• CLKOUT pin output: A clock with the same or half frequency as f(BCLK) is output from this pin.

1.1.6 Powerful Peripheral Functions Built-in

(1) 8-level interrupt controller (ICU) (2) 10-channel DMAC (3) 55-channel multijunction timer (MJT) (4) 16-channel A/D converter (ADC) (5) 6-channel serial interface (SIO) (6) 2-channel Full-CAN (7) Direct RAM interface (DRI) (8) Real-time debugger (RTD) (9) Non-break debug (NBD) (10) Wait controller (11) M32R Family’s common debug function (Scalable Debug Interface or SDI)

32192/32195/32196 Group Hardware Manual OVERVIEW Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 1.2.1 shows a block diagram of the 32192 /32195 /32196. The features of each block are described in Table 1.2.1. Figure 1.2.1 Block Diagram of the 32192/32195/32196 M32R-FPU Core (Max. 160MHz) Non-Break Debug (NBD) Direct RAM Interface (DRI) Multiplier/Accumulator (32 bits x 16 bits + 56 bits) Single-precision FPU (fully IEEE 754 compliant) Internal 32-bit bus Internal 32-bit busInternal Flash Memory (M32192F8: 1 Mbyte) (M32195F4: 512 Kbytes) (M32196F8: 1 Mbyte) Internal RAM (M32192F8: 176 Kbytes) (M32195F4: 32 Kbytes) (M32196F8: 64 Kbytes)PLL Clock Generator Internal Power Supply Generator (VDC) AddressData External Bus Interface Input/output ports, 97 lines Real-Time Debugger (RTD) Internal Bus Interface DMAC (10 channels) Multijunction Timer (MJT: 55 channels) A/D Converter (A/D0: 10-bit converter, 16 channels) Serial Interface (6 channels) Interrupt Controller (8 levels)Internal 16-bit bus Wait Controller Full CAN (2 channels)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 1.2.1 Features of the 32192/32195/32196 (1/3) Functional Block Features M32R-FPU CPU core • Implementation: Six-stage pipelined instruction processing

• Internal 32-bit structure of the core
• Register configuration General-purpose registers: 32 bits × 16 registers Control registers: 32 bits × 6 registers
• Instruction set 16-bit and 32-bit instruction formats 100 discrete instructions and six addressing modes
• Internal multiplier/accumulator (32 bits × 16 bits + 56 bits)
• Internal single-precision floating-point arithmetic unit (FPU) Internal Flash memory • Capacity: M32192F8 : 1 Mbyte M32195F4 : 512 Kbytes M32196F8 : 1 Mbyte
• One wait access
• Durability: Rewritable 100 times Internal RAM • Capacity: M32192F8 : 176 Kbytes M32195F4 : 32 Kbytes M32196F8 : 64 Kbytes
• Zero wait access
• The internal RAM can be accessed for reading or rewriting data from the outside independently of the M32R-FPU by using the Real-Time Debugger, without ever causing the CPU performance to decrease.
• By using RAM backup mode, a part of internal RAM area can be backed up when turn off the power supply. Bus specification • Fundamental bus cycle: 6.25 ns (when f(CPUCLK) = 160 MHz)
• Logical address space : 4 Gbytes linear
• Internal bus specification : Internal 32-bit data bus (for CPU <-> internal flash memory and RAM access) (or accessed in 64 bits when accessing the internal flash memory for instructions) : Internal 16-bit data bus (for internal peripheral I/O access)
• External extension area: During processor mode: maximum 32 Mbytes During external extension mode: maximum 31 Mbytes (7 Mbytes + 8 Mbytes × 3 blocks)
• External data address: 22-bit address
• External data bus: 16-bit data bus
• Shortest external bus access: 1 CLKOUT during read, 1 CLKOUT during write Multijunction timer (MJT) • 55-channel multi-functional timer 16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels, 16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels, 16-bit input related up/down timer × 2 channels, and 24-bit output related timer × 16 channels
• Flexible timer configuration is possible by interconnecting these timer channels.
• Interrupt request: Counter underflow or overflow and rising or falling or both edges or “H” or “L” level from the TIN pin (TIN pin can be used as external interrupt inputs irrespective of timer operation.)
• DMA transfer request: Counter underflow or overflow and rising or falling or both edges or “H” or “L” level from the TIN pin (TIN pin can be used as DMA transfer request inputs irrespective of timer operation.) DMAC • Number of channels: 10
• Transfers between internal peripheral I/Os or internal RAMs or between internal peripheral I/O and internal RAM are supported.
• Capable of advanced DMA transfers when used in combination with internal peripheral I/O
• Transfer request: Software or internal peripheral I/O (A/D converter, MJT, serial interface or CAN)
• DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a transfer on another channel.)
• Interrupt request: DMA transfer counter register underflow

32192/32195/32196 Group Hardware Manual OVERVIEW Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 1.2.1 Features of the 32192/32195/32196 (2/3) A/D Converter (ADC) • 16 channels: 10-bit resolution A/D converter × 1 block

• Conversion modes: In addition to ordinary A/D conversion mode, comparator mode and 2-channel simultaneous sampling mode.
• Operation modes: Single conversion mode and n-channel scan mode (n = 1–16)
• Sample-and-hold function: Performs A/D conversion with the analog input voltages sampled at start of A/D conversion.
• A/D disconnection detection assist function: Suppresses effects of the analog input voltage leakage from the preceding channel during A/D conversion.
• An inflow current bypass circuit is built-in.
• Can generate an interrupt or start DMA transfer upon completion of A/D conversion.
• Either 8-bit or 10-bit conversion results can be read out.
• Interrupt request: Completion of A/D conversion
• DMA transfer request: Completion of A/D conversion Serial Interface (SIO) • 6-channel serial interface
• Can be chosen to be clock-synchronous serial interface or clock-asynchronous serial interface.
• Data can be transferred at high speed (5 Mbits per second during clock-synchronous mode or 2.5 Mbits per second during clock-asynchronous mode when f(BCLK) = 40 MHz).
• Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed
• DMA transfer request: Reception completed or transmit buffer empty CAN • 32 message slots × 2 blocks
• Compliant with CAN specification 2.0B active.
• Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off or single shot
• DMA transfer request: Failed to send, transmission completed or reception completed Real-Time Debugger • Internal RAM can be rewritten or monitored independently of the CPU by entering a command (RTD) from the outside.
• Comes with exclusive clock-synchronous serial ports.
• Interrupt request: RTD interrupt command input Non-Break Debug • Can access to all resources on the address map from the outside (NBD) • Clock-synchronous parallel interface (4-bit)
• Event output function
• RAM monitor function Direct RAM Interface • Can control capture of clock-synchronous parallel data to the internal RAM independently of the CPU (DRI) • Clock-synchronous parallel input (8-bit, 16-bit or 32-bit)
• Maximum transfer rate: 40 Mbytes/s (when f(CPUCLK)=160 MHz) Interrupt Controller (ICU) • Controls interrupt requests from the internal peripheral I/O.
• Supports 8-level interrupt priority including an interrupt disabled state.
• External interrupt: 27 sources (SBI#, TIN0, TIN3–TIN11, TIN16–TIN27, TIN30–TIN33)
• TIN pin input sensing: Rising, falling or both edges or “H” or “L” level Wait Controller • Controls wait states for access to the external extension area.
• Insertion of 0–15 wait states by setting up in software + wait state extension by entering WAIT# signal PLL • A multiply-by-8 clock generating circuit Clock • Maximum external input clock frequency (XIN) is 20.0 MHz. (Note 1)
• CPUCLK: Operating clock for the M32R-FPU core, internal flash memory and internal RAM The maximum CPU clock is 160 MHz (when f(XIN) = 20 MHz).
• BCLK: Operating clock for the internal peripheral I/O and external data bus The maximum peripheral clock is 40 MHz (peripheral module access when f(XIN) = 20 MHz).
• BCLK pin output: A clock with the same frequency as f(BCLK) is output from this pin.
• CLKOUT pin output: A clock with the same or half frequency as f(BCLK) is output from this pin.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 JTAG • Boundary scan function VDC • Internal power supply generating circuit: Generates the internal power supply from an external power supply (5 or 3.3 V). Ports • Input/output pin: 97 pins

• The port input threshold can be set in a program to one of three levels individually for each port group (with or without Schmitt circuit, selectable). Note 1: The maximum external input clock frequency (XIN) for the M32192F8VFP, M32195F4VFP, and M32196F8VFP are 16.0 MHz. Table 1.2.1 Features of the 32192/32195/32196 (3/3)

32192/32195/32196 Group Hardware Manual OVERVIEW Rev.1.10 REJ09B0123-0110 Apr.06.07 scribed in Table 1.3.1. M32192 F8xFP, M3219 5F4xFP, M3219 6F8xFP Note 1: MOD2 must be connected to the ground (GND). Notes: . The symbol "#" suffixed to the pin (or signal) name means that the pins (or signals) are "L." . : operates with VCCE power supply : operates with VCC-BUS power supply XIN Clock Multi- junction timer Multi- junction timer Data bus DRI NBD Address bus Reset Port 0 Port 1 Port 2 Port 3 Multi- junction timer Multi- junction timer Serial Interface CAN Address bus Bus control Bus control/ Clock Real time debugger Port 4 Port 7 Flash Interrupt controller Mode A/D converter XOUT RESET# MOD0 MOD1 MOD2 (Note 1) FP Port 6 P61-P63 P70/CLKOUT/WR#/BCLK P71/WAIT# P72/HREQ#/TIN27 P73/HACK#/TIN26 P74/RTDTXD/TXD3/NBDD0 P75/RTDRXD/RXD3/NBDD1 P76/RTDACK/CTX1/NBDD2 P77/RTDCLK/CRX1/NBDD3 Port 8 Power supply P82/TXD0/TO26 P83/RXD0/TO25 P84/SCLKI0/SCLKO0/TO24 P85/TXD1/TO23 P86/RXD1/TO22 P87/SCLKI1/SCLKO1/TO21 VCCE EXCVCC VCC-BUS VDDE EXCVDD VSS SBI# AD0IN0-AD0IN15 AVCC0 AVSS0 VREF0 P93/TO16/SCLKI5/SCLKO5 P94/TO17/TXD5/DD15 P96/TO19/DD13 P97/TO20/DD12 P100/TO8 P41/BLW#/BLE# P42/BHW#/BHE# P43/RD# P44/CS0#/TIN8, P45/CS1#/TIN9 P46/A13/TIN10, P47/A14/TIN11 P00/DB0/TO21/DD0- P07/DB7/TO28/DD7 P10/DB8/TO29/DD8- P17/DB15/TO36/DD15 P20/A23/DD24- P27/A30/DD31 P30/A15/TIN4/DD16- P33/A18/TIN7/DD19 Multi- junction timer Serial Interface Port 9 Multi- junction timer Serial Interface Serial Interface Address bus Bus control CAN Serial Interface CAN Serial Interface CAN/ Bus control NBD DRI DRI DRI Port 10 Port 13 Port 15 Bus control/ ClockAddress bus/ Bus control Port 11 Port 12 P130/TIN16/PWMOFF0/DIN0 P131/TIN17/PWMOFF1/DIN1 P132/TIN18/DIN2 P133/TIN19/DIN3 P134/TIN20/TXD3/DIN4 P135/TIN21/RXD3 P136/TIN22/CRX1 P137/TIN23/CTX1 P150/TIN0/CLKOUT/WR# P153/TIN3/WAIT# P95/TO18/RXD5/DD14 P107/TO15/RXD4/DD0 P110/TO0/TO29/DD11- P117/TO7/TO36/DD4 P124/TCLK0/A9/DD3 P125/TCLK1/A10/DD2 P34/A19/TIN30/DD20- P37/A22/TIN33/DD23 P101/TO9/CRX0 P102/TO10/CTX0 P103/TO11/TIN24 P104/TO12/TIN25/DD3 P105/TO13/SCLKI4/SCLKO4/DD2 P106/TO14/TXD4/DD1 P126/TCLK2/CS2#/DD1 P127/TCLK3/CS3#/DD0 Port 22 JTAG P220/CTX0/HACK# P221/CRX0/HREQ# P224/A11/CS2# JTRST JTMS JTCK/NBDCLK JTDO/NBDEVNT# JTDI/NBDSYNC# P225/A12/CS3# Port 17 P174/TXD2/TO28 P175/RXD2/TO27 VCCER VCCE VCCEVCC-BUSVCCE VCC-BUSVCCE VCC-BUS VCC-BUS VCCE VCC-BUS VCCE Figure 1.3.1 Pin Function Diagram (144pin LQFP)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 1.3.2 Pin Function Diagram (224pin FBGA) M32192 F8xWG Note 1: MOD2 must be connected to the ground (GND). Note 2: THERMAL BALL must be connected to the ground (GND). Notes: . The symbol "#" suffixed to the pin (or signal) name means that the pins (or signals) are "L." . : operates with VCCE power supply : operates with VCC-BUS power supply XIN Clock Multi- junction timer Multi- junction timer Data bus DRI NBD Address bus Reset Port 0 Port 1 Port 2 Port 3 Multi- junction timer Multi- junction timer Serial Interface CAN Address bus Bus control Bus control/ Clock Real time debugger Port 4 Port 7 Flash Interrupt controller Mode A/D converter XOUT RESET# MOD0 MOD1 MOD2 (Note 1) FP Port 6 P61-P63 P70/CLKOUT/WR#/BCLK P71/WAIT# P72/HREQ#/TIN27 P73/HACK#/TIN26 P74/RTDTXD/TXD3/NBDD0 P75/RTDRXD/RXD3/NBDD1 P76/RTDACK/CTX1/NBDD2 P77/RTDCLK/CRX1/NBDD3 Port 8 Power supply P82/TXD0/TO26 P83/RXD0/TO25 P84/SCLKI0/SCLKO0/TO24 P85/TXD1/TO23 P86/RXD1/TO22 P87/SCLKI1/SCLKO1/TO21 VCCE EXCVCC VCC-BUS VDDE EXCVDD VSS THERMAL-BALL (Note 2) SBI# AD0IN0-AD0IN15 AVCC0 AVSS0 VREF0 P93/TO16/SCLKI5/SCLKO5 P94/TO17/TXD5/DD15 P96/TO19/DD13 P97/TO20/DD12 P100/TO8 P41/BLW#/BLE# P42/BHW#/BHE# P43/RD# P44/CS0#/TIN8, P45/CS1#/TIN9 P46/A13/TIN10, P47/A14/TIN11 P00/DB0/TO21/DD0- P07/DB7/TO28/DD7 P10/DB8/TO29/DD8- P17/DB15/TO36/DD15 P20/A23/DD24- P27/A30/DD31 P30/A15/TIN4/DD16- P33/A18/TIN7/DD19 Multi- junction timer Serial Interface Port 9 Multi- junction timer Serial Interface Serial Interface Address bus Bus control CAN Serial Interface CAN Serial Interface CAN/ Bus control NBD DRI DRI DRI Port 10 Port 13 Port 15 Bus control/ ClockAddress bus/ Bus control Port 11 Port 12 P130/TIN16/PWMOFF0/DIN0 P131/TIN17/PWMOFF1/DIN1 P132/TIN18/DIN2 P133/TIN19/DIN3 P134/TIN20/TXD3/DIN4 P135/TIN21/RXD3 P136/TIN22/CRX1 P137/TIN23/CTX1 P150/TIN0/CLKOUT/WR# P153/TIN3/WAIT# P95/TO18/RXD5/DD14 P107/TO15/RXD4/DD0 P110/TO0/TO29/DD11- P117/TO7/TO36/DD4 P124/TCLK0/A9/DD3 P125/TCLK1/A10/DD2 P34/A19/TIN30/DD20- P37/A22/TIN33/DD23 P101/TO9/CRX0 P102/TO10/CTX0 P103/TO11/TIN24 P104/TO12/TIN25/DD3 P105/TO13/SCLKI4/SCLKO4/DD2 P106/TO14/TXD4/DD1 P126/TCLK2/CS2#/DD1 P127/TCLK3/CS3#/DD0 Port 22 JTAG P220/CTX0/HACK# P221/CRX0/HREQ# P224/A11/CS2# JTRST JTMS JTCK/NBDCLK JTDO/NBDEVNT# JTDI/NBDSYNC# P225/A12/CS3# Port 17 P174/TXD2/TO28 P175/RXD2/TO27 VCCER VCCE VCCEVCC-BUSVCCE VCC-BUSVCCE VCC-BUS VCC-BUS VCCE VCC-BUS VCCE

32192/32195/32196 Group Hardware Manual OVERVIEW Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 1.3.1 Description of Pin Functions (1/3) Type Pin Name Signal Name Input/Output Description Power supply VCCER Internal power – Power supply input for the internal voltage generator circuit VCCE Port/internal – Power supply input for the port and internal peripheral I/O power supply input Apply same voltage to the all VCCE pins. VCC-BUS Port/bus interface – Power supply input for the port and bus interface pins input Apply same voltage to the all VCC-BUS pins. VDDE RAM power supply – Backup power supply input for the internal RAM (5.0 V ± 0.5 V input or 3.3 V ± 0.3 V). VSS Ground – Connect all VSS pins to ground (GND). THERMAL- THERMAL BALL – Connect THERMAL BALL to the ground (GND). BALL(Note 2) EXCVCC VCCER control – This pin connects an external capacitor for the internal voltage generator circuit. EXCVDD VDDE control – This pin connects an external capacitor for the internal power supply of the internal RAM. Clock XIN, Clock input Input These are clock input/output pins. Including a PLL-based ×8 XOUT Clock output Output frequency multiplier, they input 1/8 of the CPU clock frequency. (XIN input is 20 MHz when f(CPUCLK) = 160 MHz.) CLKOUT, System clock Output The CLKOUT pin outputs a clock that is equal to the external BCLK input clock frequency, XIN (i.e., CLKOUT output is 20 MHz when f(CPUCLK) = 160 MHz), or two times of XIN (i.e., CLKOUT output is 40 MHz when f(CPUCLK) = 160 MHz). (It is used when operationg synchronous setting in external) This clock is used when operations are synchronous external to the chip.The BCLK pin outputs a clock that is two times the external input clock frequency, XIN (i.e., BCLK output is 40 MHz when f(CPUCLK) = 160 MHz). Reset RESET# Reset Input Reset input pin for the internal circuit. Mode MOD0 − Mode Input Set the microcomputer’s operation mode. MOD2 MOD0 MOD1 MOD2 Mode L L L Single-chip mode L H L External extension mode H L L Processor mode (boot mode) (Note 1) H H L (Settings inhibited) X X H (Settings inhibited) X: Don’t care Flash protect FP Flash protect Input This special pin protects the flash memory against rewrites in hardware. Address bus A9–A30 Address bus Output Twenty-two address lines (A9–A30) are included, allowing four blocks each up to 8 Mbyte memory space to be connectedexternal to the chip. A31 is not output. Note 1: Boot mode requires that the FP pin should be at the “H” level. For details about boot mode, see Chapter 6, “Internal Memory.” Note 2: THERMAL BALL has a pin only in the M32192F8xWG.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 1.3.1 Description of Pin Functions (2/3) Type Pin Name Signal Name Input/Output Description Data bus DB0–DB15 Data bus Input/output This 16-bit data bus is used to connect external devices. When writing in byte units during a write cycle, the output data at the invalid byte position is undefined. During a read cycle, data on the entire 16-bit bus is always read in. However, only the data at the valid byte position is transferred into the internal circuit. Bus control CS0#–CS3# Chip select Output These are chip select signals for external devices. RD# Read Output This signal is output when reading an external device. WR# Write Output This signal is output when writing to an external device. BHW#/BLW# Byte high/low write Output When writing to an external device, this signal indicates the valid byte position to which data is transferred. BHW# and BLW# correspond to the upper address side (bits 0–7 are valid) and the lower address side (bits 8–15 are valid), respectively. BHE# Byte high enable Output During an external device access, this signal indicates that the high-order data (bits 0–7) is valid. BLE# Byte low enable Output During an external device access, this signal indicates that the low-order data (bits 8–15) is valid. WAIT# Wait Input When accessing an external device, a “L” level input on WAIT# pin extends the wait cycle. HREQ# Hold request Input This input pin is used by an external device to request control of the external bus. A “L” level input on HREQ# pin places the CPU in a hold state. HACK# Hold acknowledge Output This signal notifies that the CPU has entered a hold state and relinquished control of the external bus. Multijunction TIN0, Timer input Input Input pins for the multijunction timer. timer TIN3–TIN11, TIN16–TIN27, TIN30–TIN33 TO0–TO36 Timer output Output Output pins for the multijunction timer. TCLK0 Timer clock Input Clock input pins for the multijunction timer. –TCLK3 A/D converter AVCC0 Analog power – AVCC0 is the power supply input for the A/D0 converter. supply input C onnect AVCC0 to the power supply rail. AVSS0 Analog ground – AVSS0 is the analog ground for the A/D0 converter. Connect AVSS0 to ground. AD0IN0 Analog input Input 16-channel analog input pins for the A/D0 converter. –AD0IN15 VREF0 Reference voltage Input VREF0 is the reference voltage input pin for the A/D0 input converter. Interrupt SBI# System break Input This is the system break interrupt (SBI) input pin for the controller interrupt interrupt controller. Serial interface SCLKI0/ UART transmit/ Input/output When channel is in UART mode: SCLKO0, receive clock output This pin outputs a clock derived from BRG output by SCLKI1/ or CSIO transmit/ dividing it by 2. SCLKO1, receive clock When channel is in CSIO mode: SCLKI4/ input/output This pin inputs a transmit/receive clock when external SCLKO4, clock is selected or outputs a transmit/receive clock SCLKI5/ when internal clock is selected. SCLKO5

32192/32195/32196 Group Hardware Manual OVERVIEW Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 1.3.1 Description of Pin Functions (3/3) Type Pin Name Signal Name Input/Output Description Serial interface TXD0–TXD5 Transmit data Output Transmit data output pin for serial interface. RXD0–RXD5 Received data Input Received data input pin for serial interface. Real-time RTDTXD RTD transmit data Output Serial data output pin for the real-time debugger. debugger RTDRXD RTD received data Input Serial data input pin for the real-time debugger. (RTD) RTDCLK RTD clock input Input Serial data transmit/receive clock input pin for the real-time debugger. RTDACK RTD acknowledge Output A “L” level pulse is output from this pin synchronously with the start clock for the real-time debugger’s serial data output word. The “L” level pulse width indicates the type of command/ data received by the real-time debugger. CAN CTX0, CTX1 Transmit data Output This pin outputs data from the CAN module. CRX0, CRX1 Received data Input This pin inputs the data for the CAN module. JTAG JTMS Test mode select Input Test mode select input to control the state transition of the test circuit. JTCK Test clock Input Clock input for the debug module and test circuit. JTRST Test reset Input Test reset input to initialize the test circuit asynchronously with device operation. JTDI Test data input Input This pin inputs the test instruction code or test data that is serially received. JTDO Test data output Output This pin outputs the test instruction code or test data serially. NBD NBDD0 Command/ Input/output NBD command, address, and data input/output pins. –NBDD3 Address/Data NBDCLK Synchronous clock Input NBD synchronous clock input pin. input NBDSYNC# Top of data input Input Input pin to control the start position of NBD data. NBDEVNT# Event output Output Output pin used for event output when an NBD event occurs. DRI DD0–DD31 DD input Input DRI data input pin. DIN0–DIN4 DIN input Input DRI event input pin. Input/output P00–P07 Input/output port 0 Input/output Programmable input/output port. ports P10–P17 Input/output port 1 Input/output (Note 1) P20–P27 Input/output port 2 Input/output P30–P37 Input/output port 3 Input/output P41–P47 Input/output port 4 Input/output P61–P63 Input/output port 6 Input/output P70–P77 Input/output port 7 Input/output P82–P87 Input/output port 8 Input/output P93–P97 Input/output port 9 Input/output P100–P107 Input/output port 10 Input/output P110–P117 Input/output port 11 Input/output P124–P127 Input/output port 12 Input/output P130–P137 Input/output port 13 Input/output P150, P153 Input/output port 15 Input/output P174, P175 Input/output port 17 Input/output P220, Input/output port 22 Input/output P221 (Note 2), P224, P225 Note 1: Input/output ports 5, 14, 16 and 18 −21 are nonexistent. Note 2: P221 is input-only port.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 1.4.1 Pin Assignment Diagram of the M32192F8xFP, M32195F4xFP, and M32196F8xFP (Top View) M32192F8xFP M32195F4xFP M32196F8xFP 108 107 106 105 104 103 102 101 100 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VSS P87/SCLKI1/SCLKO1/TO21 P86/RXD1/TO22 P85/TXD1/TO23 P84/SCLKI0/SCLKO0/TO24 P83/RXD0/TO25 P82/TXD0/TO26 VCCER P175/RXD2/TO27 P174/TXD2/TO28 VSS EXCVCC AVSS0 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 AVCC0 VREF0 P17/DB15/TO36/DD15 P16/DB14/TO35/DD14 P15/DB13/TO34/DD13 P14/DB12/TO33/DD12 P13/DB11/TO32/DD11 P221/CRX0/HREQ# P225/A12/CS3# VSS XIN XOUT VCC-BUS P224/A11/CS2# P30/A15/TIN4/DD16 P31/A16/TIN5/DD17 P32/A17/TIN6/DD18 P33/A18/TIN7/DD19 P34/A19/TIN30/DD20 P35/A20/TIN31/DD21 P36/A21/TIN32/DD22 P37/A22/TIN33/DD23 P20/A23/DD24 P21/A24/DD25 P22/A25/DD26 P23/A26/DD27 VCC-BUS VSS P24/A27/DD28 P25/A28/DD29 P26/A29/DD30 P27/A30/DD31 P00/DB0/TO21/DD0 P01/DB1/TO22/DD1 P02/DB2/TO23/DD2 P03/DB3/TO24/DD3 P04/DB4/TO25/DD4 P05/DB5/TO26/DD5 P06/DB6/TO27/DD6 P07/DB7/TO28/DD7 P10/DB8/TO29/DD8 P11/DB9/TO30/DD9 P12/DB10/TO31/DD10 JTMS JTCK/NBDCLK JTRST JTDO/NBDEVNT# JTDI/NBDSYNC# P103/TO11/TIN24 P104/TO12/TIN25/DD3 P105/TO13/SCLKI4/SCLKO4/DD2 P106/TO14/TXD4/DD1 P107/TO15/RXD4/DD0 P124/TCLK0/A9/DD3 P125/TCLK1/A10/DD2 P126/TCLK2/CS2#/DD1 P127/TCLK3/CS3#/DD0 MOD2(Note 1) P130/TIN16/PWMOFF0/DIN0 P131/TIN17/PWMOFF1/DIN1 P132/TIN18/DIN2 P133/TIN19/DIN3 P134/TIN20/TXD3/DIN4 P135/TIN21/RXD3 P136/TIN22/CRX1 P137/TIN23/CTX1 VCCE P150/TIN0/CLKOUT/WR# P153/TIN3/WAIT# P41/BLW#/BLE# P42/BHW#/BHE# EXCVCC VSS P43/RD# P44/CS0#/TIN8 P45/CS1#/TIN9 P46/A13/TIN10 P47/A14/TIN11 P220/CTX0/HACK# VDDE P102/TO10/CTX0 P101/TO9/CRX0 P100/TO8 P117/TO7/TO36/DD4 P116/TO6/TO35/DD5 P115/TO5/TO34/DD6 P114/TO4/TO33/DD7 P113/TO3/TO32/DD8 P112/TO2/TO31/DD9 P111/TO1/TO30/DD10 P110/TO0/TO29/DD11 VSS VCCE FP MOD1 MOD0 RESET# P97/TO20/DD12 P96/TO19/DD13 P95/TO18/RXD5/DD14 P94/TO17/TXD5/DD15 P93/TO16/SCLKI5/SCLKO5 P77/RTDCLK/CRX1/NBDD3 P76/RTDACK/CTX1/NBDD2 P75/RTDRXD/RXD3/NBDD1 P74/RTDTXD/TXD3/NBDD0 P73/HACK#/TIN26 P72/HREQ#/TIN27 P71/WAIT# P70/CLKOUT/WR#/BCLK SBI# P63 P62 P61 EXCVDD Note 1: MOD2 must be connected to the ground (GND). Notes: • The symbol "#" suffixed to the pin (or signal) name means that the pins (or signals) are "L."  As for package dimension, refer to "Appendix1.1 Package Dimensional Outline Drawing."

32192/32195/32196 Group Hardware Manual OVERVIEW Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 1.4.2 Pin Assignment Diagram of the M32192F8xWG (Top View) VSS JTMS JTDO P103/TO11 P107/TO15 P150/TIN0 EXCVCC P45/CS1# VSS VDDE P100/TO8 JTRST JTDI /NBDSYNC# P153/TIN3 VSS P46/A13 /TIN10 P47/A14 /TIN11 P44/CS0# /TIN8 P31/A16 /TIN5/DD17 P35/A20 /TIN31/DD21 P20/A23 /DD24 P26/A29 /DD30 P02/DB2 /TO23/DD2 P17/DB15 /TO36/DD15 P221/CRX0 /WR# /DIN1 /PWMOFF1 MOD2 (Note 1) /TIN24 /RXD4/DD0 P126/TCLK2 /CS2#/DD1 P125/TCLK1 /A10/DD2 /WAIT# /CRX1 P132/TIN18 /DIN2 P133/TIN19 /DIN3 P127/TCLK3 /CS3#/DD0 /TXD4/DD1 P102/TO10 /CTX0 P101/TO9 /CRX0 P116/TO6 /TO35/DD5 JTCK VSS /DD2 P225/A12 P41/BLW# P43/RD# /SCLKI4 /SCLKO4 /BLE# XOUT P115/TO5 VSS P224/A11 /CS2# P34/A19 /TIN30/DD20 P37/A22 /TIN33/DD23 P23/A26 /DD27 P27/A30 /DD31 P03/DB3 /TO24/DD3 P06/DB6 /TO27/DD6 P11/DB9 /TO30/DD9XIN /TXD3/DIN4 P42/BHW# /BHE# VCCE P130/TIN16 /DIN0 /PWMOFF0 /TO34/DD6 P112/TO2 /TO31/DD9 P30/A15 /TIN4/DD16 P33/A18 /TIN7/DD19 P36/A21 /TIN32/DD22 P22/A25 /DD26 P24/A27 /DD28 P00/DB0 /TO21/DD0 P04/DB4 /TO25/DD4 P07/DB7 /TO28/DD7 P12/DB10 /TO31/DD10 P13/DB11 /TO32/DD11 P14/DB12 /TO33/DD12 VCCERVCC-BUS P114/TO4 /TO33/DD7 P110/TO0 /TO29/DD11 P94/TO17 /TXD5/DD15 P76/RTDACK /CTX1/NBDD2 P73/HACK# /TIN26 P70/CLKOUT /WR#/BCLK P86/RXD1 /TO22 P113/TO3 /TO32/DD8 P95/TO18 /RXD5/DD14 VCCE VSS MOD1 FP VCC-BUS MOD0 RESET# VSS VSS VSS /CRX1/NBDD3 /SCLKI5 /SCLKO5 P74/RTDTXD /TXD3/NBDD0 /RXD3/NBDD1 VREF0 AD0IN2 AD0IN6 AD0IN10 AD0IN15 VCCE P71/WAIT AVCC0 AD0IN3 AD0IN7 AD0IN11 AD0IN12AD0IN14 VSS /SCLKO1 /TO21 P63 SBI# EXCVDD AD0IN0 AD0IN4 AD0IN8 EXCVCC VCCER /SCLKO0 /TO24 P62 P61 VSS AD0IN1 AD0IN5 AD0IN9 AD0IN13 AVSS0 VSS CAD E FG H J KLM NPRB /CLKOUT P136 /TIN22 /CTX1 P137/TIN23 /RXD3 P135/TIN21 P131/TIN17 P134/TIN20 P106/TO14 /A9/DD3 P124/TCLK0 BALL THERMAL- BALL (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- /TO28 P174/TXD2 /TO26 P82/TXD0 /TO27 P175/RXD2 /TIN25/DD3 P104/TO12 /TO30/DD10 P111/TO1 /DD12 P97/TO20 /DD13 P96/TO19 /TO23 P85/TXD1 /TO25 P83/RXD0 P105/TO13 P93/TO16 P87/SCLKI1 P84/SCLK0 P75/RTDRXD /TIN27 P72/HREQ# P77/RTDCLK /NBDEVNT# TIN9 P220/CTX0 /HACK# /HREQ# /CS3# P32/A17 /TIN6/DD18 P21/A24 /DD25 P25/A28 /DD29 P01/DB1 /TO22/DD1 P05/DB5 /TO26/DD5 P10/DB8 /TO29/DD8 P15/DB13 /TO34/DD13 P16/DB14 /TO35/DD14 /NBDCLK P117/TO7 /TO36/DD4 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- BALL THERMAL- Package: 224pin FBGA Note 1: MOD2 must be connected to the ground (GND). Note 2: THERMAL BALL must be connected to the ground (GND). Note:  The symbol "#" suffixed to the pin (or signal) name means that the pins (or signals) are "L."

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Port Function 1 Function 2 DRI function NBD function Function Type State during reset State upon exiting reset

1 P221/CRX0/HREQ# P221 CRX0(Note 1) HREQ#(Note 1) - Input P221 Input Hi-Z Hi-Z

external extension modes P225 Input Hi-Z Hi-Z During processor mode A12 Output Hi-Z Undefined

3 VSS - VSS - - - - VSS - - -

4 XIN - XIN - - Input XIN Input - -

5 XOUT - XOUT - - Output XOUT Output XOUT XOUT

6 VCC-BUS - VCC-BUS - - - - VCC-BUS - - -

external extension modes P224 Input Hi-Z Hi-Z During processor mode A11 Output Hi-Z Undefined During single-chip and external extension modes P30 Input Hi-Z Hi-Z During processor mode A15 Output Hi-Z Undefined During single-chip and external extension modes P31 Input Hi-Z Hi-Z During processor mode A16 Output Hi-Z Undefined During single-chip and external extension modes P32 Input Hi-Z Hi-Z During processor mode A17 Output Hi-Z Undefined During single-chip and external extension modes P33 Input Hi-Z Hi-Z During processor mode A18 Output Hi-Z Undefined During single-chip and external extension modes P34 Input Hi-Z Hi-Z During processor mode A19 Output Hi-Z Undefined During single-chip and external extension modes P35 Input Hi-Z Hi-Z During processor mode A20 Output Hi-Z Undefined During single-chip and external extension modes P36 Input Hi-Z Hi-Z During processor mode A21 Output Hi-Z Undefined During single-chip and external extension modes P37 Input Hi-Z Hi-Z During processor mode A22 Output Hi-Z Undefined During single-chip and external extension modes P20 Input Hi-Z Hi-Z During processor mode A23 Output Hi-Z Undefined During single-chip and external extension modes P21 Input Hi-Z Hi-Z During processor mode A24 Output Hi-Z Undefined During single-chip and external extension modes P22 Input Hi-Z Hi-Z During processor mode A25 Output Hi-Z Undefined During single-chip and external extension modes P23 Input Hi-Z Hi-Z During processor mode A26 Output Hi-Z Undefined

20 VCC-BUS - VCC-BUS - - - - VCC-BUS - - -

21 VSS - VSS - - - - VSS - - -

external extension modes P24 Input Hi-Z Hi-Z During processor mode A27 Output Hi-Z Undefined During single-chip and external extension modes P25 Input Hi-Z Hi-Z During processor mode A28 Output Hi-Z Undefined During single-chip and external extension modes P26 Input Hi-Z Hi-Z During processor mode A29 Output Hi-Z Undefined During single-chip and external extension modes P27 Input Hi-Z Hi-Z During processor mode A30 Output Hi-Z Undefined During single-chip and external extension modes P00 Input Hi-Z Hi-Z During processor mode DB0 Input/output Hi-Z Hi-Z VC C -BU S VC C -BU S TO21(Note 1)

7 P224/A11/CS2# P224 A11 CS2#(Note 1)

CS3#(Note 1) TIN4 TIN5 TIN6 Condition Function Pin No. Pin state when reset Symbol Type Power supply - Input/ output DD16 Input/ output - Input/ output

2 P225/A12/CS3#

8 P30/A15/TIN4/DD16 P30 A15

9 P31/A16/TIN5/DD17 P31 A16

10 P32/A17/TIN6/DD18 P32 A17

11 P33/A18/TIN7/DD19

12 P34/A19/TIN30/DD20 P34 A19

13 P35/A20/TIN31/DD21 P35 A20

14 P36/A21/TIN32/DD22 P36 A21

15 P37/A22/TIN33/DD23

16 P20/A23/DD24 P20 A23

17 P21/A24/DD25 P21 A24

18 P22/A25/DD26 P22 A25

19 P23/A26/DD27

22 P24/A27/DD28 P24 A27

23 P25/A28/DD29 P25 A28

24 P26/A29/DD30 P26 A29

25 P27/A30/DD31 DD31

26 P00/DB0/TO21/DD0

DD0(Note 1) Input/ output DD29 Input/ output DD30 Input/ output The pins directed for input go to a high-impedance state (Hi-Z) when reset. The term “when reset” means that input on RESET# pin is held “L” (the device remains reset), and that the RESET# pin is released back “H” (the device comes out of reset). Table 1.4.1 Pin Assignments of the M32192F8xFP, M32195F4xFP, and M32196F8xFP (1/4) Note 1: The pins outputted at two places.

32192/32195/32196 Group Hardware Manual OVERVIEW Rev.1.10 REJ09B0123-0110 Apr.06.07 Port Function 1 Function 2 DRI function NBD function Function Type State during reset State upon exiting reset During single-chip and external extension modes P01 Input Hi-Z Hi-Z During processor mode DB1 Input/output Hi-Z Hi-Z During single-chip and external extension modes P02 Input Hi-Z Hi-Z During processor mode DB2 Input/output Hi-Z Hi-Z During single-chip and external extension modes P03 Input Hi-Z Hi-Z During processor mode DB3 Input/output Hi-Z Hi-Z During single-chip and external extension modes P04 Input Hi-Z Hi-Z During processor mode DB4 Input/output Hi-Z Hi-Z During single-chip and external extension modes P05 Input Hi-Z Hi-Z During processor mode DB5 Input/output Hi-Z Hi-Z During single-chip and external extension modes P06 Input Hi-Z Hi-Z During processor mode DB6 Input/output Hi-Z Hi-Z During single-chip and external extension modes P07 Input Hi-Z Hi-Z During processor mode DB7 Input/output Hi-Z Hi-Z During single-chip and external extension modes P10 Input Hi-Z Hi-Z During processor mode DB8 Input/output Hi-Z Hi-Z During single-chip and external extension modes P11 Input Hi-Z Hi-Z During processor mode DB9 Input/output Hi-Z Hi-Z During single-chip and external extension modes P12 Input Hi-Z Hi-Z During processor mode DB10 Input/output Hi-Z Hi-Z During single-chip and external extension modes P13 Input Hi-Z Hi-Z During processor mode DB11 Input/output Hi-Z Hi-Z During single-chip and external extension modes P14 Input Hi-Z Hi-Z During processor mode DB12 Input/output Hi-Z Hi-Z During single-chip and external extension modes P15 Input Hi-Z Hi-Z During processor mode DB13 Input/output Hi-Z Hi-Z During single-chip and external extension modes P16 Input Hi-Z Hi-Z During processor mode DB14 Input/output Hi-Z Hi-Z During single-chip and external extension modes P17 Input Hi-Z Hi-Z During processor mode DB15 Input/output Hi-Z Hi-Z

42 VREF0 - VREF0 - - - AVCC0 VREF0 - - -

43 AVCC0 - AVCC0 - - - - AVCC0 - - -

44 AD0IN0 - AD0IN0 - - Input AD0IN0 Input Hi-Z Hi-Z

45 AD0IN1 - AD0IN1 - - Input AD0IN1 Input Hi-Z Hi-Z

46 AD0IN2 - AD0IN2 - - Input AD0IN2 Input Hi-Z Hi-Z

47 AD0IN3 - AD0IN3 - - Input AD0IN3 Input Hi-Z Hi-Z

48 AD0IN4 - AD0IN4 - - Input AD0IN4 Input Hi-Z Hi-Z

49 AD0IN5 - AD0IN5 - - Input AD0IN5 Input Hi-Z Hi-Z

50 AD0IN6 - AD0IN6 - - Input AD0IN6 Input Hi-Z Hi-Z

51 AD0IN7 - AD0IN7 - - Input AD0IN7 Input Hi-Z Hi-Z

52 AD0IN8 - AD0IN8 - - Input AD0IN8 Input Hi-Z Hi-Z

53 AD0IN9 - AD0IN9 - - Input AD0IN9 Input Hi-Z Hi-Z

54 AD0IN10 - AD0IN10 - - Input AD0IN10 Input Hi-Z Hi-Z

55 AD0IN11 - AD0IN11 - - Input AD0IN11 Input Hi-Z Hi-Z

56 AD0IN12 - AD0IN12 - - Input AD0IN12 Input Hi-Z Hi-Z

57 AD0IN13 - AD0IN13 - - Input AD0IN13 Input Hi-Z Hi-Z

58 AD0IN14 - AD0IN14 - - Input AD0IN14 Input Hi-Z Hi-Z

59 AD0IN15 - AD0IN15 - - Input AD0IN15 Input Hi-Z Hi-Z

TO35(Note 1) TO36(Note 1) TO31(Note 1) TO32(Note 1) TO33(Note 1) TO34(Note 1) TO24(Note 1) TO25(Note 1) TO26(Note 1) TO27(Note 1) P02 DB2 Symbol Type TO22(Note 1) TO23(Note 1)

31 P05/DB5/

32 P06/DB6/

DD5(Note 1) Input/ output DD6(Note 1) Input/ output DD7(Note 1) Input/ outputTO28(Note 1)33 P07/DB7/ TO28/DD7

34 P10/DB8/

35 P11/DB9/

DD8(Note 1)P10 DB8 TO29(Note 1) TO30(Note 1)

37 P13/DB11/

36 P12/DB10/

TO31/DD10 P12 DB10 DD10(Note 1) Input/ output

39 P15/DB13/

38 P14/DB12/

TO33/DD12 P14 DB12 DD12(Note 1) Input/ output

40 P16/DB14/

41 P17/DB15/

28 P02/DB2/

No. DD15(Note 1) DD13(Note 1)DB13 DD11(Note 1)DB11 DD9(Note 1)DB9

27 P01/DB1/

29 P03/DB3/

30 P04/DB4/

DD2(Note 1) Input/ output DD3(Note 1) Input/ output DD1(Note 1) Input/ output ConditionPower supply VC C -BU S AVCC0 DD4(Note 1) Input/ output Function Input/ output Input/ output DD14(Note 1) Input/ output Input/ output P07 Table 1.4.1 Pin Assignments of the M32192F8xFP, M32195F4xFP, and M32196F8xFP (2/4) Note 1: The pins outputted at two places.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 1.4.1 Pin Assignments of the M32192F8xFP, M32195F4xFP, and M32196F8xFP (3/4) Note 1: The pins outputted at two places. Note 2: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin. Port Function 1 Function 2 DRI function NBD function Function Type State during reset State upon exiting reset

60 AVSS0 - AVSS0 - - - - AVSS0 - - -

61 EX CVCC - EX CVCC - - - - EX CVCC - - -

62 VSS - VSS - - - - VSS - - -

63 P174/TXD2/TO28 P174 TXD2 TO28(Note 1) -

Input/output P174 Input Hi-Z Hi-Z

64 P175/RXD2/TO27 P175 RXD2 TO27(Note 1) - Input/output P175 Input Hi-Z Hi-Z

65 VCCER - VCCER - - Input/output - VCCER - - -

66 P82/TXD0/TO26 P82 TXD0 TO26(Note 1) - Input/output P82 Input Hi-Z Hi-Z

67 P83/RXD0/TO25 P83 RXD0 TO25(Note 1) - Input/output P83 Input Hi-Z Hi-Z

68 P84/SCLKI0/

SCLKO0 TO24(Note 1) - Input/ output P84 Input Hi-Z Hi-Z

69 P85/TXD1/TO23 P85 TXD1 TO23(Note 1) - Input/output P85 Input Hi-Z Hi-Z

70 P86/RXD1/TO22 P86 RXD1 TO22(Note 1) - Input/output P86 Input Hi-Z Hi-Z

71 P87/SCLKI1/

SCLKO1 TO21(Note 1) - Input/ output P87 Input Hi-Z Hi-Z

72 VSS - VSS - - - - VSS - - -

73 EX CVDD - EX CVDD - - - - EX CVDD - - -

74 P61 P61 - - -

Input/output P61 Input Hi-Z Hi-Z

75 P62 P62 - - - Input/output P62 Input Hi-Z Hi-Z

76 P63 P63 - - - Input/output P63 Input Hi-Z Hi-Z

77 SBI# SBI# - - Input SBI# Input Hi-Z Hi-Z

78 P70/CLKOUT/WR#

/BCLK P70 CLKOUT/ WR# BCLK - Input/ output P70 Input Hi-Z Hi-Z

79 P71/WAIT# P71 WAIT# - - Input/output P71 Input Hi-Z Hi-Z

80 P72/HREQ#/TIN27 P72 HREQ# TIN27 - Input/output P72 Input Hi-Z Hi-Z

81 P73/HACK#/TIN26 P73 HACK# TIN26 - Input/output P73 Input Hi-Z Hi-Z

82 P74/RTDTX D/

TXD3/NBDD0 P74 RTDTXD TXD3(Note 1) NBDD0 Input/ output P74 Input Hi-Z Hi-Z

83 P75/RTDRXD/

RXD3/NBDD1 P75 RTDRXD RXD3(Note 1) NBDD1 Input/ output P75 Input Hi-Z Hi-Z

84 P76/RTDACK/

CTX1/NBDD2 P76 RTDACK CTX1(Note 1) NBDD2 Input/ output P76 Input Hi-Z Hi-Z

85 P77/RTDCLK/

CRX1/NBDD3 P77 RTDCLK CRX1(Note 1) NBDD3 Input/ output P77 Input Hi-Z Hi-Z

86 P93/TO16/

SCLKI5/SCLKO5 P93 TO16 SCLKI5/ SCLKO5 - Input/ output P93 Input Hi-Z Hi-Z

87 P94/TO17/

TXD5/DD15 P94 TO17 TX D5 DD15(Note 1) Input/ output P94 Input Hi-Z Hi-Z

88 P95/TO18/

RXD5/DD14 P95 TO18 RX D5 DD14(Note 1) Input/ output P95 Input Hi-Z Hi-Z

89 P96/TO19/DD13 P96 TO19 - DD13(Note 1) Input/output P96 Input Hi-Z Hi-Z

90 P97/TO20/DD12 P97 TO20 - DD12(Note 1) Input/output P97 Input Hi-Z Hi-Z

91 RESET# - RESET# - - Input RESET# Input Hi-Z Hi-Z

92 MOD0 - MOD0 - - Input MOD0 Input Hi-Z Hi-Z

93 MOD1 - MOD1 - - Input MOD1 Input Hi-Z Hi-Z

94 FP - FP - - Input FP Input Hi-Z Hi-Z

95 VCCE - VCCE - - - - VCCE - - -

96 VSS - VSS - - - - VSS - - -

No. Symbol Type Condition Function Power supply VCCE VCCE VCCE

97 P110/TO0/TO29/DD11 P110 TO0 TO29(Note 1) DD11(Note 1) Input/output P110 Input Hi-Z Hi-Z

98 P111/TO1/TO30/DD10 P111 TO1 TO30(Note 1) DD10(Note 1) Input/output P111 Input Hi-Z Hi-Z

99 P112/TO2/TO31/DD9 P112 TO2 TO31(Note 1) DD9(Note 1) Input/output P112 Input Hi-Z Hi-Z

100 P113/TO3/TO32/DD8 P113 TO3 TO32(Note 1) DD8(Note 1) Input/output P113 Input Hi-Z Hi-Z

101 P114/TO4/TO33/DD7 P114 TO4 TO33(Note 1) DD7(Note 1) Input/output P114 Input Hi-Z Hi-Z

102 P115/TO5/TO34/DD6 P115 TO5 TO34(Note 1) DD6(Note 1) Input/output P115 Input Hi-Z Hi-Z

103 P116/TO6/TO35/DD5 P116 TO6 TO35(Note 1) DD5(Note 1) Input/output P116 Input Hi-Z Hi-Z

104 P117/TO7/TO36/DD4 P117 TO7 TO36(Note 1) DD4(Note 1) Input/output P117 Input Hi-Z Hi-Z

105 P100/TO8 P100 TO8 - - Input/output P100 Input Hi-Z Hi-Z

106 P101/TO9/CRX0 P101 TO9 CRX0(Note 1) - Input/output P101 Input Hi-Z Hi-Z

107 P102/TO10/CTX0 P102 TO10 CTX0(Note 1) - Input/output P102 Input Hi-Z Hi-Z

108 VDDE - VDDE - - - - VDDE - - -

109 JTMS (Note 2) - JTMS - - Input JTMS Input Hi-Z Hi-Z

110 JTCK/NBDCLK (Note 2) - JTCK - NBDCLK Input JTCK Input Hi-Z Hi-Z

111 JTRST (Note 2) - JTRST - - Input JTRST Input Hi-Z Hi-Z

112 JTDO/NBDEVNT# (Note 2) - JTDO - NBDEVNT# Output JTDO Output Hi-Z Hi-Z

113 JTDI/NBDSYNC# (Note 2) - JTDI - NBDSYNC# Input JTDI Input Hi-Z Hi-Z

114 P103/TO11/TIN24 P103 TO11 TIN24 - Input/output P103 Input Hi-Z Hi-Z

115 P104/TO12/TIN25/DD3 P104 TO12 TIN25 DD3(Note 1) Input/output P104 Input Hi-Z Hi-Z

116 P105/TO13/

SCLKI4/SCLKO4/DD2 P105 TO13 SCLKI4/ SCLKO4 DD2(Note 1) Input/ output P105 Input Hi-Z Hi-Z

117 P106/TO14/TXD4/DD1 P106 TO14 TXD4 DD1(Note 1) Input/output P106 Input Hi-Z Hi-Z

32192/32195/32196 Group Hardware Manual OVERVIEW Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 1.4.1 Pin Assignments of the M32192F8xFP, M32195F4xFP, and M32196F8xFP (4/4) Note 1: The pins outputted at two places. Port Function 1 Function 2 DRI function NBD function Function Type State during reset State upon exiting reset

118 P107/TO15/RXD4/DD0 P107 TO15 RXD4 DD0(*) Input/output P107 Input Hi-Z Hi-Z

external extension modes P124 Input Hi-Z Hi-Z During processor mode A9 Output Hi-Z Hi-Z During single-chip and external extension modes P125 Input Hi-Z Hi-Z During processor mode A10 Output Hi-Z Hi-Z

121 P126/TCLK2/

CS2#/DD1 P126 TCLK2 CS2#(*) DD1(*) Input/ output P126 Input Hi-Z Hi-Z

122 P127/TCLK3/

CS3#/DD0 P127 TCLK3 CS3#(*) DD0(*) Input/ output P127 Input Hi-Z Hi-Z

123 MOD2 - MOD2 - - - MOD2 - - -

124 P130/TIN16/

output P130 Input Hi-Z Hi-Z

125 P131/TIN17/

output P131 Input Hi-Z Hi-Z

126 P132/TIN18/DIN2 P132 TIN18 - DIN2 Input/output P132 Input Hi-Z Hi-Z

127 P133/TIN19/DIN3 P133 TIN19 - DIN3 Input/output P133 Input Hi-Z Hi-Z

128 P134/TIN20/

TXD3/DIN4 P134 TIN20 TXD3(*) DIN4 Input/ output P134 Input Hi-Z Hi-Z

129 P135/TIN21/RXD3 P135 TIN21 RXD3(*) - Input/output P135 Input Hi-Z Hi-Z

130 P136/TIN22/CRX1 P136 TIN22 CRX1(*) - Input/output P136 Input Hi-Z Hi-Z

131 P137/TIN23/CTX1 P137 TIN23 CTX1(*) - Input/output P137 Input Hi-Z Hi-Z

132 VCCE - VCCE - - - - VCCE - - -

133 P150/TIN0/

CLKOUT/WR# P150 TIN0 CLKOUT(*)/ WR#(*) - Input/ output P150 Input Hi-Z Hi-Z

134 P153/TIN3/WAIT# P153 TIN3 WAIT#(*) - Input/output P153 Input Hi-Z Hi-Z

During single-chip mode P41 Input Hi-Z Hi-Z During external extension and processor modes BLW#/ BLE# Output Hi-Z "H" lev el During single-chip mode P42 Input Hi-Z Hi-Z During external extension and processor modes BHW#/ BHE# Output Hi-Z "H" lev el

137 EX CVCC - EX CVCC - - - - EX CVCC - - -

138 VSS - VSS - - - - VSS - - -

During single-chip mode P43 Input Hi-Z Hi-Z During external extension and processor modes RD# Output Hi-Z "H" level During single-chip and external extension modes P44 Input Hi-Z Hi-Z During processor mode CS0# Output Hi-Z "H" level During single-chip and external extension modes P45 Input Hi-Z Hi-Z During processor mode CS1# Output Hi-Z "H" level During single-chip and external extension modes P46 Input Hi-Z Hi-Z During processor mode A13 Output Hi-Z Undefined During single-chip and external extension modes P47 Input Hi-Z Hi-Z During processor mode A14 Output Hi-Z Undefined

144 P220/CTX 0/HACK# P220 CTX 0(*) HACK#(*) - Input/output P220 Input Hi-Z Hi-Z

A10 DD2(*) Input/ output

119 P124/TCLK0/A9/DD3 P124 TCLK0 A9 DD3(*) Input/

120 P125/TCLK1/A10/DD2 P125 TCLK1

139 P43/RD# P43 RD# - Input/

• Input/ output

140 P44/CS0#/TIN8 P44 CS0#

• Input/ output

142 P46/A13/TIN10 P46 A13

143 P47/A14/TIN11 P47 A14

No. - Input/ output - Input/ output

141 P45/CS1#/TIN9 P45 CS1#

136 P42/BHW#/BHE# P42 BHW#/

BHE# -- Input/ output

135 P41/BLW#/BLE# P41 BLW#/

BLE# -- Input/ output Power supply VCCE VC C -BU S VC C -BU S

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Note 1: The pins outputted at two places. Note 2: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin. Note 3: THERMAL BALL must be connected to the ground (GND). Table 1.4.2 Pin Assignments of the M32192F8xWG (1/4) Port Function 1 Function 2 DRI function NBD function Function Type State during reset State upon exiting reset A2 VSS - VSS - - - - VSS - - - A3 P220/CTX0/HACK# P220 CTX0 (Note 1) HACK# (Note 1) -I n put/Output VCC-BUS P220 In put Hi-Z Hi-Z During single-chip and external extension modes P45 Input Hi-Z Hi-Z During processor mode CS1# Out put Hi-Z "H" level A5 EXCVCC - EXCVCC - - - - EXCVCC - - - A6 P150/TIN0/CLKOUT/WR# P150 TIN0 CLKOUT (Note 1) - Input/Output VCC-BUS P150 Input Hi-Z Hi-Z A7 P135/TIN21/RXD3 P135 TIN21 RXD3 (Note1) -I n put/Output VCCE P135 In put Hi-Z Hi-Z A8 P131/TIN17/ PWMOFF1/DIN1 P131 TIN17/ PWMOFF1 - DIN1 Input/Output VCCE P131 Input Hi-Z Hi-Z A9 MOD2 - MOD2 - - - VCCE MOD2 - - - A10 P126/TCLK2/CS2#/DD1 P126 TCLK2 CS2# (Note 1) DD1 (Note 1) Input/Output VCCE P126 In put Hi-Z Hi-Z A11 P107/TO15/RXD4/DD0 P107 TO15 RXD4 DD0 (Note 1) Input/Output VCCE P107 In put Hi-Z Hi-Z A12 P103/TO11/TIN24 P103 TO11 TIN24 - In put/Output VCCE P103 In put Hi-Z Hi-Z A13 JTDO/NBDEVNT# (Note 2) - JTDO - NBDEVNT# Out put VCCE JTDO Out put Hi-Z Hi-Z A14 JTMS (Note 2) -J T M S - - I n put VCCE JTMS In put Hi-Z Hi-Z A15 VSS - VSS - - - - VSS - - - B1 XIN - XIN - - In put VCC-BUS XIN In put - - B3 P221/CRX0/HREQ# P221 CRX0 (Note 1) HREQ# (Note 1) -I n put VCC-BUS P221 In put Hi-Z Hi-Z During single-chip and external extension modes P46 Input Hi-Z Hi-Z During processor mode A13 Out put Hi-Z Undefined B5 VSS - VSS - - - - VSS - - - B6 P153/TIN3/WAIT# P153 TIN3 WAIT# (Note 1) -I n put/Output VCC-BUS P153 In put Hi-Z Hi-Z B7 P136/TIN22/CRX1 P136 TIN22 CRX1 (Note 1) -I n put/Output VCCE P136 In put Hi-Z Hi-Z B8 P132/TIN18/DIN2 P132 TIN18 - DIN2 In put/Output VCCE P132 In put Hi-Z Hi-Z B11 P106/TO14/TXD4/DD1 P106 TO14 TXD4 DD1 (Note 1) Input/Output VCCE P106 In put Hi-Z Hi-Z B12 JTDI/NBDSYNC# (Note 2) - JTDI - NBDSYNC# In put VCCE JTDI In put Hi-Z Hi-Z B13 JTRST (Note 2) -J T R S T - - I n put VCCE JTRST In put Hi-Z Hi-Z B14 P102/TO10/CTX0 P102 TO10 CTX0 (Note 1) -I n put/Output VCCE P102 In put Hi-Z Hi-Z B15 VDDE - VDDE - - - - VDDE - - - C1 XOUT - XOUT - - In put VCC-BUS XOUT Out put XOUT XOUT Input/Output During single-chip and external extension modes P225 Input Hi-Z Hi-Z Input/Output Durin g processor mode A12 Out put Hi-Z Undefined Input/Output During single-chip and external extension modes P47 Input Hi-Z Hi-Z Input/Output Durin g processor mode A14 Out put Hi-Z Undefined Input/Output Durin g single-chip mode P43 In put Hi-Z Hi-Z Input/Output During single-chip and external extension modes RD# Output Hi-Z "H" level Input/Output Durin g single-chip mode P41 In put Hi-Z Hi-Z Input/Output During single-chip and external extension modes BLW#/ BLE# Output Hi-Z "H" level C7 P137/TIN23/CTX1 P137 TIN23 CTX1 (Note 1) -I n put/Output VCCE P137 In put Hi-Z Hi-Z C8 P133/TIN19/DIN3 P133 TIN19 - DIN3 In put/Output VCCE P133 In put Hi-Z Hi-Z C9 P127/TCLK3/CS3#/DD0 P127 TCLK3 CS3# (Note 1) DD0 (Note 1) Input/Output VCCE P127 In put Hi-Z Hi-Z Input/Output During single-chip and external extension modes P125 Input Hi-Z Hi-Z Input/Output Durin g processor mode A10 Out put Hi-Z Hi-Z C11 P105/TO13/ SCLKI4/SCLKO4/DD2 P105 TO13 SCLKI4/ SCLKO4 DD2 (Note 1) Input/Output VCCE P105 Input Hi-Z Hi-Z C12 VSS - VSS - - - - VSS - - - C13 JTCK/NBDCLK (Note 2) - JTCK - NBDCLK In put VCCE JTCK In put Hi-Z Hi-Z C14 P101/TO9/CRX0 P101 TO9 CRX0 (Note 1) -I n put/Output VCCE P101 In put Hi-Z Hi-Z C15 P100/TO8 P100 TO8 - - In put/Output VCCE P100 In put Hi-Z Hi-Z Input/Output During single-chip and external extension modes P224 Input Hi-Z Hi-Z Input/Output Durin g processor mode A11 Out put Hi-Z Undefined D2 VSS - VSS - - - - VSS - - - D3 VCC-BUS - VCC-BUS - - - - VCC-BUS - - - Input/Output During single-chip and external extension modes P44 Input Hi-Z Hi-Z In put/Output Durin g processor mode CS0# Out put Hi-Z "H" level Input/Output Durin g single-chip mode P42 In put Hi-Z Hi-Z Input/Output During single-chip and external extension modes BHW#/ BHE# Output Hi-Z "H" level D6 VCCE - VCCE - - - - VCCE - - - D7 P134/TIN20/TXD3/DIN4 P134 TIN20 TXD3 (Note 1) DIN4 In put/Output VCCE P134 In put Hi-Z Hi-Z D8 P130/TIN16/ PWMOFF0/DIN0 P130 TIN16/ PWMOFF0 - DIN0 Input/Output VCCE P130 Input Hi-Z Hi-Z Input/Output During single-chip and external extension modes P124 Input Hi-Z Hi-Z Input/Output Durin g processor mode A9 Out put Hi-Z Hi-Z D12 P104/TO12/TIN25/DD3 P104 TO12 TIN25 DD3 (Note 1) Input/Output VCCE P104 In put Hi-Z Hi-Z D13 P117/TO7/TO36/DD4 P117 TO7 TO36 (Note 1) DD4 (Note 1) Input/Output VCCE P117 In put Hi-Z Hi-Z D14 P116/TO6/TO35/DD5 P116 TO6 TO35 (Note 1) DD5 (Note 1) Input/Output VCCE P116 In put Hi-Z Hi-Z D15 P115/TO5/TO34/DD6 P115 TO5 TO34 (Note 1) DD6 (Note 1) Input/Output VCCE P115 In put Hi-Z Hi-Z Input/Output During single-chip and external extension modes P30 Input Hi-Z Hi-Z Input/Output Durin g processor mode A15 Out put Hi-Z Undefined E3 VCCER - VCCER - - In put/Output - VCCER - - - Input/Output During single-chip and external extension modes P31 Input Hi-Z Hi-Z Input/Output Durin g processor mode A16 Out put Hi-Z Undefined E5 THERMAL-BALL (Note 3) -V S S - - - - V S S - - - Pin No. Symbol Function Type Power supply Condition Pin state when reset A4 P45/CS1#/TIN9 P45 CS1# TIN9 - Input/Output VCC-BUS B4 P46/A13/TIN10 P46 A13 TIN10 - Input/Output VCC-BUS CS3# (Note 1) - VCC-BUSC3 P225/A12/CS3# P225 A12 TIN11 - VCC-BUSC4 P47/A14/TIN11 P47 A14 - - VCC-BUSC5 P43/RD# P43 RD# - - VCC-BUSC6 P41/BLW#/BLE# P41 BLW#/ BLE# A10 DD2 (Note 1) VCCEC10 P125/TCLK1/A10/DD2 P125 TCLK1 CS2# (Note 1) - VCC-BUSD1 P224/A11/CS2# P224 A11 TIN8 - VCC-BUSD4 P44/CS0#/TIN8 P44 CS0# - - VCC-BUSD5 P42/BHW#/BHE# P42 BHW#/ BHE# A9 DD3 (Note 1) VCCED11 P124/TCLK0/A9/DD3 P124 TCLK0 TIN4 DD16 VCC-BUSE2 P30/A15/TIN4/DD16 P30 A15 TIN5 DD17 VCC-BUSE4 P31/A16/TIN5/DD17 P31 A16

32192/32195/32196 Group Hardware Manual OVERVIEW Rev.1.10 REJ09B0123-0110 Apr.06.07 Note 1: The pins outputted at two places. Note 2: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin. Note 3: THERMAL BALL must be connected to the ground (GND). Table 1.4.2 Pin Assignments of the M32192F8xWG (2/4) Port Function 1 Function 2 DRI function NBD function Function Type State during reset State upon exiting reset E6 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - E7 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - E8 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - E9 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - E10 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - E11 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - E12 P111/TO1/TO30/DD10 P111 TO1 TO30 (Note 1) DD10 (Note 1) Input/Output VCCE P111 In put Hi-Z Hi-Z E13 P114/TO4/TO33/DD7 P114 TO4 TO33 (Note 1) DD7 (Note 1) Input/Output VCCE P114 In put Hi-Z Hi-Z E14 P113/TO3/TO32/DD8 P113 TO3 TO32 (Note 1) DD8 (Note 1) Input/Output VCCE P113 In put Hi-Z Hi-Z E15 P112/TO2/TO31/DD9 P112 TO2 TO31 (Note 1) DD9 (Note 1) Input/Output VCCE P112 In put Hi-Z Hi-Z During single-chip and external extension modes P34 Input Hi-Z Hi-Z During processor mode A19 Out put Hi-Z Undefined During single-chip and external extension modes P33 Input Hi-Z Hi-Z During processor mode A18 Out put Hi-Z Undefined During single-chip and external extension modes P32 Input Hi-Z Hi-Z During processor mode A17 Out put Hi-Z Undefined During single-chip and external extension modes P35 Input Hi-Z Hi-Z During processor mode A20 Out put Hi-Z Undefined F5 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - F6 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - F7 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - F8 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - F9 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - F10 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - F11 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - F12 VCCE - VCCE - - - - VCCE - - - F13 P110/TO0/TO29/DD11 P110 TO0 TO29 (Note 1) DD11 (Note 1) Input/Output VCCE P110 In put Hi-Z Hi-Z F15 VSS - VSS - - - - VSS - - - During single-chip and external extension modes P37 Input Hi-Z Hi-Z Durin g processor mode A22 Out put Hi-Z Undefined During single-chip and external extension modes P36 Input Hi-Z Hi-Z During processor mode A21 Out put Hi-Z Undefined During single-chip and external extension modes P20 Input Hi-Z Hi-Z During processor mode A23 Out put Hi-Z Undefined G5 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - G6 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - G7 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - G8 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - G9 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - G10 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - G11 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - G12 MOD1 - MOD1 - - In put VCCE MOD1 In put Hi-Z Hi-Z G15 FP - FP - - In put VCCE FP In put Hi-Z Hi-Z During single-chip and external extension modes P23 Input Hi-Z Hi-Z During processor mode A26 Out put Hi-Z Undefined During single-chip and external extension modes P22 Input Hi-Z Hi-Z During processor mode A25 Out put Hi-Z Undefined During single-chip and external extension modes P21 Input Hi-Z Hi-Z During processor mode A24 Out put Hi-Z Undefined H4 VCC-BUS - VCC-BUS - - - - VCC-BUS - - - H5 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - H6 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - H7 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - H8 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - H9 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - H10 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - H11 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - H12 P97/TO20/DD12 P97 TO20 - DD12 (Note 1) Input/Output VCCE P97 In put Hi-Z Hi-Z H13 MOD0 - MOD0 - - In put VCCE MOD0 In put Hi-Z Hi-Z H14 RESET# - RESET# - - In put VCCE RESET# In put Hi-Z Hi-Z J1 VSS - VSS - - - - VSS - - - During single-chip and external extension modes P24 Input Hi-Z Hi-Z Durin g processor mode A27 Out put Hi-Z Undefined During single-chip and external extension modes P25 Input Hi-Z Hi-Z During processor mode A28 Out put Hi-Z Undefined J4 VSS - VSS - - - - VSS - - - J5 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - J6 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - J7 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - J8 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - J9 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - J10 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - J11 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - J12 P96/TO19/DD13 P96 TO19 - DD13 (Note 1) Input/Output VCCE P96 In put Hi-Z Hi-Z J13 P94/TO17/TXD5/DD15 P94 TO17 TXD5 DD15 (Note 1) Input/Output VCCE P94 In put Hi-Z Hi-Z J14 P95/TO18/RXD5/DD14 P95 TO18 RXD5 DD14 (Note 1) Input/Output VCCE P95 In put Hi-Z Hi-Z During single-chip and external extension modes P27 Input Hi-Z Hi-Z During processor mode A30 Out put Hi-Z Undefined During single-chip and external extension modes P00 Input Hi-Z Hi-Z During processor mode DB0 In put/Output Hi-Z Hi-Z Pin No. Symbol Function Type Power supply Condition Pin state when reset F1 P34/A19/TIN30/DD20 P34 A19 TIN30 DD20 Input/Output VCC-BUS F2 P33/A18/TIN7/DD19 P33 A18 TIN7 DD19 Input/Output VCC-BUS F3 P32/A17/TIN6/DD18 P32 A17 TIN6 DD18 Input/Output VCC-BUS F4 P35/A20/TIN31/DD21 P35 A20 TIN31 DD21 Input/Output VCC-BUS G1 P37/A22/TIN33/DD23 P37 A22 TIN33 DD23 Input/Output VCC-BUS G2 P36/A21/TIN32/DD22 P36 A21 TIN32 DD22 Input/Output VCC-BUS G4 P20/A23/DD24 P20 A23 - DD24 Input/Output VCC-BUS H1 P23/A26/DD27 P23 A26 - DD27 Input/Output VCC-BUS H2 P22/A25/DD26 P22 A25 - DD26 Input/Output VCC-BUS H3 P21/A24/DD25 P21 A24 - DD25 Input/Output VCC-BUS J2 P24/A27/DD28 P24 A27 - DD28 Input/Output VCC-BUS J3 P25/A28/DD29 P25 A28 - DD29 Input/Output VCC-BUS K1 P27/A30/DD31 P27 A30 - DD31 Input/Output VCC-BUS K2 P00/DB0/TO21/DD0 P00 DB0 TO21 (Note 1) DD0 (Note 1) Input/Output VCC-BUS

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Note 1: The pins outputted at two places. Note 2: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin. Note 3: THERMAL BALL must be connected to the ground (GND). Table 1.4.2 Pin Assignments of the M32192F8xWG (3/4) Port Function 1 Function 2 DRI function NBD function Function Type State during reset State upon exiting reset During single-chip and external extension modes P01 Input Hi-Z Hi-Z During processor mode DB1 In put/Output Hi-Z Hi-Z During single-chip and external extension modes P26 Input Hi-Z Hi-Z During processor mode A29 Out put Hi-Z Undefined K5 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - K6 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - K7 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - K8 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - K9 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - K10 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - K11 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - K12 VSS - VSS - - - - VSS - - - K13 P76/RTDACK/CTX1/NBDD2 P76 RTDACK CTX1 (Note 1) NBDD2 In put/Output VCCE P76 In put Hi-Z Hi-Z K14 P77/RTDCLK/CRX1/NBDD3 P77 RTDCLK CRX1 (Note 1) NBDD3 In put/Output VCCE P77 In put Hi-Z Hi-Z K15 P93/TO16/SCLKI5/SCLKO5 P93 TO16 SCLKI5/ SCLKO5 - Input/Output VCCE P93 Input Hi-Z Hi-Z During single-chip and external extension modes P03 Input Hi-Z Hi-Z During processor mode DB3 In put/Output Hi-Z Hi-Z During single-chip and external extension modes P04 Input Hi-Z Hi-Z During processor mode DB4 In put/Output Hi-Z Hi-Z During single-chip and external extension modes P05 Input Hi-Z Hi-Z During processor mode DB5 In put/Output Hi-Z Hi-Z During single-chip and external extension modes P02 Input Hi-Z Hi-Z During processor mode DB2 In put/Output Hi-Z Hi-Z L5 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - L6 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - L7 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - L8 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - L9 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - L10 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - L11 THERMAL-BALL (Note 3) - VSS - - - - VSS - - - L13 P73/HACK#/TIN26 P73 HACK# TIN26 - In put/Output VCCE P73 In put Hi-Z Hi-Z L14 P74/RTDTXD/TXD3/NBDD0 P74 RTDTXD TXD3 (Note 1) NBDD0 In put/Output VCCE P74 In put Hi-Z Hi-Z L15 P75/RTDRXD/RXD3/NBDD P75 RTDRXD RXD3 (Note 1) NBDD1 In put/Output VCCE P75 In put Hi-Z Hi-Z During single-chip and external extension modes P06 Input Hi-Z Hi-Z During processor mode DB6 In put/Output Hi-Z Hi-Z During single-chip and external extension modes P07 Input Hi-Z Hi-Z During processor mode DB7 In put/Output Hi-Z Hi-Z During single-chip and external extension modes P10 Input Hi-Z Hi-Z During processor mode DB8 In put/Output Hi-Z Hi-Z M4 VREF0 - VREF0 - - - AVCC0 VREF0 - - - M5 AD0IN2 - AD0IN2 - - In put AVCC0 AD0IN2 In put Hi-Z Hi-Z M6 AD0IN6 - AD0IN6 - - In put AVCC0 AD0IN6 In put Hi-Z Hi-Z M7 AD0IN10 - AD0IN10 - - In put AVCC0 AD0IN10 In put Hi-Z Hi-Z M8 AD0IN14 - AD0IN14 - - In put AVCC0 AD0IN14 In put Hi-Z Hi-Z M9 AD0IN15 - AD0IN15 - - In put AVCC0 AD0IN15 In put Hi-Z Hi-Z M11 P174/TXD2/TO28 P174 TXD2 TO28 (Note 1) -I n put/Output VCCE P174 In put Hi-Z Hi-Z M12 VCCE - VCCE - - - - VCCE - - - M13 P70/CLKOUT/WR#/BCLK P70 CLKOUT/ WR# BCLK - Input/Output VCCE P70 Input Hi-Z Hi-Z M14 P71/WAIT# P71 WAIT# - - In put/Output VCCE P71 In put Hi-Z Hi-Z M15 P72/HREQ#/TIN27 P72 HREQ# TIN27 - In put/Output VCCE P72 In put Hi-Z Hi-Z During single-chip and external extension modes P11 Input Hi-Z Hi-Z During processor mode DB9 In put/Output Hi-Z Hi-Z During single-chip and external extension modes P12 Input Hi-Z Hi-Z During processor mode DB10 In put/Output Hi-Z Hi-Z During single-chip and external extension modes P15 Input Hi-Z Hi-Z During processor mode DB13 In put/Output Hi-Z Hi-Z N5 AVCC0 - AVCC0 - - - - AVCC0 - - - N6 AD0IN3 - AD0IN3 - - In put AVCC0 AD0IN3 In put Hi-Z Hi-Z N7 AD0IN7 - AD0IN7 - - In put AVCC0 AD0IN7 In put Hi-Z Hi-Z N8 AD0IN11 - AD0IN11 - - In put AVCC0 AD0IN11 In put Hi-Z Hi-Z N9 VSS - VSS - - - - VSS - - - N11 P82/TXD0/TO26 P82 TXD0 TO26 (Note 1) -I n put/Output VCCE P82 In put Hi-Z Hi-Z N12 P85/TXD1/TO23 P85 TXD1 TO23 (Note 1) -I n put/Output VCCE P85 In put Hi-Z Hi-Z N13 P87/SCLKI1/ SCLKO1/TO21 P87 SCLKI1/ SCLKO1 TO21 (Note 1) - Input/Output VCCE P87 Input Hi-Z Hi-Z N14 P63 P63 - - - In put/Output VCCE P63 In put Hi-Z Hi-Z N15 SBI# SBI# - - In put VCCE SBI# In put Hi-Z Hi-Z During single-chip and external extension modes P13 Input Hi-Z Hi-Z During processor mode DB11 In put/Output Hi-Z Hi-Z During single-chip and external extension modes P16 Input Hi-Z Hi-Z During processor mode DB14 In put/Output Hi-Z Hi-Z During single-chip and external extension modes P17 Input Hi-Z Hi-Z During processor mode DB15 In put/Output Hi-Z Hi-Z P5 AD0IN0 - AD0IN0 - - In put AVCC0 AD0IN0 In put Hi-Z Hi-Z P6 AD0IN4 - AD0IN4 - - In put AVCC0 AD0IN4 In put Hi-Z Hi-Z P7 AD0IN8 - AD0IN8 - - In put AVCC0 AD0IN8 In put Hi-Z Hi-Z P8 AD0IN12 - AD0IN12 - - In put AVCC0 AD0IN12 In put Hi-Z Hi-Z Pin No. Symbol Function Type Power supply Condition Pin state when reset K3 P01/DB1/TO22/DD1 P01 DB1 TO22 (Note 1) DD1 (Note 1) Input/Output VCC-BUS K4 P26/A29/DD30 P26 A29 - DD30 Input/Output VCC-BUS L1 P03/DB3/TO24/DD3 P03 DB3 TO24 (Note 1) DD3 (Note 1) Input/Output VCC-BUS L2 P04/DB4/TO25/DD4 P04 DB4 TO25 (Note 1) DD4 (Note 1) Input/Output VCC-BUS L3 P05/DB5/TO26/DD5 P05 DB5 TO26 (Note 1) DD5 (Note 1) Input/Output VCC-BUS L4 P02/DB2/TO23/DD2 P02 DB2 TO23 (Note 1) DD2 (Note 1) Input/Output VCC-BUS M1 P06/DB6/TO27/DD6 P06 DB6 TO27 (Note 1) DD6 (Note 1) Input/Output VCC-BUS M2 P07/DB7/TO28/DD7 P07 DB7 TO28 (Note 1) DD7 (Note 1) Input/Output VCC-BUS M3 P10/DB8/TO29/DD8 P10 DB8 TO29 (Note 1) DD8 (Note 1) Input/Output VCC-BUS N1 P11/DB9/TO30/DD9 P11 DB9 TO30 (Note 1) DD9 (Note 1) Input/Output VCC-BUS N2 P12/DB10/TO31/DD10 P12 DB10 TO31 (Note 1) DD10 (Note 1) Input/Output VCC-BUS N3 P15/DB13/TO34/DD13 P15 DB13 TO34 (Note 1) DD13 (Note 1) Input/Output VCC-BUS P2 P13/DB11/TO32/DD11 P13 DB11 TO32 (Note 1) DD11 (Note 1) Input/Output VCC-BUS P3 P16/DB14/TO35/DD14 P16 DB14 TO35 (Note 1) DD14 (Note 1) Input/Output VCC-BUS P4 P17/DB15/TO36/DD15 P17 DB15 TO36 (Note 1) DD15 (Note 1) Input/Output VCC-BUS

32192/32195/32196 Group Hardware Manual OVERVIEW Rev.1.10 REJ09B0123-0110 Apr.06.07 Note 1: The pins outputted at two places. Note 2: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin. Note 3: THERMAL BALL must be connected to the ground (GND). Table 1.4.2 Pin Assignments of the M32192F8xWG (4/4) Port Function 1 Function 2 DRI function NBD function Function Type State during reset State upon exiting reset P9 EXCVCC - EXCVCC -- - - EXCVCC --- P11 VCCER - VCCER -- Input/Output - VCCER --- P12 P84/SCLKI0/ SCLKO0/TO24 - SCLKI0/ SCLKO0 -- Input/Output VCCE P84 Input Hi-Z Hi-Z P14 P62 P62 -- - Input/Output VCCE P62 Input Hi-Z Hi-Z P15 P61 P61 -- - Input/Output VCCE P61 Input Hi-Z Hi-Z During single-chip and external extension modes P14 Input Hi-Z Hi-Z During processor mode DB12 Input/Output Hi-Z Hi-Z R4 VSS - VSS -- - - VSS --- R5 AD0IN1 - AD0IN1 -- Input AVCC0 AD0IN1 Input Hi-Z Hi-Z R6 AD0IN5 - AD0IN5 -- Input AVCC0 AD0IN5 Input Hi-Z Hi-Z R7 AD0IN9 - AD0IN9 -- Input AVCC0 AD0IN9 Input Hi-Z Hi-Z R8 AD0IN13 - AD0IN13 -- Input AVCC0 AD0IN13 Input Hi-Z Hi-Z R9 AVSS0 - AVSS0 -- - - AVSS0 --- R11 P175/RXD2/TO27 P175 RXD2 TO27 (Note 1) - Input/Output VCCE P175 Input Hi-Z Hi-Z R12 P83/RXD0/TO25 P83 RXD0 TO25 (Note 1) - Input/Output VCCE P83 Input Hi-Z Hi-Z R13 P86/RXD1/TO22 P86 RXD1 TO22 (Note 1) - Input/Output VCCE P86 Input Hi-Z Hi-Z R14 VSS - VSS -- - - VSS --- R15 EXCVDD - EXCVDD -- - - EXCVDD --- Pin No. Symbol Function Type Power supply Condition Pin state when reset R2 P14/DB12/ TO33/DD12 P14 DB12 TO33 (Note 1) DD12 (Note 1) Input/Output VCC-BUS

2.1 CPU Registers

2.2 General-purpose Registers

2.3 Control Registers

2.4 Accumulator

2.5 Program Counter

2.6 Data Formats

2.7 Supplementary Explanation for BSET, BCLR,

LOCK and UNLOCK Instruction Execution

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CPU There are 6 control registers which are the Processor Status Word Register (PSW), the Condition Bit Register (CBR), the Interrupt Stack Pointer (SPI), the User Stack Pointer (SPU), the Backup PC (BPC) and the Floating- point Status Register (FPSR). The dedicated MVTC and MVFC instructions are used for writing and reading these control registers. In addition, the SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instruction. Figure 2.3.1 Control Registers The M32R-FPU has 16 general-purpose registers, 6 control registers, an accumulator and a program counter. The accumulator is of 56-bit configuration, and all other registers are of 32-bit configuration. The 16 general-purpose registers (R0–R15) are of 32-bit width and are used to retain data and base address, as well as for integer calculations, floating-point operations, etc. R14 is used as the link register and R15 as the stack pointer. The link register is used to store the return address when executing a subroutine call instruction. The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) are alternately represented by R15 depend- ing on the value of the Stack Mode (SM) bit in the Processor Status Word Register (PSW). Upon exiting the reset state, the value of the general-purpose registers is undefined. Figure 2.2.1 General-purpose Registers b0b0 b31 R10 R11 R12 R13 R14 (Link register) R15 (Stack pointer) (Note 1) Note 1: The stack pointer functions as either the SPI or the SPU depending on the value of the SM bit in the PSW. b31 Backup PC BPCCR6 b31 PSW CBR SPI SPU CR0 CR1 CR2 CR3 Processor Status Word Register Condition Bit Register Interrupt Stack Pointer User Stack Pointer CRn Notes: • CRn (n = 0-3, 6 and 7) denotes the control register number.  The dedicated MVTC and MVFC instructions are used for writing and reading these control registers.  The SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instruction. Floating-point Status RegisterFPSRCR7

2-332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CPU

2.3.1 Processor Status Word Register: PSW (CR0)

7654321 8 9 1 01 11 2 1 31 4 b 1 5b0 ?? 00000?00000000 BC SM IE C 23 24 25 26 27 28 29 30 b3117 18 19 20 21 22b16 BIEBSM BPSW field PSW field <Upon exiting reset: B’0000 0000 0000 0000 ??00 000? 0000 0000> b Bit Name Function R W 0–15 No function assigned. Fix to "0." 00

16 BSM Saves value of SM bit when EIT occurs R W

17 BIE Saves value of IE bit when EIT occurs R W

18–22 No function assigned. Fix to "0." 00

23 BC Saves value of C bit when EIT occurs R W

24 SM 0: Uses R15 as the interrupt stack pointer R W

Stack Mode Bit 1: Uses R15 as the user stack pointer

25 IE 0: Does not accept interrupt R W

Interrupt Enable Bit (Note 1) 1: Accepts interrupt 26–30 No function assigned. Fix to "0." 00

31 C Indicates carry, borrow or overflow resulting R W

Condition Bit from operations (instruction dependent) Note 1: Interrupt which is controlable is External Interrupt (EI). Reserved Instruction Exception (RIE), Address Exept (AE), R eset Interrupt (RI), System Break Interrupt (SBI) and Trap are not controlled. The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs. The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and the Condition (C) bit. The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt Enable (BIE) bit and the Backup Condition (BC) bit. Upon exiting the reset state, BSM, BIE and BC are undefined. All other bits are "0."

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CPU

2.3.2 Condition Bit Register: CBR (CR1)

The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value written to the PSW register’s C bit is reflected in this register. The register can only be read. (Writing to the register with the MVTC instruction is ignored.) Upon exiting the reset state, the value of CBR is H’0000 0000. b0 b31

0000000000000000000000000000000 CCBR

2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3)

The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) retain the address of the current stack pointer. These registers can be accessed as the general-purpose register R15. R15 switches between repre- senting the SPI and SPU depending on the value of the Stack Mode (SM) bit in the PSW. Upon exiting the reset state, the values of the SPI and SPU are undefined. b0 b31 SPI SPI b0 b31 SPU SPU

2.3.4 Backup PC: BPC (CR6)

The Backup PC (BPC) is used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31 is fixed to "0." When an EIT occurs, the register sets either the PC value when the EIT occurred or the PC value for the next instruction depending on the type of EIT. The BPC value is loaded to the PC when the RTE instruction is executed. However, the values of the lower 2 bits of the PC are always "00" when returned. (PC always returns to the word-aligned address.) Upon exiting the reset state, the value of the BPC is undefined. b0 b31 0BPCBPC

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2.3.5 Floating-point Status Register: FPSR (CR7)

23456789 1 0 1 1 1 2 1 3 1 4 b 1 51b0 00 00000100000000 EV DN CE CX CU CZ CO CV RM 18 19 20 21 22 23 24 25 26 27 28 29 30 b3117b16 EUEX FS FX FU FZ FO FV EZ EO <Upon exiting reset: H’0000 0100> b Bit Name Function R W 0 FS Reflects the logical sum of FU, FZ, FO and FV. R – Floating-point Exception Summary Bit

1 FX Set to "1" when an inexact exception occurs (if EIT processing is R W

Inexact Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software.

2 FU Set to "1" when an underflow exception occurs (if EIT processing is R W

Underflow Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software.

3 FZ Set to "1" when a zero divide exception occurs (if EIT processing is R W

Zero Divide Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software.

4 FO Set to "1" when an overflow exception occurs (if EIT processing is R W

Overflow Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software.

5 FV Set to "1" when an invalid operation exception occurs (if EIT processing R W

Invalid Operation Exception Flag is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. 6–16 No function assigned. Fix to "0." 00 17 EX 0: Mask EIT processing to be executed when an inexact exception occurs. R W Inexact Exception Enable Bit 1: Execute EIT processing when an inexact exception occurs.

18 EU 0: Mask EIT processing to be executed when an underflow exception R W

Underflow Exception Enable Bit occurs. 1: Execute EIT processing when an underflow exception occurs.

19 EZ 0: Mask EIT processing to be executed when a zero divide exception R W

Zero Divide Exception Enable Bit occurs. 1: Execute EIT processing when a zero divide exception occurs.

20 EO 0: Mask EIT processing to be executed when an overflow exception R W

Overflow Exception Enable Bit occurs. 1: Execute EIT processing when an overflow exception occurs.

21 EV 0: Mask EIT processing to be executed when an invalid operation R W

Invalid Operation Exception Enable Bit exception occurs. 1: Execute EIT processing when an invalid operation exception occurs. 22 No function assigned. Fix to "0." 00 23 DN 0: Handle the denormalized number as a denormalized number. R W Denormalized Number Zero Flush Bit 1: Handle the denormalized number as zero. (Note 2) 24 CE 0: No unimplemented operation exception occurred. R (Note 3) Unimplemented Operation 1: An unimplemented operation exception occurred. When the bit is Exception Cause Bit set to "1", the execution of an FPU operation instruction will clear it to "0." 25 CX 0: No inexact exception occurred. R (Note 3) Inexact Exception Cause Bit 1: An inexact exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0."

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CPU

26 CU 0: No underflow exception occurred R (Note 3)

Underflow Exception Cause Bit 1: An underflow exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0." 27 CZ 0: No zero divide exception occurred. R (Note 3) Zero Divide Exception Cause Bit 1: A zero divide exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0." 28 CO 0: No overflow exception occurred. R (Note 3) Overflow Exception Cause Bit 1: An overflow exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0." 29 CV 0: No invalid operation exception occurred. R (Note 3) Invalid Operation Exception Cause Bit 1: An invalid operation exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0." 30, 31 RM 00: Round to nearest R W Rounding Mode Selection Bit 01: Round toward Zero 10: Round toward + Infinity 11: Round toward – Infinity Note 1: The phrase “If EIT processing unexecuted” means whenever one of the exceptions occurs, enable bits 17 to 21 are set to "0" which masks the EIT processing so that it cannot be executed. If two exceptions occur at the same time and their corresponding exception enable bits are set differently (one enabled, and the other masked), EIT processing is executed. In this case, these two flags do not change state regardless of the enable bits settings. Note 2: If a denormalized number is given to the operand when DN = "0", an unimplemented exception occurs. Note 3: This bit is cleared by writing "0." Writing "1" has no effect (the bit retains the value it had before the write).

2-732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CPU The Accumulator (ACC) is a 56-bit register used for DSP function instructions. The accumulator is handled as a 64-bit register when accessed for read or write. When reading data from the accumulator, the value of bit 8 is sign-extended. When writing data to the accumulator, bits 0 to 7 are ignored. The accumulator is also used for the multiply instruction “MUL,” in which case the accumulator value is destroyed by instruction execution. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the high-order 32 bits (bits 0–31) and the low-order 32 bits (bits 32–63), respectively. Use the MVFACHI, MVFACLO and MVFACMI instructions for reading data from the accumulator. The MVFACHI, MVFACLO and MVFACMI instructions read data from the high-order 32 bits (bits 0–31), the low-order 32 bits (bits 32–63) and the middle 32 bits (bits 16–47), respectively. Upon exiting the reset state, the value of accumulator is undefined. 15b0 16 7 8 31 32 47 48 b6 3 ACC (Note 1) Read range of MVFACMI instruction Write and read ranges of MVTACLO and MVFACLO instructions Write and read ranges of MVTACHI and MVFACHI instructions Note 1: When read, bits 0 to 7 always show the sign-extended value of the value of bit 8. Writing to this bit field is ignored. The Program Counter (PC) is a 32-bit counter that retains the address of the instruction being executed. Since the M32R FPU instruction starts with even-numbered addresses, the LSB (bit 31) is always "0." Upon exiting the reset state, the value of PC is H’0000 0000. b0 b31 0PCPC

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CPU

2.6.1 Data Types

The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16 and 32-bit integers and single-precision floating-point numbers. The signed integers are represented by 2’s complements. Figure 2.6.1 Data Types Signed byte (8-bit) integer Unsigned byte (8-bit) integer Signed halfword (16-bit) integer Unsigned halfword (16-bit) integer Signed word (32-bit) integer Unsigned word (32-bit) integer Single-precision floating-point number b15 b15 b31 b31 S S S b0 b1 b8 b9 b31 SE F S: Sign bit; E: Exponent field; F: Fraction field

2-932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CPU

2.6.2 Data Formats

(1) Data formats in registers The data sizes in the M32R-FPU registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) to a word (32-bit) quantity before being loaded in the register. When storing data from a register into a memory, the 32-bit data, the 16-bit data on the LSB side and the 8-bit data on the LSB side of the register are stored into memory by the ST, STH and STB instructions, respectively. Figure 2.6.2 Data Formats in Registers Rn b0 b31 <Load> Byte Rn b0 b31 Halfword Rn b0 b31 Word Sign-extended (LDB instruction) or zero-extended (LDUB instruction) From memory (LDB, LDUB instructions) <Store> Rn b0 b31 Byte Rn b0 b31 Halfword Rn b0 b31 Word To memory (STB instruction) To memory (STH instruction) To memory (ST instruction) From memory (LDH, LDUH instructions) From memory (LD instruction) Sign-extended (LDH instruction) or zero-extended (LDUH instruction)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CPU Bit endian (H'01) Byte endian (H'01234567) Big endian Little endian Note:  Even when bits are arranged in big endian, H'01 is not B'10000000. HH HL LH LL H'01 H'23 H'45 H'67 LL LH HL HH H'67 H'45 H'23 H'01 B'0000001 b0 b7 B'0000001 b7 b0 Figure 2.6.4 General Endian System (2) Data formats in memory The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). Although byte data can be located at any address, halfword and word data must be located at the addresses aligned with a halfword boundary (least significant address bit = "0") or a word boundary (two low-order address bits = "00"), respectively. If an attempt is made to access memory data that overlaps the halfword or word boundary, an address exception occurs. Figure 2.6.3 Data Formats in Memory (3) Endian The diagrams below show a general endian system and the endian adopted for the M32R Family micro- computers. Address Byte Halfword Word +0 address +1 address +2 address +3 address b0 b31 Byte Byte Byte Byte Halfword Halfword Word 7 8 15 16 23 24 b0 15 b0 b31 b31

2-1132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CPU  Constant transfer LD24 Rdest, #imm24 LDI Rdest, #imm16 LDI Rdest, #imm8 SETH Rdest, #imm16 b23b0 Rdest imm24 b31b0 LD24 Rdest, #imm24 b15b0 Rdest imm16 b31b0 SETH Rdest, #imm16 00 00  Register to register transfer MV Rdest, Rsrc  Control register transfer MVFC Rdest, CRsrc MVTC Rsrc, CRdest Rsrc b31b0 Rdest b31b0 Rsrc b31b0 CRdest b31b0 MVTC Rsrc, CRdest MV Rdest, Rsrc Note:  The condition bit C changes state when data is written to CR0 (PSW) using the MVTC instruction. Figure 2.6.6 Transfer Instructions Little/little LL LH HL HH Big/big HH HL LH LL Little/big HH HL LH LL Endian (bit/byte) Data arrangement Microcomputer family name 7700 and M16C Families M32R Family 31–247–0 23–1615–8 0–7 24–31 8–15 16–23Bit number Example: 0x01234567 .byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67 Note:  The M32R Family uses the big endian for both bits and bytes. 7–031–24 15–823–16 Figure 2.6.5 Endian Adopted for the M32R Family (4) Transfer instructions

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CPU (5) Transfer from memory (signed) to registers  Signed 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc  Signed 16 bits LD24 Rsrc, #label LDH Rdest, @Rsrc  Signed 8 bits LD24 Rsrc, #label LDB Rdest, @Rsrc label Rdest b31b0+0 +1 +2 +3 Rdestlabel 00 00 FF FF Determined by MSB b31b0 +0 +1 +2 +3 Rdestlabel 00 00 00 FF FF FF b31b0 +0 +1 +2 +3 Determined by MSB Memory Register 0: Positive number 1: Negative number 0: Positive number 1: Negative number  Unsigned 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc  Unsigned 16 bits LD24 Rsrc, #label LDUB Rdest, @Rsrc  Unsigned 8 bits LD24 Rsrc, #label LDUH Rdest, @Rsrc Rdest 00 00 b31b0 label +0 +1 +2 +3 label +0 +1 +2 +3 Rdest b31b0 label +0 +1 +2 +3 Rdest 00 00 00 b31b0 Memory Register Figure 2.6.7 Transfer from Memory (Signed) to Registers (6) Transfer from memory (unsigned) to registers Figure 2.6.8 Transfer from Memory (Unsigned) to Registers

2-1332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CPU (7) Notes on data transfer When transferring data, be aware that data arrangements in registers and memory are different. Figure 2.6.9 Differences in Data Arrangements  Word data (32 bits) +0 +1 +2 +3 b0 b31 HH HL LH LL b0 b31 HH HL LH LL  Halfword data (16 bits) +0 +1 +2 +3 b0 b31 H L b0 b15 H L  Byte data (8 bits) +0 +1 +2 +3 b0 b31 b0 b7 (R0–R15) (R0–R15) (R0–R15) +0 +1 +2 +3 b0 b31 b8 b15 (R0–R15) +0 +1 +2 +3 b0 b31 b16 b23 (R0–R15) +0 +1 +2 +3 b0 b31 b24 b31 (R0–R15) +0 +1 +2 +3 b0 b31 H L b16 b31 H L (R0–R15) Data in registers Data in memory

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 CPU

2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK

The LOCK bit is set when executing the BSET or BCLR instruction, and is cleared when the BSET or BCLR instruction finishes. The LOCK instruction sets the LOCK bit, as well as performs an ordinary load operation. The UNLOCK instruc- tion is used to clear the LOCK bit. The LOCK bit is located inside the CPU, and cannot directly be accessed for read or write by users. This bit controls granting of bus control requested by devices other than the CPU.

• When LOCK bit = "0" Control of the bus requested by devices other than the CPU is granted
• When LOCK bit = "1" Control of the bus requested by devices other than the CPU is denied In the 32192/32195/32196 Group, control of the bus may be requested by devices other than the CPU in the following two cases:
• When DMA transfer is requested by the internal DMAC
• When HREQ# input is pulled low to request that the CPU be placed in a hold state

2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution

3.1 Outline of the Address Space

3.2 Operation Modes

3.3 Internal ROM and External Extension Areas

3.4 Internal RAM and SFR Areas

3.5 EIT Vector Entry

3.6 ICU Vector Table

3.7 Notes on Address Space

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The logical addresses of the M32R are always handled in 32 bits, providing a linear address space of up to 4 Gbytes. The address space of the M32R/ECU consists of the following: (1) User space

• Internal ROM area
• External extension area
• Internal RAM area
• SFR (Special Function Register) area The 2 Gbytes from the address H’0000 0000 to the address H’7FFF FFFF comprise the user space. Located in this space are the internal ROM area, an external extension area, the internal RAM area and the SFR (Special Function Register) area (in which a set of internal peripheral I/O registers exist). Of these, the internal ROM and external extension areas are located differently depending on mode set- tings as will be described later. (2) System space (This area is closed to the user) The 2 Gbytes from the address H’8000 0000 to the address H’FFFF FFFF comprise the system space. This space (except for SFR area for NBD control) is reserved for use by development tools such as an in- circuit emulator and debug monitor.

3-332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The microcomputer is placed in one of the following modes depending on how CPU operation mode is set by MOD0 and MOD1 pins. The operation mode used for rewriting the internal flash memory is described separately in Section 6.6, "Programming the Internal Flash Memory." Table 3.2.1 Operation Mode Settings MOD0 MOD1 MOD2 (Note 1) Operation mode (Note 2) VSS VSS VSS Single-chip mode VSS VCCE VSS External extension mode VCCE VSS VSS Processor mode (FP = VSS) VCCE VCCE VSS (Settings inhibited) – – VCCE (Settings inhibited) Note 1: Connect VCCE and VSS to the VCCE input power supply and ground, respectively. Note 2: For the operation mode used to rewrite the internal flash memory (FP = VCCE) which is not shown in the above table, see Section 6.6, "Programming the Internal Flash Memory." The internal ROM and external extension areas are located differently depending on how operation mode is set. (All other areas in the address space are located the same way.) The following diagram shows how the internal ROM and external extension areas are mapped into the address space in each operation mode. (For flash rewrite mode, see Section 6.6, "Programming the Internal Flash Memory.")

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Logical address Single chip mode External extension mode Processor mode Logical address (64 Mbytes) CS3 area (8 Mbytes) SFR area (16 Kbytes) Internal RAM area (176 Kbytes) H'0000 0000 H'7FFF FFFF H'0000 0000 H'FFFF FFFF H'8000 0000 H'007F FFFF H'0080 0000 H'0010 0000 H'0080 4000 H'0082 FFFF H'0083 0000 H'00FF FFFF H'03FF FFFF H'0380 0000 H'037F FFFF H'0300 0000 H'02FF FFFF H'0280 0000 H'027F FFFF H'0200 0000 H'01FF FFFF H'0180 0000 H'017F FFFF H'0100 0000 H'000F FFFF H'0080 3FFF Internal ROM area (1 Mbyte) User space System space

2 Gbytes

(8 Mbytes) CS2 area (8 Mbytes) CS2 area (8 Mbytes) CS1 area (8 Mbytes) CS1 area (8 Mbytes) CS0 area (8 Mbytes) CS0 area (7 Mbytes) Internal ROM area (1 Mbyte) SFR area (16 Kbytes) Internal RAM area (176 Kbytes) (64 Mbytes) (64 Mbytes) Ghost area in 64-Mbyte units SFR area (16 Kbytes) Internal RAM area (176 Kbytes) Notes: • CS0–CS3 areas: External extension areas of up to 32 Mbytes  : Indicates Ghost area. This area must not be used during programming intentionally. H'E000 0000 NBD control ... ... Figure 3.2.1 Address Space of the M32192F8

3-532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 3.2.2 Address Space of the M32195F4 Logical address Single chip mode External extension mode Processor mode Logical address (64 Mbytes) CS3 area (8 Mbytes) SFR area (16 Kbytes) Internal RAM area (32 Kbytes) H'0000 0000 H'7FFF FFFF H'0000 0000 H'FFFF FFFF H'8000 0000 H'007F FFFF H'0080 0000 H'0008 0000 H'000F FFFF H'0010 0000 H'0080 4000 H'0080 BFFF H'0080 C000 H'00FF FFFF H'03FF FFFF H'0380 0000 H'037F FFFF H'0300 0000 H'02FF FFFF H'0280 0000 H'027F FFFF H'0200 0000 H'01FF FFFF H'0180 0000 H'017F FFFF H'0100 0000 H'0007 FFFF H'0080 3FFF User space System space (8 Mbytes) CS2 area (8 Mbytes) CS2 area (8 Mbytes) CS1 area (8 Mbytes) CS1 area (8 Mbytes) CS0 area (8 Mbytes) CS0 area (7 Mbytes) Internal ROM area (512 Kbytes) Internal ROM area (512 Kbytes) Reserved area (512 Kbytes) SFR area (16 Kbytes) Internal RAM area (32 Kbytes) (64 Mbytes) (64 Mbytes) Ghost area in 64-Mbyte units SFR area (16 Kbytes) Internal RAM area (32 Kbytes) H'E000 0000 NBD control ... ... Notes:  CS0–CS3 areas: External extension areas of up to 32 Mbytes  : Indicates Ghost area. This area must not be used during programming intentionally.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 3.2.3 Address Space of the M32196F8 Logical address Single chip mode External extension mode Processor mode Logical address (64 Mbytes) CS3 area (8 Mbytes) SFR area (16 Kbytes) Internal RAM area (64 Kbytes) H'0000 0000 H'7FFF FFFF H'0000 0000 H'FFFF FFFF H'8000 0000 H'007F FFFF H'0080 0000 H'0010 0000 H'0080 4000 H'0081 3FFF H'0081 4000 H'00FF FFFF H'03FF FFFF H'0380 0000 H'037F FFFF H'0300 0000 H'02FF FFFF H'0280 0000 H'027F FFFF H'0200 0000 H'01FF FFFF H'0180 0000 H'017F FFFF H'0100 0000 H'000F FFFF H'0080 3FFF Internal ROM area (1 Mbyte) User space System space (8 Mbytes) CS2 area (8 Mbytes) CS2 area (8 Mbytes) CS1 area (8 Mbytes) CS1 area (8 Mbytes) CS0 area (8 Mbytes) CS0 area (7 Mbytes) Internal ROM area (1 Mbyte) SFR area (16 Kbytes) Internal RAM area (64 Kbytes) (64 Mbytes) (64 Mbytes) Ghost area in 64-Mbyte units SFR area (16 Kbytes) Internal RAM area (64 Kbytes) H'E000 0000 NBD control ... ... Notes:  CS0–CS3 areas: External extension areas of up to 32 Mbytes  : Indicates Ghost area. This area must not be used during programming intentionally.

3-732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The 64-Mbyte area in the user space from the address H’0000 0000 to the address H’03FF FFFF comprise the internal ROM and external extension areas. For the address mapping of these areas that differs with each operation mode, see Section 3.2, "Operation Modes."

3.3.1 Internal ROM Area

The internal ROM is allocated to the addresses shown below. Located at the beginning of this area is the EIT vector entry (and the ICU vector table). Table 3.3.1 Internal ROM Allocation Address Type Name Size Allocation Address M32192F8, M32196F8 1 Mbytes H’0000 0000 to H’000F FFFF M32195F4 512 Kbytes H'0000 0000 to H'0007 FFFF

3.3.2 External Extension Area

The external extension area is only available when external extension or processor mode is selected by opera- tion mode settings. When accessing the external extension area, the control signals necessary to access external devices are output. The CS0# through CS3# signals are output corresponding to the address mapping of the external extension area. The CS0#, CS1#, CS2# and CS3# signals are output for the CS0, CS1, CS2 and CS3 areas, respec- tively. Table 3.3.2 Address Mapping of the External Extension Area in Each Operation Mode Operation Mode Address Mapping of External Extension Area Single-chip mode None External extension mode Addresses H’0010 0000 to H’007F FFFF (CS0 area: 7 Mbytes) Addresses H’0100 0000 to H’017F FFFF (CS1 area: 8 Mbytes) Addresses H’0200 0000 to H’027F FFFF (CS2 area: 8 Mbytes) Addresses H’0300 0000 to H’037F FFFF (CS3 area: 8 Mbytes) Processor mode Addresses H’0000 0000 to H’007F FFFF (CS0 area: 8 Mbytes) Addresses H’0100 0000 to H’017F FFFF (CS1 area: 8 Mbytes) Addresses H’0200 0000 to H’027F FFFF (CS2 area: 8 Mbytes) Addresses H’0300 0000 to H’037F FFFF (CS3 area: 8 Mbytes)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The 8-Mbyte area from the address H’0080 0000 to the address H’00FF FFFF comprise the internal RAM and SFR (Special Function Register) areas. Of these, the space that the user can actually use is a 256-Kbyte area from the address H’0080 0000 to the address H’0083 FFFF. The other areas here are ghosts in 256-Kbyte units. (Do not use the ghost area intentionally during programming.)

3.4.1 Internal RAM Area

The internal RAM area is allocated to the addresses shown below. Table 3.4.1 Internal RAM Allocation Address Type Name Size Allocation Address M32192F8 176 Kbytes H’0080 4000 to H’0082 FFFF M32195F4 32 Kbytes H'0080 4000 to H'0080 BFFF M32196F8 64 Kbytes H’0080 4000 to H’0081 3FFF

3.4.2 SFR (Special Function Register) Area

The addresses H’0080 0000 to H’0080 3FFFF comprise the SFR (Special Function Register) area. Located in this area are the internal peripheral I/O registers. Figure 3.4.1 Internal RAM and SFR (Special Function Register) Areas of the M32192F8 H'0080 0000 H'0080 3FFF H'0080 4000 H'0082 FFFF H'0080 FFFF H'0081 0000 SFR area (16 Kbytes) Internal RAM (176 Kbytes) Virtual flash emulation areas separated in 8-Kbyte units can be allocated here. For details, see Section 6.7.

3-932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 H'0080 0000 H'0080 3FFF H'0080 4000 H'0080 BFFF SFR area (16 Kbytes) Internal RAM (32 Kbytes) Virtual flash emulation areas separated in 8-Kbyte units can be allocated here. For details, see Section 6.7. Figure 3.4.2 Internal RAM and SFR (Special Function Register) Areas of the M32195F4 H'0080 0000 H'0080 3FFF H'0080 4000 H'0081 3FFF SFR area (16 Kbytes) Internal RAM (64 Kbytes) Virtual flash emulation areas separated in 8-Kbyte units can be allocated here. For details, see Section 6.7. Figure 3.4.3 Internal RAM and SFR (Special Function Register) Areas of the M32196F8

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (1/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0000 Interrupt Vector Register 5-5 (IVECT) H'0080 0002 (Use inhibited area) H'0080 0004 Interrupt Request Mask Register (Use inhibited area) 5-6 (IMASK) H'0080 0006 SBI Control Register (Use inhibited area) 5-7 (SBICR) (Use inhibited area) H'0080 0056 RAM Write Monitor Interrupt Control Register CAN1 Error Interrupt Control Register 5-8 (IRAMWRCR) (ICAN1ERCR) H'0080 0058 CAN1 Single-Shot Interrupt Control Register CAN1 Transmit/Receive Interrupt Control Register 5-8 (ICAN1SSCR) (ICAN1TRCR) H'0080 005A CAN0 Error Interrupt Control Register CAN0 Single-Shot Interrupt Control Register 5-8 (ICAN0ERCR) (ICAN0SSCR) H'0080 005C CAN0 Transmit/Receive Interrupt Control Register DRI Event Detection Interrupt Control Register 5-8 (ICAN0TRCR) (IDRIEVCR) H'0080 005E DRI Counter Interrupt Control Register DRI Transfer Interrupt Control Register 5-8 (IDRICNTCR) (IDRITRCR) H'0080 0060 CAN0 Transmit /Receive & Error Interrupt Control Register TML1 Input Interrupt Control Register 5-8 (ICAN0CR) (ITML1CR) H'0080 0062 (Use inhibited area) H'0080 0064 SIO4,5 Transmit/Receive Interrupt Control Register TOU1 Output Interrupt Control Register 5-8 (ISIO45CR) (ITOU1CR) H'0080 0066 TID1 Output Interrupt Control Register RTD Interrupt Control Register 5-8 (ITID1CR) (IRTDCR) H'0080 0068 SIO2,3 Transmit/Receive Interrupt Control Register DMA5–9 Interrupt Control Register 5-8 (ISIO23CR) (IDMA59CR) H'0080 006A TOU0 Output Interrupt Control Register TID0 Output Interrupt Control Register 5-8 (ITOU0CR) (ITID0CR) H'0080 006C A/D0 Conversion Interrupt Control Register SIO0 Transmit Interrupt Control Register 5-8 (IAD0CCR) (ISIO0TXCR) H'0080 006E SIO0 Receive Interrupt Control Register SIO1 Transmit Interrupt Control Register 5-8 (ISIO0RXCR) (ISIO1TXCR) H'0080 0070 SIO1 Receive Interrupt Control Register DMA0–4 Interrupt Control Register 5-8 (ISIO1RXCR) (IDMA04CR) H'0080 0072 MJT Output Interrupt Control Register 0 MJT Output Interrupt Control Register 1 5-8 (IMJTOCR0) (IMJTOCR1) H'0080 0074 MJT Output Interrupt Control Register 2 MJT Output Interrupt Control Register 3 5-8 (IMJTOCR2) (IMJTOCR3) H'0080 0076 MJT Output Interrupt Control Register 4 MJT Output Interrupt Control Register 5 5-8 (IMJTOCR4) (IMJTOCR5) H'0080 0078 MJT Output Interrupt Control Register 6 MJT Output Interrupt Control Register 7 5-8 (IMJTOCR6) (IMJTOCR7) H'0080 007A MJT Input Interrupt Control Register 0 MJT Input Interrupt Control Register 1 5-8 (IMJTICR0) (IMJTICR1) H'0080 007C MJT Input Interrupt Control Register 2 MJT Input Interrupt Control Register 3 5-8 (IMJTICR2) (IMJTICR3) H'0080 007E MJT Input Interrupt Control Register 4 CAN1 Transmit/Receive & Error Interrupt Control Register 5-8 (IMJTICR4) (ICAN1CR) H'0080 0080 A/D0 Single Mode Register 0 A/D0 Single Mode Register 1 11-17 (AD0SIM0) (AD0SIM1) 11-19 H'0080 0082 (Use inhibited area) A/D0 Single Mode Register 2 11-21 (AD0SIM2) H'0080 0084 A/D0 Scan Mode Register 0 A/D0 Scan Mode Register 1 11-22 (AD0SCM0) (AD0SCM1) 11-24 H'0080 0086 A/D0 Disconnection Detection Assist Function Control Register A/D0 Conversion Speed Control Register 11-27 (AD0DDACR) (AD0CVSCR) 11-26 H'0080 0088 A/D0 Successive Approximation Register 11-31 (AD0SAR) H'0080 008A A/D0 Disconnection Detection Assist Method Select Register 11-28 (AD0DDASEL) H'0080 008C A/D0 Comparate Data Register 11-32 (AD0CMP) H'0080 008E (Use inhibited area)

3-1132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (2/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0090 10-bit A/D0 Data Register 0 11-33 (AD0DT0) H'0080 0092 10-bit A/D0 Data Register 1 11-33 (AD0DT1) H'0080 0094 10-bit A/D0 Data Register 2 11-33 (AD0DT2) H'0080 0096 10-bit A/D0 Data Register 3 11-33 (AD0DT3) H'0080 0098 10-bit A/D0 Data Register 4 11-33 (AD0DT4) H'0080 009A 10-bit A/D0 Data Register 5 11-33 (AD0DT5) H'0080 009C 10-bit A/D0 Data Register 6 11-33 (AD0DT6) H'0080 009E 10-bit A/D0 Data Register 7 11-33 (AD0DT7) H'0080 00A0 10-bit A/D0 Data Register 8 11-33 (AD0DT8) H'0080 00A2 10-bit A/D0 Data Register 9 11-33 (AD0DT9) H'0080 00A4 10-bit A/D0 Data Register 10 11-33 (AD0DT10) H'0080 00A6 10-bit A/D0 Data Register 11 11-33 (AD0DT11) H'0080 00A8 10-bit A/D0 Data Register 12 11-33 (AD0DT12) H'0080 00AA 10-bit A/D0 Data Register 13 11-33 (AD0DT13) H'0080 00AC 10-bit A/D0 Data Register 14 11-33 (AD0DT14) H'0080 00AE 10-bit A/D0 Data Register 15 11-33 (AD0DT15) (Use inhibited area) H'0080 00D0 (Use inhibited area) 8-bit A/D0 Data Register 0 11-34 (AD08DT0) H'0080 00D2 (Use inhibited area) 8-bit A/D0 Data Register 1 11-34 (AD08DT1) H'0080 00D4 (Use inhibited area) 8-bit A/D0 Data Register 2 11-34 (AD08DT2) H'0080 00D6 (Use inhibited area) 8-bit A/D0 Data Register 3 11-34 (AD08DT3) H'0080 00D8 (Use inhibited area) 8-bit A/D0 Data Register 4 11-34 (AD08DT4) H'0080 00DA (Use inhibited area) 8-bit A/D0 Data Register 5 11-34 (AD08DT5) H'0080 00DC (Use inhibited area) 8-bit A/D0 Data Register 6 11-34 (AD08DT6) H'0080 00DE (Use inhibited area) 8-bit A/D0 Data Register 7 11-34 (AD08DT7) H'0080 00E0 (Use inhibited area) 8-bit A/D0 Data Register 8 11-34 (AD08DT8) H'0080 00E2 (Use inhibited area) 8-bit A/D0 Data Register 9 11-34 (AD08DT9) H'0080 00E4 (Use inhibited area) 8-bit A/D0 Data Register 10 11-34 (AD08DT10) H'0080 00E6 (Use inhibited area) 8-bit A/D0 Data Register 11 11-34 (AD08DT11) H'0080 00E8 (Use inhibited area) 8-bit A/D0 Data Register 12 11-34 (AD08DT12) H'0080 00EA (Use inhibited area) 8-bit A/D0 Data Register 13 11-34 (AD08DT13) H'0080 00EC (Use inhibited area) 8-bit A/D0 Data Register 14 11-34 (AD08DT14) H'0080 00EE (Use inhibited area) 8-bit A/D0 Data Register 15 11-34 (AD08DT15) (Use inhibited area)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (3/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0100 SIO23 Interrupt Request Status Register SIO03 Interrupt Request Mask Register 12-9 (SI23STAT) (SI03MASK) 12-10 H'0080 0102 SIO03 Interrupt Request Source Select Register (Use inhibited area) 12-11 (SI03SEL) (Use inhibited area) H'0080 0110 SIO0 Transmit Control Register SIO0 Transmit/Receive Mode Register 12-14 (S0TCNT) (S0MOD) 12-15 H'0080 0112 SIO0 Transmit Buffer Register 12-19 (S0TXB) H'0080 0114 SIO0 Receive Buffer Register 12-20 (S0RXB) H'0080 0116 SIO0 Receive Control Register SIO0 Baud Rate Register 12-21 (S0RCNT) (S0BAUR) 12-24 H'0080 0118 SIO0 Special Mode Register (Use inhibited area) 12-27 (S0SMOD) (Use inhibited area) H'0080 0120 SIO1 Transmit Control Register SIO1 Transmit/Receive Mode Register 12-14 (S1TCNT) (S1MOD) 12-15 H'0080 0122 SIO1 Transmit Buffer Register 12-19 (S1TXB) H'0080 0124 SIO1 Receive Buffer Register 12-20 (S1RXB) H'0080 0126 SIO1 Receive Control Register SIO1 Baud Rate Register 12-21 (S1RCNT) (S1BAUR) 12-24 H'0080 0128 SIO1 Special Mode Register (Use inhibited area) 12-27 (S1SMOD) (Use inhibited area) H'0080 0130 SIO2 Transmit Control Register SIO2 Transmit/Receive Mode Register 12-14 (S2TCNT) (S2MOD) 12-15 H'0080 0132 SIO2 Transmit Buffer Register 12-19 (S2TXB) H'0080 0134 SIO2 Receive Buffer Register 12-20 (S2RXB) H'0080 0136 SIO2 Receive Control Register SIO2 Baud Rate Register 12-21 (S2RCNT) (S2BAUR) 12-24 H'0080 0138 SIO2 Special Mode Register (Use inhibited area) 12-27 (S2SMOD) (Use inhibited area) H'0080 0140 SIO3 Transmit Control Register SIO3 Transmit/Receive Mode Register 12-14 (S3TCNT) (S3MOD) 12-15 H'0080 0142 SIO3 Transmit Buffer Register 12-19 (S3TXB) H'0080 0144 SIO3 Receive Buffer Register 12-20 (S3RXB) H'0080 0146 SIO3 Receive Control Register SIO3 Baud Rate Register 12-21 (S3RCNT) (S3BAUR) 12-24 H'0080 0148 SIO3 Special Mode Register (Use inhibited area) 12-27 (S3SMOD) (Use inhibited area) H'0080 0180 CS0 Area Wait Control Register CS1 Area Wait Control Register 18-4 (CS0WTCR) (CS1WTCR) H'0080 0182 CS2 Area Wait Control Register CS3 Area Wait Control Register 18-4 (CS2WTCR) (CS3WTCR) (Use inhibited area) H'0080 01A0 CLKOUT Select Register (Use inhibited area) 17-16 (CLKOUTSEL) 20-8 H'0080 01A2 Flash E/W Wait Select Register (Use inhibited area) 18-6 (FWAIT) (Use inhibited area) H'0080 01E0 Flash Mode Register Flash Status Register 6-15 (FMOD) (FSTAT) 6-16

3-1332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (4/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 01E2 Flash Control Register 1 Flash Control Register 2 6-17 (FCNT1) (FCNT2) 6-18 H'0080 01E4 Flash Control Register 3 Flash Control Register 4 6-19 (FCNT3) (FCNT4) 6-22 (Use inhibited area) H'0080 0200 Common Count Clock Select Register Clock Bus & Input Event Bus Control Register 10-12 (CNTCKSEL) (CKIEBCR) 10-17 H'0080 0202 Prescaler Register 0 Prescaler Register 1 10-13 (PRS0) (PRS1) H'0080 0204 Prescaler Register 2 Output Event Bus Control Register 10-13 (PRS2) (OEBCR) 10-18 (Use inhibited area) H'0080 0210 TCLK Input Processing Control Register 10-21 (TCLKCR) H'0080 0212 TIN Input Processing Control Register 0 10-22 (TINCR0) H'0080 0214 TIN Input Processing Control Register 1 10-23 (TINCR1) H'0080 0216 TIN Input Processing Control Register 2 10-24 (TINCR2) H'0080 0218 TIN Input Processing Control Register 3 10-25 (TINCR3) H'0080 021A TIN Input Processing Control Register 4 10-25 (TINCR4) (Use inhibited area) H'0080 0220 F/F Source Select Register 0 10-28 (FFS0) H'0080 0222 (Use inhibited area) F/F Source Select Register 1 10-29 (FFS1) H'0080 0224 F/F Protect Register 0 10-30 (FFP0) H'0080 0226 F/F Data Register 0 10-32 (FFD0) H'0080 0228 (Use inhibited area) F/F Protect Register 1 10-30 (FFP1) H'0080 022A (Use inhibited area) F/F Data Register 1 10-32 (FFD1) (Use inhibited area) H'0080 0230 TOP Interrupt Control Register 0 TOP Interrupt Control Register 1 10-38 (TOPIR0) (TOPIR1) H'0080 0232 TOP Interrupt Control Register 2 TOP Interrupt Control Register 3 10-40 (TOPIR2) (TOPIR3) 10-41 H'0080 0234 TIO Interrupt Control Register 0 TIO Interrupt Control Register 1 10-42 (TIOIR0) (TIOIR1) 10-43 H'0080 0236 TIO Interrupt Control Register 2 TMS Interrupt Control Register 10-44 (TIOIR2) (TMSIR) 10-45 H'0080 0238 TIN Interrupt Control Register 0 TIN Interrupt Control Register 1 10-46 (TINIR0) (TINIR1) 10-47 H'0080 023A TIN Interrupt Control Register 2 TIN Interrupt Control Register 3 10-48 (TINIR2) (TINIR3) H'0080 023C TIN Interrupt Control Register 4 TIN Interrupt Control Register 5 10-50 (TINIR4) (TINIR5) H'0080 023E TIN Interrupt Control Register 6 TIN Interrupt Control Register 7 10-52 (TINIR6) (TINIR7) 10-55 H'0080 0240 TOP0 Counter 10-71 (TOP0CT) H'0080 0242 TOP0 Reload Register 10-72 (TOP0RL) H'0080 0244 (Use inhibited area) H'0080 0246 TOP0 Correction Register 10-73 (TOP0CC) (Use inhibited area)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (5/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0250 TOP1 Counter 10-71 (TOP1CT) H'0080 0252 TOP1 Reload Register 10-72 (TOP1RL) H'0080 0254 (Use inhibited area) H'0080 0256 TOP1 Correction Register 10-73 (TOP1CC) (Use inhibited area) H'0080 0260 TOP2 Counter 10-71 (TOP2CT) H'0080 0262 TOP2 Reload Register 10-72 (TOP2RL) H'0080 0264 (Use inhibited area) H'0080 0266 TOP2 Correction Register 10-73 (TOP2CC) (Use inhibited area) H'0080 0270 TOP3 Counter 10-71 (TOP3CT) H'0080 0272 TOP3 Reload Register 10-72 (TOP3RL) H'0080 0274 (Use inhibited area) H'0080 0276 TOP3 Correction Register 10-73 (TOP3CC) (Use inhibited area) H'0080 0280 TOP4 Counter 10-71 (TOP4CT) H'0080 0282 TOP4 Reload Register 10-72 (TOP4RL) H'0080 0284 (Use inhibited area) H'0080 0286 TOP4 Correction Register 10-73 (TOP4CC) (Use inhibited area) H'0080 0290 TOP5 Counter 10-71 (TOP5CT) H'0080 0292 TOP5 Reload Register 10-72 (TOP5RL) H'0080 0294 (Use inhibited area) H'0080 0296 TOP5 Correction Register 10-73 (TOP5CC) H'0080 0298 (Use inhibited area) H'0080 029A TOP0–5 Control Register 0 10-67 (TOP05CR0) H'0080 029C (Use inhibited area) TOP0–5 Control Register 1 10-67 (TOP05CR1) (Use inhibited area) H'0080 02A0 TOP6 Counter 10-71 (TOP6CT) H'0080 02A2 TOP6 Reload Register 10-72 (TOP6RL) H'0080 02A4 (Use inhibited area) H'0080 02A6 TOP6 Correction Register 10-73 (TOP6CC) H'0080 02A8 (Use inhibited area) H'0080 02AA TOP6,7 Control Register 10-69 (TOP67CR)

3-1532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (6/37) Address +0 address +1 address See pages b0 b7 b8 b15 (Use inhibited area) H'0080 02B0 TOP7 Counter 10-71 (TOP7CT) H'0080 02B2 TOP7 Reload Register 10-72 (TOP7RL) H'0080 02B4 (Use inhibited area) H'0080 02B6 TOP7 Correction Register 10-73 (TOP7CC) (Use inhibited area) H'0080 02C0 TOP8 Counter 10-71 (TOP8CT) H'0080 02C2 TOP8 Reload Register 10-72 (TOP8RL) H'0080 02C4 (Use inhibited area) H'0080 02C6 TOP8 Correction Register 10-73 (TOP8CC) (Use inhibited area) H'0080 02D0 TOP9 Counter 10-71 (TOP9CT) H'0080 02D2 TOP9 Reload Register 10-72 (TOP9RL) H'0080 02D4 (Use inhibited area) H'0080 02D6 TOP9 Correction Register 10-73 (TOP9CC) (Use inhibited area) H'0080 02E0 TOP10 Counter 10-71 (TOP10CT) H'0080 02E2 TOP10 Reload Register 10-72 (TOP10RL) H'0080 02E4 (Use inhibited area) H'0080 02E6 TOP10 Correction Register 10-73 (TOP10CC) H'0080 02E8 (Use inhibited area) H'0080 02EA TOP8–10 Control Register 10-70 (TOP810CR) (Use inhibited area) H'0080 02FA TOP0-10 External Enable Permit Register 10-74 (TOPEEN) H'0080 02FC TOP0-10 Enable Protect Register 10-74 (TOPPRO) H'0080 02FE TOP0-10 Count Enable Register 10-75 (TOPCEN) H'0080 0300 TIO0 Counter 10-105 (TIO0CT) H'0080 0302 (Use inhibited area) H'0080 0304 TIO0 Reload 1 Register 10-107 (TIO0RL1) H'0080 0306 TIO0 Reload 0/ Measure Register 10-106 (TIO0RL0) (Use inhibited area) H'0080 0310 TIO1 Counter 10-105 (TIO1CT) H'0080 0312 (Use inhibited area) H'0080 0314 TIO1 Reload 1 Register 10-107 (TIO1RL1)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (7/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0316 TIO1 Reload 0/ Measure Register 10-106 (TIO1RL0) H'0080 0318 (Use inhibited area) H'0080 031A TIO0–3 Control Register 0 10-98 (TIO03CR0) H'0080 031C (Use inhibited area) TIO0–3 Control Register 1 10-99 (TIO03CR1) (Use inhibited area) H'0080 0320 TIO2 Counter 10-105 (TIO2CT) H'0080 0322 (Use inhibited area) H'0080 0324 TIO2 Reload 1 Register 10-107 (TIO2RL1) H'0080 0326 TIO2 Reload 0/ Measure Register 10-106 (TIO2RL0) (Use inhibited area) H'0080 0330 TIO3 Counter 10-105 (TIO3CT) H'0080 0332 (Use inhibited area) H'0080 0334 TIO3 Reload 1 Register 10-107 (TIO3RL1) H'0080 0336 TIO3 Reload 0/ Measure Register 10-106 (TIO3RL0) (Use inhibited area) H'0080 0340 TIO4 Counter 10-105 (TIO4CT) H'0080 0342 (Use inhibited area) H'0080 0344 TIO4 Reload 1 Register 10-107 (TIO4RL1) H'0080 0346 TIO4 Reload 0/ Measure Register 10-106 (TIO4RL0) H'0080 0348 (Use inhibited area) H'0080 034A TIO4 Control Register TIO5 Control Register 10-100 (TIO4CR) (TIO5CR) 10-102 (Use inhibited area) H'0080 0350 TIO5 Counter 10-105 (TIO5CT) H'0080 0352 (Use inhibited area) H'0080 0354 TIO5 Reload 1 Register 10-107 (TIO5RL1) H'0080 0356 TIO5 Reload 0/ Measure Register 10-106 (TIO5RL0) (Use inhibited area) H'0080 0360 TIO6 Counter 10-105 (TIO6CT) H'0080 0362 (Use inhibited area) H'0080 0364 TIO6 Reload 1 Register 10-107 (TIO6RL1) H'0080 0366 TIO6 Reload 0/ Measure Register 10-106 (TIO6RL0) H'0080 0368 (Use inhibited area) H'0080 036A TIO6 Control Register TIO7 Control Register 10-103 (TIO6CR) (TIO7CR) 10-104 (Use inhibited area)

3-1732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (8/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0370 TIO7 Counter 10-105 (TIO7CT) H'0080 0372 (Use inhibited area) H'0080 0374 TIO7 Reload 1 Register 10-107 (TIO7RL1) H'0080 0376 TIO7 Reload 0/ Measure Register 10-106 (TIO7RL0) (Use inhibited area) H'0080 0380 TIO8 Counter 10-105 (TIO8CT) H'0080 0382 (Use inhibited area) H'0080 0384 TIO8 Reload 1 Register 10-107 (TIO8RL1) H'0080 0386 TIO8 Reload 0/ Measure Register 10-106 (TIO8RL0) H'0080 0388 (Use inhibited area) H'0080 038A TIO8 Control Register TIO9 Control Register 10-104 (TIO8CR) (TIO9CR) 10-105 (Use inhibited area) H'0080 0390 TIO9 Counter 10-105 (TIO9CT) H'0080 0392 (Use inhibited area) H'0080 0394 TIO9 Reload 1 Register 10-107 (TIO9RL1) H'0080 0396 TIO9 Reload 0/ Measure Register 10-106 (TIO9RL0) (Use inhibited area) H'0080 03BC TIO0-9 Enable Protect Register 10-108 (TIOPRO) H'0080 03BE TIO0-9 Count Enable Register 10-109 (TIOCEN) H'0080 03C0 TMS0 Counter 10-127 (TMS0CT) H'0080 03C2 TMS0 Measure 3 Register 10-127 (TMS0MR3) H'0080 03C4 TMS0 Measure 2 Register 10-127 (TMS0MR2) H'0080 03C6 TMS0 Measure 1 Register 10-127 (TMS0MR1) H'0080 03C8 TMS0 Measure 0 Register 10-127 (TMS0MR0) H'0080 03CA TMS0 Control Register TMS1 Control Register 10-126 (TMS0CR) (TMS1CR) (Use inhibited area) H'0080 03D0 TMS1 Counter 10-127 (TMS1CT) H'0080 03D2 TMS1 Measure 3 Register 10-127 (TMS1MR3) H'0080 03D4 TMS1 Measure 2 Register 10-127 (TMS1MR2) H'0080 03D6 TMS1 Measure 1 Register 10-127 (TMS1MR1) H'0080 03D8 TMS1 Measure 0 Register 10-127 (TMS1MR0) (Use inhibited area) H'0080 03E0 TML0 Counter (Upper) 10-132 (TML0CT) (TML0CTH) H'0080 03E2 (Lower) (TML0CTL)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (9/37) Address +0 address +1 address See pages b0 b7 b8 b15 (Use inhibited area) H'0080 03EA (Use inhibited area) TML0 Control Register 10-131 (TML0CR) (Use inhibited area) H'0080 03F0 TML0 Measure 3 Register (Upper) 10-132 (TML0MR3) (TML0MR3H) H'0080 03F2 (Lower) (TML0MR3L) H'0080 03F4 TML0 Measure 2 Register (Upper) 10-132 (TML0MR2) (TML0MR2H) H'0080 03F6 (Lower) (TML0MR2L) H'0080 03F8 TML0 Measure 1 Register (Upper) 10-132 (TML0MR1) (TML0MR1H) H'0080 03FA (Lower) (TML0MR1L) H'0080 03FC TML0 Measure 0 Register (Upper) 10-132 (TML0MR0) (TML0MR0H) H'0080 03FE (Lower) (TML0MR0L) H'0080 0400 DMA0–4 Interrupt Request Status Register DMA0–4 Interrupt Request Mask Register 9-35 (DM04ITST) (DM04ITMK) 9-36 (Use inhibited area) H'0080 0408 DMA5–9 Interrupt Request Status Register DMA5–9 Interrupt Request Mask Register 9-35 (DM59ITST) (DM59ITMK) 9-36 (Use inhibited area) H'0080 0410 DMA0 Channel Control Register 0 DMA0 Channel Control Register 1 9-6 (DM0CNT0) (DM0CNT1) 9-7 H'0080 0412 DMA0 Source Address Register 9-30 (DM0SA) H'0080 0414 DMA0 Destination Address Register 9-31 (DM0DA) H'0080 0416 DMA0 Transfer Count Register 9-32 (DM0TCT) H'0080 0418 DMA5 Channel Control Register 0 DMA5 Channel Control Register 1 9-16 (DM5CNT0) (DM5CNT1) 9-17 H'0080 041A DMA5 Source Address Register 9-30 (DM5SA) H'0080 041C DMA5 Destination Address Register 9-31 (DM5DA) H'0080 041E DMA5 Transfer Count Register 9-32 (DM5TCT) H'0080 0420 DMA1 Channel Control Register 0 DMA1 Channel Control Register 1 9-8 (DM1CNT0) (DM1CNT1) 9-9 H'0080 0422 DMA1 Source Address Register 9-30 (DM1SA) H'0080 0424 DMA1 Destination Address Register 9-31 (DM1DA) H'0080 0426 DMA1 Transfer Count Register 9-32 (DM1TCT) H'0080 0428 DMA6 Channel Control Register 0 DMA6 Channel Control Register 1 9-18 (DM6CNT0) (DM6CNT1) 9-19 H'0080 042A DMA6 Source Address Register 9-30 (DM6SA) H'0080 042C DMA6 Destination Address Register 9-31 (DM6DA) H'0080 042E DMA6 Transfer Count Register 9-32 (DM6TCT) H'0080 0430 DMA2 Channel Control Register 0 DMA2 Channel Control Register 1 9-10 (DM2CNT0) (DM2CNT1) 9-11 H'0080 0432 DMA2 Source Address Register 9-30 (DM2SA) H'0080 0434 DMA2 Destination Address Register 9-31 (DM2DA)

3-1932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (10/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0436 DMA2 Transfer Count Register 9-32 (DM2TCT) H'0080 0438 DMA7 Channel Control Register 0 DMA7 Channel Control Register 1 9-20 (DM7CNT0) (DM7CNT1) 9-21 H'0080 043A DMA7 Source Address Register 9-30 (DM7SA) H'0080 043C DMA7 Destination Address Register 9-31 (DM7DA) H'0080 043E DMA7 Transfer Count Register 9-32 (DM7TCT) H'0080 0440 DMA3 Channel Control Register 0 DMA3 Channel Control Register 1 9-12 (DM3CNT0) (DM3CNT1) 9-13 H'0080 0442 DMA3 Source Address Register 9-30 (DM3SA) H'0080 0444 DMA3 Destination Address Register 9-31 (DM3DA) H'0080 0446 DMA3 Transfer Count Register 9-32 (DM3TCT) H'0080 0448 DMA8 Channel Control Register 0 DMA8 Channel Control Register 1 9-22 (DM8CNT0) (DM8CNT1) 9-23 H'0080 044A DMA8 Source Address Register 9-30 (DM8SA) H'0080 044C DMA8 Destination Address Register 9-31 (DM8DA) H'0080 044E DMA8 Transfer Count Register 9-32 (DM8TCT) H'0080 0450 DMA4 Channel Control Register 0 DMA4 Channel Control Register 1 9-14 (DM4CNT0) (DM4CNT1) 9-15 H'0080 0452 DMA4 Source Address Register 9-30 (DM4SA) H'0080 0454 DMA4 Destination Address Register 9-31 (DM4DA) H'0080 0456 DMA4 Transfer Count Register 9-32 (DM4TCT) H'0080 0458 DMA9 Channel Control Register 0 DMA9 Channel Control Register 1 9-24 (DM9CNT0) (DM9CNT1) 9-25 H'0080 045A DMA9 Source Address Register 9-30 (DM9SA) H'0080 045C DMA9 Destination Address Register 9-31 (DM9DA) H'0080 045E DMA9 Transfer Count Register 9-32 (DM9TCT) H'0080 0460 DMA0 Software Request Generation Register 9-29 (DM0SRI) H'0080 0462 DMA1 Software Request Generation Register 9-29 (DM1SRI) H'0080 0464 DMA2 Software Request Generation Register 9-29 (DM2SRI) H'0080 0466 DMA3 Software Request Generation Register 9-29 (DM3SRI) H'0080 0468 DMA4 Software Request Generation Register 9-29 (DM4SRI) (Use inhibited area) H'0080 0470 DMA5 Software Request Generation Register 9-29 (DM5SRI) H'0080 0472 DMA6 Software Request Generation Register 9-29 (DM6SRI) H'0080 0474 DMA7 Software Request Generation Register 9-29 (DM7SRI) H'0080 0476 DMA8 Software Request Generation Register 9-29 (DM8SRI) H'0080 0478 DMA9 Software Request Generation Register 9-29 (DM9SRI) (Use inhibited area) H'0080 0480 (Use inhibited area) DMA0 Channel Control Register 2 9-26 (DM0CNT2)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (11/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0482 (Use inhibited area) DMA1 Channel Control Register 2 9-26 (DM1CNT2) H'0080 0484 (Use inhibited area) DMA2 Channel Control Register 2 9-26 (DM2CNT2) H'0080 0486 (Use inhibited area) DMA3 Channel Control Register 2 9-26 (DM3CNT2) H'0080 0488 (Use inhibited area) DMA4 Channel Control Register 2 9-26 (DM4CNT2) (Use inhibited area) H'0080 0490 (Use inhibited area) DMA5 Channel Control Register 2 9-26 (DM5CNT2) H'0080 0492 (Use inhibited area) DMA6 Channel Control Register 2 9-26 (DM6CNT2) H'0080 0494 (Use inhibited area) DMA7 Channel Control Register 2 9-26 (DM7CNT2) H'0080 0496 (Use inhibited area) DMA8 Channel Control Register 2 9-26 (DM8CNT2) H'0080 0498 (Use inhibited area) DMA9 Channel Control Register 2 9-26 (DM9CNT2) (Use inhibited area) H'0080 0500 Port Group 0,1 Input Level Setting Register Port Group 3 Input Level Setting Register 8-33 (PG01LEV) (PG3LEV) H'0080 0502 Port Group 4,5 Input Level Setting Register Port Group 6,7 Input Level Setting Register 8-33 (PG45LEV) (PG67LEV) H'0080 0504 Port Group 8 Input Level Setting Register (Use inhibited area) 8-33 (PG8LEV) H'0080 0506 (Use inhibited area) H'0080 0508 Port Group 0,1 Output Drive Capability Setting Register Port Group 3 Output Drive Capability Setting Register 8-35 (PG01DRV) (PG3DRV) H'0080 050A Port Group 4,5 Output Drive Capability Setting Register Port Group 6,7 Output Drive Capability Setting Register 8-35 (PG45DRV) (PG67DRV) H'0080 050C Port Group 8 Output Drive Capability Setting Register P70 Output Drive Capability Setting Register 8-35 (PG8DRV) (P70DRV) 8-36 H'0080 050E (Use inhibited area) H'0080 0510 Noise Canceller Control Register 8-38 (NZCNSLCR) (Use inhibited area) H'0080 0520 PWM Output 0 Disable Control Register GA PWM Output 0 Disable Level Control Register GA 10-168 (PO0DISGACR) (PO0LVGACR) 10-171 H'0080 0522 PWM Output 1 Disable Control Register GA PWM Output 1 Disable Level Control Register GA 10-168 (PO1DISGACR) (PO1LVGACR) 10-171 H'0080 0524 (Use inhibited area) H'0080 0526 PWMOFF 0 Function Enable Register PWMOFF 1 Function Enable Register 10-173 (PWMOFF0EN) (PWMOFF1EN) H'0080 0528 (Use inhibited area) H'0080 052A CAN Bus Mode Control Register DD Input Pin Select Register 13-23 (CANBUSCR) (DDSEL) 14-6 (Use inhibited area) H'0080 0530 RAM Write Monitor Interrupt Status Register 6-4 (RAMWRIST) H'0080 0532 (Use inhibited area) H'0080 0534 RAM Write Source Status Register 6-5 (RAMWRFST) H'0080 0536 (Use inhibited area) H'0080 0538 RAM Write Disable Control Register 6-6 (RAMWRCNT) H'0080 053A (Use inhibited area)

3-2132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (12/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 053C (Use inhibited area) RAM Write Disable Protect Register 6-7 (RAMWRPROT) (Use inhibited area) H'0080 0600 Dummy Access area (Note1) Dummy Access area (Note1) 3-46 H'0080 0602 Dummy Access area (Note1) Dummy Access area (Note1) 3-46 (Use inhibited area) H'0080 0700 P0 Data Register P1 Data Register 8-12 (P0DATA) (P1DATA) H'0080 0702 P2 Data Register P3 Data Register 8-12 (P2DATA) (P3DATA) H'0080 0704 P4 Data Register (Use inhibited area) 8-12 (P4DATA) H'0080 0706 P6 Data Register P7 Data Register 8-12 (P6DATA) (P7DATA) H'0080 0708 P8 Data Register P9 Data Register 8-12 (P8DATA) (P9DATA) H'0080 070A P10 Data Register P11 Data Register 8-12 (P10DATA) (P11DATA) H'0080 070C P12 Data Register P13 Data Register 8-12 (P12DATA) (P13DATA) H'0080 070E (Use inhibited area) P15 Data Register 8-12 (P15DATA) H'0080 0710 (Use inhibited area) P17 Data Register 8-12 (P17DATA) (Use inhibited area) H'0080 0716 P22 Data Register (Use inhibited area) 8-12 (P22DATA) (Use inhibited area) H'0080 0720 P0 Direction Register P1 Direction Register 8-13 (P0DIR) (P1DIR) H'0080 0722 P2 Direction Register P3 Direction Register 8-13 (P2DIR) (P3DIR) H'0080 0724 P4 Direction Register (Use inhibited area) 8-13 (P4DIR) H'0080 0726 P6 Direction Register P7 Direction Register 8-13 (P6DIR) (P7DIR) H'0080 0728 P8 Direction Register P9 Direction Register 8-13 (P8DIR) (P9DIR) H'0080 072A P10 Direction Register P11 Direction Register 8-13 (P10DIR) (P11DIR) H'0080 072C P12 Direction Register P13 Direction Register 8-13 (P12DIR) (P13DIR) H'0080 072E (Use inhibited area) P15 Direction Register 8-13 (P15DIR) H'0080 0730 (Use inhibited area) P17 Direction Register 8-13 (P17DIR) (Use inhibited area) H'0080 0736 P22 Direction Register (Use inhibited area) 8-13 (P22DIR) (Use inhibited area) H'0080 0740 P0 Operation Mode Register P1 Operation Mode Register 8-14.17-5 (P0MOD) (P1MOD) 8-15,17-7 H'0080 0742 P2 Operation Mode Register P3 Operation Mode Register 8-16,17-8 (P2MOD) (P3MOD) 8-17,17-9 H'0080 0744 P4 Operation Mode Register Port Input Special Function Control Register 8-18,17-10 (P4MOD) (PICNT) 8-29,20-3 H'0080 0746 (Use inhibited area) P7 Operation Mode Register 8-19,17-11 (P7MOD) 20-9 H'0080 0748 P8 Operation Mode Register P9 Operation Mode Register 8-20 (P8MOD) (P9MOD) 8-21 H'0080 074A P10 Operation Mode Register P11 Operation Mode Register 8-22 (P10MOD) (P11MOD) 8-23

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (13/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 074C P12 Operation Mode Register P13 Operation Mode Register 8-24,17-12 (P12MOD) (P13MOD) 8-25 H'0080 074E (Use inhibited area) P15 Operation Mode Register 8-26,17-13 (P15MOD) 20-10 H'0080 0750 (Use inhibited area) P17 Operation Mode Register 8-27 (P17MOD) (Use inhibited area) H'0080 0756 P22 Operation Mode Register (Use inhibited area) 8-28 (P22MOD) 17-14 (Use inhibited area) H'0080 0760 P0 Peripheral Function Select Register P1 Peripheral Function Select Register 8-14,17-6 (P0SMOD) (P1SMOD) 8-15,17-7 H'0080 0762 (Use inhibited area) P3 Peripheral Function Select Register 8-17 (P3SMOD) 17-9 H'0080 0764 P4 Peripheral Function Select Register (Use inhibited area) 8-18 (P4SMOD) 17-10 H'0080 0766 (Use inhibited area) P7 Peripheral Function Select Register 8-19,17-11 (P7SMOD) 20-9 H'0080 0768 P8 Peripheral Function Select Register P9 Peripheral Function Select Register 8-20 (P8SMOD) (P9SMOD) 8-21 H'0080 076A P10 Peripheral Function Select Register P11 Peripheral Function Select Register 8-22 (P10SMOD) (P11SMOD) 8-23 H'0080 076C P12 Peripheral Function Select Register P13 Peripheral Function Select Register 8-24,17-12 (P12SMOD) (P13SMOD) 8-25 H'0080 076E (Use inhibited area) P15 Peripheral Function Select Register 8-26,17-13 (P15SMOD) 20-10 H'0080 0770 (Use inhibited area) P17 Peripheral Function Select Register 8-27 (P17SMOD) (Use inhibited area) H'0080 0776 P22 Peripheral Function Select Register (Use inhibited area) 8-28 (P22SMOD) 17-14 H'0080 0778 (Use inhibited area) H'0080 077A (Use inhibited area) RTD Write Function Disable Control Register 15-3 (WRRDIS) H'0080 077C (Use inhibited area) H'0080 077E (Use inhibited area) Bus Mode Control Register 17-15 (BUSMODC) H'0080 0780 PWM Output 0 Disable Control Register GB PWM Output 0 Disable Level Control Register GB 10-168 (PO0DISGBCR) (PO0LVGBCR) 10-171 H'0080 0782 PWM Output 1 Disable Control Register GB PWM Output 1 Disable Level Control Register GB 10-169 (PO1DISGBCR) (PO1LVGBCR) 10-171 H'0080 0784 (Use inhibited area) H'0080 0786 Clock Control Register (Use inhibited area) 20-5 (CLKCR) (Use inhibited area) H'0080 078C TID0 Counter 10-140 (TID0CT) H'0080 078E TID0 Reload Register 10-140 (TID0RL) H'0080 0790 TOU0_0 Counter (Upper) 10-157 (TOU00CTW) (TOU00CTH) H'0080 0792 (Lower) 10-159 (TOU00CT) H'0080 0794 TOU0_0 Reload Register TOU0_0 Reload 1 Register 10-160 (TOU00RLW) (TOU00RL1) 10-162 H'0080 0796 TOU0_0 Reload 0 Register 10-161 (TOU00RL0) H'0080 0798 TOU0_1 Counter (Upper) 10-157 (TOU01CTW) (TOU01CTH) H'0080 079A (Lower) 10-159 (TOU01CT)

3-2332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (14/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 079C TOU0_1 Reload Register TOU0_1 Reload 1 Register 10-160 (TOU01RLW) (TOU01RL1) 10-162 H'0080 079E TOU0_1 Reload 0 Register 10-161 (TOU01RL0) H'0080 07A0 TOU0_2 Counter (Upper) 10-157 (TOU02CTW) (TOU02CTH) H'0080 07A2 (Lower) 10-159 (TOU02CT) H'0080 07A4 TOU0_2 Reload Register TOU0_2 Reload 1 Register 10-160 (TOU02RLW) (TOU02RL1) 10-162 H'0080 07A6 TOU0_2 Reload 0 Register 10-161 (TOU02RL0) H'0080 07A8 TOU0_3 Counter (Upper) 10-157 (TOU03CTW) (TOU03CTH) H'0080 07AA (Lower) 10-159 (TOU03CT) H'0080 07AC TOU0_3 Reload Register TOU0_3 Reload 1 Register 10-160 (TOU03RLW) (TOU03RL1) 10-162 H'0080 07AE TOU0_3 Reload 0 Register 10-161 (TOU03RL0) H'0080 07B0 TOU0_4 Counter (Upper) 10-157 (TOU04CTW) (TOU04CTH) H'0080 07B2 (Lower) 10-159 (TOU04CT) H'0080 07B4 TOU0_4 Reload Register TOU0_4 Reload 1 Register 10-160 (TOU04RLW) (TOU04RL1) 10-162 H'0080 07B6 TOU0_4 Reload 0 Register 10-161 (TOU04RL0) H'0080 07B8 TOU0_5 Counter (Upper) 10-157 (TOU05CTW) (TOU05CTH) H'0080 07BA (Lower) 10-159 (TOU05CT) H'0080 07BC TOU0_5 Reload Register TOU0_5 Reload 1 Register 10-160 (TOU05RLW) (TOU05RL1) 10-162 H'0080 07BE TOU0_5 Reload 0 Register 10-161 (TOU05RL0) H'0080 07C0 TOU0_6 Counter (Upper) 10-157 (TOU06CTW) (TOU06CTH) H'0080 07C2 (Lower) 10-159 (TOU06CT) H'0080 07C4 TOU0_6 Reload Register TOU0_6 Reload 1 Register 10-160 (TOU06RLW) (TOU06RL1) 10-162 H'0080 07C6 TOU0_6 Reload 0 Register 10-161 (TOU06RL0) H'0080 07C8 TOU0_7 Counter (Upper) 10-157 (TOU07CTW) (TOU07CTH) H'0080 07CA (Lower) 10-159 (TOU07CT) H'0080 07CC TOU0_7 Reload Register TOU0_7 Reload 1 Register 10-160 (TOU07RLW) (TOU07RL1) 10-162 H'0080 07CE TOU0_7 Reload 0 Register 10-161 (TOU07RL0) H'0080 07D0 Prescaler Register 3 TID0 Control & Prescaler 3 Enable Register 10-13 (PRS3) (TID0PRS3EN) 10-138 H'0080 07D2 TOU0 Interrupt Request Mask Register TOU0 Interrupt Request Status Register 10-56 (TOU0IMA) (TOU0IST) H'0080 07D4 Shorting Prevention Function F/F21-26 Protect Register F/F21-28 Protect Register 10-155 (SHFF2126P) (FF2128P) 10-31 H'0080 07D6 Shorting Prevention Function F/F21-26 Data Register F/F21-28 Data Register 10-156 (SHFF2126D) (FF2128D) 10-33 H'0080 07D8 TOU0 Control Register 1 10-153 (TOU0CR1) H'0080 07DA TOU0 Control Register 0 10-153 (TOU0CR0) H'0080 07DC (Use inhibited area) TOU0 Enable Protect Register 10-163 (TOU0PRO) H'0080 07DE (Use inhibited area) TOU0 Count Enable Register 10-164 (TOU0CEN)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (15/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 07E0 PWMOFF0 Input Processing Control Register TIN24,25 Input Processing Control Register 10-166 (PWMOFF0CR) (TIN2425CR) 10-26 H'0080 07E2 TIN24,25 Interrupt Request Mask Register TIN24,25 Interrupt Request Status Register 10-52 (TIN2425IMA) (TIN2425IST) (Use inhibited area) H'0080 07E8 Virtual Flash L Bank Register 0 6-24 (FELBANK0) H'0080 07EA Virtual Flash L Bank Register 1 6-24 (FELBANK1) H'0080 07EC Virtual Flash L Bank Register 2 6-24 (FELBANK2) H'0080 07EE Virtual Flash L Bank Register 3 6-24 (FELBANK3) H'0080 07F0 Virtual Flash L Bank Register 4 (Note 3) 6-24 (FELBANK4) H'0080 07F2 Virtual Flash L Bank Register 5 (Note 3) 6-24 (FELBANK5) H'0080 07F4 Virtual Flash L Bank Register 6 (Note 3) 6-24 (FELBANK6) H'0080 07F6 Virtual Flash L Bank Register 7 (Note 3) 6-24 (FELBANK7) H'0080 07F8 Virtual Flash L Bank Register 8 (Note 2) 6-24 (FELBANK8) H'0080 07FA Virtual Flash L Bank Register 9 (Note 2) 6-24 (FELBANK9) H'0080 07FC Virtual Flash L Bank Register 10 (Note 2) 6-24 (FELBANK10) H'0080 07FE Virtual Flash L Bank Register 11 (Note 2) 6-24 (FELBANK11) H'0080 0800 Virtual Flash L Bank Register 12 (Note 2) 6-24 (FELBANK12) H'0080 0802 Virtual Flash L Bank Register 13 (Note 2) 6-24 (FELBANK13) H'0080 0804 Virtual Flash L Bank Register 14 (Note 2) 6-24 (FELBANK14) H'0080 0806 Virtual Flash L Bank Register 15 (Note 2) 6-24 (FELBANK15) (Use inhibited area) H'0080 0A00 SIO45 Interrupt Request Status Register SIO45 Interrupt Request Mask Register 12-9 (SI45STAT) (SI45MASK) 12-10 H'0080 0A02 SIO45 Interrupt Request Source Select Register (Use inhibited area) 12-11 (SI45SEL) (Use inhibited area) H'0080 0A10 SIO4 Transmit Control Register SIO4 Transmit/Receive Mode Register 12-14 (S4TCNT) (S4MOD) 12-15 H'0080 0A12 SIO4 Transmit Buffer Register 12-19 (S4TXB) H'0080 0A14 SIO4 Receive Buffer Register 12-20 (S4RXB) H'0080 0A16 SIO4 Receive Control Register SIO4 Baud Rate Register 12-21 (S4RCNT) (S4BAUR) 12-24 H'0080 0A18 SIO4 Special Mode Register (Use inhibited area) 12-27 (S4SMOD) (Use inhibited area) H'0080 0A20 SIO5 Transmit Control Register SIO5 Transmit/Receive Mode Register 12-14 (S5TCNT) (S5MOD) 12-15 H'0080 0A22 SIO5 Transmit Buffer Register 12-19 (S5TXB) H'0080 0A24 SIO5 Receive Buffer Register 12-20 (S5RXB) H'0080 0A26 SIO5 Receive Control Register SIO5 Baud Rate Register 12-21 (S5RCNT) (S5BAUR) 12-24 H'0080 0A28 SIO5 Special Mode Register (Use inhibited area) 12-27 (S5SMOD) (Use inhibited area)

3-2532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (16/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0B8C TID1 Counter 10-140 (TID1CT) H'0080 0B8E TID1 Reload Register 10-140 (TID1RL) H'0080 0B90 TOU1_0 Counter (Upper) 10-157 (TOU10CTW) (TOU10CTH) H'0080 0B92 (Lower) 10-159 (TOU10CT) H'0080 0B94 TOU1_0 Reload Register TOU1_0 Reload 1 Register 10-160 (TOU10RLW) (TOU10RL1) 10-162 H'0080 0B96 TOU1_0 Reload 0 Register 10-161 (TOU10RL0) H'0080 0B98 TOU1_1 Counter (Upper) 10-157 (TOU11CTW) (TOU11CTH) H'0080 0B9A (Lower) 10-159 (TOU11CT) H'0080 0B9C TOU1_1 Reload Register TOU1_1 Reload 1 Register 10-160 (TOU11RLW) (TOU11RL1) 10-162 H'0080 0B9E TOU1_1 Reload 0 Register 10-161 (TOU11RL0) H'0080 0BA0 TOU1_2 Counter (Upper) 10-157 (TOU12CTW) (TOU12CTH) H'0080 0BA2 (Lower) 10-159 (TOU12CT) H'0080 0BA4 TOU1_2 Reload Register TOU1_2 Reload 1 Register 10-160 (TOU12RLW) (TOU12RL1) 10-162 H'0080 0BA6 TOU1_2 Reload 0 Register 10-161 (TOU12RL0) H'0080 0BA8 TOU1_3 Counter (Upper) 10-157 (TOU13CTW) (TOU13CTH) H'0080 0BAA (Lower) 10-159 (TOU13CT) H'0080 0BAC TOU1_3 Reload Register TOU1_3 Reload 1 Register 10-160 (TOU13RLW) (TOU13RL1) 10-162 H'0080 0BAE TOU1_3 Reload 0 Register 10-161 (TOU13RL0) H'0080 0BB0 TOU1_4 Counter (Upper) 10-157 (TOU14CTW) (TOU14CTH) H'0080 0BB2 (Lower) 10-159 (TOU14CT) H'0080 0BB4 TOU1_4 Reload Register TOU1_4 Reload 1 Register 10-160 (TOU14RLW) (TOU14RL1) 10-162 H'0080 0BB6 TOU1_4 Reload 0 Register 10-161 (TOU14RL0) H'0080 0BB8 TOU1_5 Counter (Upper) 10-157 (TOU15CTW) (TOU15CTH) H'0080 0BBA (Lower) 10-159 (TOU15CT) H'0080 0BBC TOU1_5 Reload Register TOU1_5 Reload 1 Register 10-160 (TOU15RLW) (TOU15RL1) 10-162 H'0080 0BBE TOU1_5 Reload 0 Register 10-161 (TOU15RL0) H'0080 0BC0 TOU1_6 Counter (Upper) 10-157 (TOU16CTW) (TOU16CTH) H'0080 0BC2 (Lower) 10-159 (TOU16CT) H'0080 0BC4 TOU1_6 Reload Register TOU1_6 Reload 1 Register 10-160 (TOU16RLW) (TOU16RL1) 10-162 H'0080 0BC6 TOU1_6 Reload 0 Register 10-161 (TOU16RL0) H'0080 0BC8 TOU1_7 Counter (Upper) 10-157 (TOU17CTW) (TOU17CTH) H'0080 0BCA (Lower) 10-159 (TOU17CT) H'0080 0BCC TOU1_7 Reload Register TOU1_7 Reload 1 Register 10-160 (TOU17RLW) (TOU17RL1) 10-162 H'0080 0BCE TOU1_7 Reload 0 Register 10-161 (TOU17RL0)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (17/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0BD0 Prescaler Register 4 TID1 Control & Prescaler 4 Enable Register 10-13 (PRS4) (TID1PRS4EN) 10-139 H'0080 0BD2 TOU1 Interrupt Request Mask Register TOU1 Interrupt Request Status Register 10-58 (TOU1IMA) (TOU1IST) H'0080 0BD4 Shorting Prevention Function F/F29-34 Protect Register F/F29-36 Protect Register 10-155 (SHFF2934P) (FF2936P) 10-31 H'0080 0BD6 Shorting Prevention Function F/F29-34 Data Register F/F29-36 Data Register 10-156 (SHFF2934D) (FF2936D) 10-33 H'0080 0BD8 TOU1 Control Register 1 10-154 (TOU1CR1) H'0080 0BDA TOU1 Control Register 0 10-154 (TOU1CR0) H'0080 0BDC (Use inhibited area) TOU1 Enable Protect Register 10-163 (TOU1PRO) H'0080 0BDE (Use inhibited area) TOU1 Count Enable Register 10-164 (TOU1CEN) H'0080 0BE0 PWMOFF1 Input Processing Control Register TIN26,27 Input Processing Control Register 10-166 (PWMOFF1CR) (TIN2627CR) 10-26 H'0080 0BE2 TIN26,27 Interrupt Request Mask Register TIN26,27 Interrupt Request Status Register 10-53 (TIN2627IMA) (TIN2627IST) (Use inhibited area) H'0080 0FE0 TML1 Counter (Upper) 10-132 (TML1CT) (TML1CTH) H'0080 0FE2 (Lower) (TML1CTL) (Use inhibited area) H'0080 0FEA (Use inhibited area) TML1 Control Register 10-131 (TML1CR) (Use inhibited area) H'0080 0FF0 TML1 Measure 3 Register (Upper) 10-132 (TML1MR3) (TML1MR3H) H'0080 0FF2 (Lower) (TML1MR3L) H'0080 0FF4 TML1 Measure 2 Register (Upper) 10-132 (TML1MR2) (TML1MR2H) H'0080 0FF6 (Lower) (TML1MR2L) H'0080 0FF8 TML1 Measure 1 Register (Upper) 10-132 (TML1MR1) (TML1MR1H) H'0080 0FFA (Lower) (TML1MR1L) H'0080 0FFC TML1 Measure 0 Register (Upper) 10-132 (TML1MR0) (TML1MR0H) H'0080 0FFE (Lower) (TML1MR0L)

3-2732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (18/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1000 CAN0 Control Register 13-26 (CAN0CNT) H'0080 1002 CAN0 Status Register 13-29 (CAN0STAT) H'0080 1004 (Use inhibited area) H'0080 1006 CAN0 Configuration Register 13-32 (CAN0CONF) H'0080 1008 CAN0 Timestamp Count Register 13-35 (CAN0TSTMP) H'0080 100A CAN0 Receive Error Count Register CAN0 Transmit Error Count Register 13-36 (CAN0REC) (CAN0TEC) H'0080 100C CAN0 Slot Interrupt Request Status Register (Upper) 13-40 (CAN0SLISTW) (CAN0SLIST) H'0080 100E (Lower) (CAN0SLISTL) H'0080 1010 CAN0 Slot Interrupt Request Mask Register (Upper) 13-42 (CAN0SLIMKW) (CAN0SLIMK) H'0080 1012 (Lower) (CAN0SLIMKL) H'0080 1014 CAN0 Error Interrupt Request Status Register CAN0 Error Interrupt Request Mask Register 13-43 (CAN0ERIST) (CAN0ERIMK) 13-44 H'0080 1016 CAN0 Baud Rate Prescaler CAN0 Cause of Error Register 13-37 (CAN0BRP) (CAN0EF) 13-67 H'0080 1018 CAN0 Mode Register CAN0 DMA Transfer Request Select Register 13-69 (CAN0MOD) (CAN0DMARQ) 13-70 H'0080 101A CAN0 Message Slot Number Register CAN0 Clock Select Register 13-71 (CAN0MSN) (CAN0CKSEL) 13-72 H'0080 101C CAN0 Frame Format Select Register (Upper) 13-74 (CAN0FFSW) (CAN0FFS) H'0080 101E (Lower) (CAN0FFSL) H'0080 1020 CAN0 Global Mask Register A Standard ID0 CAN0 Global Mask Register A Standard ID1 13-76 (C0GMSKAS0) (C0GMSKAS1) H'0080 1022 CAN0 Global Mask Register A Extended ID0 CAN0 Global Mask Register A Extended ID1 13-77 (C0GMSKAE0) (C0GMSKAE1) H'0080 1024 CAN0 Global Mask Register A Extended ID2 (Use inhibited area) 13-78 (C0GMSKAE2) H'0080 1026 (Use inhibited area) H'0080 1028 CAN0 Global Mask Register B Standard ID0 CAN0 Global Mask Register B Standard ID1 13-76 (C0GMSKBS0) (C0GMSKBS1) H'0080 102A CAN0 Global Mask Register B Extended ID0 CAN0 Global Mask Register B Extended ID1 13-77 (C0GMSKBE0) (C0GMSKBE1) H'0080 102C CAN0 Global Mask Register B Extended ID2 (Use inhibited area) 13-78 (C0GMSKBE2) H'0080 102E (Use inhibited area) H'0080 1030 CAN0 Local Mask Register A Standard ID0 CAN0 Local Mask Register A Standard ID1 13-76 (C0LMSKAS0) (C0LMSKAS1) H'0080 1032 CAN0 Local Mask Register A Extended ID0 CAN0 Local Mask Register A Extended ID1 13-77 (C0LMSKAE0) (C0LMSKAE1) H'0080 1034 CAN0 Local Mask Register A Extended ID2 (Use inhibited area) 13-78 (C0LMSKAE2) H'0080 1036 (Use inhibited area) H'0080 1038 CAN0 Local Mask Register B Standard ID0 CAN0 Local Mask Register B Standard ID1 13-76 (C0LMSKBS0) (C0LMSKBS1) H'0080 103A CAN0 Local Mask Register B Extended ID0 CAN0 Local Mask Register B Extended ID1 13-77 (C0LMSKBE0) (C0LMSKBE1) H'0080 103C CAN0 Local Mask Register B Extended ID2 (Use inhibited area) 13-78 (C0LMSKBE2) H'0080 103E (Use inhibited area) H'0080 1040 CAN0 Single-Shot Mode Control Register (Upper) 13-80 (CAN0SSMODEW) (CAN0SSMODE) H'0080 1042 (Lower) (CAN0SSMODEL)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (19/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1044 CAN0 Single-Shot Interrupt Request Status Register (Upper) 13-45 (CAN0SSISTW) (CAN0SSIST) H'0080 1046 (Lower) (CAN0SSISTL) H'0080 1048 CAN0 Single-Shot Interrupt Request Mask Register (Upper) 13-47 (CAN0SSIMKW) (CAN0SSIMK) H'0080 104A (Lower) (CAN0SSIMKL) (Use inhibited area) H'0080 1050 CAN0 Message Slot 0 Control Register CAN0 Message Slot 1 Control Register 13-82 (C0MSL0CNT) (C0MSL1CNT) H'0080 1052 CAN0 Message Slot 2 Control Register CAN0 Message Slot 3 Control Register 13-82 (C0MSL2CNT) (C0MSL3CNT) H'0080 1054 CAN0 Message Slot 4 Control Register CAN0 Message Slot 5 Control Register 13-82 (C0MSL4CNT) (C0MSL5CNT) H'0080 1056 CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register 13-82 (C0MSL6CNT) (C0MSL7CNT) H'0080 1058 CAN0 Message Slot 8 Control Register CAN0 Message Slot 9 Control Register 13-82 (C0MSL8CNT) (C0MSL9CNT) H'0080 105A CAN0 Message Slot 10 Control Register CAN0 Message Slot 11 Control Register 13-82 (C0MSL10CNT) (C0MSL11CNT) H'0080 105C CAN0 Message Slot 12 Control Register CAN0 Message Slot 13 Control Register 13-82 (C0MSL12CNT) (C0MSL13CNT) H'0080 105E CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register 13-82 (C0MSL14CNT) (C0MSL15CNT) H'0080 1060 CAN0 Message Slot 16 Control Register CAN0 Message Slot 17 Control Register 13-82 (C0MSL16CNT) (C0MSL17CNT) H'0080 1062 CAN0 Message Slot 18 Control Register CAN0 Message Slot 19 Control Register 13-82 (C0MSL18CNT) (C0MSL19CNT) H'0080 1064 CAN0 Message Slot 20 Control Register CAN0 Message Slot 21 Control Register 13-82 (C0MSL20CNT) (C0MSL21CNT) H'0080 1066 CAN0 Message Slot 22 Control Register CAN0 Message Slot 23 Control Register 13-82 (C0MSL22CNT) (C0MSL23CNT) H'0080 1068 CAN0 Message Slot 24 Control Register CAN0 Message Slot 25 Control Register 13-82 (C0MSL24CNT) (C0MSL25CNT) H'0080 106A CAN0 Message Slot 26 Control Register CAN0 Message Slot 27 Control Register 13-82 (C0MSL26CNT) (C0MSL27CNT) H'0080 106C CAN0 Message Slot 28 Control Register CAN0 Message Slot 29 Control Register 13-82 (C0MSL28CNT) (C0MSL29CNT) H'0080 106E CAN0 Message Slot 30 Control Register CAN0 Message Slot 31 Control Register 13-82 (C0MSL30CNT) (C0MSL31CNT) (Use inhibited area) H'0080 1100 CAN0 Message Slot 0 Standard ID0 CAN0 Message Slot 0 Standard ID1 13-86 (C0MSL0SID0) (C0MSL0SID1) 13-88 H'0080 1102 CAN0 Message Slot 0 Extended ID0 CAN0 Message Slot 0 Extended ID1 13-90 (C0MSL0EID0) (C0MSL0EID1) 13-92 H'0080 1104 CAN0 Message Slot 0 Extended ID2 CAN0 Message Slot 0 Data Length Register 13-94 (C0MSL0EID2) (C0MSL0DLC) 13-96 H'0080 1106 CAN0 Message Slot 0 Data 0 CAN0 Message Slot 0 Data 1 13-98 (C0MSL0DT0) (C0MSL0DT1) 13-100 H'0080 1108 CAN0 Message Slot 0 Data 2 CAN0 Message Slot 0 Data 3 13-102 (C0MSL0DT2) (C0MSL0DT3) 13-104 H'0080 110A CAN0 Message Slot 0 Data 4 CAN0 Message Slot 0 Data 5 13-106 (C0MSL0DT4) (C0MSL0DT5) 13-108 H'0080 110C CAN0 Message Slot 0 Data 6 CAN0 Message Slot 0 Data 7 13-110 (C0MSL0DT6) (C0MSL0DT7) 13-112 H'0080 110E CAN0 Message Slot 0 Timestamp 13-114 (C0MSL0TSP) H'0080 1110 CAN0 Message Slot 1 Standard ID0 CAN0 Message Slot 1 Standard ID1 13-86 (C0MSL1SID0) (C0MSL1SID1) 13-88 H'0080 1112 CAN0 Message Slot 1 Extended ID0 CAN0 Message Slot 1 Extended ID1 13-90 (C0MSL1EID0) (C0MSL1EID1) 13-92 H'0080 1114 CAN0 Message Slot 1 Extended ID2 CAN0 Message Slot 1 Data Length Register 13-94 (C0MSL1EID2) (C0MSL1DLC) 13-96 H'0080 1116 CAN0 Message Slot 1 Data 0 CAN0 Message Slot 1 Data 1 13-98 (C0MSL1DT0) (C0MSL1DT1) 13-100 H'0080 1118 CAN0 Message Slot 1 Data 2 CAN0 Message Slot 1 Data 3 13-102 (C0MSL1DT2) (C0MSL1DT3) 13-104

3-2932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (20/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 111A CAN0 Message Slot 1 Data 4 CAN0 Message Slot 1 Data 5 13-106 (C0MSL1DT4) (C0MSL1DT5) 13-108 H'0080 111C CAN0 Message Slot 1 Data 6 CAN0 Message Slot 1 Data 7 13-110 (C0MSL1DT6) (C0MSL1DT7) 13-112 H'0080 111E CAN0 Message Slot 1 Timestamp 13-114 (C0MSL1TSP) H'0080 1120 CAN0 Message Slot 2 Standard ID0 CAN0 Message Slot 2 Standard ID1 13-86 (C0MSL2SID0) (C0MSL2SID1) 13-88 H'0080 1122 CAN0 Message Slot 2 Extended ID0 CAN0 Message Slot 2 Extended ID1 13-90 (C0MSL2EID0) (C0MSL2EID1) 13-92 H'0080 1124 CAN0 Message Slot 2 Extended ID2 CAN0 Message Slot 2 Data Length Register 13-94 (C0MSL2EID2) (C0MSL2DLC) 13-96 H'0080 1126 CAN0 Message Slot 2 Data 0 CAN0 Message Slot 2 Data 1 13-98 (C0MSL2DT0) (C0MSL2DT1) 13-100 H'0080 1128 CAN0 Message Slot 2 Data 2 CAN0 Message Slot 2 Data 3 13-102 (C0MSL2DT2) (C0MSL2DT3) 13-104 H'0080 112A CAN0 Message Slot 2 Data 4 CAN0 Message Slot 2 Data 5 13-106 (C0MSL2DT4) (C0MSL2DT5) 13-108 H'0080 112C CAN0 Message Slot 2 Data 6 CAN0 Message Slot 2 Data 7 13-110 (C0MSL2DT6) (C0MSL2DT7) 13-112 H'0080 112E CAN0 Message Slot 2 Timestamp 13-114 (C0MSL2TSP) H'0080 1130 CAN0 Message Slot 3 Standard ID0 CAN0 Message Slot 3 Standard ID1 13-86 (C0MSL3SID0) (C0MSL3SID1) 13-88 H'0080 1132 CAN0 Message Slot 3 Extended ID0 CAN0 Message Slot 3 Extended ID1 13-90 (C0MSL3EID0) (C0MSL3EID1) 13-92 H'0080 1134 CAN0 Message Slot 3 Extended ID2 CAN0 Message Slot 3 Data Length Register 13-94 (C0MSL3EID2) (C0MSL3DLC) 13-96 H'0080 1136 CAN0 Message Slot 3 Data 0 CAN0 Message Slot 3 Data 1 13-98 (C0MSL3DT0) (C0MSL3DT1) 13-100 H'0080 1138 CAN0 Message Slot 3 Data 2 CAN0 Message Slot 3 Data 3 13-102 (C0MSL3DT2) (C0MSL3DT3) 13-104 H'0080 113A CAN0 Message Slot 3 Data 4 CAN0 Message Slot 3 Data 5 13-106 (C0MSL3DT4) (C0MSL3DT5) 13-108 H'0080 113C CAN0 Message Slot 3 Data 6 CAN0 Message Slot 3 Data 7 13-110 (C0MSL3DT6) (C0MSL3DT7) 13-112 H'0080 113E CAN0 Message Slot 3 Timestamp 13-114 (C0MSL3TSP) H'0080 1140 CAN0 Message Slot 4 Standard ID0 CAN0 Message Slot 4 Standard ID1 13-86 (C0MSL4SID0) (C0MSL4SID1) 13-88 H'0080 1142 CAN0 Message Slot 4 Extended ID0 CAN0 Message Slot 4 Extended ID1 13-90 (C0MSL4EID0) (C0MSL4EID1) 13-92 H'0080 1144 CAN0 Message Slot 4 Extended ID2 CAN0 Message Slot 4 Data Length Register 13-94 (C0MSL4EID2) (C0MSL4DLC) 13-96 H'0080 1146 CAN0 Message Slot 4 Data 0 CAN0 Message Slot 4 Data 1 13-98 (C0MSL4DT0) (C0MSL4DT1) 13-100 H'0080 1148 CAN0 Message Slot 4 Data 2 CAN0 Message Slot 4 Data 3 13-102 (C0MSL4DT2) (C0MSL4DT3) 13-104 H'0080 114A CAN0 Message Slot 4 Data 4 CAN0 Message Slot 4 Data 5 13-106 (C0MSL4DT4) (C0MSL4DT5) 13-108 H'0080 114C CAN0 Message Slot 4 Data 6 CAN0 Message Slot 4 Data 7 13-110 (C0MSL4DT6) (C0MSL4DT7) 13-112 H'0080 114E CAN0 Message Slot 4 Timestamp 13-114 (C0MSL4TSP) H'0080 1150 CAN0 Message Slot 5 Standard ID0 CAN0 Message Slot 5 Standard ID1 13-86 (C0MSL5SID0) (C0MSL5SID1) 13-88 H'0080 1152 CAN0 Message Slot 5 Extended ID0 CAN0 Message Slot 5 Extended ID1 13-90 (C0MSL5EID0) (C0MSL5EID1) 13-92 H'0080 1154 CAN0 Message Slot 5 Extended ID2 CAN0 Message Slot 5 Data Length Register 13-94 (C0MSL5EID2) (C0MSL5DLC) 13-96 H'0080 1156 CAN0 Message Slot 5 Data 0 CAN0 Message Slot 5 Data 1 13-98 (C0MSL5DT0) (C0MSL5DT1) 13-100 H'0080 1158 CAN0 Message Slot 5 Data 2 CAN0 Message Slot 5 Data 3 13-102 (C0MSL5DT2) (C0MSL5DT3) 13-104 H'0080 115A CAN0 Message Slot 5 Data 4 CAN0 Message Slot 5 Data 5 13-106 (C0MSL5DT4) (C0MSL5DT5) 13-108 H'0080 115C CAN0 Message Slot 5 Data 6 CAN0 Message Slot 5 Data 7 13-110 (C0MSL5DT6) (C0MSL5DT7) 13-112 H'0080 115E CAN0 Message Slot 5 Timestamp 13-114 (C0MSL5TSP)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (21/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1160 CAN0 Message Slot 6 Standard ID0 CAN0 Message Slot 6 Standard ID1 13-86 (C0MSL6SID0) (C0MSL6SID1) 13-88 H'0080 1162 CAN0 Message Slot 6 Extended ID0 CAN0 Message Slot 6 Extended ID1 13-90 (C0MSL6EID0) (C0MSL6EID1) 13-92 H'0080 1164 CAN0 Message Slot 6 Extended ID2 CAN0 Message Slot 6 Data Length Register 13-94 (C0MSL6EID2) (C0MSL6DLC) 13-96 H'0080 1166 CAN0 Message Slot 6 Data 0 CAN0 Message Slot 6 Data 1 13-98 (C0MSL6DT0) (C0MSL6DT1) 13-100 H'0080 1168 CAN0 Message Slot 6 Data 2 CAN0 Message Slot 6 Data 3 13-102 (C0MSL6DT2) (C0MSL6DT3) 13-104 H'0080 116A CAN0 Message Slot 6 Data 4 CAN0 Message Slot 6 Data 5 13-106 (C0MSL6DT4) (C0MSL6DT5) 13-108 H'0080 116C CAN0 Message Slot 6 Data 6 CAN0 Message Slot 6 Data 7 13-110 (C0MSL6DT6) (C0MSL6DT7) 13-112 H'0080 116E CAN0 Message Slot 6 Timestamp 13-114 (C0MSL6TSP) H'0080 1170 CAN0 Message Slot 7 Standard ID0 CAN0 Message Slot 7 Standard ID1 13-86 (C0MSL7SID0) (C0MSL7SID1) 13-88 H'0080 1172 CAN0 Message Slot 7 Extended ID0 CAN0 Message Slot 7 Extended ID1 13-90 (C0MSL7EID0) (C0MSL7EID1) 13-92 H'0080 1174 CAN0 Message Slot 7 Extended ID2 CAN0 Message Slot 7 Data Length Register 13-94 (C0MSL7EID2) (C0MSL7DLC) 13-96 H'0080 1176 CAN0 Message Slot 7 Data 0 CAN0 Message Slot 7 Data 1 13-98 (C0MSL7DT0) (C0MSL7DT1) 13-100 H'0080 1178 CAN0 Message Slot 7 Data 2 CAN0 Message Slot 7 Data 3 13-102 (C0MSL7DT2) (C0MSL7DT3) 13-104 H'0080 117A CAN0 Message Slot 7 Data 4 CAN0 Message Slot 7 Data 5 13-106 (C0MSL7DT4) (C0MSL7DT5) 13-108 H'0080 117C CAN0 Message Slot 7 Data 6 CAN0 Message Slot 7 Data 7 13-110 (C0MSL7DT6) (C0MSL7DT7) 13-112 H'0080 117E CAN0 Message Slot 7 Timestamp 13-114 (C0MSL7TSP) H'0080 1180 CAN0 Message Slot 8 Standard ID0 CAN0 Message Slot 8 Standard ID1 13-86 (C0MSL8SID0) (C0MSL8SID1) 13-88 H'0080 1182 CAN0 Message Slot 8 Extended ID0 CAN0 Message Slot 8 Extended ID1 13-90 (C0MSL8EID0) (C0MSL8EID1) 13-92 H'0080 1184 CAN0 Message Slot 8 Extended ID2 CAN0 Message Slot 8 Data Length Register 13-94 (C0MSL8EID2) (C0MSL8DLC) 13-96 H'0080 1186 CAN0 Message Slot 8 Data 0 CAN0 Message Slot 8 Data 1 13-98 (C0MSL8DT0) (C0MSL8DT1) 13-100 H'0080 1188 CAN0 Message Slot 8 Data 2 CAN0 Message Slot 8 Data 3 13-102 (C0MSL8DT2) (C0MSL8DT3) 13-104 H'0080 118A CAN0 Message Slot 8 Data 4 CAN0 Message Slot 8 Data 5 13-106 (C0MSL8DT4) (C0MSL8DT5) 13-108 H'0080 118C CAN0 Message Slot 8 Data 6 CAN0 Message Slot 8 Data 7 13-110 (C0MSL8DT6) (C0MSL8DT7) 13-112 H'0080 118E CAN0 Message Slot 8 Timestamp 13-114 (C0MSL8TSP) H'0080 1190 CAN0 Message Slot 9 Standard ID0 CAN0 Message Slot 9 Standard ID1 13-86 (C0MSL9SID0) (C0MSL9SID1) 13-88 H'0080 1192 CAN0 Message Slot 9 Extended ID0 CAN0 Message Slot 9 Extended ID1 13-90 (C0MSL9EID0) (C0MSL9EID1) 13-92 H'0080 1194 CAN0 Message Slot 9 Extended ID2 CAN0 Message Slot 9 Data Length Register 13-94 (C0MSL9EID2) (C0MSL9DLC) 13-96 H'0080 1196 CAN0 Message Slot 9 Data 0 CAN0 Message Slot 9 Data 1 13-98 (C0MSL9DT0) (C0MSL9DT1) 13-100 H'0080 1198 CAN0 Message Slot 9 Data 2 CAN0 Message Slot 9 Data 3 13-102 (C0MSL9DT2) (C0MSL9DT3) 13-104 H'0080 119A CAN0 Message Slot 9 Data 4 CAN0 Message Slot 9 Data 5 13-106 (C0MSL9DT4) (C0MSL9DT5) 13-108 H'0080 119C CAN0 Message Slot 9 Data 6 CAN0 Message Slot 9 Data 7 13-110 (C0MSL9DT6) (C0MSL9DT7) 13-112 H'0080 119E CAN0 Message Slot 9 Timestamp 13-114 (C0MSL9TSP) H'0080 11A0 CAN0 Message Slot 10 Standard ID0 CAN0 Message Slot 10 Standard ID1 13-86 (C0MSL10SID0) (C0MSL10SID1) 13-88 H'0080 11A2 CAN0 Message Slot 10 Extended ID0 CAN0 Message Slot 10 Extended ID1 13-90 (C0MSL10EID0) (C0MSL10EID1) 13-92 H'0080 11A4 CAN0 Message Slot 10 Extended ID2 CAN0 Message Slot 10 Data Length Register 13-94 (C0MSL10EID2) (C0MSL10DLC) 13-96

3-3132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (22/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 11A6 CAN0 Message Slot 10 Data 0 CAN0 Message Slot 10 Data 1 13-98 (C0MSL10DT0) (C0MSL10DT1) 13-100 H'0080 11A8 CAN0 Message Slot 10 Data 2 CAN0 Message Slot 10 Data 3 13-102 (C0MSL10DT2) (C0MSL10DT3) 13-104 H'0080 11AA CAN0 Message Slot 10 Data 4 CAN0 Message Slot 10 Data 5 13-106 (C0MSL10DT4) (C0MSL10DT5) 13-108 H'0080 11AC CAN0 Message Slot 10 Data 6 CAN0 Message Slot 10 Data 7 13-110 (C0MSL10DT6) (C0MSL10DT7) 13-112 H'0080 11AE CAN0 Message Slot 10 Timestamp 13-114 (C0MSL10TSP) H'0080 11B0 CAN0 Message Slot 11 Standard ID0 CAN0 Message Slot 11 Standard ID1 13-86 (C0MSL11SID0) (C0MSL11SID1) 13-88 H'0080 11B2 CAN0 Message Slot 11 Extended ID0 CAN0 Message Slot 11 Extended ID1 13-90 (C0MSL11EID0) (C0MSL11EID1) 13-92 H'0080 11B4 CAN0 Message Slot 11 Extended ID2 CAN0 Message Slot 11 Data Length Register 13-94 (C0MSL11EID2) (C0MSL11DLC) 13-96 H'0080 11B6 CAN0 Message Slot 11 Data 0 CAN0 Message Slot 11 Data 1 13-98 (C0MSL11DT0) (C0MSL11DT1) 13-100 H'0080 11B8 CAN0 Message Slot 11 Data 2 CAN0 Message Slot 11 Data 3 13-102 (C0MSL11DT2) (C0MSL11DT3) 13-104 H'0080 11BA CAN0 Message Slot 11 Data 4 CAN0 Message Slot 11 Data 5 13-106 (C0MSL11DT4) (C0MSL11DT5) 13-108 H'0080 11BC CAN0 Message Slot 11 Data 6 CAN0 Message Slot 11 Data 7 13-110 (C0MSL11DT6) (C0MSL11DT7) 13-112 H'0080 11BE CAN0 Message Slot 11 Timestamp 13-114 (C0MSL11TSP) H'0080 11C0 CAN0 Message Slot 12 Standard ID0 CAN0 Message Slot 12 Standard ID1 13-86 (C0MSL12SID0) (C0MSL12SID1) 13-88 H'0080 11C2 CAN0 Message Slot 12 Extended ID0 CAN0 Message Slot 12 Extended ID1 13-90 (C0MSL12EID0) (C0MSL12EID1) 13-92 H'0080 11C4 CAN0 Message Slot 12 Extended ID2 CAN0 Message Slot 12 Data Length Register 13-94 (C0MSL12EID2) (C0MSL12DLC) 13-96 H'0080 11C6 CAN0 Message Slot 12 Data 0 CAN0 Message Slot 12 Data 1 13-98 (C0MSL12DT0) (C0MSL12DT1) 13-100 H'0080 11C8 CAN0 Message Slot 12 Data 2 CAN0 Message Slot 12 Data 3 13-102 (C0MSL12DT2) (C0MSL12DT3) 13-104 H'0080 11CA CAN0 Message Slot 12 Data 4 CAN0 Message Slot 12 Data 5 13-106 (C0MSL12DT4) (C0MSL12DT5) 13-108 H'0080 11CC CAN0 Message Slot 12 Data 6 CAN0 Message Slot 12 Data 7 13-110 (C0MSL12DT6) (C0MSL12DT7) 13-112 H'0080 11CE CAN0 Message Slot 12 Timestamp 13-114 (C0MSL12TSP) H'0080 11D0 CAN0 Message Slot 13 Standard ID0 CAN0 Message Slot 13 Standard ID1 13-86 (C0MSL13SID0) (C0MSL13SID1) 13-88 H'0080 11D2 CAN0 Message Slot 13 Extended ID0 CAN0 Message Slot 13 Extended ID1 13-90 (C0MSL13EID0) (C0MSL13EID1) 13-92 H'0080 11D4 CAN0 Message Slot 13 Extended ID2 CAN0 Message Slot 13 Data Length Register 13-94 (C0MSL13EID2) (C0MSL13DLC) 13-96 H'0080 11D6 CAN0 Message Slot 13 Data 0 CAN0 Message Slot 13 Data 1 13-98 (C0MSL13DT0) (C0MSL13DT1) 13-100 H'0080 11D8 CAN0 Message Slot 13 Data 2 CAN0 Message Slot 13 Data 3 13-102 (C0MSL13DT2) (C0MSL13DT3) 13-104 H'0080 11DA CAN0 Message Slot 13 Data 4 CAN0 Message Slot 13 Data 5 13-106 (C0MSL13DT4) (C0MSL13DT5) 13-108 H'0080 11DC CAN0 Message Slot 13 Data 6 CAN0 Message Slot 13 Data 7 13-110 (C0MSL13DT6) (C0MSL13DT7) 13-112 H'0080 11DE CAN0 Message Slot 13 Timestamp 13-114 (C0MSL13TSP) H'0080 11E0 CAN0 Message Slot 14 Standard ID0 CAN0 Message Slot 14 Standard ID1 13-86 (C0MSL14SID0) (C0MSL14SID1) 13-88 H'0080 11E2 CAN0 Message Slot 14 Extended ID0 CAN0 Message Slot 14 Extended ID1 13-90 (C0MSL14EID0) (C0MSL14EID1) 13-92 H'0080 11E4 CAN0 Message Slot 14 Extended ID2 CAN0 Message Slot 14 Data Length Register 13-94 (C0MSL14EID2) (C0MSL14DLC) 13-96 H'0080 11E6 CAN0 Message Slot 14 Data 0 CAN0 Message Slot 14 Data 1 13-98 (C0MSL14DT0) (C0MSL14DT1) 13-100 H'0080 11E8 CAN0 Message Slot 14 Data 2 CAN0 Message Slot 14 Data 3 13-102 (C0MSL14DT2) (C0MSL14DT3) 13-104 H'0080 11EA CAN0 Message Slot 14 Data 4 CAN0 Message Slot 14 Data 5 13-106 (C0MSL14DT4) (C0MSL14DT5) 13-108

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (23/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 11EC CAN0 Message Slot 14 Data 6 CAN0 Message Slot 14 Data 7 13-110 (C0MSL14DT6) (C0MSL14DT7) 13-112 H'0080 11EE CAN0 Message Slot 14 Timestamp 13-114 (C0MSL14TSP) H'0080 11F0 CAN0 Message Slot 15 Standard ID0 CAN0 Message Slot 15 Standard ID1 13-86 (C0MSL15SID0) (C0MSL15SID1) 13-88 H'0080 11F2 CAN0 Message Slot 15 Extended ID0 CAN0 Message Slot 15 Extended ID1 13-90 (C0MSL15EID0) (C0MSL15EID1) 13-92 H'0080 11F4 CAN0 Message Slot 15 Extended ID2 CAN0 Message Slot 15 Data Length Register 13-94 (C0MSL15EID2) (C0MSL15DLC) 13-96 H'0080 11F6 CAN0 Message Slot 15 Data 0 CAN0 Message Slot 15 Data 1 13-98 (C0MSL15DT0) (C0MSL15DT1) 13-100 H'0080 11F8 CAN0 Message Slot 15 Data 2 CAN0 Message Slot 15 Data 3 13-102 (C0MSL15DT2) (C0MSL15DT3) 13-104 H'0080 11FA CAN0 Message Slot 15 Data 4 CAN0 Message Slot 15 Data 5 13-106 (C0MSL15DT4) (C0MSL15DT5) 13-108 H'0080 11FC CAN0 Message Slot 15 Data 6 CAN0 Message Slot 15 Data 7 13-110 (C0MSL15DT6) (C0MSL15DT7) 13-112 H'0080 11FE CAN0 Message Slot 15 Timestamp 13-114 (C0MSL15TSP) H'0080 1200 CAN0 Message Slot 16 Standard ID0 CAN0 Message Slot 16 Standard ID1 13-86 (C0MSL16SID0) (C0MSL16SID1) 13-88 H'0080 1202 CAN0 Message Slot 16 Extended ID0 CAN0 Message Slot 16 Extended ID1 13-90 (C0MSL16EID0) (C0MSL16EID1) 13-92 H'0080 1204 CAN0 Message Slot 16 Extended ID2 CAN0 Message Slot 16 Data Length Register 13-94 (C0MSL16EID2) (C0MSL16DLC) 13-96 H'0080 1206 CAN0 Message Slot 16 Data 0 CAN0 Message Slot 16 Data 1 13-98 (C0MSL16DT0) (C0MSL16DT1) 13-100 H'0080 1208 CAN0 Message Slot 16 Data 2 CAN0 Message Slot 16 Data 3 13-102 (C0MSL16DT2) (C0MSL16DT3) 13-104 H'0080 120A CAN0 Message Slot 16 Data 4 CAN0 Message Slot 16 Data 5 13-106 (C0MSL16DT4) (C0MSL16DT5) 13-108 H'0080 120C CAN0 Message Slot 16 Data 6 CAN0 Message Slot 16 Data 7 13-110 (C0MSL16DT6) (C0MSL16DT7) 13-112 H'0080 120E CAN0 Message Slot 16 Timestamp 13-114 (C0MSL16TSP) H'0080 1210 CAN0 Message Slot 17 Standard ID0 CAN0 Message Slot 17 Standard ID1 13-86 (C0MSL17SID0) (C0MSL17SID1) 13-88 H'0080 1212 CAN0 Message Slot 17 Extended ID0 CAN0 Message Slot 17 Extended ID1 13-90 (C0MSL17EID0) (C0MSL17EID1) 13-92 H'0080 1214 CAN0 Message Slot 17 Extended ID2 CAN0 Message Slot 17 Data Length Register 13-94 (C0MSL17EID2) (C0MSL17DLC) 13-96 H'0080 1216 CAN0 Message Slot 17 Data 0 CAN0 Message Slot 17 Data 1 13-98 (C0MSL17DT0) (C0MSL17DT1) 13-100 H'0080 1218 CAN0 Message Slot 17 Data 2 CAN0 Message Slot 17 Data 3 13-102 (C0MSL17DT2) (C0MSL17DT3) 13-104 H'0080 121A CAN0 Message Slot 17 Data 4 CAN0 Message Slot 17 Data 5 13-106 (C0MSL17DT4) (C0MSL17DT5) 13-108 H'0080 121C CAN0 Message Slot 17 Data 6 CAN0 Message Slot 17 Data 7 13-110 (C0MSL17DT6) (C0MSL17DT7) 13-112 H'0080 121E CAN0 Message Slot 17 Timestamp 13-114 (C0MSL17TSP) H'0080 1220 CAN0 Message Slot 18 Standard ID0 CAN0 Message Slot 18 Standard ID1 13-86 (C0MSL18SID0) (C0MSL18SID1) 13-88 H'0080 1222 CAN0 Message Slot 18 Extended ID0 CAN0 Message Slot 18 Extended ID1 13-90 (C0MSL18EID0) (C0MSL18EID1) 13-92 H'0080 1224 CAN0 Message Slot 18 Extended ID2 CAN0 Message Slot 18 Data Length Register 13-94 (C0MSL18EID2) (C0MSL18DLC) 13-96 H'0080 1226 CAN0 Message Slot 18 Data 0 CAN0 Message Slot 18 Data 1 13-98 (C0MSL18DT0) (C0MSL18DT1) 13-100 H'0080 1228 CAN0 Message Slot 18 Data 2 CAN0 Message Slot 18 Data 3 13-102 (C0MSL18DT2) (C0MSL18DT3) 13-104 H'0080 122A CAN0 Message Slot 18 Data 4 CAN0 Message Slot 18 Data 5 13-106 (C0MSL18DT4) (C0MSL18DT5) 13-108 H'0080 122C CAN0 Message Slot 18 Data 6 CAN0 Message Slot 18 Data 7 13-110 (C0MSL18DT6) (C0MSL18DT7) 13-112 H'0080 122E CAN0 Message Slot 18 Timestamp 13-114 (C0MSL18TSP) H'0080 1230 CAN0 Message Slot 19 Standard ID0 CAN0 Message Slot 19 Standard ID1 13-86 (C0MSL19SID0) (C0MSL19SID1) 13-88

3-3332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (24/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1232 CAN0 Message Slot 19 Extended ID0 CAN0 Message Slot 19 Extended ID1 13-90 (C0MSL19EID0) (C0MSL19EID1) 13-92 H'0080 1234 CAN0 Message Slot 19 Extended ID2 CAN0 Message Slot 19 Data Length Register 13-94 (C0MSL19EID2) (C0MSL19DLC) 13-96 H'0080 1236 CAN0 Message Slot 19 Data 0 CAN0 Message Slot 19 Data 1 13-98 (C0MSL19DT0) (C0MSL19DT1) 13-100 H'0080 1238 CAN0 Message Slot 19 Data 2 CAN0 Message Slot 19 Data 3 13-102 (C0MSL19DT2) (C0MSL19DT3) 13-104 H'0080 123A CAN0 Message Slot 19 Data 4 CAN0 Message Slot 19 Data 5 13-106 (C0MSL19DT4) (C0MSL19DT5) 13-108 H'0080 123C CAN0 Message Slot 19 Data 6 CAN0 Message Slot 19 Data 7 13-110 (C0MSL19DT6) (C0MSL19DT7) 13-112 H'0080 123E CAN0 Message Slot 19 Timestamp 13-114 (C0MSL19TSP) H'0080 1240 CAN0 Message Slot 20 Standard ID0 CAN0 Message Slot 20 Standard ID1 13-86 (C0MSL20SID0) (C0MSL20SID1) 13-88 H'0080 1242 CAN0 Message Slot 20 Extended ID0 CAN0 Message Slot 20 Extended ID1 13-90 (C0MSL20EID0) (C0MSL20EID1) 13-92 H'0080 1244 CAN0 Message Slot 20 Extended ID2 CAN0 Message Slot 20 Data Length Register 13-94 (C0MSL20EID2) (C0MSL20DLC) 13-96 H'0080 1246 CAN0 Message Slot 20 Data 0 CAN0 Message Slot 20 Data 1 13-98 (C0MSL20DT0) (C0MSL20DT1) 13-100 H'0080 1248 CAN0 Message Slot 20 Data 2 CAN0 Message Slot 20 Data 3 13-102 (C0MSL20DT2) (C0MSL20DT3) 13-104 H'0080 124A CAN0 Message Slot 20 Data 4 CAN0 Message Slot 20 Data 5 13-106 (C0MSL20DT4) (C0MSL20DT5) 13-108 H'0080 124C CAN0 Message Slot 20 Data 6 CAN0 Message Slot 20 Data 7 13-110 (C0MSL20DT6) (C0MSL20DT7) 13-112 H'0080 124E CAN0 Message Slot 20 Timestamp 13-114 (C0MSL20TSP) H'0080 1250 CAN0 Message Slot 21 Standard ID0 CAN0 Message Slot 21 Standard ID1 13-86 (C0MSL21SID0) (C0MSL21SID1) 13-88 H'0080 1252 CAN0 Message Slot 21 Extended ID0 CAN0 Message Slot 21 Extended ID1 13-90 (C0MSL21EID0) (C0MSL21EID1) 13-92 H'0080 1254 CAN0 Message Slot 21 Extended ID2 CAN0 Message Slot 21 Data Length Register 13-94 (C0MSL21EID2) (C0MSL21DLC) 13-96 H'0080 1256 CAN0 Message Slot 21 Data 0 CAN0 Message Slot 21 Data 1 13-98 (C0MSL21DT0) (C0MSL21DT1) 13-100 H'0080 1258 CAN0 Message Slot 21 Data 2 CAN0 Message Slot 21 Data 3 13-102 (C0MSL21DT2) (C0MSL21DT3) 13-104 H'0080 125A CAN0 Message Slot 21 Data 4 CAN0 Message Slot 21 Data 5 13-106 (C0MSL21DT4) (C0MSL21DT5) 13-108 H'0080 125C CAN0 Message Slot 21 Data 6 CAN0 Message Slot 21 Data 7 13-110 (C0MSL21DT6) (C0MSL21DT7) 13-112 H'0080 125E CAN0 Message Slot 21 Timestamp 13-114 (C0MSL21TSP) H'0080 1260 CAN0 Message Slot 22 Standard ID0 CAN0 Message Slot 22 Standard ID1 13-86 (C0MSL22SID0) (C0MSL22SID1) 13-88 H'0080 1262 CAN0 Message Slot 22 Extended ID0 CAN0 Message Slot 22 Extended ID1 13-90 (C0MSL22EID0) (C0MSL22EID1) 13-92 H'0080 1264 CAN0 Message Slot 22 Extended ID2 CAN0 Message Slot 22 Data Length Register 13-94 (C0MSL22EID2) (C0MSL22DLC) 13-96 H'0080 1266 CAN0 Message Slot 22 Data 0 CAN0 Message Slot 22 Data 1 13-98 (C0MSL22DT0) (C0MSL22DT1) 13-100 H'0080 1268 CAN0 Message Slot 22 Data 2 CAN0 Message Slot 22 Data 3 13-102 (C0MSL22DT2) (C0MSL22DT3) 13-104 H'0080 126A CAN0 Message Slot 22 Data 4 CAN0 Message Slot 22 Data 5 13-106 (C0MSL22DT4) (C0MSL22DT5) 13-108 H'0080 126C CAN0 Message Slot 22 Data 6 CAN0 Message Slot 22 Data 7 13-110 (C0MSL22DT6) (C0MSL22DT7) 13-112 H'0080 126E CAN0 Message Slot 22 Timestamp 13-114 (C0MSL22TSP) H'0080 1270 CAN0 Message Slot 23 Standard ID0 CAN0 Message Slot 23 Standard ID1 13-86 (C0MSL23SID0) (C0MSL23SID1) 13-88 H'0080 1272 CAN0 Message Slot 23 Extended ID0 CAN0 Message Slot 23 Extended ID1 13-90 (C0MSL23EID0) (C0MSL23EID1) 13-92 H'0080 1274 CAN0 Message Slot 23 Extended ID2 CAN0 Message Slot 23 Data Length Register 13-94 (C0MSL23EID2) (C0MSL23DLC) 13-96 H'0080 1276 CAN0 Message Slot 23 Data 0 CAN0 Message Slot 23 Data 1 13-98 (C0MSL23DT0) (C0MSL23DT1) 13-100

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (25/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1280 CAN0 Message Slot 24 Standard ID0 CAN0 Message Slot 24 Standard ID1 13-86 (C0MSL24SID0) (C0MSL24SID1) 13-88 H'0080 1282 CAN0 Message Slot 24 Extended ID0 CAN0 Message Slot 24 Extended ID1 13-90 (C0MSL24EID0) (C0MSL24EID1) 13-92 H'0080 1284 CAN0 Message Slot 24 Extended ID2 CAN0 Message Slot 24 Data Length Register 13-94 (C0MSL24EID2) (C0MSL24DLC) 13-96 H'0080 1286 CAN0 Message Slot 24 Data 0 CAN0 Message Slot 24 Data 1 13-98 (C0MSL24DT0) (C0MSL24DT1) 13-100 H'0080 1288 CAN0 Message Slot 24 Data 2 CAN0 Message Slot 24 Data 3 13-102 (C0MSL24DT2) (C0MSL24DT3) 13-104 H'0080 128A CAN0 Message Slot 24 Data 4 CAN0 Message Slot 24 Data 5 13-106 (C0MSL24DT4) (C0MSL24DT5) 13-108 H'0080 128C CAN0 Message Slot 24 Data 6 CAN0 Message Slot 24 Data 7 13-110 (C0MSL24DT6) (C0MSL24DT7) 13-112 H'0080 128E CAN0 Message Slot 24 Timestamp 13-114 (C0MSL24TSP) H'0080 1290 CAN0 Message Slot 25 Standard ID0 CAN0 Message Slot 25 Standard ID1 13-86 (C0MSL25SID0) (C0MSL25SID1) 13-88 H'0080 1292 CAN0 Message Slot 25 Extended ID0 CAN0 Message Slot 25 Extended ID1 13-90 (C0MSL25EID0) (C0MSL25EID1) 13-92 H'0080 1294 CAN0 Message Slot 25 Extended ID2 CAN0 Message Slot 25 Data Length Register 13-94 (C0MSL25EID2) (C0MSL25DLC) 13-96 H'0080 1296 CAN0 Message Slot 25 Data 0 CAN0 Message Slot 25 Data 1 13-98 (C0MSL25DT0) (C0MSL25DT1) 13-100 H'0080 1298 CAN0 Message Slot 25 Data 2 CAN0 Message Slot 25 Data 3 13-102 (C0MSL25DT2) (C0MSL25DT3) 13-104 H'0080 129A CAN0 Message Slot 25 Data 4 CAN0 Message Slot 25 Data 5 13-106 (C0MSL25DT4) (C0MSL25DT5) 13-108 H'0080 129C CAN0 Message Slot 25 Data 6 CAN0 Message Slot 25 Data 7 13-110 (C0MSL25DT6) (C0MSL25DT7) 13-112 H'0080 129E CAN0 Message Slot 25 Timestamp 13-114 (C0MSL25TSP) H'0080 12A0 CAN0 Message Slot 26 Standard ID0 CAN0 Message Slot 26 Standard ID1 13-86 (C0MSL26SID0) (C0MSL26SID1) 13-88 H'0080 12A2 CAN0 Message Slot 26 Extended ID0 CAN0 Message Slot 26 Extended ID1 13-90 (C0MSL26EID0) (C0MSL26EID1) 13-92 H'0080 12A4 CAN0 Message Slot 26 Extended ID2 CAN0 Message Slot 26 Data Length Register 13-94 (C0MSL26EID2) (C0MSL26DLC) 13-96 H'0080 12A6 CAN0 Message Slot 26 Data 0 CAN0 Message Slot 26 Data 1 13-98 (C0MSL26DT0) (C0MSL26DT1) 13-100 H'0080 12A8 CAN0 Message Slot 26 Data 2 CAN0 Message Slot 26 Data 3 13-102 (C0MSL26DT2) (C0MSL26DT3) 13-104 H'0080 12AA CAN0 Message Slot 26 Data 4 CAN0 Message Slot 26 Data 5 13-106 (C0MSL26DT4) (C0MSL26DT5) 13-108 H'0080 12AC CAN0 Message Slot 26 Data 6 CAN0 Message Slot 26 Data 7 13-110 (C0MSL26DT6) (C0MSL26DT7) 13-112 H'0080 12AE CAN0 Message Slot 26 Timestamp 13-114 (C0MSL26TSP) H'0080 12B0 CAN0 Message Slot 27 Standard ID0 CAN0 Message Slot 27 Standard ID1 13-86 (C0MSL27SID0) (C0MSL27SID1) 13-88 H'0080 12B2 CAN0 Message Slot 27 Extended ID0 CAN0 Message Slot 27 Extended ID1 13-90 (C0MSL27EID0) (C0MSL27EID1) 13-92 H'0080 12B4 CAN0 Message Slot 27 Extended ID2 CAN0 Message Slot 27 Data Length Register 13-94 (C0MSL27EID2) (C0MSL27DLC) 13-96 H'0080 12B6 CAN0 Message Slot 27 Data 0 CAN0 Message Slot 27 Data 1 13-98 (C0MSL27DT0) (C0MSL27DT1) 13-100 H'0080 12B8 CAN0 Message Slot 27 Data 2 CAN0 Message Slot 27 Data 3 13-102 (C0MSL27DT2) (C0MSL27DT3) 13-104 H'0080 12BA CAN0 Message Slot 27 Data 4 CAN0 Message Slot 27 Data 5 13-106 (C0MSL27DT4) (C0MSL27DT5) 13-108 H'0080 12BC CAN0 Message Slot 27 Data 6 CAN0 Message Slot 27 Data 7 13-110 (C0MSL27DT6) (C0MSL27DT7) 13-112 H'0080 1278 CAN0 Message Slot 23 Data 2 CAN0 Message Slot 23 Data 3 13-102 (C0MSL23DT2) (C0MSL23DT3) 13-104 H'0080 127A CAN0 Message Slot 23 Data 4 CAN0 Message Slot 23 Data 5 13-106 (C0MSL23DT4) (C0MSL23DT5) 13-108 H'0080 127C CAN0 Message Slot 23 Data 6 CAN0 Message Slot 23 Data 7 13-110 (C0MSL23DT6) (C0MSL23DT7) 13-112 H'0080 127E CAN0 Message Slot 23 Timestamp 13-114 (C0MSL23TSP)

3-3532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (26/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 12BE CAN0 Message Slot 27 Timestamp 13-114 (C0MSL27TSP) H'0080 12C0 CAN0 Message Slot 28 Standard ID0 CAN0 Message Slot 28 Standard ID1 13-86 (C0MSL28SID0) (C0MSL28SID1) 13-88 H'0080 12C2 CAN0 Message Slot 28 Extended ID0 CAN0 Message Slot 28 Extended ID1 13-90 (C0MSL28EID0) (C0MSL28EID1) 13-92 H'0080 12C4 CAN0 Message Slot 28 Extended ID2 CAN0 Message Slot 28 Data Length Register 13-94 (C0MSL28EID2) (C0MSL28DLC) 13-96 H'0080 12C6 CAN0 Message Slot 28 Data 0 CAN0 Message Slot 28 Data 1 13-98 (C0MSL28DT0) (C0MSL28DT1) 13-100 H'0080 12C8 CAN0 Message Slot 28 Data 2 CAN0 Message Slot 28 Data 3 13-102 (C0MSL28DT2) (C0MSL28DT3) 13-104 H'0080 12CA CAN0 Message Slot 28 Data 4 CAN0 Message Slot 28 Data 5 13-106 (C0MSL28DT4) (C0MSL28DT5) 13-108 H'0080 12CC CAN0 Message Slot 28 Data 6 CAN0 Message Slot 28 Data 7 13-110 (C0MSL28DT6) (C0MSL28DT7) 13-112 H'0080 12CE CAN0 Message Slot 28 Timestamp 13-114 (C0MSL28TSP) H'0080 12D0 CAN0 Message Slot 29 Standard ID0 CAN0 Message Slot 29 Standard ID1 13-86 (C0MSL29SID0) (C0MSL29SID1) 13-88 H'0080 12D2 CAN0 Message Slot 29 Extended ID0 CAN0 Message Slot 29 Extended ID1 13-90 (C0MSL29EID0) (C0MSL29EID1) 13-92 H'0080 12D4 CAN0 Message Slot 29 Extended ID2 CAN0 Message Slot 29 Data Length Register 13-94 (C0MSL29EID2) (C0MSL29DLC) 13-96 H'0080 12D6 CAN0 Message Slot 29 Data 0 CAN0 Message Slot 29 Data 1 13-98 (C0MSL29DT0) (C0MSL29DT1) 13-100 H'0080 12D8 CAN0 Message Slot 29 Data 2 CAN0 Message Slot 29 Data 3 13-102 (C0MSL29DT2) (C0MSL29DT3) 13-104 H'0080 12DA CAN0 Message Slot 29 Data 4 CAN0 Message Slot 29 Data 5 13-106 (C0MSL29DT4) (C0MSL29DT5) 13-108 H'0080 12DC CAN0 Message Slot 29 Data 6 CAN0 Message Slot 29 Data 7 13-110 (C0MSL29DT6) (C0MSL29DT7) 13-112 H'0080 12DE CAN0 Message Slot 29 Timestamp 13-114 (C0MSL29TSP) H'0080 12E0 CAN0 Message Slot 30 Standard ID0 CAN0 Message Slot 30 Standard ID1 13-86 (C0MSL30SID0) (C0MSL30SID1) 13-88 H'0080 12E2 CAN0 Message Slot 30 Extended ID0 CAN0 Message Slot 30 Extended ID1 13-90 (C0MSL30EID0) (C0MSL30EID1) 13-92 H'0080 12E4 CAN0 Message Slot 30 Extended ID2 CAN0 Message Slot 30 Data Length Register 13-94 (C0MSL30EID2) (C0MSL30DLC) 13-96 H'0080 12E6 CAN0 Message Slot 30 Data 0 CAN0 Message Slot 30 Data 1 13-98 (C0MSL30DT0) (C0MSL30DT1) 13-100 H'0080 12E8 CAN0 Message Slot 30 Data 2 CAN0 Message Slot 30 Data 3 13-102 (C0MSL30DT2) (C0MSL30DT3) 13-104 H'0080 12EA CAN0 Message Slot 30 Data 4 CAN0 Message Slot 30 Data 5 13-106 (C0MSL30DT4) (C0MSL30DT5) 13-108 H'0080 12EC CAN0 Message Slot 30 Data 6 CAN0 Message Slot 30 Data 7 13-110 (C0MSL30DT6) (C0MSL30DT7) 13-112 H'0080 12EE CAN0 Message Slot 30 Timestamp 13-114 (C0MSL30TSP) H'0080 12F0 CAN0 Message Slot 31 Standard ID0 CAN0 Message Slot 31 Standard ID1 13-86 (C0MSL31SID0) (C0MSL31SID1) 13-88 H'0080 12F2 CAN0 Message Slot 31 Extended ID0 CAN0 Message Slot 31 Extended ID1 13-90 (C0MSL31EID0) (C0MSL31EID1) 13-92 H'0080 12F4 CAN0 Message Slot 31 Extended ID2 CAN0 Message Slot 31 Data Length Register 13-94 (C0MSL31EID2) (C0MSL31DLC) 13-96 H'0080 12F6 CAN0 Message Slot 31 Data 0 CAN0 Message Slot 31 Data 1 13-98 (C0MSL31DT0) (C0MSL31DT1) 13-100 H'0080 12F8 CAN0 Message Slot 31 Data 2 CAN0 Message Slot 31 Data 3 13-102 (C0MSL31DT2) (C0MSL31DT3) 13-104 H'0080 12FA CAN0 Message Slot 31 Data 4 CAN0 Message Slot 31 Data 5 13-106 (C0MSL31DT4) (C0MSL31DT5) 13-108 H'0080 12FC CAN0 Message Slot 31 Data 6 CAN0 Message Slot 31 Data 7 13-110 (C0MSL31DT6) (C0MSL31DT7) 13-112 H'0080 12FE CAN0 Message Slot 31 Timestamp 13-114 (C0MSL31TSP) (Use inhibited area)|

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (27/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1400 CAN1 Control Register 13-26 (CAN1CNT) H'0080 1402 CAN1 Status Register 13-29 (CAN1STAT) H'0080 1404 (Use inhibited area) H'0080 1406 CAN1 Configuration Register 13-32 (CAN1CONF) H'0080 1408 CAN1 Timestamp Count Register 13-35 (CAN1TSTMP) H'0080 140A CAN1 Receive Error Count Register CAN1 Transmit Error Count Register 13-36 (CAN1REC) (CAN1TEC) H'0080 140C CAN1 Slot Interrupt Request Status Register (Upper) 13-40 (CAN1SLISTW) (CAN1SLIST) H'0080 140E (Lower) (CAN1SLISTL) H'0080 1410 CAN1 Slot Interrupt Request Mask Register (Upper) 13-42 (CAN1SLIMKW) (CAN1SLIMK) H'0080 1412 (Lower) (CAN1SLIMKL) H'0080 1414 CAN1 Error Interrupt Request Status Register CAN1 Error Interrupt Request Mask Register 13-43 (CAN1ERIST) (CAN1ERIMK) 13-44 H'0080 1416 CAN1 Baud Rate Prescaler CAN1 Cause of Error Register 13-37 (CAN1BRP) (CAN1EF) 13-67 H'0080 1418 CAN1 Mode Register CAN1 DMA Transfer Request Select Register 13-69 (CAN1MOD) (CAN1DMARQ) 13-70 H'0080 141A CAN1 Message Slot Number Register CAN1 Clock Select Register 13-71 (CAN1MSN) (CAN1CKSEL) 13-72 H'0080 141C CAN1 Frame Format Select Register (Upper) 13-74 (CAN1FFSW) (CAN1FFS) H'0080 141E (Lower) (CAN1FFSL) H'0080 1420 CAN1 Global Mask Register A Standard ID0 CAN1 Global Mask Register A Standard ID1 13-76 (C1GMSKAS0) (C1GMSKAS1) H'0080 1422 CAN1 Global Mask Register A Extended ID0 CAN1 Global Mask Register A Extended ID1 13-77 (C1GMSKAE0) (C1GMSKAE1) H'0080 1424 CAN1 Global Mask Register A Extended ID2 (Use inhibited area) 13-78 (C1GMSKAE2) H'0080 1426 (Use inhibited area) H'0080 1428 CAN1 Global Mask Register B Standard ID0 CAN1 Global Mask Register B Standard ID1 13-76 (C1GMSKBS0) (C1GMSKBS1) H'0080 142A CAN1 Global Mask Register B Extended ID0 CAN1 Global Mask Register B Extended ID1 13-77 (C1GMSKBE0) (C1GMSKBE1) H'0080 142C CAN1 Global Mask Register B Extended ID2 (Use inhibited area) 13-78 (C1GMSKBE2) H'0080 142E (Use inhibited area) H'0080 1430 CAN1 Local Mask Register A Standard ID0 CAN1 Local Mask Register A Standard ID1 13-76 (C1LMSKAS0) (C1LMSKAS1) H'0080 1432 CAN1 Local Mask Register A Extended ID0 CAN1 Local Mask Register A Extended ID1 13-77 (C1LMSKAE0) (C1LMSKAE1) H'0080 1434 CAN1 Local Mask Register A Extended ID2 (Use inhibited area) 13-78 (C1LMSKAE2) H'0080 1436 (Use inhibited area) H'0080 1438 CAN1 Local Mask Register B Standard ID0 CAN1 Local Mask Register B Standard ID1 13-76 (C1LMSKBS0) (C1LMSKBS1) H'0080 143A CAN1 Local Mask Register B Extended ID0 CAN1 Local Mask Register B Extended ID1 13-77 (C1LMSKBE0) (C1LMSKBE1) H'0080 143C CAN1 Local Mask Register B Extended ID2 (Use inhibited area) 13-78 (C1LMSKBE2) H'0080 143E (Use inhibited area) H'0080 1440 CAN1 Single-Shot Mode Control Register (Upper) 13-80 (CAN1SSMODEW) (CAN1SSMODE) H'0080 1442 (Lower) (CAN1SSMODEL)

3-3732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (28/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1444 CAN1 Single-Shot Interrupt Request Status Register (Upper) 13-45 (CAN1SSISTW) (CAN1SSIST) H'0080 1446 (Lower) (CAN1SSISTL) H'0080 1448 CAN1 Single-Shot Interrupt Request Mask Register (Upper) 13-47 (CAN1SSIMKW) (CAN1SSIMK) H'0080 144A (Lower) (CAN1SSIMKL) (Use inhibited area) H'0080 1450 CAN1 Message Slot 0 Control Register CAN1 Message Slot 1 Control Register 13-82 (C1MSL0CNT) (C1MSL1CNT) H'0080 1452 CAN1 Message Slot 2 Control Register CAN1 Message Slot 3 Control Register 13-82 (C1MSL2CNT) (C1MSL3CNT) H'0080 1454 CAN1 Message Slot 4 Control Register CAN1 Message Slot 5 Control Register 13-82 (C1MSL4CNT) (C1MSL5CNT) H'0080 1456 CAN1 Message Slot 6 Control Register CAN1 Message Slot 7 Control Register 13-82 (C1MSL6CNT) (C1MSL7CNT) H'0080 1458 CAN1 Message Slot 8 Control Register CAN1 Message Slot 9 Control Register 13-82 (C1MSL8CNT) (C1MSL9CNT) H'0080 145A CAN1 Message Slot 10 Control Register CAN1 Message Slot 11 Control Register 13-82 (C1MSL10CNT) (C1MSL11CNT) H'0080 145C CAN1 Message Slot 12 Control Register CAN1 Message Slot 13 Control Register 13-82 (C1MSL12CNT) (C1MSL13CNT) H'0080 145E CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register 13-82 (C1MSL14CNT) (C1MSL15CNT) H'0080 1460 CAN1 Message Slot 16 Control Register CAN1 Message Slot 17 Control Register 13-83 (C1MSL16CNT) (C1MSL17CNT) H'0080 1462 CAN1 Message Slot 18 Control Register CAN1 Message Slot 19 Control Register 13-83 (C1MSL18CNT) (C1MSL19CNT) H'0080 1464 CAN1 Message Slot 20 Control Register CAN1 Message Slot 21 Control Register 13-83 (C1MSL20CNT) (C1MSL21CNT) H'0080 1466 CAN1 Message Slot 22 Control Register CAN1 Message Slot 23 Control Register 13-83 (C1MSL22CNT) (C1MSL23CNT) H'0080 1468 CAN1 Message Slot 24 Control Register CAN1 Message Slot 25 Control Register 13-83 (C1MSL24CNT) (C1MSL25CNT) H'0080 146A CAN1 Message Slot 26 Control Register CAN1 Message Slot 27 Control Register 13-83 (C1MSL26CNT) (C1MSL27CNT) H'0080 146C CAN1 Message Slot 28 Control Register CAN1 Message Slot 29 Control Register 13-83 (C1MSL28CNT) (C1MSL29CNT) H'0080 146E CAN1 Message Slot 30 Control Register CAN1 Message Slot 31 Control Register 13-83 (C1MSL30CNT) (C1MSL31CNT) (Use inhibited area) H'0080 1500 CAN1 Message Slot 0 Standard ID0 CAN1 Message Slot 0 Standard ID1 13-86 (C1MSL0SID0) (C1MSL0SID1) 13-88 H'0080 1502 CAN1 Message Slot 0 Extended ID0 CAN1 Message Slot 0 Extended ID1 13-90 (C1MSL0EID0) (C1MSL0EID1) 13-92 H'0080 1504 CAN1 Message Slot 0 Extended ID2 CAN1 Message Slot 0 Data Length Register 13-94 (C1MSL0EID2) (C1MSL0DLC) 13-96 H'0080 1506 CAN1 Message Slot 0 Data 0 CAN1 Message Slot 0 Data 1 13-98 (C1MSL0DT0) (C1MSL0DT1) 13-100 H'0080 1508 CAN1 Message Slot 0 Data 2 CAN1 Message Slot 0 Data 3 13-102 (C1MSL0DT2) (C1MSL0DT3) 13-104 H'0080 150A CAN1 Message Slot 0 Data 4 CAN1 Message Slot 0 Data 5 13-106 (C1MSL0DT4) (C1MSL0DT5) 13-108 H'0080 150C CAN1 Message Slot 0 Data 6 CAN1 Message Slot 0 Data 7 13-110 (C1MSL0DT6) (C1MSL0DT7) 13-112 H'0080 150E CAN1 Message Slot 0 Timestamp 13-114 (C1MSL0TSP) H'0080 1510 CAN1 Message Slot 1 Standard ID0 CAN1 Message Slot 1 Standard ID1 13-86 (C1MSL1SID0) (C1MSL1SID1) 13-88 H'0080 1512 CAN1 Message Slot 1 Extended ID0 CAN1 Message Slot 1 Extended ID1 13-90 (C1MSL1EID0) (C1MSL1EID1) 13-92 H'0080 1514 CAN1 Message Slot 1 Extended ID2 CAN1 Message Slot 1 Data Length Register 13-94 (C1MSL1EID2) (C1MSL1DLC) 13-96 H'0080 1516 CAN1 Message Slot 1 Data 0 CAN1 Message Slot 1 Data 1 13-98 (C1MSL1DT0) (C1MSL1DT1) 13-100 H'0080 1518 CAN1 Message Slot 1 Data 2 CAN1 Message Slot 1 Data 3 13-102 (C1MSL1DT2) (C1MSL1DT3) 13-104

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (29/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 151A CAN1 Message Slot 1 Data 4 CAN1 Message Slot 1 Data 5 13-106 (C1MSL1DT4) (C1MSL1DT5) 13-108 H'0080 151C CAN1 Message Slot 1 Data 6 CAN1 Message Slot 1 Data 7 13-110 (C1MSL1DT6) (C1MSL1DT7) 13-112 H'0080 151E CAN1 Message Slot 1 Timestamp 13-114 (C1MSL1TSP) H'0080 1520 CAN1 Message Slot 2 Standard ID0 CAN1 Message Slot 2 Standard ID1 13-86 (C1MSL2SID0) (C1MSL2SID1) 13-88 H'0080 1522 CAN1 Message Slot 2 Extended ID0 CAN1 Message Slot 2 Extended ID1 13-90 (C1MSL2EID0) (C1MSL2EID1) 13-92 H'0080 1524 CAN1 Message Slot 2 Extended ID2 CAN1 Message Slot 2 Data Length Register 13-94 (C1MSL2EID2) (C1MSL2DLC) 13-96 H'0080 1526 CAN1 Message Slot 2 Data 0 CAN1 Message Slot 2 Data 1 13-98 (C1MSL2DT0) (C1MSL2DT1) 13-100 H'0080 1528 CAN1 Message Slot 2 Data 2 CAN1 Message Slot 2 Data 3 13-102 (C1MSL2DT2) (C1MSL2DT3) 13-104 H'0080 152A CAN1 Message Slot 2 Data 4 CAN1 Message Slot 2 Data 5 13-106 (C1MSL2DT4) (C1MSL2DT5) 13-108 H'0080 152C CAN1 Message Slot 2 Data 6 CAN1 Message Slot 2 Data 7 13-110 (C1MSL2DT6) (C1MSL2DT7) 13-112 H'0080 152E CAN1 Message Slot 2 Timestamp 13-114 (C1MSL2TSP) H'0080 1530 CAN1 Message Slot 3 Standard ID0 CAN1 Message Slot 3 Standard ID1 13-86 (C1MSL3SID0) (C1MSL3SID1) 13-88 H'0080 1532 CAN1 Message Slot 3 Extended ID0 CAN1 Message Slot 3 Extended ID1 13-90 (C1MSL3EID0) (C1MSL3EID1) 13-92 H'0080 1534 CAN1 Message Slot 3 Extended ID2 CAN1 Message Slot 3 Data Length Register 13-94 (C1MSL3EID2) (C1MSL3DLC) 13-96 H'0080 1536 CAN1 Message Slot 3 Data 0 CAN1 Message Slot 3 Data 1 13-98 (C1MSL3DT0) (C1MSL3DT1) 13-100 H'0080 1538 CAN1 Message Slot 3 Data 2 CAN1 Message Slot 3 Data 3 13-102 (C1MSL3DT2) (C1MSL3DT3) 13-104 H'0080 153A CAN1 Message Slot 3 Data 4 CAN1 Message Slot 3 Data 5 13-106 (C1MSL3DT4) (C1MSL3DT5) 13-108 H'0080 153C CAN1 Message Slot 3 Data 6 CAN1 Message Slot 3 Data 7 13-110 (C1MSL3DT6) (C1MSL3DT7) 13-112 H'0080 153E CAN1 Message Slot 3 Timestamp 13-114 (C1MSL3TSP) H'0080 1540 CAN1 Message Slot 4 Standard ID0 CAN1 Message Slot 4 Standard ID1 13-86 (C1MSL4SID0) (C1MSL4SID1) 13-88 H'0080 1542 CAN1 Message Slot 4 Extended ID0 CAN1 Message Slot 4 Extended ID1 13-90 (C1MSL4EID0) (C1MSL4EID1) 13-92 H'0080 1544 CAN1 Message Slot 4 Extended ID2 CAN1 Message Slot 4 Data Length Register 13-94 (C1MSL4EID2) (C1MSL4DLC) 13-96 H'0080 1546 CAN1 Message Slot 4 Data 0 CAN1 Message Slot 4 Data 1 13-98 (C1MSL4DT0) (C1MSL4DT1) 13-100 H'0080 1548 CAN1 Message Slot 4 Data 2 CAN1 Message Slot 4 Data 3 13-102 (C1MSL4DT2) (C1MSL4DT3) 13-104 H'0080 154A CAN1 Message Slot 4 Data 4 CAN1 Message Slot 4 Data 5 13-106 (C1MSL4DT4) (C1MSL4DT5) 13-108 H'0080 154C CAN1 Message Slot 4 Data 6 CAN1 Message Slot 4 Data 7 13-110 (C1MSL4DT6) (C1MSL4DT7) 13-112 H'0080 154E CAN1 Message Slot 4 Timestamp 13-114 (C1MSL4TSP) H'0080 1550 CAN1 Message Slot 5 Standard ID0 CAN1 Message Slot 5 Standard ID1 13-86 (C1MSL5SID0) (C1MSL5SID1) 13-88 H'0080 1552 CAN1 Message Slot 5 Extended ID0 CAN1 Message Slot 5 Extended ID1 13-90 (C1MSL5EID0) (C1MSL5EID1) 13-92 H'0080 1554 CAN1 Message Slot 5 Extended ID2 CAN1 Message Slot 5 Data Length Register 13-94 (C1MSL5EID2) (C1MSL5DLC) 13-96 H'0080 1556 CAN1 Message Slot 5 Data 0 CAN1 Message Slot 5 Data 1 13-98 (C1MSL5DT0) (C1MSL5DT1) 13-100 H'0080 1558 CAN1 Message Slot 5 Data 2 CAN1 Message Slot 5 Data 3 13-102 (C1MSL5DT2) (C1MSL5DT3) 13-104 H'0080 155A CAN1 Message Slot 5 Data 4 CAN1 Message Slot 5 Data 5 13-106 (C1MSL5DT4) (C1MSL5DT5) 13-108 H'0080 155C CAN1 Message Slot 5 Data 6 CAN1 Message Slot 5 Data 7 13-110 (C1MSL5DT6) (C1MSL5DT7) 13-112 H'0080 155E CAN1 Message Slot 5 Timestamp 13-114 (C1MSL5TSP)

3-3932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (30/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1560 CAN1 Message Slot 6 Standard ID0 CAN1 Message Slot 6 Standard ID1 13-86 (C1MSL6SID0) (C1MSL6SID1) 13-88 H'0080 1562 CAN1 Message Slot 6 Extended ID0 CAN1 Message Slot 6 Extended ID1 13-90 (C1MSL6EID0) (C1MSL6EID1) 13-92 H'0080 1564 CAN1 Message Slot 6 Extended ID2 CAN1 Message Slot 6 Data Length Register 13-94 (C1MSL6EID2) (C1MSL6DLC) 13-96 H'0080 1566 CAN1 Message Slot 6 Data 0 CAN1 Message Slot 6 Data 1 13-98 (C1MSL6DT0) (C1MSL6DT1) 13-100 H'0080 1568 CAN1 Message Slot 6 Data 2 CAN1 Message Slot 6 Data 3 13-102 (C1MSL6DT2) (C1MSL6DT3) 13-104 H'0080 156A CAN1 Message Slot 6 Data 4 CAN1 Message Slot 6 Data 5 13-106 (C1MSL6DT4) (C1MSL6DT5) 13-108 H'0080 156C CAN1 Message Slot 6 Data 6 CAN1 Message Slot 6 Data 7 13-110 (C1MSL6DT6) (C1MSL6DT7) 13-112 H'0080 156E CAN1 Message Slot 6 Timestamp 13-114 (C1MSL6TSP) H'0080 1570 CAN1 Message Slot 7 Standard ID0 CAN1 Message Slot 7 Standard ID1 13-86 (C1MSL7SID0) (C1MSL7SID1) 13-88 H'0080 1572 CAN1 Message Slot 7 Extended ID0 CAN1 Message Slot 7 Extended ID1 13-90 (C1MSL7EID0) (C1MSL7EID1) 13-92 H'0080 1574 CAN1 Message Slot 7 Extended ID2 CAN1 Message Slot 7 Data Length Register 13-94 (C1MSL7EID2) (C1MSL7DLC) 13-96 H'0080 1576 CAN1 Message Slot 7 Data 0 CAN1 Message Slot 7 Data 1 13-98 (C1MSL7DT0) (C1MSL7DT1) 13-100 H'0080 1578 CAN1 Message Slot 7 Data 2 CAN1 Message Slot 7 Data 3 13-102 (C1MSL7DT2) (C1MSL7DT3) 13-104 H'0080 157A CAN1 Message Slot 7 Data 4 CAN1 Message Slot 7 Data 5 13-106 (C1MSL7DT4) (C1MSL7DT5) 13-108 H'0080 157C CAN1 Message Slot 7 Data 6 CAN1 Message Slot 7 Data 7 13-110 (C1MSL7DT6) (C1MSL7DT7) 13-112 H'0080 157E CAN1 Message Slot 7 Timestamp 13-114 (C1MSL7TSP) H'0080 1580 CAN1 Message Slot 8 Standard ID0 CAN1 Message Slot 8 Standard ID1 13-86 (C1MSL8SID0) (C1MSL8SID1) 13-88 H'0080 1582 CAN1 Message Slot 8 Extended ID0 CAN1 Message Slot 8 Extended ID1 13-90 (C1MSL8EID0) (C1MSL8EID1) 13-92 H'0080 1584 CAN1 Message Slot 8 Extended ID2 CAN1 Message Slot 8 Data Length Register 13-94 (C1MSL8EID2) (C1MSL8DLC) 13-96 H'0080 1586 CAN1 Message Slot 8 Data 0 CAN1 Message Slot 8 Data 1 13-98 (C1MSL8DT0) (C1MSL8DT1) 13-100 H'0080 1588 CAN1 Message Slot 8 Data 2 CAN1 Message Slot 8 Data 3 13-102 (C1MSL8DT2) (C1MSL8DT3) 13-104 H'0080 158A CAN1 Message Slot 8 Data 4 CAN1 Message Slot 8 Data 5 13-106 (C1MSL8DT4) (C1MSL8DT5) 13-108 H'0080 158C CAN1 Message Slot 8 Data 6 CAN1 Message Slot 8 Data 7 13-110 (C1MSL8DT6) (C1MSL8DT7) 13-112 H'0080 158E CAN1 Message Slot 8 Timestamp 13-114 (C1MSL8TSP) H'0080 1590 CAN1 Message Slot 9 Standard ID0 CAN1 Message Slot 9 Standard ID1 13-86 (C1MSL9SID0) (C1MSL9SID1) 13-88 H'0080 1592 CAN1 Message Slot 9 Extended ID0 CAN1 Message Slot 9 Extended ID1 13-90 (C1MSL9EID0) (C1MSL9EID1) 13-92 H'0080 1594 CAN1 Message Slot 9 Extended ID2 CAN1 Message Slot 9 Data Length Register 13-94 (C1MSL9EID2) (C1MSL9DLC) 13-96 H'0080 1596 CAN1 Message Slot 9 Data 0 CAN1 Message Slot 9 Data 1 13-98 (C1MSL9DT0) (C1MSL9DT1) 13-100 H'0080 1598 CAN1 Message Slot 9 Data 2 CAN1 Message Slot 9 Data 3 13-102 (C1MSL9DT2) (C1MSL9DT3) 13-104 H'0080 159A CAN1 Message Slot 9 Data 4 CAN1 Message Slot 9 Data 5 13-106 (C1MSL9DT4) (C1MSL9DT5) 13-108 H'0080 159C CAN1 Message Slot 9 Data 6 CAN1 Message Slot 9 Data 7 13-110 (C1MSL9DT6) (C1MSL9DT7) 13-112 H'0080 159E CAN1 Message Slot 9 Timestamp 13-114 (C1MSL9TSP) H'0080 15A0 CAN1 Message Slot 10 Standard ID0 CAN1 Message Slot 10 Standard ID1 13-86 (C1MSL10SID0) (C1MSL10SID1) 13-88 H'0080 15A2 CAN1 Message Slot 10 Extended ID0 CAN1 Message Slot 10 Extended ID1 13-90 (C1MSL10EID0) (C1MSL10EID1) 13-92 H'0080 15A4 CAN1 Message Slot 10 Extended ID2 CAN1 Message Slot 10 Data Length Register 13-94 (C1MSL10EID2) (C1MSL10DLC) 13-96

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (31/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 15A6 CAN1 Message Slot 10 Data 0 CAN1 Message Slot 10 Data 1 13-98 (C1MSL10DT0) (C1MSL10DT1) 13-100 H'0080 15A8 CAN1 Message Slot 10 Data 2 CAN1 Message Slot 10 Data 3 13-102 (C1MSL10DT2) (C1MSL10DT3) 13-104 H'0080 15AA CAN1 Message Slot 10 Data 4 CAN1 Message Slot 10 Data 5 13-106 (C1MSL10DT4) (C1MSL10DT5) 13-108 H'0080 15AC CAN1 Message Slot 10 Data 6 CAN1 Message Slot 10 Data 7 13-110 (C1MSL10DT6) (C1MSL10DT7) 13-112 H'0080 15AE CAN1 Message Slot 10 Timestamp 13-114 (C1MSL10TSP) H'0080 15B0 CAN1 Message Slot 11 Standard ID0 CAN1 Message Slot 11 Standard ID1 13-86 (C1MSL11SID0) (C1MSL11SID1) 13-88 H'0080 15B2 CAN1 Message Slot 11 Extended ID0 CAN1 Message Slot 11 Extended ID1 13-90 (C1MSL11EID0) (C1MSL11EID1) 13-92 H'0080 15B4 CAN1 Message Slot 11 Extended ID2 CAN1 Message Slot 11 Data Length Register 13-94 (C1MSL11EID2) (C1MSL11DLC) 13-96 H'0080 15B6 CAN1 Message Slot 11 Data 0 CAN1 Message Slot 11 Data 1 13-98 (C1MSL11DT0) (C1MSL11DT1) 13-100 H'0080 15B8 CAN1 Message Slot 11 Data 2 CAN1 Message Slot 11 Data 3 13-102 (C1MSL11DT2) (C1MSL11DT3) 13-104 H'0080 15BA CAN1 Message Slot 11 Data 4 CAN1 Message Slot 11 Data 5 13-106 (C1MSL11DT4) (C1MSL11DT5) 13-108 H'0080 15BC CAN1 Message Slot 11 Data 6 CAN1 Message Slot 11 Data 7 13-110 (C1MSL11DT6) (C1MSL11DT7) 13-112 H'0080 15BE CAN1 Message Slot 11 Timestamp 13-114 (C1MSL11TSP) H'0080 15C0 CAN1 Message Slot 12 Standard ID0 CAN1 Message Slot 12 Standard ID1 13-86 (C1MSL12SID0) (C1MSL12SID1) 13-88 H'0080 15C2 CAN1 Message Slot 12 Extended ID0 CAN1 Message Slot 12 Extended ID1 13-90 (C1MSL12EID0) (C1MSL12EID1) 13-92 H'0080 15C4 CAN1 Message Slot 12 Extended ID2 CAN1 Message Slot 12 Data Length Register 13-94 (C1MSL12EID2) (C1MSL12DLC) 13-96 H'0080 15C6 CAN1 Message Slot 12 Data 0 CAN1 Message Slot 12 Data 1 13-98 (C1MSL12DT0) (C1MSL12DT1) 13-100 H'0080 15C8 CAN1 Message Slot 12 Data 2 CAN1 Message Slot 12 Data 3 13-102 (C1MSL12DT2) (C1MSL12DT3) 13-104 H'0080 15CA CAN1 Message Slot 12 Data 4 CAN1 Message Slot 12 Data 5 13-106 (C1MSL12DT4) (C1MSL12DT5) 13-108 H'0080 15CC CAN1 Message Slot 12 Data 6 CAN1 Message Slot 12 Data 7 13-110 (C1MSL12DT6) (C1MSL12DT7) 13-112 H'0080 15CE CAN1 Message Slot 12 Timestamp 13-114 (C1MSL12TSP) H'0080 15D0 CAN1 Message Slot 13 Standard ID0 CAN1 Message Slot 13 Standard ID1 13-86 (C1MSL13SID0) (C1MSL13SID1) 13-88 H'0080 15D2 CAN1 Message Slot 13 Extended ID0 CAN1 Message Slot 13 Extended ID1 13-90 (C1MSL13EID0) (C1MSL13EID1) 13-92 H'0080 15D4 CAN1 Message Slot 13 Extended ID2 CAN1 Message Slot 13 Data Length Register 13-94 (C1MSL13EID2) (C1MSL13DLC) 13-96 H'0080 15D6 CAN1 Message Slot 13 Data 0 CAN1 Message Slot 13 Data 1 13-98 (C1MSL13DT0) (C1MSL13DT1) 13-100 H'0080 15D8 CAN1 Message Slot 13 Data 2 CAN1 Message Slot 13 Data 3 13-102 (C1MSL13DT2) (C1MSL13DT3) 13-104 H'0080 15DA CAN1 Message Slot 13 Data 4 CAN1 Message Slot 13 Data 5 13-106 (C1MSL13DT4) (C1MSL13DT5) 13-108 H'0080 15DC CAN1 Message Slot 13 Data 6 CAN1 Message Slot 13 Data 7 13-110 (C1MSL13DT6) (C1MSL13DT7) 13-112 H'0080 15DE CAN1 Message Slot 13 Timestamp 13-114 (C1MSL13TSP) H'0080 15E0 CAN1 Message Slot 14 Standard ID0 CAN1 Message Slot 14 Standard ID1 13-86 (C1MSL14SID0) (C1MSL14SID1) 13-88 H'0080 15E2 CAN1 Message Slot 14 Extended ID0 CAN1 Message Slot 14 Extended ID1 13-90 (C1MSL14EID0) (C1MSL14EID1) 13-92 H'0080 15E4 CAN1 Message Slot 14 Extended ID2 CAN1 Message Slot 14 Data Length Register 13-94 (C1MSL14EID2) (C1MSL14DLC) 13-96 H'0080 15E6 CAN1 Message Slot 14 Data 0 CAN1 Message Slot 14 Data 1 13-98 (C1MSL14DT0) (C1MSL14DT1) 13-100 H'0080 15E8 CAN1 Message Slot 14 Data 2 CAN1 Message Slot 14 Data 3 13-102 (C1MSL14DT2) (C1MSL14DT3) 13-104 H'0080 15EA CAN1 Message Slot 14 Data 4 CAN1 Message Slot 14 Data 5 13-106 (C1MSL14DT4) (C1MSL14DT5) 13-108

3-4132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (32/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 15EC CAN1 Message Slot 14 Data 6 CAN1 Message Slot 14 Data 7 13-110 (C1MSL14DT6) (C1MSL14DT7) 13-112 H'0080 15EE CAN1 Message Slot 14 Timestamp 13-114 (C1MSL14TSP) H'0080 15F0 CAN1 Message Slot 15 Standard ID0 CAN1 Message Slot 15 Standard ID1 13-86 (C1MSL15SID0) (C1MSL15SID1) 13-88 H'0080 15F2 CAN1 Message Slot 15 Extended ID0 CAN1 Message Slot 15 Extended ID1 13-90 (C1MSL15EID0) (C1MSL15EID1) 13-92 H'0080 15F4 CAN1 Message Slot 15 Extended ID2 CAN1 Message Slot 15 Data Length Register 13-94 (C1MSL15EID2) (C1MSL15DLC) 13-96 H'0080 15F6 CAN1 Message Slot 15 Data 0 CAN1 Message Slot 15 Data 1 13-98 (C1MSL15DT0) (C1MSL15DT1) 13-100 H'0080 15F8 CAN1 Message Slot 15 Data 2 CAN1 Message Slot 15 Data 3 13-102 (C1MSL15DT2) (C1MSL15DT3) 13-104 H'0080 15FA CAN1 Message Slot 15 Data 4 CAN1 Message Slot 15 Data 5 13-106 (C1MSL15DT4) (C1MSL15DT5) 13-108 H'0080 15FC CAN1 Message Slot 15 Data 6 CAN1 Message Slot 15 Data 7 13-110 (C1MSL15DT6) (C1MSL15DT7) 13-112 H'0080 15FE CAN1 Message Slot 15 Timestamp 13-114 (C1MSL15TSP) H'0080 1600 CAN1 Message Slot 16 Standard ID0 CAN1 Message Slot 16 Standard ID1 13-87 (C1MSL16SID0) (C1MSL16SID1) 13-89 H'0080 1602 CAN1 Message Slot 16 Extended ID0 CAN1 Message Slot 16 Extended ID1 13-91 (C1MSL16EID0) (C1MSL16EID1) 13-93 H'0080 1604 CAN1 Message Slot 16 Extended ID2 CAN1 Message Slot 16 Data Length Register 13-95 (C1MSL16EID2) (C1MSL16DLC) 13-97 H'0080 1606 CAN1 Message Slot 16 Data 0 CAN1 Message Slot 16 Data 1 13-99 (C1MSL16DT0) (C1MSL16DT1) 13-101 H'0080 1608 CAN1 Message Slot 16 Data 2 CAN1 Message Slot 16 Data 3 13-103 (C1MSL16DT2) (C1MSL16DT3) 13-105 H'0080 160A CAN1 Message Slot 16 Data 4 CAN1 Message Slot 16 Data 5 13-107 (C1MSL16DT4) (C1MSL16DT5) 13-109 H'0080 160C CAN1 Message Slot 16 Data 6 CAN1 Message Slot 16 Data 7 13-111 (C1MSL16DT6) (C1MSL16DT7) 13-113 H'0080 160E CAN1 Message Slot 16 Timestamp 13-115 (C1MSL16TSP) H'0080 1610 CAN1 Message Slot 17 Standard ID0 CAN1 Message Slot 17 Standard ID1 13-87 (C1MSL17SID0) (C1MSL17SID1) 13-89 H'0080 1612 CAN1 Message Slot 17 Extended ID0 CAN1 Message Slot 17 Extended ID1 13-91 (C1MSL17EID0) (C1MSL17EID1) 13-93 H'0080 1614 CAN1 Message Slot 17 Extended ID2 CAN1 Message Slot 17 Data Length Register 13-95 (C1MSL17EID2) (C1MSL17DLC) 13-97 H'0080 1616 CAN1 Message Slot 17 Data 0 CAN1 Message Slot 17 Data 1 13-99 (C1MSL17DT0) (C1MSL17DT1) 13-101 H'0080 1618 CAN1 Message Slot 17 Data 2 CAN1 Message Slot 17 Data 3 13-103 (C1MSL17DT2) (C1MSL17DT3) 13-105 H'0080 161A CAN1 Message Slot 17 Data 4 CAN1 Message Slot 17 Data 5 13-107 (C1MSL17DT4) (C1MSL17DT5) 13-109 H'0080 161C CAN1 Message Slot 17 Data 6 CAN1 Message Slot 17 Data 7 13-111 (C1MSL17DT6) (C1MSL17DT7) 13-113 H'0080 161E CAN1 Message Slot 17 Timestamp 13-115 (C1MSL17TSP) H'0080 1620 CAN1 Message Slot 18 Standard ID0 CAN1 Message Slot 18 Standard ID1 13-87 (C1MSL18SID0) (C1MSL18SID1) 13-89 H'0080 1622 CAN1 Message Slot 18 Extended ID0 CAN1 Message Slot 18 Extended ID1 13-91 (C1MSL18EID0) (C1MSL18EID1) 13-93 H'0080 1624 CAN1 Message Slot 18 Extended ID2 CAN1 Message Slot 18 Data Length Register 13-95 (C1MSL18EID2) (C1MSL18DLC) 13-97 H'0080 1626 CAN1 Message Slot 18 Data 0 CAN1 Message Slot 18 Data 1 13-99 (C1MSL18DT0) (C1MSL18DT1) 13-101 H'0080 1628 CAN1 Message Slot 18 Data 2 CAN1 Message Slot 18 Data 3 13-103 (C1MSL18DT2) (C1MSL18DT3) 13-105 H'0080 162A CAN1 Message Slot 18 Data 4 CAN1 Message Slot 18 Data 5 13-107 (C1MSL18DT4) (C1MSL18DT5) 13-109 H'0080 162C CAN1 Message Slot 18 Data 6 CAN1 Message Slot 18 Data 7 13-111 (C1MSL18DT6) (C1MSL18DT7) 13-113 H'0080 162E CAN1 Message Slot 18 Timestamp 13-115 (C1MSL18TSP) H'0080 1630 CAN1 Message Slot 19 Standard ID0 CAN1 Message Slot 19 Standard ID1 13-87 (C1MSL19SID0) (C1MSL19SID1) 13-89

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (33/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1632 CAN1 Message Slot 19 Extended ID0 CAN1 Message Slot 19 Extended ID1 13-91 (C1MSL19EID0) (C1MSL19EID1) 13-93 H'0080 1634 CAN1 Message Slot 19 Extended ID2 CAN1 Message Slot 19 Data Length Register 13-95 (C1MSL19EID2) (C1MSL19DLC) 13-97 H'0080 1636 CAN1 Message Slot 19 Data 0 CAN1 Message Slot 19 Data 1 13-99 (C1MSL19DT0) (C1MSL19DT1) 13-101 H'0080 1638 CAN1 Message Slot 19 Data 2 CAN1 Message Slot 19 Data 3 13-103 (C1MSL19DT2) (C1MSL19DT3) 13-105 H'0080 163A CAN1 Message Slot 19 Data 4 CAN1 Message Slot 19 Data 5 13-107 (C1MSL19DT4) (C1MSL19DT5) 13-109 H'0080 163C CAN1 Message Slot 19 Data 6 CAN1 Message Slot 19 Data 7 13-111 (C1MSL19DT6) (C1MSL19DT7) 13-113 H'0080 163E CAN1 Message Slot 19 Timestamp 13-115 (C1MSL19TSP) H'0080 1640 CAN1 Message Slot 20 Standard ID0 CAN1 Message Slot 20 Standard ID1 13-87 (C1MSL20SID0) (C1MSL20SID1) 13-89 H'0080 1642 CAN1 Message Slot 20 Extended ID0 CAN1 Message Slot 20 Extended ID1 13-91 (C1MSL20EID0) (C1MSL20EID1) 13-93 H'0080 1644 CAN1 Message Slot 20 Extended ID2 CAN1 Message Slot 20 Data Length Register 13-95 (C1MSL20EID2) (C1MSL20DLC) 13-97 H'0080 1646 CAN1 Message Slot 20 Data 0 CAN1 Message Slot 20 Data 1 13-99 (C1MSL20DT0) (C1MSL20DT1) 13-101 H'0080 1648 CAN1 Message Slot 20 Data 2 CAN1 Message Slot 20 Data 3 13-103 (C1MSL20DT2) (C1MSL20DT3) 13-105 H'0080 164A CAN1 Message Slot 20 Data 4 CAN1 Message Slot 20 Data 5 13-107 (C1MSL20DT4) (C1MSL20DT5) 13-109 H'0080 164C CAN1 Message Slot 20 Data 6 CAN1 Message Slot 20 Data 7 13-111 (C1MSL20DT6) (C1MSL20DT7) 13-113 H'0080 164E CAN1 Message Slot 20 Timestamp 13-115 (C1MSL20TSP) H'0080 1650 CAN1 Message Slot 21 Standard ID0 CAN1 Message Slot 21 Standard ID1 13-87 (C1MSL21SID0) (C1MSL21SID1) 13-89 H'0080 1652 CAN1 Message Slot 21 Extended ID0 CAN1 Message Slot 21 Extended ID1 13-91 (C1MSL21EID0) (C1MSL21EID1) 13-93 H'0080 1654 CAN1 Message Slot 21 Extended ID2 CAN1 Message Slot 21 Data Length Register 13-95 (C1MSL21EID2) (C1MSL21DLC) 13-97 H'0080 1656 CAN1 Message Slot 21 Data 0 CAN1 Message Slot 21 Data 1 13-99 (C1MSL21DT0) (C1MSL21DT1) 13-101 H'0080 1658 CAN1 Message Slot 21 Data 2 CAN1 Message Slot 21 Data 3 13-103 (C1MSL21DT2) (C1MSL21DT3) 13-105 H'0080 165A CAN1 Message Slot 21 Data 4 CAN1 Message Slot 21 Data 5 13-107 (C1MSL21DT4) (C1MSL21DT5) 13-109 H'0080 165C CAN1 Message Slot 21 Data 6 CAN1 Message Slot 21 Data 7 13-111 (C1MSL21DT6) (C1MSL21DT7) 13-113 H'0080 165E CAN1 Message Slot 21 Timestamp 13-115 (C1MSL21TSP) H'0080 1660 CAN1 Message Slot 22 Standard ID0 CAN1 Message Slot 22 Standard ID1 13-87 (C1MSL22SID0) (C1MSL22SID1) 13-89 H'0080 1662 CAN1 Message Slot 22 Extended ID0 CAN1 Message Slot 22 Extended ID1 13-91 (C1MSL22EID0) (C1MSL22EID1) 13-93 H'0080 1664 CAN1 Message Slot 22 Extended ID2 CAN1 Message Slot 22 Data Length Register 13-95 (C1MSL22EID2) (C1MSL22DLC) 13-97 H'0080 1666 CAN1 Message Slot 22 Data 0 CAN1 Message Slot 22 Data 1 13-99 (C1MSL22DT0) (C1MSL22DT1) 13-101 H'0080 1668 CAN1 Message Slot 22 Data 2 CAN1 Message Slot 22 Data 3 13-103 (C1MSL22DT2) (C1MSL22DT3) 13-105 H'0080 166A CAN1 Message Slot 22 Data 4 CAN1 Message Slot 22 Data 5 13-107 (C1MSL22DT4) (C1MSL22DT5) 13-109 H'0080 166C CAN1 Message Slot 22 Data 6 CAN1 Message Slot 22 Data 7 13-111 (C1MSL22DT6) (C1MSL22DT7) 13-113 H'0080 166E CAN1 Message Slot 22 Timestamp 13-115 (C1MSL22TSP) H'0080 1670 CAN1 Message Slot 23 Standard ID0 CAN1 Message Slot 23 Standard ID1 13-87 (C1MSL23SID0) (C1MSL23SID1) 13-89 H'0080 1672 CAN1 Message Slot 23 Extended ID0 CAN1 Message Slot 23 Extended ID1 13-91 (C1MSL23EID0) (C1MSL23EID1) 13-93 H'0080 1674 CAN1 Message Slot 23 Extended ID2 CAN1 Message Slot 23 Data Length Register 13-95 (C1MSL23EID2) (C1MSL23DLC) 13-97 H'0080 1676 CAN1 Message Slot 23 Data 0 CAN1 Message Slot 23 Data 1 13-99 (C1MSL23DT0) (C1MSL23DT1) 13-101

3-4332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (34/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1678 CAN1 Message Slot 23 Data 2 CAN1 Message Slot 23 Data 3 13-103 (C1MSL23DT2) (C1MSL23DT3) 13-105 H'0080 167A CAN1 Message Slot 23 Data 4 CAN1 Message Slot 23 Data 5 13-107 (C1MSL23DT4) (C1MSL23DT5) 13-109 H'0080 167C CAN1 Message Slot 23 Data 6 CAN1 Message Slot 23 Data 7 13-111 (C1MSL23DT6) (C1MSL23DT7) 13-113 H'0080 167E CAN1 Message Slot 23 Timestamp 13-115 (C1MSL23TSP) H'0080 1680 CAN1 Message Slot 24 Standard ID0 CAN1 Message Slot 24 Standard ID1 13-87 (C1MSL24SID0) (C1MSL24SID1) 13-89 H'0080 1682 CAN1 Message Slot 24 Extended ID0 CAN1 Message Slot 24 Extended ID1 13-91 (C1MSL24EID0) (C1MSL24EID1) 13-93 H'0080 1684 CAN1 Message Slot 24 Extended ID2 CAN1 Message Slot 24 Data Length Register 13-95 (C1MSL24EID2) (C1MSL24DLC) 13-97 H'0080 1686 CAN1 Message Slot 24 Data 0 CAN1 Message Slot 24 Data 1 13-99 (C1MSL24DT0) (C1MSL24DT1) 13-101 H'0080 1688 CAN1 Message Slot 24 Data 2 CAN1 Message Slot 24 Data 3 13-103 (C1MSL24DT2) (C1MSL24DT3) 13-105 H'0080 168A CAN1 Message Slot 24 Data 4 CAN1 Message Slot 24 Data 5 13-107 (C1MSL24DT4) (C1MSL24DT5) 13-109 H'0080 168C CAN1 Message Slot 24 Data 6 CAN1 Message Slot 24 Data 7 13-111 (C1MSL24DT6) (C1MSL24DT7) 13-113 H'0080 168E CAN1 Message Slot 24 Timestamp 13-115 (C1MSL24TSP) H'0080 1690 CAN1 Message Slot 25 Standard ID0 CAN1 Message Slot 25 Standard ID1 13-87 (C1MSL25SID0) (C1MSL25SID1) 13-89 H'0080 1692 CAN1 Message Slot 25 Extended ID0 CAN1 Message Slot 25 Extended ID1 13-91 (C1MSL25EID0) (C1MSL25EID1) 13-93 H'0080 1694 CAN1 Message Slot 25 Extended ID2 CAN1 Message Slot 25 Data Length Register 13-95 (C1MSL25EID2) (C1MSL25DLC) 13-97 H'0080 1696 CAN1 Message Slot 25 Data 0 CAN1 Message Slot 25 Data 1 13-99 (C1MSL25DT0) (C1MSL25DT1) 13-101 H'0080 1698 CAN1 Message Slot 25 Data 2 CAN1 Message Slot 25 Data 3 13-103 (C1MSL25DT2) (C1MSL25DT3) 13-105 H'0080 169A CAN1 Message Slot 25 Data 4 CAN1 Message Slot 25 Data 5 13-107 (C1MSL25DT4) (C1MSL25DT5) 13-109 H'0080 169C CAN1 Message Slot 25 Data 6 CAN1 Message Slot 25 Data 7 13-111 (C1MSL25DT6) (C1MSL25DT7) 13-113 H'0080 169E CAN1 Message Slot 25 Timestamp 13-115 (C1MSL25TSP) H'0080 16A0 CAN1 Message Slot 26 Standard ID0 CAN1 Message Slot 26 Standard ID1 13-87 (C1MSL26SID0) (C1MSL26SID1) 13-89 H'0080 16A2 CAN1 Message Slot 26 Extended ID0 CAN1 Message Slot 26 Extended ID1 13-91 (C1MSL26EID0) (C1MSL26EID1) 13-93 H'0080 16A4 CAN1 Message Slot 26 Extended ID2 CAN1 Message Slot 26 Data Length Register 13-95 (C1MSL26EID2) (C1MSL26DLC) 13-97 H'0080 16A6 CAN1 Message Slot 26 Data 0 CAN1 Message Slot 26 Data 1 13-99 (C1MSL26DT0) (C1MSL26DT1) 13-101 H'0080 16A8 CAN1 Message Slot 26 Data 2 CAN1 Message Slot 26 Data 3 13-103 (C1MSL26DT2) (C1MSL26DT3) 13-105 H'0080 16AA CAN1 Message Slot 26 Data 4 CAN1 Message Slot 26 Data 5 13-107 (C1MSL26DT4) (C1MSL26DT5) 13-109 H'0080 16AC CAN1 Message Slot 26 Data 6 CAN1 Message Slot 26 Data 7 13-111 (C1MSL26DT6) (C1MSL26DT7) 13-113 H'0080 16AE CAN1 Message Slot 26 Timestamp 13-115 (C1MSL26TSP) H'0080 16B0 CAN1 Message Slot 27 Standard ID0 CAN1 Message Slot 27 Standard ID1 13-87 (C1MSL27SID0) (C1MSL27SID1) 13-89 H'0080 16B2 CAN1 Message Slot 27 Extended ID0 CAN1 Message Slot 27 Extended ID1 13-91 (C1MSL27EID0) (C1MSL27EID1) 13-93 H'0080 16B4 CAN1 Message Slot 27 Extended ID2 CAN1 Message Slot 27 Data Length Register 13-95 (C1MSL27EID2) (C1MSL27DLC) 13-97 H'0080 16B6 CAN1 Message Slot 27 Data 0 CAN1 Message Slot 27 Data 1 13-99 (C1MSL27DT0) (C1MSL27DT1) 13-101 H'0080 16B8 CAN1 Message Slot 27 Data 2 CAN1 Message Slot 27 Data 3 13-103 (C1MSL27DT2) (C1MSL27DT3) 13-105 H'0080 16BA CAN1 Message Slot 27 Data 4 CAN1 Message Slot 27 Data 5 13-107 (C1MSL27DT4) (C1MSL27DT5) 13-109 H'0080 16BC CAN1 Message Slot 27 Data 6 CAN1 Message Slot 27 Data 7 13-111 (C1MSL27DT6) (C1MSL27DT7) 13-113

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (35/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 16BE CAN1 Message Slot 27 Timestamp 13-115 (C1MSL27TSP) H'0080 16C0 CAN1 Message Slot 28 Standard ID0 CAN1 Message Slot 28 Standard ID1 13-87 (C1MSL28SID0) (C1MSL28SID1) 13-89 H'0080 16C2 CAN1 Message Slot 28 Extended ID0 CAN1 Message Slot 28 Extended ID1 13-91 (C1MSL28EID0) (C1MSL28EID1) 13-93 H'0080 16C4 CAN1 Message Slot 28 Extended ID2 CAN1 Message Slot 28 Data Length Register 13-95 (C1MSL28EID2) (C1MSL28DLC) 13-97 H'0080 16C6 CAN1 Message Slot 28 Data 0 CAN1 Message Slot 28 Data 1 13-99 (C1MSL28DT0) (C1MSL28DT1) 13-101 H'0080 16C8 CAN1 Message Slot 28 Data 2 CAN1 Message Slot 28 Data 3 13-103 (C1MSL28DT2) (C1MSL28DT3) 13-105 H'0080 16CA CAN1 Message Slot 28 Data 4 CAN1 Message Slot 28 Data 5 13-107 (C1MSL28DT4) (C1MSL28DT5) 13-109 H'0080 16CC CAN1 Message Slot 28 Data 6 CAN1 Message Slot 28 Data 7 13-111 (C1MSL28DT6) (C1MSL28DT7) 13-113 H'0080 16CE CAN1 Message Slot 28 Timestamp 13-115 (C1MSL28TSP) H'0080 16D0 CAN1 Message Slot 29 Standard ID0 CAN1 Message Slot 29 Standard ID1 13-87 (C1MSL29SID0) (C1MSL29SID1) 13-89 H'0080 16D2 CAN1 Message Slot 29 Extended ID0 CAN1 Message Slot 29 Extended ID1 13-91 (C1MSL29EID0) (C1MSL29EID1) 13-93 H'0080 16D4 CAN1 Message Slot 29 Extended ID2 CAN1 Message Slot 29 Data Length Register 13-95 (C1MSL29EID2) (C1MSL29DLC) 13-97 H'0080 16D6 CAN1 Message Slot 29 Data 0 CAN1 Message Slot 29 Data 1 13-99 (C1MSL29DT0) (C1MSL29DT1) 13-101 H'0080 16D8 CAN1 Message Slot 29 Data 2 CAN1 Message Slot 29 Data 3 13-103 (C1MSL29DT2) (C1MSL29DT3) 13-105 H'0080 16DA CAN1 Message Slot 29 Data 4 CAN1 Message Slot 29 Data 5 13-107 (C1MSL29DT4) (C1MSL29DT5) 13-109 H'0080 16DC CAN1 Message Slot 29 Data 6 CAN1 Message Slot 29 Data 7 13-111 (C1MSL29DT6) (C1MSL29DT7) 13-113 H'0080 16DE CAN1 Message Slot 29 Timestamp 13-115 (C1MSL29TSP) H'0080 16E0 CAN1 Message Slot 30 Standard ID0 CAN1 Message Slot 30 Standard ID1 13-87 (C1MSL30SID0) (C1MSL30SID1) 13-89 H'0080 16E2 CAN1 Message Slot 30 Extended ID0 CAN1 Message Slot 30 Extended ID1 13-91 (C1MSL30EID0) (C1MSL30EID1) 13-93 H'0080 16E4 CAN1 Message Slot 30 Extended ID2 CAN1 Message Slot 30 Data Length Register 13-95 (C1MSL30EID2) (C1MSL30DLC) 13-97 H'0080 16E6 CAN1 Message Slot 30 Data 0 CAN1 Message Slot 30 Data 1 13-99 (C1MSL30DT0) (C1MSL30DT1) 13-101 H'0080 16E8 CAN1 Message Slot 30 Data 2 CAN1 Message Slot 30 Data 3 13-103 (C1MSL30DT2) (C1MSL30DT3) 13-105 H'0080 16EA CAN1 Message Slot 30 Data 4 CAN1 Message Slot 30 Data 5 13-107 (C1MSL30DT4) (C1MSL30DT5) 13-109 H'0080 16EC CAN1 Message Slot 30 Data 6 CAN1 Message Slot 30 Data 7 13-111 (C1MSL30DT6) (C1MSL30DT7) 13-113 H'0080 16EE CAN1 Message Slot 30 Timestamp 13-115 (C1MSL30TSP) H'0080 16F0 CAN1 Message Slot 31 Standard ID0 CAN1 Message Slot 31 Standard ID1 13-87 (C1MSL31SID0) (C1MSL31SID1) 13-89 H'0080 16F2 CAN1 Message Slot 31 Extended ID0 CAN1 Message Slot 31 Extended ID1 13-91 (C1MSL31EID0) (C1MSL31EID1) 13-93 H'0080 16F4 CAN1 Message Slot 31 Extended ID2 CAN1 Message Slot 31 Data Length Register 13-95 (C1MSL31EID2) (C1MSL31DLC) 13-97 H'0080 16F6 CAN1 Message Slot 31 Data 0 CAN1 Message Slot 31 Data 1 13-99 (C1MSL31DT0) (C1MSL31DT1) 13-101 H'0080 16F8 CAN1 Message Slot 31 Data 2 CAN1 Message Slot 31 Data 3 13-103 (C1MSL31DT2) (C1MSL31DT3) 13-105 H'0080 16FA CAN1 Message Slot 31 Data 4 CAN1 Message Slot 31 Data 5 13-107 (C1MSL31DT4) (C1MSL31DT5) 13-109 H'0080 16FC CAN1 Message Slot 31 Data 6 CAN1 Message Slot 31 Data 7 13-111 (C1MSL31DT6) (C1MSL31DT7) 13-113 H'0080 16FE CAN1 Message Slot 31 Timestamp 13-115 (C1MSL31TSP) (Use inhibited area)|

3-4532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (36/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 2000 DIN Interrupt Request Status Register DIN Interrupt Request Enable Register 14-9 (DRIDINIST) (DRIDINIEN) H'0080 2002 DEC Interrupt Request Status Register DEC Interrupt Request Enable Register 14-10 (DRIDECIST) (DRIDECIEN) H'0080 2004 DRI Transfer Interrupt Request Status Register DRI Transfer Interrupt Request Enable Register 14-11 (DRITRMIST) (DRITRMIEN) 14-12 H'0080 2006 DRI Transfer Control Register DRI Special Mode Register 14-13 (DRITRMCNT) (DRISPMOD) 14-15 H'0080 2008 DRI Data Capture Control Register 14-18 (DRIDCAPCNT) H'0080 200A DRI Data Interleave Control Register DIN Input Event Select Register 14-22 (DRIDSELCNT) (DINSEL) H'0080 200C DD Input Enable Register 0 DD Input Enable Register 1 14-23 (DRIDDEN0) (DRIDDEN1) H'0080 200E DD Input Enable Register 2 DD Input Enable Register 3 14-23 (DRIDDEN2) (DRIDDEN3) 14-24 H'0080 2010 DRI Data Capture Event Count Setting Register (Upper) 14-25 (DRIDCAPNUM) H'0080 2012 (Lower) H'0080 2014 DRI Capture Event Counter (Upper) 14-26 (DRIDCAPCT) H'0080 2016 (Lower) H'0080 2018 DRI Transfer Counter (Upper) 14-27 (DRITRMCT) H'0080 201A (Lower) (Use inhibited area) H'0080 2020 DRI Address Reload Register 0 (Upper) 14-29 (DRIADR0RLD) H'0080 2022 (Lower) H'0080 2024 DRI Address Counter 0 (Upper) 14-28 (DRIADR0CT) H'0080 2026 (Lower) H'0080 2028 DRI Address Reload Register 1 (Upper) 14-29 (DRIADR1RLD) H'0080 202A (Lower) H'0080 202C DRI Address Counter 1 (Upper) 14-28 (DRIADR1CT) H'0080 202E (Lower) H'0080 2030 DIN Input Processing Control Register 14-30 (DINCNT) H'0080 2032 DEC0 Control Register (Use inhibited area) 14-31 (DEC0CNT) H'0080 2034 DEC0 Reload Register 14-36 (DEC0RLD) H'0080 2036 DEC0 Counter 14-36 (DEC0CT) H'0080 2038 DEC1 Control Register (Use inhibited area) 14-31 (DEC1CNT) H'0080 203A DEC1 Reload Register 14-36 (DEC1RLD) H'0080 203C DEC1 Counter 14-36 (DEC1CT) H'0080 203E DEC2 Control Register (Use inhibited area) 14-32 (DEC2CNT) H'0080 2040 DEC2 Reload Register 14-36 (DEC2RLD) H'0080 2042 DEC2 Counter 14-36 (DEC2CT) H'0080 2044 DEC3 Control Register (Use inhibited area) 14-32 (DEC3CNT)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SFR Area Register Map (37/37) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 2046 DEC3 Reload Register 14-36 (DEC3RLD) H'0080 2048 DEC3 Counter 14-36 (DEC3CT) H'0080 204A DEC4 Control Register (Use inhibited area) 14-33 (DEC4CNT) H'0080 204C DEC4 Reload Register 14-36 (DEC4RLD) H'0080 204E DEC4 Counter 14-36 (DEC4CT) (Use inhibited area) H'0080 3FFE (Use inhibited area) Note 1 : Address H'0080 0600 to H'0080 0603 are dummy areas. When there is access to these areas, writing value is disabled and reading value is undefinited. In addition, it does not effect on the other SFR area by writing and reading out operation to dummy access area. Note 2 : This area exists only in the 32192 and it is use prohibition area in the 32195/32196. Note 3 : This area exists only in the 32192/32196 and it is use prohibition area in the 32195.

3-4732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 NBD Control Area Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'E000 0000 NBD Enable Register (Use inhibited area) 16-6 (NBDENB) H'E000 0002 (Use inhibited area) H'E000 0004 NBD Pin Control Register (Use inhibited area) 16-4 (NBDCNT) H'E000 0006 (Use inhibited area) H'E000 0008 Event Generation Register (Use inhibited area) 16-12 (NEVNTGEN)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The EIT vector entry is located at the beginning of the internal ROM/external extension areas. The branch in- struction for jumping to the start address of each EIT event processing handler is written here. Note that it is the branch instruction and not the jump address itself that is written here. For details, see Chapter 4, "EIT." H'0000 0040 H'0000 0044 H'0000 0048 H'0000 004C H'0000 0050 H'0000 0054 H'0000 0058 H'0000 005C H'0000 0060 H'0000 0064 H'0000 0068 H'0000 006C H'0000 0070 H'0000 0074 H'0000 0078 H'0000 007C H'0000 0080 H'0000 0090 H'0000 0030 H'0000 0020 H'0000 0010 H'0000 0000 H'0000 0034 H'0000 0038 H'0000 003C H'0000 0024 H'0000 0028 H'0000 002C H'0000 0004 H'0000 0008 H'0000 000C H'0000 0014 H'0000 0018 H'0000 001C TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 AE (Address Exception) EI (External Interrupt) (Note 1) RI (Reset Interrupt) SBI (System Break Interrupt) RIE (Reserved Instruction Exception) FPE (Floating-Point Exception) 03 1 Note 1: When flash entry bit = 1 (flash E/W enable mode), the EI vector entry is located at H'0080 4000. Figure 3.5.1 EIT Vector Entry

3-4932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The ICU vector table is used by the internal interrupt controller of the microcomputer. This table has the ad- dresses shown below, at which the start addresses of interrupt handlers for the interrupt requests from respec- tive internal peripheral I/Os are set. For details, see Chapter 5, "Interrupt Controller." ICU Vector Table Memory Map (1/3) Address +0 address +1 address b0 b7 b8 b15 H'0000 0094 MJT Input Interrupt 4 Handler Start Address (A0–A15) H'0000 0096 MJT Input Interrupt 4 Handler Start Address (A16–A31) H'0000 0098 MJT Input Interrupt 3 Handler Start Address (A0–A15) H'0000 009A MJT Input Interrupt 3 Handler Start Address (A16–A31) H'0000 009C MJT Input Interrupt 2 Handler Start Address (A0–A15) H'0000 009E MJT Input Interrupt 2 Handler Start Address (A16–A31) H'0000 00A0 MJT Input Interrupt 1 Handler Start Address (A0–A15) H'0000 00A2 MJT Input Interrupt 1 Handler Start Address (A16–A31) H'0000 00A4 MJT Input Interrupt 0 Handler Start Address (A0–A15) H'0000 00A6 MJT Input Interrupt 0 Handler Start Address (A16–A31) H'0000 00A8 MJT Output Interrupt 7 Handler Start Address (A0–A15) H'0000 00AA MJT Output Interrupt 7 Handler Start Address (A16–A31) H'0000 00AC MJT Output Interrupt 6 Handler Start Address (A0–A15) H'0000 00AE MJT Output Interrupt 6 Handler Start Address (A16–A31) H'0000 00B0 MJT Output Interrupt 5 Handler Start Address (A0–A15) H'0000 00B2 MJT Output Interrupt 5 Handler Start Address (A16–A31) H'0000 00B4 MJT Output Interrupt 4 Handler Start Address (A0–A15) H'0000 00B6 MJT Output Interrupt 4 Handler Start Address (A16–A31) H'0000 00B8 MJT Output Interrupt 3 Handler Start Address (A0–A15) H'0000 00BA MJT Output Interrupt 3 Handler Start Address (A16–A31) H'0000 00BC MJT Output Interrupt 2 Handler Start Address (A0–A15) H'0000 00BE MJT Output Interrupt 2 Handler Start Address (A16–A31) H'0000 00C0 MJT Output Interrupt 1 Handler Start Address (A0–A15) H'0000 00C2 MJT Output Interrupt 1 Handler Start Address (A16–A31) H'0000 00C4 MJT Output Interrupt 0 Handler Start Address (A0–A15) H'0000 00C6 MJT Output Interrupt 0 Handler Start Address (A16–A31) H'0000 00C8 DMA0–4 Interrupt Handler Start Address (A0–A15) H'0000 00CA DMA0–4 Interrupt Handler Start Address (A16–A31) H'0000 00CC SIO1 Receive Interrupt Handler Start Address (A0–A15) H'0000 00CE SIO1 Receive Interrupt Handler Start Address (A16–A31) H'0000 00D0 SIO1 Transmit Interrupt Handler Start Address (A0–A15) H'0000 00D2 SIO1 Transmit Interrupt Handler Start Address (A16–A31) H'0000 00D4 SIO0 Receive Interrupt Handler Start Address (A0–A15) H'0000 00D6 SIO0 Receive Interrupt Handler Start Address (A16–A31)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 ICU Vector Table Memory Map (2/3) Address +0 address +1 address b0 b7 b8 b15 H'0000 00D8 SIO0 Transmit Interrupt Handler Start Address (A0–A15) H'0000 00DA SIO0 Transmit Interrupt Handler Start Address (A16–A31) H'0000 00DC A/D0 Conversion Interrupt Handler Start Address (A0–A15) H'0000 00DE A/D0 Conversion Interrupt Handler Start Address (A16–A31) H'0000 00E0 TID0 Input Interrupt Handler Start Address (A0–A15) H'0000 00E2 TID0 Input Interrupt Handler Start Address (A16–A31) H'0000 00E4 TOU0 Output Interrupt Handler Start Address (A0–A15) H'0000 00E6 TOU0 Output Interrupt Handler Start Address (A16–A31) H'0000 00E8 DMA5–9 Interrupt Handler Start Address (A0–A15) H'0000 00EA DMA5–9 Interrupt Handler Start Address (A16–A31) H'0000 00EC SIO2, 3 Transmit/receive Interrupt Handler Start Address (A0–A15) H'0000 00EE SIO2, 3 Transmit/receive Interrupt Handler Start Address (A16–A31) H'0000 00F0 RTD Interrupt Handler Start Address (A0–A15) H'0000 00F2 RTD Interrupt Handler Start Address (A16–A31) H'0000 00F4 TID1 Input Interrupt Handler Start Address (A0–A15) H'0000 00F6 TID1 Input Interrupt Handler Start Address (A16–A31) H'0000 00F8 TOU1 Output Interrupt Handler Start Address (A0–A15) H'0000 00FA TOU1 Output Interrupt Handler Start Address (A16–A31) H'0000 00FC SIO4, 5 Transmit/receive Interrupt Handler Start Address (A0–A15) H'0000 00FE SIO4, 5 Transmit/receive Interrupt Handler Start Address (A16–A31) H'0000 0100 H'0000 0102 H'0000 0104 H'0000 0106 H'0000 0108 TML1 Input Interrupt Handler Start Address (A0–A15) H'0000 010A TML1 Input Interrupt Handler Start Address (A16–A31) H'0000 010C CAN0 Transmit/receive & Error Interrupt Handler Start Address (A0–A15) H'0000 010E CAN0 Transmit/receive & Error Interrupt Handler Start Address (A16–A31) H'0000 0110 CAN1 Transmit/receive & Error Interrupt Handler Start Address (A0–A15) H'0000 0112 CAN1 Transmit/receive & Error Interrupt Handler Start Address (A16–A31) H'0000 0114 DRI Transfer Interrupt Handler Start Address (A0–A15) H'0000 0116 DRI Transfer Interrupt Handler Start Address (A16–A31) H'0000 0118 DRI Counter Interrupt Handler Start Address (A0–A15) H'0000 011A DRI Counter Interrupt Handler Start Address (A16–A31) H'0000 011C DRI Event Detection Interrupt Handler Start Address (A0–A15) H'0000 011E DRI Event Detection Interrupt Handler Start Address (A16–A31) H'0000 0120 CAN0 Transmit/receive Completion Interrupt Handler Start Address (A0–A15) H'0000 0122 CAN0 Transmit/receive Completion Interrupt Handler Start Address (A16–A31)

3-5132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 ICU Vector Table Memory Map (3/3) Address +0 address +1 address b0 b7 b8 b15 H'0000 0124 CAN0 Single-shot Interrupt Handler Start Address (A0–A15) H'0000 0126 CAN0 Single-shot Interrupt Handler Start Address (A16–A31) H'0000 0128 CAN0 Error Interrupt Handler Start Address (A0–A15) H'0000 012A CAN0 Error Interrupt Handler Start Address (A16–A31) H'0000 012C CAN1 Transmit/receive Completion Interrupt Handler Start Address (A0–A15) H'0000 012E CAN1 Transmit/receive Completion Interrupt Handler Start Address (A16–A31) H'0000 0130 CAN1 Single-shot Interrupt Handler Start Address (A0–A15) H'0000 0132 CAN1 Single-shot Interrupt Handler Start Address (A16–A31) H'0000 0134 CAN1 Error Interrupt Handler Start Address (A0–A15) H'0000 0136 CAN1 Error Interrupt Handler Start Address (A16–A31) H'0000 0138 RAM Write Monitor Interrupt Handler Start Address (A0–A15) H'0000 013A RAM Write Monitor Interrupt Handler Start Address (A16–A31)

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• Virtual flash emulation function The microcomputer has the function to map 8-Kbyte memory blocks of the internal RAM (maximum for 32192 is 16 blocks, for 32195 is 4 blocks, for 32196 is 8 blocks) into areas (L banks) of the internal flash memory that are divided in 8-Kbyte units. This functions is referred to as the Virtual Flash Emulation Function. This function allows the data located in 8-Kbyte blocks of the internal RAM to be changed with the contents of internal flash memory at the addresses specified by the Virtual Flash L Bank Register. That way, the relevant RAM data can read out by reading the content of internal flash memory. For details about this function, see Section 6.7, "Virtual Flash Emulation Function."
• Dummy access area Address H'0080 0600 to H'0080 0603 are dummy areas. When there is access to these areas, writing value is disabled and reading value is undefinited. In addition, it does not effect on the other SFR area by writing and reading out operation to dummy access area.

4.1 Outline of EIT

4.2 EIT Events

4.3 EIT Processing Procedure

4.4 EIT Processing Mechanism

4.5 Acceptance of EIT Events

4.6 Saving and Restoring the PC and PSW

4.7 EIT Vector Entry

4.8 Exception Processing

4.9 Interrupt Processing

4.10 Trap Processing

4.11 EIT Priority Levels

4.12 Example of EIT Processing

4.13 Notes on EIT

4-232192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. Events like this one are referred to by a generic name as EIT (Exception, Interrupt and Trap). (1) Exception This is an event related to the context being executed. It is generated by an error or violation during instruction execution. This type of event includes Address Exception (AE), Reserved Instruction Exception (RIE) and Float- ing-Point Exception (FPE). (2) Interrupt This is an event generated irrespective of the context being executed. It is generated by a hardware-derived signal from an external source, as well as by the internal peripheral I/O. This type of event includes Reset Interrupt (RI), System Break Interrupt (SBI) and External Interrupt (EI). (3) Trap This refers to a software interrupt generated by executing a TRAP instruction. This type of event is intentionally generated in a program as in the OS’s system call by the programmer. Figure 4.1.1 Classification of EITs EIT Exception (Exception) Reserved Instruction Exception (RIE) Address Exception (AE) Floating-Point Exception (FPE) Reset Interrupt (RI) System Break Interrupt (SBI) External Interrupt (EI) Trap (TRAP) Interrupt (Interrupt) Trap (Trap)

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4.2.1 Exception

(1) Reserved Instruction Exception (RIE) Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (unimplemented instruction) is detected. (2) Address Exception (AE) Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions. (3) Floating-point Exception (FPE) Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five excep- tions specified in the IEEE 754 standard (OVF/UDF/IXCT/DIV0/IVLD) is detected. Each exception pro- cessing is outlined below. 1) Overflow Exception (OVF) The exception occurs when the absolute value of the operation result exceeds the largest describable precision in the floating-point format. The following table shows the operation results when an OVF occurs. Table 4.2.1 Operation Results When an OVF Occurred Note 1: When the overflow exception enable (EO) bit (FPSR register bit 20) = "0" Note 2: When the overflow exception enable (EO) bit (FPSR register bit 20) = "1" Notes:  If an OVF occurs while EIT processing for OVF is masked, an IXCT occurs at the same time.  +MAX = H’7F7F FFFF, –MAX = H’FF7F FFFF 2) Underflow Exception (UDF) The exception occurs when the absolute value of the operation result is less than the largest describable precision in the floating-point format. The following table shows the operation results when a UDF occurs. Table 4.2.2 Operation Results when a UDF Occurred Note 1: When the underflow exception enable (EU) bit (FPSR register bit 18) = "0" Note 2: When the underflow exception enable (EU) bit (FPSR register bit 18) = "1" Sign of the Resul t -Infinity +Infinity Rounding Mode Nearest Operation Result (Content When the OVF EIT processing is masked (Note 1) +MAX -Infinity +Infinity -MAX +MAX -MAX +Infinity -Infinity of the Destination Register) When the OVF EIT processing is executed (Note 2) No change Operation Result (Content When UDF EIT processing is masked (Note 1) DN = 0: An unimplemented exception occurs DN = 1: 0 is returned of the Destination Register) When UDF EIT processing is executed (Note 2) No change

4-432192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Note 1: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "0" Note 2: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "1" Please note that the DIV0 EIT processing does not occur in the following conditions. Table 4.2.5 Cases in Which No DIV0 Occur 3) Inexact Exception (IXCT) The exception occurs when the operation result differs from a result led out with an infinite range of precision. The following table shows the operation results and the respective conditions in which each IXCT occurs. Table 4.2.3 Operation Results when an IXCT Occurred Note 1: When the inexact exception enable (EX) bit (FPSR register bit 17) = "0" Note 2: When the inexact exception enable (EX) bit (FPSR register bit 17) = "1" 4) Zero Division Exception (DIV0) The exception occurs when a finite nonzero value is divided by zero. The following table shows the operation results when a DIV0 is occurs. Table 4.2.4 Operation Results When a DIV0 Occurred Overflow occurs in OVF masked condition Rounding occurs Occurrence Condition Operation Result (Content of When the IXCT EIT processing is masked (Note 1) Reference OVF operation results Rounded value the Destination Register) When the IXCT EIT processing is executed (Note 2) No change No change Nonzero finite value Dividend of the Destination Register) When the DIV0 EIT processing is executed (Note 2) No change Operation Result (Content When the DIV0 EIT processing is masked (Note 1) +-Infinity (Sign is derived by exclusive ORing the signs of the divisor and dividend.)Dividend Infinity Behavior An invalid operation exception occurs No exceptions occur (with the result = "Infinity")

4-532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 5) Invalid Operation Exception (IVLD) The exception occurs when an invalid operation is executed. The following table shows the operation results and the respective conditions in which each IVLD occurs. Table 4.2.6 Operation Results When an IVLD Occurred Note 1: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "0" Note 2: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "1" Note:  NaN (Not a Number) SNaN (Signaling NaN): a NaN in which the MSB of the decimal field is "0." When SNaN is used as the source operand in an operation, an IVLD occurs. SNaNs are useful in identifying program bugs when used as the initial value in a variable. However, SNaNs cannot be generated by hardware. QNaN (Quiet NaN): a NaN in which the MSB of the decimal field is "1." Even when QNaN is used as the source operand in an operation, an IVLD will not occur (excluding comparison and format conversion). Because a result can be influenced by the arithmetic operations, QNaN allows the user to debug without executing an EIT processing. QNaNs are created by hardware. 6) Unimplemented Exception (UIPL) The exception occurs when the denormalized number zero flush (DN) bit (FPSR register bit 23) = "0" and a denormalized number is given as an operation operand. (Note 1) Because the UIPL has no enable bits available, it cannot be masked when they occur. The destination register remains unchanged. Note 1: A UDF occurs when the intermediate result of an operation is a denormalized number, in which case if the DN bit (FPSR register bit 23) = "0", an UIPL occurs.

4.2.2 Interrupt

(1) Reset Interrupt (RI) Reset Interrupt (RI) is always accepted by entering the RESET# signal. The reset interrupt is assigned the highest priority. For details about the reset interrupt, see Chapter 7, “Reset.” (2) System Break Interrupt (SBI) System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. This interrupt can only be used in cases when after interrupt processing, control will not return to the program that was being executed when the interrupt occurred. (3) External Interrupt (EI) External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt controller. The interrupt controller manages these interrupts by assigning each one of eight priority levels including an interrupt-disabled state. When an integer conversion overflowed When FTOI ins truction was executed When NaN or Infinity was converted into an integer When FTOS ins truction was executed Occurrence Condition Operation for SNaN operand +Infinity-(+Infinity), -Infinity-(-Infinity) 0 x Infinity 0 / 0, Infinity / Infinity When < or > comparison was performed on NaN Operation Result (Content of the Destination Register) When the IVLD EIT processing is masked (Note 1) When the IVLD EIT processing is executed (Note 2) Return value when pre-conversion signed bit is: "0": H’7FFF FFFF "1": H’8000 0000 Return value when pre-conversion signed bit is: "0": H’0000 7FFF "1": H’FFFF 8000 Comparison results (comparison invalid) QNaN No change

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4.2.3 Trap

Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector addresses are provided corresponding to TRAP instruction operands 0–15. EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except for a reset interrupt, is shown below. Figure 4.3.1 Outline of the EIT Processing Procedure When an EIT is accepted, the CPU branches to the EIT vector after hardware preprocessing (as will be described later). The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction for the EIT handler (not the jump address itself) is written. In the hardware preprocessing, the PC is transferred to the BPC (backup PC), and the content of the PSW register’s PSW field is transferred to the BPSW field in that register. Other necessary operations must be performed in the user-created EIT handler. These include saving the BPC and PSW registers (including the BPSW field) and the general-purpose registers to be used in the EIT handler to the stack. In addition, the accumulator and the FPSR register must be saved to the stack as necessary. Remem- ber that all these registers must be saved to the stack in a program by the user. When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute the RTE instruction. Control is thereby returned from the EIT processing to the program that was being executed when the EIT occurred. (This does not apply to the System Break Interrupt, however.) In the hardware postprocessing, the BPC is returned to the PC, and the content of the PSW register’s BPSW field is returned to the PSW field in that register. Note that the values stored in the BPC and the PSW register’s BPSW field after executing the RTE instruction are undefined. Instruction A PC →BPC PSW →BPSW EIT vector entry EIT handler except for SBI RTE instruction Program suspended and EIT request accepted Instruction processing-canceled type (RIE, AE) Instruction processing-completed type (FPE, EI, TRAP) Program execution restarted EIT request generated Hardware preprocessing BPC, PSW, FPSR and general-purpose registers are saved to the stack Branch instruction BPC, PSW, FPSR and general-purpose registers are restored from the stack Hardware postprocessing (SBI) Program terminated or system is reset User-created EIT handler BPSW →PSW BPC →PC Processing by handler Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields. (Note 1) (Note 1) SBI (System Break Interrupt processing) Instruction B Instruction C Instruction C Instruction D

4-732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/Os. It also has the backup registers for the PC and PSW (the BPC register and the BPSW field of the PSW register). The EIT processing mechanism is shown below. Figure 4.4.1 EIT Processing Mechanism Interrupt controller (ICU) SBI EIInternal peripheral I/Os RESET# RI AE, RIE, FPE, TRAP IE flag (PSW) M32R CPU core SBI# Low High Priority SBI EI RI M32R/ECU PSW register PSWBPSW BPC register PC register

4-832192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 When an EIT event occurs, the CPU suspends the program it has hitherto been executed and branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are accepted are shown below. Table 4.5.1 Acceptance of EIT Events EIT Event Type of Processing Acceptance Timing Values Set in BPC Register Reserved Instruction Instruction processing- During instruction execution PC value of the instruction that Exception (RIE) canceled type generated RIE Address Exception (AE) Instruction processing- During instruction execution PC value of the instruction that canceled type generated AE Floating-Point Exception Instruction processing- Break in instructions PC value of the instruction that (FPE) completed type generated FPE + 4 Reset Interrupt (RI) Instruction processing- Each machine cycle Undefined value aborted type System Break Interrupt Instruction processing- Break in instructions PC value of the next instruction (SBI) completed type (word boundary only) External Interrupt (EI) Instruction processing- Break in instructions PC value of the next instruction completed type (word boundary only) Trap (TRAP) Instruction processing- Break in instructions PC value of TRAP instruction + 4 completed type The following describes operation of the microcomputer at the time when it accepts an EIT and when it executes the RTE instruction. (1) Hardware preprocessing when an EIT is accepted [1] Save the PSW register’s SM, IE and C bits in its backup field. BSM ← SM BIE ← IE BC ← C [2] Update the PSW register’s SM, IE and C bits SM ← Remains unchanged (RIE, AE, FPE, TRAP) or cleared to "0" (SBI, EI, RI) IE ← Cleared to "0" C ← Cleared to "0" [3] Save the PC register BPC ← PC [4] Set the vector address in the PC register Branches to the EIT vector and executes the branch (BRA) instruction written in it, thereby transferring control to the user-created EIT handler. (2) Hardware postprocessing when the RTE instruction is executed [A] Restore the PSW register’s SM, IE and C bits from its backup field. SM ← BSM IE ← BIE C ← BC [B] Restore the PC register from the BPC register. PC ← BPC Note:  The values stored in the BPC and the PSW register’s BSM, BIE and BC bits after executing the RTE instruction are undefined.

4-932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 [1] Saving the SM, IE and C bits BSM BIE BC SM IE C [2] Updating the SM, IE and C bits SM IE C Unchanged or 0 [3] Saving the PC BPC PC← [4] Setting the vector address in the PC PC Vector address← [B] Restoring the PC from the BPC register The value stored in the BPC register after executing the RTE instruction is undefined. [A] Restoring the SM, IE and C bits from the backup field SM IE C The values stored in the BSM, BIE and BC bits after executing the RTE instruction are undefined. BSM BIE BC [1] [A] [B] [2] [3] [4] Figure 4.6.1 Saving and Restoring the PC and PSW 16 17 23 24 25 31(LSB)15870(MSB) SM IE CBCBSM BIE 00000000000000000000000000PSW BPSW field PSW field

4-1032192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The EIT vector entry is located in the user space beginning with the address H’0000 0000. The table below lists the EIT vector entry and shows the states of SM bit, IE bit, and BPC bit after the occurrence of each EIT event. Table 4.7.1 EIT Vector Entry Name Abbreviation Vector Address SM IE BPC Reset Interrupt RI H'0000 0000 (Note 1) 0 0 Undefined System Break SBI H'0000 0010 0 0 PC of the next instruction Interrupt Reserved Instruction RIE H'0000 0020 Unchanged 0 PC of the instruction that generated RIE Exception Address Exception AE H'0000 0030 Unchanged 0 PC of the instruction that generated AE Trap TRAP0 H'0000 0040 Unchanged 0 PC of TRAP instruction + 4 TRAP1 H'0000 0044 Unchanged 0 PC of TRAP instruction + 4 TRAP2 H'0000 0048 Unchanged 0 PC of TRAP instruction + 4 TRAP3 H'0000 004C Unchanged 0 PC of TRAP instruction + 4 TRAP4 H'0000 0050 Unchanged 0 PC of TRAP instruction + 4 TRAP5 H'0000 0054 Unchanged 0 PC of TRAP instruction + 4 TRAP6 H'0000 0058 Unchanged 0 PC of TRAP instruction + 4 TRAP7 H'0000 005C Unchanged 0 PC of TRAP instruction + 4 TRAP8 H'0000 0060 Unchanged 0 PC of TRAP instruction + 4 TRAP9 H'0000 0064 Unchanged 0 PC of TRAP instruction + 4 TRAP10 H'0000 0068 Unchanged 0 PC of TRAP instruction + 4 TRAP11 H'0000 006C Unchanged 0 PC of TRAP instruction + 4 TRAP12 H'0000 0070 Unchanged 0 PC of TRAP instruction + 4 TRAP13 H'0000 0074 Unchanged 0 PC of TRAP instruction + 4 TRAP14 H'0000 0078 Unchanged 0 PC of TRAP instruction + 4 TRAP15 H'0000 007C Unchanged 0 PC of TRAP instruction + 4 External Interrupt EI H'0000 0080 (Note 2) 0 0 PC of the next instruction Floating-Point Exception FPE H'0000 0090 Unchanged 0 PC of the instruction that generated FPE + 4 Note 1: During boot mode, the CPU starts executing the boot program after exiting the reset state. For details, see Section 6.6, “Programming the Internal Flash Memory.” Note 2: During flash E/W enable mode, this vector address is moved to the beginning of the internal RAM (address H’0080 4000). For details, see Section 6.6, “Programming the Internal Flash Memory.”

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4.8.1 Reserved Instruction Exception (RIE)

[Occurrence Conditions] Reserved Instruction Exception (RIE) occurs when a reserved instruction (unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a reserved instruction exception occurs, the instruction that generated it is not executed. If an external interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved instruction exception that is accepted. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC The PC value of the instruction that generated the reserved instruction exception is set in the BPC regis- ter. For example, if the instruction that generated the reserved instruction exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction that generated the reserved instruction exception is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.) Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE) H'00 Address RIE occurredH'04 H'08 H'0C +0 +1 +2 +3 H'00 Address RIE occurredH'04 H'08 H'0C +0 +1 +2 +3 Return address BPC H'06BPC H'04 Return address

4-1232192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0020 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0020 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from a word-boundary instruction including the instruction that generated a RIE (see Figure 4.8.1). Except when using reserved instruction exceptions intentionally, occurrence of a reserved instruction exception suggests that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the reserved instruction exception handler to the program that was being executed when the exception occurred.

4.8.2 Address Exception (AE)

[Occurrence Conditions] Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions. The following lists the combination of instructions and accessed addresses that may cause address exceptions to occur.  Two low-order address bits accessed in the LDH, LDUH or STH instruction are ‘01’ or ‘11’  Two low-order address bits accessed in the LD, ST, LOCK or UNLOCK instruction are ‘01,’ ‘10’ or ‘11’ When an address exception occurs, memory access by the instruction that generated the exception is not performed. If an external interrupt is requested at the same time an address exception is detected, it is the address exception that is accepted. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC The PC value of the instruction that generated the address exception is set in the BPC register. For example, if the instruction that generated the address exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction that generated the address exception is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.)

4-1332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 4.8.2 Example of a Return Address for Address Exception (AE) (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0030 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0030 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from a word-boundary instruction including the instruction that generated an AE (see Figure 4.8.2). Except when using address exceptions intentionally, occurrence of an address exception suggests that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the address exception handler to the program that was being executed when the exception occurred.

4.8.3 Floating-Point Exception (FPE)

[Occurrence Conditions] Floating-Point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five excep- tions specified in IEEE 754 standards (OVF, UDF, IXCT, DIV0 or IVLD) is detected. Note, however, that the EIT processing described below is executed only when the exception that oc- curred is one whose exception enable bit in the FPSR register is set to "1" or an unimplemented excep- tion. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 H'00 Address AE occurredH'04 H'08 H'0C +0 +1 +2 +3 H'00 Address AE occurredH'04 H'08 H'0C +0 +1 +2 +3 BPC H'06BPC H'04 Return address Return address

4-1432192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (3) Saving the PC The PC value of the instruction that generated the FPE + 4 is set in the BPC register. Because all of the instructions that generate an FPE are 32 bits long, the address to which the RTE instruction returns is always the instruction next to the one that generated the FPE. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0090 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0090 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC, PSW and FPSR registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed.

4-1532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

4.9.1 Reset Interrupt (RI)

[Occurrence Conditions] A reset interrupt is accepted in machine cycle by pulling the RESET# input signal "L." The reset interrupt is assigned the highest priority among all EITs. [EIT Processing] (1) Initializing SM, IE and C bits The PSW register’s SM, IE and C bits are initialized as shown below. SM ← 0 IE ← 0 C ← 0 For the reset interrupt, the values of BSM, BIE and BC bits are undefined. (2) Branching to the EIT vector entry The CPU branches to the address H’0000 0000 in the user space. However, when operating in boot mode, the CPU jumps to the boot program. For details, see Section 6.6, “Programming the Internal Flash Memory.” (3) Jumping from the EIT vector entry to the user program The CPU executes the instruction written by the user at the address H’0000 0000 of the EIT vector entry. In the reset vector entry, be sure to initialize the PSW and SPI registers before jumping to the start address of the user program.

4.9.2 System Break Interrupt (SBI)

System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt cannot be masked by the PSW register IE bit. Therefore, the system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred. [Occurrence Conditions] A system break interrupt is accepted by a falling edge on SBI# input pin. (The system break interrupt cannot be masked by the PSW register IE bit.) In no case will a system break interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immedi- ately after branching.) Note also that because of the instruction processing-completed type, a system break interrupt is accepted after the instruction is completed.

4-1632192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Order in which instructions are executed 32-bit instruction Address 1000 Address 1002 Address 1004 Address 1008 Interrupt may be accepted Interrupt cannot be accepted 16-bit instruction Interrupt may be accepted Interrupt may be accepted Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving the PC The address of the next instruction (always on word boundary) following one in which the interrupt was detected is stored in the BPC register. If the interrupt was detected in a branch instruction, then the next instruction is one that exists at the jump address. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0010 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0010 of the EIT vector entry to jump to the start address of the user-created handler. The system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break inter- rupt occurred.

4-1732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 4.9.2 Timing at Which External Interrupt (EI) is Accepted [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving the PC The content of the PC register (always on word boundary) is saved to the BPC register. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0080 in the user space. However, when operating in flash E/W enable mode, the CPU goes to the beginning of the internal RAM (address H’0080 4000). (For details, see Section 6.6, “Programming the Internal Flash Memory.”) This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0080 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary.

4.9.3 External Interrupt (EI)

An external interrupt is generated upon an interrupt request which is output by the microcomputer’s internal interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority levels. For details, see Chapter 5, “Interrupt Controller.” For details about the interrupt request sources, see each section in which the relevant internal peripheral I/O is described. [Occurrence Conditions] External interrupts are managed based on interrupt requests from each internal peripheral I/O by the microcomputer’s internal interrupt controller, and are sent to the CPU via the interrupt controller. The CPU checks these interrupt requests at a break in instructions residing on word boundaries, and when an interrupt request is detected and the PSW register IE flag = "1", accepts it as an external interrupt. In no case will an external interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately after branching.) Order in which instructions are executed 32-bit instruction Address 1000 Address 1002 Address 1004 Address 1008 Interrupt may be accepted Interrupt cannot be accepted 16-bit instruction Interrupt may be accepted Interrupt may be accepted

4-1832192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 4.10.1 Example of a Return Address for Trap (TRAP) H'00 Address H'04 H'08 H'0C +0 +1 +2 +3 H'00 Address H'04 H'08 H'0C +0 +1 +2 +3 BPC H'0ABPC H'08 TRAP instruction Return address Return address TRAP instruction (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed.

4.10.1 Trap

[Occurrence Conditions] Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen traps are generated, each corresponding to one of TRAP instruction operands 0–15. Accordingly, sixteen vector entries are provided. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC When the trap instruction is executed, the PC value of TRAP instruction + 4 is set in the BPC register. For example, if the TRAP instruction is located at address 4, the value H’08 is set in the BPC register. Similarly, if the TRAP instruction is located at address 6, the value H’0A is set in the BPC register. The value of the BPC register bit 30 indicates whether the trap instruction resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 8. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.)

4-1932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (4) Branching to the EIT vector entry The CPU branches to the addresses H’0000 0040–H’0000 007C in the user space. This is the last opera- tion performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the addresses H’0000 0040–H’0000 007C of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user- created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from the next word-boundary instruction including the instruction that generates a trap (see Figure 4.10.1). The table below lists the priority levels of EIT events. When two or more EITs occur simultaneously, the event with the highest priority is accepted first. Table 4.11.1 Priority of EIT Events and How Returned from EIT Priority EIT Event Type of Processing Values Set in BPC Register Highest 1 Reset Interrupt (RI) Instruction processing-aborted type Undefined

2 Address Exception (AE) Instruction processing-canceled type PC of the instruction that

Reserved Instruction Instruction processing-canceled type PC of the instruction that Exception (RIE) generated RIE Floating-Point Exception Instruction processing-completed type PC of the instruction that (FPE) generated FPE + 4 Trap (TRAP) Instruction processing-completed type TRAP instruction + 4

3 System Break Interrupt Instruction processing-completed type PC of the next instruction

(SBI) Lowest 4 External Interrupt (EI) Instruction processing-completed type PC of the next instruction Note that for External Interrupt (EI), the priority levels of interrupt requests from each peripheral I/O are set by the microcomputer’s internal interrupt controller. For details, see Chapter 5, “Interrupt Controller.”

4-2032192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (1) When RIE, AE, FPE, SBI, EI or TRAP occurs singly Figure 4.12.1 Processing of Events When RIE, AE, FPE, SBI, EI or TRAP Occurs Singly (2) When RIE, AE, FPE or TRAP and EI occur simultaneously Figure 4.12.2 Processing of Events When RIE, AE, FPE or TRAP and EI Occur Simultaneously RTE instruction IE = 0 RIE, AE, FPE or TRAP is accepted first. BPC register = Return address AIE = 1 RIE, AE, FPE or TRAP and EI occur simultaneously Return address A: IE = 1 IE = 0 IE = 1 RTE instruction : EIT handler EI is accepted next. BPC register = Return address A RTE instruction IE = 0 IE = 1 BPC register = Return address A IE = 1 RIE, AE, FPE, SBI, EI or TRAP occurs singly Return address A: If IE = 0, no events but reset and SBI are accepted. : EIT handler

4-2132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 4.12.3 Example of EIT Processing BRA instruction RTE EIT handler EIT vector entry Program being executed Save BPC to the stack Save PSW to the stack Save general-purpose registers to the stack Processing by EIT handler Restore general-purpose registers from the stack Restore PSW from the stack Restore BPC from the stack EIT event occurs (SBI) System Break Interrupt (SBI) processing Program terminated or system reset (Other than SBI) PC →BPC PSW →BPSWHardware preprocessing Hardware postprocessingBPSW →PSW BPC →PC (Note 1) (Note 1) Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields.

4-2232192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The Address Exception (AE) requires caution because if one of the instructions that use “register indirect + register update” addressing mode (following three) generates an address exception when it is executed, the values of the registers to be automatically updated (Rsrc and Rsrc2) become undefined. Except that the values of Rsrc and Rsrc2 become undefined, these instructions behave the same way as when used in other addressing modes.  Applicable instructions LD Rdest, @Rsrc+ ST Rsrc1, @-Rsrc2 ST Rsrc1, @+Rsrc2 If the above case applies, consider the fact that the register values become undefined when you design the processing to be performed after executing said instructions. (If an address exception occurs, it means that the system has some fatal fault already existing in it. Therefore, address exceptions must be used on condition that control will not be returned from the address exception handler to the program that was being executed when the exception occurred.)

INTERRUPT CONTROLLER (ICU)

5.1 Outline of the Interrupt Controller

5.2 ICU Related Registers

5.3 Interrupt Request Sources in Internal

5.4 ICU Vector Table

5.5 Description of Interrupt Operation

5.6 Description of System Break Interrupt (SBI)

INTERRUPT CONTROLLER (ICU) 5-232192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are sent to the M32R CPU as external interrupts (EI). The maskable interrupts from internal peripheral I/Os are managed by assigning them one of eight priority levels including an interrupt-disabled state. If two or more interrupt requests with the same priority level occur at the same time, their priorities are resolved by predetermined hardware priority. The source of an interrupt request generated in internal peripheral I/Os is identified by reading the relevant interrupt status register provided for internal peripheral I/Os. On the other hand, the system break interrupt (SBI) is recognized when a low-going transition occurs on the SBI# signal input pin. This interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer, so that it is always accepted irrespective of the PSW register IE bit status. When the CPU has finished servicing an SBI, shut down or reset the system without returning to the program that was being executed when the interrupt occurred. Specifications of the Interrupt Controller are outlined below. Table 5.1.1 Outline of the Interrupt Controller (ICU) Item Specification Interrupt request source Maskable interrupt requests from internal peripheral I/Os : 40 sources (Note 1) System break interrupt request : 1 source (entered from SBI# pin) Priority management 8 priority levels including an interrupt-disabled state (However, interrupts with the same priority level have their priorities resolved by fixed hardware priority.) Note 1: It is the number which summarized the number of interrupt requests for every group, and they are 257 factors as an interrupt request factor total.

INTERRUPT CONTROLLER (ICU) 5-332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 NEW_IMASK ILEVEL SBI# EI SBI SBIREQ IREQ IREQ IREQ IREQ IREQ IREQ Interrupt Vector Register (IVECT) Interrupt Request Mask Register (IMASK) External Interrupt (EI) request generated (maskable) IMASK compari- son System Break Interrupt (SBI) request generated (nonmaskable) Interrupt Controller (ICU) Interrupt Control Register SBI Control Register (SBICR) To the CPU core To the CPU core Priority resolved by interrupt priority levels set Priority resolved by fixed hardware priority Note 1: Interrupt control circuit indicates Interrupt request status register and Interrupt request mask register in each peripheral function. Internal Peripheral circuits Interrupt control circuit Interrupt request Interrupt request Interrupt request Interrupt control circuit Interrupt control circuit Edge Edge Edge Level Level Level (Note 1) Figure 5.1.1 Block Diagram of the Interrupt Controller

INTERRUPT CONTROLLER (ICU) 5-432192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The diagram below shows a register map associated with the Interrupt Controller (ICU). ICU Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0000 Interrupt Vector Register 5-5 (IVECT) H'0080 0002 (Use inhibited area) H'0080 0004 Interrupt Request Mask Register (Use inhibited area) 5-6 (IMASK) H'0080 0006 SBI Control Register (Use inhibited area) 5-7 (SBICR) (Use inhibited area) H'0080 0056 RAM Write Monitor Interrupt Control Register CAN1 Error Interrupt Control Register 5-8 (IRAMWRCR) (ICAN1ERCR) H'0080 0058 CAN1 Single-Shot Interrupt Control Register CAN1 Transmit/Receive Interrupt Control Register 5-8 (ICAN1SSCR) (ICAN1TRCR) H'0080 005A CAN0 Error Interrupt Control Register CAN0 Single-Shot Interrupt Control Register 5-8 (ICAN0ERCR) (ICAN0SSCR) H'0080 005C CAN0 Transmit/Receive Interrupt Control RegisterDRI Event Detection Interrupt Control Register 5-8 (ICAN0TRCR) (IDRIEVCR) H'0080 005E DRI Counter Interrupt Control Register DRI Transfer Interrupt Control Register 5-8 (IDRICNTCR) (IDRITRCR) H'0080 0060 CAN0 Transmit/Receive & Error Interrupt Control RegisterTML1 Input Interrupt Control Register 5-8 (ICAN0CR) (ITML1CR) H'0080 0062 (Use inhibited area) H'0080 0064 SIO4,5 Transmit/Receive Interrupt Control Register TOU1 Output Interrupt Control Register 5-8 (ISIO45CR) (ITOU1CR) H'0080 0066 TID1 Output Interrupt Control Register RTD Interrupt Control Register 5-8 (ITID1CR) (IRTDCR) H'0080 0068 SIO2,3 Transmit/Receive Interrupt Control Register DMA5–9 Interrupt Control Register 5-8 (ISIO23CR) (IDMA59CR) H'0080 006A TOU0 Output Interrupt Control Register TID0 Output Interrupt Control Register 5-8 (ITOU0CR) (ITID0CR) H'0080 006C A/D0 Conversion Interrupt Control Register SIO0 Transmit Interrupt Control Register 5-8 (IAD0CCR) (ISIO0TXCR) H'0080 006E SIO0 Receive Interrupt Control Register SIO1 Transmit Interrupt Control Register 5-8 (ISIO0RXCR) (ISIO1TXCR) H'0080 0070 SIO1 Receive Interrupt Control Register DMA0–4 Interrupt Control Register 5-8 (ISIO1RXCR) (IDMA04CR) H'0080 0072 MJT Output Interrupt Control Register 0 MJT Output Interrupt Control Register 1 5-8 (IMJTOCR0) (IMJTOCR1) H'0080 0074 MJT Output Interrupt Control Register 2 MJT Output Interrupt Control Register 3 5-8 (IMJTOCR2) (IMJTOCR3) H'0080 0076 MJT Output Interrupt Control Register 4 MJT Output Interrupt Control Register 5 5-8 (IMJTOCR4) (IMJTOCR5) H'0080 0078 MJT Output Interrupt Control Register 6 MJT Output Interrupt Control Register 7 5-8 (IMJTOCR6) (IMJTOCR7) H'0080 007A MJT Input Interrupt Control Register 0 MJT Input Interrupt Control Register 1 5-8 (IMJTICR0) (IMJTICR1) H'0080 007C MJT Input Interrupt Control Register 2 MJT Input Interrupt Control Register 3 5-8 (IMJTICR2) (IMJTICR3) H'0080 007E MJT Input Interrupt Control Register 4 CAN1 Transmit/Receive & Error Interrupt Control Register 5-8 (IMJTICR4) (ICAN1CR)

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5.2.1 Interrupt Vector Register

Interrupt Vector Register (IVECT) <Address: H’0080 0000> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 IVECT <Upon exiting reset: Undefined> b Bit Name Function R W 0−15 IVECT When an interrupt request is accepted, the 16-low-order R N 16 low-order bits of ICU vector table addressbits of the ICU vector table address for the accepted interrupt request source are stored in this register. Note:  This register must always be accessed in halfwords (2 bytes). (This is a read-only register.) The Interrupt Vector Register (IVECT) is used when an interrupt request is accepted to store the 16-low-order bits of the ICU vector table address for the accepted interrupt request source. Before this function can work, the ICU vector table (addresses H’0000 0094 through H’0000 013B) must have set in it the start addresses of interrupt handlers for each internal peripheral I/O. When an interrupt request is accepted, the 16-low-order bits of the ICU vector table address for the accepted interrupt request source are stored in the IVECT register. In the EIT handler, read the content of this IVECT register using the LDH instruc- tion to get the ICU vector table address. When the IVECT register is read, operations (1) to (4) below are automatically performed in hardware. (1) The interrupt priority level of the accepted interrupt request source (ILEVEL) is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.) (2) The interrupt request bit for the accepted interrupt request source is cleared (not cleared for level-recog- nized interrupt request sources). (3) The interrupt request (EI) to the CPU core is dropped. (4) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Notes:  Do not read the Interrupt Vector Register (IVECT) in the EIT handler unless interrupts are dis- abled (PSW register IE bit = "0"). In the EIT handler, furthermore, read the Interrupt Request Mask Register (IMASK) first before reading the IVECT register.  To reenable interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register (IVECT), execute the following processing in the order given: (1) Read the Interrupt Vector Register (IVECT) (2) Perform a read access to the SFR at least once (3) Perform a dumy access to the internal memory, SFR, etc. at least once (4) Enable interrupts (by setting the IE bit to "1")

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5.2.2 Interrupt Request Mask Register

Interrupt Request Mask Register (IMASK) <Address: H’0080 0004> 123456 b 7b0 IMASK 1110 0 0 0 0 <Upon exiting reset: H’07> b Bit Name Function R W 0–4 No function assigned. Fix to "0" 00 5–7 IMASK 000: Disable maskable interrupts R W Interrupt request mask bit 001: Accept interrupts with priority level 0 010: Accept interrupts with priority levels 0–1 011: Accept interrupts with priority levels 0–2 100: Accept interrupts with priority levels 0–3 101: Accept interrupts with priority levels 0–4 110: Accept interrupts with priority levels 0–5 111: Accept interrupts with priority levels 0–6 The Interrupt Request Mask Register (IMASK) is used to finally determine whether or not to accept an interrupt request after comparing its priority with the priority levels (Interrupt Control Register ILEVEL bits) that have been set for each interrupt request source. When the Interrupt Vector Register (IVECT) is read, the interrupt priority level of the accepted interrupt request source is set in this IMASK register as a new mask value. When any value is written to the IMASK register, operations (1) to (2) below are automatically performed in hardware. (1) The interrupt request (EI) to the CPU core is deasserted. (2) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Notes:  Do not write to the Interrupt Request Mask Register (IMASK) unless interrupts are disabled (PSW register IE bit = "0").  To reenable interrupts (by setting the IE bit to "1") after writing to the Interrupt Request Mask Register (IMASK), execute the following processing in the order given: (1) Write to the Interrupt Request Mask Register (IMASK) (2) Perform a read access to the SFR at least once (3) Perform a dumy access to the internal memory, SFR, etc. at least once (4) Enable interrupts (by setting the IE bit to "1") or (1) Write to the Interrupt Request Mask Register (IMASK) (2) Perform a dumy access to the internal memory, SFR, etc. twice or more (3) Issue four or more instructions (Note 1) (4) Enable interrupts (by setting the IE bit to "1") Note 1: Any instructions other than NOP that does not require clock cycles (one that is automati- cally inserted by the assembler for alignment adjustment: instruction code H'F000)

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5.2.3 SBI (System Break Interrupt) Control Register

SBI (System Break Interrupt) Control Register (SBICR) <Address: H’0080 0006> 123456 b 7b0 SBIREQ 00 0 0 0 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 0–6 No function assigned. Fix to "0" 00

7 SBIREQ 0: SBI not requested R (Note 1)

SBI request bit 1: SBI requested Note 1: This bit can only be cleared (see below) The System Break Interrupt (SBI) is an interrupt request generated by a falling edge on the SBI# signal input pin. When a falling edge on the SBI# signal input pin is detected and this bit is set to "1", a system break interrupt (SBI) request is generated to the CPU. This bit cannot be set to "1" in software, it can only be cleared. To clear this bit to "0", follow the procedure described below. 1. Write "1" to the SBI request bit. 2. Write "0" to the SBI request bit. Notes:  Unless this bit is set to "1", do not perform the above clearing operation.  If falling edge is inputted to SBI# pin again, system break is not occured while SBI request bit is set to "1."

INTERRUPT CONTROLLER (ICU) 5-832192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

5.2.4 Interrupt Control Registers

RAM Write Monitor Interrupt Control Register (IRAMWRCR) <Address: H’0080 0056> CAN1 Error Interrupt Control Register (ICAN1ERCR) <Address: H’0080 0057> CAN1 Single-Shot Interrupt Control Register (ICAN1SSCR) <Address: H’0080 0058> CAN1 Transmit/Receive Interrupt Control Register (ICAN1TRCR) <Address: H’0080 0059> CAN0 Error Interrupt Control Register (ICAN0ERCR) <Address: H’0080 005A> CAN0 Single-Shot Interrupt Control Register (ICAN0SSCR) <Address: H’0080 005B> CAN0 Transmit/Receive Interrupt Control Register (ICAN0TRCR) <Address: H’0080 005C> DRI Event Detection Interrupt Control Register (IDRIEVCR) <Address: H’0080 005D> DRI Counter Interrupt Control Register (IDRICNTCR) <Address: H’0080 005E> DRI Transfer Interrupt Control Register (IDRITRCR) <Address: H’0080 005F> CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) <Address: H’0080 0060> TML1 Input Interrupt Control Register (ITML1CR) <Address: H’0080 0061> SIO4,5 Transmit/Receive Interrupt Control Register (ISIO45CR) <Address: H’0080 0064> TOU1 Output Interrupt Control Register (ITOU1CR) <Address: H’0080 0065> TID1 Output Interrupt Control Register (ITID1CR) <Address: H’0080 0066> RTD Interrupt Control Register (IRTDCR) <Address: H’0080 0067> SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) <Address: H’0080 0068> DMA5–9 Interrupt Control Register (IDMA59CR) <Address: H’0080 0069> TOU0 Output Interrupt Control Register (ITOU0CR) <Address: H’0080 006A> TID0 Output Interrupt Control Register (ITID0CR) <Address: H’0080 006B> A/D0 Conversion Interrupt Control Register (IAD0CCR) <Address: H’0080 006C> SIO0 Transmit Interrupt Control Register (ISIO0TXCR) <Address: H’0080 006D> SIO0 Receive Interrupt Control Register (ISIO0RXCR) <Address: H’0080 006E> SIO1 Transmit Interrupt Control Register (ISIO1TXCR) <Address: H’0080 006F> SIO1 Receive Interrupt Control Register (ISIO1RXCR) <Address: H’0080 0070> DMA0–4 Interrupt Control Register (IDMA04CR) <Address: H’0080 0071> MJT Output Interrupt Control Register 0 (IMJTOCR0) <Address: H’0080 0072> MJT Output Interrupt Control Register 1 (IMJTOCR1) <Address: H’0080 0073> MJT Output Interrupt Control Register 2 (IMJTOCR2) <Address: H’0080 0074> MJT Output Interrupt Control Register 3 (IMJTOCR3) <Address: H’0080 0075> MJT Output Interrupt Control Register 4 (IMJTOCR4) <Address: H’0080 0076> MJT Output Interrupt Control Register 5 (IMJTOCR5) <Address: H’0080 0077> MJT Output Interrupt Control Register 6 (IMJTOCR6) <Address: H’0080 0078> MJT Output Interrupt Control Register 7 (IMJTOCR7) <Address: H’0080 0079> MJT Input Interrupt Control Register 0 (IMJTICR0) <Address: H’0080 007A> MJT Input Interrupt Control Register 1 (IMJTICR1) <Address: H’0080 007B> MJT Input Interrupt Control Register 2 (IMJTICR2) <Address: H’0080 007C> MJT Input Interrupt Control Register 3 (IMJTICR3) <Address: H’0080 007D> MJT Input Interrupt Control Register 4 (IMJTICR4) <Address: H’0080 007E> CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR) <Address: H’0080 007F>

INTERRUPT CONTROLLER (ICU) 5-932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 9 1 01 11 21 31 4 b 1 5 )(b8 123456 b 7b0 ILEVELIREQ 0 1110 0 0 0 <Upon exiting reset: H’07> b Bit Name Function R W 0–2 No function assigned. Fix to "0" 00 (8–10)

3 IREQ <When edge-recognized> R W

(11) Interrupt request bit At read 0: Interrupt not requested 1: Interrupt requested At write 0: Clear interrupt request 1: Generate interrupt request <When level-recognized> R 0 At read 0: Interrupt not requested 1: Interrupt requested 4 No function assigned. Fix to "0" 00 (12) 5–7 ILEVEL 000: Interrupt priority level 0 R W (13–15) Interrupt priority level bits 001: Interrupt priority level 1 010: Interrupt priority level 2 011: Interrupt priority level 3 100: Interrupt priority level 4 101: Interrupt priority level 5 110: Interrupt priority level 6 111: Interrupt priority level 7 (interrupt disabled) (1) IREQ (Interrupt Request) bit (Bit 3 or 11) When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Request) bit is set to "1." This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for level-recognized interrupt request sources). Also, when this bit is set by an edge-recognized interrupt re- quest generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not cleared in the case of level-recognized interrupt request). If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Register (IVECT) at the same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority. Note:  External Interrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External Interrupt (EI) to the CPU core can only be deasserted by the following operation: (1) Reset (2) IVECT register read (3) Write to the IMASK register

INTERRUPT CONTROLLER (ICU) 5-1032192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 5.2.1 Configuration of the Interrupt Control Register (Edge-recognized Type) Figure 5.2.2 Configuration of the Interrupt Control Register (Level-recognized Type) (2) ILEVEL (Interrupt Priority Level) (Bits 5–7 or bits 13–15) These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set these bits to ‘111’ to disable or any value ‘000’ through ‘110’ to enable the interrupt from some internal peripheral I/O. When an interrupt occurs, the Interrupt Controller resolves priority between this interrupt and other interrupt sources based on ILEVEL settings and finally compares priority with the IMASK value to determine whether to forward an EI request to the CPU or keep the interrupt request pending. The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts are accepted. Table 5.2.1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 (ILEVEL = "000") Accepted when IMASK is 1–7 1 (ILEVEL = "001") Accepted when IMASK is 2–7 2 (ILEVEL = "010") Accepted when IMASK is 3–7 3 (ILEVEL = "011") Accepted when IMASK is 4–7 4 (ILEVEL = "100") Accepted when IMASK is 5–7 5 (ILEVEL = "101") Accepted when IMASK is 6–7 6 (ILEVEL = "110") Accepted when IMASK is 7 7 (ILEVEL = "111") Not accepted (interrupts disabled) Interrupt request from each internal peripheral I/O Interrupt enabled ILEVEL (levels 0-7) Data bus Bits 5-7 or bits 13-15 F/F Set Set/clear IREQ Interrupt priority resolving circuit F/F Reset IVECT read IMASK write Clear To the CPU core Bit 3 or bit 11 Set EI Group interrupt request from each internal peripheral I/O Interrupt enabled Bit 3 or bit 11Data bus Bits 5-7 or bits 13-15 Read IREQ Read-only circuit ILEVEL (levels 0-7) Group interrupt Interrupt priority resolving circuit F/F Clear To the CPU coreSet EI Reset IVECT read IMASK write

INTERRUPT CONTROLLER (ICU) 5-1132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

5.3 Interrupt Request Sources in Internal Peripheral I/O

The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial interface, A/D converter, RTD, CAN, DRI and RAM write monitor. For details about these interrupts, see each section in which the relevant internal peripheral I/O is described. Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O Interrupt Request Sources Contents Number of ICU Type of Input Input SourcesSource ( Note 1) MJT input interrupt 4 MJT input interrupt group 4 (TIN3–TIN6 inputs) 4 Level-recognized MJT input interrupt 3 MJT input interrupt group 3 (TIN20–TIN27 inputs) 8 Level-recognized MJT input interrupt 2 MJT input interrupt group 2 (TIN16–TIN19 inputs) 4 Level-recognized MJT input interrupt 1 MJT input interrupt group 1 (TIN0 input) 1 Level-recognized MJT input interrupt 0 MJT input interrupt group 0 (TIN7–TIN11 inputs) 5 Level-recognized MJT output interrupt 7 MJT output interrupt group 7 (TMS0, TMS1 output) 2 Level-recognized MJT output interrupt 6 MJT output interrupt group 6 (TOP8, TOP9 output) 2 Level-recognized MJT output interrupt 5 MJT output interrupt group 5 (TOP10 output) 1 Edge-recognized MJT output interrupt 4 MJT output interrupt group 4 (TIO4–TIO7 outputs) 4 Level-recognized MJT output interrupt 3 MJT output interrupt group 3 (TIO8, TIO9 outputs) 2 Level-recognized MJT output interrupt 2 MJT output interrupt group 2 (TOP0–TOP5 outputs) 6 Level-recognized MJT output interrupt 1 MJT output interrupt group 1 (TOP6, TOP7 outputs) 2 Level-recognized MJT output interrupt 0 MJT output interrupt group 0 (TIO0–TIO3 outputs) 4 Level-recognized DMA0–4 interrupt DMA0–4 transfer-completed 5 Level-recognized SIO1 receive interrupt SIO1 reception-completed or receive error interrupt 1 Edge-recognized SIO1 transmit interrupt SIO1 transmission-completed or transmit buffer empty interrupt 1Edge-recognized SIO0 receive interrupt SIO0 reception-completed or receive error interrupt 1 Edge-recognized SIO0 transmit interrupt SIO0 transmission-completed or transmit buffer empty interrupt 1Edge-recognized A/D0 conversion interrupt A/D0 conversion (single mode, scan single-shot mode, or 1 cycle 1Edge-recognized of scan continuous mode) completed and comparate-completed TID0 output interrupt TID0 output 1 Edge-recognized TOU0 output interrupt TOU0_0–TOU0_7 outputs 8 Level-recognized DMA5–9 interrupt DMA5–9 transfer-completed 5 Level-recognized SIO2,3 transmit/receive interrupt SIO2,3 reception-completed or receive error interrupt, 4 Level-recognized transmission-completed or transmit buffer empty interrupt RTD interrupt RTD interrupt generation command 1 Edge-recognized TID1 output interrupt TID1 output 1 Edge-recognized TOU1 output interrupt TOU1_0–TOU1_7 outputs 8 Level-recognized SIO4,5 transmit/receive interrupt SIO4,5 reception-completed or receive error interrupt, 4 Level-recognized transmission-completed or transmit buffer empty interrupt TML1 input interrupt TML1 input (TIN30–TIN33 inputs) 4 Level-recognized CAN0 transmit/receive & errorCAN0 transmission or reception completed, CAN0 bus error, 67Level-recognized interrupt CAN0 error passive, CAN0 bus-off, CAN0 single-shot CAN1 transmit/receive & errorCAN1 transmission or reception completed, CAN1 bus error, 67Level-recognized interrupt CAN1 error passive, CAN1 bus-off, CAN1 single-shot DRI transfer interrupt DRI address counter 0 transfer-completed, 5 Level-recognized DRI address counter 1 transfer-completed, overrun error, latch enable error and DRI transfer counter underflow DRI counter interrupt DEC0–DEC4 underflow 5 Level-recognized DRI event detection interrupt DIN0–DIN5 event detected 6 Level-recognized CAN0 transmit/receive interrupt CAN0 transmission-completed, CAN0 reception-completed 32 Level-recognized CAN0 single-shot interrupt CAN0 single-shot 32 Level-recognized CAN0 error interrupt CAN0 bus error, CAN0 error passive, CAN0 bus off 3 Level-recognized CAN1 transmit/receive interrupt CAN1 transmission-completed, CAN1 reception-completed 32 Level-recognized CAN1 single-shot interrupt CAN1 single-shot 32 Level-recognized CAN1 error interrupt CAN1 bus error, CAN1 error passive, CAN1 bus off 3 Level-recognized RAM write monitor interrupt RAM write 16 Level-recognized Note 1: ICU type of input source  Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU.  Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held "L." For this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software.

INTERRUPT CONTROLLER (ICU) 5-1232192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The 40-source interrupt requests are assigned the following vector table addresses. The interrupt request sources are also assigned the following hardware fixed priority levels. Table 5.4.1 ICU Vector Table Priority Interrupt Request Source ICU Vector Table Address Number of ICU Type of Input Input Source Source (Note 1) High MJT input interrupt 4 H'0000 0094 – H'0000 0097 4 Level-recognized MJT input interrupt 3 H'0000 0098 – H'0000 009B 8 Level-recognized MJT input interrupt 2 H'0000 009C – H'0000 009F 4 Level-recognized MJT input interrupt 1 H'0000 00A0 – H'0000 00A3 1 Level-recognized MJT input interrupt 0 H'0000 00A4 – H'0000 00A7 5 Level-recognized MJT output interrupt 7 H'0000 00A8 – H'0000 00AB 2 Level-recognized MJT output interrupt 6 H'0000 00AC – H'0000 00AF 2 Level-recognized MJT output interrupt 5 H'0000 00B0 – H'0000 00B3 1 Edge-recognized MJT output interrupt 4 H'0000 00B4 – H'0000 00B7 4 Level-recognized MJT output interrupt 3 H'0000 00B8 – H'0000 00BB 2 Level-recognized MJT output interrupt 2 H'0000 00BC – H'0000 00BF 6 Level-recognized MJT output interrupt 1 H'0000 00C0 – H'0000 00C3 2 Level-recognized MJT output interrupt 0 H'0000 00C4 – H'0000 00C7 4 Level-recognized DMA0–4 interrupt H'0000 00C8 – H'0000 00CB 5 Level-recognized SIO1 receive interrupt H'0000 00CC – H'0000 00CF 1 Edge-recognized SIO1 transmit interrupt H'0000 00D0 – H'0000 00D3 1 Edge-recognized SIO0 receive interrupt H'0000 00D4 – H'0000 00D7 1 Edge-recognized SIO0 transmit interrupt H'0000 00D8 – H'0000 00DB 1 Edge-recognized A/D0 conversion interrupt H'0000 00DC – H'0000 00DF 1 Edge-recognized TID0 output interrupt H'0000 00E0 – H'0000 00E3 1 Edge-recognized TOU0 output interrupt H'0000 00E4 – H'0000 00E7 8 Level-recognized DMA5–9 interrupt H'0000 00E8 – H'0000 00EB 5 Level-recognized SIO2,3 transmit/receive interrupt H'0000 00EC – H'0000 00EF 4 Level-recognized RTD interrupt H'0000 00F0 – H'0000 00F3 1 Edge-recognized TID1 output interrupt H'0000 00F4 – H'0000 00F7 1 Edge-recognized TOU1 output interrupt H'0000 00F8 – H'0000 00FB 8 Level-recognized SIO4,5 transmit/receive interrupt H'0000 00FC – H'0000 00FF 4 Level-recognized TML1 input interrupt H'0000 0108 – H'0000 010B 4 Level-recognized CAN0 transmit/receive & error interrupt H'0000 010C – H'0000 010F 67 Level-recognized CAN1 transmit/receive & error interrupt H'0000 0110 – H'0000 0113 67 Level-recognized DRI transfer interrupt H'0000 0114 – H'0000 0117 5 Level-recognized DRI counter interrupt H'0000 0118 – H'0000 011B 5 Level-recognized DRI event detection interrupt H'0000 011C – H'0000 011F 6 Level-recognized CAN0 transmit/receive interrupt H'0000 0120 – H'0000 0123 32 Level-recognized CAN0 single-shot interrupt H'0000 0124 – H'0000 0127 32 Level-recognized CAN0 error interrupt H'0000 0128 – H'0000 012B 3 Level-recognized CAN1 transmit/receive interrupt H'0000 012C – H'0000 012F 32 Level-recognized CAN1single-shot interrupt H'0000 0130 – H'0000 0133 32 Level-recognized CAN1 error interrupt H'0000 0134 – H'0000 0137 3 Level-recognized Low RAM write monitor interrupt H'0000 0138 – H'0000 013B 16 Level-recognized Note 1: ICU type of input source  Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU.  Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held low. For this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software.

INTERRUPT CONTROLLER (ICU) 5-1332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 5.5.1 Example of Priority Resolution when Accepting Interrupt Requests Table 5.5.1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 (ILEVEL = "000") Accepted when IMASK is 1–7 1 (ILEVEL = "001") Accepted when IMASK is 2–7 2 (ILEVEL = "010") Accepted when IMASK is 3–7 3 (ILEVEL = "011") Accepted when IMASK is 4–7 4 (ILEVEL = "100") Accepted when IMASK is 5–7 5 (ILEVEL = "101") Accepted when IMASK is 6–7 6 (ILEVEL = "110") Accepted when IMASK is 7 7 (ILEVEL = "111") Not accepted (interrupts disabled)

5.5.1 Acceptance of Internal Peripheral I/O Interrupts

An interrupt request from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set in the Interrupt Control Register and the IMASK value of the Interrupt Request Mask Register. If its priority is higher than the IMASK value, the interrupt request is accepted. However, if two or more interrupt requests occur simultaneously, the Interrupt Controller resolves priority between these interrupt requests fol- lowing the procedure described below. 1) The ILEVEL values set in the Interrupt Control Registers for the respective internal peripheral I/Os are compared with each other. 2) If the ILEVEL values are the same, priorities are resolved according to the predetermined hardware priority. 3) The ILEVEL and IMASK values are compared. If two or more interrupt requests occur simultaneously, the Interrupt Controller first compares their priority levels set in each Interrupt Control Register’s ILEVEL bit to select an interrupt request that has the highest priority. If the interrupt requests have the same ILEVEL value, their priorities are resolved according to the hardware fixed priority. The interrupt request thus selected has its ILEVEL value compared with the IMASK value and if its priority is higher than the IMASK value, the Interrupt Controller sends an EI request to the CPU. Interrupt requests may be masked by setting the Interrupt Request Mask Register and the Interrupt Control Register’s ILEVEL bit (disabled at level 7) provided for each internal peripheral I/O and the PSW register IE bit. Level (ILEVEL) Resolve priority according to hardware priority Compare with IMASK value TIN3 input interrupt request (MJT input interrupt 4) TIO5 output interrupt request (MJT output interrupt 4) TOP8 output interrupt request (MJT output interrupt 6) SIO0 transmit interrupt request DMA1 interrupt request (DMA0-4 interrupt) A/D0 conversion interrupt request (ILEVEL settings) Level 3 Level 4 Level 5 Level 3 Level 1 Level 3 Not requested Requested Requested Requested Requested Requested Hardware fixed priority Accept interrupt if PSW register IE bit = 1 Level 3 Level 3 Level 3 Can be accepted when IMASK = 4-7 1) 2) 3)

INTERRUPT CONTROLLER (ICU) 5-1432192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers

(1) Branching to the interrupt handler Upon accepting an interrupt request, the CPU branches to the EIT vector entry after performing the hard- ware preprocessing as described in Section 4.3, “EIT Processing Procedure.” The EIT vector entry for External Interrupt (EI) is located at the address H’0000 0080. This address is where the instruction (not the jump address itself) for branching to the beginning of the interrupt handler routine for external interrupt requests is written. (2) Processing in the External Interrupt (EI) handler A typical operation of the External Interrupt (EI) handler (for interrupts from internal peripheral I/O) is shown in Figure 5.5.2. [1] Saving each register to the stack Save the BPC, PSW and general-purpose registers to the stack. Also, save the accumulator and FPSR register to the stack as necessary. [2] Reading the Interrupt Request Mask Register (IMASK) and saving to the stack Read the Interrupt Request Mask Register and save its content to the stack. [3] Reading the Interrupt Vector Register (IVECT) Read the Interrupt Vector Register. This register holds the 16 low-order address bits of the ICU vector table for the accepted interrupt request source that was stored in it when accepting an interrupt request. When the Interrupt Vector Register is read, the following processing is automatically performed in hardware:  The interrupt priority level of the accepted interrupt request (ILEVEL) is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.)  The accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources).  The interrupt request (EI) to the CPU core is dropped.  The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). [4] Reading and overwriting the Interrupt Request Mask Register (IMASK) Read the Interrupt Request Mask Register and overwrite it with the read value. This write to the IMASK register causes the following processing to be automatically performed in hardware:  The interrupt request (EI) to the CPU core is dropped.  The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). [5] Reading the ICU vector table Read the ICU vector table for the accepted interrupt request source. The relevant ICU vector table address can be obtained by zero-extending the content of the Interrupt Vector Register that was read in [3] (i.e., the 16 low-order address bits of the ICU vector table for the accepted interrupt request source). The ICU vector table must have set in it the start address of the interrupt handler for the interrupt request source concerned.) [6] Enabling multiple interrupts To enable another higher priority interrupt while processing the accepted interrupt (i.e., enabling mul- tiple interrupts), set the PSW register IE bit to "1." Notes:  There are precautions to be taken when reenabling interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register (IVECT). For details, see the Section 5.2.1, "Interrupt Vector Register (IVECT)." The precautions apply to the Process [4], therefore, other processes are not required to add.  There are precautions to be taken when reenabling interrupts (by setting the IE bit to "1") after writing to the Interrupt Request Mask Register (IMASK). For details, see the Section 5.2.2, "Interrupt Request Mask Register (IMASK)."

INTERRUPT CONTROLLER (ICU) 5-1532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 [7] Branching to the internal peripheral I/O interrupt handler Branch to the start address of the interrupt handler that was read out in [5]. [8] Processing in the internal peripheral I/O interrupt handler [9] Disabling interrupts Clear the PSW register IE bit to "0" to disable interrupts. [10] Restoring the Interrupt Request Mask Register (IMASK) Restore the Interrupt Request Mask Register that was saved to the stack in [2]. [11] Restoring registers from the stack Restore the registers that were saved to the stack in [1]. [12] Completion of external interrupt processing Execute the RTE instruction to complete the external interrupt processing. The program returns to the state in which it was before the interrupt request currently being processed was accepted. (3) Identifying the source of the interrupt request generated If any internal peripheral I/O has two or more interrupt request sources, check the Interrupt Request Status Register provided for each internal peripheral I/O to identify the source of the interrupt request generated. (4) Enabling multiple interrupts To enable multiple interrupts in the interrupt handler, set the PSW register IE (Interrupt Enable) bit to enable interrupt requests to be accepted. However, before writing "1" to the IE bit, be sure to save each register (BPC, PSW, general-purpose registers and IMASK) to the stack. Note:  Before enabling multiple interrupts, read the Interrupt Vector Register (IVECT) and then the ICU vector table, as shown in Figure 5.5.2, “Typical Handler Operation for Interrupts from Internal Peripheral I/O.”

INTERRUPT CONTROLLER (ICU) 5-1632192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O H'0000 0080 BRA instruction Read Interrupt Vector Register (IVECT) Read ICU vector table Branch to the interrupt handler for each internal peripheral I/O RTE H'0080 0004 H'0000 0094 H'0000 013B Interrupt handler EI (External Interrupt) handler EI (External Interrupt) vector entry Interrupt handler start address Program being executed Interrupt generated IVECT Save BPC to the stack Save PSW to the stack Save general-purpose registers to the stack Restore BPC from the stack Restore PSW from the stack Restore general-purpose registers from the stack Read and save Interrupt Request Mask Register (IMASK) to the stack IMASK H'0080 0000 Set PSW register IE bit to 1 Clear PSW register IE bit to 0 Restore Interrupt Request Mask Register (IMASK) from the stack [1] [2] [3] [5] [7] [8] [9] [6] [10] [11] ICU vector table (Note 1) (Note 1) Hardware preprocessing when EIT is accepted Hardware postprocessing when RTE instruction is executed Read and overwrite Interrupt Request Mask Register (IMASK) [4] [12] (Note 2) (Note 2) (Note 3) (Note 4) (Note 3) (Note 2) Interrupt handler [1] to [12]: Processing of EI by interrupt handler Note 1: For operations at EIT acceptance and return from EIT, also see Section 4.3, "EIT Processing Procedure." Note 2: Do not read the Interrupt Vector Register (IVECT) or write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts are disabled (PSW register IE bit = 0). Note 3: To enable multiple interrupts, execute processing in [6] and [9]. Note 4: There are precautions to be taken when reenabling interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register (IVECT). For details, see the Section 5.2.1, "Interrupt Vector Register (IVECT)." The precautions apply to the Process [4], therefore, other processes are not required to add. Also, there are precautions to be taken when reenabling interrupts (by setting the IE bit to "1") after writing to the Interrupt Request Mask Register (IMASK). For details, see the Section 5.2.2, "Interrupt Request Mask Register (IMASK)."

INTERRUPT CONTROLLER (ICU) 5-1732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

5.6 Description of System Break Interrupt (SBI) Operation

5.6.1 Acceptance of SBI

System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt is accepted anytime upon detection of a falling edge on the SBI# signal input pin no matter how the PSW register IE bit is set, and cannot be masked. If falling edge is inputted to SBI# pin again, system break is not occured while SBI request bit is set to "1."

5.6.2 SBI Processing by Handler

When the system break interrupt generated has been serviced, shut down or reset the system without return- ing to the program that was being executed when the interrupt occurred. Figure 5.6.1 Typical SBI Operation H'0000 0010 BRA instruction SBI (System Break Interrupt) handler SBI (System Break Interrupt) vector entry Program being executed SBI generated Processing to shut down the system (Note 1) Note 1: Do not return to the program that was being executed when the interrupt occurred. Shut down or reset the system

INTERRUPT CONTROLLER (ICU) 5-1832192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 This page is blank for reasons of layout.

6.1 Outline of the Internal Memory

6.2 Internal RAM

6.3 Internal RAM Protect Function

6.4 Internal Flash Memory

6.5 Registers Associated with the Internal

6.6 Programming the Internal Flash Memory

6.7 Virtual Flash Emulation Function

6.8 Connecting to A Serial Programmer (CSIO

Mode)

6.9 Connecting to A Serial Programmer (UART

Mode)

6.10 Internal Flash Memory Protect Function

6.11 Notes on the Internal RAM

6.12 Notes on the Internal Flash Memory

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The 32192/32195/32196 internally contains the following types of memory:

• 176-Kbyte, 32-Kbyte, 64-Kbyte RAM
• 1-Mbyte (1024 Kbytes) and 512-Kbyte flash memory

Specifications of the internal RAM are shown below. Table 6.2.1 Specifications of the Internal RAM Item Specification Size M32192F8 : 176 Kbytes M32195F4 : 32 Kbytes M32196F8 : 64 Kbytes Location address M32192F8 : H’0080 4000 to H’0082 FFFF M32195F4 : H'0080 4000 to H'0080 BFFF M32196F8 : H’0080 4000 to H’0081 3FFF Wait insertion Operates with zero wait states Internal bus connection Connected by 32-bit bus Dual port By using the Real-Time Debugger (RTD), data can be read (monitored) or written to any area of the internal RAM via serial communication from external devices independently of the CPU. (See Chapter 15, “Real-Time Debugger.”) Note: • The value of RAM is undefined immediately after reset is deasserted during power-on (the power-on in which VDDE also rises at GND). However, in the RAM backup mode (Power to VDDE only), the value of before deassertion of reset is held only in the RAM backup area. This function monitors writes to the internal RAM. Writes to the RAM can be disabled in 16-Kbyte units for area of H'0080 4000 to H'0084 3FFF. And if a write area set to disable is accessed for write, an interrupt can be generated. Note: • The internal resources that are likely to access the internal RAM for write include six modules: CPU, DMA, SDI (tool), NBD, RTD, and DRI. Of these, the RTD and DRI are not subject to the RAM protect function, so that write accesses made to the internal RAM by the RTD or DRI cannot be detected.

6-332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The diagram below shows the areas in 16-Kbyte units of the internal RAM that can individually be disabled against write by the RAM protect function. Table 6.3.1 Definition of the Write Disabled Area Area Target address M32192F8 M32195F4 M32196F8 Area 0 H'0080 4000 - H'0080 7FFF Area 1 H'0080 8000 − H'0080 BFFF Area 2 H'0080 C000 − H'0080 FFFF Area 3 H'0081 0000 − H'0081 3FFF Area 4 H'0081 4000 − H'0081 7FFF Area 5 H'0081 8000 − H'0081 BFFF Area 6 H'0081 C000 − H'0081 FFFF Area 7 H'0082 0000 − H'0082 3FFF Area 8 H'0082 4000 − H'0082 7FFF Area 9 H'0082 8000 − H'0082 BFFF Area 10 H'0082 C000 − H'0082 FFFF Area 11 H'0083 0000 − H'0083 3FFF Area 12 H'0083 4000 − H'0083 7FFF Area 13 H'0083 8000 − H'0083 BFFF Area 14 H'0083 C000 − H'0083 FFFF Area 15 H'0084 0000 − H'0084 3FFF A register map associated with the internal RAM protect function is shown below. Internal RAM Protect Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0530 RAM Write Monitor Interrupt Status Register 6-4 (RAMWRIST) H'0080 0532 (Use inhibited area) H'0080 0534 RAM Write Source Status Register 6-5 (RAMWRFST) H'0080 0536 (Use inhibited area) H'0080 0538 RAM Write Disable Control Register 6-6 (RAMWRCNT) H'0080 053A (Use inhibited area) H'0080 053C (Use inhibited area) RAM Write Disable Protect Register 6-7 (RAMWRPROT)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 <Upon exiting reset: H'0000> b Bit Name Function R W

0 RAMWRIST0 0: Area 0 interrupt not request R (Note 1)

(Area 0 RAM write monitor interrupt status bit) 1: Area 0 interrupt requested

1 RAMWRIST1 0: Area 1 interrupt not request R (Note 1)

(Area 1 RAM write monitor interrupt status bit) 1: Area 1 interrupt requested

2 RAMWRIST2 0: Area 2 interrupt not request R (Note 1)

(Area 2 RAM write monitor interrupt status bit) 1: Area 2 interrupt requested

3 RAMWRIST3 0: Area 3 interrupt not request R (Note 1)

(Area 3 RAM write monitor interrupt status bit) 1: Area 3 interrupt requested

4 RAMWRIST4 0: Area 4 interrupt not request R (Note 1)

(Area 4 RAM write monitor interrupt status bit) 1: Area 4 interrupt requested

5 RAMWRIST5 0: Area 5 interrupt not request R (Note 1)

(Area 5 RAM write monitor interrupt status bit) 1: Area 5 interrupt requested

6 RAMWRIST6 0: Area 6 interrupt not request R (Note 1)

(Area 6 RAM write monitor interrupt status bit) 1: Area 6 interrupt requested

7 RAMWRIST7 0: Area 7 interrupt not request R (Note 1)

(Area 7 RAM write monitor interrupt status bit) 1: Area 7 interrupt requested

8 RAMWRIST8 0: Area 8 interrupt not request R (Note 1)

(Area 8 RAM write monitor interrupt status bit) 1: Area 8 interrupt requested

9 RAMWRIST9 0: Area 9 interrupt not request R (Note 1)

(Area 9 RAM write monitor interrupt status bit) 1: Area 9 interrupt requested

10 RAMWRIST10 0: Area 10 interrupt not request R (Note 1)

(Area 10 RAM write monitor interrupt status bit) 1: Area 10 interrupt requested

11 RAMWRIST11 0: Area 11 interrupt not request R (Note 1)

(Area 11 RAM write monitor interrupt status bit) 1: Area 11 interrupt requested

12 RAMWRIST12 0: Area 12 interrupt not request R (Note 1)

(Area 12 RAM write monitor interrupt status bit) 1: Area 12 interrupt requested

13 RAMWRIST13 0: Area 13 interrupt not request R (Note 1)

(Area 13 RAM write monitor interrupt status bit) 1: Area 13 interrupt requested

14 RAMWRIST14 0: Area 14 interrupt not request R (Note 1)

(Area 14 RAM write monitor interrupt status bit) 1: Area 14 interrupt requested

15 RAMWRIST15 0: Area 15 interrupt not request R (Note 1)

(Area 15 RAM write monitor interrupt status bit) 1: Area 15 interrupt requested Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Note: • This register must always be accessed in halfwords. If the CPU, DMA, SDI (tool), or NBD attempted to write to any area that is “disabled against write” by the RAM Write Disable Control Register, the corresponding bit in this register is set to "1." The bit is cleared by writing a "0" in software. When writing to this register, be sure to write a "0" for the bits to be cleared and a "1" for all other bits. Writing a "1" to any bit in this register has no effect, so the bit retains the value it had before the write. b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 RAMWRIST0 RAMWRIST1 RAMWRIST3 RAMWRIST4 RAMWRIST5 RAMWRIST8 0000000000000000 RAMWRIST15RAMWRIST14RAMWRIST13RAMWRIST12RAMWRIST11RAMWRIST10RAMWRIST9RAMWRIST7RAMWRIST6RAMWRIST2 RAM Write Monitor Interrupt Status Register (RAMWRIST) <Address: H’0080 0530>

6-532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 RAM Write Source Status Register (RAMWRFST) <Address: H'0080 0534> <Upon exiting reset: H'0000> b Bit Name Function R W

0 RAMWRFST0 0: Write to area 0 by DMA R (Note 1)

(Area 0 RAM write source status bit) 1: Write to area 0 by CPU, SDI, or NBD

1 RAMWRFST1 0: Write to area 1 by DMA R (Note 1)

(Area 1 RAM write source status bit) 1: Write to area 1 by CPU, SDI, or NBD

2 RAMWRFST2 0: Write to area 2 by DMA R (Note 1)

(Area 2 RAM write source status bit) 1: Write to area 2 by CPU, SDI, or NBD

3 RAMWRFST3 0: Write to area 3 by DMA R (Note 1)

(Area 3 RAM write source status bit) 1: Write to area 3 by CPU, SDI, or NBD

4 RAMWRFST4 0: Write to area 4 by DMA R (Note 1)

(Area 4 RAM write source status bit) 1: Write to area 4 by CPU, SDI, or NBD

5 RAMWRFST5 0: Write to area 5 by DMA R (Note 1)

(Area 5 RAM write source status bit) 1: Write to area 5 by CPU, SDI, or NBD

6 RAMWRFST6 0: Write to area 6 by DMA R (Note 1)

(Area 6 RAM write source status bit) 1: Write to area 6 by CPU, SDI, or NBD

7 RAMWRFST7 0: Write to area 7 by DMA R (Note 1)

(Area 7 RAM write source status bit) 1: Write to area 7 by CPU, SDI, or NBD

8 RAMWRFST8 0: Write to area 8 by DMA R (Note 1)

(Area 8 RAM write source status bit) 1: Write to area 8 by CPU, SDI, or NBD

9 RAMWRFST9 0: Write to area 9 by DMA R (Note 1)

(Area 9 RAM write source status bit) 1: Write to area 9 by CPU, SDI, or NBD

10 RAMWRFST10 0: Write to area 10 by DMA R (Note 1)

(Area 10 RAM write source status bit) 1: Write to area 10 by CPU, SDI, or NBD

11 RAMWRFST11 0: Write to area 11 by DMA R (Note 1)

(Area 11 RAM write source status bit) 1: Write to area 11 by CPU, SDI, or NBD

12 RAMWRFST12 0: Write to area 12 by DMA R (Note 1)

(Area 12 RAM write source status bit) 1: Write to area 12 by CPU, SDI, or NBD

13 RAMWRFST13 0: Write to area 13 by DMA R (Note 1)

(Area 13 RAM write source status bit) 1: Write to area 13 by CPU, SDI, or NBD

14 RAMWRFST14 0: Write to area 14 by DMA R (Note 1)

(Area 14 RAM write source status bit) 1: Write to area 14 by CPU, SDI, or NBD

15 RAMWRFST15 0: Write to area 15 by DMA R (Note 1)

(Area 15 RAM write source status bit) 1: Write to area 15 by CPU, SDI, or NBD Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. If the CPU, SDI(tool), or NBD attempted to access any area for write that is “disabled against write” by the RAM Write Disable Control Register, the corresponding bit in this register is set to "1." After setting the bit to "1," the bit is not cleared to "0" if a DMA write access occurred. The bit is cleared by writing a "0" in software. Writing a "1" to any bit in this register has no effect, so the bit retains the value it had before the write. b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 RAMWRFST0 RAMWRFST1 RAMWRFST3 RAMWRFST4 RAMWRFST5 RAMWRFST8 0000000000000000 RAMWRFST15RAMWRFST14RAMWRFST13RAMWRFST12RAMWRFST11RAMWRFST10RAMWRFST9RAMWRFST7RAMWRFST6RAMWRFST2

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 <Upon exiting reset: H'0000> b Bit Name Function R W

0 RAMWRCNT0 0: Enable write to area 0 R W

(Area 0 RAM write disable control bit) 1: Disable write to area 0

1 RAMWRCNT1 0: Enable write to area 1 R W

(Area 1 RAM write disable control bit) 1: Disable write to area 1

2 RAMWRCNT2 0: Enable write to area 2 R W

(Area 2 RAM write disable control bit) 1: Disable write to area 2

3 RAMWRCNT3 0: Enable write to area 3 R W

(Area 3 RAM write disable control bit) 1: Disable write to area 3

4 RAMWRCNT4 0: Enable write to area 4 R W

(Area 4 RAM write disable control bit) 1: Disable write to area 4

5 RAMWRCNT5 0: Enable write to area 5 R W

(Area 5 RAM write disable control bit) 1: Disable write to area 5

6 RAMWRCNT6 0: Enable write to area 6 R W

(Area 6 RAM write disable control bit) 1: Disable write to area 6

7 RAMWRCNT7 0: Enable write to area 7 R W

(Area 7 RAM write disable control bit) 1: Disable write to area 7

8 RAMWRCNT8 0: Enable write to area 8 R W

(Area 8 RAM write disable control bit) 1: Disable write to area 8

9 RAMWRCNT9 0: Enable write to area 9 R W

(Area 9 RAM write disable control bit) 1: Disable write to area 9

10 RAMWRCNT10 0: Enable write to area 10 R W

(Area 10 RAM write disable control bit) 1: Disable write to area 10

11 RAMWRCNT11 0: Enable write to area 11 R W

(Area 11 RAM write disable control bit) 1: Disable write to area 11

12 RAMWRCNT12 0: Enable write to area 12 R W

(Area 12 RAM write disable control bit) 1: Disable write to area 12

13 RAMWRCNT13 0: Enable write to area 13 R W

(Area 13 RAM write disable control bit) 1: Disable write to area 13

14 RAMWRCNT14 0: Enable write to area 14 R W

(Area 14 RAM write disable control bit) 1: Disable write to area 14

15 RAMWRCNT15 0: Enable write to area 15 R W

(Area 15 RAM write disable control bit) 1: Disable write to area 15 This register controls accesses for write to the RAM by enabling or disabling the access. Controlled by this register are the accesses made by the CPU, DMA, SDI (tool), and NBD. If one of these modules attempted to access any area for write that is disabled against write, the corresponding RAM write monitor interrupt status is set to "1," with no data actually written to the RAM. Before this register can be rewritten, the RAMWRCNTPRO bit in the RAM Write Disable Protect Register must be "0." b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 RAMWRCNT0 RAMWRCNT1 RAMWRCNT3 RAMWRCNT4 RAMWRCNT5 RAMWRCNT8 0000000000000000 RAMWRCNT15RAMWRCNT14RAMWRCNT13RAMWRCNT12RAMWRCNT11RAMWRCNT10RAMWRCNT9RAMWRCNT7RAMWRCNT6RAMWRCNT2 RAM Write Disable Control Register (RAMWRCNT) <Address: H’0080 0538>

6-732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 RAM Write Disable Protect Register (RAMWRPROT) <Address: H'0080 053D> <Upon exiting reset: H'00> b Bit Name Function R W 8−13 No function assigned. Fix to "0." 00

14 RAMWRCNTP 0W

RAMWRCNTPRO write control bit

15 RAMWRCNTPRO 0: Enable write to RAMWRCNTn R W

RAM write disable protect bit 1: Disable write to RAMWRCNTn This register controls writes to the RAM Write Disable Control Register by enabling or disabling the write. If a write to the RAM Write Disable Control Register is attempted when the RAMWRCNTPRO bit = "1," the attempted write is ignored. To set this register, follow the procedure described below. 1. Write a "1" to RAMWRCNTP. 2. Subsequent to 1 above, write a "0" to RAMWRCNTP and a set value ("0" or "1") to RAMWRCNTPRO. Note: • If theare are writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and 2, the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the writing value is not reflected. Therefore, disable interrupts and DMA transfers before setting. However the writing cycle from RTD and DRI are not effected. b 8 9 1 01 11 21 31 4 b 1 5 RAMWRCNTP RAMWRCNTPRO 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 If a write cycle to any other area occurs during this interval, the value that was set in the RAMWRCNTPRO bits is not reflected. (Note 1) RAMWRCNTP "1" RAMWRCNTP "0" RAMWRCNTPRO Set value

• Example of correct settings  Cases where settings have no effect Because a write cycle to other area exists, the set value is not reflected. (Note 1) RAMWRCNTP "1" Write to other area RAMWRCNTP "0" RAMWRCNTPRO Set value (1) (2) RAMWRCNTP "1" RAMWRCNTP "1" RAMWRCNTP "0" RAMWRCNTPRO Set value Because these two consecutive writes comprise a pair, the next set value is not reflected. Note 1: The writing cycle to the other area is the writing cycle from CPU, DMA, SDI (tool), NBD to any other area. The writing cycle from RTD and DRI are not effected. Figure 6.3.1 RAMWRCNTPRO Setting Procedure

6-932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.3.2 Block Diagram of RAM Write Monitor Interrupt Request (1/2) F/F F/F RAMWRCNT0 RAMWRIST0 Data bus Write to area 0 The remaining 8-source inputs in the next page RAM write monitor interrupt request(Level) 16-source inputs RAMWRIST (H'0080 0530) RAMWRCNT (H'0080 0538) WR F/F (RAMWRCNTPRO) WR F/F F/F RAMWRCNT1 RAMWRIST1 Write to area 1WR F/F F/F RAMWRCNT2 RAMWRIST2 Write to area 2WR F/F F/F RAMWRCNT3 RAMWRIST3 Write to area 3WR F/F F/F RAMWRCNT4 RAMWRIST4 Write to area 4WR F/F F/F RAMWRCNT5 RAMWRIST5 Write to area 5 WR F/F F/F RAMWRCNT6 RAMWRIST6 Write to area 6WR F/F F/F RAMWRCNT7 RAMWRIST7 Write to area 7WR To the next page RAM write disable protect

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.3.3 Block Diagram of RAM Write Monitor Interrupt Request (2/2) To the previous page(Level) 8-source inputs F/F F/F RAMWRCNT8 RAMWRIST8 Data bus Write to area 8 RAMWRIST (H'0080 0530) RAMWRCNT (H'0080 0538) WR F/F F/F RAMWRCNT9 RAMWRIST9 Write to area 9WR F/F F/F RAMWRCNT10 RAMWRIST10 b10 Write to area 10WR b10 F/F F/F RAMWRCNT11 RAMWRIST11 b11 Write to area 11WR b11 F/F F/F RAMWRCNT12 RAMWRIST12 b12 Write to area 12WR b12 F/F F/F RAMWRCNT13 RAMWRIST13 b13 Write to area 13 WR b13 F/F F/F RAMWRCNT14 RAMWRIST14 b14 Write to area 14WR b14 F/F F/F RAMWRCNT15 RAMWRIST15 b15 Write to area 15WR b15 From the previous page

6-1132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Specifications of the internal flash memory are shown below. Table 6.4.1 Specifications of the Internal Flash Memory Item Specification Size M32192F8 : 1 Mbyte (1024 Kbytes) M32195F4 : 512 Kbytes M32196F8 : 1 Mbyte (1024 Kbytes) Location address M32192F8 : H’0000 0000 to H’000F FFFF M32195F4 : H'0000 0000 to H'0007 FFFF M32196F8 : H'0000 0000 to H'000F FFFF Wait insertion Operates with one wait state Durability Standard product : 100 times Internal bus connection Instruction access: Connected by 64-bit bus (32-bit: Transfer rate equivalent to zero-wait states achieved) Data access: Connected by 32-bit bus Other Virtual flash emulation function is incorporated. (See Section 6.7, “Virtual Flash Emulation function.”)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.4.1 Block Configuration of the Internal Flash Memory for the M32192F8 and M32196F8 H'0002 0000 H'0000 7FFF H'0000 8000 H'0001 FFFF H'0000 FFFF H'0001 0000 H'0000 4000 H'0002 FFFF H'0003 0000 H'0003 FFFF H'0004 0000 H'0004 FFFF H'0005 0000 H'0005 FFFF H'0006 0000 H'0006 FFFF H'0007 0000 H'0007 FFFF H'0000 0000 H'0000 1FFF H'0000 2000H'0000 2FFF H'0000 3000H'0000 3FFF H'0008 0000 H'0008 FFFF H'0009 0000 H'0009 FFFF H'000A 0000 H'000A FFFF H'000B 0000 H'000B FFFF H'000C 0000 H'000C FFFF H'000D 0000 H'000D FFFF H'000E 0000 H'000E FFFF H'000F 0000 H'000F FFFF Internal flash memory area of the M32192F8 and M32196F8 (1024 Kbytes) Block 0 Unequal blocks Equal blocks Block 1 Block 2 Block 3 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4

6-1332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 H'0002 0000 H'0000 7FFF H'0000 8000 H'0001 FFFF H'0000 FFFF H'0001 0000 H'0000 4000 H'0002 FFFF H'0003 0000 H'0003 FFFF H'0004 0000 H'0004 FFFF H'0005 0000 H'0005 FFFF H'0006 0000 H'0006 FFFF H'0007 0000 H'0007 FFFF H'0000 0000 H'0000 1FFF H'0000 2000H'0000 2FFF H'0000 3000H'0000 3FFF Internal flash memory area of the M32195F4 (512 Kbytes) Block 0 Unequal blocks Equal blocks Block 1 Block 2 Block 3 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Figure 6.4.2 Block Configuration of the Internal Flash Memory for the M32195F4

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.5 Registers Associated with the Internal Flash Memory

A register map associated with the internal flash memory is shown below. Internal Flash Memory Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 01E0 Flash Mode Register Flash Status Register 6-15 (FMOD) (FSTAT) 6-16 H'0080 01E2 Flash Control Register 1 Flash Control Register 2 6-17 (FCNT1) (FCNT2) 6-18 H'0080 01E4 Flash Control Register 3 Flash Control Register 4 6-19 (FCNT3) (FCNT4) 6-22 H'0080 07E8 Virtual Flash L Bank Register 0 6-24 (FELBANK0) H'0080 07EA Virtual Flash L Bank Register 1 6-24 (FELBANK1) H'0080 07EC Virtual Flash L Bank Register 2 6-24 (FELBANK2) H'0080 07EE Virtual Flash L Bank Register 3 6-24 (FELBANK3) H'0080 07F0 Virtual Flash L Bank Register 4 (Note 2) 6-24 (FELBANK4) H'0080 07F2 Virtual Flash L Bank Register 5 (Note 2) 6-24 (FELBANK5) H'0080 07F4 Virtual Flash L Bank Register 6 (Note 2) 6-24 (FELBANK6) H'0080 07F6 Virtual Flash L Bank Register 7 (Note 2) 6-24 (FELBANK7) H'0080 07F8 Virtual Flash L Bank Register 8 (Note 1) 6-24 (FELBANK8) H'0080 07FA Virtual Flash L Bank Register 9 (Note 1) 6-24 (FELBANK9) H'0080 07FC Virtual Flash L Bank Register 10 (Note 1) 6-24 (FELBANK10) H'0080 07FE Virtual Flash L Bank Register 11 (Note 1) 6-24 (FELBANK11) H'0080 0800 Virtual Flash L Bank Register 12 (Note 1) 6-24 (FELBANK12) H'0080 0802 Virtual Flash L Bank Register 13 (Note 1) 6-24 (FELBANK13) H'0080 0804 Virtual Flash L Bank Register 14 (Note 1) 6-24 (FELBANK14) H'0080 0806 Virtual Flash L Bank Register 15 (Note 1) 6-24 (FELBANK15) Note 1: This area exists only in the 32192 and it is use prohibition area in the 32195/32196. Note 2: This area exists only in the 32192/32196 and it is use prohibition area in the 32195.

6-1532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.5.1 Flash Mode Register

Flash Mode Register (FMOD) <Address: H’0080 01E0> <Upon exiting reset: H’1?> b Bit Name Function R W 0–2 No function assigned. Fix to "0" 00

3 FAENS 0: Flash access disabled R –

Flash access enable status bit 1: Flash access enabled 4–6 No function assigned. Fix to "0" 00

7 FPMOD 0: FP pin = "L" R –

External FP pin status bit 1: FP pin = "H" (1) FAENS (Flash Access Enable Status) bit (Bit 3) The FAENS bit shows whether access to the flash memory is enabled or disabled. When the flash memory is reset by the FRESET bit in Flash Control Register 4 (FCNT4) or accessed for programming/erasure, this bit is cleared to "0," resulting in the flash memory being disabled against access. When the flash memory becomes ready for access, this bit is set to "1." However, it requires up to 30 µs for FAENS bit to be "1" from "0" after exiting Flash reset by FRESET bit or executing programming and erasing operation for Flash memory. (2) FPMOD (External FP Pin Status) bit (Bit 7) The FPMOD is a status bit which indicates the FP (Flash Protect) pin status. The internal flash memory is enabled for programming or erase operation only when FPMOD = "1," and is protected against programming or erase operation when FPMOD = "0." b 0 123456 b 7 FAENS FPMOD 0001000?

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.5.2 Flash Status Register

Flash Status Register (FSTAT) <Address: H’0080 01E1> <Upon exiting reset: H’80> b Bit Name Function R W

8 FBUSY 0: Being programmed or erased R –

Flash busy bit 1: Ready state 9 No function assigned. Fix to "0." 00

10 ERASE 0: Erase normally operating or terminated R –

Erase status confirmation bit 1: Erase error occurred

11 WRERR 0: Programming normally operating or terminated R –

Write status confirmation bit 1: Programming error occurred 12 No function assigned. Fix to "0." 00 13 FESQ1 ?– Reserved bit 14 FESQ2 ?– Reserved bit 15 No function assigned. Fix to "0." 00 Flash Status Register (FSTAT) consists of the following status bits that indicate the operation condition of the flash memory. (1) FBUSY (Flash Busy) bit (Bit 8) The FBUSY bit is used to determine whether the operation on the flash memory is finished when it is being programmed or erased. When FBUSY = "0," it means that the programming or erase operation is being executed; when FBUSY = "1," the operation is finished. Note: • Except when programming/erase processing on the flash memory is forcibly terminated, do not manipulate the FRESET bit in Flash Control Register 4 (FCNT4) while the FBUSY bit = "0" (programming/erasure in progress). (2) ERASE (Erase Status Confirmation) bit (Bit 10) The ERASE bit is used to determine after execution of processing whether the erase operation performed on the flash memory resulted in an error. When ERASE = "0," it means that the erase operation terminated normally; when ERASE = "1," the erase operation terminated in an error. This bit is set to "1" (Erase error occurred) in the following cases:

• An invalid command is issued
• The operation is not executed under normal erase conditions (power voltage, temperature)
• Protect function by lock bit attempts to erase the valid area
• Erase operation is not available because of the internal flash memory failure (3) WRERR (Write Status Confirmation) bit (Bit 11) The WRERR bit is used to determine after completion of processing whether the programming operation performed on the flash memory resulted in an error. When WRERR = "0," it means that the programming operation terminated normally; when WRERR = "1," the programming operation terminated in an error. This bit is set to "1" (Programming error occurred) in the following cases:
• An invalid command is issued
• The operation is not executed under normal programming conditions (power voltage, temperature)
• Protect function by lock bit attempts to write to the valid area
• Write operation is not available because of the internal flash memory failure b 8 9 1 01 11 21 31 4 b 1 5 FBUSY ERASE WRERR FESQ1 FESQ2 10000000

6-1732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.5.3 Flash Control Registers

Flash Control Register 1 (FCNT1) <Address: H’0080 01E2> <Upon exiting reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0." 00

3 FENTRY 0: Normal read R W

Flash E/W enable mode entry bit 1: Program/erase enable 4–6 No function assigned. Fix to "0." 00

7 FEMMOD 0: Normal mode R W

Virtual flash emulation mode bit 1: Virtual flash emulation mode Flash Control Register 1 (FCNT1) consists of the following two bits to control the internal flash memory. (1) FENTRY (Flash E/W Enable Mode Entry) bit (Bit 3) The FENTRY bit controls entry to flash E/W enable mode. Flash E/W enable mode can only be entered when FENTRY = "1." To set the FENTRY bit to "1," write "0" and then "1" to the FENTRY bit in succession while the FP pin = "H." To clear the FENTRY bit, check to see that the Flash Status Register (FSTAT) FBUSY bit = "1" (ready), issue Read Array commands (or Flash memory reset by FRESET bit), make sure that FAENS bit = "1," and then write "0" to the FENTRY bit. However, when Flash memory is not reset by FRESET bit, it is not required to check the FAENS bit. Note that the following operations cannot be performed while programming or erasing the internal flash memory (FSTAT register FBUSY bit = "0"). If one of these operations is attempted, the FENTRY bit is cleared to "0" in hardware. 1) Writing "0" to the FENTRY bit 2) Entering a "L" level signal to the FP pin 3) Entering a "L"level signal to the RESET# pin When running a program resident in the internal flash memory while the FENTRY bit = "0," the EI vector entry is located at the address H’0000 0080 of the internal flash memory. When running the flash write/ erase program in the RAM while the FENTRY bit = "1," the EI vector entry is located at the address H’0080 4000 of the RAM, allowing the flash programming/erase operation to be controlled using interrupts. Table 6.5.1 Changes of the EI Vector Entry by FENTRY FENTRY EI Vector Entry Address

0 Internal flash memory area H'0000 0080

1 Internal RAM area H'0080 4000

(2) FEMMOD (Virtual Flash Emulation Mode) bit (Bit 7) The FEMMOD bit controls entry to virtual flash emulation mode. Virtual flash emulation mode is entered by setting the FEMMOD bit to "1" while the FENTRY bit = "0." (For details, see Section 6.7, “Virtual Flash Emulation Function.”) b 0 123456 b 7 FENTRY FEMMOD 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Flash Control Register 2 (FCNT2) <Address: H’0080 01E3> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0." 00

11 FLOCKS 0: Memory area read mode R (Note 1)

Lock bit read mode select bit 1: Register read mode 12–14 No function assigned. Fix to "0." 00

15 FPROT 0: Protection by lock bit effective R (Note 1)

Lock bit protect control bit 1: Protection by lock bit invalidated Note 1: It can be accessed for write only during the Flash E/W entry mode (FENTRY bit = "1"). (1) FLOCKS (Lock Bit Read Mode Select) bit (Bit 11) The FLOCKS bit is used to select a method for reading out the lock bit status. When the FLOCKS bit = "0," the internal flash memory is placed in memory area read mode, so that it is possible to inspect the lock bit status by issuing command data H’7171 to any address of the flash memory and then reading the last even address of the target block. When the FLOCKS bit = "1," the internal flash memory is placed in register read mode, so that it is possible to inspect the lock bit status by first issuing command data H’7171 and H’D0D0 to any address of the target block in succession and then, when the FBUSY bit is set to "1," by reading the FLOCKST bit in Flash Control Register 4. The FLOCKS bit can only be accessed for write when the FENTRY bit = "1." If one of the following operations is attempted, the FLOCKS bit is cleared to "0." 1) Writing "0" to the FLOCKS bit 2) Entering a "L" level signal to the FP pin 3) Clearing the FENTRY bit to "0" 4) Entering a "L" level signal to the RESET# pin (2) FPROT (Lock Bit Protect Control) bit (Bit 15) The FPROT bit controls invalidation of the internal flash memory protection by a lock bit (protection against programming/erase operation). Protection of the internal flash memory is invalidated by setting the FPROT bit to "1," so that any blocks protected by a lock bit can now be programmed or erased. To set the FPROT bit to "1," write "0" and then "1" to the FPROT bit in succession while the FENTRY bit = "1." To clear the FPROT bit to "0," write "0" to the FPROT bit. If one of the following operations is attempted, the FPROT bit is cleared to "0." 1) Writing "0" to the FPROT bit 2) Entering a "L" level signal to the FP pin 3) Clearing the FENTRY bit to "0" 4) Entering a "L" level signal to the RESET# pin b 8 9 1 01 11 21 31 4 b 1 5 FLOCKS FPROT 00000000

6-1932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 FPROT = 0 FENTRY = 1 YES NO FENTRY = 1 FPROT = 1 FPROT is not set to 1 if a write cycle to any other area occurs during this time. FPRO T = 0 FPRO T = Figure 6.5.1 Protection Unlocking Flow Flash Control Register 3 (FCNT3) <Address: H’0080 01E4> <Upon exiting reset: H’11> b Bit Name Function R W 0–2 No function assigned. Fix to "0." 00

3 FBSYCK 0: Command accepted normally R –

Busy check bit 1: Command not accepted normally 4–6 No function assigned. Fix to "0." 00

7 FPBSYCK 0: Command accepted normally R –

Prebusy check bit 1: Command not accepted normally Flash Control Register 3 (FCNT3) is used when developing an internal flash memory write/erase program to check whether commands have been accepted normally. This register does not need to be used for a program that has been verified to be able to operate properly. (1) FBSYCK (Busy Check) bit (Bit 3) The FBSYCK bit is used to check whether the command of two or more cycles (confirmation command H'D0D0 or a command that requires write data) issued to the flash memory during flash E/W enable mode has been accepted normally. Commands of two or more cycles are shown in Table 6.5.2. If the FBSYCK bit is found to be "0" after issuing the busy check target command (See Table 6.5.2), it means that the busy check target com- mand has been accepted normally. Conversely, if the FBSYCK bit is found to be "1," it means that the busy check target command has not been accepted normally. In addition to the above, the FBSYCK bit is set to "1" in the following cases: 1) When a prebusy check target command has been accepted 2) When the FRESET bit = "1" 3) When input on RESET# pin is pulled "L" b 0 123456 b 7 FBSYCK FPBSYCK 00010001

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) FPBSYCK (Prebusy Check) bit (Bit 7) The FPBSYCK bit is used to check whether the command of two or more cycles (confirmation command H'D0D0 or a command that requires write data) issued to the flash memory during flash E/W enable mode has been accepted normally. If the FPBSYCK bit is found to be "0" after issuing the prebusy check target command (See Table 6.5.2), it means that the prebusy check target command has been accepted normally. Conversely, if the FPBSYCK bit is found to be "1," it means that the prebusy check target command has not been accepted normally. In addition to the above, the FPBSYCK bit is set to "1" in the following cases: 1) When in a ready state (FBUSY bit = "H" after a prebusy check target command has been accepted) 2) When the Clear Status Register command is issued 3) When the FRESET bit = "1" 4) When input on RESET# pin is pulled "L" Table 6.5.2 Prebusy, Busy Check Target Comand (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) __ _ __ _ ___ Lock bit Program Write H'7777 (Lock bit program command) Write H'2020 (Block erase command) Write H'7171 (Read lock bit status command) Write H'4343 (4 halfword program command) Write H'D0D0 (Confirmation command) Write H'D0D0 (Confirmation command) Write H'D0D0 (Confirmation command) Write halfword data Write halfword data Write halfword data Write halfword data Block Erase Read Lock bit Status (during Register read mode) 4 Halfword Program Note 1: Prebusy check target command Note 2: Busy check target command

6-2132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 END Confirm execution result (Note 3) START Write a prebusy check target command (Note 1) FBUSY = "1" TIME OUT ? YES NO Forcibly terminate YES NO FPBSYCK = "0" YES Write a busy check target command (Note 1) 1 µs wait (by hardware timer or software timer) (Note 2) Operation starts FBSYCK = "0" YES Write a clear status command, H'5050 NO NO Note 1: Refer to Table 6.5.2 for prebusy check target command and busy check target command. Note 2: It is not required during read lock bit status command (during register read command). Note 3: Confirm by ERASE bit of the FSTAT register, WRERR bit, or FLOCKST bit of the FCNT4 register depending on the respective commands. Figure 6.5.2 Method to Confirm the Command Acceptance by Checking FCNT3

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Flash Control Register 4 (FCNT4) <Address: H’0080 01E5> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0." 00

11 FLOCKST 0: Protected (Note 1) –

Lock bit status bit 1: Unprotected 12–14 No function assigned. Fix to "0." 00

15 FRESET 0: No operation R W

Flash reset bit 1: Reset Note 1: Under setting FLOCKS bit of the flash control register 2 as "1" (register read mode), only the reading out value becom es effective after issuing read rock bit status command . The reading out value is undefined after issuing that read rock bit status command under setting FLOCKS bit as "0" (memory area read mode) and that other internal flash control command. (1) FLOCKST (Lock Bit Status) bit (Bit 11) The FLOCKST bit is used to read the lock bit status. If the FLOCKST bit = "0," it means that the relevant memory block is protected. If the FLOCKST bit = "1," it means that the relevant memory block is not pro- tected. Confirmation of the lock bit status by the FLOCKST bit is possible when the FLOCKS bit = "1." In this case, the lock bit status can be checked by first issuing command data H’7171 and H’D0D0 to any address of the target block in succession and then, when the FBUSY bit is set to "1," by reading the FLOCKST bit. (2) FRESET (Flash Reset) bit (Bit 15) The FRESET bit controls forcible termination of the internal flash memory programming/erase operation, initialization (to H’80) of each status bit in the Flash Status Register (FSTAT), and initialization of the FPBSYCK bit in Flash Control Register 3 (FCNT3). Setting the FRESET bit to "1" forcibly terminates programming/erase operation and initializes each status bit in the FSTAT (to H’80) and the FPBSYCK bit in FCNT3. Make sure FRESET is held high (= "1") for at least 10 µs during a flash reset. After a flash reset, the internal flash memory is disabled against access until the FAENS bit is set to "1." The FRESET bit is effective only when the FENTRY bit = "1." Unless the FENTRY bit = "1," settings made to the FRESET bit are ignored. Make sure the FRESET bit = "0" while programming or erasing the flash memory. b 8 9 1 01 11 21 31 4 b 1 5 FLOCKST FRESET 00000000

6-2332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.5.3 Example of FRESET Bit 1 (Initializing Flash Status Register 2) Figure 6.5.4 Example of FRESET Bit 2 (Forcibly Terminating Programming/Erasing Operation) YES NO 10µs wait (by hardware timer or software timer) FMOD register FAENS = 1? YES NO FRESET = 1 FENTRY = 1 Program/erase the flash memory Error found FRESET = 0 Program/erase the flash memory FENTRY = 0 Programming/erase operation terminated normally YES NO FRESET = 1 FRESET = 0 Forcibly terminate Flash programming/erase operation has timed out 10µs wait (by hardware timer or software timer) FMOD register FAENS = 1?

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.5.4 Virtual Flash L Bank Registers

Virtual Flash L Bank Register 0 (FELBANK0) <Address: H’0080 07E8> Virtual Flash L Bank Register 1 (FELBANK1) <Address: H’0080 07EA> Virtual Flash L Bank Register 2 (FELBANK2) <Address: H’0080 07EC> Virtual Flash L Bank Register 3 (FELBANK3) <Address: H’0080 07EE> Virtual Flash L Bank Register 4 (FELBANK4) (Note 3) <Address: H’0080 07F0> Virtual Flash L Bank Register 5 (FELBANK5) (Note 3) <Address: H’0080 07F2> Virtual Flash L Bank Register 6 (FELBANK6) (Note 3) <Address: H’0080 07F4> Virtual Flash L Bank Register 7 (FELBANK7) (Note 3) <Address: H’0080 07F6> Virtual Flash L Bank Register 8 (FELBANK8) (Note 2) <Address: H’0080 07F8> Virtual Flash L Bank Register 9 (FELBANK9) (Note 2) <Address: H’0080 07FA> Virtual Flash L Bank Register 10 (FELBANK10) (Note 2) <Address: H’0080 07FC> Virtual Flash L Bank Register 11 (FELBANK11) (Note 2) <Address: H’0080 07FE> Virtual Flash L Bank Register 12 (FELBANK12) (Note 2) <Address: H’0080 0800> Virtual Flash L Bank Register 13 (FELBANK13) (Note 2) <Address: H’0080 0802> Virtual Flash L Bank Register 14 (FELBANK14) (Note 2) <Address: H’0080 0804> Virtual Flash L Bank Register 15 (FELBANK15) (Note 2) <Address: H’0080 0806> <Upon exiting reset: H’0000> b Bit Name Function R W

0 MODENL 0: Disable virtual flash emulation function R W

Virtual flash emulation L enable bit 1: Enable virtual flash emulation function 1–6 No function assigned. Fix to "0." 00 7–14 LBANKAD Start address A11–A18 of the relevant L bank R W L bank address bit (Note 1) 15 No function assigned. Fix to "0." 00 Note 1: Because the internal flash memory of the M32192F8 and M32196F8 are 1M (1024K) bytes, the address b7 (A11) must always be set to "0." Also, because the internal flash memory of the M32195F4 is 512 Kbytes, the address b7(A11) and b5(A12) must always be set to "0." Note 2: This area exists only in the 32192 and it is use prohibition area in the 32195/32196. Note 3: This area exists only in the 32192/32196 and it is use prohibition area in the 32195. Note: • These registers must always be accessed in halfwords. (1) MODENL (Virtual Flash Emulation L Enable) /bit (Bit 0) The MODENL bit can be set to "1" after entering virtual flash emulation mode (by setting the FEMMOD bit to "1" while the FENTRY bit = "0"). This causes the virtual flash emulation function to be enabled for the L bank area selected by the LBANKAD bits. (2) LBANKAD (L Bank Address) bits (Bits 7–14) The LBANKAD bits are provided for selecting one of the L banks that are separated every 8 Kbytes. Use these LBANKAD bits to set the eight bits A11–A18 (b7 corresponds to the address A11 and b14 corresponds to the address A18) of the 32-bit start address of the desired L bank. Note: • For details, see Section 6.7, “Virtual Flash Emulation Function.” b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 LBANKAD 000000000000000 MOD ENL

6-2532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.6.1 Outline of Internal Flash Memory Programming

To program or erase the internal flash memory, there are following two methods to choose depending on the situation: (1) When the flash write/erase program does not exist in the internal flash memory (2) When the flash write/erase program already exists in the internal flash memory For (1), set the FP pin = "H," MOD0 = "H" and MOD1 = "L" to enter boot mode. In this case, the CPU starts running the boot program upon exiting the reset state. The boot program transfers the flash write/erase program into the internal RAM. After the transfer, jump to a location in the RAM and use the RAM-resident program to set the Flash Control Register 1 (FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in boot mode + flash E/W enable mode). When the above is done, use the flash write/erase program that has been transferred into the internal RAM to program or erase the internal flash memory. For (2), set the FP pin = "H," MOD0 = "L" and MOD1 = "L" to enter single-chip mode. Transfer the flash write/ erase program from the internal flash memory in which it has been prepared into the internal RAM. After the transfer, jump to the RAM and use the program transferred into the RAM to set the Flash Control Register 1 (FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in single-chip mode + flash E/W enable mode). When the above is done, use the flash write/erase program that has been transferred into the internal RAM to program or erase the internal flash memory. Or flash E/W enable mode can be entered from external extension mode by setting the FP pin = "H," MOD0 = "L" and MOD1 = "H." During flash E/W enable mode (FP pin = "H", FENTRY = "1"), the EIT vector entry for External Interrupt (EI) is relocated to the start address (H’0080 4000) of the internal RAM. During normal mode, it is located in the flash area (H’0000 0080). To use an external interrupt (EI) in flash E/W enable mode, write at the beginning of the internal RAM an instruction for branching to the external interrupt (EI) handler that has been transferred into the internal RAM. Furthermore, because the IVECT register which is read out in the external interrupt (EI) handler has stored in it the flash memory address of the ICU vector table, make sure the ICU vector table to be used during flash E/ W enable mode is prepared in the internal RAM so that the value of the IVECT register will be converted into the internal RAM address of the ICU vector table (for example, by adding an offset) before performing branch processing. When started by boot mode, internal RAM value is indefinite after started by boot mode in order to "Flash writing/erasing program" is transferred to internal RAM.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 EI vector entry (H'0000 0080) Internal ROM area Internal RAM H'0000 0000 H'00FF FFFF H'0080 4000 Internal ROM area Internal RAM H'0080 3FFF Flash E/W enable mode (FENTRY = 1) Normal mode (FENTRY = 0) H'0000 0000 H'0080 3FFF EI vector entry (H'0080 4000)H'0080 4000 H'00FF FFFF Figure 6.6.1 EI Vector Entry during Flash E/W Enable Mode

6-2732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.6.2 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase program does not exist in it) (1) When the flash write/erase program does not exist in the internal flash memory In this case, the boot program is used to program or erase the internal flash memory. To transfer the write data, use SIO1 of serial interface 1 in clock-synchronous serial interface, or clock-asynchronous serial interface mode. To program or erase the internal flash memory using a flash programmer, follow the procedure described below. SIO1 CPU SIO1 CPU Flash write/ erase program MOD1 = L SIO1 CPU internal RAM internal Flash memory FP = L or H internal RAM internal RAM <Step 1> <Step 2>  Set the FP pin "H," MOD0 pin "H" and MOD1 pin "L" to place the flash memory in boot mode + flash E/W enable mode.  Deassert reset signal and start up with the boot program.  Transfer the flash write/erase program into the internal RAM. (Note 1)  Jump to the flash write/erase program in the internal RAM. <Step 3>  Using the flash write/erase program in the internal RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1.  Program or erase the internal flash memory using the flash write/erase program.  When finished, set the MOD0 "L" and jump to the internal flash memory or apply a reset to enter normal mode. M32R/ECU M32R/ECU M32R/ECU External device (e.g., flash programmer) External device (e.g., flash programmer) internal Flash memory Flash write data internal Flash memory MOD0 = L Boot program Boot program Boot program MOD1 = LFP = H MOD0 = H MOD1 = LFP = H MOD0 = H RESET# = L RESET# = H RESET# = H Flash write/ erase program Write data Write data Write data External device (e.g., flash programmer) Note 1: When started by boot mode, internal RAM value is indefinite after started by boot mode in order to “Flash writing/ erasing program” is transferred to internal RAM.  Initial state (internal Flash write/erase program nonexistent in the internal flash memory)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 RESET# pin MOD0 pin FENTRY bit FP pin MOD1 pin POWER ON Mode selected Reset signal deasserted (Boot program starts) Mode selected Reset signal deasserted Flash programming/erasing by the boot program Settings by the boot program Figure 6.6.3 Internal Flash Memory Write/Erase Timing (when the flash write/erase program does not exist in it)

6-2932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.6.4 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase program already exists in it) (2) When the flash write/erase program already exists in the internal flash memory In this case, the flash write/erase program prepared in the internal flash memory is used to program or erase the internal flash memory. For programming/erase operation here, use the internal peripheral circuits in the manner suitable for the programming system. (All resources of the internal peripheral circuits such as the data bus, serial interface and ports can be used.) The following shows an example for programming or erasing the internal flash memory by using SIO0 in single-chip mode. SIO0 CPU Flash write/ erase program SIO0 CPU Flash write/ erase program MOD1 = L SIO0 CPU internal RAM Flash write/ erase program FP = L or H Write data internal RAM internal RAM <Step 1>  Initial state (Flash write/erase program existing in the internal flash memory)  An ordinary program in the internal flash memory is being executed. <Step 2>  Set the FP pin "H", MOD1 pin "L" and MOD0 pin "L" to place the flash memory in single-chip + flash E/W enable mode.  After determining the FP pin and MOD1 pin levels, transfer the flash write/erase program from the internal flash memory area into the RAM.  Jump to the flash write/erase program in the internal RAM. <Step 3>  Using the flash write/erase program in the internal RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1.  Program or erase the internal flash memory using the flash write/erase program in the internal RAM.  When finished, jump to the program in the internal flash memory or apply a reset to enter normal mode. M32R/ECU M32R/ECU M32R/ECU External device External device External device internal Flash memory Flash write data internal Flash memory MOD0 = L MOD1 = LFP = H MOD0 = L MOD1 = LFP = H MOD0 = L Write data Write data

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 RESET# pin MOD0 pin FENTRY bit FP pin "H" or "L" "H" or "L" (single-chip or external extension)MOD1 pin "L" "H" or "L" Flash programming/erasing by the flash write/erase program Flash rewrite starts Flash mode turned on Flash mode turned off Flash write/erase program transferred into the RAM Figure 6.6.5 Internal Flash Memory Write/Erase Control Pin Timing (when the flash write/erase program already exists in it)

6-3132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.6.2 Controlling Operation Modes during Flash Programming

The microcomputer’s operation mode is set by MOD0, MOD1 and Flash Control Register 1 (FCNT1) FENTRY bit. The table below lists operation modes that may be used when programming or erasing the internal flash memory. Table 6.6.1 Operation Modes Set during Flash Programming/Erase FP MOD0 MOD1 FENTRY (Note 1) Operation Mode Reset Vector Entry EI Vector Entry 0 0 0 0 Single-chip mode Start address of internal Flash area 1 0 0 0 flash memory (H'0000 0080) (H'0000 0000) 0 1 0 0 Processor mode Start address of external External area area (H'0000 0000) (H'0000 0080) 0 0 1 0 External extension Start address of internal Flash area 1 0 1 0 mode flash memory (H'0000 0080) (H'0000 0000) 1 0 0 1 Single-chip mode Start address of internal Beginning of internal RAM + flash E/W enable flash memory (H'0080 4000) (H'0000 0000) 1 1 0 0 Boot mode Boot program startup Flash area address (H'0000 0080) 1 1 0 1 Boot mode + flash Boot program startup Beginning of internal RAM E/W enable address (H'0080 4000) 1 0 1 1 External extension Start address of internal Beginning of internal RAM mode + flash E/W flash memory (H'0080 4000) enable (H'0000 0000) – 1 1 – Setting inhibited – – Note 1: Indicates the Flash Control Register 1 (FCNT1) FENTRY bit status (– denotes “Don’t care”). However, if FP = "0," writing "1" to FENTRY only results in it cleared to "0." Note: • Always make sure the MOD2 pin is connected low (= 0) to ground (GND).

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (1) Flash E/W enable mode Flash E/W enable mode is a mode in which the internal flash memory can be programmed or erased. In flash E/W enable mode, no programs can be executed in the internal flash memory. Therefore, the neces- sary program must be transferred into the internal RAM before entering flash E/W enable mode, so that it can be executed in the RAM. (2) Entering flash E/W enable mode Flash E/W enable mode can only be entered when operating in single-chip, external extension or boot mode. Furthermore, it is only when the FP pin = "H" and the Flash Control Register 1 (FCNT1) FENTRY bit = "1" that flash E/W enable mode can be entered. Flash E/W enable mode cannot be entered when operat- ing in processor mode or the FP pin = "L." (3) Detecting the MOD0 and MOD1 pin levels The MOD0 and MOD1 pin levels ("H" or "L") can be known by checking the P8 Data Register (Port Data Register, H’0080 0708) MOD0DT and MOD1DT bits. P8 Data Register (P8DATA) <Address: H’0080 0708> 123456 b 7b0 P87DTP86DTP85DTP84DTP83DTP82DTMOD1DTMOD0DT <Upon exiting reset: Undefined> b Bit Name Function R W

0 MOD0DT (P80DT) 0: MOD0 pin = "L" R –

MOD0 data bit 1: MOD0 pin = "H"

1 MOD1DT (P81DT) 0: MOD1 pin = "L" R –

MOD1 data bit 1: MOD1 pin = "H"

2 P82DT At read R W

Port P82 data bit Depends on how the Port Direction Register is set

3 P83DT • If direction bit = "0" (input mode)

Port P83 data bit 0: Port input pin = "L"

4 P84DT 1: Port input pin = "H"

Port P84 data bit • If direction bit = "1" (output mode) (Note 1)

5 P85DT 0: Port output latch = "0" / Port pin level = "L"

Port P85 data bit 1: Port output latch = "1" / Port pin level = "H"

6 P86DT At write

Port P86 data bit Write to the port output latch

7 P87DT

Note 1: To select the port data to read, use the Port Input Special Function Control Register’s port input data select bit (PIS EL).

6-3332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.6.6 Procedure for Entering Flash E/W Enable Mode END START Enter one of the following modes:  Single-chip mode  Boot mode  External extension mode Transfer the flash write/erase program into the internal RAM Set the Flash Control Register in SFR area (FCNT1) FENTRY bit to 0 Set the Flash Control Register in SFR area (FCNT1) FENTRY bit to 1 Execute flash write/erase command and various read commands (Note 1) Switched to the flash write/erase program Wait for 1 µs (using a hardware or software timer) Jump to the flash memory or apply reset Switched to normal mode Check MOD0/1 and FP (Note 2) pin levels YES NO END Note 1: For details about each command, see Section 6.6.3, "Procedure for Programming/Erasing the Internal Flash Memory." Note 2: Check FMOD register, FPMOD bit and P8DATA register MOD0DT and MOD1DT bits Go to flash E/W enable mode

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.6.7 Procedure for Entering Normal Mode START Execute flash write/erase command and various read commands FBUSY bit = 1 (Note 1) YES NO Execute read array command or reset flash memory with the FRESET bit in Flash Control Register 4 (FCNT4) FAENS bit = 1 (Note 2) YES NO Set the FENTRY bit of the Flash Control Register 1 (FCNT1) to 0 Wait for more than 8 CPUCLK cycles (Note 3) END Note 1: If it is checked that the value of FBUSY bit in Flash Status Register (FSTAT) is "1" after executing the command in flash E/W enable mode, it is not necessary to check that the value of FBUSY bit is "1." Note 2: If flash memory reset by FRESET bit in Flash Control Register 4 (FCNT4) is not executed, it is not necessary to check that the value of FAENS bit in Flash Mode Register (FMOD) is "1." Note 3: Insert any instructions for more than 8 CPUCLK waits other than NOP that do not require clock cycles (one that is automatically inserted by the assembler for alignment adjustment: instruction code H'F000). As the EI vector entry address is exchanged in the instructions for 8 CPUCLK waits, disenable the External Interrupt (EI). Note:  When switching to normal mode by entering a "L" level signal to the RESET# pin in flash E/W enable mode, enter the signal to the RESET# pin after checking that the value of FBUSY bit is "1"(ready). Jump to the flash memory or apply reset Switched to normal mode

6-3532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.6.3 Procedure for Programming/Erasing the Internal Flash Memory

To program or erase the internal flash memory, set up chip mode to enter flash E/W enable mode and execute the flash write/erase program in the internal RAM into which it has been transferred from the internal flash memory. In flash E/W enable mode, because the internal flash memory cannot be accessed for read as in normal mode, no programs present in it can be executed. Therefore, the flash write/erase program must be made available in the internal RAM before entering flash E/W enable mode. (Once flash E/W enable mode is entered into, only flash command and no other commands can be used to access the internal flash memory.) To access the internal flash memory in flash E/W enable mode, issue commands for the internal flash memory address to be operated on. The table below lists the commands that can be issued in flash E/W enable mode. Note: • During flash E/W enable mode, the internal flash memory cannot be accessed for read or write wordwise. Table 6.6.2 Commands in Flash E/W Enable Mode Command Name Issued Command Data Read Array command H'FFFF

4 Halfword Program command H'4343

Lock Bit Program command H'7777 Block Erase command H'2020 Clear Status Register command H'5050 Read Lock Bit Status command H'7171 Verify command (Note 1) H'D0D0 Note 1: This command must be issued immediately after the Lock Bit Program, Block Erase or Read Lock Bit Status command. If the Lock Bit Program, Block Erase or Read Lock Bit Status command is followed by other than the Verify (H'D0D0) command, the Lock Bit Program, Block Erase or Read Lock Bit Status command is not executed normally and terminated in error. (1) Read Array command Writing the Read Array command (H’FFFF) to any address of the internal flash memory places it in read mode. Then read the desired flash memory address, and the content of that address will be read out. Before exiting flash E/W enable mode, always be sure to execute the Read Array command. Write the Read Array command (H'FFFF) to any address of the internal flash memory Read the desired flash memory address END Final Address? YES NO Figure 6.6.8 Read Array

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Confirm the result of execution of the programming process (Note 1) Last address? YES NO START Write the program data (2 bytes x 4) to the internal flash memory address to be programmed Write the 4 Halfword Program command (H'4343) to any address of the internal flash memory Internal flash memory is programmed by 4 Halfword Program Wait for 1 µs (using a hardware or software timer) FBUSY bit = 1 TIME OUT? 1600 µs (Note 2) YES NO Forcibly terminated YES NO To next 4 halfword Note 1: Check Flash Status Register (FSTAT) ERASE bit (for the erase status) and WRERR bit (for the write status). Note 2: It is a timeout period for 4-Kbyte block. The timeout period for other than 4 Kbytes is 800 µs. Figure 6.6.9 4 Halfword Program (2) 4 Halfword Program command This command performs write (programming) to the flash memory in 4 halfword units (8-byte unit), or every 2 bytes (Half word) x 4 times. Also, the initial address at write must always be written with the address of 4 halfword boundary (low-order address, B'000). To program data to the flash memory, write the Program command (H’4343) to any address of the internal flash memory, and then the program data to the address to be programmed. The protected flash memory blocks cannot be accessed for write by the 4 Halfword Program command. 4 halfword programming is automatically performed by the internal control circuit, and whether the 4 Halfword Program command has finished can be known by checking the FBUSY (Flash Busy) bit in the Flash Status Register. While the FBUSY bit = "0," the next programming cannot be performed.

6-3732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (3) Lock Bit Program command The internal flash memory can be protected against programming/erase operation one block at a time. The Lock Bit Program command is provided for protecting the flash memory blocks. Write the Lock Bit Program command (H’7777) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to the last even address of the flash memory block to be protected, and this memory block is thereby protected against programming/erase operation. To remove protection, use the Flash Control Register 2 (FCNT2) FPROT (Rock bit Protect Control) bit to invalidate protection by a lock bit and erase the flash memory block whose protection is to be removed. (The content of that memory block is also erased.) Lock bit programming is automatically performed by the internal control circuit, and whether the Lock Bit Program command has finished can be known by checking FBUSY (Flash Busy) bit in the Flash Status Register (FSTAT). While the FBUSY bit = "0," the next programming cannot be performed. The table below lists the target flash memory blocks and their addresses to be specified when writing the Verify command data. Table 6.6.3 Target Blocks and Specified Addresses Target Block Specified Address

0 H'0000 1FFE

1 H'0000 2FFE

2 H'0000 3FFE

3 H'0000 7FFE

4 H'0000 FFFE

5 H'0001 FFFE

6 H'0002 FFFE

7 H'0003 FFFE

8 H'0004 FFFE

9 H'0005 FFFE

10 H'0006 FFFE

11 H'0007 FFFE

12 H'0008 FFFE

13 H'0009 FFFE

14 H'000A FFFE

15 H'000B FFFE

16 H'000C FFFE

17 H'000D FFFE

18 H'000E FFFE

19 H'000F FFFE

Note: • Because the internal flash memory of the M32195F4 is 512 Kbytes, block 12 to block 19 do not exist.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 END START Write the Verify command (H'D0D0) to the last even address of the flash memory block to be protected Write the Lock Bit Program command (H'7777) to any address of the internal flash memory Lock bit is programmed by Lock Bit Program Wait for 1 µs (using a hardware or software timer) FBUSY bit = 1 TIME OUT? YES NO Forcibly terminated YES NO Confirm the result of execution of the programming process (Note 1) Note 1: Check Flash Status Register (FSTAT) ERASE bit (for the erase status) and WRERR bit (for the write status). Note 2: It is a timeout period for 4-Kbyte block. The timeout period for other than 4 Kbytes is 800 µs. 1600 µs (Note 2) Figure 6.6.10 Lock Bit Program

6-3932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.6.11 Block Erase (4) Block Erase command The Block Erase command erases the content of the internal flash memory one block at a time. To perform this operation, write the command data (H’2020) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to the last even address of the flash memory block to be erased (see Table 6.6.3, “Target Blocks and Specified Addresses”). The protected flash memory blocks cannot be erased by the Block Erase command. Block erase operation is automatically performed by the internal control circuit, and whether the Block Erase command has finished can be known by checking FBUSY (Flash Busy) bit in the Flash Status Register (FSTAT). While the FBUSY bit = "0," the next block erase operation cannot be performed. END START Write the Verify command (H'D0D0) to the last even address of the flash memory block to be erased Write the Block Erase command (H'2020) to any address of the internal flash memory Internal flash memory contents are erased by the Block Erase command Wait for 1 µs (using a hardware or software timer) TIME OUT? YES NO Forcibly terminated YES NO Confirm the result of execution of the erase process (Note 1) FBUSY bit = 1 6 s Note 1: Check Flash Status Register (FSTAT) ERASE bit (for the erase status) and WRERR bit (for the write status).

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (5) Clear Status Register command The Clear Status Register command clears the Flash Status Register (FSTAT) ERASE (erase status), and WRERR (write status) bits to "0." Write the command data (H’5050) to any address of the internal flash memory, and Flash Status Register is thereby initialized. Also, issue the Clear Status Register command, and Flash Status Register 3 (FCNT3) is initialized. If an error occurs when programming or erasing the flash memory and the Flash Status Register (FSTAT) ERASE (erase status) or WRERR (write status) bit is set to "1," the next programming or erase operation cannot be executed unless each status bit is cleared to "0." START Write the Clear Status Register command (H'5050) to any address of the internal flash memory END Figure 6.6.12 Clear Status Register

6-4132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 FLBST Write the Read Lock Bit Status command (H'7171) to any address of the internal flash memory Read the last even address of the flash memory block to be checked END Figure 6.6.13 Read Lock Bit Status (Memory Area Read Mode) 2) Register read mode (FLOCKS bit = 1) Write the command data (H’7171) to any address of the target block. Next, write the verify command data (H'D0D0), and the Flash Control Register 4 (FCNT4) FLOCKST (Lock Bit Status) bit shows whether the target block is protected. (6) Read Lock Bit Status command The Read Lock Bit Status command is provided for checking whether a flash memory block is protected against programming/erase operation. The method for reading lock bit can be chosen from the following depends on the setting for Flash Control Register 2 (FCNT2) FLOCKS (Lock bit read mode select) bit. 1) Memory area read mode (FLOCKS bit = 0) Write the command data (H’7171) to any address of the internal flash memory. Next, read the last even address of the flash memory block to be checked (see Table 6.6.3, “Target Blocks and Specified Ad- dresses”), and the read data shows whether the target block is protected. If the FLBST (lock bit) in the read data is "0," it means that the target memory block is protected. If the FLBST (lock bit) is "1," it means that the target memory block is not protected. Lock Bit Status Register (FLBST) <Upon exiting reset: Undefined> b Bit Name Function R W 0–8 No function assigned. ?0

9 FLBST 0: Protected R –

Lock bit 1: Not protected 10–15 No function assigned. ? 0 The Lock Bit Status Register is a read-only register, which is included for each memory block independently of one another. To read this register, Flash Control Register 2 (FCNT2) FLOCKS bit must be set to "0."

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.6.14 Read Lock Bit Status (Register Read Mode) The following describes how to write to the lock bit. a) To clear the lock bit to "0" (flash protected) Issue the Lock Bit Program command (H’7777) to the memory block to be protected. b) To set the lock bit to "1" (flash unprotected) After setting the FPROT bit in Flash Control Register 2 to "1" (protection by lock bit disabled), use the Block Erase command (H’2020) to erase the memory block to be unprotected. The lock bit cannot be set to "1" directly by writing to it. c) Lock bit status when reset Because the lock bit is a nonvolatile bit, it remains unaffected when the microcomputer is reset or powered off. END START Write the Verify command (H'D0D0) to any address of the block Write the Read Lock Bit Status command (H'7171) to any address of the block to be read TIME OUT? YES NO Forcibly terminated YES NO Confirm the Lock bit status bit (Note 1) FBUSY bit = 1 10 µs Note 1: Check Flash Control Register 4 (FCNT4) FLOCKST bit.

6-4332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.6.4 Flash Programming Time (Reference)

The following shows the time needed to program internal flash memory for reference. (1) M32192F8 and M32196F8 [1] Transfer time by SIO (When the capacity of transfer data : 1024KB) 1 / 57600bps x 1(fram) x 11(the number of transfer bit) x 1024KB = approx. 200.2 [s] [2] Flash writing time Other than 4KB block (1024KB - 4KB x 2) / 8byte x 100ms = approx.13.0 [s] 4KB block 4KB x 2 / 8byte x 200ms = approx.0.2 [s] Total 13.2 [s] [3] Erase time (all areas) [4] Total flash writing time (1024KB all areas) During 57600bps connection,flash writing time to serial connection is so short that it is able to be ignored For this reason, flash writing time is calculable with the following formula. [1] + [3] = approx.220.3 [s] In addition, the quickest data writing time with high speed is by speeding up serial connection or other means is calculable with the following formula. [2] + [3] = approx.33.3 [s] (2) M32195F4 [1] Transfer time by SIO (When the capacity of transfer data : 512KB) 1 / 57600bps x 1(fram) x 11(the number of transfer bit) x 512KB = approx. 100.1 [s] [2] Flash writing time Other than 4KB block (512KB - 4KB x 2) / 8byte x 100ms = approx.6.5 [s] 4KB block 4KB x 2 / 8byte x 200ms = approx.0.2 [s] Total 6.7 [s] [3] Erase time (all areas) [4] Total flash writing time (512KB all areas) During 57600bps connection,flash writing time to serial connection is so short that it is able to be ignored For this reason, flash writing time is calculable with the following formula. [1] + [3] = approx.110.6 [s] In addition, the quickest data writing time with high speed is by speeding up serial connection or other means is calculable with the following formula. [2] + [3] = approx.17.2 [s]

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The microcomputer has the function to map 8-Kbyte memory blocks of the internal RAM (maximum for 32192 is 16 blocks, for 32195 is 4 blocks for 32196 is 8 blocks) into areas (L banks) of the internal flash memory that are divided in 8-Kbyte units. This functions is referred to as the Virtual Flash Emulation Function. This function allows the data located in 8-Kbyte blocks of the internal RAM to be changed with the contents of internal flash memory at the addresses specified by the Virtual Flash L Bank Register. That way, the relevant internal RAM data can read out by reading the content of internal flash memory. For applications that require modifying the contents of internal flash memory (e.g., data table) during operation, this function enables dynamic data modification by modifying the relevant internal RAM data. The internal RAM blocks allocated for virtual flash emulation can be accessed for read and write the same way as in usual internal RAM. This function, when used in combination with the microcomputer’s internal Real-Time Debugger (RTD), allows the data table, etc. created in the internal flash memory to be referenced or rewritten from the outside, thereby facilitat- ing data table tuning from an external device. Note: • Before programming/erasing the internal flash memory, always be sure to exit this virtual flash emulation mode. Figure 6.7.1 Internal RAM Bank Configuration of the 32192 H'0080 4000 H'0081 0000 H'0081 1FFF H'0081 2000 H'0081 3FFF H'0081 4000 Unusable for virtual flash emulation function

48 Kbytes

H'0080 FFFF H'0081 6000 H'0081 7FFF H'0081 8000 H'0081 9FFF H'0081 A000 H'0081 5FFFH'0081 C000 H'0081 DFFF H'0081 E000 H'0081 FFFF H'0082 0000 H'0081 BFFFH'0082 2000 H'0082 3FFF H'0082 4000 H'0082 5FFF H'0082 6000 H'0082 1FFFH'0082 8000 H'0082 9FFF H'0082 A000 H'0082 BFFF H'0082 C000 H'0082 7FFFH'0082 E000 H'0082 FFFF H'0082 DFFF RAM bank L block 0 (FELBANK0)

8 Kbytes

(FELBANK1) (FELBANK2) (FELBANK3) (FELBANK4) (FELBANK5) (FELBANK6) (FELBANK7) (FELBANK8) (FELBANK9) (FELBANK10) (FELBANK11) (FELBANK12) (FELBANK13) (FELBANK14) (FELBANK15)

6-4532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.7.3 Internal RAM Bank Configuration of the 32196 H'0080 4000 H'0080 5FFF H'0080 6000 H'0080 7FFF H'0080 8000 H'0080 A000 H'0080 BFFF H'0080 C000 H'0080 DFFF H'0080 E000 H'0080 9FFF H'0081 0000 H'0081 1FFF H'0081 2000 H'0081 3FFF H'0080 FFFF RAM bank L block 0 (FELBANK0) (FELBANK1) (FELBANK2) (FELBANK3) (FELBANK4) (FELBANK5) (FELBANK6) (FELBANK7) Figure 6.7.2 Internal RAM Bank Configuration of the 32195 H'0080 4000 H'0080 5FFF H'0080 6000 H'0080 7FFF H'0080 8000 H'0080 A000 H'0080 BFFF H'0080 9FFF RAM bank L block 0 (FELBANK0) (FELBANK1) (FELBANK2) (FELBANK3)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.7.1 Virtual Flash Emulation Area

Figure 6.7.1 to Figure 6.7.3 show the internal flash memory areas in which the Virtual Flash Emulation Function is applicable. Using the Virtual Flash L Bank Register (M32192 F8: FELBANK0 to FELBANK15, M32195F4: FELBANK0 to FELBANK3, M32196F8: FELBANK0 to FELBANK7), select one among all L banks of internal flash memory that are divided in 8-Kbyte units (by setting the eight start address bits A11–A18 of the desired L bank in the Virtual Flash L Bank Register LBANKAD bits). Then set the Virtual Flash L Bank Register’s flash emulation L enable bit (MODENL) to "1," and the selected L bank area will be replaced with 8-Kbyte blocks of the internal RAM, (maximum for 32192 is 16 blocks, for 32195 is 4 blocks, for 32196 is 8 blocks). Notes: • If the same bank area is set in two or more Virtual Flash L Bank Registers and accessed while each register’s flash emulation enable bit is enabled, the data will be destroyed. Therefore, do not set the same bank area in two or more registers.

• During virtual flash emulation mode, RAM can be accessed for read and write from the internal RAM area and the virtual flash set area.
• Before reading any virtual flash set area after setting the Flash Control Register 1 virtual flash emulation mode bit to "1," be sure to check that the virtual flash emulation mode bit has been set to "1" by reading it once.
• Before reading any virtual flash set area after setting the Virtual Flash L Bank Register virtual flash emulation L enable bit and L bank address bits, be sure to check that the virtual flash emulation L enable bit and L bank address bits have been set to the intended values by reading them once.

Figure 6.7.4 Virtual Flash Emulation Area divided in 8-Kbyte units for the M32192F8 H'0000 0000 H'0000 2000 H'0081 0000 H'0000 4000 H'000F E000 H'000F C000 H'0081 2000 H'0081 4000 H'0082 E000 H'0080 4000 <Internal flash> L bank 0 (8 Kbytes) L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) L bank 126 (8 Kbytes) L bank 127 (8 Kbytes) <Internal RAM> Notes:  If the same bank area is set in two or more Virtual Flash L Bank Registers and accessed while each register’s flash emulation enable bit is enabled, the data will be destroyed. Therefore, do not set the same bank area in two or more registers.  If any 8-Kbyte area (L bank) specified by the Virtual Flash L Bank Registers 0 to 15 is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, internal RAM can be accessed for read and write from both the internal RAM area and the virtual flash set area.

6-4732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.7.6 Virtual Flash Emulation Area divided in 8-Kbyte units for M32196F8 H'0000 0000 H'0000 2000 H'0000 4000 H'000F E000 H'000F C000 <Internal flash> L bank 0 (8 Kbytes) L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) L bank 126 (8 Kbytes) L bank 127 (8 Kbytes) <Internal RAM> Notes:  If the same bank area is set in two or more Virtual Flash L Bank Registers and accessed while each register’s flash emulation enable bit is enabled, the data will be destroyed. Therefore, do not set the same bank area in two or more registers.  If any 8-Kbyte area (L bank) specified by the Virtual Flash L Bank Registers 0 to 7 is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, internal RAM can be accessed for read and write from both the internal RAM area and the virtual flash set area. H'0080 4000 H'0080 6000 H'0080 8000 H'0081 2000 Figure 6.7.5 Virtual Flash Emulation Area divided in 8-Kbyte units for M32195F4 H'0000 0000 H'0000 2000 H'0000 4000 H'0007 E000 H'0007 C000 <Internal flash> L bank 0 (8 Kbytes) L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) L bank 62 (8 Kbytes) L bank 63 (8 Kbytes) <Internal RAM> Notes:  If the same bank area is set in two or more Virtual Flash L Bank Registers and accessed while each register’s flash emulation enable bit is enabled, the data will be destroyed. Therefore, do not set the same bank area in two or more registers.  If any 8-Kbyte area (L bank) specified by the Virtual Flash L Bank Registers 0 to 3 is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, internal RAM can be accessed for read and write from both the internal RAM area and the virtual flash set area. H'0080 4000 H'0080 6000 H'0080 8000 H'0080 A000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.7.7 Values Set in Virtual Flash Bank Register when divided in 8-Kbyte units (32192/32196) H'0000 0000 L bank Start address of bank in flash memory Values set in L bank address (LBANKAD) bit L bank 0 L bank 1 L bank 2 L bank 126 L bank 127 H'0000 2000 H'0000 4000 H'000F C000 H'000F E000 H'000 H'002 H'004 H'0FC H'0FE (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Note 1: Set the eight start address bits A11-A18 of each L bank of internal flash memory that is divided in 8-Kbyte units in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Note:  Because the internal flash memory of the M32192F8 and M32196F8 are 1M (1024K) bytes, the address b7 (A11) must always be set to "0." Figure 6.7.8 Values Set in Virtual Flash Bank Register when divided in 8-Kbyte units (32195) H'0000 0000 L bank Start address of bank in flash memory Values set in L bank address (LBANKAD) bit L bank 0 L bank 1 L bank 2 L bank 62 L bank 63 H'0000 2000 H'0000 4000 H'0007 C000 H'0007 E000 H'000 H'002 H'004 H'07C H'07E (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Note 1: Set the eight start address bits A11-A18 of each L bank of internal flash memory that is divided in 8-Kbyte units in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Note:  Because the internal flash memory of the M32195F4 is 512 Kbytes, the address b7 (A11) and b8 (A12) must always be set to "0."

6-4932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.7.2 Entering Virtual Flash Emulation Mode

To enter virtual flash emulation mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit by writing "1." After entering virtual flash emulation mode, set the Virtual Flash L Bank Register MODENL bit to "1" to enable the Virtual Flash Emulation Function. Even during virtual flash emulation mode, the internal RAM area ( M32192F8 : H’0080 4000 to H’0082 FFFF, M32195F4 : H’0080 4000 to H’0080 BFFF, M32196F8 : H’0080 4000 to H’0081 3FFF ) can be accessed the same way as in usual internal RAM. Figure 6.7.9 Virtual Flash Emulation Mode Sequence Set RAM location address in Virtual Flash L Bank Register LBANKAD Address A11–A18 Write flash data to RAM Enable virtual flash emulation MODENL 1 Settings completed Enter virtual flash emulation mode FEMMOD 1 Settings start

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.8 Connecting to A Serial Programmer (CSIO Mode)

For the internal flash memory to be rewritten in boot mode + flash E/W enable mode by using a general-purpose serial programmer, several pins on the microcomputer must be processed to make them suitable for the serial programmer, as shown below. Table 6.8.1 Processing Microcomputer Pins before Using a Serial Programmer (CSIO Mode) Note: • Pin processing is not required for those that are not listed above. Pin Name Pin No. Function Remark SCLKI1 71 Transfer clock input Pull high RXD1 70 Serial data input (received data) Pull high TXD1 69 Serial data output (transmit data) P84 68 Transmit/receive enable output Pull high FP 94 Flash memory protect Pull high MOD0 92 Operation mode 0 Connect to the main power supply MOD1 93 Operation mode 1 Connect to ground MOD2 123 Operation mode 2 Connect to ground RESET# 91 Reset After setting MOD0/MOD1, ground and back to main power supply XIN 4 Clock input XOUT 5 Clock output SBI# 77 System Break Interrupt (SBI) input Pull high or low VREF0 42 Reference voltage input for A/D converter Connect to the main power supply AVCC0 43 Analog power supply Connect to the main power supply AVSS0 60 Analog ground Connect to ground VDDE 108 RAM backup power supply Connect to the main power supply VCCER 65 Power supply for the internal voltage generator circuit 5 V +/- 10% or 3.3 V +/- 10% VCCE 95, 132 Main power supply 5 V +/- 10% or 3.3 V +/- 10% EXCVCC 61, 137 Connects external capacitance for the internal power supply Need to be grounded to earth via capacitor EXCVDD 73 Connects external capacitance for the RAM power supply Need to be grounded to earth via capacitor VCC-BUS 6, 20 External bus power supply Depends on the target system VSS 3, 21, 62, 72, 96, 138 Ground 0V JTRST 111 JTAG reset input Pull low (0 - 100k )

6-5132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 6.8.1 Pin Connection Diagram (CSIO Mode) The diagram below shows an example of a user system configuration which has had a serial programmer con- nected. After the user system is powered on, the serial programmer writes to the internal flash memory in clock- synchronous serial mode (CSIO mode). No communication problems associated with the oscillator frequency may occur. If the system uses any pins that are to be connected to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the addresses H’0000 0084 through H’0000 008F as an area in which to check the ID for flash memory protection. If the internal flash memory needs to be protected, set any ID in this area. VCC-BUS 32192/32195/32196 XOUT XIN JTRST MOD1 AVSS0 VSS RESET# FP MOD0 P84/SCLKI0/SCLKO0 P87/SCLKI1/SCLKO1 P86/RXD1 P85/TXD1 EXCVDD EXCVCC VREF0 AVCC0 VDDE VCCER Connect to the VCCE (5 or 3.3 V) power supply rail Main power supply Connect to the VCCE (5 or 3.3V) power supply rail Main power supply (for reference) RxD (input) TxD (output) SCLK0 (output) BUSY (input) MOD0 (output) FP (output) RESET (output) GND (common) ConnectorFlash programmer signals To system circuit Set microcomputer operating conditions User system board Note 1: SBI# must be fixed "H" or "L" to ensure that no interrupts will be generated. Notes:  Turn on the power for the user system before writing to the internal flash memory.  If P84-P87 are used in the system circuit, connection to a serial programmer must be taken into consideration.  The pullup resistance values of P84, P86 and P87 must be selected to suit the system design condition.  The typical pullup resistance values of P84, P86 and P87 are 4.7 to 10 kΩ.  The status of any other ports that are not shown here will not affect flash memory programming.  Make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes while rewriting the internal flash memory. MOD2 Connect to the user system power supply rail SBI#(Note 1) VCCE

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

6.9 Connecting to A Serial Programmer (UART Mode)

For the internal flash memory to be rewritten in boot mode + flash E/W enable mode by using a general-purpose serial programmer, several pins on the microcomputer must be processed to make them suitable for the serial programmer, as shown below. Table 6.9.1 Processing Microcomputer Pins before Using a Serial Programmer (UART Mode) Note: • Pin processing is not required for those that are not listed above. Pin Name Pin No. Function Remark SCLKI1 71 SIO mode selection Pull low ("L" level input) RXD1 70 Serial data input (received data) Pull high TXD1 69 Serial data output (transmit data) P84 68 General-purpose port input Not used during UART mode Pull high or pull low FP 94 Flash memory protect Pull high MOD0 92 Operation mode 0 Connect to the main power supply MOD1 93 Operation mode 1 Connect to ground MOD2 123 Operation mode 2 Connect to ground RESET# 91 Reset XIN 4 Clock input XOUT 5 Clock output SBI# 77 System Break Interrupt (SBI) input Pull high or low VREF0 42 Reference voltage input for A/D converter Connect to the main power supply AVCC0 43 Analog power supply Connect to the main power supply AVSS0 60 Analog ground Connect to ground VDDE 108 RAM backup power supply Connect to the main power supply VCCER 65 Power supply for the internal voltage generator circuit 5 V +/- 10% or 3.3 V +/- 10% VCCE 95, 132 Main power supply 5 V +/- 10% or 3.3 V +/- 10% EXCVCC 61, 137 Connects external capacitance for the internal power supply Need to be grounded to earth via capacitor EXCVDD 73 Connects external capacitance for the RAM power supply Need to be grounded to earth via capacitor VCC-BUS 6, 20 External bus power supply Depends on the target system VSS 3, 21, 62, 72, 96, 138 Ground 0V JTRST 111 JTAG reset input Pull low (0 - 100k )

6-5332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The diagram below shows an example of a user system configuration which has had a serial programmer con- nected. After the user system is powered on, the serial programmer writes to the internal flash memory in clock- asynchronous serial mode (UART mode). No communication problems associated with the oscillator frequency may occur. If the system uses any pins that are to be connected to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the addresses H’0000 0084 through H’0000 008F as an area in which to check the ID for flash memory protection. If the internal flash memory needs to be protected, set any ID in this area. 32192/32195/32196 XOUT XIN JTRST MOD1 MOD2 AVSS0 VSS RESET# FP MOD0 P84/SCLKI0/SCLKO0 P87/SCLKI1/SCLKO1 P86/RXD1 P85/TXD1 EXCVDD EXCVCC VCC-BUS VREF0 AVCC0 VDDE VCCER Connect to the VCCE (5 or 3.3 V) power supply rail Main power supply Connect to the VCCE (5 or 3.3V) power supply rail Main power supply (for reference) RxD (input) TxD (output) Mode selection (output) GND (common) ConnectorFlash programmer signals To system circuit Set microcomputer operating conditions User system board Connect to the user system power supply rail VCCE SBI#(Note 1) Note 1: SBI# must be fixed "H" or "L" to ensure that no interrupts will be generated. Notes:  Turn on the power for the user system before writing to the internal flash memory.  If P84-P87 are used in the system circuit, connection to a serial programmer must be taken into consideration.  The pullup/pulldown resistance values of P84, P86, P87, FP and MOD0 must be selected to suit the system design condition.  The typical pullup/pulldown resistance values of P84, P86, P87, FP and MOD0 are 4.7 to 10 kΩ.  The status of any other ports that are not shown here will not affect flash memory programming.  Make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes while rewriting the internal flash memory. Figure 6.9.1 Pin Connection Diagram (UART Mode)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The internal flash memory has the following four types of protect functions to prevent it from being inadvertently rewritten or illegally copied, programmed or erased. (1) Flash memory protect ID When using a tool to program/erase the internal flash memory such as a general-purpose programmer or emulator, the ID entered by a tool and the ID stored in the internal flash memory are collated. Unless the correct ID is entered, the internal flash memory cannot be read out, programmed nor erased. (For some tools, tool execution is enabled after erasing the entire flash memory area, and the internal flash memory becomes accessible for write.) (2) Protection by FP pin The internal flash memory is protected in hardware against programming/erase operation by pulling the FP (Flash Protect) pin "L". For systems that do not require rewriting flash memory or systems in which flash reprogramming is prohibited as in the case of automotive applications, make sure the FP pin is fixed "L" except when programming or erasing the internal flash memory. Furthermore, because the FP pin level can be known by reading the Flash Mode Register (FMOD)’s FPMOD (external FP pin status) bit in the flash write/erase program, the internal flash memory can also be protected in software. For systems that do not require protec- tion by setting external pins, the FP pin may be fixed "H" to simplify the operation to program/erase the internal flash memory. However, to prevent the flash memory from being inadvertently rewritten by an erratic operation in software, use the protection by a lock bit described in (4) below. When programming/erasing via JTAG, the flash memory can be programmed or erased regardless of the pin state because the FP pin is controlled internally within the chip. (3) Protection by FENTRY bit Flash E/W enable mode cannot be entered into unless the Flash Control Register 1 (FCNT1)’s FENTRY (flash mode entry) bit is set to "1." To set the FENTRY bit to "1," write "0" and then "1" in succession while the FP pin is "H." (4) Protection by a lock bit Any block of internal flash memory can be protected by setting the lock bit provided for it to "0." That memory block is disabled against programming/erase operation.

6-5532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Precautions about the Internal Memory is shown below.

• The writes from DRI,RTD to internal RAM uncompete with access from other bus masters (CPU, DMA, NBD, SDI), because of using dedicated bus not M32R-FPU. But in case DRI,RTD transfers and access from other bus masters for area in 16-Kbyte of internal RAM occur at same time, access competition occurs. When access competition occurs, arbitration is performed according to the following priority. NBD/SDI > DMA > CPU > DRI > RTD
• When started by boot mode, internal RAM value is indefinite after started by boot mode in order to "Flash writing/erasing program" is transferred to internal RAM.

The following describes precautions to be taken when programming/erasing the internal flash memory.

• When the internal flash memory is programmed or erased, a high voltage is generated internally. Because mode transitions during programming/erase operation may cause the chip to break down, make sure the mode setting/reset pin and power supply voltages do not fluctuate to prevent unintended changes of modes.
• If the system uses any pins that are to be used by a general-purpose programming/erase tool, care must be taken to prevent adverse effects on the system when the tool is connected.
• If the internal flash memory needs to be protected while using a general-purpose programming/erase tool, set any ID in the flash memory protect ID verification area (H’0000 0084 to H’0000 008F).
• If the internal flash memory does not need to be protected while using a general-purpose programming/erase tool, fill the entire flash memory protect ID verification area (H’0000 0084 to H’0000 008F) with H’FF.
• If the Flash Status Register (FSTAT)’s each error status is to be cleared (initialized to H’80) by resetting the Flash Control Register 4 (FCNT4) FRESET bit, check to see that the Flash Status Register (FSTAT) FBUSY bit = "1" (ready) before clearing the error status.
• Before resetting the Flash Control Register 1 (FCNT1) FENTRY bit from "1" to "0," check to see that the Flash Status Register (FSTAT) FBUSY bit = "1" (ready).
• Do not clear the FENTRY bit if the Flash Control Register 1 (FCNT1) FENTRY bit = "1" and the Flash Status Register (FSTAT) FBUSY bit = "0" (being programmed or erased).
• When programming/erasing via JTAG, the flash memory can be programmed or erased regardless of the pin state because the FP pin is controlled internally within the chip.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 This page is blank for reasons of layout.

7.1 Outline of Reset

7.2 Reset Operation

7.3 Internal State upon Exiting Reset

7.4 Things to Be Considered upon Exiting Reset

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The microcomputer is reset by applying a "L" level signal to the RESET# input pin. The microcomputer is gotten out of a reset state by releasing the RESET# input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the CPU starts executing from the reset vector entry. When a "L" level signal in width of more than 300 ns is applied to the RESET# pin, the microcomputer enters a reset state. At this time, the internal circuits (including the CPU) are reset. (For details about the pin state when reset, see Table 1.4.1, “Pin Assignments of the M32192F8xFP, M32195F4xFP,and M32196F8xFP” and Table 1.4.2 "Pin Assignments of the M32192F8xWG") When the RESET# input is returned "H," the internal circuits get out of a reset state (2333 to 2334 BCLK) periods after that. Internal circuit reset signal Flip-flop Counter RESET# Extended for a duration during which the RESET# input is held "L" 2333 to 2334 BCLK RESET# pin Reset signal (internal signal) past the noise canceller Internal circuit reset signal (internal signal) Duration needed for noise cancellation(50 to 300ns) Figure 7.2.2 Reset Sequence Figure 7.2.1 Reset Circuit

7-332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

7.2.1 Reset at Power-on

When powering on the microcomputer, hold the RESET# signal input pin "L" until the rated power supply voltage is reached and the microcomputer’s internal x8 clock generator becomes oscillating stably. For details, see Section 22.2, "Power-On Sequence."

7.2.2 Reset during Operation

To reset the microcomputer during operation, hold the RESET# signal input pin "L" for more than 300 ns.

7.2.3 Reset Vector Relocation during Flash Programming

When the microcomputer is reset after entering boot mode, the reset vector entry address is moved to the boot program startup address. The boot program starts running after the reset state is deasserted. For details, see Section 6.6, “Programming the Internal Flash Memory.”

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The table below lists the internal state of the microcomputer when it has gotten out of a reset state. For details about the initial register state of each internal peripheral I/O, see each section in this manual in which the relevant internal peripheral I/O is described. Table 7.3.1 Internal State upon Exiting Reset Register State upon exiting reset PSW (CR0) B'0000 0000 0000 0000 ??00 000? 0000 0000 (BSM, BIE, BC bits = undefined) CBR (CR1) H'0000 0000 (C bits = 0) SPI (CR2) Undefined SPU (CR3) Undefined BPC (CR6) Undefined FPSR (CR7) H'0000 0100 (only DN bit = 1) PC H'0000 0000 (Executed beginning with the address H’0000 0000) (Note 1) R0–R15 Undefined ACC (accumulator) Undefined RAM Undefined when reset at power-on. (However, if the RAM is gotten out of reset after returning from backup mode, it retains the content it had before being reset.) Note 1: When in boot mode, the CPU executes the boot program.

• Input/output ports When exiting reset, the microcomputer’s input/output ports are disabled against input in order to prevent shoot- through current. To use any ports in input mode, set the Port Input Special Function Control Register (PICNT) PIEN0 bit to enable them for input. For details, see Section 8.3, “Input/Output Port Related Registers.”

8.1 Outline of Input/Output Ports

8.2 Selecting Pin Functions

8.3 Input/Output Port Related Registers

8.4 Port Input Level Switching Function

8.5 Port Output Drive Capability Setting Function

8.6 Noise Canceller Control Function

8.7 Port Peripheral Circuits

8.8 Notes on Input/Output Ports

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The 32192/32195/32196 has a total of 97 input/output ports from P0–P13, P15, P17 and P22 (except P5, which is reserved for future use). These input/output ports can be used as input or output ports by setting the respective direction registers. Each input/output port has double or triple functions shared with other internal peripheral I/O or external bus interface related signal lines, or multiple functions shared with multi-function peripheral I/Os. Pin functions are selected depending on the operation mode of the CPU or by setting the operation mode register and peripheral function select register for the input/output port. (If any internal peripheral I/O has still another function, it is also necessary to set the register provided for that internal peripheral I/O.) Abundant port functions are incorporated, including a port input level switching function, port output drive capa- bility setting function, and noise canceller control function. Note that before any ports can be used in input mode, this port input function enable bit must be set accordingly. The input/output ports are outlined below. Table 8.1.1 Outline of Input/Output Ports Item Specification Number of ports Total 97 ports P0 : P00–P07 (8 ports) P1 : P10–P17 (8 ports) P2 : P20–P27 (8 ports) P3 : P30–P37 (8 ports) P4 : P41–P47 (7 ports) P6 : P61–P63 (3 ports) P7 : P70–P77 (8 ports) P8 : P82–P87 (6 ports) P9 : P93–P97 (5 ports) P10 : P100–P107 (8 ports) P11 : P110–P117 (8 ports) P12 : P124–P127 (4 ports) P13 : P130–P137 (8 ports) P15 : P150, P153 (2 ports) P17 : P174, P175 (2 ports) P22 : P220, P221, P224, P225 (4 ports) Port function The input/output ports can individually be set for input or output mode using the direction control register provided for each input/output port. (However, P221 is an input-only port.) Pin function Shared with peripheral I/O or external bus interface signals to serve dual-functions (or shared with two or more peripheral I/O functions to serve multiple functions) Note: • P5, P14, P16, P18-P21 are nonexist.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Each input/output port has double or triple functions shared with other internal peripheral I/O or external bus interface related signal lines, or multiple functions shared with multi-function peripheral I/Os. Pin functions are selected depending on the operation mode of the CPU or by setting the operation mode register and peripheral function select register for the input/output port. (If any internal peripheral I/O has still another function, it is also necessary to set the register provided for that internal peripheral I/O.) P0–P4, P124, P125, P224 and P225, when the CPU is set to operate in processor mode, all are switched to serve as signal pins for external access. The CPU operation mode is determined depending on how the MOD0 and MOD1 pins are set (see the table below). Table 8.2.1 CPU Operation Modes and P0–P4, P124, P125, P224 and P225 Pin Functions MOD0 MOD1 Operation Mode P0–P4, P124, P125, P224 and P225 Pin Function VSS VSS Single-chip mode Input/output port pin VSS VCCE External extension mode Input/output port or external bus interface signal pin (Note 1) VCCE VSS Processor mode External bus interface signal pin VCCE VCCE (Settings inhibited) – Note 1: P41–P43 only function as external bus interface signal pins. Note: • VCCE and VSS are connected to main power supply and GND, respectively. Each input/output port has their functions switched between input/output port pins and internal peripheral I/O pins by setting the respective port operation mode and peripheral function select registers. If any internal periph- eral I/O has two or more pin functions, use the register provided for that internal peripheral I/O to select the desired pin function. Note that FP pin operations during internal flash memory programming do not affect the pin functions.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-4 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 8.2.1 Input/Output Ports and Pin Function Assignments during Single Chip Mode 0 1 2 3 4 5 6 7 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 TIN16 / TIN17 / TIN20 / TIN18 / TIN19 / TIN21 / TIN22 / TIN23 / PWMOFF0 / PWMOFF1 / TXD3 / DIN2 DIN3 RXD3 CRX1 CTX1 DIN0 DIN1 DIN4 TO21 / TO22 / TO23 / TO24 / TO25 / TO26 / TO27 / TO28 / DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 CLKOUT / RTDTXD / RTDRXD / RTDACK / RTDCLK / HREQ# / HACK# / WR# / WAIT# TXD3 / RXD3 / CTX1 / CRX1 / TIN27 TIN26 BCLK( Note 2) NBDD0 NBDD1 NBDD2 NBDD3 TO29 / TO30 / TO31 / TO32 / TO33 / TO34 / TO35 / TO36 / DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 TCLK0 / TCLK1 / TCLK2 / TCLK3 / DD3 DD2 DD1 DD0 TIN0 / TIN3 / CLKOUT / WAIT# WR#( Note 2) TO0 / TO1 / TO2 / TO3 / TO4 / TO5 / TO6 / TO7 / TO29 / TO30 / TO31 / TO32 / TO33 / TO34 / TO35 / TO36 / DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 TIN4 / TIN5 / TIN6 / TIN7 / TIN30 / TIN31 / TIN32 / TIN33 / DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 TO12 / TO14 / TO15 / TO9 / TO10 / TO11 / TO8 TIN25 / TXD4 / RXD4 / CRX0 CTX0 TIN24 DD3 DD1 DD0 T O 1 3 / SCLKI4 / SCLKO4 D D 2 SCLKI0 / SCLKI1 / MOD0 MOD1 TXD0 / RXD0 / TXD1 / RXD1 / SCLKO0 / SCLKO1 / Note 1) ( Note 1) TO26 TO25 TO23 TO22 TO24 TO21 TO16 / TO17 / TO18 / TO19 / TO20 / SCLKI5 / TXD5 / RXD5 / DD13 DD12 SCLKO5 DD15 DD14 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31 P41 P42 P43 TIN8 TIN9 TIN10 TIN11 Port only) ( Port only) ( Port only) P61 P62 P63 SBI# Port only) ( Port only) ( Port only) ( Note 1) TXD2 / RXD2 / TO28 TO27 CTX0 / CRX0 / P224 P225 HACK# HREQ# ( Port only) (Port only) Pin functions are selected by the settings for the port operation mode and port peripheral function select registers Pin functions are selected by the settings for the port operation mode, port peripheral function select and NBD function select registers Note 1: These ports cannot be used for input/output port function. The SBI#, MOD0 and MOD1 pin input levels can be read from these ports. Note 2: Respective functions are selected by the Bus Mode Control Register. Notes: • P5, P14, P16, P18, P19, P20 and P21 are not provided.  Some functions have two separate pins assigned per function. For details, see Table 8.2.2.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 8.2.2 Input/Output Ports and Pin Function Assignments during External Extension Mode 0 1 2 3 4 5 6 7 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 TIN16 / TIN17 / TIN20 / TIN18 / TIN19 / TIN21 / TIN22 / TIN23 / PWMOFF0 / PWMOFF1 / TXD3 / DIN2 DIN3 RXD3 CRX1 CTX1 DIN0 DIN1 DIN4 DB0 / DB1 / DB2 / DB3 / DB4 / DB5 / DB6 / DB7 / TO21 / TO22 / TO23 / TO24 / TO25 / TO26 / TO27 / TO28 / DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 BLW# / BHW# / RD# CS0# / CS1# / A13 / A14 / BLE# BHE# ( Note 1) TIN8 TIN9 TIN10 TIN11 ( Note 1, 3) (Note 1, 3) CLKOUT / RTDTXD / RTDRXD / RTDACK / RTDCLK / HREQ# / HACK# / WR# / WAIT# TXD3 / RXD3 / CTX1 / CRX1 / TIN27 TIN26 BCLK (Note 3) NBDD0 NBDD1 NBDD2 NBDD3 DB8 / DB9 / DB10 / DB11 / DB12 / DB13 / DB14 / DB15 / TO29 / TO30 / TO31 / TO32 / TO33 / TO34 / TO35 / TO36 / DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 TCLK0 / TCLK1 / TCLK2 / TCLK3 / A9 / A10 / CS2# / CS3# / DD3 DD2 DD1 DD0 TIN0 / TIN3 / CLKOUT / WAIT# WR# (Note 3) TO0 / TO1 / TO2 / TO3 / TO4 / TO5 / TO6 / TO7 / TO29 / TO30 / TO31 / TO32 / TO33 / TO34 / TO35 / TO36 / DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 A15 / A16 / A17 / A18 / A19 / A20 / A21 / A22 / TIN4 / TIN5 / TIN6 / TIN7 / TIN30 / TIN31 / TIN32 / TIN33 / DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 TO12 / TO14 / TO15 / TO9 / TO10 / TO11 / TO8 TIN25 / TXD4 / RXD4 / CRX0 CTX0 TIN24 DD3 DD1 DD0 T O 1 3 / SCLKI4 / SCLKO4 D D 2 SCLKI0 / SCLKI1 / MOD0 MOD1 TXD0 / RXD0 / TXD1 / RXD1 / SCLKO0 / SCLKO1 / (Note 2) (Note 2) TO26 TO25 TO23 TO22 TO24 TO21 TO16 / TO17 / TO18 / TO19 / TO20 / SCLKI5 / TXD5 / RXD5 / DD13 DD12 SCLKO5 DD15 DD14 A23 / A24 / A25 / A26 / A27 / A28 / A29 / A30 / DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31 P61 P62 P63 SBI# (Port only) (Port only) (Port only) (Note 2) TXD2 / RXD2 / TO28 TO27 CTX0 / CRX0 / A11 / A12 / HACK# HREQ# CS2# CS3# Note 1: These ports cannot be used for input/output port function, function as external bus interface related signals. Note 2: These ports cannot be used for input/output port function. The SBI#, MOD0 and MOD1 pin input levels can be read from these ports. Note 3: Respective functions are selected by the Bus Mode Control Register. Notes:  P5, P14, P16, P18, P19, P20 and P21 are not provided.  Some functions have two separate pins assigned per function. For details, see Table 8.2.2. Pin functions are selected by the settings for the port operation mode and port peripheral function select registers Pin functions are selected by the settings for the port operation mode, port peripheral function select and NBD function select registers

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-6 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 8.2.3 Input/Output Ports and Pin Function Assignments during Processor Mode (Note 1) TIN16 / TIN17 / TIN20 / TIN18 / TIN19 / TIN21 / TIN22 / TIN23 / PWMOFF0 / PWMOFF1 / TXD3 / DIN2 DIN3 RXD3 CRX1 CTX1 DIN0 DIN1 DIN4 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 CLKOUT / RTDTXD / RTDRXD / RTDACK / RTDCLK / HREQ# / HACK# / WR# / WAIT# TXD3 / RXD3 / CTX1 / CRX1 / TIN27 TIN26 BCLK( Note 3) NBDD0 NBDD1 NBDD2 NBDD3 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 TCLK2 / TCLK3 / A9 A10 CS2# / CS3# / (Note 1) (Note 1) DD1 DD0 TIN0 / TIN3 / CLKOUT / WAIT# WR#( Note 3) TO0 / TO1 / TO2 / TO3 / TO4 / TO5 / TO6 / TO7 / TO29 / TO30 / TO31 / TO32 / TO33 / TO34 / TO35 / TO36 / DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 A15 A16 A17 A18 A19 A20 A21 A22 TO12 / TO14 / TO15 / TO9 / TO10 / TO11 / TO8 TIN25 / TXD4 / RXD4 / CRX0 CTX0 TIN24 DD3 DD1 DD0 T O 1 3 / SCLKI4 / SCLKO4 D D 2 SCLKI0 / SCLKI1 / MOD0 MOD1 TXD0 / RXD0 / TXD1 / RXD1 / SCLKO0 / SCLKO1 / (Note 2) (Note 2) TO26 TO25 TO23 TO22 TO24 TO21 TO16 / TO17 / TO18 / TO19 / TO20 / SCLKI5 / TXD5 / RXD5 / DD13 DD12 SCLKO5 DD15 DD14 A23 A24 A25 A26 A27 A28 A29 A30 BLW# / BHW# / RD# CS0# CS1# A13 A14 BLE#( Note 3) BHE#(Note 3) P61 P62 P63 SBI# (Port only) (Port only) (Port only) (Note 2) TXD2 / RXD2 / TO28 TO27 CTX0 / CRX0 / A11/CS2# A12/CS3# HACK# HREQ# (Note 1) (Note 1) Pin functions are selected by the settings for the port operation mode, port peripheral function select and NBD function select registers Note 1: These ports cannot be used for input/output port function, function as external bus interface related signals. Note 2: These ports cannot be used for input/output port function. The SBI#, MOD0 and MOD1 pin input levels can be read from these ports. Note 3: Respective functions are selected by the Bus Mode Control Register. Notes:  P5, P14, P16, P18, P19, P20 and P21 are not provided.  Some functions have two separate pins assigned per function. For details, see Table 8.2.2. 0 1 2 3 4 5 6 7

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 One peripheral I/O can be assigned to two separate pins by setting the CPU operation mode and peripheral function select register. Table 8.2.2 Peripheral I/Os Allowed for Input/Output at Two Pins and Pin Assignments (1/2) Module Signal name Pin group A Pin group B Note DRI DD0 P127/TCLK3/CS3#/DD0 P00/DB0/TO21/DD0 P107/TO15/RXD4/DD0 DD1 P126/TCLK2/CS2/DD1 P01/DB1/TO22/DD1 P106/TO14/TXD4/DD1 DD2 P125/TCLK1/A10/DD2 P02/DB2/TO23/DD2 P105/TO13/SCLKI4/SCLKO4/DD2 DD3 P124/TCLK0/A9/DD3 P03/DB3/TO24/DD3 P104/TO12/TIN25/DD3 DD4 P117/TO7/TO36/DD4 P04/DB4/TO25/DD4 DD5 P116/TO6/TO35/DD5 P05/DB5/TO26/DD5 DD6 P115/TO5/TO34/DD6 P06/DB6/TO27/DD6 DD7 P114/TO4/TO33/DD7 P07/DB7/TO28/DD7 DD8 P113/TO3/TO32/DD8 P10/DB8/TO29/DD8 DD9 P112/TO2/TO31/DD9 P11/DB9/TO30/DD9 DD10 P111/TO1/TO30/DD10 P12/DB10/TO31/DD10 DD11 P110/TO0/TO29/DD11 P13/DB11/TO32/DD11 DD12 P97/TO20/DD12 P14/DB12/TO33/DD12 DD13 P96/TO19/DD13 P15/DB13/TO34/DD13 DD14 P95/TO18/RXD5/DD14 P16/DB14/TO35/DD14 DD15 P94/TO17/TXD5/DD15 P17/DB15/TO36/DD15 TOU TO21 P87/SCLKI1/SCLKO1/TO21 P00/DB0/TO21/DD0 TO22 P86/RXD1/TO22 P01/DB1/TO22/DD1 TO23 P85/TXD1/TO23 P02/DB2/TO23/DD2 TO24 P84/SCLKI0/SCLKO0/TO24 P03/DB3/TO24/DD3 TO25 P83/RXD0/TO25 P04/DB4/TO25/DD4 TO26 P82/TXD0/TO26 P05/DB5/TO26/DD5 TO27 P175/RXD2/TO27 P06/DB6/TO27/DD6 TO28 P174/TXD2/TO28 P07/DB7/TO28/DD7 TO29 P110/TO0/TO29/DD11 P10/DB8/TO29/DD8 TO30 P111/TO1/TO30/DD10 P11/DB9/TO30/DD9 TO31 P112/TO2/TO31/DD9 P12/DB10/TO31/DD10 TO32 P113/TO3/TO32/DD8 P13/DB11/TO32/DD11 TO33 P114/TO4/TO33/DD7 P14/DB12/TO33/DD12 TO34 P115/TO5/TO34/DD6 P15/DB13/TO34/DD13 TO35 P116/TO6/TO35/DD5 P16/DB14/TO35/DD14 TO36 P117/TO7/TO36/DD4 P17/DB15/TO36/DD15 SIO TXD3 P134/TIN20/TXD3/DIN4 P74/RTDTXD/TXD3/NBDD0 RXD3 P135/TIN21/RXD3 P75/RTDRXD/RXD3/NBDD1 CAN CTX0 P102/TO10/CTX0 P220/CTX0/HACK# CRX0 P101/TO9/CRX0 P221/CRX0/HREQ# CTX1 P137/TIN23/CTX1 P76/RTDACK/CTX1/NBDD2 CRX1 P136/TIN22/CRX1 P77/RTDCLK/CRX1/NBDD3 (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) (Note 1)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-8 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 8.2.2 Peripheral I/Os Allowed for Input/Output at Two Pins and Pin Assignments (2/2) Module Signal name Pin group A Pin group B Note (External bus CS2# P126/TCLK2/CS2#/DD1 P224/A11/CS2# interface CS3# P127/TCLK3/CS3#/DD0 P225/A12/CS3# related) CLKOUT P150/TIN0/CLKOUT/WR# P70/CLKOUT/WR#/BCLK WR# P150/TIN0/CLKOUT/WR# P70/CLKOUT/WR#/BCLK WAIT# P153/TIN3/WAIT# P71/WAIT# HACK# P220/CTX0/HACK# P73/HACK#/TIN26 HREQ# P221/CRX0/HREQ# P72/HREQ#/TIN27 Note 1: If Pin group A and Pin group B have the same internal peripheral input pin set, the setting for Pin group A comes into effect so that input from Pin group A is accepted as input for the relevant internal peripheral I/O. For the 16 high-order DD input bits of the DRI (DD0–DD15), which pins to use can be selected in the DRI related register. (For details, refer to the Chapter 14, "Direct RAM Interface.") Note 2: If Pin group A and Pin group B have the same internal peripheral input pin set, the signal is output from both pins. (Note 1) (Note 2) (Note 1) (Note 2)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The tables below show an input/output port related register map. Input/Output Port Related Register Map (1/3) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0500 Port Group 0,1 Input Level Setting Register Port Group 3 Input Level Setting Register 8-33 (PG01LEV) (PG3LEV) H'0080 0502 Port Group 4,5 Input Level Setting Register Port Group 6,7 Input Level Setting Register 8-33 (PG45LEV) (PG67LEV) H'0080 0504 Port Group 8 Input Level Setting Register (Use inhibited area) 8-33 (PG8LEV) H'0080 0506 (Use inhibited area) H'0080 0508 Port Group 0,1 Output Drive Capability Setting Register Port Group 3 Output Drive Capability Setting Register 8-35 (PG01DRV) (PG3DRV) H'0080 050A Port Group 4,5 Output Drive Capability Setting Register Port Group 6,7 Output Drive Capability Setting Register 8-35 (PG45DRV) (PG67DRV) H'0080 050C Port Group 8 Output Drive Capability Setting Register P70 Output Drive Capability Setting Register 8-35 (PG8DRV) (P70DRV) 8-36 H'0080 050E (Use inhibited area) H'0080 0510 Noise Canceller Control Register 8-38 (NZCNSLCR) H'0080 0700 P0 Data Register P1 Data Register 8-12 (P0DATA) (P1DATA) H'0080 0702 P2 Data Register P3 Data Register 8-12 (P2DATA) (P3DATA) H'0080 0704 P4 Data Register (Use inhibited area) 8-12 (P4DATA) H'0080 0706 P6 Data Register P7 Data Register 8-12 (P6DATA) (P7DATA) H'0080 0708 P8 Data Register P9 Data Register 8-12 (P8DATA) (P9DATA) H'0080 070A P10 Data Register P11 Data Register 8-12 (P10DATA) (P11DATA) H'0080 070C P12 Data Register P13 Data Register 8-12 (P12DATA) (P13DATA) H'0080 070E (Use inhibited area) P15 Data Register 8-12 (P15DATA) H'0080 0710 (Use inhibited area) P17 Data Register 8-12 (P17DATA) (Use inhibited area) H'0080 0716 P22 Data Register (Use inhibited area) 8-12 (P22DATA) (Use inhibited area)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-10 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Input/Output Port Related Register Map (2/3) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0720 P0 Direction Register P1 Direction Register 8-13 (P0DIR) (P1DIR) H'0080 0722 P2 Direction Register P3 Direction Register 8-13 (P2DIR) (P3DIR) H'0080 0724 P4 Direction Register (Use inhibited area) 8-13 (P4DIR) H'0080 0726 P6 Direction Register P7 Direction Register 8-13 (P6DIR) (P7DIR) H'0080 0728 P8 Direction Register P9 Direction Register 8-13 (P8DIR) (P9DIR) H'0080 072A P10 Direction Register P11 Direction Register 8-13 (P10DIR) (P11DIR) H'0080 072C P12 Direction Register P13 Direction Register 8-13 (P12DIR) (P13DIR) H'0080 072E (Use inhibited area) P15 Direction Register 8-13 (P15DIR) H'0080 0730 (Use inhibited area) P17 Direction Register 8-13 (P17DIR) (Use inhibited area) H'0080 0736 P22 Direction Register (Use inhibited area) 8-13 (P22DIR) (Use inhibited area) H'0080 0740 P0 Operation Mode Register P1 Operation Mode Register 8-14 (P0MOD) (P1MOD) 8-15 H'0080 0742 P2 Operation Mode Register P3 Operation Mode Register 8-16 (P2MOD) (P3MOD) 8-17 H'0080 0744 P4 Operation Mode Register Port Input Special Function Control Register 8-18 (P4MOD) (PICNT) 8-29 H'0080 0746 (Use inhibited area) P7 Operation Mode Register 8-19 (P7MOD) H'0080 0748 P8 Operation Mode Register P9 Operation Mode Register 8-20 (P8MOD) (P9MOD) 8-21 H'0080 074A P10 Operation Mode Register P11 Operation Mode Register 8-22 (P10MOD) (P11MOD) 8-23 H'0080 074C P12 Operation Mode Register P13 Operation Mode Register 8-24 (P12MOD) (P13MOD) 8-25 H'0080 074E (Use inhibited area) P15 Operation Mode Register 8-26 (P15MOD) H'0080 0750 (Use inhibited area) P17 Operation Mode Register 8-27 (P17MOD) (Use inhibited area) H'0080 0756 P22 Operation Mode Register (Use inhibited area) 8-28 (P22MOD) (Use inhibited area)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Input/Output Port Related Register Map (3/3) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0760 P0 Peripheral Function Select Register P1 Peripheral Function Select Register 8-14 (P0SMOD) (P1SMOD) 8-15 H'0080 0762 (Use inhibited area) P3 Peripheral Function Select Register 8-17 (P3SMOD) H'0080 0764 P4 Peripheral Function Select Register (Use inhibited area) 8-18 (P4SMOD) H'0080 0766 (Use inhibited area) P7 Peripheral Function Select Register 8-19 (P7SMOD) H'0080 0768 P8 Peripheral Function Select Register P9 Peripheral Function Select Register 8-20 (P8SMOD) (P9SMOD) 8-21 H'0080 076A P10 Peripheral Function Select Register P11 Peripheral Function Select Register 8-22 (P10SMOD) (P11SMOD) 8-23 H'0080 076C P12 Peripheral Function Select Register P13 Peripheral Function Select Register 8-24 (P12SMOD) (P13SMOD) 8-25 H'0080 076E (Use inhibited area) P15 Peripheral Function Select Register 8-26 (P15SMOD) H'0080 0770 (Use inhibited area) P17 Peripheral Function Select Register 8-27 (P17SMOD) (Use inhibited area) H'0080 0776 P22 Peripheral Function Select Register (Use inhibited area) 8-28 (P22SMOD)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-12 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

8.3.1 Port Data Registers

P0 Data Register (P0DATA) <Address: H’0080 0700> P1 Data Register (P1DATA) <Address: H’0080 0701> P2 Data Register (P2DATA) <Address: H’0080 0702> P3 Data Register (P3DATA) <Address: H’0080 0703> P4 Data Register (P4DATA) <Address: H’0080 0704> P6 Data Register (P6DATA) <Address: H’0080 0706> P7 Data Register (P7DATA) <Address: H’0080 0707> P8 Data Register (P8DATA) <Address: H’0080 0708> P9 Data Register (P9DATA) <Address: H’0080 0709> P10 Data Register (P10DATA) <Address: H’0080 070A> P11 Data Register (P11DATA) <Address: H’0080 070B> P12 Data Register (P12DATA) <Address: H’0080 070C> P13 Data Register (P13DATA) <Address: H’0080 070D> P15 Data Register (P15DATA) <Address: H’0080 070F> P17 Data Register (P17DATA) <Address: H’0080 0711> P22 Data Register (P22DATA) <Address: H’0080 0716> Note: • n = 0–13, 15, 17, 22 (not including P5) <Upon exiting reset: Undefined> b Bit Name Function R W 0(8) Pn0DT <At read> R W Port Pn0 data bit Depends on how the Port Direction Register is set 1(9) Pn1DT If direction bit = "0" (input mode) Port Pn1 data bit 0: Port input pin = "L" 2(10) Pn2DT 1: Port input pin = "H" Port Pn2 data bit If direction bit = "1" (output mode) (Note 1) 3(11) Pn3DT 0: Port output latch = "0" / Port pin level = "L" Port Pn3 data bit 1: Port output latch = "1" / Port pin level = "H" 4(12) Pn4DT <At write> Port Pn4 data bit Write to the port output latch 5(13) Pn5DT Port Pn5 data bit 6(14) Pn6DT Port Pn6 data bit 7(15) Pn7DT Port Pn7 data bit Note 1: To select the port data to read, use the Port Input Special Function Control Register’s port input data select bit (PIS EL). Notes: • Following bits are not provided (read as "0," writing has no effect): P40, P60, P65–P67, P90–P92, P120–P123, P151, P152, P154–P157, P170–P173, P176, P177, P222, P223, P226, P227

• The SBI# pin input level can be read out by reading the P64DT bit. Writing to the P64DT bit has no effect.
• The MOD0 and MOD1 pin input levels can be read out by reading the P80DT and P81DT bits, respectively. Writing to the P80DT and P81DT bits has no effect.
• P221 is an input-only port. Writing to the P221DT bit has no effect.

(b8 9 10 11 12 13 14 b15) Pn0DT Pn1DT Pn2DT Pn3DT Pn4DT Pn5DT Pn6DT Pn7DT

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

8.3.2 Port Direction Registers

P0 Direction Register (P0DIR) <Address: H’0080 0720> P1 Direction Register (P1DIR) <Address: H’0080 0721> P2 Direction Register (P2DIR) <Address: H’0080 0722> P3 Direction Register (P3DIR) <Address: H’0080 0723> P4 Direction Register (P4DIR) <Address: H’0080 0724> P6 Direction Register (P6DIR) <Address: H’0080 0726> P7 Direction Register (P7DIR) <Address: H’0080 0727> P8 Direction Register (P8DIR) <Address: H’0080 0728> P9 Direction Register (P9DIR) <Address: H’0080 0729> P10 Direction Register (P10DIR) <Address: H’0080 072A> P11 Direction Register (P11DIR) <Address: H’0080 072B> P12 Direction Register (P12DIR) <Address: H’0080 072C> P13 Direction Register (P13DIR) <Address: H’0080 072D> P15 Direction Register (P15DIR) <Address: H’0080 072F> P17 Direction Register (P17DIR) <Address: H’0080 0731> P22 Direction Register (P22DIR) <Address: H’0080 0736> Note: • n = 0–13, 15, 17, 22 (not including P5) <Upon exiting reset: H’00> b Bit Name Function R W 0(8) Pn0DR 0: Input mode R W Port Pn0 direction bit 1: Output mode 1(9) Pn1DR Port Pn1 direction bit 2(10) Pn2DR Port Pn2 direction bit 3(11) Pn3DR Port Pn3 direction bit 4(12) Pn4DR Port Pn4 direction bit 5(13) Pn5DR Port Pn5 direction bit 6(14) Pn6DR Port Pn6 direction bit 7(15) Pn7DR Port Pn7 direction bit Notes: • Following bits are not provided (read as 0, writing has no effect): P40, P60, P64–P67, P80, P81, P90–P92, P120–P123, P151, P152, P154–P157, P170–P173, P176, P177, P222, P223, P226, P227

• All ports are set for input mode upon exiting the reset state.
• P221 is an input-only port. Fix it to "0" when write.
• After switching from output mode to input mode in the Port Direction Register, or after setting port input enable (PIEN0) bit to "1" (input enable), pin level can be read after 2BCLK period. b 0 123456 b 7 (b8 9 10 11 12 13 14 b15) Pn0DR Pn1DR Pn2DR Pn3DR Pn4DR Pn5DR Pn6DR Pn7DR 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-14 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

8.3.3 Port Operation Mode and Port Peripheral Function Select Registers

P0 Operation Mode Register (P0MOD) <Address: H’0080 0740> <Upon exiting reset: H’00> b Bit Name Function R W

0 P00MD 0: P00/DD0 (Note 1) R W

Port P00 operation mode bit 1: DB0/TO21 (Note 2)

1 P01MD 0: P01/DD1 (Note 1) R W

Port P01 operation mode bit 1: DB1/TO22 (Note 2)

2 P02MD 0: P02/DD2 (Note 1) R W

Port P02 operation mode bit 1: DB2/TO23 (Note 2)

3 P03MD 0: P03/DD3 (Note 1) R W

Port P03 operation mode bit 1: DB3/TO24 (Note 2)

4 P04MD 0: P04/DD4 (Note 1) R W

Port P04 operation mode bit 1: DB4/TO25 (Note 2)

5 P05MD 0: P05/DD5 (Note 1) R W

Port P05 operation mode bit 1: DB5/TO26 (Note 2)

6 P06MD 0: P06/DD6 (Note 1) R W

Port P06 operation mode bit 1: DB6/TO27 (Note 2)

7 P07MD 0: P07/DD7 (Note 1) R W

Port P07 operation mode bit 1: DB7/TO28 (Note 2) Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input. Note 2: Which function of the pin is used depends on how the P0 Peripheral Function Select Register is set. Note: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (DB0-DB7). P00MD P01MD P02MD P03MD P04MD P05MD P06MD P07MD 00000000 P0 Peripheral Function Select Register (P0SMOD) <Address: H’0080 0760> <Upon exiting reset: H’00> b Bit Name Function R W

0 P00SMD 0: DB0 R W

Port P00 peripheral function select bit 1: TO21

1 P01SMD 0: DB1 R W

Port P01 peripheral function select bit 1: TO22

2 P02SMD 0: DB2 R W

Port P02 peripheral function select bit 1: TO23

3 P03SMD 0: DB3 R W

Port P03 peripheral function select bit 1: TO24

4 P04SMD 0: DB4 R W

Port P04 peripheral function select bit 1: TO25

5 P05SMD 0: DB5 R W

Port P05 peripheral function select bit 1: TO26

6 P06SMD 0: DB6 R W

Port P06 peripheral function select bit 1: TO27

7 P07SMD 0: DB7 R W

Port P07 peripheral function select bit 1: TO28 Notes: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (DB0-DB7).

• The value of this register can only be modified when the corresponding P0 operation mode register bit = 0 (set for port). Then set the corresponging P0 operation mode register bit to "1."
• During single-chip mode, selecting the external bus interface function is prohibited. b 0 123456 b 7 P00SMD P01SMD P02SMD P03SMD P04SMD P05SMD P06SMD P07SMD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P1 Operation Mode Register (P1MOD) <Address: H’0080 0741> <Upon exiting reset: H’00> b Bit Name Function R W

8 P10MD 0: P10/DD8 (Note 1) R W

Port P10 operation mode bit 1: DB8/TO29 (Note 2)

9 P11MD 0: P11/DD9 (Note 1) R W

Port P11 operation mode bit 1: DB9/TO30 (Note 2)

10 P12MD 0: P12/DD10 (Note 1) R W

Port P12 operation mode bit 1: DB10/TO31 (Note 2)

11 P13MD 0: P13/DD11 (Note 1) R W

Port P13 operation mode bit 1: DB11/TO32 (Note 2)

12 P14MD 0: P14/DD12 (Note 1) R W

Port P14 operation mode bit 1: DB12/TO33 (Note 2)

13 P15MD 0: P15/D13 (Note 1) R W

Port P15 operation mode bit 1: DB13/TO34 (Note 2)

14 P16MD 0: P16/DD14 (Note 1) R W

Port P16 operation mode bit 1: DB14/TO35 (Note 2)

15 P17MD 0: P17/DD15 (Note 1) R W

Port P17 operation mode bit 1: DB15/TO36 (Note 2) Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input. Note 2: Which function of the pin is used depends on how the P1 Peripheral Function Select Register is set. Note: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (DB8-DB15). b 8 9 1 01 11 21 31 4 b 1 5 P10MD P11MD P12MD P13MD P14MD P15MD P16MD P17MD 00000000 P1 Peripheral Function Select Register (P1SMOD) <Address: H’0080 0761> <Upon exiting reset: H’00> b Bit Name Function R W

8 P10SMD 0: DB8 R W

Port P10 peripheral function select bit 1: TO29

9 P11SMD 0: DB9 R W

Port P11 peripheral function select bit 1: TO30

10 P12SMD 0: DB10 R W

Port P12 peripheral function select bit 1: TO31

11 P13SMD 0: DB11 R W

Port P13 peripheral function select bit 1: TO32

12 P14SMD 0: DB12 R W

Port P14 peripheral function select bit 1: TO33

13 P15SMD 0: DB13 R W

Port P15 peripheral function select bit 1: TO34

14 P16SMD 0: DB14 R W

Port P16 peripheral function select bit 1: TO35

15 P17SMD 0: DB15 R W

Port P17 peripheral function select bit 1: TO36 Notes: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (DB8-DB15).

• The value of this register can only be modified when the corresponding P1 operation mode register bit = 0 (set for port). Then set the corresponging P1 operation mode register bit to "1."
• During single-chip mode, selecting the external bus interface function is prohibited. b 8 9 1 01 11 21 31 4 b 1 5 P10SMD P11SMD P12SMD P13SMD P14SMD P15SMD P16SMD P17SMD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-16 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456 b 7 P20MD P21MD P22MD P23MD P24MD P25MD P26MD P27MD 00000000 P2 Operation Mode Register (P2MOD) <Address: H’0080 0742> <Upon exiting reset: H’00> b Bit Name Function R W

0 P20MD 0: P20/DD24 (Note 1) R W

Port P20 operation mode bit 1: A23

1 P21MD 0: P21/DD25 (Note 1) R W

Port P21 operation mode bit 1: A24

2 P22MD 0: P22/DD26 (Note 1) R W

Port P22 operation mode bit 1: A25

3 P23MD 0: P23/DD27 (Note 1) R W

Port P23 operation mode bit 1: A26

4 P24MD 0: P24/DD28 (Note 1) R W

Port P24 operation mode bit 1: A27

5 P25MD 0: P25/DD29 (Note 1) R W

Port P25 operation mode bit 1: A28

6 P26MD 0: P26/DD30 (Note 1) R W

Port P26 operation mode bit 1: A29

7 P27MD 0: P27/DD31 (Note 1) R W

Port P27 operation mode bit 1: A30 Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input. Notes: • During single-chip mode, settings of this register have no effect, and the port functions as port input/output or DD input pin.

• During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (A23-A30).

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P3 Operation Mode Register (P3MOD) <Address: H’0080 0743> <Upon exiting reset: H’00> b Bit Name Function R W

8 P30MD 0: P30/DD16 (Note 1) R W

Port P30 operation mode bit 1: A15/TIN4 (Note 2)

9 P31MD 0: P31/DD17 (Note 1) R W

Port P31 operation mode bit 1: A16/TIN5 (Note 2)

10 P32MD 0: P32/DD18 (Note 1) R W

Port P32 operation mode bit 1: A17/TIN6 (Note 2)

11 P33MD 0: P33/DD19 (Note 1) R W

Port P33 operation mode bit 1:A18/TIN17 (Note 2)

12 P34MD 0: P34/DD20 (Note 1) R W

Port P34 operation mode bit 1:A19/TIN30 (Note 2)

13 P35MD 0: P35/DD21 (Note 1) R W

Port P35 operation mode bit 1:A20/TIN31 (Note 2)

14 P36MD 0: P36/DD22 (Note 1) R W

Port P36 operation mode bit 1: A21/TIN32 (Note 2)

15 P37MD 0: P37/DD23 (Note 1) R W

Port P37 operation mode bit 1: A22/TIN33 (Note 2) Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input. Note 2: Which function of the pin is used depends on how the P3 Peripheral Function Select Register is set. Note: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signal pins (A15-A22). b 8 9 1 01 11 21 31 4 b 1 5 P30MD P31MD P32MD P33MD P34MD P35MD P36MD P37MD 00000000 P3 Peripheral Function Select Register (P3SMOD) <Address: H’0080 0763> <Upon exiting reset: H’00> b Bit Name Function R W

8 P30SMD 0: A15 R W

Port P30 peripheral function select bit 1: TIN4

9 P31SMD 0: A16 R W

Port P31 peripheral function select bit 1: TIN5

10 P32SMD 0: A17 R W

Port P32 peripheral function select bit 1: TIN6

11 P33SMD 0: A18 R W

Port P33 peripheral function select bit 1: TIN7

12 P34SMD 0: A19 R W

Port P34 peripheral function select bit 1: TIN30

13 P35SMD 0: A20 R W

Port P35 peripheral function select bit 1: TIN31

14 P36SMD 0: A21 R W

Port P36 peripheral function select bit 1: TIN32

15 P37SMD 0: A22 R W

Port P37 peripheral function select bit 1: TIN33 Notes: • During processor mode, settings of this bit have no effect and the ports function as external bus interface signal pins (A15-A22).

• The value of this register can only be modified when the corresponding P3 operation mode register bit = 0 (set for port). Then set the corresponging P3 operation mode register bit to "1."
• During single-chip mode, selecting the external bus interface function is prohibited. b 8 9 1 01 11 21 31 4 b 1 5 P30SMD P31SMD P32SMD P33SMD P34SMD P35SMD P36SMD P37SMD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-18 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P4 Operation Mode Register (P4MOD) <Address: H’0080 0744> <Upon exiting reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0." 00

4 P44MD 0: P44 R W

Port P44 operation mode bit 1: CS0#/TIN8 (Note 1)

5 P45MD 0: P45 R W

Port P45 operation mode bit 1: CS1#/TIN9 (Note 1)

6 P46MD 0: P46 R W

Port P46 operation mode bit 1: A13/TIN10 (Note 1)

7 P47MD 0: P47 R W

Port P47 operation mode bit 1: A14/TIN11 (Note 1) Note 1: Which function of the pin is used depends on how the P4 Peripheral Function Select Register is set. Note: • During processor mode, settings of this register have no effect, and the ports function as external bus interface signa l pins (CS0#, CS1#, A13 and A14). P4 Peripheral Function Select Register (P4SMOD) <Address: H’0080 0764> <Upon exiting reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0." 00

4 P44SMD 0: CS0# R W

Port P44 peripheral function select bit 1: TIN8

5 P45SMD 0: CS1# R W

Port P45 peripheral function select bit 1: TIN9

6 P46SMD 0: A13 R W

Port P46 peripheral function select bit 1: TIN10

7 P47SMD 0: A14 R W

Port P47 peripheral function select bit 1: TIN11 Notes: • During processor mode, settings of this register have no effect, and the ports function as external bus interface sig nal pins (CS0#, CS1#, A13 and A14).

• The value of this register can only be modified when the corresponding P4 operation mode register bit = 0 (set for port). Then set the corresponging P4 operation mode register bit to "1."
• During single-chip mode, selecting the external bus interface function is prohibited. b 0 123456 b 7 P44SMD P45SMD P46SMD P47SMD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P7 Operation Mode Register (P7MOD) <Address: H’0080 0747> <Upon exiting reset: H’00> b Bit Name Function R W

8 P70MD 0: P70 R W

Port P70 operation mode bit 1: CLKOUT/WR#/BCLK (Note 1)

9 P71MD 0: P71 R W

Port P71 operation mode bit 1: WAIT# (Note 2)

10 P72MD 0: P72 R W

Port P72 operation mode bit 1: HREQ#/TIN27 (Note 3)

11 P73MD 0: P73 R W

Port P73 operation mode bit 1: HACK#/TIN26 (Note 3)

12 P74MD 0: P74 R W

Port P74 operation mode bit (Note 4) 1: RTDTXD/TXD3/NBDD0 (Note 3)

13 P75MD 0: P75 R W

Port P75 operation mode bit (Note 4) 1: RTDRXD/RXD3/NBDD1 (Note 3)

14 P76MD 0: P76 R W

Port P76 operation mode bit (Note 4) 1: RTDACK/CTX1/NBDD2 (Note 3)

15 P77MD 0: P77 R W

Port P77 operation mode bit (Note 4) 1: RTDCLK/CRX1/NBDD3 (Note 3) Note 1: These functions are selected using the P7 Peripheral Function Select Register and Bus Mode Control Register. Note 2: During single-chip mode, settings of this register have no effect, and the port functions as port input/output pin. Note 3: These functions are selected using the P7 Peripheral Function Select Register. Note 4: If the NBD function is selected by the NBD Pin Control Register, the port functions as NBD pin no matter how this register is set. b 8 9 1 01 11 21 31 4 b 1 5 P70MD P71MD P72MD P73MD P74MD P75MD P76MD P77MD 00000000 P7 Peripheral Function Select Register (P7SMOD) <Address: H’0080 0767> <Upon exiting reset: H’00> b Bit Name Function R W

8 P70SMD 0: CLKOUT/WR# (Note 1) R W

Port P70 peripheral function select bit 1: BCLK 9 No function assigned. Fix to "0." 00

10 P72SMD 0: HREQ# R W

Port P72 peripheral function select bit 1: TIN27

11 P73SMD 0: HACK# R W

Port P73 peripheral function select bit 1: TIN26

12 P74SMD (Note 2) 0: RTDTXD R W

Port P74 peripheral function select bit 1: TXD3

13 P75SMD (Note 2) 0: RTDRXD R W

Port P75 peripheral function select bit 1: RXD3

14 P76SMD (Note 2) 0: RTDACK R W

Port P76 peripheral function select bit 1: CTX1

15 P77SMD (Note 2) 0: RTDCLK R W

Port P77 peripheral function select bit 1: CRX1 Note 1: Which function of the pin is used depends on how the Bus Mode Control Register is set. Note 2: If the NBD function is selected by the NBD Pin Control Register, the port functions as NBD pin no matter how this register is set. Note: • The value of this register can only be modified when the corresponding P7 operation mode register bit = 0 (set for port). Then set the corresponging P7 operation mode register bit to "1." b 8 9 1 01 11 21 31 4 b 1 5 P70SMD P72SMD P73SMD P74SMD P75SMD P76SMD P77SMD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-20 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P8 Operation Mode Register (P8MOD) <Address: H’0080 0748> <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0." 00

2 P82MD 0: P82 R W

Port P82 operation mode bit 1: TXD0/TO26 (Note 1)

3 P83MD 0: P83 R W

Port P83 operation mode bit 1: RXD0/TO25 (Note 1)

4 P84MD 0: P84 R W

Port P84 operation mode bit 1: SCLKI0/SCLKO0/TO24 (Note 1)

5 P85MD 0: P85 R W

Port P85 operation mode bit 1: TXD1/TO23 (Note 1)

6 P86MD 0: P86 R W

Port P86 operation mode bit 1: RXD1/TO22 (Note 1)

7 P87MD 0: P87 R W

Port P87 operation mode bit 1: SCLKI1/SCLKO1/TO21 (Note 1) Note 1: Which function of the pin is used depends on how the P8 Peripheral Function Select Register is set. P8 Peripheral Function Select Register (P8SMOD) <Address: H’0080 0768> <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0." 00

2 P82SMD 0: TXD0 R W

Port P82 peripheral function select bit 1: TO26

3 P83SMD 0: RXD0 R W

Port P83 peripheral function select bit 1: TO25

4 P84SMD 0: SCLKI0/SCLKO0 R W

Port P84 peripheral function select bit 1: TO24

5 P85SMD 0:TXD1 R W

Port P85 peripheral function select bit 1: TO23

6 P86SMD 0: RXD1 R W

Port P86 peripheral function select bit 1: TO22

7 P87SMD 0: SCLKI1/SCLKO1 R W

Port P87 peripheral function select bit 1: TO21 Note: • The value of this register can only be modified when the corresponding P8 operation mode register bit = 0 (set for port). Then set the corresponging P8 operation mode register bit to "1." b 0 123456 b 7 P82SMD P83SMD P84SMD P85SMD P86SMD P87SMD 00000000 b 0 123456 b 7 P82MD P83MD P84MD P85MD P86MD P87MD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P9 Peripheral Function Select Register (P9SMOD) <Address: H’0080 0769> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0." 00

11 P93SMD 0: TO16 R W

Port P93 peripheral function select bit 1: SCLKI5/SCLKO5

12 P94SMD 0: TO17 R W

Port P94 peripheral function select bit 1: TXD5

13 P95SMD 0: TO18 R W

Port P95 peripheral function select bit 1: RXD5 14, 15 No function assigned. Fix to "0." 00 Note: • The value of this register can only be modified when the corresponding P9 operation mode register bit = 0 (set for port). Then set the corresponging P9 operation mode register bit to "1." P9 Operation Mode Register (P9MOD) <Address: H’0080 0749> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0." 00

11 P93MD 0: P93 R W

Port P93 operation mode bit 1: TO16/SCLKI5/SCLKO5 (Note 2)

12 P94MD 0: P94/DD15 (Note 1) R W

Port P94 operation mode bit 1: TO17/TXD5 (Note 2)

13 P95MD 0: P95/DD14 (Note 1) R W

Port P95 operation mode bit 1: TO18/RXD5 (Note 2)

14 P96MD 0: P96/DD13 (Note 1) R W

Port P96 operation mode bit 1: TO19

15 P97MD 0: P97/DD12 (Note 1) R W

Port P97 operation mode bit 1: TO20 Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input. Note 2: Which function of the pin is used depends on how the P9 Peripheral Function Select Register is set. b 8 9 1 01 11 21 31 4 b 1 5 P93MD P94MD P95MD P96MD P97MD 00000000 b 8 9 1 01 11 21 31 4 b 1 5 P93SMD P94SMD P95SMD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-22 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P10 Operation Mode Register (P10MOD) <Address: H’0080 074A> <Upon exiting reset: H’00> b Bit Name Function R W

0 P100MD 0: P100 R W

Port P100 operation mode bit 1: TO8

1 P101MD 0: P101 R W

Port P101 operation mode bit 1: TO9/CRX0 (Note 1)

2 P102MD 0: P102 R W

Port P102 operation mode bit 1: TO10/CTX0 (Note 1)

3 P103MD 0: P103 R W

Port P103 operation mode bit 1: TO11/TIN24 (Note 1)

4 P104MD 0: P104/DD3 (Note 2) R W

Port P104 operation mode bit 1: TO12/TIN25 (Note 1)

5 P105MD 0: P105/DD2 (Note 2) R W

Port P105 operation mode bit 1: TO13/SCLKI4/SCLKO4 (Note 1)

6 P106MD 0: P106/DD1 (Note 2) R W

Port P106 operation mode bit 1: TO14/TXD4 (Note 1)

7 P107MD 0: P107/DD0 (Note 2) R W

Port P107 operation mode bit 1: TO15/RXD4 (Note 1) Note 1: Which function of the pin is used depends on how the P10 Peripheral Function Select Register is set. Note 2: The DD input functions are effective depending on the settings of DD input pin select register (DDSEL). (For details, r efer to the Chapter 14, "Direct RAM Interface") To use the port as DD input pin, set the port direction for input. b 0 123456 b 7 P100MD P101MD P102MD P103MD P104MD P105MD P106MD P107MD 00000000 P10 Peripheral Function Select Register (P10SMOD) <Address: H’0080 076A> <Upon exiting reset: H’00> b Bit Name Function R W 0 No function assigned. Fix to "0." 00

1 P101SMD 0: TO9 R W

Port P101 peripheral function select bit (Note 1) 1: CRX0

2 P102SMD 0: TO10 R W

Port P102 peripheral function select bit 1: CTX0

3 P103SMD 0: TO11 R W

Port P103 peripheral function select bit 1: TIN24

4 P104SMD 0: TO12 R W

Port P104 peripheral function select bit 1: TIN25

5 P105SMD 0:TO13 R W

Port P105 peripheral function select bit 1: SCLKI4/SCLKO4

6 P106SMD 0: TO14 R W

Port P106 peripheral function select bit 1: TXD4

7 P107SMD 0: TO15 R W

Port P107 peripheral function select bit 1: RXD4 Note 1: When not using this pin as CRX0 pin, always be sure to set the bit to "0." Note: • The value of this register can only be modified when the corresponding P10 operation mode register bit = 0 (set for po rt). Then set the corresponging P10 operation mode register bit to "1." P101SMD P102SMD P103SMD P104SMD P105SMD P106SMD P107SMD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P11 Peripheral Function Select Register (P11SMOD) <Address: H’0080 076B> <Upon exiting reset: H’00> b Bit Name Function R W

8 P110SMD 0: TO0 R W

Port P110 peripheral function select bit 1: TO29

9 P111SMD 0: TO1 R W

Port P111 peripheral function select bit 1: TO30

10 P112SMD 0: TO2 R W

Port P112 peripheral function select bit 1: TO31

11 P113SMD 0: TO3 R W

Port P113 peripheral function select bit 1: TO32

12 P114SMD 0: TO4 R W

Port P114 peripheral function select bit 1: TO33

13 P115SMD 0: TO5 R W

Port P115 peripheral function select bit 1: TO34

14 P116SMD 0: TO6 R W

Port P116 peripheral function select bit 1: TO35

15 P117SMD 0: TO7 R W

Port P117 peripheral function select bit 1: TO36 Note: • The value of this register can only be modified when the corresponding P11 operation mode register bit = 0 (set for po rt). Then set the corresponging P11 operation mode register bit to "1." P11 Operation Mode Register (P11MOD) <Address: H’0080 074B> <Upon exiting reset: H’00> b Bit Name Function R W

8 P110MD 0: P110/DD11 (Note 1) R W

Port P110 operation mode bit 1: TO0/TO29 (Note 2)

9 P111MD 0: P111/DD10 (Note 1) R W

Port P111 operation mode bit 1: TO1/TO30 (Note 2)

10 P112MD 0: P112/DD9 (Note 1) R W

Port P112 operation mode bit 1: TO2/TO31 (Note 2)

11 P113MD 0: P113/DD8 (Note 1) R W

Port P113 operation mode bit 1: TO3/TO32 (Note 2)

12 P114MD 0: P114/DD7 (Note 1) R W

Port P114 operation mode bit 1: TO4/TO33 (Note 2)

13 P115MD 0: P115/DD6 (Note 1) R W

Port P115 operation mode bit 1: TO5/TO34 (Note 2)

14 P116MD 0: P116/DD5 (Note 1) R W

Port P116 operation mode bit 1: TO6/TO35 (Note 2)

15 P117MD 0: P117/DD4 (Note 1) R W

Port P117 operation mode bit 1: TO7/TO36 (Note 2) Note 1: The port and DD input functions both are effective. To use the port as DD input pin, set the port direction for input. Note 2: Which function of the pin is used depends on how the P11 Peripheral Function Select Register is set. b 8 9 1 01 11 21 31 4 b 1 5 P110MD P111MD P112MD P113MD P114MD P115MD P116MD P117MD 00000000 b 8 9 1 01 11 21 31 4 b 1 5 P110SMD P111SMD P112SMD P113SMD P114SMD P115SMD P116SMD P117SMD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-24 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P12 Operation Mode Register (P12MOD) <Address: H’0080 074C> <Upon exiting reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0." 00

4 P124MD 0: P124/DD3 (Note 1) R W

Port P124 operation mode bit (Note 3) 1: TCLK0/A9 (Note 2)

5 P125MD 0: P125/DD2 (Note 1) R W

Port P125 operation mode bit (Note 3) 1: TCLK1/A10 (Note 2)

6 P126MD 0: P126/DD1 (Note 1) R W

Port P126 operation mode bit 1: TCLK2/CS2# (Note 2)

7 P127MD 0: P127/DD0 (Note 1) R W

Port P127 operation mode bit 1: TCLK3/CS3# (Note 2) Note 1: The DD input functions are effective depending on the settings of DD input pin select register (DDSEL). (For details, r efer to the Chapter 14, "Direct RAM Interface") To use the port as DD input pin, set the port direction for input. Note 2: Which function of the pin is used depends on how the P12 Peripheral Function Select Register is set. Note 3: During processor mode, settings of this bit have no effect and the port functions as external bus interface signal pin (A9 or A10). P124MD P125MD P126MD P127MD 00000000 P12 Peripheral Function Select Register (P12SMOD) <Address: H’0080 076C> <Upon exiting reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0." 00

4 P124SMD 0: TCLK0 R W

Port P124 peripheral function select bit (Note 1) 1: A9

5 P125SMD 0: TCLK1 R W

Port P125 peripheral function select bit (Note 1) 1: A10

6 P126SMD 0: TCLK2 R W

Port P126 peripheral function select bit 1: CS2#

7 P127SMD 0: TCLK3 R W

Port P127 peripheral function select bit 1: CS3# Note 1: During processor mode, settings of this bit have no effect and the port functions as external bus interface signal pin (A9 or A10). Note: • The value of this register can only be modified when the corresponding P12 operation mode register bit = 0 (set for port). Then set the corresponging P12 operation mode register bit to "1." b 0 123456 b 7 P124SMD P125SMD P126SMD P127SMD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P13 Peripheral Function Select Register (P13SMOD) <Address: H’0080 076D> <Upon exiting reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0." 00

12 P134SMD 0: TIN20/DIN4 (Note 1) R W

Port P134 peripheral function select bit 1: TXD3

13 P135SMD 0: TIN21 R W

Port P135 peripheral function select bit (Note 2) 1: RXD3

14 P136SMD 0: TIN22 R W

Port P136 peripheral function select bit (Note 3) 1: CRX1

15 P137SMD 0: TIN23 R W

Port P137 peripheral function select bit 1: CTX1 Note 1: TIN input and DIN input functions both are effective. Note 2: When not using this pin as RXD3 pin, always be sure to set the bit to "0." Note 3: When not using this pin as CRX1 pin, always be sure to set the bit to "0." Note: • The value of this register can only be modified when the corresponding P13 operation mode register bit = 0 (set for port). Then set the corresponging P13 operation mode register bit to "1." P13 Operation Mode Register (P13MOD) <Address: H’0080 074D> <Upon exiting reset: H’00> b Bit Name Function R W

8 P130MD 0: P130 R W

Port P130 operation mode bit 1: TIN16/PWMOFF0/DIN0 (Note 1)

9 P131MD 0: P131 R W

Port P131 operation mode bit 1: TIN17/PWMOFF1/DIN1 (Note 1)

10 P132MD 0: P132 R W

Port P132 operation mode bit 1: TIN18/DIN2 (Note 2)

11 P133MD 0: P133 R W

Port P133 operation mode bit 1: TIN19/DIN3 (Note 2)

12 P134MD 0: P134 R W

Port P134 operation mode bit 1: TIN20/TXD3/DIN4 (Note 3)

13 P135MD 0: P135 R W

Port P135 operation mode bit 1: TIN21/RXD3 (Note 3)

14 P136MD 0: P136 R W

Port P136 operation mode bit 1: TIN22/CRX1 (Note 3)

15 P137MD 0: P137 R W

Port P137 operation mode bit 1: TIN23/CTX1 (Note 3) Note 1: TIN input, DIN input, and PWMOFF input functions all are effective. Note 2: TIN input and DIN input functions both are effective. Note 3: Which function of the pin is used depends on how the P13 Peripheral Function Select Register is set. b 8 9 1 01 11 21 31 4 b 1 5 P130MD P131MD P132MD P133MD P134MD P135MD P136MD P137MD 00000000 b 8 9 1 01 11 21 31 4 b 1 5 P134SMD P135SMD P136SMD P137SMD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-26 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P15 Peripheral Function Select Register (P15SMOD) <Address: H’0080 076F> <Upon exiting reset: H’00> b Bit Name Function R W

8 P150SMD 0: TIN0 R W

Port P150 peripheral function select bit 1: CLKOUT/WR# (Note 1) 9, 10 No function assigned. Fix to "0." 00

11 P153SMD 0: TIN3 R W

Port P153 peripheral function select bit (Note 2) 1: WAIT# 12–15 No function assigned. Fix to "0." 00 Note 1: Which function of the pin is used depends on how the Bus Mode Control Register is set. Note 2: During single-chip mode, selecting the external bus interface signal function is prohibited. Note: • The value of this register can only be modified when the corresponding P15 operation mode register bit = 0 (set for port). Then set the corresponging P15 operation mode register bit to "1." P15 Operation Mode Register (P15MOD) <Address: H’0080 074F> <Upon exiting reset: H’00> b Bit Name Function R W

8 P150MD 0: P150 R W

Port P150 operation mode bit 1: TIN0/CLKOUT/WR# (Note 1) 9, 10 No function assigned. Fix to "0." 00

11 P153MD 0: P153 R W

Port P153 operation mode bit 1: TIN3/WAIT# (Note 2) 12–15 No function assigned. Fix to "0." 00 Note 1: Which function of the pin is used depends on how the P15 Peripheral Function Select Register and Bus Mode Control Register are set. Note 2: Which function of the pin is used depends on how the P15 Peripheral Function Select Register is set. b 8 9 1 01 11 21 31 4 b 1 5 P150MD P153MD 00000000 b 8 9 1 01 11 21 31 4 b 1 5 P150SMD P153SMD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P17 Operation Mode Register (P17MOD) <Address: H’0080 0751> <Upon exiting reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0." 00

12 P174MD 0: P174 R W

Port P174 operation mode bit 1: TXD2/TO28 (Note 1)

13 P175MD 0: P175 R W

Port P175 operation mode bit 1: RXD2/TO27 (Note 1) 14, 15 No function assigned. Fix to "0." 00 Note 1: Which function of the pin is used depends on how the P17 Peripheral Function Select Register is set. b 8 9 1 01 11 21 31 4 b 1 5 P174MD P175MD 00000000 P17 Peripheral Function Select Register (P17SMOD) <Address: H’0080 0771> <Upon exiting reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0." 00

12 P174SMD 0: TXD2 R W

Port P174 peripheral function select bit 1: TO28

13 P175SMD 0: RXD2 R W

Port P175 peripheral function select bit 1: TO27 14, 15 No function assigned. Fix to "0." 00 Note: • The value of this register can only be modified when the corresponding P17 operation mode register bit = 0 (set for port). Then set the corresponging P17 operation mode register bit to "1." b 8 9 1 01 11 21 31 4 b 1 5 P174SMD P175SMD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-28 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P22 Peripheral Function Select Register (P22SMOD) <Address: H’0080 0776> <Upon exiting reset: H’00> b Bit Name Function R W

0 P220SMD 0: CTX0 R W

Port P220 peripheral function select bit 1: HACK#

1 P221SMD 0: CRX0 R W

Port P221 peripheral function select bit 1: HREQ# 2, 3 No function assigned. Fix to "0." 00

4 P224SMD 0: A11 R W

Port P224 peripheral function select bit (Note 1) 1: CS2#

5 P225SMD 0: A12 R W

Port P225 peripheral function select bit (Note 1) 1: CS3# 6, 7 No function assigned. Fix to "0." 00 Note 1: During single-chip mode, selecting the external bus interface signal function is prohibited. Note: • The value of this register can only be modified when the corresponding P22 operation mode register bit = 0 (set for port). Then set the corresponging P22 operation mode register bit to "1." P22 Operation Mode Register (P22MOD) <Address: H’0080 0756> <Upon exiting reset: H’00> b Bit Name Function R W

0 P220MD 0: P220 R W

Port P220 operation mode bit 1: CTX0/HACK# (Note 1)

1 P221MD 0: P221 R W

Port P221 operation mode bit 1: CRX0/HREQ# (Note 1) 2, 3 No function assigned. Fix to "0." 00

4 P224MD 0: P224 R W

Port P224 operation mode bit (Note 2) 1: A11/CS2# (Note 1)

5 P225MD 0: P225 R W

Port P225 operation mode bit (Note 2) 1: A12/CS3# (Note 1) 6, 7 No function assigned. Fix to "0." 00 Note 1: Which function of the pin is used depends on how the P22 Peripheral Function Select Register is set. Note 2: During processor mode, settings of this bit have no effect and the port functions as external bus interface signal pin (A11/CS2# or A12/CS3#). P220SMD P221SMD P224SMD P225SMD 00000000 b 0 123456 b 7 P220MD P221MD P224MD P225MD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

8.3.4 Port Input Special Function Control Register

Port Input Special Function Control Register (PICNT) <Address: H’0080 0745> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0." 00

11 XSTAT 0: XIN oscillating R(Note 1)

XIN oscillation status bit 1: XIN inactive 12, 13 No function assigned. Fix to "0." 00

14 PISEL 0: Content of port output latch R W

Port input data select bit 1: Port pin level

15 PIEN0 0: Disable input R W

Port input enable bit 1: Enable input Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Note 2: After switching from output mode to input mode in the Port Direction Register, or after setting port input enable (PIEN 0) bit to "1" (input enable), pin level can be read after 2BCLK period. (1) XSTAT (XIN oscillation status) bit (Bit 11)

• Conditions under which XSTAT bit is set to "1" XSTAT bit is set to "1" upon detecting that XIN oscillation has stopped. When XIN remains at the same level for a predetermined time (3 BCLK periods up to 4 BCLK periods) on the basis of threshold, XIN oscillation is assumed to have stopped. When operating normally, XIN changes state (high or low) once every BCLK period.
• Conditions under which XSTAT bit is cleared to "0" XSTAT bit is cleared to "0" by a system reset or by writing "0." If XSTAT bit is cleared at the same time it is set above, the former has priority. Writing "1" to XSTAT bit is ignored.
• Method for using XSTAT bit to detect XIN oscillation stoppage Because the M32R/ECU internally contains a PLL, the internal clock remains active even when XIN oscilla- tion has stopped. By reading XSTAT bit without clearing it once after exiting the reset state, it is possible to know whether XIN has ever stopped since the reset signal was deasserted. Similarly, by reading XSTAT bit after clearing it by writing "0," it is possible to know the current oscillating status of XIN. However, there must be an interval of at least 5 BCLK periods (20 CPU clock periods) between read and write. Pay attention about processing when XSTAT bit is set to "1," make double check after clearing XSTAT bit etc.

b 8 9 1 01 11 21 31 4 b 1 5 XSTAT PISEL PIEN0 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-30 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (1) To know whether XIN oscillation has ever stopped after being reset Write XSTAT bit = 0 (2) To know the current status of XIN oscillation Wait for 20 CPU clock periods or more Read XSTAT bit Wait before inspecting XSTAT bit Note:  Pay attention about processing when XSTAT bit is set to "1," make double check after clearing XSTAT bit etc. Figure 8.3.1 Procedure for Setting XSTAT (2) PISEL (Port input data select) bit (Bit 14) When the Port Direction Register is set for output, this bit selects the target data to be read from the Port Data Register. At this time, this bit is unaffected by the Port Operation Mode Register. Table 8.3.1 PISEL Bit Settings and the Target Data To Be Read from the Port Data Register Direction Register PISEL Settings Target Data to Be Read 0 (input) 0/1 Port pin level 1 (output) 0 Port output latch

1 Port pin level

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-3132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (3) PIEN0 (Port input enable) bit (Bit 15) This bit is used to prevent shoot-through current from flowing into the port input pins. Because the input/output ports are disabled against input upon exiting reset, if any ports need to be used in input mode they must be enabled for input by setting this bit to "1." When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a low-level input applied. Consequently, if a peripheral input function (uncontrolled pin) is selected for any port while disabled against input by using the Port Operation Mode Register, the port may operate unex- pectedly due to the "L" level input on it. The following shows the procedure for selecting a peripheral input function. (1) Enable the port for input when its pin level is valid (high or low) (2) Select a function using the port operation mode bit During boot mode, the pins shared with serial interface functions are enabled for input and can therefore be protected against shoot-through current flowing in from the pins other than serial interface functions during flash programming by clearing PIEN0. The table below lists the pins that can be controlled by the PIEN0 bit in each operation mode. Table 8.3.2 Pins Controllable by Port Input Enable Bit Mode Name Controllable Pins Uncontrolled Pins P00–P07, P10–P17, P20–P27 P221, FP, SBI#, MOD0, MOD1, MOD2, RESET# P30–P37, P41–P47, P61–P63 Single-chip P70–P77, P82–P87, P93–P97 P100–P107, P110–P117, P124–P127 P130–P137, P150, P153, P174, P175 P220, P224, P225 P61–P63, P70–P77, P82–P87 P00–P07, P10–P17 External extension P93–P97, P100–P107, P110–P117 P20–P27, P30–P37 Microprocessor P126, P127, P130–P137 P41–P47, P124, P125, P221, P224, P225 P150, P153, P174, P175, P220 FP, SBI#, MOD0, MOD1, MOD2, RESET# P00–P07, P10–P17, P20–P27 P82–P87, P174, P175, P221 Boot P30–P37, P41–P47, P61–P63 FP, SBI#, MOD0, MOD1, MOD2, RESET# (single-chip) P70–P77, P93–P97, P100–P107 P110–P117, P124–P127, P130–P137 P150, P153, P220, P224, P225

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-32 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The port input level switching function allows the port threshold to be switched to one of three voltage levels (with or without Schmitt as selected) in units of the following port group. This can be set to the following registers in units of group. Note that port inputs are used for the DD input of DRI. Port Group 0: P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P70–P73, P224, P225 Port Group 1: P82–P87, P174, P175 Port Group 3: P93–P97, P110–P117 Port Group 4: P124–P127 Port Group 5: P61–P63, SBI# Port Group 6: P74–P77, P100–P107 Port Group 7: P220, P221 Port Group 8: P130–P137, P150, P153 0.7VCCE 0.5VCCE 0.35VCCE CMOS S S S S S WFnSEL PTnSEL VTnSEL Standard input level for each peripheral function pin Schmitt Peripheral function input Port input Pin Threshold Port Input enable Noise Canceller S PIEN0 Figure 8.4.1 Port Input Level Switching Function

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-3332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Port Group 0,1 Input Level Setting Register (PG01LEV) <Address: H’0080 0500> Port Group 3 Input Level Setting Register (PG3LEV) <Address: H’0080 0501> Note: • The PG3LEV register bits 8–11 have no functions assigned. Port Group 4,5 Input Level Setting Register (PG45LEV) <Address: H’0080 0502> Port Group 6,7 Input Level Setting Register (PG67LEV) <Address: H’0080 0503> Port Group 8 Input Level Setting Register (PG8LEV) <Address: H’0080 0504> Note: • The PG8LEV register bits 4–7 have no functions assigned. b 8 9 1 01 11 21 31 4 b 1 5 WF3SEL PT3SEL VT3SEL0 VT3SEL1 00000001 b 0 123456 b 7 WF0SEL PT0SEL VT0SEL0 VT0SEL1 WF1SEL PT1SEL VT1SEL0 VT1SEL1 00010001 b 0 123456 b 7 WF4SEL PT4SEL VT4SEL0 VT4SEL1 WF5SEL PT5SEL VT5SEL0 VT5SEL1 00010001 b 8 9 1 01 11 21 31 4 b 1 5 WF6SEL PT6SEL VT6SEL0 VT6SEL1 WF7SEL PT7SEL VT7SEL0 VT7SEL1 00010001 b 0 123456 b 7 WF8SEL PT8SEL VT8SEL0 VT8SEL1 00010000 <Upon exiting reset: :H'11, H'01, H'10> (Note 2) b Bit Name Function R W 0(4) WFnSEL (Note 1) 0: Select standard input for each pin R W 8(12) Group n dual-function input select bit 1: Select threshold switching function 1-3 PTnSEL 000 : FInput CMOS, Select 0.35VCCE R W (9 ~ 11) (Group n port input select bit ) 001 : Input CMOS, Select 0.50VCCE VTnSEL0, VTnSEL1 010 : Input CMOS, Select 0.70VCCE (Group n input threshold select bit) 011 : Settings inhibited 100 : Schmitt input , VT += 0.50VCCE, VT -= 0.35VCCE 101 : Settings inhibited 110 : Schmitt input , VT += 0.70VCCE, VT -= 0.35VCCE 111 : Schmitt input , VT += 0.70VCCE, VT -= 0.50VCCE 4(12) WFnSEL (Note 1) 0 : Select standard input for each pin R W Group n dual-function input select bit 1 : Select threshold switching function 5 ~ 7 PTnSEL 000 : Input CMOS, Select 0.35VCCE R W (13 ~ 15) (Group n port input select bit) 001 : Input CMOS, Select 0.50VCCE VTnSEL0, VTnSEL1 010 : Input CMOS, Select 0.70VCCE (Group n input threshold select bit) 011 : Settings inhibited 100 : Schmitt input , VT += 0.50VCCE, AVT -= 0.35VCCE 101 : Settings inhibited 110 : Schmitt input , VT += 0.70VCCE, AVT -= 0.35VCCE 111 : Schmitt input , VT += 0.70VCCE, AVT -= 0.50VCCE Note 1.When the multipurpose port function pin is selected (Set bit corresponding Px operation mode register(PxMOD) to "0"), setting value for WFnSEL is invalid and threshold switch function is effective. Note 2. Upon exiting reset, VTnSEL1 bit value is "1" and the other bit is set to "0."

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-34 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 This function sets the drive capability of output pins by selecting high or low drive power, one port group at a time. Port Group 0: P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P70–P73, P224, P225 Port Group 1: P82–P87, P174, P175 Port Group 3: P93–P97, P110–P117 Port Group 4: P124–P127 Port Group 5: P61–P63, SBI# Port Group 6: P74–P77, P100–P107 Port Group 7: P220, P221 Port Group 8: P130–P137, P150, P153

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-3532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Port Group 0,1 Output Drive Capability Setting Register (PG01DRV) <Address: H'0080 0508> Port Group 3 Output Drive Capability Setting Register (PG3DRV) <Address: H'0080 0509> Port Group 4,5 Output Drive Capability Setting Register (PG45DRV) <Address: H'0080 050A> Port Group 6,7 Output Drive Capability Setting Register (PG67DRV) <Address: H'0080 050B> Note: • The PG8DRV register bits 4–7 have no functions assigned. Port Group 8 Output Drive Capability Setting Register (PG8DRV) <Address: H'0080 050C> Note: • The PG3DRV register bits 8–14 have no functions assigned. <Upon exiting reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0." 00 (8–10) 3 (11) GnDSEL (Note 1) 0: 50% R W Group n output drive capability select bit 1: 100% 4–6 No function assigned. Fix to "0." 00 (12–14) 3 (15) GnDSEL (Note 1) 0: 50% R W Group n output drive capability select bit 1: 100% Note 1:The 50% drive capability is equivalent to that of the M32R/ECU Series without the port output drive capability setting function. Note : • For the P70/CLKOUT/WR#/BCLK pin, the drive capability can be set to one of four capability levels by using the P70 Output Drive Capability Setting Register. Note that 50% of GnDSEL bit and 50% of P70DSEL bit drive capabilities are equivalent. b 8 9 1 01 11 21 31 4 b 1 5 G3DSEL 00000000 b 0 123456 b 7 G4DSEL G5DSEL 00000000 b 8 9 1 01 11 21 31 4 b 1 5 G6DSEL G7DSEL 00000000 b 0 123456 b 7 G8DSEL 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-36 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 <Upon exiting reset: H’00> b Bit Name Function R W 8–12 No function assigned. Fix to "0." 00

13 P70DSELEN (Note 1) 0: Disable setting R W

P70 output drive capability setting enable bit 1: Enable setting 14, 15 P70DSEL (Note 2)(Note 3) 00: 25% low R W P70 output drive capability setting bit 01: 50% 10: 75% 11: 100% high Note 1: Setting this bit to "0" nullifies settings made to this register, so that the drive capability set by the Group 0,1 Out put Drive Capability Setting Register is assumed. When this bit is set to "1," settings of the Group 0,1 Output Drive Capability Setting Register have no effect and the drive capability is controlled by the P70DSEL bit. Note 2: This bit selects the drive capability of the P70/CLKOUT/WR#/BCLK pin. For settings of this bit to take effect, the P70DSELEN bit must be set to "1." Note 3: The 50% drive capability is equivalent to that of the M32R/ECU Series without the port output drive capability setting function. Note : • For the pins other than the P70/CLKOUT/WR#/BCLK pin, the drive capability can be set by using the Port Group Output Drive Capability Setting Registers. Note that 50% of GnDSEL and 50% of P70DSEL drive capabilities are equivalent. P70 Output Drive Capability Setting Register (P70DRV) <Address: H'0080 050D> b 8 9 1 01 11 21 31 4 b 1 5 P70DSELEN P70DSEL 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-3732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The Noise Canceller Control Register allows to select whether the noise canceller for the input signal to each peripheral module to be used or not, one port group at a time. Note that port inputs are used for the DD input of DRI. Port Group 0: TIN26, TIN27, TIN4–TIN11, TIN30–TIN33 Port Group 1: RXD0, SCLKI0, RXD1, SCLKI1, RXD2 Port Group 2: None Port Group 3: SCLKI5, RXD5 Port Group 4: TCLK0–TCLK3 Port Group 5: None Port Group 6: RTDRXD, RTDCLK, RXD3, TIN24, TIN25, SCLKI4, RXD4 Port Group 7: None Port Group 8: TIN16–TIN23, PWMOFF0, PWMOFF1, TIN0, TIN3 Figure 8.6.1 Noise Canceller Control Function VT+ VT- 0.7VCCE 0.5VCCE 0.35VCCE CMOS S S S S S WFnSEL PTnSEL VTnSEL Standard input level for each peripheral function pin Schmitt Peripheral function input Port input Pin Threshold Noise Canceller S Port Input enable PIEN0

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-38 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Noise Canceller Control Register (NZCNSLCR) <Address: H'0080 0510> <Upon exiting reset: H’0000> b Bit Name Function R W

0 G0NSEL 0: Group 0 noise canceller used R W

Group 0 noise canceller disable bit 1: Group 0 noise canceller not used

1 G1NSEL 0: Group 1 noise canceller used R W

Group 1 noise canceller disable bit 1: Group 1 noise canceller not used 2 No function assigned. Fix to "0." 00

3 G3NSEL 0: Group 3 noise canceller used R W

Group 3 noise canceller disable bit 1: Group 3 noise canceller not used

4 G4NSEL 0: Group 4 noise canceller used R W

Group 4 noise canceller disable bit 1: Group 4 noise canceller not used 5 No function assigned. Fix to "0." 00

6 G6NSEL 0: Group 6 noise canceller used R W

Group 6 noise canceller disable bit 1: Group 6 noise canceller not used 7 No function assigned. Fix to "0." 00

8 G8NSEL 0: Group 8 noise canceller used R W

Group 8 noise canceller disable bit 1: Group 8 noise canceller not used 9–15 No function assigned. Fix to "0." 00 Note: • This register must always be accessed in halfwords. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 G0NSEL G1NSEL G3NSEL G4NSEL G6NSEL G8NSEL 0000000000000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-3932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figures 8.7.1 through 8.7.5 show the peripheral circuit diagrams of the input/output ports described in the pre- ceding pages. Figure 8.7.1 Port Peripheral Circuit Diagram (1) Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Note 2: The standard input level of TIN4-TIN11,TIN30-TIN33 is peripheral TTL. Note 3: "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Notes:  During external extension and processor modes, P20-P27, P41-P43, P224 and P225 are external bus interface control signal pins, but their functional description in this block diagram is omitted.  The circle denotes a pin.  The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE or VCC-BUS voltage.  The input capacitance of each pin is approximately 10 pF.  The logic of peripheral function select register for P83, P86, P124, P125, P126, P127, P134, P137, P150, P175 are reversal, but it is not mentioned in this clock diagram.  DRI relative pin is not mentioned in this clock diagram. P20−P27(A23/DD24−A30/DD31) P41(BLW#/BLE#) P42(BHW#/BHE#) P43(RD#) P61−P63 P225(A12/CS3#) P224(A11/CS2#) P30(A15/TIN4/DD16) P31(A16/TIN5/DD17) P32(A17/TIN6/DD18) P33(A18/TIN7/DD19) P34(A19/TIN30/DD20) P35(A20/TIN31/DD21) P36(A21/TIN32/DD22) P37(A22/TIN33/DD23) P44(CS0#/TIN8) P45(CS1#/TIN9) P46(A13/TIN10) P47(A14/TIN11) P73(HACK#/TIN26) P83(RXD0/TO25) P86(RXD1/TO22) P95(TO18/RXD5/DD14) P101(TO9/CRX0) P103(TO11/TIN24) P104(TO12/TIN25/DD3) P107(TO15/RXD4/DD0) P124(TCLK0/A9/DD3) P125(TCLK1/A10/DD2) P126(TCLK2/CS2#/DD1) P127(TCLK3/CS3#/DD0) P134(TIN20/TXD3/DIN4) P137(TIN23/CTX1) P150(TIN0/CLKOUT/WR#) P175(RXD2/TO27) Port input data selection Data bus Port output latch Input function enable Direction register Data bus Direction register Port output latch Peripheral function output Operation mode register Peripheral function select register Peripheral function input (Note 3) Port input level switching function (Standard: no peripheral input) (Note 1) (Note 1) (Note 2) Port input data selection Port input level switching function (Standard: peripheral schmitt) Input function enable

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-40 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 8.7.2 Port Peripheral Circuit Diagram (2) Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Note 2: The standard input level of WAIT# is peripheral TTL. Note 3: "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Notes:  The circle denotes a pin.  The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE or VCC-BUS voltage.  The input capacitance of each pin is approximately 10 pF. SBI# SBI# P71(WAIT#) P130(TIN16/PWMOFF0/DIN0) P131(TIN17/PWMOFF1/DIN1) P132(TIN18/DIN2) P133(TIN19/DIN3) Port input data selection Data bus Data bus Peripheral function input (Note 3) Direction register Port output latch Operation mode register Input function enable Port input level switching function (Standard: peripheral schmitt) (Note 1) Port input level switching function (Standard: peripheral schmitt) (Note 1) (Note 2)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-4132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 P84(SCLKI0/SCLKO0/TO24) P87(SCLKI1/SCLKO1/TO21) P93(TO16/SCLKI5/SCLKO5) P105(TO13/SCLKI4/SCLKO4/DD2) Port input data selection Port input data selection Data bus Peripheral function output Direction register Port output latch Operation mode register Input function enable Data bus SCLKIi input (Note 2) SCLKOi output Direction register Port output latch Operation mode register Port input level switching function (Standard: peripheral schmitt) Input function enable (Note 1) UART/CSIO function select bit Internal/external clock select bit Peripheral function select register Peripheral function output Port input level switching function (Standard: no peripheral input) (Note 1) Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Note 2: "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Notes:  The circle denotes a pin.  The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE or VCC-BUS voltage.  The input capacitance of each pin is approximately 10 pF.  The logic of peripheral function select register for P93, P105 are reversal, but it is not mentioned in this clock diagram.  DRI relative pin is not mentioned in this clock diagram. P00-P07(DB0/TO21/DD0 -DB7/TO28/DD7) P10-P17(DB8/TO29/DD8 -DB15/TO36/DD15) P96(TO19/DD13) P97(TO20/DD12) P100(TO8) Figure 8.7.3 Port Peripheral Circuit Diagram (3)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-42 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 8.7.4 Port Peripheral Circuit Diagram (4) P70(CLKOUT/WR#/BCLK) P74(RTDTXD/TXD3/NBDD0) P76(RTDACK/CTX1/NBDD2) P82(TXD0/TO26) P85(TXD1/TO23) P94(TO17/TXD5/DD15) P102(TO10/CTX0) P106(TO14/TXD4/DD1) P110 - P117(TO0/TO29/DD11 -TO8/TO36/DD4) P174(TXD2/TO28) P220(CTX0/HACK#) P221(CRX0/HREQ#) P72(HREQ#/TIN27) P75(RTDRXD/RXD3/NBDD1) P77(RTDCLK/CRX1/NBDD3) P135(TIN21/RXD3) P136(TIN22/CRX1) P153(TIN3/WAIT#) Port input data selection Data bus Peripheral function input 2 (Note 4) Peripheral function input 1 (Note 4) Peripheral function input 2 (Note 4) Peripheral function input 1 (Note 4) Peripheral function input 2 Peripheral function input 1 Port input data selection Direction register Port output latch Data bus Data bus Operation mode register Peripheral function select register Input function enable (Note 1) (Note 2) Port input level switching function (Standard: peripheral schmitt) Operation mode register Peripheral function select register Input function enable (Note 1) (Note 3) Port input level switching function (Standard: peripheral schmitt) Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Note 2: The standard input level of WAIT# is peripheral TTL. Note 3: There is no standard input level in P70, P82, P85, P94, P102, P106, P110-P117, P174, and P220. Note 4: "H" level is entered to the peripheral function input when it is set to the general-purpose port inthe operation mode register. Notes:  The circle denotes a pin.  The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE or VCC-BUS voltage.  The input capacitance of each pin is approximately 10 pF. Operation mode register Peripheral function select register Input function enable (Note 1) Port input level switching function (Standard: peripheral schmitt) Port input data selection Direction register Port output latch

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-4332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 8.7.5 Port Peripheral Circuit Diagram (5) Notes:  The circle denotes a pin.  The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE or VCC-BUS voltage.  The input capacitance of each pin is approximately 10 pF. JTCK/NBDCLK MOD0 MOD1 MOD2 RESET# XIN JTRST JTMS JTDI/NBDSYNC# FP AD0IN0-AD0IN15 VREF0 XOUT VCC-BUS VCCE VDDE AVCC0 VCCER EXCVCC EXCVDD JTDO/NBDEVNT# JTCK/NBDCLK MOD0, MOD1, MOD2, FP,RESET#,XIN, JTRST, JTMS JTDI/NBDSYNC# AD0IN0-AD0IN15, VREF0, XOUT VCC-BUS, VCCE, VDDE, AVCC0 VCCER, EXCVCC, EXCVDD JTDO/NBDEVNT#

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-44 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

• When using input/output ports in output mode Because the value of the Port Data Register is undefined when exiting the reset state, the Port Data Register must have its initial value set in it before the Port Direction Register can be set for output. Conversely, if the Port Direction Register is set for output before setting data in the Port Data Register, the Port Data Register outputs an undefined value until any data is written into it.
• When using input/output ports in intput mode After switching from output mode to input mode in the Port Direction Register, or after setting port input enable (PIEN0) bit to "1" (input enable), pin level can be read after 2BCLK period.
• About the port input disable function Because the input/output ports are disabled against input upon exiting reset, they must be enabled for input by setting the Port Input Enable (PIEN0) bit to "1" before their input functions can be used. When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a "L" level input applied. Consequently, if a peripheral input function (uncontrolled pin) is selected for any port while disabled against input by using the Port Operation Mode Register, the port may operate unexpectedly due to the "L" level input on it.
• About the port peripheral function select register setting The Port Peripheral Function Select Register can only be set when the corresponding bit of the Port Operation Mode Register is "0."
• About the pereipheral function input when it is set to the gereral-purpose port In the pin for both peripheral function input and general-purpose port, "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Therefore, when "L" level is entered to the peripheral function input pin, edge signal is entered to the peripheral function input at manipulating operation mode register.

9.1 Outline of the DMAC

9.2 DMAC Related Registers

9.3 Functional Description of the DMAC

9.4 Notes on the DMAC

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The microcomputer internally contains a 10-channel DMAC (Direction Memory Access Controller). It allows data to be transferred at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, or between internal RAMs, as initiated by a software trigger or requested from an internal peripheral I/O. Table 9.1.1 Outline of the DMAC Item Description Number of channels 10 channels Transfer request sources • Software trigger

• Request from internal peripheral I/Os: A/D converter, multijunction timer, serial interface (reception completed, transmit buffer empty), CAN or DRI
• DMA channels can be cascaded (Note 1) Maximum number of 65,536 times times transferred Transferable address • 32192 : 64 Kbytes x 3 banks (address space from H’0080 0000 to H’0082 FFFF) 32195 : 48 Kbytes (address space from H’0080 0000 to H’0080 BFFF) 32196 : 64 Kbytes + 16 byte (address space from H’0080 0000 to H’0081 3FFF) space (Note 2) • Transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs are supported. Transfer data size 16 or 8 bits Transfer method Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual- address transfer Transfer mode Single transfer mode Direction of transfer One of three modes can be selected for the source and destination:
• Address fixed
• Address incremental
• Ring buffered (can be selected from 32, 16, 8, 4 or 2 times) Channel priority DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9 (Priority is fixed) Maximum transfer rate 26.6 Mbytes per second (when internal peripheral clock BCLK = 40 MHz) Interrupt request Group interrupt request can be generated when each transfer count register underflows. Transfer area (Note 2) 32192 : 64 Kbytes x 3 banks of H’0080 0000 to H’0082 FFFF 32195 : 48 Kbytes of H’0080 0000 to H’0080 BFFF) 32196 : 64 Kbytes + 16 byte of H’0080 0000 to H’0081 3FFF (Transferable in the entire RAM/SFR area) Note 1: The DMA channels can be cascaded in the manner described below.
• Start DMA transfer on DMA1 upon completion of one DMA transfer on DMA0
• Start DMA transfer on DMA5 upon completion of all DMA transfers on DMA0 (upon underflow of the transfer count register)
• Start DMA transfer on DMA2 upon completion of one DMA transfer on DMA1
• Start DMA transfer on DMA0 upon completion of one DMA transfer on DMA2
• Start DMA transfer on DMA3 upon completion of one DMA transfer on DMA2
• Start DMA transfer on DMA4 upon completion of one DMA transfer on DMA3
• Start DMA transfer on DMA6 upon completion of one DMA transfer on DMA5
• Start DMA transfer on DMA7 upon completion of one DMA transfer on DMA6
• Start DMA transfer on DMA5 upon completion of one DMA transfer on DMA7
• Start DMA transfer on DMA8 upon completion of one DMA transfer on DMA7
• Start DMA transfer on DMA9 upon completion of one DMA transfer on DMA8 Note 2: The source address and destination address cannot go over the bank, which can be only transferred to the same bank or another one from a certain bank.

9-332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 9.1.1 Block Diagram of the DMAC S S S S S S S S S S S DMA0 udf end DMA1 udf end DMA2 udf end DMA3 udf end DMA4 udf end DMA5 udf end DMA6 udf end DMA7 udf end DMA8 udf end DMA9 udf end S S S S S S S S S (Note 1) TIN3S TID1_udf/ovf TOU1_1irq (Note 2) DRI(DIN1) SIO4_RXD TID0_udf/ovf (Note 2) CAN0_S0/S31 TOU1_0irq (Note 2) DRI(DIN0) (Note 2) SIO4_TXD (Note 2) A/D0 conversion completed (Note 1) TIN0S TIO8_udf TIN30S TIO9_udf (Note 2) A/D0 conversion completed TIO8_udf Software start Software start Software start (Note 1) TIN18S Software start (Note 2) SIO0_TXD (Note 2) SIO1_RXD Software start (Note 2) SIO0_RXD Software start DMA0-4 interrupts DMA5-9 interrupts (Note 2) SIO2_RXD Software start (Note 2) SIO1_TXD (Note 2) CAN0_S0/S31 Software start (Note 2) SIO2_TXD (Note 2) CAN0_S1/S30 Software start (Note 2) SIO3_RXD (Note 2) CAN0_S1/S30 (Note 2) DRI(DIN2) SIO5_TXD (Note 1) TIN0S TOU1_6irq (Note 2) DRI(DIN3) SIO5_RXD (Note 1) TIN19S (Note 2) SIO0_TXD TOU1_7irq (Note 1) TIN7S (Note 2) DRI(DIN4) (Note 1) TIN20S TOU0_0irq (Note 1) TIN8S (Note 2) DRI(DEC0_udf) (Note 2) CAN1_S0/S31 TOU0_1irq (Note 2) SIO1_RXD (Note 2) DRI Address counter 0 transfer completed (Note 2) DRI(DEC1_udf) TOU0_6irq (Note 2) CAN1_S0/S31 (Note 2) DRI Latch event counter_udf (Note 2) DRI(DEC3_udf) TOU0_7irq (Note 2) DRI Transfer counter_udf (Note 2) DRI(DEC4_udf) (Note 2) DRI(DIN5) TOU0_2irq (Note 2) SIO3_TXD(Note 2) DRI Address counter 1 transfer completed (Note 2) DRI(DEC2_udf) (Note 2) CAN1_S1/S30 Software start (Note 2) SIO3_TXD (Note 2) CAN1_S1/S30 0123 Input event bus Output event bus 3210 3210 0123 Note 1: Indicates edge select input at the timer input pin. Note 2: Indicates an input signal from each peripheral circuit.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The diagram below shows a memory map of the DMAC related registers. DMAC Related Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0400 DMA0–4 Interrupt Request Status Register DMA0–4 Interrupt Request Mask Register 9-35 (DM04ITST) (DM04ITMK) 9-36 (Use inhibited area) H'0080 0408 DMA5–9 Interrupt Request Status Register DMA5–9 Interrupt Request Mask Register 9-35 (DM59ITST) (DM59ITMK) 9-36 (Use inhibited area) H'0080 0410 DMA0 Channel Control Register 0 DMA0 Channel Control Register 1 9-6 (DM0CNT0) (DM0CNT1) 9-7 H'0080 0412 DMA0 Source Address Register 9-30 (DM0SA) H'0080 0414 DMA0 Destination Address Register 9-31 (DM0DA) H'0080 0416 DMA0 Transfer Count Register 9-32 (DM0TCT) H'0080 0418 DMA5 Channel Control Register 0 DMA5 Channel Control Register 1 9-16 (DM5CNT0) (DM5CNT1) 9-17 H'0080 041A DMA5 Source Address Register 9-30 (DM5SA) H'0080 041C DMA5 Destination Address Register 9-31 (DM5DA) H'0080 041E DMA5 Transfer Count Register 9-32 (DM5TCT) H'0080 0420 DMA1 Channel Control Register 0 DMA1 Channel Control Register 1 9-8 (DM1CNT0) (DM1CNT1) 9-9 H'0080 0422 DMA1 Source Address Register 9-30 (DM1SA) H'0080 0424 DMA1 Destination Address Register 9-31 (DM1DA) H'0080 0426 DMA1 Transfer Count Register 9-32 (DM1TCT) H'0080 0428 DMA6 Channel Control Register 0 DMA6 Channel Control Register 1 9-18 (DM6CNT0) (DM6CNT1) 9-19 H'0080 042A DMA6 Source Address Register 9-30 (DM6SA) H'0080 042C DMA6 Destination Address Register 9-31 (DM6DA) H'0080 042E DMA6 Transfer Count Register 9-32 (DM6TCT) H'0080 0430 DMA2 Channel Control Register 0 DMA2 Channel Control Register 1 9-10 (DM2CNT0) (DM2CNT1) 9-11 H'0080 0432 DMA2 Source Address Register 9-30 (DM2SA) H'0080 0434 DMA2 Destination Address Register 9-31 (DM2DA) H'0080 0436 DMA2 Transfer Count Register 9-32 (DM2TCT) H'0080 0438 DMA7 Channel Control Register 0 DMA7 Channel Control Register 1 9-20 (DM7CNT0) (DM7CNT1) 9-21 H'0080 043A DMA7 Source Address Register 9-30 (DM7SA) H'0080 043C DMA7 Destination Address Register 9-31 (DM7DA) H'0080 043E DMA7 Transfer Count Register 9-32 (DM7TCT) H'0080 0440 DMA3 Channel Control Register 0 DMA3 Channel Control Register 1 9-12 (DM3CNT0) (DM3CNT1) 9-13 H'0080 0442 DMA3 Source Address Register 9-30 (DM3SA) H'0080 0444 DMA3 Destination Address Register 9-31 (DM3DA) H'0080 0446 DMA3 Transfer Count Register 9-32 (DM3TCT)

9-532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMAC Related Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0448 DMA8 Channel Control Register 0 DMA8 Channel Control Register 1 9-22 (DM8CNT0) (DM8CNT1) 9-23 H'0080 044A DMA8 Source Address Register 9-30 (DM8SA) H'0080 044C DMA8 Destination Address Register 9-31 (DM8DA) H'0080 044E DMA8 Transfer Count Register 9-32 (DM8TCT) H'0080 0450 DMA4 Channel Control Register 0 DMA4 Channel Control Register 1 9-14 (DM4CNT0) (DM4CNT1) 9-15 H'0080 0452 DMA4 Source Address Register 9-30 (DM4SA) H'0080 0454 DMA4 Destination Address Register 9-31 (DM4DA) H'0080 0456 DMA4 Transfer Count Register 9-32 (DM4TCT) H'0080 0458 DMA9 Channel Control Register 0 DMA9 Channel Control Register 1 9-24 (DM9CNT0) (DM9CNT1) 9-25 H'0080 045A DMA9 Source Address Register 9-30 (DM9SA) H'0080 045C DMA9 Destination Address Register 9-31 (DM9DA) H'0080 045E DMA9 Transfer Count Register 9-32 (DM9TCT) H'0080 0460 DMA0 Software Request Generation Register 9-29 (DM0SRI) H'0080 0462 DMA1 Software Request Generation Register 9-29 (DM1SRI) H'0080 0464 DMA2 Software Request Generation Register 9-29 (DM2SRI) H'0080 0466 DMA3 Software Request Generation Register 9-29 (DM3SRI) H'0080 0468 DMA4 Software Request Generation Register 9-29 (DM4SRI) (Use inhibited area) H'0080 0470 DMA5 Software Request Generation Register 9-29 (DM5SRI) H'0080 0472 DMA6 Software Request Generation Register 9-29 (DM6SRI) H'0080 0474 DMA7 Software Request Generation Register 9-29 (DM7SRI) H'0080 0476 DMA8 Software Request Generation Register 9-29 (DM8SRI) H'0080 0478 DMA9 Software Request Generation Register 9-29 (DM9SRI) (Use inhibited area) H'0080 0480 (Use inhibited area) DMA0 Channel Control Register 2 9-26 (DM0CNT2) H'0080 0482 (Use inhibited area) DMA1 Channel Control Register 2 9-26 (DM1CNT2) H'0080 0484 (Use inhibited area) DMA2 Channel Control Register 2 9-26 (DM2CNT2) H'0080 0486 (Use inhibited area) DMA3 Channel Control Register 2 9-26 (DM3CNT2) H'0080 0488 (Use inhibited area) DMA4 Channel Control Register 2 9-26 (DM4CNT2) (Use inhibited area) H'0080 0490 (Use inhibited area) DMA5 Channel Control Register 2 9-26 (DM5CNT2) H'0080 0492 (Use inhibited area) DMA6 Channel Control Register 2 9-26 (DM6CNT2) H'0080 0494 (Use inhibited area) DMA7 Channel Control Register 2 9-26 (DM7CNT2) H'0080 0496 (Use inhibited area) DMA8 Channel Control Register 2 9-26 (DM8CNT2) H'0080 0498 (Use inhibited area) DMA9 Channel Control Register 2 9-26 (DM9CNT2)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

9.2.1 DMA Channel Control Registers

DMA0 Channel Control Register 0 (DM0CNT0) <Address: H’0080 0410> 123456 b 7b0 SADSL0 DADSL0MDSEL0 TREQF0 REQSL0 TENL0 TSZSL0 00000000 <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL0 0: Normal mode R W

DMA0 transfer mode select bit 1: Ring buffer mode

1 TREQF0 0: Transfer not requested R(Note 1)

DMA0 transfer request flag bit 1: Transfer requested 2, 3 REQSL0 00: Software start or one DMA2 transfer completed R W DMA0 transfer request source select bit 01: A/D0 conversion completed 10: MJT (TIO8_udf) 11: Extended DMA0 transfer request source select (DMA0 Channel Control Register 1)

4 TENL0 0: Disable transfer R W

DMA0 transfer enable bit 1: Enable transfer

5 TSZSL0 0: 16 bits R W

DMA0 transfer size select bit 1: 8 bits

6 SADSL0 0: Fixed R W

DMA0 source address direction select bit 1: Increment

7 DADSL0 0: Fixed R W

DMA0 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9-732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA0 Channel Control Register 1 (DM0CNT1) <Address: H’0080 0411> 9 1 01 11 21 31 4 b 1 5b8 REQESEL0 00000000 SADBN0 DADBN0 <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 SADBN0 00: Bank 0 (A14=0, A15=0) R W Source address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 10, 11 DADBN0 00: Bank 0 (A14=0, A15=0) R W Destination address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 12–15 REQESEL0 0000: MJT (input event bus 2) R W Extended DMA0 transfer request source select bit 0001: MJT (TID0_udf/ovf) 0010: CAN (CAN0_S0/S31) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: MJT (TOU1_0irq) 1110: DRI (DIN0) 1111: SIO4_TXD (transimit buffer empty) Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the sour ce/ destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank2 does not exist in the 32196, setting Bank2(A14=1, A15=0) is prohibited. Also, because Bank1 and Bank2 do not exist in the 32195, setting Bank1(A14=0, A15=1), and Bank2(A14=1, A15=0) is prohibited.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA1 Channel Control Register 0 (DM1CNT0) <Address: H’0080 0420> 123456 b 7b0 SADSL1 DADSL1MDSEL1 TREQF1 REQSL1 TENL1 TSZSL1 00000000 <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL1 0: Normal mode R W

DMA1 transfer mode select bit 1: Ring buffer mode

1 TREQF1 0: Transfer not requested R(Note 1)

DMA1 transfer request flag bit 1: Transfer requested 2, 3 REQSL1 00: Software start R W DMA1 transfer request source select bit 01: MJT (output event bus 0) 10: Settings inhibited 11: Extended DMA1 transfer request source select (DMA1 Channel Control Register 1)

4 TENL1 0: Disable transfer R W

DMA1 transfer enable bit 1: Enable transfer

5 TSZSL1 0: 16 bits R W

DMA1 transfer size select bit 1: 8 bits

6 SADSL1 0: Fixed R W

DMA1 source address direction select bit 1: Increment

7 DADSL1 0: Fixed R W

DMA1 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9-932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA1 Channel Control Register 1 (DM1CNT1) <Address: H’0080 0421> 9 1 01 11 21 31 4 b 1 5b8 REQESEL1 00000000 SADBN1 DADBN1 <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 SADBN1 00: Bank 0 (A14=0, A15=0) R W Source address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 10, 11 DADBN1 00: Bank 0 (A14=0, A15=0) R W Destination address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 12–15 REQESEL1 0000: One DMA0 transfer completed R W Extended DMA1 transfer request source select bit 0001: MJT(TIN3S) 0010: MJT(TID1_udf/ovf) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: MJT (TOU1_1irq) 1110: DRI (DIN1) 1111: SIO4_RXD (reception completed) Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the sour ce/ destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank2 does not exist in the 32196, setting Bank2(A14=1, A15=0) is prohibited. Also, because Bank1 and Bank2 do not exist in the 32195, setting Bank1(A14=0, A15=1), and Bank2(A14=1, A15=0) is prohibited.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA2 Channel Control Register 0 (DM2CNT0) <Address: H’0080 0430> 123456 b 7b0 SADSL2 DADSL2MDSEL2 TREQF2 REQSL2 TENL2 TSZSL2 00000000 <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL2 0: Normal mode R W

DMA2 transfer mode select bit 1: Ring buffer mode

1 TREQF2 0: Transfer not requested R(Note 1)

DMA2 transfer request flag bit 1: Transfer requested 2, 3 REQSL2 00: Software start R W DMA2 transfer request source select bit 01: MJT (output event bus 1) 10: MJT (TIN18S) 11: Extended DMA2 transfer request source select (DMA2 Channel Control Register 1)

4 TENL2 0: Disable transfer R W

DMA2 transfer enable bit 1: Enable transfer

5 TSZSL2 0: 16 bits R W

DMA2 transfer size select bit 1: 8 bits

6 SADSL2 0: Fixed R W

DMA2 source address direction select bit 1: Increment

7 DADSL2 0: Fixed R W

DMA2 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9-1132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA2 Channel Control Register 1 (DM2CNT1) <Address: H’0080 0431> 9 1 01 11 21 31 4 b 1 5b8 REQESEL2 00000000 SADBN2 DADBN2 <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 SADBN2 00: Bank 0 (A14=0, A15=0) R W Source address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 10, 11 DADBN2 00: Bank 0 (A14=0, A15=0) R W Destination address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 12–15 REQESEL2 0000: One DMA1 transfer completed R W Extended DMA2 transfer request source select bit 0001: Settings inhibited 0010: CAN(CAN0_S1/S30) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: Settings inhibited 1110: DRI (DIN2) 1111: SIO5_TXD (transmit buffer empty) Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the sour ce/ destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank2 does not exist in the 32196, setting Bank2(A14=1, A15=0) is prohibited. Also, because Bank1 and Bank2 do not exist in the 32195, setting Bank1(A14=0, A15=1), and Bank2(A14=1, A15=0) is prohibited.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA3 Channel Control Register 0 (DM3CNT0) <Address: H’0080 0440> 123456 b 7b0 SADSL3 DADSL3MDSEL3 TREQF3 REQSL3 TENL3 TSZSL3 00000000 <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL3 0: Normal mode R W

DMA3 transfer mode select bit 1: Ring buffer mode

1 TREQF3 0: Transfer not requested R(Note 1)

DMA3 transfer request flag bit 1: Transfer requested 2, 3 REQSL3 00: Software start R W DMA3 transfer request source select bit 01: SIO0_TXD (transmit buffer empty) 10: SIO1_RXD (reception completed) 11: Extended DMA3 transfer request source select (DMA3 Channel Control Register 1)

4 TENL3 0: Disable transfer R W

DMA3 transfer enable bit 1: Enable transfer

5 TSZSL3 0: 16 bits R W

DMA3 transfer size select bit 1: 8 bits

6 SADSL3 0: Fixed R W

DMA3 source address direction select bit 1: Increment

7 DADSL3 0: Fixed R W

DMA3 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9-1332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA3 Channel Control Register 1 (DM3CNT1) <Address: H’0080 0441> 9 1 01 11 21 31 4 b 1 5b8 REQESEL3 00000000 SADBN3 DADBN3 <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 SADBN3 00: Bank 0 (A14=0, A15=0) R W Source address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 10, 11 DADBN3 00: Bank 0 (A14=0, A15=0) R W Destination address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 12–15 REQESEL3 0000: MJT(TIN0S) R W Extended DMA3 transfer request source select bit 0001: One DMA2 transfer completed 0010: Settings inhibited 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: MJT (TOU1_6irq) 1110: DRI (DIN3) 1111: SIO5_RXD (reception completed) Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the sour ce/ destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank2 does not exist in the 32196, setting Bank2(A14=1, A15=0) is prohibited. Also, because Bank1 and Bank2 do not exist in the 32195, setting Bank1(A14=0, A15=1), and Bank2(A14=1, A15=0) is prohibited.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA4 Channel Control Register 0 (DM4CNT0) <Address: H’0080 0450> 123456 b 7b0 SADSL4 DADSL4MDSEL4 TREQF4 REQSL4 TENL4 TSZSL4 00000000 <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL4 0: Normal mode R W

DMA4 transfer mode select bit 1: Ring buffer mode

1 TREQF4 0: Transfer not requested R(Note 1)

DMA4 transfer request flag bit 1: Transfer requested 2, 3 REQSL4 00: Software start R W DMA4 transfer request source select bit 01: One DMA3 transfer completed 10: SIO0_RXD (reception completed) 11: Extended DMA4 transfer request source select (DMA4 Channel Control Register 1)

4 TENL4 0: Disable transfer R W

DMA4 transfer enable bit 1: Enable transfer

5 TSZSL4 0: 16 bits R W

DMA4 transfer size select bit 1: 8 bits

6 SADSL4 0: Fixed R W

DMA4 source address direction select bit 1: Increment

7 DADSL4 0: Fixed R W

DMA4 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9-1532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA4 Channel Control Register 1 (DM4CNT1) <Address: H’0080 0451> 9 1 01 11 21 31 4 b 1 5b8 REQESEL4 00000000 SADBN4 DADBN4 <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 SADBN4 00: Bank 0 (A14=0, A15=0) R W Source address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 10, 11 DADBN4 00: Bank 0 (A14=0, A15=0) R W Destination address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 12–15 REQESEL4 0000: MJT(TIN19S) R W Extended DMA4 transfer request source select bit 0001: SIO0_TXD (transmit buffer empty) 0010: MJT(TOU1_7irq) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: MJT (TIN7S) 1110: DRI (DIN4) 1111: Settings inhibited Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the sour ce/ destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank2 does not exist in the 32196, setting Bank2(A14=1, A15=0) is prohibited. Also, because Bank1 and Bank2 do not exist in the 32195, setting Bank1(A14=0, A15=1), and Bank2(A14=1, A15=0) is prohibited.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA5 Channel Control Register 0 (DM5CNT0) <Address: H’0080 0418> 123456 b 7b0 SADSL5 DADSL5MDSEL5 TREQF5 REQSL5 TENL5 TSZSL5 00000000 <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL5 0: Normal mode R W

DMA5 transfer mode select bit 1: Ring buffer mode

1 TREQF5 0: Transfer not requested R(Note 1)

DMA5 transfer request flag bit 1: Transfer requested 2, 3 REQSL5 00: Software start or one DMA7 transfer completed R W DMA5 transfer request source select bit 01: All DMA0 transfers completed 10: SIO2_RXD (reception completed) 11: Extended DMA5 transfer request source select (DMA5 Channel Control Register 1)

4 TENL5 0: Disable transfer R W

DMA5 transfer enable bit 1: Enable transfer

5 TSZSL5 0: 16 bits R W

DMA5 transfer size select bit 1: 8 bits

6 SADSL5 0: Fixed R W

DMA5 source address direction select bit 1: Increment

7 DADSL5 0: Fixed R W

DMA5 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9-1732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA5 Channel Control Register 1 (DM5CNT1) <Address: H’0080 0419> 9 1 01 11 21 31 4 b 1 5b8 REQESEL5 00000000 SADBN5 DADBN5 <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 SADBN5 00: Bank 0 (A14=0, A15=0) R W Source address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 10, 11 DADBN5 00: Bank 0 (A14=0, A15=0) R W Destination address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 12–15 REQESEL5 0000: MJT(TIN20S) R W Extended DMA5 transfer request source select bit 0001: MJT(TOU0_0irq) 0010: Settings inhibited 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: MJT (TIN8S) 1110: DRI (DEC0_udf) 1111: CAN1_S0/S31 Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the sour ce/ destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank2 does not exist in the 32196, setting Bank2(A14=1, A15=0) is prohibited. Also, because Bank1 and Bank2 do not exist in the 32195, setting Bank1(A14=0, A15=1), and Bank2(A14=1, A15=0) is prohibited.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA6 Channel Control Register 0 (DM6CNT0) <Address: H’0080 0428> 123456 b 7b0 SADSL6 DADSL6MDSEL6 TREQF6 REQSL6 TENL6 TSZSL6 00000000 <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL6 0: Normal mode R W

DMA6 transfer mode select bit 1: Ring buffer mode

1 TREQF6 0: Transfer not requested R(Note 1)

DMA6 transfer request flag bit 1: Transfer requested 2, 3 REQSL6 00: Software start R W DMA6 transfer request source select bit 01: SIO1_TXD (transmit buffer empty) 10: CAN0_S0/S31 11: Extended DMA6 transfer request source select (DMA6 Channel Control Register 1)

4 TENL6 0: Disable transfer R W

DMA6 transfer enable bit 1: Enable transfer

5 TSZSL6 0: 16 bits R W

DMA6 transfer size select bit 1: 8 bits

6 SADSL6 0: Fixed R W

DMA6 source address direction select bit 1: Increment

7 DADSL6 0: Fixed R W

DMA6 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9-1932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA6 Channel Control Register 1 (DM6CNT1) <Address: H’0080 0429> 9 1 01 11 21 31 4 b 1 5b8 REQESEL6 00000000 SADBN6 DADBN6 <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 SADBN6 00: Bank 0 (A14=0, A15=0) R W Source address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 10, 11 DADBN6 00: Bank 0 (A14=0, A15=0) R W Destination address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 12–15 REQESEL6 0000: One DMA5 transfer completed R W Extended DMA6 transfer request source select bit 0001: MJT(TOU0_1irq) 0010: SIO1_RXD (reception completed) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: DRI (address counter 0 transfer) 1110: DRI (DEC1_udf) 1111: Settings inhibited Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the sour ce/ destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank2 does not exist in the 32196, setting Bank2(A14=1, A15=0) is prohibited. Also, because Bank1 and Bank2 do not exist in the 32195, setting Bank1(A14=0, A15=1), and Bank2(A14=1, A15=0) is prohibited.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA7 Channel Control Register 0 (DM7CNT0) <Address: H’0080 0438> 123456 b 7b0 SADSL7 DADSL7MDSEL7 TREQF7 REQSL7 TENL7 TSZSL7 00000000 <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL7 0: Normal mode R W

DMA7 transfer mode select bit 1: Ring buffer mode

1 TREQF7 0: Transfer not requested R(Note 1)

DMA7 transfer request flag bit 1: Transfer requested 2, 3 REQSL7 00: Software start R W DMA7 transfer request source select bit 01: SIO2_TXD (transmit buffer empty) 10: CAN0_S1/S30 11: Extended DMA7 transfer request source select (DMA7 Channel Control Register 1)

4 TENL7 0: Disable transfer R W

DMA7 transfer enable bit 1: Enable transfer

5 TSZSL7 0: 16 bits R W

DMA7 transfer size select bit 1: 8 bits

6 SADSL7 0: Fixed R W

DMA7 source address direction select bit 1: Increment

7 DADSL7 0: Fixed R W

DMA7 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9-2132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA7 Channel Control Register 1 (DM7CNT1) <Address: H’0080 0439> 9 1 01 11 21 31 4 b 1 5b8 REQESEL7 00000000 SADBN7 DADBN7 <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 SADBN7 00: Bank 0 (A14=0, A15=0) R W Source address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 10, 11 DADBN7 00: Bank 0 (A14=0, A15=0) R W Destination address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 12–15 REQESEL7 0000: One DMA6 transfer completed R W Extended DMA7 transfer request source select bit 0001: MJT(TOU0_2irq) 0010: SIO3_TXD (transmit buffer empty) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: DRI (address counter 1 transfer) 1110: DRI (DEC2_udf) 1111: CAN1_S1/S30 Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the sour ce/ destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank2 does not exist in the 32196, setting Bank2(A14=1, A15=0) is prohibited. Also, because Bank1 and Bank2 do not exist in the 32195, setting Bank1(A14=0, A15=1), and Bank2(A14=1, A15=0) is prohibited.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA8 Channel Control Register 0 (DM8CNT0) <Address: H’0080 0448> 123456 b 7b0 SADSL8 DADSL8MDSEL8 TREQF8 REQSL8 TENL8 TSZSL8 00000000 <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL8 0: Normal mode R W

DMA8 transfer mode select bit 1: Ring buffer mode

1 TREQF8 0: Transfer not requested R(Note 1)

DMA8 transfer request flag bit 1: Transfer requested 2, 3 REQSL8 00: Software start R W DMA8 transfer request source select bit 01: MJT (input event bus 0) 10: SIO3_RXD (reception completed) 11: Extended DMA8 transfer request source selected (DMA8 Channel Control Register 1)

4 TENL8 0: Disable transfer R W

DMA8 transfer enable bit 1: Enable transfer

5 TSZSL8 0: 16 bits R W

DMA8 transfer size select bit 1: 8 bits

6 SADSL8 0: Fixed R W

DMA8 source address direction select bit 1: Increment

7 DADSL8 0: Fixed R W

DMA8 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9-2332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA8 Channel Control Register 1 (DM8CNT1) <Address: H’0080 0449> 9 1 01 11 21 31 4 b 1 5b8 REQESEL8 00000000 SADBN8 DADBN8 <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 SADBN8 00: Bank 0 (A14=0, A15=0) R W Source address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 10, 11 DADBN8 00: Bank 0 (A14=0, A15=0) R W Destination address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 12–15 REQESEL8 0000: CAN1_S0/S31 R W Extended DMA8 transfer request source select bit 0001: MJT(TOU0_6irq) 0010: One DMA7 transfer completed 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: DRI (latch event counter_udf) 1110: DRI (DEC3_udf) 1111: Settings inhibited Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the sour ce/ destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank2 does not exist in the 32196, setting Bank2(A14=1, A15=0) is prohibited. Also, because Bank1 and Bank2 do not exist in the 32195, setting Bank1(A14=0, A15=1), and Bank2(A14=1, A15=0) is prohibited.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA9 Channel Control Register 0 (DM9CNT0) <Address: H’0080 0458> 123456 b 7b0 SADSL9 DADSL9MDSEL9 TREQF9 REQSL9 TENL9 TSZSL9 00000000 <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL9 0: Normal mode R W

DMA9 transfer mode select bit 1: Ring buffer mode

1 TREQF9 0: Transfer not requested R(Note 1)

DMA9 transfer request flag bit 1: Transfer requested 2, 3 REQSL9 00: Software start R W DMA9 transfer request source select bit 01: SIO3_TXD (transmit buffer empty) 10: CAN1_S1/S30 11: Extended DMA9 transfer request source selected (DMA9 Channel Control Register 1)

4 TENL9 0: Disable transfer R W

DMA9 transfer enable bit 1: Enable transfer

5 TSZSL9 0: 16 bits R W

DMA9 transfer size select bit 1: 8 bits

6 SADSL9 0: Fixed R W

DMA9 source address direction select bit 1: Increment

7 DADSL9 0: Fixed R W

DMA9 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

9-2532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA9 Channel Control Register 1 (DM9CNT1) <Address: H’0080 0459> 9 1 01 11 21 31 4 b 1 5b8 REQESEL9 00000000 SADBN9 DADBN9 <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 SADBN9 00: Bank 0 (A14=0, A15=0) R W Source address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 10, 11 DADBN9 00: Bank 0 (A14=0, A15=0) R W Destination address bank select bit 01: Bank 1 (A14=0, A15=1) (Note 1)(Note 2) 10: Bank 2 (A14=1, A15=0) 11: Settings inhibited 12–15 REQESEL9 0000: One DMA8 transfer completed R W Extended DMA9 transfer request source select bit 0001: MJT(TOU0_7irq) 0010: Settings inhibited 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Common 8) MJT (TIN30S) 1011: Common 9) MJT (TIO9_udf) 1100: Common 10) Settings inhibited 1101: DRI (transfer counter_udf) 1110: DRI (DEC4_udf) 1111: DRI (DIN5) Note 1: No transfer over the bank is possible. Even when the address is incremented at the breakpoint of the bank and the sour ce/ destination addresses go over the bank, the source address bank select/destination address bank select bits are not incremented, and the bank head corresponds to the source address/destination address. Note 2: Because Bank2 does not exist in the 32196, setting Bank2(A14=1, A15=0) is prohibited. Also, because Bank1 and Bank2 do not exist in the 32195, setting Bank1(A14=0, A15=1), and Bank2(A14=1, A15=0) is prohibited.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA0 Channel Control Register 2 (DM0CNT2) <Address: H’0080 0481> DMA1 Channel Control Register 2 (DM1CNT2) <Address: H’0080 0483> DMA2 Channel Control Register 2 (DM2CNT2) <Address: H’0080 0485> DMA3 Channel Control Register 2 (DM3CNT2) <Address: H’0080 0487> DMA4 Channel Control Register 2 (DM4CNT2) <Address: H’0080 0489> DMA5 Channel Control Register 2 (DM5CNT2) <Address: H’0080 0491> DMA6 Channel Control Register 2 (DM6CNT2) <Address: H’0080 0493> DMA7 Channel Control Register 2 (DM7CNT2) <Address: H’0080 0495> DMA8 Channel Control Register 2 (DM8CNT2) <Address: H’0080 0497> DMA9 Channel Control Register 2 (DM9CNT2) <Address: H’0080 0499> 9 10 11 12 13 14 b15b8 0 000000 RINGSELSELFEN <Upon exiting reset: H’00> b Bit Name Function R W

8 SELFEN 0: Disable self channel transfer R W

Self channel transfer selection 1: Enable self channel transfer 9 No function assigned. Fix to "0." 00 10–15 RINGSEL 00 0000: 32-time ring buffer mode R W RIng buffer select bit 10 0000: 32-time ring buffer mode 11 0000: 16-time ring buffer mode 11 1000: 8-time ring buffer mode 11 1100: 4-time ring buffer mode 11 1110: 2-time ring buffer mode Settings other than above are inhibited The DMA Channel Control Register 0 consists of the bits to select DMA transfer mode on each channel, set the DMA transfer request flag, select the cause or source of DMA request and enable DMA transfer, as well as those to set the transfer size and the source/destination address directions. The DMA Channel Control Register 1 consists of the bits to select a source/destination address bank and the cause or source of extended DMA transfer request on each DMA channel. The DMA Channel Control Register 2 consists of the bits to enable self channel transfer on each channel and set the number of transfers in the ring buffer mode.

9-2732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 [DMnCNT0 Register] (1) MDSELn (DMAn Transfer Mode Select) bit (Bit 0) When performing DMA transfer in single transfer mode, this bit selects normal mode or ring buffer mode. Setting this bit to "0" selects normal mode and setting it to "1" selects ring buffer mode. The number of transfers in the ring buffer mode is selected with register DMnCNT2. (2) TREQFn (DMAn Transfer Request Flag) bit (Bit 1) This flag indicates if there are DMA transfer requests for each channel. This bit is set to "1," when DMA transfer requests are occurred in spite of TENLn bit setting value and then after completing transmission, it is cleared to "0." And when write "0" to this bit, it clear DMA transfer requests occurred. When write "1," it keeps value which before writing. If a new DMA transfer request occurs on a channel for which the DMA transfer request flag has already been set to "1," the next DMA transfer request is not accepted until the transfer being performed on that channel is completed. (3) REQSLn (DMAn Transfer Request Source Select) bits (Bits 2, 3) These bits select the cause or source of DMA transfer request on each DMA channel. (4) TENLn (DMAn Transfer Enable) bit (Bit 4) When setting this bit to "1" (enable transfer), DMA transfer is enable and when all transmissions are com- pleted (underflow of transfer count register), it is cleared to "0." And when DMA transfer request is already occurred and set to transfer enable, DMA transfer starts immediately so that make sure not to do that. When setting this bit to "0" (disable transfer), DMA transfer is disable. However, if a transfer request has already been accepted, transfers on that channel are not disabled until after the requested transfer is com- pleted. (5) TSZSLn (DMAn Transfer Size Select) bit (Bit 5) This bit selects the number of bits to be transferred in one DMA transfer operation (the unit of one transfer). The unit of one transfer is 16 bits when TSZSL = "0" or 8 bits when TSZSL = "1." (6) SADSLn (DMAn Source Address Direction Select) bit (Bit 6) This bit selects the direction in which the source address changes. This mode can be selected from two choices: Address fixed or Address incremental. (7) DADSLn (DMAn Destination Address Direction Select) bit (Bit 7) This bit selects the direction in which the destination address changes. This mode can be selected from two choices: Address fixed or Address incremental. Extended DMA transfer request source selected DMAn transfer request sourceS S DMAn Figure 9.2.1 Block Diagram of Extended DMAn Transfer Request Source Selection

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 [DMnCNT1 Register] (1) SADBNx (DMAn Source Address Bank Select) bits (Bits 8, 9) These bits select a source address bank to be used from among Bank 0, Bank 1 and Bank 2. But no bank exsits in 32196, setting Bank2(A14=1, A15=0) is prohibited. Because Bank1 and Bank2 do not exist in the 32195, setting Bank1 and Bank2 is prohibited. And also no transfer over the bank is carried out. Upon completion of bank transfer to the final address, the bank is then to be transferred to the head address. (2) DADBNx (DMAn Destination Address Bank Select) bits (Bits 10, 11) These bits select a destination address bank to be used from among Bank 0, Bank 1 and Bank 2. But no bank exsits in 32196, setting Bank2(A14=1, A15=0) is prohibited. Because Bank1 and Bank2 do not exist in the 32195, setting Bank1 and Bank2 is prohibited. And also no transfer over the bank is carried out. Upon completion of bank transfer to the final address, the bank is then to be transferred to the head address. (3) REQESELn (Extended DMAn Transfer Request Source Select) bits (Bits 12–15) These bits select the cause or source of extended DMA transfer request on each DMA channel. Note: • The extended DMA transfer request sources selected by the REQESELn (Extended DMAn Transfer Request Source Select) bits have no effect unless the “Extended” DMA transfer re- quest source is selected with the DMA Channel Control Register’s DMA Request Source Se- lect (REQSLn) bits. [DMnCNT2 Register] (1) SELFEN (DMAn Self Channel Transfer Select ) bit (Bit 8) Clearing this bit to “0” disables self channel transfer, and setting it to “1” enables self channel transfer. In case where self channel transfer was allowed, the DMA transfer request occurs for the self channel each time single DMA transfer is completed if the initial transfer request arises, and DMA transfer is carried out until all transfers are completed (transfer count register underflow). However the control of internal bus is relinquished each time single DMA transfer is completed. And if set DMA transfer n times, DMA transfer request is occured for its channel after completing all DMA transfer, so that it is necessary to pay attention of clearing DMA transfer request or so on when DMA transfer is started again. (2) RINGSEL (DMAn Rign Buffer Select) bit (Bits 10–15) These bits select the number of DMA transfers to each channel in the ring buffer mode from among 32, 16, 8, 4 and 2 times. In the ring buffer mode, after transfer from the transfer start address, the bit returns to the transfer start address again, and the same operation is repeated by the number of transfers thus selected. In the ring buffer mode, the transfer count register is placed in the free run mode, and transfer operation is continued until the transfer enable bit is cleared to “0” (transfer disable). Also, the DMA transfer-completed interrupt request does not arise during ring buffer mode. Notes: • When the self channel transfer was allowed during ring buffer mode setting, care must be exercised to its endless transfer.

• The transfer start address must be as follows: Transfer Size: 8 bits Transfer Size: 16 bits 32-time ring buffer mode Low order 5 bits – B’00000 Low order 6 bits – B’000000 16-time ring buffer mode Low order 4 bits – B’0000 Low order 5 bits – B’00000 8-time ring buffer mode Low order 3 bits – B’000 Low order 4 bits – B’0000 4-time ring buffer mode Low order 2 bits – B’00 Low order 3 bits – B’000 2-time ring buffer mode Low order 1 bits – B’0 Low order 2 bits – B’00

9-2932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

9.2.2 DMA Software Request Generation Registers

DMA0 Software Request Generation Register (DM0SRI) <Address: H’0080 0460> DMA1 Software Request Generation Register (DM1SRI) <Address: H’0080 0462> DMA2 Software Request Generation Register (DM2SRI) <Address: H’0080 0464> DMA3 Software Request Generation Register (DM3SRI) <Address: H’0080 0466> DMA4 Software Request Generation Register (DM4SRI) <Address: H’0080 0468> DMA5 Software Request Generation Register (DM5SRI) <Address: H’0080 0470> DMA6 Software Request Generation Register (DM6SRI) <Address: H’0080 0472> DMA7 Software Request Generation Register (DM7SRI) <Address: H’0080 0474> DMA8 Software Request Generation Register (DM8SRI) <Address: H’0080 0476> DMA9 Software Request Generation Register (DM9SRI) <Address: H’0080 0478> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 DM0SRI–DM9SRI <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 DM0SRI–DM9SRI DMA transfer request is generated by writing any ? W DMA software request generation bits data to these bits. Note: • This register may be accessed in either bytes or halfwords. The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA transfer request can be generated by writing any data to this register when “Software start” has been selected for the cause of DMA transfer request. (1) DM0SRI–DM9SRI (DMA Software Request Generation) bits A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in byte (8 bits) beginning with an even or odd address when “Software start” is selected as the cause of DMA transfer request (by setting the DMAn Channel Control Register 0 bits 2–3 to "00").

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

9.2.3 DMA Source Address Registers

DMA0 Source Address Register (DM0SA) <Address: H’0080 0412> DMA1 Source Address Register (DM1SA) <Address: H’0080 0422> DMA2 Source Address Register (DM2SA) <Address: H’0080 0432> DMA3 Source Address Register (DM3SA) <Address: H’0080 0442> DMA4 Source Address Register (DM4SA) <Address: H’0080 0452> DMA5 Source Address Register (DM5SA) <Address: H’0080 041A> DMA6 Source Address Register (DM6SA) <Address: H’0080 042A> DMA7 Source Address Register (DM7SA) <Address: H’0080 043A> DMA8 Source Address Register (DM8SA) <Address: H’0080 044A> DMA9 Source Address Register (DM9SA) <Address: H’0080 045A> b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 DM0SA–DM9SA <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 DM0SA–DMA9SA Source address bits A16–A31 R W (Note 1) Note 1: A0 to A15 are fixed by setting DMAn Channel Control Register 1 (DMnCNT1) bits 8 and 9. Notes: • This register must always be accessed in halfwords.

• Address other than SFR area and internal RAM area must not be set. The DMA Source Address Register is used to set the source address of DMA transfer in such a way that bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the values read from this register are always the current value. When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Source Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. (1) DM0SA–DM9SA (Source Address bits A16–A31) Set this register to specify the source address of DMA transfer in SFR area or internal RAM area. For high-order 16 bits (A0 to A15) of the source address, the high-order 16 bits of the corresponding source address are fixed by setting of DMAn channel control register 1 (DMnCNT1) bits 8 and 9. In this register, the low-order 16 bits of the source address are set. (Bit 0 and bit 15 correspond to A16 and A31 of the source address, respectively). Note that when SADSLn bit in DMAn channel control register (DMnCNT0) set to "increment," no transfer over the bank is carried out. Upon completion of bank transfer to the final address, the bank is to be transferred to the head address.

9-3132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

9.2.4 DMA Destination Address Registers

DMA0 Destination Address Register (DM0DA) <Address: H’0080 0414> DMA1 Destination Address Register (DM1DA) <Address: H’0080 0424> DMA2 Destination Address Register (DM2DA) <Address: H’0080 0434> DMA3 Destination Address Register (DM3DA) <Address: H’0080 0444> DMA4 Destination Address Register (DM4DA) <Address: H’0080 0454> DMA5 Destination Address Register (DM5DA) <Address: H’0080 041C> DMA6 Destination Address Register (DM6DA) <Address: H’0080 042C> DMA7 Destination Address Register (DM7DA) <Address: H’0080 043C> DMA8 Destination Address Register (DM8DA) <Address: H’0080 044C> DMA9 Destination Address Register (DM9DA) <Address: H’0080 045C> b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 DM0DA–DM9DA <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 DM0DA–DM9DA Destination address bits A16–A31 R W (Note 1) Note 1: A0 to A15 are fixed by setting DMAn Channel Control Register 1 (DMnCNT1) bits 10 and 11. Notes: • This register must always be accessed in halfwords.

• Address other than SFR area and internal RAM area must not be set. The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the values read from this register are always the current value. When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Destination Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. (1) DM0DA–DM9DA (Destination Address bits A16–A31) Set this register to specify the destination address of DMA transfer in SFR area or internal RAM area. For high-order 16 bits (A0 to A15) of the destination address, Bank 0 to Bank 2 are selected according to the setting of DMAn channel control register 1 (DMnCNT1) bits 10 and 11, and the high-order 16 bits of the corresponding destination address are fixed. In this register, the low-order 16 bits of the destination ad- dress are set. (Bit 0 and bit 15 correspond to A16 and A31 of the destination address, respectively) Note that when SADSLn bit in DMAn channel control register (DMnCNT0) set to "increment," no transfer over the bank is carried out. Upon completion of bank transfer to the final address, the bank is to be transferred to the head address.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

9.2.5 DMA Transfer Count Registers

DMA0 Transfer Count Register (DM0TCT) <Address: H’0080 0416> DMA1 Transfer Count Register (DM1TCT) <Address: H’0080 0426> DMA2 Transfer Count Register (DM2TCT) <Address: H’0080 0436> DMA3 Transfer Count Register (DM3TCT) <Address: H’0080 0446> DMA4 Transfer Count Register (DM4TCT) <Address: H’0080 0456> DMA5 Transfer Count Register (DM5TCT) <Address: H’0080 041E> DMA6 Transfer Count Register (DM6TCT) <Address: H’0080 042E> DMA7 Transfer Count Register (DM7TCT) <Address: H’0080 043E> DMA8 Transfer Count Register (DM8TCT) <Address: H’0080 044E> DMA9 Transfer Count Register (DM9TCT) <Address: H’0080 045E> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 DM0TCT–DM15TCT <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 DM0TCT–DM9TCT DMA transfer count R W (Has no effect during ring buffer mode) Note: • This register must always be accessed in halfwords. The DMA Transfer Count Register is used to set the number of times data is transferred on each channel. However, the value in this register has no effect during ring buffer mode. The transfer count is the value set in the transfer count register + 1. Because the DMA Transfer Count Register is comprised of a current register, the values read from this register are always the current value. (However, if the register is read in a cycle immediately after transfer, the value obtained is one that was stored in the count register before the transfer began.) When transfer finishes, this count register underflows and the value read from it is H’FFFF. When transfer is enabled, this register is protected in hardware and cannot be accessed for write. During ring buffer mode, the transfer count register counts down in free-run mode and continues counting until transfer is disabled. No interrupt is generated at underflow. If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all trans- fers on a channel are completed (i.e., the transfer count register underflows), transfer on the cascaded channel starts. The DMA Transfer Count Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined.

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9.2.6 DMA Interrupt Related Registers

The DMA interrupt related registers are used to control the interrupt request signals sent from the DMAC to the Interrupt Controller. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0." Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt request mask bit, it can be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "0" to enable interrupt requests or "1" to disable interrupt requests. Figure 9.2.2 Interrupt Request Status and Mask Registers To the Interrupt Controller Interrupt request from each peripheral function Interrupt request status Data bus Set Group interrupt Interrupt request enabled clear F/F F/F Data = 0

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 9.2.3 Example for Clearing Interrupt Request Status b4 5 b7 Interrupt request status Initial state Event occurs on bit 6 Interrupt request Event occurs on bit 4 Only bit 6 cleared Bit 4 data retained b4 5 b7 1 1 0 1 Write to the interrupt request status Example for clearing interrupt request status 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 Program example ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */  To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. b4 5 6 b7 Interrupt request status Event occurs on bit 6 Event occurs on bit 4 Only bit 6 cleared Bit 4 also cleared 0 0 1 0 1 0 1 0 0 0 0 0 Read 0 0 1 0 0 0 0 0 Clear bit 6 (AND'ing with 1101) Write ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */

9-3532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA0–4 Interrupt Request Status Register (DM04ITST) <Address: H’0080 0400> 123456 b 7b0 DMITST4 DMITST3 DMITST1 DMITST0DMITST2 000000 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0." 00

3 DMITST4 (DMA4 interrupt request status bit) 0: Interrupt not requested R(Note 1)

4 DMITST3 (DMA3 interrupt request status bit) 1: Interrupt requested

5 DMITST2 (DMA2 interrupt request status bit)

6 DMITST1 (DMA1 interrupt request status bit)

7 DMITST0 (DMA0 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA5–9 Interrupt Request Status Register (DM59ITST) <Address: H’0080 0408> 123456 b 7b0 DMITST9 DMITST8 DMITST6 DMITST5DMITST7 000000 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0." 00

3 DMITST9 (DMA9 interrupt request status bit) 0: Interrupt not requested R(Note 1)

4 DMITST8 (DMA8 interrupt request status bit) 1: Interrupt requested

5 DMITST7 (DMA7 interrupt request status bit)

6 DMITST6 (DMA6 interrupt request status bit)

7 DMITST5 (DMA5 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. The Interrupt Request Status Register helps to know the status of interrupt requests on each channel. If the DMAn interrupt request status bit (n = 0–9) is set to "1," it means that a DMA interrupt request on the correspond- ing channel has been generated. (1) DMITSTn (DMAn Interrupt Request Status) bit (n = 0–9) [Setting the DMAn interrupt request status bit] This bit is set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing "0" in software. Note: • The DMAn interrupt request status bit cannot be cleared by writing "0" to the DMA Interrupt Control Register’s “interrupt request bit” included in the Interrupt Controller. When writing to the DMA Interrupt Request Status Register, make sure only the bits to be cleared are set to "0" and all other bits are set to "1." Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA0–4 Interrupt Request Mask Register (DM04ITMK) <Address: H’0080 0401> 9 1 01 11 21 31 4 b 1 5b8 DMITMK4 DMITMK3 DMITMK1 DMITMK0DMITMK2 000000 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0." 00

11 DMITMK4 (DMA4 interrupt request mask bit) 0: Enable interrupt request R W

12 DMITMK3 (DMA3 interrupt request mask bit) 1: Mask (disable) interrupt request

13 DMITMK2 (DMA2 interrupt request mask bit)

14 DMITMK1 (DMA1 interrupt request mask bit)

15 DMITMK0 (DMA0 interrupt request mask bit)

DMA5–9 Interrupt Request Mask Register (DM59ITMK) <Address: H’0080 0409> 9 1 01 11 21 31 4 b 1 5b8 DMITMK9 DMITMK8 DMITMK6 DMITMK5DMITMK7 000000 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0." 00

11 DMITMK9 (DMA9 interrupt request mask bit) 0: Enable interrupt request R W

12 DMITMK8 (DMA8 interrupt request mask bit) 1: Mask (disable) interrupt request

13 DMITMK7 (DMA7 interrupt request mask bit)

14 DMITMK6 (DMA6 interrupt request mask bit)

15 DMITMK5 (DMA5 interrupt request mask bit)

The DMA Interrupt Request Mask Register is used to mask interrupt requests on each DMA channel. (1) DMITMKn (DMAn Interrupt Request Mask) bit (n = 0–9) Setting the DMAn interrupt request mask bit to "1" masks the interrupt requests on DMAn channel. How- ever, if an interrupt request occurs, the DMAn interrupt request status bit is always set to "1" irrespective of the contents of this mask register.

9-3732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 F/F F/F DMITMK5 DMITST5 F/F F/F DMITMK6 DMITST6 F/F F/F DMITMK7 DMITST7 F/F F/F DMITMK8 DMITST8 F/F F/F DMITMK9 DMITST9 b15 b14 b13 b12 b11 Data bus DMA9UDF DMA8UDF DMA7UDF DMA6UDF DMA5UDF DMA transfer interrupt request 1(Level) 5-source inputs DM59ITST (H'0080 0408) DM59ITMK (H'0080 0409) Figure 9.2.5 Block Diagram of DMA Transfer Interrupt Request 1 F/F F/F DMITMK0 DMITST0 F/F F/F DMITMK1 DMITST1 F/F F/F DMITMK2 DMITST2 F/F F/F DMITMK3 DMITST3 F/F F/F DMITMK4 DMITST4 b15 b14 b13 b12 b11 Data bus DMA4UDF DMA3UDF DMA2UDF DMA1UDF DMA0UDF DMA transfer interrupt request 0(Level) 5-source inputs DM04ITST (H'0080 0400) DM04ITMK (H'0080 0401) Figure 9.2.4 Block Diagram of DMA Transfer Interrupt Request 0

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

9.3.1 DMA Transfer Request Sources

For each DMA channel (channels 0–9), DMA transfer can be requested from two or more sources. There are various causes or sources of DMA transfer request, so that DMA transfer can be started by a request from some internal peripheral I/O, in software by a program, or upon completion of one transfer or all transfers on another DMA channel (cascade mode). The causes or sources of DMA transfer requests are selected using the transfer request source select bits REQSLn on each channel (DMAn Channel Control Register 0 bits 2–3) or the extended transfer request source select bits REQESELn (DMAn Channel Control Register 1 bits 12–15). The tables below list the causes or sources of DMA transfer requests on each channel. Table 9.3.1 DMA Transfer Request Sources and Generation Timings on DMA0 REQSL0 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start or one DMA2 When any data is written to the DMA0 Software Request Generation transfer completed Register (software start) or when one DMA2 transfer is completed (cascade mode) 0 1 A/D0 conversion completed When A/D0 conversion is completed 1 0 MJT (TIO8_udf) When MJT TIO8 underflows 1 1 Extended DMA0 transfer request The source selected by the DMA0 Channel Control Register 1 source selected (DM0CNT1) REQESEL0 bits (see below) REQESEL0 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 MJT (input event bus 2) When MJT input event bus 2 signal is generated

0001 MJT (TID0_udf/ovf) When MJT TID0 underflow/overflow occurs

0010 CAN (CAN0_S0/S31) When CAN0 slot 0 transmission failed or slot 31 transmission/reception

0011 Common 1) MJT (input event bus 1) When MJT input event bus 1 signal is generated

0100 Common 2) MJT (input event bus 3) When MJT input event bus 3 signal is generated

0101 Common 3) MJT (output event bus 2) When MJT output event bus 2 signal is generated

0110 Common 4) MJT (output event bus 3) When MJT output event bus 3 signal is generated

0111 Common 5) A/D0 conversion completed When A/D0 conversion is completed

1000 Common 6) MJT (TIN0S) When MJT TIN0 input signal is generated

1001 Common 7) MJT (TIO8_udf) When MJT TIO8 underflow occurs

1010 Common 8) MJT (TIN30S) When MJT TIN30 input signal is generated

1011 Common 9) MJT (TIO9_udf) When MJT TIO9 underflow occurs

1100 Common 10) Settings inhibited –

1101 MJT (TOU1_0irq) When MJT TOU1_0 interrupt request is generated

1110 DRI (DIN0) When DRI DIN0 event detection interrupt is generated

1111 SIO4_TXD (transmit buffer empty) When SIO4 transmit buffer empty interrupt is generated

9-3932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 9.3.2 DMA Transfer Request Sources and Generation Timings on DMA1 REQSL1 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA1 Software Request Generation Register 0 1 MJT (output event bus 0) When MJT output event bus 0 signal is generated 1 0 Settings inhibited – 1 1 Extended DMA1 transfer request The source selected by the DMA1 Channel Control Register 1 source selected (DM1CNT1) REQESEL1 bits (see below) REQESEL1 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 One DMA0 transfer completed When one DMA0 transfer is completed (cascade mode)

0001 MJT (TIN3S) When MJT TIN3 input signal is generated

0010 MJT (TID1_udf/ovf) When MJT TID1 underflow/overflow occurs

1101 MJT (TOU1_1irq) When TOU1_1 interrupt request is generated

1110 DRI (DIN1) When DRI DIN1 event detection interrupt is generated

1111 SIO4_RXD (reception completed) When SIO4 reception-completed interrupt is generated

Table 9.3.3 DMA Transfer Request Sources and Generation Timings on DMA2 REQSL2 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA2 Software Request Generation Register 0 1 MJT (output event bus 1) When MJT output event bus 1 signal is generated 1 0 MJT (TIN18S) When MJT TIN18 input signal is generated 1 1 Extended DMA2 transfer request The source selected by the DMA2 Channel Control Register 1 source selected (DM2CNT1) REQESEL2 bits (see below) REQESEL2 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 One DMA1 transfer completed When one DMA1 transfer is completed (cascade mode)

0001 Settings inhibited –

0010 CAN(CAN0_S1/S30) When CAN0 slot 1 transmission failed or slot 30 transmission/reception

1101 Settings inhibited –

1110 DRI (DIN2) When DRI DIN2 event detection interrupt is generated

1111 SIO5_TXD (transmit buffer empty) When SIO5 transmit buffer empty interrupt is generated

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 9.3.4 DMA Transfer Request Sources and Generation Timings on DMA3 REQSL3 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA3 Software Request Generation Register 0 1 SIO0_TXD (transmit buffer empty) When SIO0 transmit buffer is empty 1 0 SIO1_RXD (reception completed) When SIO1 reception is completed 1 1 Extended DMA3 transfer request The source selected by the DMA3 Channel Control Register 1 source selected (DM3CNT1) REQESEL3 bits (see below) REQESEL3 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 MJT (TIN0S) When MJT TIN0 input signal is generated

0001 One DMA2 transfer completed When one DMA2 transfer is completed (cascade mode)

0010 Settings inhibited –

1101 MJT (TOU1_6irq) When MJT TOU1_6 interrupt request is generated

1110 DRI (DIN3) When DRI DIN3 event detection interrupt is generated

1111 SIO5_RXD (reception completed) When SIO5 reception-completed interrupt is generated

Table 9.3.5 DMA Transfer Request Sources and Generation Timings on DMA4 REQSL4 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA4 Software Request Generation Register 0 1 One DMA3 transfer completed When one DMA3 transfer is completed (cascade mode) 1 0 SIO0_RXD (reception completed) When SIO0 reception is completed 1 1 Extended DMA4 transfer request The source selected by the DMA4 Channel Control Register 1 source selected (DM4CNT1) REQESEL4 bits (see below) REQESEL4 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 MJT (TIN19S) When MJT TIN19 input signal is generated

0001 SIO0_TXD (transmit buffer empty) When SIO0 transmit buffer is empty

0010 MJT (TOU1_7irq) MJT TOU1_7 interrupt source

1101 MJT (TIN7S) When MJT TIN7 input signal is generated

1110 DRI (DIN4) When DRI DIN4 event detection interrupt is generated

1111 Settings inhibited –

9-4132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5 REQSL5 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start or one DMA7 When any data is written to the DMA5 Software Request Generation Register transfer completed or when one DMA7 transfer is completed (cascade mode) 0 1 All DMA0 transfers completed When all DMA0 transfers are completed (cascade mode) 1 0 SIO2_RXD (reception completed) When SIO2 reception is completed 1 1 Extended DMA5 transfer request The source selected by the DMA5 Channel Control Register 1 source selected (DM5CNT1) REQESEL5 bits (see below) REQESEL5 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 MJT (TIN20S) When MJT TIN20 input signal is generated

0001 MJT (TOU0_0irq) MJT TOU0_0 interrupt source

1101 MJT (TIN8S) When MJT TIN8 input signal is generated

1110 DRI (DEC0_udf) When DRI DEC0 underflow occurs

1111 CAN1_S0/S31 When CAN1 slot 0 transmission failed or slot 31 transmission/reception

Table 9.3.7 DMA Transfer Request Sources and Generation Timings on DMA6 REQSL6 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA6 Software Request Generation Register 0 1 SIO1_TXD (transmit buffer empty) When SIO1 transmit buffer is empty 1 0 CAN0_S0/S31 When CAN0 slot 0 transmission failed or slot 31 transmission/reception finished 1 1 Extended DMA6 transfer request The source selected by the DMA6 Channel Control Register 1 source selected (DM6CNT1) REQESEL6 bits (see below) REQESEL6 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 One DMA5 transfer completed When one DMA5 transfer is completed (cascade mode)

0001 MJT (TOU0_1irq) MJT TOU0_1 interrupt source

0010 SIO1_RXD (reception completed) When SIO1 reception is completed

1101 DRI address counter 0 transfer completed When DRI address counter 0 transfer completed

1110 DRI (DEC1_udf) When DRI DEC1 underflow occurs

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 9.3.8 DMA Transfer Request Sources and Generation Timings on DMA7 REQSL7 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA7 Software Request Generation Register 0 1 SIO2_TXD (transmit buffer empty) When SIO2 transmit buffer is empty 1 0 CAN0_S1/S30 When CAN0 slot 1 transmission failed or slot 30 transmission/reception finished 1 1 Extended DMA7 transfer request The source selected by the DMA7 Channel Control Register 1 source selected (DM7CNT1) REQESEL7 bits (see below) REQESEL7 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 One DMA6 transfer completed When one DMA6 transfer is completed (cascade mode)

0001 MJT (TOU0_2irq) MJT TOU0_2 interrupt source

0010 SIO3_TXD (transmit buffer empty) When SIO3 transmit buffer is empty

1101 DRI address counter 1 transfer completed When DRI address counter 1 transfer completed

1110 DRI (DEC2_udf) When DRI DEC2 underflow occurs

1111 CAN1_S1/S30 When CAN1 slot 1 transmission failed or slot 30 transmission/reception

Table 9.3.9 DMA Transfer Request Sources and Generation Timings on DMA8 REQSL8 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA8 Software Request Generation Register 0 1 MJT (input event bus 0) When MJT input event bus 0 signal is generated 1 0 SIO3_RXD (reception completed) When SIO3 reception is completed 1 1 Extended DMA8 transfer request The source selected by the DMA8 Channel Control Register 1 source selected (DM8CNT1) REQESEL8 bits (see below) REQESEL8 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 CAN1_S0/S31 When CAN1 slot 0 transmission failed or slot 31 transmission/reception

0001 MJT (TOU0_6irq) MJT TOU0_6 interrupt source

0010 One DMA7 transfer completed When one DMA7 transfer is completed (cascade mode)

1101 DRI latch event counter_udf When DRI latch event counter underflow occurs

1110 DRI (DEC3_udf) When DRI DEC3 underflow occurs

9-4332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 9.3.10 DMA Transfer Request Sources and Generation Timings on DMA9 REQSL9 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA9 Software Request Generation Register 0 1 SIO3_TXD (transmit buffer empty) When SIO3 transmit buffer is empty 1 0 CAN1_S1/S30 When CAN1 slot 1 transmission failed or slot 30 transmission/reception finished 1 1 Extended DMA9 transfer request The source selected by the DMA9 Channel Control Register 1 source selected (DM9CNT1) REQESEL9 bits (see below) REQESEL9 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 One DMA8 transfer completed When one DMA8 transfer is completed (cascade mode)

0001 MJT (TOU0_7irq) MJT TOU0_7 interrupt source

1101 DRI transfer counter_udf When DRI transfer counter underflow occurs

1110 DRI (DEC4_udf) When DRI DEC4 underflow occurs

1111 DRI (DIN5) When DRI DIN5 event detection interrupt is generated

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA transfer starts as requested by internal peripheral I/O DMA transfer processing starts Transfer count register underflows Interrupt request generated Set DMA0 Channel Control Register 0 Set DMA0-4 Interrupt Request Status Register Set DMA0 Channel Control Registers 0, 1 and 2 Set DMA0 Source Address Register Set DMA0 Destination Address Register Set DMA0 Count Register Setting DMAC-related registers Starting DMA transfer DMA transfer completed

• Transfers disabled  Interrupt request status bits cleared Set DMA0-4 Interrupt Request Mask Register  Source address of transfer  Destination address of transfer  Number of times DMA transfer is performed  Transfer mode, request source, transfer size, address direction, bank and transfer enable DMA operation completed  Interrupt request enabled Set the interrupt controller's DMA0-4 Interrupt Control Register  Interrupt priority level Setting interrupt controller-related registers Figure 9.3.1 Example of a DMA Transfer Processing Procedure

9.3.2 DMA Transfer Processing Procedure

Shown below is an example of how to control DMA transfer in cases when performing transfer on DMA channel 0.

9-4532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 9.3.2 Gaining and Releasing Control of the Internal Bus One DMA transfer DMAC CPU Internal bus arbitration (requests from the DMAC) Internal bus R: Read W: Write RW RW RW Requested Gained Requested Gained Requested Gained One DMA transfer One DMA transfer Released Released Released

9.3.3 Starting DMA

Use the DMAn Channel Control Register 0 REQSL (DMA transfer request source select) and DMAn Channel Control Register 1 REQESEL (extended DMA transfer request source select) bits to set the cause or source of DMA transfer request. To enable DMA, set the TENL (DMA transfer enable) bit to "1." DMA transfer begins when the specified cause or source of DMA transfer request becomes effective after setting the TENL (DMA transfer enable) bit to "1." Note: • If the transfer request source selected by the REQSL (DMA transfer request source select) and REQESEL (extended DMA transfer request source select) bits is MJT (TIN input signal), the time required for DMA transfer to begin after detecting the rising or falling or both edges of the TIN input signal is three cycles (75 ns when the internal peripheral clock = 40 MHz) at the shortest. Or, depending on the preceding or following bus usage condition, up to five cycles (125 ns when the internal peripheral clock = 40 MHz) may be required. (However, this applies when the external bus, HOLD and the LOCK instruction all are unused.) To ensure that changes of the TIN input signal state will be detected correctly, make sure the TIN input signal is held active for a duration of more than 7tc (BCLK)/2. (For details, see Section 23.9, “AC Characteristics (when VCCE = 5 V),” and Section 23.10, “AC Characteristics (when VCCE = 3.3 V).”)

9.3.4 DMA Channel Priority

DMA0 has the highest priority. The priority of this and other channels is shown below. DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9 This order of priority is fixed and cannot be changed. Among channels on which DMA transfer is requested, the channel that has the highest priority is selected.

9.3.5 Gaining and Releasing Control of the Internal Bus

For any channel, control of the internal bus is gained and released in “single transfer DMA” mode. In single transfer DMA, the DMAC gains control of the internal bus (in one peripheral clock cycle) when DMA transfer request is accepted and after executing one DMA transfer (in one read and one write peripheral clock cycle), returns bus control to the CPU. The diagram below shows the operation in single transfer DMA.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

9.3.6 Transfer Units

Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one DMA transfer.

9.3.7 Transfer Counts

Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be performed up to 65,536 times. The value of the DMA Transfer Count Register is decremented by one every time one transfer unit is transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-run mode, with the value set in it ignored.

9.3.8 Address Space

The address space in which data can be transferred by DMA is 64 Kbytes × 3 banks of SFR area or internal RAM area (32192 : H’0080 0000 to H’0082 FFFF, 32195 : H’0080 0000 to H’0080 BFFF, 32196 : H’0080 0000 to H’0081 3FFF) for both source and destination. To set the source and destination addresses on each DMA channel, use the DMA Source Address Register and DMA Destination Address Register. Note that no transfer over the bank is carried out. Upon completion of bank transfer to the final address, the bank is to be transferred to the head address.

9.3.9 Transfer Operation

(1) Dual-address transfer Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and the other for destination write access. (The transfer data is taken into the DMAC’s internal temporary regis- ter before being transferred.) (2) Bus protocol and bus timing Because the bus interface is shared with the CPU, DMA transfer is performed with the same bus protocol and the same bus timing as when peripheral modules are accessed by the CPU. (3) Transfer rate Transfer is performed using a total of three peripheral clock cycles, one cycle to gain control of the bus and one read and one write cycles to perform one transfer. Therefore, the maximum transfer rate is calculated by the equation below: Maximum transfer rate [bytes per second] = 2 bytes × 1 1/f(BCLK) × 3 cycles (4) Address count direction and address changes The direction in which the source and destination addresses are counted as transfer proceeds (“Address fixed” or “Address incremental”) is set for each channel using the SADSL (source address direction select) and DADSL (destination address direction select) bits. When the transfer size is 16 bits, the address is incremented by two for each DMA transfer performed; when the transfer size is 8 bits, the address is incremented by one. Table 9.3.11 Address Count Direction and Address Changes Address Count Direction Transfer Unit Address Change for One DMA Address fixed 8 bits 0 16 bits 0 Address incremental8 bits 8 bits +1 16 bits +2

9-4732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 9.3.3 Transfer Byte Positions (7) Ring buffer mode In the ring buffer mode, the number of DMA transfers to each channel can be selected from among 32, 16, 8, 4 and 2 times, and after transfer from the transfer start address, the bit returns to the transfer start address again: thus, the same operation is repeated by the selected frequency. Note: • The transfer start address must be as follows: Transfer Size: 8 bits Transfer Size: 16 bits 32-time ring buffer mode Low order 5 bits – B’00000 Low order 6 bits – B’000000 16-time ring buffer mode Low order 4 bits – B’0000 Low order 5 bits – B’00000 8-time ring buffer mode Low order 3 bits – B’000 Low order 4 bits – B’0000 4-time ring buffer mode Low order 2 bits – B’00 Low order 3 bits – B’000 2-time ring buffer mode Low order 1 bits – B’0 Low order 2 bits – B’00 The address increment operation in the ring buffer mode is as follows. [1] When the transfer size is 8 bits The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented by one at a time. When as transfer proceeds the five low-order bits reach B’11111, they are recycled to B’00000 by the next increment operation, thus returning to the start address again. [2] When the transfer size is 16 bits The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented by two at a time. When as transfer proceeds the six low-order bits reach B’111110, they are recycled to B’000000 by the next increment operation, thus returning to the start address again. (5) Transfer count value The transfer count value is decremented one at a time, irrespective of the size of transfer unit (8 or 16 bits). (6) Transfer byte positions When the transfer unit is 8 bits, the LSB of the address register is effective for both source and destination. (Therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address or vice versa.) When the transfer unit is 16 bits, the LSB of the address register (= bit 15) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus. The diagram below shows the valid byte positions in DMA transfer. b0 b7 b8 b15 8 bits +0 +1 Source Destination <When transfer size = 8 bits> 8 bits 8 bits 8 bits 16 bits 16 bits b0 b7 b8 b15 +0 +1 <When transfer size = 16 bits>

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 9.3.4 Example of How Addresses Are Incremented in 32-channel Ring Buffer Mode

9.3.10 End of DMA and Interrupt

In normal mode, DMA transfer is terminated by an underflow of the transfer count register. When transfer finishes, the transfer enable bit is cleared to "0" and transfers are thereby disabled. Also, an interrupt request is generated at completion of transfer. However, if interrupt requests on any channel have been masked by the DMA Interrupt Request Mask Register, no interrupt requests are generated on that channel. During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the transfer enable bit is cleared to "0" (to disable transfer). In this case, therefore, no interrupt requests are generated at completion of DMA transfer. Nor are these DMA transfer-completed interrupt requests generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit.

9.3.11 Each Register Status after Completion of DMA Transfer

When DMA transfer is completed, the status of the source and destination address registers becomes as follows: (1) Address fixed

• The values set in the address registers before DMA transfer started remain intact (fixed). (2) Address incremental
• For 8-bit transfer, the values of the address registers are the last transfer address + 1.
• For 16-bit transfer, the values of the address registers are the last transfer address + 2. The transfer count register at completion of DMA transfer is in an underflow state (H’FFFF). Therefore, before another DMA transfer can be performed, the transfer count register must be set newly again, except when trying to perform transfers 65,536 times (H’FFFF). <When transfer size = 8 bits> Transfer count Transfer address

1 H'0080 1000

2 H'0080 1001

3 H'0080 1002

31 H'0080 101E

32 H'0080 101F

↓ ↓ ↓ ↓ <When transfer size = 16 bits> Transfer count Transfer address

2 H'0080 1002

3 H'0080 1004

31 H'0080 103C

32 H'0080 103E

| | | | | | | | If the source address has been set to be incremented, it is the source address that recycles to the start address; if the destination address has been set to be incremented, it is the destination address that re- cycles to the start address. If both source and destination addresses have been set to be incremented, both addresses recycle to the start address. However, the start address on either side must have their five low- order bits initially set to B’00000 (if transfer size = 16 bits, the six low-order bits must be B’000000). During ring buffer mode, the transfer count register is ignored. Once DMA operation starts, the counter operates in free-run mode, and the transfer continues until the transfer enable bit is cleared to "0" (to disable transfer).

9-4932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

• About writing to the DMAC related registers Because DMA transfer involves exchanging data via the internal bus, the DMAC related registers basically can only be accessed for write upon exiting the reset state or when transfer is disabled (transfer enable bit = "0"). When transfer is enabled, do not write to the DMAC related registers, except the DMA transfer enable bit, the transfer request flag, DMA interrupt related register and the DMA Transfer Count Register that is protected in hardware. This is a precaution necessary to ensure stable DMA operation. The table below lists the registers that can or cannot be accessed for write. Table 9.4.1 DMAC Related Registers That Can or Cannot Be Accessed for Write Status Transfer enable bit Transfer request flag DMA interrupt related register Other DMAC related registers Transfer enabled Can be accessed Can be accessed Can be accessed Cannot be accessed Transfer disabled Can be accessed Can be accessed Can be accessed Can be accessed Even for registers that can exceptionally be written to while transfer is enabled, the following conditions must be observed: (1) DMA Channel Control Register 0 transfer enable bit and transfer request flag For all bits other than transfer enable bit and transfer request flag in this register, be sure to write the same data that those bits had before the write. Note, however, that only writing "0" is effective for the transfer request flag. (2) DMA Transfer Count Register When transfer is enabled, this register is protected in hardware, so that any data rewritten to it is ignored. (3) Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer Although this operation means accessing the DMAC related registers while DMA is enabled, there is no problem. Note, however, that no data can be transferred by DMA to the DMAC related registers on the currently active channel itself.
• Manipulating the DMAC related registers by DMA transfer When manipulating the DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related registers with the initial values by DMA transfer), do not write to the DMAC related registers on the currently active channel through that channel. (If this precaution is neglected, device operation cannot be guaranteed.) It is only the DMAC related registers on other channels that can be rewritten by means of DMA transfer. (For example, the DMAn Source Address and DMAn Destination Address Registers on channel 1 can be rewritten by DMA transfer through channel 0.)
• About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register, be sure to write "1" to all bits, except those to be cleared. Writing "1" to any bits in this register has no effect, so that they retain the data they had before the write.
• About the stable operation of DMA transfer To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except transfer enable bits of the DMA channel control register 0, unless transfer is disabled. One exception is that even when transfer is enabled, the DMA Source Address and DMA Destination Address Registers can be rewritten by DMA transfer from one channel to another.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 This page is blank for reasons of layout.

10.1 Outline of Multijunction Timers

10.2 Common Units of Multijunction Timers

10.3 TOP (Output-Related 16-Bit Timer)

10.4 TIO (Input/Output-Related 16-Bit Timer)

10.5 TMS (Input-Related 16-Bit Timer)

10.6 TML (Input-Related 32-Bit Timer)

10.7 TID (Input-Related 16-Bit Timer)

10.8 TOU (Output-Related 24-Bit Timer)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to being used as a single unit, the timers can be internally connected to each other. This capability allows for highly flexible timer configuration, making it possible to meet various application needs. It is because the timers are connected to the internal event buses at multiple points that they are called the “multijunction” timers. The 32192/32195/32196 has six types of MJT as listed in the table below, providing a total of 55-channel timers. Table 10.1.1 Outline of MJT Name Type No. of Channels Description TOP Output-related 11 One of three output modes can be selected by software. (Timer 16-bit timer <With correction function> Output) (down-counter) • Single-shot output mode

• Delayed single-shot output mode <Without correction function>
• Continuous output mode TIO Input/output-related 10 One of three input modes or four output modes can be selected (Timer 16-bit timer by software. Input (down-counter) <Input modes> Output) • Measure clear input mode
• Measure free-run input mode
• Noise processing input mode <Output modes without correction function>
• PWM output mode
• Single-shot output mode
• Delayed single-shot output mode
• Continuous output mode TMS Input-related 8 16-bit input measure timer (Timer 16-bit timer Measure (up-counter) Small) TML Input-related 8 32-bit input measure timer (Timer 32-bit timer Measure (up-counter) Large) TID Input-related 2 One of four input modes can be selected by software. (Timer 16-bit timer • Fixed period mode Input (up/down-counter)) • Event count mode Derivation) • Multiply-by-4 event count mode
• Up/down event count mode TOU Output-related 16 One of five output modes can be selected by software. (Timer 24-bit timer <Without correction function> Output (down-counter) • PWM output mode Unification) (16-bit timer during • Single-shot PWM output mode PWM output and • Delayed single-shot output mode single-shot PWM • Single-shot output mode output modes) • Continuous output mode

10-332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 10.1.2 Interrupt Generation Functions of MJT Signal Name MJT Interrupt Request Source Source of Interrupt No. of ICU Input Sources IRQ0 TIO0–3 output MJT output interrupt 0 4 IRQ1 TOP6, TOP7 output MJT output interrupt 1 2 IRQ2 TOP0–5 output MJT output interrupt 2 6 IRQ3 TIO8, TIO9 output MJT output interrupt 3 2 IRQ4 TIO4–7 output MJT output interrupt 4 4 IRQ5 TOP10 output MJT output interrupt 5 1 IRQ6 TOP8, TOP9 output MJT output interrupt 6 2 IRQ7 TMS0, TMS1 output MJT output interrupt 7 2 IRQ8 TIN7–TIN11 input MJT input interrupt 0 5 IRQ9 TIN0 input MJT input interrupt 1 1 IRQ10 TIN16–TIN19 input MJT input interrupt 2 4 IRQ11 TIN20–TIN27 input MJT input interrupt 3 8 IRQ12 TIN3–TIN6 input MJT input interrupt 4 4 IRQ13 TOU0_0–TOU0_7 output TOU0 output interrupt 8 IRQ14 TID0 output TID0 output interrupt 1 IRQ15 TID1 output TID1 output interrupt 1 IRQ16 TOU1_0–TOU1_7 output TOU1 output interrupt 8 IRQ18 TIN30–TIN33 input TML1 input interrupt 4 Table 10.1.3 DMA Transfer Request Generation by MJT Corresponding DMAC Channel No. DMA Transfer Request Source DMA0 TIO8_udf Input event bus 2 TID0_udf/ovf TOU1_0irq Common transfer request source (see Table 10.1.4) DMA1 Output event bus 0 TIN3 input signal TID1_udf/ovf TOU1_1irq Common transfer request source (see Table 10.1.4) DMA2 Output event bus 1 TIN18 input signal Common transfer request source (see Table 10.1.4) DMA3 TIN0 input signal TOU1_6irq Common transfer request source (see Table 10.1.4) DMA4 TIN19 input signal TOU1_7irq TIN7 input signal Common transfer request source (see Table 10.1.4)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 DMA5 TIN20 input signal TOU0_0irq TIN8 input signal Common transfer request source (see Table 10.1.4) DMA6 TOU0_1irq Common transfer request source (see Table 10.1.4) DMA7 TOU0_2irq Common transfer request source (see Table 10.1.4) DMA8 Input event bus 0 TOU0_6irq Common transfer request source (see Table 10.1.4) DMA9 TOU0_7irq Common transfer request source (see Table 10.1.4) Table 10.1.4 DMA Transfer Request Generation by MJT (Common) Corresponding DMAC Channel No. DMA Transfer Request Source DMAn Input event bus 1 Input event bus 3 Output event bus 2 Output event bus 3 TIN0 input signal TIN30 input signal TIO8_udf TIO9_udf Table 10.1.5 A/D Conversion Start Request by MJT Signal Name A/D Conversion Start Request Source A/D Converter AD0TRG Input event bus 2, input event bus 3, Can be input to A/D0 conversion start trigger output event bus 3, TIN23

10-532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.1.1 Block Diagram of MJT (1/4) TCLK0 (P124) TIN0 (P150) TIN3 (P153) TIN4 (P30) TIN5 (P31) TIN6 (P32) TCLK1 (P125) TIN7 (P33) TCLK2 (P126) TIN8 (P44) TIN9 (P45) TIN10 (P46) TIN11 (P47) TO0 (P110) TO1 (P111) TO2 (P112) TO3 (P113) TO4 (P114) TO5 (P115) TO6 (P116) TO7 (P117) TO8 (P100) TO9 (P101) TO10 (P102) TO11 (P103) TO12 (P104) TO13 (P105) TO14 (P106) TO15 (P107) TO16 (P93) TO17 (P94) TO18 (P95) TO19 (P96) TO20 (P97) IRQ9 IRQ12 DMA1 IRQ12 IRQ12 IRQ12 IRQ8 DMA4 IRQ8 DMA5 IRQ8 IRQ8 IRQ8 IRQ2 IRQ2 IRQ2 IRQ2 IRQ2 IRQ2 IRQ1 IRQ1 IRQ6 IRQ6 IRQ5 IRQ0 IRQ0 IRQ0 IRQ0 IRQ4 IRQ4 IRQ4 IRQ4 DMA0 DMA common IRQ3 : Prescalers : Output flip-flop : Selector Notes: • IRQ0-18 denotes interrupt signals, of which the same number represents the same group of interrupts.  DMA0-9 and DMA common denote DMA request signals to the DMAC.  AD0TRG denotes trigger signal to the A/D0 converter. SF/FPRS0-4 DMA common DMA3,DMA commom IRQ3 BCLK TOP 0clk en udf TOP 1clk en udf TOP 2clk en udf TOP 3clk en udf TOP 4clk en udf TOP 5clk en udf TOP 6clk en udf TOP 7clk en udf TOP 8clk en udf TOP 9clk en udf TOP 10clk en udf TIO 0clk en/cap udf TIO 1clk en/cap udf TIO 2clk en/cap udf TIO 3clk en/cap udf TIO 4clk en/cap udf TIO 5clk en/cap udf TIO 6clk en/cap udf TIO 7clk en/cap udf TIO 8clk en/cap udf TIO 9clk en/cap udf S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S TIN0S TCLK0S F/F10 F/F11 F/F12 F/F13 F/F14 F/F15 F/F16 F/F17 F/F18 F/F19 F/F20 F/F0 F/F1 F/F2 F/F3 F/F4 F/F5 F/F6 F/F7 F/F8 F/F9 TIN3S TIN4S TIN5S TIN6S S S S PRS0 PRS1 PRS2 TCLK1S TIN7S TCLK2S TIN8S TIN9S TIN10S TIN11S S S S 3210 3210 0123 3210 3210 0123 Clock bus Input event bus Output event bus

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TCLK3 (P127) TIN16/PWMOFF0 (P130) TIN17/PWMOFF1 (P131) TIN18 (P132) TIN19 (P133) TIN20 (P134) TIN21 (P135) TIN22 (P136) TIN23 (P137) TIN30 (P34) TIN31 (P35) TIN32 (P36) TIN33 (P37) IRQ10 IRQ10 IRQ10 DMA2 IRQ10 DMA4 IRQ11 DMA5 IRQ11 IRQ11 IRQ11 (To A/D0 converter) AD0TRG IRQ18 IRQ18 IRQ18 IRQ18 AD0TRG (to A/D0 converter) AD0TRG (to A/D0 converter) AD0TRG (to A/D0 converter) IRQ7 IRQ7 DMA common TMS 0clk cap3 cap2 cap1 cap0 ovfSTCLK3S S S S S TMS 1clk cap3 cap2 cap1 cap0 ovf TIN16S TIN17S TIN18S TIN19S S S S S S TML 0 (32-bit)clk cap3 cap2 cap1 cap0 TIN20S TIN21S TIN22S TIN23S S S S S S TML 1 (32-bit)clk cap3 cap2 cap1 cap0 TIN30S TIN31S TIN32S TIN33S S S S S S 3210 3210 0123 3210 3210 0123 Clock bus Input event bus Output event bus BCLK Figure 10.1.2 Block Diagram of MJT (2/4)

10-732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIN16/PWMOFF0 (P130) TIN24 (P103) TIN25 (P104) TIN17/PWMOFF1 (P131) TIN26 (P73) TIN27 (P72) TO21 (P00/P87) TO22 (P01/P86) TO23 (P02/P85) TO24 (P03/P84) TO25 (P04/P83) TO26 (P05/P82) TO27 (P06/P175) TO28 (P07/P174) TO29 (P10/P110) TO30 (P11/P111) TO31 (P12/P112) TO32 (P13/P113) TO33 (P14/P114) TO34 (P15/P115) TO35 (P16/P116) TO36 (P17/P117) IRQ11 IRQ11 IRQ11 IRQ11 DMA5 DMA6 DMA7 DMA8 DMA9 DMA0 DMA4 DMA1 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ14 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ15 BCLK DMA0 DMA1 DMA3 TOU0_0 (24-bit)clk en udf TOU0_1 (24-bit)clk en udf TOU0_2 (24-bit)clk en udf TOU0_3 (24-bit)clk en udf TOU0_4 (24-bit)clk en udf TOU0_5 (24-bit)clk en udf TOU0_6 (24-bit)clk en udf TOU0_7 (24-bit)clk en udf TID 0clk CLK1 CLK2 ovf udf TOU1_0 (24-bit)clk en udf TOU1_1 (24-bit)clk en udf TOU1_2 (24-bit)clk en udf TOU1_3 (24-bit)clk en udf TOU1_4 (24-bit)clk en udf TOU1_5 (24-bit)clk en udf TOU1_6 (24-bit)clk en udf TOU1_7 (24-bit)clk en udf TID 1clk CLK1 CLK2 ovf udf TIN25S PWMOFF1S PWMOFF0S PO1DIS PO0DIS TIN24S PRS3 F/F29 F/F30 F/F31 F/F32 F/F33 F/F34 F/F35 F/F36 F/F21 F/F22 F/F23 F/F24 F/F25 F/F26 F/F27 F/F28S TIN27S TIN26S PRS4 S S S Output event bus BCLK Figure 10.1.3 Block Diagram of MJT (3/4)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.1.4 Block Diagram of MJT (4/4) S S S S S S S S S S S DMA0 udf end DMA1 udf end DMA2 udf end DMA3 udf end DMA4 udf end DMA5 udf end DMA6 udf end DMA7 udf end DMA8 udf end DMA9 udf end S S S S S S S S S (Note 1) TIN3S TID1_udf/ovf TOU1_1irq (Note 2) DRI(DIN1) SIO4_RXD TID0_udf/ovf (Note 2) CAN0_S0/S31 TOU1_0irq (Note 2) DRI(DIN0) (Note 2) SIO4_TXD (Note 2) A/D0 conversion completed (Note 1) TIN0S TIO8_udf TIN30S TIO9_udf (Note 2) A/D0 conversion completed TIO8_udf Software start Software start Software start (Note 1) TIN18S Software start (Note 2) SIO0_TXD (Note 2) SIO1_RXD Software start (Note 2) SIO0_RXD Software start DMA0-4 interrupts DMA5-9 interrupts (Note 2) SIO2_RXD Software start (Note 2) SIO1_TXD (Note 2) CAN0_S0/S31 Software start (Note 2) SIO2_TXD (Note 2) CAN0_S1/S30 Software start (Note 2) SIO3_RXD (Note 2) CAN0_S1/S30 (Note 2) DRI(DIN2) SIO5_TXD (Note 1) TIN0S TOU1_6irq (Note 2) DRI(DIN3) SIO5_RXD (Note 1) TIN19S (Note 2) SIO0_TXD TOU1_7irq (Note 1) TIN7S (Note 2) DRI(DIN4) (Note 1) TIN20S TOU0_0irq (Note 1) TIN8S (Note 2) DRI(DEC0_udf) (Note 2) CAN1_S0/S31 TOU0_1irq (Note 2) SIO1_RXD (Note 2) DRI Address counter 0 transfer completed (Note 2) DRI(DEC1_udf) TOU0_6irq (Note 2) CAN1_S0/S31 (Note 2) DRI Latch event counter_udf (Note 2) DRI(DEC3_udf) TOU0_7irq (Note 2) DRI Transfer counter_udf (Note 2) DRI(DEC4_udf) (Note 2) DRI(DIN5) TOU0_2irq (Note 2) SIO3_TXD(Note 2) DRI Address counter 1 transfer completed (Note 2) DRI(DEC2_udf) (Note 2) CAN1_S1/S30 Software start (Note 2) SIO3_TXD (Note 2) CAN1_S1/S30 0123 Input event bus Output event bus 3210 3210 0123 Note 1: Indicates edge select input at the timer input pin. Note 2: Indicates an input signal from each peripheral circuit.

10-932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The common units of MJT include the following:

• Prescaler Unit
• Clock Bus and Input/Output Event Bus Control Unit
• Input Processing Control Unit
• Output Flip-flop Control Unit
• Interrupt Control Unit

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.2.1 MJT Common Unit Register Map

The table below shows a common unit register map of MJT. MJT Common Unit Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0200 Common Count Clock Select Register Clock Bus & Input Event Bus Control Register 10-12 (CNTCKSEL) (CKIEBCR) 10-17 H'0080 0202 Prescaler Register 0 Prescaler Register 1 10-13 (PRS0) (PRS1) H'0080 0204 Prescaler Register 2 Output Event Bus Control Register 10-13 (PRS2) (OEBCR) 10-18 (Use inhibited area) H'0080 0210 TCLK Input Processing Control Register 10-21 (TCLKCR) H'0080 0212 TIN Input Processing Control Register 0 10-22 (TINCR0) H'0080 0214 TIN Input Processing Control Register 1 10-23 (TINCR1) H'0080 0216 TIN Input Processing Control Register 2 10-24 (TINCR2) H'0080 0218 TIN Input Processing Control Register 3 10-25 (TINCR3) H'0080 021A TIN Input Processing Control Register 4 10-25 (TINCR4) (Use inhibited area) H'0080 0220 F/F Source Select Register 0 10-28 (FFS0) H'0080 0222 (Use inhibited area) F/F Source Select Register 1 10-29 (FFS1) H'0080 0224 F/F Protect Register 0 10-30 (FFP0) H'0080 0226 F/F Data Register 0 10-32 (FFD0) H'0080 0228 (Use inhibited area) F/F Protect Register 1 10-30 (FFP1) H'0080 022A (Use inhibited area) F/F Data Register 1 10-32 (FFD1) (Use inhibited area) H'0080 0230 TOP Interrupt Control Register 0 TOP Interrupt Control Register 1 10-38 (TOPIR0) (TOPIR1) H'0080 0232 TOP Interrupt Control Register 2 TOP Interrupt Control Register 3 10-40 (TOPIR2) (TOPIR3) 10-41 H'0080 0234 TIO Interrupt Control Register 0 TIO Interrupt Control Register 1 10-42 (TIOIR0) (TIOIR1) 10-43 H'0080 0236 TIO Interrupt Control Register 2 TMS Interrupt Control Register 10-44 (TIOIR2) (TMSIR) 10-45 H'0080 0238 TIN Interrupt Control Register 0 TIN Interrupt Control Register 1 10-46 (TINIR0) (TINIR1) 10-47 H'0080 023A TIN Interrupt Control Register 2 TIN Interrupt Control Register 3 10-48 (TINIR2) (TINIR3) H'0080 023C TIN Interrupt Control Register 4 TIN Interrupt Control Register 5 10-50 (TINIR4) (TINIR5) H'0080 023E TIN Interrupt Control Register 6 TIN Interrupt Control Register 7 10-52 (TINIR6) (TINIR7) 10-55 H'0080 07D0 Prescaler Register 3 10-13 (PRS3) H'0080 07D2 TOU0 Interrupt Request Mask Register TOU0 Interrupt Request Status Register 10-56 (TOU0IMA) (TOU0IST) H'0080 07D4 F/F21-28 Protect Register 10-31 (FF2128P) H'0080 07D6 F/F21-28 Data Register 10-33 (FF2128D)

10-1132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 MJT Common Unit Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 07E0 TIN24,25 Input Processing Control Register 10-26 (TIN2425CR) H'0080 07E2 TIN24,25 Interrupt Request Mask Register TIN24,25 Interrupt Request Status Register 10-52 (TIN2425IMA) (TIN2425IST) H'0080 0BD0 Prescaler Register 4 10-13 (PRS4) H'0080 0BD2 TOU1 Interrupt Request Mask Register TOU1 Interrupt Request Status Register 10-58 (TOU1IMA) (TOU1IST) H'0080 0BD4 F/F29-36 Protect Register 10-31 (FF2936P) H'0080 0BD6 F/F29-36 Data Register 10-33 (FF2936D) H'0080 0BE0 TIN26,27 Input Processing Control Register 10-26 (TIN2627CR) H'0080 0BE2 TIN26,27 Interrupt Request Mask Register TIN26,27 Interrupt Request Status Register 10-53 (TIN2627IMA) (TIN2627IST)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.2.2 Common Count Clock Select Function

Common Count Clock Select Register (CNTCKSEL) <Address: H’0080 0200> <Upon exiting reset: H’00> b Bit Name Function R W

0 PRS012CKS 0: BCLK/4 R W

Prescaler 0-2, TML0,1 supplied clock select bit 1: BCLK/2 1–7 No function assigned. Fix to "0." 00 Note 1: Clock switchover takes effect asynchronously with the count clock. This bit can only be set or reset before the prescal ers 0, 1, 2 and the TML0, 1 counters are set when the TOP/TIO/TMS are inactive. This register is used to select the clock supplied to the prescalers 0–2 and the timers (TML0, 1). (1) PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit (Bit 0) This bit selects the clock supplied to the prescalers 0–2 and the timers TML0 and 1. Setting this bit to "0" selects BCLK/4 (10 MHz when f(CPUCLK) = 160 MHz); setting this bit to "1" selects BCLK/2 (20 MHz when f(CPUCLK) = 160 MHz). Figure 10.2.1 Block Diagram of the Common Count Clock Select Function b 0 123456 b 7 PRS012CKS 00000000 PRS0 PRS1 PRS2 BCLK/2 S TML0 TML1S Clock bus 0 Clock bus 1 Clock bus 2 BCLK 1/2 BCLK/4

10-1332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.2.3 Prescaler Unit

The Prescalers PRS0 to 2 are an 8-bit counter, which generates clocks supplied to each timer (TOP, TIO, TMS, TML) from the internal peripheral clock (BCLK) divided by 2 or 4. The Prescalers PRS3 and 4 are an 8-bit counter, which generates clocks supplied to timerTID and TOU from the internal peripheral clock BCLK or BCLK divided by 4. The values of prescaler registers are initialized to H’00 upon exting the reset state. When the set value of any prescaler register is rewritten, the prescaler starts operating with the new value at the same time it has underflowed. Values H’00 to H’FF can be set in the prescaler register. The prescaler’s divide-by ratio is given by the equation below: Prescaler divide-by ratio = 1 prescaler set value + 1 Prescaler Register 0 (PRS0) <Address: H’0080 0202> Prescaler Register 1 (PRS1) <Address: H’0080 0203> Prescaler Register 2 (PRS2) <Address: H’0080 0204> Prescaler Register 3 (PRS3) <Address: H’0080 07D0> Prescaler Register 4 (PRS4) <Address: H’0080 0BD0> <Upon exiting reset: H’00> b Bit Name Function R W 0–7 PRS0–PRS4 Set the prescaler divide-by value R W (8–15) Prescaler Prescaler Registers 0–2 start counting after exiting the reset state. Prescaler Registers 3, 4 each are activated by setting the TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) or TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) prescaler-n enable (PRSnEN) bit to "1" (count start), upon which the prescaler register value is reloaded and the prescaler starts counting. For details, see Section 10.7, “TID (Input-Related 16-Bit Timer).” If the prescaler register is accessed for read during operation, the value written into it, not the current count, is read out. b 8 9 1 01 11 21 31 4 b 1 5 PRS0-PRS4 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.2.4 Clock Bus and Input/Output Event Bus Control Unit

(1) Clock bus The clock bus is provided for supplying clock to each timer, and is comprised of four lines of clock bus 0–3. Each timer can use these clock bus signals as clock input signals. The table below lists the signals that can be fed into the clock bus. Table 10.2.1 Acceptable Clock Bus Signals Clock Bus Acceptable Signal

3 TCLK0 input

2 Internal prescaler (PRS2) or TCLK3 input

1 Internal prescaler (PRS1)

0 Internal prescaler (PRS0)

(2) Input event bus The input event bus is provided for supplying a count enable signal or measure capture signal to each timer, and is comprised of four lines of input event bus 0–3. Each timer can use these input event bus signals as enable (or capture) input. Furthermore, they can also be used as request signals to start A/D conversion or DMA transfer. The table below lists the signals that can be fed into the input event bus. Table 10.2.2 Connectable (Acceptable) Input Event Bus Signals Input Event Bus Connectable (Acceptable) Signal (Note 1)

3 TIN3 input, output event bus 2 or TIO7 underflow signal

2 TIN0 input or TIN4 input

1 TIO6 underflow signal, TIN5 input

0 TIO5 underflow signal, TIN6 input

Note 1: For the destination (output) to which the input event bus signals are connected, see Figure 10.1.1, “Block Diagram of MJT.” (3) Output event bus The output event bus has the underflow signal from each timer connected to it, and is comprised of four lines of output event bus 0–3. Output event bus signals are connected to output flip-flops, and can also be connected to the A/D converter and DMAC. Furthermore, output event bus 2 can be connected to input event bus 3. The table below lists the signals that can be connected to the output event bus. Table 10.2.3 Connectable (Acceptable) Output Event Bus Signals Output Event Bus Connectable (Acceptable) Signal (Note 1)

3 TOP8, TIO3, TIO4 or TIO8 underflow signal

2 TOP9 or TIO2 underflow signal

1 TOP7 or TIO1 underflow signal

0 TOP6 or TIO0 underflow signal

Note 1: For the destination (output) to which the output event bus signals are connected, see Figure 10.1.1, “Block Diagram of MJT.” Note that the signals from each timer to the output event bus (and TIO5, 6 signals to the input event bus) are generated with the timing shown in Table 10.2.4, and not the timing at which signals are output from the timer to the output flip-flop.

10-1532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 10.2.4 Timing at Which Signals are Generated to the Output Event Bus by Each Timer Timer Mode Timing at which signals are generated to the output event bus TOP Single-shot output mode When the counter underflows Delayed single-shot output mode When the counter underflows Continuous output mode When the counter underflows TIO(Note 1) Measure clear input mode When the counter underflows Measure free-run input mode When the counter underflows Noise processing input mode When the counter underflows PWM output mode When the counter underflows Single-shot output mode When the counter underflows Delayed single-shot output mode When the counter underflows Continuous output mode When the counter underflows TMS (16-bit measure input) No signals generated TML (32-bit measure input) No signals generated TID Fixed period mode No signals generated Event count mode No signals generated Multiply-by-4 event count mode No signals generated Up/down event count mode No signals generated TOU PWM output mode No signals generated Single-shot PWM mode No signals generated Delayed single-shot output mode No signals generated Single-shot output mode No signals generated Continuous output mode No signals generated Note 1: TIO5–7 output an underflow signal to the input event bus.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.2.2 Conceptual Diagram of the Clock Bus and Input/Output Event Bus Clock bus Input event bus TCLK0S 3 2 1 0 TCLK0 (P124) TIN0 (P150) TIN3 (P153) TIN4 (P30) TIN5 (P31) TIN6 (P32) PRS1 PRS0 PRS0–2 : Prescaler 3 2 1 0 3 2 1 0 3 2 1 0 PRS2 TCLK3 (P127) udfTIO 5 udfTIO 6 S Output event bus 0 1 2 3 udfTIO 7 clk en udfTOP 6 clk en udfTOP 7 clk en udfTOP 8 clk en udfTOP 9 udfTIO 0 udfTIO 1 udfTIO 2 udfTIO 3 udfTIO 4 udfTIO 8 0 1 2 3 S : Selector TCLK3S TIN0S TIN3S TIN4S TIN5S TIN6S Note: . This diagram only illustrates the clock bus and input/output event bus, and is partly omitted. BCLK

10-1732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 8 9 1 01 11 21 31 4 b 1 5 IEB3S IEB2S IEB1S IEB0S CKB2S 00000000 The Clock Bus and Input/Output Event Bus Control Unit has the following registers:

• Clock Bus & Input Event Bus Control Register (CKIEBCR)
• Output Event Bus Control Register (OEBCR) Clock Bus & Input Event Bus Control Register (CKIEBCR) <Address: H’0080 0201> <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 IEB3S 00: Select external input 3 (TIN3) R W Input event bus 3 input select bit 01: Select external input 3 (TIN3) 10: Select output event bus 2 11: Select TIO7 output 10, 11 IEB2S 00: Select external input 0 (TIN0) R W Input event bus 2 input select bit 01: Does not use input event bus 2 10: Select external input 4 (TIN4) 11: Select external input 4 (TIN4)

12 IEB1S 0: Select external input 5 (TIN5) R W

Input event bus 1 input select bit 1: Select TIO6 output

13 IEB0S 0: Select external input 6 (TIN6) R W

Input event bus 0 input select bit 1: Select TIO5 output 14 No function assigned. Fix to "0." 00

15 CKB2S 0: Select prescaler 2 R W

Clock bus 2 input select bit 1: Select external clock 3 (TCLK3) The CKIEBCR register is used to select the clock source (external input or prescaler) supplied to the clock bus and the count enable/capture signal (external input or output event bus) supplied to the input event bus.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 8 9 1 01 11 21 31 4 b 1 5 OEB3S OEB2S OEB1S OEB0S 00000000 Output Event Bus Control Register (OEBCR) <Address: H’0080 0205> <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 OEB3S 00: Select TOP8 output R W Output event bus 3 input select bit 01: Select TIO3 output 10: Select TIO4 output 11: Select TIO8 output 10 No function assigned. Fix to "0." 00

11 OEB2S 0: Select TOP9 output R W

Output event bus 2 input select bit 1: Select TIO2 output 12 No function assigned. Fix to "0." 00

13 OEB1S 0: Select TOP7 output R W

Output event bus 1 input select bit 1: Select TIO1 output 14 No function assigned. Fix to "0." 00

15 OEB0S 0: Select TOP6 output R W

Output event bus 0 input select bit 1: Select TIO0 output The OEBCR register is used to select the timer (TOP or TIO) whose underflow signal is supplied to the output event bus.

10.2.5 Input Processing Control Unit

The Input Processing Control Unit processes TCLK and TIN input signals to the MJT. In TCLK input process- ing, it selects the source of TCLK signal, and for external input, it selects the active edge (rising or falling or both) or level ("H" or "L") of the signal, at which to generate the clock signal supplied to the clock bus. In TIN input processing, the unit selects the active edge (rising or falling or both) or level ("H" or "L") of the signal, at which to generate the enable, measure or count source signal for each timer or the signal supplied to each event bus. Following input processing registers are included:

• TLCK Input Processing Control Register (TCLKCR)
• TIN Input Processing Control Register 0 (TINCR0)
• TIN Input Processing Control Register 1 (TINCR1)
• TIN Input Processing Control Register 2 (TINCR2)
• TIN Input Processing Control Register 3 (TINCR3)
• TIN Input Processing Control Register 4 (TINCR4)
• TIN24,25 Input Processing Control Register (TIN2425CR)
• TIN26,27 Input Processing Control Register (TIN2627CR)

10-1932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Count clock Count clock Count clock BCLK/2 or BCLK/4 (Note 1) TCLK TCLK Count clock TCLK TCLK TCLK Count clock BCLK/2 or BCLK/4 (Note 1) Item Function BCLK/2 or BCLK/4 (Note 1) Rising edge Falling edge Both edges "L" level "H" level Note 1: To select BCLK/2 or BCLK/4, use the PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit of the Common Count Clock Select Register (CNTCKSEL). For details, refer to Section 10.2.2, “Common Count Clock Select Function.” Count clock BCLK/2 or BCLK/4 (Note 1) (1) Functions of TCLK Input Processing Control Registers

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) Functions of TIN Input Processing Control Registers Internal edge signal Internal edge signal Internal edge signal TIN TIN Internal edge signal TIN TIN TIN Internal edge signal Item Function Rising edge Falling edge Both edges "L" level "H" level Prescaler output period or TCLK input period Prescaler output period or TCLK input period

10-2132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TCLK Input Processing Control Register (TCLKCR) <Address: H’0080 0210> <Upon exiting reset: H’0000> b Bit Name Function R W 0, 1 No function assigned. Fix to "0." 00 2, 3 TCLK3S 00: BCLK/2 or BCLK/4 (Note 1) R W TCLK3 input processing select bit 01: Rising edge 10: Falling edge 11: Both edges 4 No function assigned. Fix to "0." 00 5–7 TCLK2S 000: Disable input R W TCLK2 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 8 No function assigned. Fix to "0." 00 9–11 TCLK1S 000: Disable input R W TCLK1 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 12,13 No function assigned. Fix to "0." 00 14,15 TCLK0S 00: BCLK/2 or BCLK/4 (Note 1) R W TCLK0 input processing select bit 01: Rising edge 10: Falling edge 11: Both edges110 Note 1: To select BCLK/2 or BCLK/4, use the PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit of the Common Count Clock Select Register (CNTCLKSEL). For details, refer to Section 10.2.2, “Common Count Clock Select Function.” Note: • This register must always be accessed in halfwords. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TCLK3S TCLK2S TCLK1S TCLK0S 0000000000000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIN4S TIN3S TIN2S TIN1S TIN0S 0000000000000000 TIN Input Processing Control Register 0 (TINCR0) <Address: H’0080 0212> <Upon exiting reset: H’0000> b Bit Name Function R W 0 No function assigned. Fix to "0." 00 1–3 TIN4S 000: Disable input R W TIN4 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 4 No function assigned. Fix to "0." 00 5–7 TIN3S 000: Disable input R W TIN3 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 8,9 No function assigned. Fix to "0." 00 10,11 TIN2S Fix to "0" 0 0 Reserved bit 12,13 TIN1S Fix to "0" 0 0 Reserved bit 14,15 TIN0S 00: Disable input R W TIN0 input processing select bit 01: Rising edge 10: Falling edge 11: Both edges Note: • This register must always be accessed in halfwords.

10-2332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIN8S TIN7S TIN6S TIN5S 0000000000000000 TIN Input Processing Control Register 1 (TINCR1) <Address: H’0080 0214> <Upon exiting reset: H’0000> b Bit Name Function R W 0 No function assigned. Fix to "0." 00 1–3 TIN8S 000: Disable input R W TIN8 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 4 No function assigned. Fix to "0." 00 5–7 TIN7S 000: Disable input R W TIN7 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 8 No function assigned. Fix to "0." 00 9–11 TIN6S 000: Disable input R W TIN6 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 12 No function assigned. Fix to "0." 00 13–15 TIN5S 000: Disable input R W TIN5 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level Note: • This register must always be accessed in halfwords.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIN Input Processing Control Register 2 (TINCR2) <Address: H’0080 0216> <Upon exiting reset: H’0000> b Bit Name Function R W 0–4 No function assigned. Fix to "0." 00 5–7 TIN11S 000: Disable input R W TIN11 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 8 No function assigned. Fix to "0." 00 9–11 TIN10S 000: Disable input R W TIN10 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level 12 No function assigned. Fix to "0." 00 13–15 TIN9S 000: Disable input R W TIN9 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: "L" level 101: "L" level 110: "H" level 111: "H" level Note: • This register must always be accessed in halfwords. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIN11S TIN10S TIN9S 0000000000000000

10-2532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIN Input Processing Control Register 3 (TINCR3) <Address: H’0080 0218> <Upon exiting reset: H’0000> b Bit Name Function R W 0, 1 TIN19S (TIN19 input processing select bit) 00: Disable input R W 2, 3 TIN18S (TIN18 input processing select bit) 01: Rising edge 4, 5 TIN17S (TIN17 input processing select bit) 10: Falling edge 6, 7 TIN16S (TIN16 input processing select bit) 11: Both edges 8, 9 TIN15S (Reserved bit) Fix to "0" 0 0 10, 11 TIN14S (Reserved bit) 12, 13 TIN13S (Reserved bit) 14, 15 TIN12S (Reserved bit) Note: • This register must always be accessed in halfwords. TIN Input Processing Control Register 4 (TINCR4) <Address: H’0080 021A> <Upon exiting reset: H’0000> b Bit Name Function R W 0, 1 TIN33S (TIN33 input processing select bit) 00: Disable input R W 2, 3 TIN32S (TIN32 input processing select bit) 01: Rising edge 4, 5 TIN31S (TIN31 input processing select bit) 10: Falling edge 6, 7 TIN30S (TIN30 input processing select bit) 11: Both edges 8, 9 TIN23S (TIN23 input processing select bit) 10, 11 TIN22S (TIN22 input processing select bit) 12, 13 TIN21S (TIN21 input processing select bit) 14, 15 TIN20S (TIN20 input processing select bit) Note: • This register must always be accessed in halfwords. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIN33S TIN32S TIN31S TIN30S TIN29S TIN28S TIN27S TIN26S 0000000000000000 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIN19S TIN18S TIN17S TIN16S TIN15S TIN14S TIN13S TIN12S 0000000000000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 8 9 1 01 11 21 31 4 b 1 5 TIN27S TIN26S 00000000

10.2.6 Output Flip-flop Control Unit

The Output Flip-flop Control Unit controls the flip-flops (F/F) provided for each timer. Following flip-flop control registers are included:

• F/F Source Select Register 0 (FFS0)
• F/F Source Select Register 1 (FFS1)
• F/F Protect Register 0 (FFP0)
• F/F Protect Register 1 (FFP1)
• F/F21–28 Protect Register (FF2128P)
• F/F29–36 Protect Register (FF2936P)
• F/F Data Register 0 (FFD0)
• F/F Data Register 1 (FFD1)
• F/F21–28 Data Register (FF2128D)
• F/F29–36 Data Register (FF2936D) The timing at which signals are generated to the output flip-flop by each timer are shown in Table 10.2.5. (Note that this timing is different from one at which signals are output from the timer to the output event bus.) TIN24,25 Input Processing Control Register (TIN2425CR) <Address: H’0080 07E1> <Upon exiting reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0." 00 12, 13 TIN25S (TIN25 input processing select bit) 00: Disable input RW 14, 15 TIN24S (TIN24 input processing select bit) 01: Rising edge 10: Falling edge 11: Both edges TIN26,27 Input Processing Control Register (TIN2627CR) <Address: H’0080 0BE1> <Upon exiting reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0." 00 12, 13 TIN27S (TIN27 input processing select bit) 00: Disable input RW 14, 15 TIN26S (TIN26 input processing select bit) 01: Rising edge 10: Falling edge 11: Both edges b 8 9 1 01 11 21 31 4 b 1 5 TIN25S TIN24S 00000000

10-2732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Output event bus 0 Data bus F/F protect (FPn) WR Data bus Output control (ON/OFF) TOn Internal edge signal Port operation mode register (PnMOD) F/Fn output data (FDn) TOP/TIO/TOU udf F/F source selection (FSn) Output event bus 1 Output event bus 2 Output event bus 3 F/F F/F F/F Figure 10.2.3 Configuration of the F/F Output Circuit Table 10.2.5 Timing at Which Signals Are Generated to the Output Flip-Flop by Each Timer Timer Mode Timing at which signals are generated to the output flip-flop TOP Single-shot output mode When count is enabled or underflows Delayed single-shot output mode When counter underflows Continuous output mode When count is enabled or underflows TIO Measure clear input mode When counter underflows Measure free-run input mode When counter underflows Noise processing input mode When counter underflows PWM output mode When count is enabled or underflows Single-shot output mode When count is enabled or underflows Delayed single-shot output mode When counter underflows Continuous output mode When count is enabled or underflows TMS (16-bit measure input) No signals generated TML (32-bit measure input) No signals generated TID Fixed period count mode No signals generated Event count mode No signals generated Multiply-by-4 event count mode No signals generated Up/down event count mode No signals generated TOU PWM output mode When count is enabled or underflows Single-shot PWM output mode When counter underflows Delayed single-shot output mode When counter underflows Single-shot output mode When count is enabled or underflows Continuous output mode When count is enabled or underflows

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 0000000000000000 F/F Source Select Register 0 (FFS0) <Address: H’0080 0220> <Upon exiting reset: H’0000> b Bit Name Function R W 0–2 No function assigned. Fix to "0." 00

3 FS15 0: TIO4 output R W

F/F15 source select bit 1: Output event bus 0

4 FS14 0: TIO3 output R W

F/F14 source select bit 1: Output event bus 0

5 FS13 0: TIO2 output R W

F/F13 source select bit 1: Output event bus 3

6 FS12 0: TIO1 output R W

F/F12 source select bit 1: Output event bus 2

7 FS11 0: TIO0 output R W

F/F11 source select bit 1: Output event bus 1 8, 9 FS10 00: TOP10 output R W F/F10 source select bit 01: TOP10 output 10: Output event bus 0 11: Output event bus 1 10, 11 FS9 00: TOP9 output R W F/F9 source select bit 01: TOP9 output 10: Output event bus 0 11: Output event bus 1 12, 13 FS8 00: TOP8 output R W F/F8 source select bit 01: Output event bus 0 10: Output event bus 1 11: Output event bus 2

14 FS7 0: TOP7 output R W

F/F7 source select bit 1: Output event bus 0

15 FS6 0: TOP6 output R W

F/F6 source select bit 1: Output event bus 1 Note: • This register must always be accessed in halfwords.

10-2932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 F/F Source Select Register 1 (FFS1) <Address: H’0080 0223> <Upon exiting reset: H’0000> b Bit Name Function R W 8, 9 FS19 00: TIO8 output R W F/F19 source select bit 01: TIO8 output 10: Output event bus 0 11: Output event bus 1 10, 11 FS18 00: TIO7 output R W F/F18 source select bit 01: TIO7 output 10: Output event bus 0 11: Output event bus 1 12, 13 FS17 00: TIO6 output R W F/F17 source select bit 01: TIO6 output 10: Output event bus 0 11: Output event bus 1 14, 15 FS16 00: TIO5 output R W F/F16 source select bit 01: Output event bus 0 10: Output event bus 1 11: Output event bus 3 These registers select the signal source for each output F/F (flip-flop). This signal source can be chosen to be a signal from the internal output bus or an underflow output from each timer. b 8 9 1 01 11 21 31 4 b 1 5 FS19 FS18 FS17 FS16 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 8 9 1 01 11 21 31 4 b 1 5 FP20 FP19 FP18 FP17 FP16 00000000 F/F Protect Register 0 (FFP0) <Address: H’0080 0224> <Upon exiting reset: H’0000> b Bit Name Function R W

0 FP15 (F/F15 protect bit) 0: Enable write to F/F output bit R W

1 FP14 (F/F14 protect bit) 1: Disable write to F/F output bit

2 FP13 (F/F13 protect bit)

3 FP12 (F/F12 protect bit)

4 FP11 (F/F11 protect bit)

5 FP10 (F/F10 protect bit)

6 FP9 (F/F9 protect bit)

7 FP8 (F/F8 protect bit)

8 FP7 (F/F7 protect bit)

9 FP6 (F/F6 protect bit)

10 FP5 (F/F5 protect bit)

11 FP4 (F/F4 protect bit)

12 FP3 (F/F3 protect bit)

13 FP2 (F/F2 protect bit)

14 FP1 (F/F1 protect bit)

15 FP0 (F/F0 protect bit)

Note: • This register must always be accessed in halfwords. F/F Protect Register 1 (FFP1) <Address: H’0080 0229> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0." 00

11 FP20 (F/F20 protect bit) 0: Enable write to F/F output bit R W

12 FP19 (F/F19 protect bit) 1: Disable write to F/F output bit

13 FP18 (F/F18 protect bit)

14 FP17 (F/F17 protect bit)

15 FP16 (F/F16 protect bit)

b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 0000000000000000

10-3132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 8 9 1 01 11 21 31 4 b 1 5 FP21 FP22 FP23 FP24 FP25 FP26 FP27 FP28 00000000 F/F21–28 Protect Register (FF2128P) <Address: H’0080 07D5> <Upon exiting reset: H’00> b Bit Name Function R W

8 FP21 (F/F21 protect bit) 0: Enable write to F/F output bit R W

9 FP22 (F/F22 protect bit) 1: Disable write to F/F output bit

10 FP23 (F/F23 protect bit)

11 FP24 (F/F24 protect bit)

12 FP25 (F/F25 protect bit)

13 FP26 (F/F26 protect bit)

14 FP27 (F/F27 protect bit)

15 FP28 (F/F28 protect bit)

F/F29–36 Protect Register (FF2936P) <Address: H’0080 0BD5> <Upon exiting reset: H’00> b Bit Name Function R W

8 FP29 (F/F29 protect bit) 0: Enable write to F/F output bit R W

9 FP30 (F/F30 protect bit) 1: Disable write to F/F output bit

10 FP31 (F/F31 protect bit)

11 FP32 (F/F32 protect bit)

12 FP33 (F/F33 protect bit)

13 FP34 (F/F34 protect bit)

14 FP35 (F/F35 protect bit)

15 FP36 (F/F36 protect bit)

These registers control write to each output F/F (flip-flop) by enabling or disabling. If write to any output F/F is disabled, writing to the F/F data register has no effect. b 8 9 1 01 11 21 31 4 b 1 5 FP29 FP30 FP31 FP32 FP33 FP34 FP35 FP36 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 FD15 FD14 FD13 FD12 FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 0000000000000000 F/F Data Register 0 (FFD0) <Address: H’0080 0226> <Upon exiting reset: H’0000> b Bit Name Function R W

0 FD15 (F/F15 output data bit) 0: F/F output data = 0 R W

1 FD14 (F/F14 output data bit) 1: F/F output data = 1

2 FD13 (F/F13 output data bit)

3 FD12 (F/F12 output data bit)

4 FD11 (F/F11 output data bit)

5 FD10 (F/F10 output data bit)

6 FD9 (F/F9 output data bit)

7 FD8 (F/F8 output data bit)

8 FD7 (F/F7 output data bit)

9 FD6 (F/F6 output data bit)

10 FD5 (F/F5 output data bit)

11 FD4 (F/F4 output data bit)

12 FD3 (F/F3 output data bit)

13 FD2 (F/F2 output data bit)

14 FD1 (F/F1 output data bit)

15 FD0 (F/F0 output data bit)

Note: • This register must always be accessed in halfwords. F/F Data Register 1 (FFD1) <Address: H’0080 022B> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0." 00

11 FD20 (F/F20 output data bit) 0: F/F output data = 0 R W

12 FD19 (F/F19 output data bit) 1: F/F output data = 1

13 FD18 (F/F18 output data bit)

14 FD17 (F/F17 output data bit)

15 FD16 (F/F16 output data bit)

b 8 9 1 01 11 21 31 4 b 1 5 FD20 FD19 FD18 FD17 FD16 00000000

10-3332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 F/F21–28 Data Register (FF2128D) <Address: H’0080 07D7> <Upon exiting reset: H’00> b Bit Name Function R W

8 FD21 (F/F21 output data bit) 0: F/F output data = 0 R W

9 FD22 (F/F22 output data bit) 1: F/F output data = 1

10 FD23 (F/F23 output data bit)

11 FD24 (F/F24 output data bit)

12 FD25 (F/F25 output data bit)

13 FD26 (F/F26 output data bit)

14 FD27 (F/F27 output data bit)

15 FD28 (F/F28 output data bit)

F/F29–36 Data Register (FF2936D) <Address: H’0080 0BD7> <Upon exiting reset: H’00> b Bit Name Function R W

8 FD29 (F/F29 output data bit) 0: F/F output data = 0 R W

9 FD30 (F/F30 output data bit) 1: F/F output data = 1

10 FD31 (F/F31 output data bit)

11 FD32 (F/F32 output data bit)

12 FD33 (F/F33 output data bit)

13 FD34 (F/F34 output data bit)

14 FD35 (F/F35 output data bit)

15 FD36 (F/F36 output data bit)

These registers are used to set data in each output F/F (flip-flop). Although F/F output normally changes with timer output, setting data 0 or 1 in this register allows to produce desired output from any F/F. The F/F data register can only be operated on when the F/F protect register described earlier is enabled for write. b 8 9 1 01 11 21 31 4 b 1 5 FD21 FD22 FD23 FD24 FD25 FD26 FD27 FD28 00000000 b 8 9 1 01 11 21 31 4 b 1 5 FD29 FD30 FD31 FD32 FD33 FD34 FD35 FD36 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.2.7 Interrupt Control Unit

The Interrupt Control Unit controls the interrupt request signals output to the Interrupt Controller by each timer. Following timer interrupt control registers are provided for each timer:

• TOP Interrupt Control Register 0 (TOPIR0)
• TOP Interrupt Control Register 1 (TOPIR1)
• TOP Interrupt Control Register 2 (TOPIR2)
• TOP Interrupt Control Register 3 (TOPIR3)
• TIO Interrupt Control Register 0 (TIOIR0)
• TIO Interrupt Control Register 1 (TIOIR1)
• TIO Interrupt Control Register 2 (TIOIR2)
• TMS Interrupt Control Register (TMSIR)
• TIN Interrupt Control Register 0 (TINIR0)
• TIN Interrupt Control Register 1 (TINIR1)
• TIN Interrupt Control Register 2 (TINIR2)
• TIN Interrupt Control Register 3 (TINIR3)
• TIN Interrupt Control Register 4 (TINIR4)
• TIN Interrupt Control Register 5 (TINIR5)
• TIN Interrupt Control Register 6 (TINIR6)
• TIN24,25 Interrupt Request Mask Register (TIN2425IMA)
• TIN24,25 Interrupt Request Status Register (TIN2425IST)
• TIN26,27 Interrupt Request Mask Register (TIN2627IMA)
• TIN26,27 Interrupt Request Status Register (TIN2627IST)
• TIN Interrupt Control Register 7 (TINIR7)
• TOU0 Interrupt Request Mask Register (TOU0IMA)
• TOU0 Interrupt Request Status Register (TOU0IST)
• TOU1 Interrupt Request Mask Register (TOU1IMA)
• TOU1 Interrupt Request Status Register (TOU1IST) For interrupts which have only one interrupt request source in the interrupt vector table, no interrupt control registers are included in the timer, and the interrupt request status flags are automatically managed within the Interrupt Controller. For details, see Chapter 5, “Interrupt Controller.”
• TOP10 TOP10 Output Interrupt Request (IRQ5)
• TID0 TID0 Output Interrupt Request (IRQ14)
• TID1 TID1 Output Interrupt Request (IRQ15)

10-3532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 To the Interrupt Controller Timer or TIN input interrupt request Interrupt request status Data bus Set Group interrupt Interrupt request enabled clear F/F F/F Data = 0 Figure 10.2.4 Interrupt Request Status and Mask Registers For interrupts which have two or more interrupt sources in the interrupt vector table, interrupt control registers are included, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in the Interrupt Controller only serve as a bit to determine interrupt requests from interrupt-enabled sources and cannot be accessed for write. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0." Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt request mask bit, it can be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the interrupt request status grouped as a group interrupt, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupts within the interrupt request grouped as a group interrupt. Set this bit to "0" to enable interrupt requests or "1" to disable interrupt requests.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b4 5 b7 Interrupt request status Initial state Event occurs on bit 6 Interrupt request Event occurs on bit 4 Only bit 6 cleared Bit 4 data retained b4 5 b7 1 1 0 1 Write to the interrupt request status Example for clearing interrupt request status 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 Program example ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */  To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. b4 5 6 b7 Interrupt request status Event occurs on bit 6 Event occurs on bit 4 Only bit 6 cleared Bit 4 also cleared 0 0 1 0 1 0 1 0 0 0 0 0 Read 0 0 1 0 0 0 0 0 Clear bit 6 (ANDing with 1101) Write ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */ Figure 10.2.5 Example for Clearing Interrupt Request Status

10-3732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The table below shows the relationship between the interrupt request signals generated by multijunction timers and the interrupt sources input to the Interrupt Controller (ICU). Table 10.2.6 Interrupt Request Signals Generated by MJT Signal Name Generated by Interrupt Request Source (Note 1) No. of ICU Input Sources IRQ0 TIO0, TIO1, TIO2, TIO3 MJT output interrupt 0 4 IRQ1 TOP6, TOP7 MJT output interrupt 1 2 IRQ2 TOP0, TOP1, TOP2, TOP3, TOP4, TOP5 MJT output interrupt 2 6 IRQ3 TIO8, TIO9 MJT output interrupt 3 2 IRQ4 TIO4, TIO5, TIO6, TIO7 MJT output interrupt 4 4 IRQ6 TOP8, TOP9 MJT output interrupt 5 2 IRQ7 TMS0, TMS1 MJT output interrupt 6 2 IRQ8 TIN7, TIN8, TIN9, TIN10, TIN11 MJT input interrupt 0 5 IRQ9 TIN0 MJT input interrupt 1 1 IRQ10 TIN16, TIN17, TIN18, TIN19 MJT input interrupt 2 4 IRQ11 TIN20, TIN21, TIN22, TIN23, TIN24, TIN25 MJT input interrupt 3 8 TIN26, TIN27 IRQ12 TIN3, TIN4, TIN5, TIN6 MJT input interrupt 4 4 IRQ13 TOU0_0, TOU0_1, TOU0_2, TOU0_3 TOU0 output interrupt 8 TOU0_4, TOU0_5, TOU0_6, TOU0_7 IRQ16 TOU1_0, TOU1_1, TOU1_2, TOU1_3 TOU1 output interrupt 8 TOU1_4, TOU1_5, TOU1_6, TOU1_7 IRQ18 TIN30, TIN31, TIN32, TIN33 TML1 input interrupt 4 Note 1: See Chapter 5, “Interrupt Controller (ICU).” Note: • TOP10, TID0 and TID1 have only one interrupt source in each interrupt group, so that their status and mask registers are nonexistent in the MJT interrupt control registers. (They are controlled directly by the Interrupt Controller.)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TOP Interrupt Control Register 0 (TOPIR0) <Address: H’0080 0230> <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0." 00

2 TOPIS5 (TOP5 interrupt request status bit) 0: Interrupt not requested R(Note 1)

3 TOPIS4 (TOP4 interrupt request status bit) 1: Interrupt requested

4 TOPIS3 (TOP3 interrupt request status bit)

5 TOPIS2 (TOP2 interrupt request status bit)

6 TOPIS1 (TOP1 interrupt request status bit)

7 TOPIS0 (TOP0 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TOP Interrupt Control Register 1 (TOPIR1) <Address: H’0080 0231> <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 No function assigned. Fix to "0." 00

10 TOPIM5 (TOP5 interrupt request mask bit) 0: Enable interrupt request R W

11 TOPIM4 (TOP4 interrupt request mask bit) 1: Mask (disable) interrupt request

12 TOPIM3 (TOP3 interrupt request mask bit)

13 TOPIM2 (TOP2 interrupt request mask bit)

14 TOPIM1 (TOP1 interrupt request mask bit)

15 TOPIM0 (TOP0 interrupt request mask bit)

TOPIS5 TOPIS4 TOPIS3 TOPIS2 TOPIS1 TOPIS0 00000000 b 8 9 1 01 11 21 31 4 b 1 5 TOPIM5 TOPIM4 TOPIM3 TOPIM2 TOPIM1 TOPIM0 00000000

10-3932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 MJT output interrupt request 2 IRQ2 Data bus TOPIS5 F/F TOPIM5 F/Fb10 TOPIS4 F/F TOPIM4 F/Fb11 b4 TOPIS3 F/F TOPIM3 F/Fb12 b5 TOPIS2 F/F TOPIM2 F/Fb13 b6 TOPIS1 F/F TOPIM1 F/Fb14 TOPIS0 F/F TOPIM0 F/Fb15 (Level) 6-source inputs TOPIR0 <H'0080 0230> TOPIR1 <H'0080 0231> TOP5udf TOP4udf TOP3udf TOP2udf TOP1udf TOP0udf Figure 10.2.6 Block Diagram of MJT Output Interrupt Request 2

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TOP Interrupt Control Register 2 (TOPIR2) <Address: H’0080 0232> <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0." 00

2 TOPIS7 (TOP7 interrupt request status bit) 0: Interrupt not requested R(Note 1)

3 TOPIS6 (TOP6 interrupt request status bit) 1: Interrupt requested

4, 5 No function assigned. Fix to "0." 00

6 TOPIM7 (TOP7 interrupt request mask bit) 0: Enable interrupt request R W

7 TOPIM6 (TOP6 interrupt request mask bit) 1: Mask (disable) interrupt request

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. b 0 123456 b 7 TOPIS7 TOPIS6 TOPIM7 TOPIM6 00000000 MJT output interrupt request 1 IRQ1 Data bus TOPIS7 F/F TOPIM7 F/Fb6 TOPIS6 F/F TOPIM6 F/Fb7 (Level) 2-source inputs TOPIR2 <H'0080 0232> TOP7udf TOP6udf Figure 10.2.7 Block Diagram of MJT Output Interrupt Request 1

10-4132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TOP Interrupt Control Register 3 (TOPIR3) <Address: H’0080 0233> <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 No function assigned. Fix to "0." 00

10 TOPIS9 (TOP9 interrupt request status bit) 0: Interrupt not requested R(Note 1)

11 TOPIS8 (TOP8 interrupt request status bit) 1: Interrupt requested

12, 13 No function assigned. Fix to "0." 00

14 TOPIM9 (TOP9 interrupt request mask bit) 0: Enable interrupt request R W

15 TOPIM8 (TOP8 interrupt request mask bit) 1: Mask (disable) interrupt request

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Note: • TOP10 has only one interrupt source in the interrupt group, so that its status and mask registers are nonexistent in th e MJT interrupt control registers. (They are controlled directly by the Interrupt Controller.) b10 TOPIS9 F/F TOPIM9 F/Fb14 b11 TOPIS8 F/F TOPIM8 F/Fb15 MJT output interrupt request 6 IRQ6(Level) 2-source inputs TOPIR3 <H'0080 0233> Data bus TOP9udf TOP8udf Figure 10.2.8 Block Diagram of MJT Output Interrupt Request 6 b 8 9 1 01 11 21 31 4 b 1 5 TOPIS9 TOPIS8 TOPIM9 TOPIM8 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIO Interrupt Control Register 0 (TIOIR0) <Address: H’0080 0234> <Upon exiting reset: H’00> b Bit Name Function R W

0 TIOIS3 (TIO3 interrupt request status bit) 0: Interrupt not requested R(Note 1)

1 TIOIS2 (TIO2 interrupt request status bit) 1: Interrupt requested

2 TIOIS1 (TIO1 interrupt request status bit)

3 TIOIS0 (TIO0 interrupt request status bit)

4 TIOIM3 (TIO3 interrupt request mask bit) 0: Enable interrupt request R W

5 TIOIM2 (TIO2 interrupt request mask bit) 1: Mask (disable) interrupt request

6 TIOIM1 (TIO1 interrupt request mask bit)

7 TIOIM0 (TIO0 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MJT output interrupt request 0 IRQ0 Data bus TIOIS3 F/F TIOIM3 F/Fb4 TIOIS2 F/F TIOIM2 F/Fb5 b2 TIOIS1 F/F TIOIM1 F/Fb6 b3 TIOIS0 F/F TIOIM0 F/Fb7 (Level) 4-source inputs TIOIR0 <H'0080 0234> TIO3udf TIO2udf TIO1udf TIO0udf Figure 10.2.9 Block Diagram of MJT Output Interrupt Request 0 b 0 123456 b 7 TIOIS3 TIOIS2 TIOIS1 TIOIS0 TIOIM3 TIOIM2 TIOIM1 TIOIM0 00000000

10-4332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIO Interrupt Control Register 1 (TIOIR1) <Address: H’0080 0235> <Upon exiting reset: H’00> b Bit Name Function R W

8 TIOIS7 (TIO7 interrupt request status bit) 0: Interrupt not requested R(Note 1)

9 TIOIS6 (TIO6 interrupt request status bit) 1: Interrupt requested

10 TIOIS5 (TIO5 interrupt request status bit)

11 TIOIS4 (TIO4 interrupt request status bit)

12 TIOIM7 (TIO7 interrupt request mask bit) 0: Enable interrupt request R W

13 TIOIM6 (TIO6 interrupt request mask bit) 1: Mask (disable) interrupt request

14 TIOIM5 (TIO5 interrupt request mask bit)

15 TIOIM4 (TIO4 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MJT output interrupt request 4 IRQ4 Data bus TIOIS7 F/F TIOIM7 F/Fb12 b9 TIOIS6 F/F TIOIM6 F/Fb13 b10 TIOIS5 F/F TIOIM5 F/Fb14 b11 TIOIS4 F/F TIOIM4 F/Fb15 (Level) 4-source inputs TIOIR1 <H'0080 0235> TIO7udf TIO6udf TIO5udf TIO4udf Figure 10.2.10 Block Diagram of MJT Output Interrupt Request 4 b 8 9 1 01 11 21 31 4 b 1 5 TIOIS7 TIOIS6 TIOIS5 TIOIS4 TIOIM7 TIOIM6 TIOIM5 TIOIM4 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIO Interrupt Control Register 2 (TIOIR2) <Address: H’0080 0236> <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0." 00

2 TIOIS9 (TIO9 interrupt request status bit) 0: Interrupt not requested R(Note 1)

3 TIOIS8 (TIO8 interrupt request status bit) 1: Interrupt requested

4, 5 No function assigned. Fix to "0." 00

6 TIOIM9 (TIO9 interrupt request mask bit) 0: Enable interrupt request R W

7 TIOIM8 (TIO8 interrupt request mask bit) 1: Mask (disable) interrupt request

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MJT output interrupt request 3 IRQ3 Data bus TIOIS9 F/F TIOIM9 F/Fb6 TIOIS8 F/F TIOIM8 F/Fb7 (Level) 2-source inputs TIOIR2 <H'0080 0236> TIO9udf TIO8udf Figure 10.2.11 Block Diagram of MJT Output Interrupt Request 3 b 0 123456 b 7 TIOIS9 TIOIS8 TIOIM9 TIOIM8 00000000

10-4532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TMS Interrupt Control Register (TMSIR) <Address: H’0080 0237> <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 No function assigned. Fix to "0." 00

10 TMSIS1 (TMS1 interrupt request status bit) 0: Interrupt not requested R(Note 1)

11 TMSIS0 (TMS0 interrupt request status bit) 1: Interrupt requested

12, 13 No function assigned. Fix to "0." 00

14 TMSIM1 (TMS1 interrupt request mask bit) 0: Enable interrupt request R W

15 TMSIM0 (TMS0 interrupt request mask bit) 1: Mask (disable) interrupt request

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MJT output interrupt request 7 IRQ7 Data bus b10 TMSIS1 F/F TMSIM1 F/Fb14 b11 TMSIS0 F/F TMSIM0 F/Fb15 (Level) 2-source inputs TMSIR <H'0080 0237> TMS1ovf TMS0ovf Figure 10.2.12 Block Diagram of MJT Output Interrupt Request 7 b 8 9 1 01 11 21 31 4 b 1 5 TMSIS1 TMSIS0 TMSIM1 TMSIM0 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIN Interrupt Control Register 0 (TINIR0) <Address: H’0080 0238> <Upon exiting reset: H’00> b Bit Name Function R W 0 No function assigned. Fix to "0." 00

1 TINIS2 (Reserved bit) Fix to "0" 0 0

2 TINIS1 (Reserved bit)

3 TINIS0 (TIN0 interrupt request status bit) 0: Interrupt not requested R (Note 1)

1: Interrupt requested 4 No function assigned. Fix to "0." 00

5 TINIM2 (Reserved bit) Fix to "0" 0 0

6 TINIM1 (Reserved bit)

7 TINIM0 (TIN0 interrupt request mask bit) 0: Enable interrupt request R W

1: Mask (disable) interrupt request Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Figure 10.2.13 Block Diagram of MJT Input Interrupt Request 1 MJT input interrupt request 1 IRQ9 Data bus TINIS0 F/F TINIM0 F/Fb7 (Level) TINIR0 <H'0080 0238> TIN0edge b 0 123456 b 7 TINIS2 TINIS1 TINIS0 TINIM2 TINIM1 TINIM0 00000000

10-4732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIN Interrupt Control Register 1 (TINIR1) <Address: H’0080 0239> <Upon exiting reset: H’00> b Bit Name Function R W

8 TINIS6 (TIN6 interrupt request status bit) 0: Interrupt not requested R(Note 1)

9 TINIS5 (TIN5 interrupt request status bit) 1: Interrupt requested

10 TINIS4 (TIN4 interrupt request status bit)

11 TINIS3 (TIN3 interrupt request status bit)

12 TINIM6 (TIN6 interrupt request mask bit) 0: Enable interrupt request R W

13 TINIM5 (TIN5 interrupt request mask bit) 1: Mask (disable) interrupt request

14 TINIM4 (TIN4 interrupt request mask bit)

15 TINIM3 (TIN3 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Figure 10.2.14 Block Diagram of MJT Input Interrupt Request 4 MJT input interrupt request 4 IRQ12 Data bus TINIS6 F/F TINIM6 F/Fb12 TINIS5 F/F TINIM5 F/Fb13 b10 TINIS4 F/F TINIM4 F/Fb14 (Level) 4-source inputs TINIR1 <H'0080 0239> TIN6edge TIN5edge TIN4edge b11 TINIS3 F/F TINIM3 F/Fb15 TIN3edge b 8 9 1 01 11 21 31 4 b 1 5 TINIS6 TINIS5 TINIS4 TINIS3 TINIM6 TINIM5 TINIM4 TINIM3 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIN Interrupt Control Register 2 (TINIR2) <Address: H’0080 023A> <Upon exiting reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0." 00

3 TINIS11 (TIN11 interrupt request status bit) 0: Interrupt not requested R(Note 1)

4 TINIS10 (TIN10 interrupt request status bit) 1: Interrupt requested

5 TINIS9 (TIN9 interrupt request status bit)

6 TINIS8 (TIN8 interrupt request status bit)

7 TINIS7 (TIN7 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIN Interrupt Control Register 3 (TINIR3) <Address: H’0080 023B> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0." 00

11 TINIM11 (TIN11 interrupt request mask bit) 0: Enable interrupt request R W

12 TINIM10 (TIN10 interrupt request mask bit) 1: Mask (disable) interrupt request

13 TINIM9 (TIN9 interrupt request mask bit)

14 TINIM8 (TIN8 interrupt request mask bit)

15 TINIM7 (TIN7 interrupt request mask bit)

TINIS11 TINIS10 TINIS9 TINIS8 TINIS7 00000000 b 8 9 1 01 11 21 31 4 b 1 5 TINIM11 TINIM10 TINIM9 TINIM8 TINIM7 00000000

10-4932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 MJT input interrupt request 0 IRQ8 Data bus TINIS11 F/F TINIM11 F/Fb11 TINIS10 F/F TINIM10 F/Fb12 b5 TINIS9 F/F TINIM9 F/Fb13 b6 TINIS8 F/F TINIM8 F/Fb14 b7 TINIS7 F/F TINIM7 F/Fb15 (Level) 5-source inputs TINIR2 <H'0080 023A> TINIR3 <H'0080 023B> TIN11edge TIN10edge TIN9edge TIN8edge TIN7edge Figure 10.2.15 Block Diagram of MJT Input Interrupt Request 0

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIN Interrupt Control Register 4 (TINIR4) <Address: H’0080 023C> <Upon exiting reset: H’00> b Bit Name Function R W

0 TINIS19 (TIN19 interrupt request status bit) 0: Interrupt not requested R(Note 1)

1 TINIS18 (TIN18 interrupt request status bit) 1: Interrupt requested

2 TINIS17 (TIN17 interrupt request status bit)

3 TINIS16 (TIN16 interrupt request status bit)

4 TINIS15 (Reserved bit) Fix to "0" 0 0

5 TINIS14 (Reserved bit)

6 TINIS13 (Reserved bit)

7 TINIS12 (Reserved bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIN Interrupt Control Register 5 (TINIR5) <Address: H’0080 023D> <Upon exiting reset: H’00> b Bit Name Function R W

8 TINIM19 (TIN19 interrupt request mask bit) 0: Enable interrupt request R W

9 TINIM18 (TIN18 interrupt request mask bit) 1: Mask (disable) interrupt request

10 TINIM17 (TIN17 interrupt request mask bit)

11 TINIM16 (TIN16 interrupt request mask bit)

12 TINIM15 (Reserved bit) Fix to "0" 0 0

13 TINIM14 (Reserved bit)

14 TINIM13 (Reserved bit)

15 TINIM12 (Reserved bit)

TINIS19 TINIS18 TINIS17 TINIS16 TINIS15 TINIS14 TINIS13 TINIS12 00000000 b 8 9 1 01 11 21 31 4 b 1 5 TINIM19 TINIM18 TINIM17 TINIM16 TINIM15 TINIM14 TINIM13 TINIM12 00000000

10-5132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 IRQ10 TINIS19 F/F TINIM19 F/Fb8 TINIS18 F/F TINIM18 F/Fb9 b2 TINIS17 F/F TINIM17 F/Fb10 b3 TINIS16 F/F TINIM16 F/Fb11 TINIR4 <H'0080 023C> TINIR5 <H'0080 023D> TIN19edge TIN18edge TIN17edge TIN16edge MJT input interrupt request 2 Data bus (Level) 4-source inputs Figure 10.2.16 Block Diagram of MJT Input Interrupt Request 2

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIN Interrupt Control Register 6 (TINIR6) <Address: H’0080 023E> <Upon exiting reset: H’00> b Bit Name Function R W

0 TINIS23 (TIN23 interrupt request status bit) 0: Interrupt not requested R(Note 1)

1 TINIS22 (TIN22 interrupt request status bit) 1: Interrupt requested

2 TINIS21 (TIN21 interrupt request status bit)

3 TINIS20 (TIN20 interrupt request status bit)

4 TINIM23 (TIN23 interrupt request mask bit) 0: Enable interrupt request R W

5 TINIM22 (TIN22 interrupt request mask bit) 1: Mask (disable) interrupt request

6 TINIM21 (TIN21 interrupt request mask bit)

7 TINIM20 (TIN20 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIN24,25 Interrupt Request Mask Register (TIN2425IMA) <Address: H’0080 07E2> <Upon exiting reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0." 00

6 TINIM24 (TIN24 interrupt request mask bit) 0: Enable interrupt request R W

7 TINIM25 (TIN25 interrupt request mask bit) 1: Mask (disable) interrupt request

TIN24,25 Interrupt Request Status Register (TIN2425IST) <Address: H’0080 07E3> <Upon exiting reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0." 00

14 TINIS24 (TIN24 interrupt request status bit) 0: Interrupt not requested R(Note 1)

15 TINIS25 (TIN25 interrupt request status bit) 1: Interrupt requested

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. b 0 123456 b 7 TINIS23 TINIS22 TINIS21 TINIS20 TINIM23 TINIM22 TINIM21 TINIM20 00000000 b 0 123456 b 7 TINIM24 TINIM25 00000000 b 8 9 1 01 11 21 31 4 b 1 5 TINIS24 TINIS25 00000000

10-5332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIN26,27 Interrupt Request Mask Register (TIN2627IMA) <Address: H’0080 0BE2> <Upon exiting reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0." 00

6 TINIM26 (TIN26 interrupt request mask bit) 0: Enable interrupt request R W

7 TINIM27 (TIN27 interrupt request mask bit) 1: Mask (disable) interrupt request

TIN26,27 Interrupt Request Status Register (TIN2627IST) <Address: H’0080 0BE3> <Upon exiting reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0." 00

14 TINIS26 (TIN26 interrupt request status bit) 0: Interrupt not requested R(Note 1)

15 TINIS27 (TIN27 interrupt request status bit) 1: Interrupt requested

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. b 0 123456 b 7 TINIM26 TINIM27 00000000 b 8 9 1 01 11 21 31 4 b 1 5 TINIS26 TINIS27 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 IRQ11 b15 TINIS27 F/F TINIM27 F/Fb7 b14 TINIS26 F/F TINIM26 F/Fb6 b15 TINIS25 F/F TINIM25 F/Fb7 b14 TINIS24 F/F TINIM24 F/Fb6 TINIS23 F/F TINIM23 F/Fb4 TIN2425IST<H'0080 07E3> TIN2425IMA<H'0080 07E2> TIN2627IST<H'0080 0BE3> TIN2627IMA<H'0080 0BE2> TINIR6<H'0080 023E> TIN27edge TIN26edge TIN25edge TIN24edge TIN23edge TINIS22 F/F TINIM22 F/Fb5 TIN22edge TINIS21 F/F TINIM21 F/Fb6 TIN21edge TINIS20 F/F TINIM20 F/Fb7 TIN20edge MJT input interrupt request 3 Data bus (Level) 8-source inputs Figure 10.2.17 Block Diagram of MJT Input Interrupt Request 3

10-5532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIN Interrupt Control Register 7 (TINIR7) <Address: H’0080 023F> <Upon exiting reset: H’00> b Bit Name Function R W

8 TINIS33 (TIN33 interrupt request status bit) 0: Interrupt not requested R(Note 1)

9 TINIS32 (TIN32 interrupt request status bit) 1: Interrupt requested

10 TINIS31 (TIN31 interrupt request status bit)

11 TINIS30 (TIN30 interrupt request status bit)

12 TINIM33 (TIN33 interrupt request mask bit) 0: Enable interrupt request R W

13 TINIM32 (TIN32 interrupt request mask bit) 1: Mask (disable) interrupt request

14 TINIM31 (TIN31 interrupt request mask bit)

15 TINIM30 (TIN30 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Note: • TIN24–TIN29 do not have interrupt functions, so that their status and mask registers are nonexistent. TML1 input interrupt request IRQ18 Data bus TINIS33 F/F TINIM33 F/Fb12 TINIS32 F/F TINIM32 F/Fb13 b10 TINIS31 F/F TINIM31 F/Fb14 b11 TINIS30 F/F TINIM30 F/Fb15 (Level) 4-source inputs TINIR7 <H'0080 023F> TIN33edge TIN32edge TIN31edge TIN30edge Figure 10.2.18 Block Diagram of TML1 Input Interrupt Request b 8 9 1 01 11 21 31 4 b 1 5 TINIS33 TINIS32 TINIS31 TINIS30 TINIM33 TINIM32 TINIM31 TINIM30 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TOU0 Interrupt Request Mask Register (TOU0IMA) <Address: H’0080 07D2> <Upon exiting reset: H’00> b Bit Name Function R W

0 TOU0IM7 (TOU0_7 interrupt request mask bit) 0: Enable interrupt request R W

1 TOU0IM6 (TOU0_6 interrupt request mask bit) 1: Mask (disable) interrupt request

2 TOU0IM5 (TOU0_5 interrupt request mask bit)

3 TOU0IM4 (TOU0_4 interrupt request mask bit)

4 TOU0IM3 (TOU0_3 interrupt request mask bit)

5 TOU0IM2 (TOU0_2 interrupt request mask bit)

6 TOU0IM1 (TOU0_1 interrupt request mask bit)

7 TOU0IM0 (TOU0_0 interrupt request mask bit)

TOU0 Interrupt Request Status Register (TOU0IST) <Address: H’0080 07D3> <Upon exiting reset: H’00> b Bit Name Function R W

8 TOU0IS7 (TOU0_7 interrupt request status bit) 0: Interrupt not requested R(Note 1)

9 TOU0IS6 (TOU0_6 interrupt request status bit) 1: Interrupt requested

10 TOU0IS5 (TOU0_5 interrupt request status bit)

11 TOU0IS4 (TOU0_4 interrupt request status bit)

12 TOU0IS3 (TOU0_3 interrupt request status bit)

13 TOU0IS2 (TOU0_2 interrupt request status bit)

14 TOU0IS1 (TOU0_1 interrupt request status bit)

15 TOU0IS0 (TOU0_0 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. b 0 123456 b 7 TOU0IM7 TOU0IM6 TOU0IM5 TOU0IM4 TOU0IM3 TOU0IM2 TOU0IM1 TOU0IM0 00000000 b 8 9 1 01 11 21 31 4 b 1 5 TOU0IS7 TOU0IS6 TOU0IS5 TOU0IS4 TOU0IS3 TOU0IS2 TOU0IS1 TOU0IS0 00000000

10-5732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TOU0 output interrupt request IRQ13 Data bus TOU0IS7 F/F TOU0IM7 F/Fb0 TOU0IS6 F/F TOU0IM6 F/Fb1 b10 TOU0IS5 F/F TOU0IM5 F/Fb2 b11 TOU0IS4 F/F TOU0IM4 F/Fb3 b12 TOU0IS3 F/F TOU0IM3 F/Fb4 (Level) 8-source inputs TOU0IMA <H'0080 07D2> TOU0IST <H'0080 07D3> TOU07udf TOU06udf TOU05udf TOU04udf TOU03udf b13 TOU0IS2 F/F TOU0IM2 F/Fb5 b14 TOU0IS1 F/F TOU0IM1 F/Fb6 b15 TOU0IS0 F/F TOU0IM0 F/Fb7 TOU02udf TOU01udf TOU00udf Figure 10.2.19 Block Diagram of TOU0 Output Interrupt Request

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TOU1 Interrupt Request Mask Register (TOU1IMA) <Address: H’0080 0BD2> <Upon exiting reset: H’00> b Bit Name Function R W

0 TOU1IM7 (TOU1_7 interrupt request mask bit) 0: Enable interrupt request R W

1 TOU1IM6 (TOU1_6 interrupt request mask bit) 1: Mask (disable) interrupt request

2 TOU1IM5 (TOU1_5 interrupt request mask bit)

3 TOU1IM4 (TOU1_4 interrupt request mask bit)

4 TOU1IM3 (TOU1_3 interrupt request mask bit)

5 TOU1IM2 (TOU1_2 interrupt request mask bit)

6 TOU1IM1 (TOU1_1 interrupt request mask bit)

7 TOU1IM0 (TOU1_0 interrupt request mask bit)

TOU1 Interrupt Request Status Register (TOU1IST) <Address: H’0080 0BD3> <Upon exiting reset: H’00> b Bit Name Function R W

8 TOU1IS7 (TOU1_7 interrupt request status bit) 0: Interrupt not requested R (Note 1)

9 TOU1IS6 (TOU1_6 interrupt request status bit) 1: Interrupt requested

10 TOU1IS5 (TOU1_5 interrupt request status bit)

11 TOU1IS4 (TOU1_4 interrupt request status bit)

12 TOU1IS3 (TOU1_3 interrupt request status bit)

13 TOU1IS2 (TOU1_2 interrupt request status bit)

14 TOU1IS1 (TOU1_1 interrupt request status bit)

15 TOU1IS0 (TOU1_0 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. b 0 123456 b 7 TOU1IM7 TOU1IM6 TOU1IM5 TOU1IM4 TOU1IM3 TOU1IM2 TOU1IM1 TOU1IM0 00000000 b 8 9 1 01 11 21 31 4 b 1 5 TOU1IS7 TOU1IS6 TOU1IS5 TOU1IS4 TOU1IS3 TOU1IS2 TOU1IS1 TOU1IS0 00000000

10-5932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 IRQ16 TOU1IS7 F/F TOU1IM7 F/Fb0 TOU1IS6 F/F TOU1IM6 F/Fb1 b10 TOU1IS5 F/F TOU1IM5 F/Fb2 b11 TOU1IS4 F/F TOU1IM4 F/Fb3 b12 TOU1IS3 F/F TOU1IM3 F/Fb4 TOU1IMA <H'0080 0BD2> TOU1IST <H'0080 0BD3> TOU17udf TOU16udf TOU15udf TOU14udf TOU13udf b13 TOU1IS2 F/F TOU1IM2 F/Fb5 b14 TOU1IS1 F/F TOU1IM1 F/Fb6 b15 TOU1IS0 F/F F/Fb7 TOU12udf TOU11udf TOU10udf TOU1IM0 TOU1 output interrupt request Data bus (Level) 8-source inputs Figure 10.2.20 Block Diagram of TOU1 Output Interrupt Request

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.3.1 Outline of TOP

TOP (Timer OutPut) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software:

• Single-shot output mode  Delayed single-shot output mode  Continuous output mode The table below and the diagram in the next page show specifications and a block diagram of TOP, respectively. Table 10.3.1 Specifications of TOP (Output-Related 16-Bit Timer) Item Specification Number of channels 11 channels Counter 16-bit down-counter Reload register 16-bit reload register Correction register 16-bit correction register Timer startup Started by writing to the enable bit in software or enabled by external input (rising or falling edge or both) Operation mode <With correction function>  Single-shot output mode  Delayed single-shot output mode <Without correction function>  Continuous output mode Interrupt request generation Can be generated by a counter underflow

10-6132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.3.1 Block Diagram of TOP (Output-Related 16-Bit Timer) IRQ2 clk en udf TOP 0 Clock bus Input event bus clk en udfTOP 1 clk en udfTOP 2 clk en udfTOP 3 Output event bus TCLK0S TO 0 (P110) IRQ9 3 2 1 0 clk en udfTOP 4 clk en udfTOP 5 TCLK0 (P124) TIN0 (P150) S STIN0S clk en udfTOP 6 clk en udfTOP 7 S S S S S clk en udfTOP 8 clk en udfTOP 9 clk en udfTOP 10 F/F0 F/F1 F/F2 F/F3 F/F4 F/F5 F/F6 F/F7 F/F8 F/F9 F/F10 S S S S S IRQ2 IRQ2 IRQ2 IRQ2 IRQ2 TO 1 (P111) TO 2 (P112) TO 3 (P113) TO 4 (P114) TO 5 (P115) TO 6 (P116) TO 7 (P117) TO 8 (P100) TO 9 (P101) TO 10 (P102) IRQ1 IRQ1 IRQ6 IRQ6 IRQ5 3 2 1 0 0 1 2 3 Reload register Down-counter Correction register 3 2 1 0 3 2 1 0 0 1 2 3 (16-bit) DMA3, DMA common S : SelectorF/F : Output flip-flop

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.3.2 Outline of Each Mode of TOP

Each mode of TOP is outlined below. For each TOP channel, only one of the following modes can be selected. (1) Single-shot output mode In single-shot output mode, the timer generates a pulse in width of "reload register set value + 1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload register, the counter is loaded with the content of “the reload register -1” and starts counting synchro- nously with the count clock at the next circle. The counter counts down and stops. The F/F output waveform in single-shot output mode is inverted at enable and upon underflow (F/F output level is changed “L” to “H”, or “H” to “L”), generating a single-shot pulse waveform in width of “reload register set value + 1” only once. And also an interrupt request can be generated when the counter underflows. The counter value is “setting value of reload register +1.” (2) Delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of “reload register set value + 1” after a finite time equal to “counter set value + 1” only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. The next cycle after first counter underflow, it is loaded with “the reload register value -1” and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level is changed “L” to “H”, or “H” to “L”), when the counter underflows first time and next, generating a single-shot pulse waveform in width of “reload register set value + 1” after a finite time equal to “first set value of counter + 1” only once. And also an interrupt request can be generated when the counter underflows first time and next. The effective counter value is “counter set value +1” or “reload register set value +1.” (3) Continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and at the cycle after the counter underflows, it is loaded with the value that “ the reload register -1”. Thereafter, this opera- tion is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of “reload register set value + 1.” When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. At the cycle after this underflow, the counter to be loaded with the content of “the reload register -1” and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output level is changed “L” to “H”, or “H” to “L”), at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each time the counter underflows. The effective counter value is “counter set value +1” and “reload register set value +1.”

10-6332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 <Count clock-dependent delay>  Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated by the time when the timer actually starts operating after writing to the enable bit. In operation mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is inverted. BCLK Count clock Enable F/F operation (Note 1) Count clock period Count clock-dependent delay Write to the enable bit Note 1: This applies to the case where F/F output is inverted when the timer is enabled. Inverted Figure 10.3.2 Count Clock Dependent Delay

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.3.3 TOP Related Register Map

Shown below is a TOP related register map. TOP Related Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0240 TOP0 Counter 10-71 (TOP0CT) H'0080 0242 TOP0 Reload Register 10-72 (TOP0RL) H'0080 0244 (Use inhibited area) H'0080 0246 TOP0 Correction Register 10-73 (TOP0CC) (Use inhibited area) H'0080 0250 TOP1 Counter 10-71 (TOP1CT) H'0080 0252 TOP1 Reload Register 10-72 (TOP1RL) H'0080 0254 (Use inhibited area) H'0080 0256 TOP1 Correction Register 10-73 (TOP1CC) (Use inhibited area) H'0080 0260 TOP2 Counter 10-71 (TOP2CT) H'0080 0262 TOP2 Reload Register 10-72 (TOP2RL) H'0080 0264 (Use inhibited area) H'0080 0266 TOP2 Correction Register 10-73 (TOP2CC) (Use inhibited area) H'0080 0270 TOP3 Counter 10-71 (TOP3CT) H'0080 0272 TOP3 Reload Register 10-72 (TOP3RL) H'0080 0274 (Use inhibited area) H'0080 0276 TOP3 Correction Register 10-73 (TOP3CC) (Use inhibited area) H'0080 0280 TOP4 Counter 10-71 (TOP4CT) H'0080 0282 TOP4 Reload Register 10-72 (TOP4RL) H'0080 0284 (Use inhibited area) H'0080 0286 TOP4 Correction Register 10-73 (TOP4CC) (Use inhibited area) H'0080 0290 TOP5 Counter 10-71 (TOP5CT) H'0080 0292 TOP5 Reload Register 10-72 (TOP5RL) H'0080 0294 (Use inhibited area) H'0080 0296 TOP5 Correction Register 10-73 (TOP5CC) H'0080 0298 (Use inhibited area)

10-6532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TOP Related Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 029A TOP0–5 Control Register 0 10-67 (TOP05CR0) H'0080 029C (Use inhibited area) TOP0–5 Control Register 1 10-67 (TOP05CR1) (Use inhibited area) H'0080 02A0 TOP6 Counter 10-71 (TOP6CT) H'0080 02A2 TOP6 Reload Register 10-72 (TOP6RL) H'0080 02A4 (Use inhibited area) H'0080 02A6 TOP6 Correction Register 10-73 (TOP6CC) H'0080 02A8 (Use inhibited area) H'0080 02AA TOP6,7 Control Register 10-69 (TOP67CR) (Use inhibited area) H'0080 02B0 TOP7 Counter 10-71 (TOP7CT) H'0080 02B2 TOP7 Reload Register 10-72 (TOP7RL) H'0080 02B4 (Use inhibited area) H'0080 02B6 TOP7 Correction Register 10-73 (TOP7CC) (Use inhibited area) H'0080 02C0 TOP8 Counter 10-71 (TOP8CT) H'0080 02C2 TOP8 Reload Register 10-72 (TOP8RL) H'0080 02C4 (Use inhibited area) H'0080 02C6 TOP8 Correction Register 10-73 (TOP8CC) (Use inhibited area) H'0080 02D0 TOP9 Counter 10-71 (TOP9CT) H'0080 02D2 TOP9 Reload Register 10-72 (TOP9RL) H'0080 02D4 (Use inhibited area) H'0080 02D6 TOP9 Correction Register 10-73 (TOP9CC) (Use inhibited area) H'0080 02E0 TOP10 Counter 10-71 (TOP10CT) H'0080 02E2 TOP10 Reload Register 10-72 (TOP10RL) H'0080 02E4 (Use inhibited area) H'0080 02E6 TOP10 Correction Register 10-73 (TOP10CC) H'0080 02E8 (Use inhibited area) H'0080 02EA TOP8–10 Control Register 10-70 (TOP810CR) (Use inhibited area) H'0080 02FA TOP0–10 External Enable Permit Register 10-74 (TOPEEN) H'0080 02FC TOP0–10 Enable Protect Register 10-74 (TOPPRO) H'0080 02FE TOP0–10 Count Enable Register 10-75 (TOPCEN)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.3.4 TOP Control Registers

The TOP control registers are used to select operation modes of TOP0–10 (single-shot output, delayed single- shot output or continuous output mode), as well as select the count enable and count clock sources. Following four TOP control registers are provided for each timer group.  TOP0–5 Control Register 0 (TOP05CR0)  TOP0–5 Control Register 1 (TOP05CR1)  TOP6,7 Control Register (TOP67CR)  TOP8–10 Control Register (TOP810CR)

10-6732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TOP0–5 Control Register 0 (TOP05CR0) <Address: H’0080 029A> <Upon exiting reset: H’0000> b Bit Name Function R W 0, 1 TOP3M (TOP3 operation mode select bit) 00: Single-shot output mode R W 2, 3 TOP2M (TOP2 operation mode select bit) 01: Delayed single-shot output mode 4, 5 TOP1M (TOP1 operation mode select bit) 10: Continuous output mode 6, 7 TOP0M (TOP0 operation mode select bit) 11: Continuous output mode 8 No function assigned. Fix to "0." 00 9–11 TOP05ENS 000: External TIN0 input R W TOP0–5 enable source select bit 001: External TIN0 input 010: External TIN0 input 011: External TIN0 input 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12, 13 No function assigned. Fix to "0." 00 14, 15 TOP05CKS 00: Clock bus 0 R W TOP0–5 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive. TOP0–5 Control Register 1 (TOP05CR1) <Address: H’0080 029D> <Upon exiting reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0." 00 12, 13 TOP5M (TOP5 operation mode select bit) 00: Single-shot output mode R W 14, 15 TOP4M (TOP4 operation mode select bit) 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode Note:  Operation mode can only be set or changed while the counter is inactive. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP3M TOP2M TOP1M TOP0M TOP05ENS TOP05CKS 0000000000000000 b 8 9 1 01 11 21 31 4 b 1 5 TOP5M TOP4M 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 clk en TOP 0 Clock bus Input event bus clk en TOP 1 clk en TOP 2 clk en TOP 3 3 2 1 0 clk en TOP 4 clk en TOP 5 S S : Selector TIN0 (P150) S TIN0S 3 2 1 0 Note: • This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.3 Outline Diagram of TOP0–5 Clock and Enable Inputs

10-6932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP7ENS TOP7M TOP6M TOP67ENS TOP67CKS 0000000000000000 TOP6,7 Control Register (TOP67CR) <Address: H’0080 02AA> <Upon exiting reset: H’0000> b Bit Name Function R W 0 No function assigned. Fix to "0." 00

1 TOP7ENS 0: Result selected by TOP67ENS bit R W

TOP7 enable source select bit 1: TOP6 output 2, 3 TOP7M 00: Single-shot output mode R W TOP7 operation mode select bit 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode 4, 5 No function assigned. Fix to "0." 00 6, 7 TOP6M 00: Single-shot output mode R W TOP6 operation mode select bit 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode 8 No function assigned. Fix to "0." 00 9–11 TOP67ENS 000: Does not select the enable source R W TOP6, TOP7 enable source select bit 001: Does not select the enable source 010: Does not select the enable source 011: Does not select the enable source 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12, 13 No function assigned. Fix to "0." 00 14, 15 TOP67CKS 00: Clock bus 0 R W TOP6, TOP7 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive. Clock bus Input event bus 3 2 1 0 clk en udfTOP 6 clk en udfTOP 7 S S S : Selector 3 2 1 0 S Note:  This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.4 Outline Diagram of TOP6, TOP7 Clock and Enable Inputs

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TOP8–10 Control Register (TOP810CR) <Address: H’0080 02EA> <Upon exiting reset: H’0000> b Bit Name Function R W 0, 1 No function assigned. Fix to "0." 00 2, 3 TOP10M (TOP10 operation mode select bit) 00: Single-shot output mode R W 4, 5 TOP9M (TOP9 operation mode select bit) 01: Delayed single-shot output mode 6, 7 TOP8M (TOP8 operation mode select bit) 10: Continuous output mode 11: Continuous output mode 8–10 No function assigned. Fix to "0." 00

11 TOP810ENS 0: Does not select the enable source R W

TOP8–10 enable source select bit 1: Input event bus 3 12, 13 No function assigned. Fix to "0." 00 14, 15 TOP810CKS 00: Clock bus 0 R W TOP8–10 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP10M TOP9M TOP8M TOP810 TOP810CKSENS 0000000000000000 Clock bus Input event bus 3 2 1 0 S S clk en TOP 8 clk en TOP 9 clk en TOP 10 S : Selector 3 2 1 0 Note:  This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.5 Outline Diagram of TOP8–10 Clock and Enable Inputs

10-7132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.3.5 TOP Counters (TOP0CT–TOP10CT)

TOP0 Counter (TOP0CT) <Address: H’0080 0240> TOP1 Counter (TOP1CT) <Address: H’0080 0250> TOP2 Counter (TOP2CT) <Address: H’0080 0260> TOP3 Counter (TOP3CT) <Address: H’0080 0270> TOP4 Counter (TOP4CT) <Address: H’0080 0280> TOP5 Counter (TOP5CT) <Address: H’0080 0290> TOP6 Counter (TOP6CT) <Address: H’0080 02A0> TOP7 Counter (TOP7CT) <Address: H’0080 02B0> TOP8 Counter (TOP8CT) <Address: H’0080 02C0> TOP9 Counter (TOP9CT) <Address: H’0080 02D0> TOP10 Counter (TOP10CT) <Address: H’0080 02E0> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TOP0CT–TOP10CT 16-bit counter value R W Note:  These registers must always be accessed in halfwords. The TOP counters are a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by external input), the counter starts counting synchronously with the count clock. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP0CT –TOP10CT

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.3.6 TOP Reload Registers (TOP0RL–TOP10RL)

TOP0 Reload Register (TOP0RL) <Address: H’0080 0242> TOP1 Reload Register (TOP1RL) <Address: H’0080 0252> TOP2 Reload Register (TOP2RL) <Address: H’0080 0262> TOP3 Reload Register (TOP3RL) <Address: H’0080 0272> TOP4 Reload Register (TOP4RL) <Address: H’0080 0282> TOP5 Reload Register (TOP5RL) <Address: H’0080 0292> TOP6 Reload Register (TOP6RL) <Address: H’0080 02A2> TOP7 Reload Register (TOP7RL) <Address: H’0080 02B2> TOP8 Reload Register (TOP8RL) <Address: H’0080 02C2> TOP9 Reload Register (TOP9RL) <Address: H’0080 02D2> TOP10 Reload Register (TOP10RL) <Address: H’0080 02E2> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TOP0RL–TOP10RL 16-bit reload register value R W Note:  This register must always be accessed in halfwords. The TOP reload registers are used to load data into the TOP counters (TOP0CT~TOP10CT). The content of "the reload register -1" is loaded into the counter synchronously with the count clock at the following timing:  At the next cycle when the counter is enabled in single-shot output mode  At the next cycle when the counter underflowed in delayed single-shot or continuous output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. Note that reloading of data after an underflow is performed synchronously with a clock pulse at which the counter underflowed. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP0RL–TOP10RL

10-7332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.3.7 TOP Correction Registers (TOP0CC–TOP10CC)

TOP0 Correction Register (TOP0CC) <Address: H’0080 0246> TOP1 Correction Register (TOP1CC) <Address: H’0080 0256> TOP2 Correction Register (TOP2CC) <Address: H’0080 0266> TOP3 Correction Register (TOP3CC) <Address: H’0080 0276> TOP4 Correction Register (TOP4CC) <Address: H’0080 0286> TOP5 Correction Register (TOP5CC) <Address: H’0080 0296> TOP6 Correction Register (TOP6CC) <Address: H’0080 02A6> TOP7 Correction Register (TOP7CC) <Address: H’0080 02B6> TOP8 Correction Register (TOP8CC) <Address: H’0080 02C6> TOP9 Correction Register (TOP9CC) <Address: H’0080 02D6> TOP10 Correction Register (TOP10CC) <Address: H’0080 02E6> (Acceptable range of values: +32,767 to –32,768) <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TOP0CC–TOP10CC 16-bit correction register value R W Note:  These registers must always be accessed in halfwords. The TOP correction registers are used to correct the TOP counter value by adding or subtracting in the middle of operation. To increase or reduce the counter value, write to this correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the correction register. The counter is corrected synchronously with a clock pulse next to one at which the correction value was written to the TOP correction register. If the counter is corrected this way, note that because one down count in that clock period is canceled, the counter value actually is corrected by "correction register value + 1." For example, if the initial counter value is 10 and the value 3 is written to the correction register when the counter has counted down to 5, then the counter counts a total of 15 before it underflows. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP0CC –TOP10CC

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.3.8 TOP Enable Control Registers

TOP0–10 External Enable Permit Register (TOPEEN) <Address: H’0080 02FA> <Upon exiting reset: H’0000> b Bit Name Function R W 0–4 No function assigned. Fix to "0." 00

5 TOP10EEN (TOP10 external enable permit bit) 0: Disable external enable R W

6 TOP9EEN (TOP9 external enable permit bit) 1: Enable external enable

7 TOP8EEN (TOP8 external enable permit bit)

8 TOP7EEN (TOP7 external enable permit bit)

9 TOP6EEN (TOP6 external enable permit bit)

10 TOP5EEN (TOP5 external enable permit bit)

11 TOP4EEN (TOP4 external enable permit bit)

12 TOP3EEN (TOP3 external enable permit bit)

13 TOP2EEN (TOP2 external enable permit bit)

14 TOP1EEN (TOP1 external enable permit bit)

15 TOP0EEN (TOP0 external enable permit bit)

Note:  This register must always be accessed in halfwords. The TOP0–10 External Enable Permit Register controls enable operation on TOP counters from external de- vices by enabling or disabling it. TOP0–10 Enable Protect Register (TOPPRO) <Address: H’0080 02FC> <Upon exiting reset: H’0000> b Bit Name Function R W 0–4 No function assigned. Fix to "0." 00

5 TOP10PRO (TOP10 enable protect bit) 0: Enable for rewriting R W

6 TOP9PRO (TOP9 enable protect bit) 1: Protect against rewriting

7 TOP8PRO (TOP8 enable protect bit)

8 TOP7PRO (TOP7 enable protect bit)

9 TOP6PRO (TOP6 enable protect bit)

10 TOP5PRO (TOP5 enable protect bit)

11 TOP4PRO (TOP4 enable protect bit)

12 TOP3PRO (TOP3 enable protect bit)

13 TOP2PRO (TOP2 enable protect bit)

14 TOP1PRO (TOP1 enable protect bit)

15 TOP0PRO (TOP0 enable protect bit)

Note:  This register must always be accessed in halfwords. The TOP0–10 Enable Protect Register controls rewriting of the TOP count enable bit by enabling for or protect- ing it against rewriting. b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO 0000000000000000 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 EEN EEN EEN EEN EEN EEN EEN EEN EEN EEN EEN 0000000000000000

10-7532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 CEN CEN CEN CEN CEN CEN CEN CEN CEN CEN CEN 0000000000000000 TOP0–10 Count Enable Register (TOPCEN) <Address: H’0080 02FE> <Upon exiting reset: H’0000> b Bit Name Function R W 0–4 No function assigned. Fix to "0." 00

5 TOP10CEN (TOP10 count enable bit) 0: Stop counting R W

6 TOP9CEN (TOP9 count enable bit) 1: Enable counting

7 TOP8CEN (TOP8 count enable bit)

8 TOP7CEN (TOP7 count enable bit)

9 TOP6CEN (TOP6 count enable bit)

10 TOP5CEN (TOP5 count enable bit)

11 TOP4CEN (TOP4 count enable bit)

12 TOP3CEN (TOP3 count enable bit)

13 TOP2CEN (TOP2 count enable bit)

14 TOP1CEN (TOP1 count enable bit)

15 TOP0CEN (TOP0 count enable bit)

Note:  This register must always be accessed in halfwords. The TOP0–10 Count Enable Register controls operation of TOP counters. To enable any TOP counter in software, enable its corresponding enable protect bit for write and set the count enable bit by writing "1." To stop any TOP counter, enable its corresponding enable protect bit for write and reset the count enable bit by writing "0." In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable bit is automatically reset to "0." Therefore, the TOP0-10 Count Enable Register when accessed for read serves as a status register indicating whether the counter is operating or idle. WR bn TOPm enable protect (TOPmPRO) WR EN-ON TOPm external enable (TOPmEEN) TINnS TOPm count enable (TOPmCEN) TOP enable control Input processing selection F/F F/F F/F Event bus TINn Figure 10.3.6 Configuration of the TOP Enable Circuit

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function)

(1) Outline of TOP single-shot output mode In single-shot output mode, the timer generates a pulse in width of "reload register set value+1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload register, at the next cycle the counter is loaded with the content of "the reload register -1" and starts counting synchronously with the count clock. The counter counts down and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from "L" to "H" or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of "reload register set value + 1" only once. An interrupt request can be generated when the counter underflows. The count value is "reload register set value + 1." For example, if the initial reload register value is 7, then the count value is 8. Figure 10.3.7 Example of Counting in TOP Single-shot Output Mode 12345678 6 5 4 3 H'FFFF 2 1 (Note 3) Enable Reload register Counter Interrupt request Underflow Count value = 8 Note 1: What actually is seen in the cycle immediately during enable is the previous counter value, and not 7. Note 2: A count clock dependent delay is included before F/F output changes state after the timer is enabled. Note 3: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. F/F output Count clock (Note 2) (Note 1)

10-7732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 In the example below, the reload register is initially set to H’A000. (The initial counter value can be undefined, and does not have to be specific.) When the timer starts, the value that "the reload register -1" is loaded into the counter, letting it start counting. Thereafter, it continues counting down until it underflows after reaching the minimum count. H'FFFF H'0000 H'A000 H'FFFF H'(A000-1) Count clock Correction register Enabled (by writing to the enable bit or by external input) F/F output Disabled (by underflow) (Unused) TOP interrupt request due to underflow Enable bit Starts counting down from the reload register set value Reload register Data inverted by enable Counter Data inverted by underflow Indeterminate value (Note 1) (Note 2) Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled. Note 2: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. Figure 10.3.8 Typical Operation in TOP Single-shot Output Mode

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) Correction function of TOP single-shot output mode To change the counter value while in progress, write to the TOP correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the correction register. The counter is corrected synchronously with a count clock pulse next to one at which the correction value was written to the TOP correction register. If the counter is corrected this way, note that because one down count in that clock period is canceled, the counter value actually is corrected by "correction register value + 1." For example, if the initial counter value is 7 and the value 3 is written to the correction register when the counter has counted down to 3, then the counter counts a total of 12 before it underflows. Figure 10.3.9 Example of Counting in TOP Single-shot Output Mode When Count is Corrected When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. 123456789 1 0 1 1 1 2 6 5 4 3 2 1 0 6 5 4 3 H'FFFF Correction register Underflow Count value = (7 + 1) + (3 + 1) = 12 Count clock dependent delay Enable Reload register Counter Interrupt request Count clock (Note 1) Note 1: What actually is seen in the cycle immediately after enable is the previous counter value, and not 7. Note 2: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. Indeterminate value (Note 2) + 3

10-7932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.3.10 Typical Operation in TOP Single-shot Output Mode When Count is Corrected H'(8000 - 1) H'FFFF H'0000 H'8000 H'5000 H'5000 + H'4000 H'8000 H'FFFF H'4000Undefined F/F output TOP interrupt request due to underflow Count clock Correction register Enabled (by writing to the enable bit or by external input) Enable bit Reload register Write to the correction register Undefined value Disabled (by underflow) Counter (Note 1) Note 1: What actually is seen in the cycle immediately after enable is the previous counter value, and not 7. Note 2: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. (Note 2) Data inverted by enable Data inverted by underflow In the example below, the reload register is initially set to H’8000. When the timer starts, the value that "the reload register -1" is loaded into the counter, letting it start counting down. In the diagram below, the value H’4000 is written to the correction register when the counter has counted down to H’5000. As a result of this correction, the count has been increased to H’9000, so that the counter counts a total of (H’8000 + 1 + H’4000 + 1) before it stops.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (3) Notes on using TOP single-shot output mode The following describes precautions to be observed when using TOP single-shot output mode.  If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.  If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  Because the timer operates synchronously with the count clock, a count clock-dependent delay is included before F/F output is inverted after the timer is enabled.  When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. Therefore, if the counter underflows in the subsequent down-count after an overflow, a false interrupt request is generated for an underflow that includes the overflowed count.

10-8132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 H'FFFF H'0000 H'FFF8 H'(FFF0+0014) H'0004 H'FFF0 H'0014 H'FFF8 H'FFFF H'(FFF8-1) Data inverted by enable Data inverted by underflow Counter Count clock Correction register F/F output Enable bit Reload register Write to the correction register Enabled (by writing to the enable bit or by external input) Undefined value Actual count after overflow Overflow occurs Undefined TOP interrupt request due to underflow Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled. Note 2: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. (Note 2) (Note 1) Figure 10.3.11 Example of an Operation in TOP Single-shot Output Mode Where Count Overflows Due to Correction In the example below, the reload register is initially set to H’FFF8. When the timer starts, the value that "the reload register -1" is loaded into the counter, letting it start counting down. In the diagram below, the value H’0014 is written to the correction register when the counter has counted down to H’FFF0. As a result of this correction, the count overflows to H’0004 and the counter fails to count correctly. Also, an interrupt request is generated for an erroneous overflowed count.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function)

(1) Outline of TOP delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of "reload register set value + 1" after a finite time equal to "counter set value + 1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. At the cycle after the first time the counter underflows, it is loaded with the value that "the reload register -1" and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of "reload register set value + 1" after a finite time equal to "first set value of counter + 1" only once. An interrupt request can be generated when the counter underflows first time and next. The "counter set value + 1" and "reload register set value + 1" are effective as count values. For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates as shown below. Figure 10.3.12 Example of Counting in TOP Delayed Single-shot Output Mode 123 45 678 9 10 11 4 3 2 1 3 2 1 0 H'FFFFH'FFFF F/F output (Note 1) Count clock dependent delay Enable Reload register Counter Interrupt request Count clock Underflow Underflow Count value = (4 + 1) + (5 + 1) = 11 (Note 2) Note 1: What actually is seen in the cycle immediately during underflow is H'FFFF(underflow value), and not 5. Note 2: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information.

10-8332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respec- tively. When the timer is enabled, the counter starts counting down and at the cycle after it underflows , the counter is loaded with the content of "the reload register -1" and continues counting down. The counter stops when it underflows second time. Figure 10.3.13 Typical Operation in TOP Delayed Single-shot Output Mode H'FFFF H'0000 Underflow (first time) Count down from the counter's set valueH'A000 Underflow (second time) H'F000 Count down from the reload register's set value H'(F000-1) (Unused) H'FFFF H'F000 Data inverted by underflow Data inverted by underflow Count clock Correction register Enabled (by writing to the enable bit or by external input) F/F output TOP interrupt request due to underflow Enable bit Reload register Counter (Note 1) Note 1: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) Correction function of TOP delayed single-shot output mode To change the counter value while in progress, write to the TOP correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the correction register. The counter is corrected synchronously with a count clock pulse next to one at which the correction value was written to the TOP correction register. If the counter is corrected this way, note that because one down count in that clock period is canceled, the counter value actually is corrected by "correction register value + 1." For example, if the reload register value is 7 and the value 3 is written to the correction register when the counter has counted down to 3 after being reloaded, then the counter counts a total of 12 after being reloaded before it underflows. 6 5 4 3 2 1 0 123456789 1 0 1 1 1 2 6 5 4 3 H'FFFF H'FFFF Enable = "H" (Note 1) Underflow Correction register Reload register Counter Interrupt request Count clock Count value after being reloaded = (7 + 1) + (3 + 1) = 12 (Note 2) Note 1: What actually is seen in the cycle immediately during underflow is H'FFFF(the underflow value), and not 7. Note 2: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. Figure 10.3.14 Example of Counting in TOP Delayed Single-shot Output Mode When Count is Corrected When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow.

10-8532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.3.15 Typical Operation in TOP Delayed Single-shot Output Mode when Count is Corrected H'FFFF H'0000 H'9000+H'0008 H'F000 H'A000 H'F000 H'(F000+0008+1) H'0008 Write to the correction register H'9000 Data inverted by underflow Data inverted by underflow Correction register F/F output TOP interrupt request due to underflow Enable bit Note 1: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. Reload register Counter Count clock Underflow (first time) Underflow (second time) Enabled (by writing to the enable bit or by external input) Undefined (Note 1) In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respec- tively. When the timer is enabled, the counter starts counting down and at the cycle after the first underflow, the counter is loaded with the content of "the reload register -1" and continues counting down. In the dia- gram below, the value H’0008 is written to the correction register when the counter has counted down to H’9000. As a result of this correction, the counter has its count value increased to H’9008 and counts (H’F000 + 1 + H’0008 + 1) after the first underflow before it stops.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (3) Notes on using TOP delayed single-shot output mode The following describes precautions to be observed when using TOP delayed single-shot output mode.  If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.  If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. Therefore, if the counter underflows in the subsequent down-count after an overflow, a false interrupt request is generated for an underflow that includes the overflowed count.  If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF but changes to "reload register value -1" at the next count clock timing after underflow. Figure 10.3.16 Counter Value Immediately after Underflow Count clock Enable bit "H" H'0001 H'0000 H'FFFF H'AAA9 H'AAA8Counter value H'AAAAReload register underflow H'(AAAA-1) H'(AAAA-2) What is seen during underflow cycle is always H'FFFF, and not the reload register value (in this case, H'AAAA). Count down from the reload register value Reload cycle The value that "reload register - 1" is reloaded by count clock next underflow

10-8732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.3.11 Operation in TOP Continuous Output Mode (without Correction Function)

(1) Outline of TOP continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and at the cycle after the counter underflows, it is loaded with the value that "the reload register -1." Thereafter, this opera- tion is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of "reload register set value + 1." When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. At the cycle after this underflow, the counter to be loaded with the content of "the reload register -1" and count down over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each time the counter underflows. The "counter set value + 1" and "reload register set value + 1" are effective as count values. For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates as shown below. Figure 10.3.17 Example of Counting in TOP Continuous Output Mode 12345 123456123456 (4) 3 2 1 0 3 2 1 0 4 3 2 1 0 (Note 1) F/F output (Note 2) Interrupt request Underflow Note 1: What actually is seen in the cycle immediately during enable is the previous counter value, and not 4. Note 2: What actually is seen in the cycle immediately during underflow is H'FFFF (underflow value), and not 5. Note 3: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. Underflow Underflow (Note 2) (Note 2) Count clock dependent delay Enable Counter Count clock Count value = 5 Count value = 6 Count value = 6 (Note 3) (Note 3) (Note 3 Reload register

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 In the example below, the counter and the reload register are initially set to H’A000 and H’E000, respectively. When the timer is enabled, the counter starts counting down and when it underflows after reaching the mini- mum count, the counter is loaded with the content of "the reload register -1" and continues counting down. However the timing for reloading is at the cycle after underflow. H'FFFF H'0000 H'E000 H'A000 H'FFFF H'FFFF Data inverted by underflow Data inverted by underflow Data inverted by enable Count clock Correction register F/F output TOP interrupt request due to underflow Enable bit Reload register Counter Underflow (first time) Underflow (second time) Enabled (by writing to the enable bit or by external input) Count down from the counter's set value Count down from the reload register's set value Count down from the reload register's set value (Unused) (Note 2) Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled. Note 2: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. (Note 2) (Note 1) Figure 10.3.18 Typical Operation in TOP Continuous Output Mode

10-8932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) Notes on using TOP continuous output mode The following describes precautions to be observed when using TOP continuous output mode.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF but changes to "reload register value -1" at the next count clock timing.  Because the timer operates synchronously with the count clock, a count clock-dependent delay is included before F/F output is inverted after the timer is enabled.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.4.1 Outline of TIO

TIO (Timer Input/Output) is an input/output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time: <Input modes>

• Measure clear input mode  Measure free-run input mode  Noise processing input mode <Output modes without correction function>  PWM output mode  Single-shot output mode  Delayed single-shot output mode  Continuous output mode The table below and the diagram in the next page show specifications and a block diagram of TIO, respectively. Table 10.4.1 Specifications of TIO (Input/Output-Related 16-Bit Timer) Item Specification Number of channels 10 channels Counter 16-bit down-counter Reload register 16-bit reload register Measure register 16-bit capture register Timer startup Started by writing to the enable bit in software or enabled by external input (rising or falling or both edges or "H" or "L" level) Operation mode <Input modes>  Measure clear input mode  Measure free-run input mode  Noise processing input mode <Output modes without correction function>  PWM output mode  Single-shot output mode  Delayed single-shot output mode  Continuous output mode Interrupt request generation Can be generated by a counter underflow DMA transfer request generation Can be generated by a counter underflow (TIO8, TIO9 only)

10-9132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 IRQ12 IRQ12 IRQ12 3 2 1 0 IRQ8 TIN7 (P33) TCLK1 (P125) clk en/cap udf TIO 0 clk en/cap udfTIO 1 clk en/cap udfTIO 2 clk en/cap udfTIO 3 clk en/cap udfTIO 4 S STIN3STIN3 (P153) S S TIN4STIN4 (P30) TIN5STIN5 (P31) S SIRQ12 TIN6STIN6 (P32) PRS1 PRS0 clk en/cap udfTIO 5STCLK1S STIN7S IRQ8 TIN8 (P44) TCLK2 (P126) clk en/cap udfTIO 6STCLK2S STIN8S IRQ8 TIN9 (P45) clk en/cap udfTIO 7S STIN9S IRQ8 TIN10 (P46) S STIN10S clk en/cap udfTIO 8 clk en/cap udfTIO 9 IRQ8 TIN11 (P47) S STIN11S F/F11 F/F12 F/F13 F/F14 F/F15 S F/F16 F/F17 F/F18 F/F19 S S S S S S S S S TO 11 (P103) TO 12 (P104) TO 13 (P105) TO 14 (P106) TO 15 (P107) IRQ0 IRQ0 IRQ0 IRQ0 IRQ4 TO 16 (P93) TO 17 (P94) TO 18 (P95) TO 19 (P96) TO 20 (P97) IRQ4 IRQ4 IRQ4 DMA0, DMA common IRQ3 3 2 1 0 0 1 2 3 0 1 2 33 2 1 0 3 2 1 0 PRS2 IRQ3 F/F20 DMA4 DMA5 DMA common DMA1 Clock bus Input event bus Output event bus S : SelectorF/F : Flip-flopPRS0–2 : Prescaler Reload 0/measure register Down-counter Reload 1 register (Note 1) (16-bit) Note 1: The reload 1 register is used in only PWM output mode. BCLK Figure 10.4.1 Block Diagram of TIO (Input/Output-Related 16-Bit Timer)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.4.2 Outline of Each Mode of TIO

Each mode of TIO is outlined below. For each TIO channel, only one of the following modes can be selected. (1) Measure clear/free-run input modes In measure clear/free-run input modes, the timer is used to measure a duration of time from when the counter starts counting until when an external capture signal is entered.And also it is possible to generate both an interrupt requested by underflow at the counter or execution of measurement operation and a DMA transfer request (for only the TIO8 and TIO9) upon underflow of the counter. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchro- nously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written into a register called the “measure register.” In measure clear input mode, the counter value is initialized to H’FFFF upon capture, from which the counter starts counting down again. The counter returns to H’FFFF upon underflow, from which it starts counting down.Furthermore when it underflows goes back to H’FFFF and continues down countingB In measure free-run input mode, the counter continues counting down even after capture. The counter returns to H’FFFF upon underflow, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. (2) Noise processing input mode In noise processing input mode, the timer is used to detect that the input signal remained in the same state for over a predetermined time. In noise processing input mode, a "H" or "L" level on external input activates the counter and if the input signal remains in the same state for over a predetermined time before the counter underflows, the counter generates an interrupt request before stopping. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and at the next cycle when a valid-level signal is entered again, the counter is reloaded with the value that "the reload register -1" and restarts counting. The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) upon underflow of the counter. (3) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the value that “the reload 0 register -1” and starts counting down synchronously with the count clock at the next cycle.The next cycle after the first time the counter underflows, it is loaded with the value that “the reload 1 register -1” and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs.The effective counter value is “reload 0 register set value +1” or “reload 1 register set value +1”. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output level changes from "L" to "H" or vice versa), when the counter starts counting and each time it underflows. Furthermore, it is possible to generate an interrupt request at even-numbered occurrences of underflow after the counter is enabled and a DMA transfer request (for only the TIO8 and TIO9) every time the counter underflows. In addition PWM output mode of TIO does not have function of correction.

10-9332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (4) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of “reload 0 register set value + 1” only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload 0 register, the counter is loaded with the value that “the reload 0 register -1” and starts counting synchronously with the count clock at the next cycle. The counter counts down and when the minimum count is reached, stops upon underflow. The F/F output waveform in single-shot output mode is inverted(F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of “reload 0 register set value + 1” only once. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) upon underflow of the counter. (5) Delayed single-shot output mode (without correction function) In delayed single-shot output mode, the timer generates a pulse in width of “reload 0 register set value + 1” after a finite time equal to “counter set value + 1” only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock. The next cycle after the first time the counter underflows, it is loaded with the value that “the reload 0 register -1” and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted(F/F output level changes from "L" to "H" or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of “reload 0 register set value + 1” after a finite time equal to “first set value of counter + 1” only once. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) upon the first and next underflows of the counter. (6) Continuous output mode (without correction function) In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses in width of “reload 0 register set value + 1”. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. The next cycle after this underflow causes the counter to be loaded with the content of “the reload 0 register -1” and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The timing for reloading to counter is the cycle after underflow. The F/F output waveform in continuous output mode is inverted(F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) each time the counter underflows.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 <Count clock-dependent delay>  Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated by the time when the timer actually starts operating after writing to the enable bit. In operation mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is inverted. BCLK Count clock Enable F/F operation (Note 1) Count clock period Count clock-dependent delay Write to the enable bit Note 1: This applies to the case where F/F output is inverted when the timer is enabled. Inverted Figure 10.4.2 Count Clock Dependent Delay

10-9532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.4.3 TIO Related Register Map

Shown below is a TIO related register map. TIO Related Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0300 TIO0 Counter 10-105 (TIO0CT) H'0080 0302 (Use inhibited area) H'0080 0304 TIO0 Reload 1 Register 10-107 (TIO0RL1) H'0080 0306 TIO0 Reload 0/ Measure Register 10-106 (TIO0RL0) (Use inhibited area) H'0080 0310 TIO1 Counter 10-105 (TIO1CT) H'0080 0312 (Use inhibited area) H'0080 0314 TIO1 Reload 1 Register 10-107 (TIO1RL1) H'0080 0316 TIO1 Reload 0/ Measure Register 10-106 (TIO1RL0) H'0080 0318 (Use inhibited area) H'0080 031A TIO0–3 Control Register 0 10-98 (TIO03CR0) H'0080 031C (Use inhibited area) TIO0–3 Control Register 1 10-99 (TIO03CR1) (Use inhibited area) H'0080 0320 TIO2 Counter 10-105 (TIO2CT) H'0080 0322 (Use inhibited area) H'0080 0324 TIO2 Reload 1 Register 10-107 (TIO2RL1) H'0080 0326 TIO2 Reload 0/ Measure Register 10-106 (TIO2RL0) (Use inhibited area) H'0080 0330 TIO3 Counter 10-105 (TIO3CT) H'0080 0332 (Use inhibited area) H'0080 0334 TIO3 Reload 1 Register 10-107 (TIO3RL1) H'0080 0336 TIO3 Reload 0/ Measure Register 10-106 (TIO3RL0) (Use inhibited area) H'0080 0340 TIO4 Counter 10-105 (TIO4CT) H'0080 0342 (Use inhibited area) H'0080 0344 TIO4 Reload 1 Register 10-107 (TIO4RL1) H'0080 0346 TIO4 Reload 0/ Measure Register 10-106 (TIO4RL0) H'0080 0348 (Use inhibited area) H'0080 034A TIO4 Control Register TIO5 Control Register 10-100 (TIO4CR) (TIO5CR) 10-102 (Use inhibited area)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIO Related Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0350 TIO5 Counter 10-105 (TIO5CT) H'0080 0352 (Use inhibited area) H'0080 0354 TIO5 Reload 1 Register 10-107 (TIO5RL1) H'0080 0356 TIO5 Reload 0/ Measure Register 10-106 (TIO5RL0) (Use inhibited area) H'0080 0360 TIO6 Counter 10-105 (TIO6CT) H'0080 0362 (Use inhibited area) H'0080 0364 TIO6 Reload 1 Register 10-107 (TIO6RL1) H'0080 0366 TIO6 Reload 0/ Measure Register 10-106 (TIO6RL0) H'0080 0368 (Use inhibited area) H'0080 036A TIO6 Control Register TIO7 Control Register 10-103 (TIO6CR) (TIO7CR) 10-104 (Use inhibited area) H'0080 0370 TIO7 Counter 10-105 (TIO7CT) H'0080 0372 (Use inhibited area) H'0080 0374 TIO7 Reload 1 Register 10-107 (TIO7RL1) H'0080 0376 TIO7 Reload 0/ Measure Register 10-106 (TIO7RL0) (Use inhibited area) H'0080 0380 TIO8 Counter 10-105 (TIO8CT) H'0080 0382 (Use inhibited area) H'0080 0384 TIO8 Reload 1 Register 10-107 (TIO8RL1) H'0080 0386 TIO8 Reload 0/ Measure Register 10-106 (TIO8RL0) H'0080 0388 (Use inhibited area) H'0080 038A TIO8 Control Register TIO9 Control Register 10-104 (TIO8CR) (TIO9CR) 10-105 (Use inhibited area) H'0080 0390 TIO9 Counter 10-105 (TIO9CT) H'0080 0392 (Use inhibited area) H'0080 0394 TIO9 Reload 1 Register 10-107 (TIO9RL1) H'0080 0396 TIO9 Reload 0/ Measure Register 10-106 (TIO9RL0) (Use inhibited area) H'0080 03BC TIO0–9 Enable Protect Register 10-108 (TIOPRO) H'0080 03BE TIO0–9 Count Enable Register 10-109 (TIOCEN)

10-9732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.4.4 TIO Control Registers

The TIO control registers are used to select operation modes of TIO0–9 (measure input, noise processing input, PWM output, single-shot output, delayed single-shot output or continuous output mode), as well as select the count enable and count clock sources. Following TIO control registers are provided for each timer group.  TIO0–3 Control Register 0 (TIO03CR0)  TIO0–3 Control Register 1 (TIO03CR1)  TIO4 Control Register (TIO4CR)  TIO5 Control Register (TIO5CR)  TIO6 Control Register (TIO6CR)  TIO7 Control Register (TIO7CR)  TIO8 Control Register (TIO8CR)  TIO9 Control Register (TIO9CR)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIO0–3 Control Register 0 (TIO03CR0) <Address: H’0080 031A> <Upon exiting reset: H’0000> b Bit Name Function R W

0 TIO3EEN (Note 1) 0: Disable external input R W

TIO3 external input enable bit 1: Enable external input 1–3 TIO3M 000: Single-shot output mode R W TIO3 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode

4 TIO2ENS 0: Do not use enable/measure input source R W

TIO2 enable/measure input source select bit 1: External input TIN5 5–7 TIO2M 000: Single-shot output mode R W TIO2 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode

8 TIO1ENS 0: Do not use enable/measure input source R W

TIO1 enable/measure input source select bit 1: External input TIN4 9–11 TIO1M 000: Single-shot output mode R W TIO1 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode

12 TIO0ENS 0: Do not use enable/measure input source R W

TIO0 enable/measure input source select bit 1: External input TIN3 13–15 TIO0M 000: Single-shot output mode R W TIO0 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note 1: During measure free-run/clear input mode, even if this bit is set to "0" (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written into the measure register. In measure clear input mode, however, if this bit = "0" (external input disabled), the counter value is not initialized (H’FFFF) upon capture and, therefore, this bit should be set to "1" (external input enabled) when using measure clear input mode. Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive.  To select TIO3 enable/measure input sources, use the TIO4 Control Register TIO34ENS (TIO3, TIO4 enable/measure input source select) bits. b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TIO3EEN TIO3M TIO2ENS TIO2M TIO1ENS TIO1M TIO0ENS TIO0M 0000000000000000

10-9932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIO0–3 Control Register 1 (TIO03CR1) <Address: H’0080 031D> <Upon exiting reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0." 00 14, 15 TIO03CKS 00: Clock bus 0 R W TIO0–3 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Figure 10.4.3 Outline Diagram of TIO0–4 Clock and Enable Inputs Clock bus Input event bus 3 2 1 0 clk en/cap TIO 0 clk en/cap TIO 1 clk en/cap TIO 2 clk en/cap TIO 3 clk en/cap TIO 4 S STIN3STIN3 (P153) S S TIN4STIN4 (P30) TIN5STIN5 (P31) S S TIN6STIN6 (P32) S : Selector 3 2 1 0 3 2 1 0 3 2 1 0 Note:  This diagram only illustrates TIO control registers and is partly omitted. b 8 9 1 01 11 21 31 4 b 1 5 TIO03CKS 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIO4 Control Register (TIO4CR) <Address: H’0080 034A> <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 TIO4CKS 00: Clock bus 0 R W TIO4 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3

2 TIO4EEN (Note 1) 0: Disable external input R W

TIO4 external input enable bit 1: Enable external input 3, 4 TIO34ENS 00: External input TIN6 R W TIO3,4 enable/measure input source select bit 01: External input TIN6 10: Input event bus 2 11: Input event bus 3 5–7 TIO4M 000: Single-shot output mode R W TIO4 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note 1: During measure free-run/clear input mode, even if this bit is set to "0" (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written into the measure register. In measure clear input mode, however, if this bit = "0" (external input disabled), the counter value is not initialized (H’FFFF) upon capture and, therefore, this bit should be set to "1" (external input enabled) when using measure clear input mode. Note:  Operation mode can only be set or changed while the counter is inactive. b 0 123456 b 7 TIO4CKS TIO4EEN TIO34ENS TIO4M 00000000

10-10132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 clk en/capS TCLK2S STIN8S Clock bus Input event bus 3 2 1 0 TIN7 (P33) TCLK1 (P125) clk en/cap TIO 5S TCLK1S STIN7S TIN8 (P44) TCLK2 (P126) TIO 6 TIN9 (P45) clk en/cap TIO 7S STIN9S TIN10 (P46) S S TIN10S clk en/cap TIO 8 clk en/cap TIO 9 TIN11 (P47) S STIN11S S : Selector 3 2 1 0 3 2 1 0 3 2 1 0 Note:  This diagram only illustrates TIO control registers and is partly omitted. Figure 10.4.4 Outline Diagram of TIO5–9 Clock and Enable Inputs

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIO5 Control Register (TIO5CR) <Address: H’0080 034B> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 TIO5CKS 000: External input TCLK1 R W TIO5 clock source select bit 001: External input TCLK1 010: External input TCLK1 011: External input TCLK1 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 11, 12 TIO5ENS 00: Do not use enable/measure input source R W TIO5 enable/measure input source select bit 01: Do not use enable/measure input source 10: External input TIN7 11: Input event bus 3 13–15 TIO5M 000: Single-shot output mode R W TIO5 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note:  Operation mode can only be set or changed while the counter is inactive. b 8 9 1 01 11 21 31 4 b 1 5 TIO5CKS TIO5ENS TIO5M 00000000

10-10332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIO6 Control Register (TIO6CR) <Address: H’0080 036A> <Upon exiting reset: H’00> b Bit Name Function R W 0–2 TIO6CKS 000: External input TCLK2 R W TIO6 clock source select bit 001: External input TCLK2 010: External input TCLK2 011: External input TCLK2 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 3, 4 TIO6ENS 00: Do not use enable/measure input source R W TIO6 enable/measure input source select bit 01: External input TIN8 10: Input event bus 2 11: Input event bus 3 5–7 TIO6M 000: Single-shot output mode R W TIO6 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note:  Operation mode can only be set or changed while the counter is inactive. b 0 123456 b 7 TIO6CKS TIO6ENS TIO6M 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIO7 Control Register (TIO7CR) <Address: H’0080 036B> <Upon exiting reset: H’00> b Bit Name Function R W 8 No function assigned. Fix to "0." 00 9, 10 TIO7CKS 00: Clock bus 0 R W TIO7 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11, 12 TIO7ENS 00: Do not use enable/measure input source R W TIO7 enable/measure input source select bit 01: External input TIN9 10: Input event bus 0 11: Input event bus 3 13–15 TIO7M 000: Single-shot output mode R W TIO7 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note:  Operation mode can only be set or changed while the counter is inactive. TIO8 Control Register (TIO8CR) <Address: H’0080 038A> <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 TIO8CKS 100: Clock bus 0 R W TIO8 clock source select bit 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 2–4 TIO8ENS 000: Do not use enable/measure input source R W TIO8 enable/measure input source select bit 001: Do not use enable/measure input source 010: Do not use enable/measure input source 011: Do not use enable/measure input source 100: External input TIN10 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 5–7 TIO8M 000: Single-shot output mode R W TIO8 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note:  Operation mode can only be set or changed while the counter is inactive. b 8 9 1 01 11 21 31 4 b 1 5 TIO7CKS TIO7ENS TIO7M 00000000 b 0 123456 b 7 TIO8CKS TIO8ENS TIO8M 00000000

10-10532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.4.5 TIO Counters (TIO0CT–TIO9CT)

TIO0 Counter (TIO0CT) <Address: H’0080 0300> TIO1 Counter (TIO1CT) <Address: H’0080 0310> TIO2 Counter (TIO2CT) <Address: H’0080 0320> TIO3 Counter (TIO3CT) <Address: H’0080 0330> TIO4 Counter (TIO4CT) <Address: H’0080 0340> TIO5 Counter (TIO5CT) <Address: H’0080 0350> TIO6 Counter (TIO6CT) <Address: H’0080 0360> TIO7 Counter (TIO7CT) <Address: H’0080 0370> TIO8 Counter (TIO8CT) <Address: H’0080 0380> TIO9 Counter (TIO9CT) <Address:H’0080 0390> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TIO0CT–TIO9CT 16-bit counter value R(Note 1) Note 1: Protected against write during PWM output mode. Note:  These registers must always be accessed in halfwords. The TIO counters are a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by external input), the counter starts counting synchronously with the count clock. These counters are protected against write during PWM output mode. TIO9 Control Register (TIO9CR) <Address: H’0080 038B> <Upon exiting reset: H’00> b Bit Name Function R W 8 No function assigned. Fix to "0." 00 9, 10 TIO9CKS 00: Clock bus 0 R W TIO9 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11, 12 TIO9ENS 00: Do not use enable/measure input source R W TIO9 enable/measure input source select bit 01: External input TIN11 10: Input event bus 1 11: Input event bus 3 13–15 TIO9M 000: Single-shot output mode R W TIO9 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note:  Operation mode can only be set or changed while the counter is inactive. b 8 9 1 01 11 21 31 4 b 1 5 TIO9CKS TIO9ENS TIO9M 00000000 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO0CT –TIO9CT

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0)

TIO0 Reload 0/ Measure Register (TIO0RL0) <Address: H’0080 0306> TIO1 Reload 0/ Measure Register (TIO1RL0) <Address: H’0080 0316> TIO2 Reload 0/ Measure Register (TIO2RL0) <Address: H’0080 0326> TIO3 Reload 0/ Measure Register (TIO3RL0) <Address: H’0080 0336> TIO4 Reload 0/ Measure Register (TIO4RL0) <Address: H’0080 0346> TIO5 Reload 0/ Measure Register (TIO5RL0) <Address: H’0080 0356> TIO6 Reload 0/ Measure Register (TIO6RL0) <Address: H’0080 0366> TIO7 Reload 0/ Measure Register (TIO7RL0) <Address: H’0080 0376> TIO8 Reload 0/ Measure Register (TIO8RL0) <Address: H’0080 0386> TIO9 Reload 0/ Measure Register (TIO9RL0) <Address:H’0080 0396> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TIO0RL0–TIO9RL0 16-bit reload register value R(Note 1) Note 1: These registers are protected against write during measure input mode. Note:  These registers must always be accessed in halfwords. The TIO Reload 0/ Measure Registers serve dual purposes as a register for reloading data into the TIO Count Registers (TIO0CT-TIO9CT) and as a measure register during measure input mode. These registers are pro- tected against write during measure input mode. The content of "the reload 0 register -1" is reloaded into the counter synchronously with the count clock at the following timing:  At the next cycle when after the counter started counting in noise processing input mode, the input signal is inverted and a valid-level signal is entered again before the counter underflows  At the next cycle when the counter is enabled in single-shot output mode  At the next cycle when the counter underflowed in delayed single-shot output or continuous output mode  At the next cycle when the counter is enabled in PWM output mode and at the next cyclewhen the counter value set by the reload 1 register underflowed Simply because data is written to the reload 0 register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. If the register is used as a measure register, the counter value is latched into that measure register by event input. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO0RL0 –TIO9RL0

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10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1)

TIO0 Reload 1 Register (TIO0RL1) <Address: H’0080 0304> TIO1 Reload 1 Register (TIO1RL1) <Address: H’0080 0314> TIO2 Reload 1 Register (TIO2RL1) <Address: H’0080 0324> TIO3 Reload 1 Register (TIO3RL1) <Address: H’0080 0334> TIO4 Reload 1 Register (TIO4RL1) <Address: H’0080 0344> TIO5 Reload 1 Register (TIO5RL1) <Address: H’0080 0354> TIO6 Reload 1 Register (TIO6RL1) <Address: H’0080 0364> TIO7 Reload 1 Register (TIO7RL1) <Address: H’0080 0374> TIO8 Reload 1 Register (TIO8RL1) <Address: H’0080 0384> TIO9 Reload 1 Register (TIO9RL1) <Address:H’0080 0394> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TIO0RL1–TIO9RL1 16-bit reload register value R W Note:  These registers must always be accessed in halfwords. The TIO Reload 1 Registers are used to reload data into the TIO Count Registers (TIO0CT–TIO9CT). The content of "the reload 1 register -1" is reloaded into the counter counting synchronously with the count clock at the following timing:  At the next cycle when the count value set by the reload 0 register underflowed in PWM output mode Simply because data is written to the reload 1 register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TIO0RL1 –TIO9RL1

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO9 TIO8 TIO7 TIO6 TIO5 TIO4 TIO3 TIO2 TIO1 TIO0 PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO 0000000000000000

10.4.8 TIO Enable Control Registers

TIO0–9 Enable Protect Register (TIOPRO) <Address: H’0080 03BC> <Upon exiting reset: H’0000> b Bit Name Function R W 0–5 No function assigned. Fix to "0." 00

6 TIO9PRO (TIO9 enable protect bit) 0: Enable rewrite R W

7 TIO8PRO (TIO8 enable protect bit) 1: Disable rewrite

8 TIO7PRO (TIO7 enable protect bit)

9 TIO6PRO (TIO6 enable protect bit)

10 TIO5PRO (TIO5 enable protect bit)

11 TIO4PRO (TIO4 enable protect bit)

12 TIO3PRO (TIO3 enable protect bit)

13 TIO2PRO (TIO2 enable protect bit)

14 TIO1PRO (TIO1 enable protect bit)

15 TIO0PRO (TIO0 enable protect bit)

Note:  This register must always be accessed in halfwords. The TIO0–9 Enable Protect Register controls rewriting of the TIO count enable bit described in the next page by enabling or disabling it.

10-10932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO9 TIO8 TIO7 TIO6 TIO5 TIO4 TIO3 TIO2 TIO1 TIO0 CEN CEN CEN CEN CEN CEN CEN CEN CEN CEN 0000000000000000 WR bn TIOm enable protect (TIOmPRO) WR EN-ON TIOm external enable (TIOmEEN or TIOmENS) TINnS TIOm count enable (TIOmCEN) TIO enable control Input processing selection F/F F/F F/F Event bus TINn Figure 10.4.5 Configuration of the TIO Enable Circuit TIO0–9 Count Enable Register (TIOCEN) <Address: H’0080 03BE> <Upon exiting reset: H’0000> b Bit Name Function R W 0–5 No function assigned. Fix to "0." 00

6 TIO9CEN (TIO9 count enable bit) 0: Stop count R W

7 TIO8CEN (TIO8 count enable bit) 1: Enable count

8 TIO7CEN (TIO7 count enable bit)

9 TIO6CEN (TIO6 count enable bit)

10 TIO5CEN (TIO5 count enable bit)

11 TIO4CEN (TIO4 count enable bit)

12 TIO3CEN (TIO3 count enable bit)

13 TIO2CEN (TIO2 count enable bit)

14 TIO1CEN (TIO1 count enable bit)

15 TIO0CEN (TIO0 count enable bit)

Note:  This register must always be accessed in halfwords The TIO0–9 Count Enable Register controls operation of the TIO counters. To enable any TIO counter in software, enable its corresponding enable protect bit for write and set the count enable bit by writing "1." To stop any TIO counter, enable its corresponding enable protect bit for write and reset the count enable bit by writing "0." In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable bit is automatically reset to "0." Therefore, the TIO0–9 Count Enable Register when accessed for read serves as a status register indicating whether the counter is operating or idle.

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10.4.9 Operation in TIO Measure Free-Run/Clear Input Modes

(1) Outline of TIO measure free-run/clear input modes In measure free-run/clear input modes, the timer is used to measure a duration of time from when the counter starts counting until when an external capture signal is entered. It is possible to generate an inter- rupt request upon underflow of the counter or execution of measurement operation and a DMA transfer request (for only the TIO8 and TIO9) upon underflow of the counter. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchro- nously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written into a register called the “measure register.” In measure clear input mode, the counter value is initialized to H’FFFF upon capture, from which the counter starts counting down again. The counter returns to H’FFFF upon underflow, from which it starts counting down. In measure free-run input mode, the counter continues counting down even after capture and upon under- flow, recycles to H’FFFF, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. Figure 10.4.6 Typical Operation in Measure Free-Run Input Mode H'FFFF H'0000 H'7000 H'9000 H'7000 H'9000 DMA transfer request (Note 1) Count clock Counter TIO interrupt request Enable bit Measure register TIN interrupt request Undefined value Undefined Note 1: Only TIO8 and TIO9 can be generated. Note:  This diagram does not show detailed timing information. Enabled (by writing to the enable bit) Measure event (capture) occurs Measure event (capture) TIN interrupt request due to external event input TIO interrupt request due to underflow TIN interrupt request due to external event input DMA transfer request due to underflow

10-11132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) Notes on using TIO measure free-run/ clear input modes The following describes precautions to be observed when using TIO measure free-run/ clear input modes.  If measure event input and write to the counter occur in the same clock period, the write value is set in the counter while at the same time latched into the measure register. Figure 10.4.7 Typical Operation in Measure Clear Input Mode H'FFFF H'0000 H'7000 H'7000 DMA transfer request (Note 1) Note 1: Only TIO8 and TIO9 can be generated. Note:  This diagram does not show detailed timing information. DMA transfer request due to underflow Enabled (by writing to the enable bit) Measure event (capture) occurs Count clock Counter TIO interrupt request Enable bit Measure register TIN interrupt request Undefined value TIN interrupt request due to external event input Undefined TIO interrupt request due to underflow

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.4.10 Operation in TIO Noise Processing Input Mode

In noise processing input mode, the timer is used to detect that the input signal remained in the same state for over a predetermined time. In noise processing input mode, a "H" or "L" level on external input activates the counter and if the input signal remains in the same state for over a predetermined time before the counter underflows, the counter generates an interrupt request before stopping. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and at the next cycle after a valid-level signal is entered again, the counter is reloaded with the value that "reload register -1" and restarts counting. The effec- tive count width is "reload 0 register set value + 1." The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) upon underflow of the counter. Figure 10.4.8 Typical Operation in Noise Processing Input Mode H'FFFF H'0000 H'A000 H'A000 DMA transfer request (Note 1) Note 1: Only TIO8 and TIO9 can be generated. Note 2: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. DMA transfer request due to underflow Reload 0 register External input (noise processing) Effective signal width Invalid Disabled by underflow Count clock Counter Enabled (by writing to the enable bit) TIO interrupt request Enable bit Invalid TIO interrupt request due to underflow Undefined value (Note 2) (Note 2) (Note 2)

10-11332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 H'FFFF H'0000 H'A000 (Note 3) (Note 2) H'C000 H'A000 H'C000 H'A000(Note 2) Count clock Enabled (by writing to the enable bit or by external input) Underflow (first time) Enable bit Reload 0 register Count down from the reload 1 register set value Reload 1 register Reload 1 buffer Count down from the reload 0 register set value DMA transfer request (Note 1) Note 1: Only TIO8 and TIO9 can be generated. Note 2: The value that "reload 0 register - 1" is reloaded. Note 3: The value that "reload 1 buffer - 1" is reloaded. Note 4: When reload0 is reloaded after updating reload0 register, reload 1 buffer is tranferd. Note 5: Updating of reload 0 and reload 1 during timer operation does not effect PWM waveform that is outputting at present. Updating is reflected at the next PWM period after updating reload 0 register. Note:  This diagram does not show detailed timing information. DMA transfer request due to underflow TIO interrupt request DMA transfer request due to underflow TIO interrupt request due to even-numbered occurrences of underflow Undefined value Underflow (second time) Count down from the reload 0 register set value H'A000 H'C000 H'A000 Counter PWM output period (Note 4) (Note 4) F/F output (Note 5) Data inverted by enable Data inverted by underflow Data inverted by underflow

10.4.11 Operation in TIO PWM Output Mode

(1) Outline of TIO PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When the timer is enabled "by writing to the enable bit in software or by external input" after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the value that "the reload 0 register -1" and starts counting down synchronously with the count clock at the next cycle. At the cycle after the first time the counter underflows, it is loaded with the value that "the reload 1 register -1" and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The "reload 0 register set value + 1" and "reload 1 register set value + 1" respectively are effective as count values. The timer stops at the same time count is disabled by writing to the enable bit "and not in synchronism with PWM output period." The F/F output waveform in PWM output mode is inverted "F/F output level changes from "L" to "H" or vice versa" when the counter starts counting and each time it underflows. Furthermore, it is possible to generate an interrupt request at even-numbered occurrences of underflow after the counter is enabled and a DMA transfer request "for only the TIO8 and TIO9" every time the counter underflows. Note that TIO’s PWM output mode does not have the count correction function. Figure 10.4.9 Typical Operation in PWM Output Mode

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 To rewrite the reload 0 and reload 1 registers while the timer is operating, rewrite the reload 1 register first and then the reload 0 register. That way, the reload 0 and reload 1 registers both are updated synchro- nously with PWM period, from which the timer starts operating. This operation can normally be performed collectively by accessing 32-bit addresses beginning with the reload 1 register address wordwise. (Data are automatically written to the reload 1 and then the reload 0 registers in succession.) If the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have been written to the respective registers, and not the reload values being actually used. When altering PWM period by rewriting the reload registers, if the PWM period terminates before the CPU finishes writing to reload 0, the PWM period is not altered in the current session and the data written to the register is reflected in the next period. When altering PWM period by rewriting the reload registers, if the PWM period terminates before the CPU finishes writing to reload 0, the PWM period is not altered in the current session and the data written to the register is reflected in the next period. When operating in the PWM output mode, writing the reload 0 register and reloard 1 register more than twice within the PWM period and meet the following conditions at the same time, the PWM waveform is output with the value that the last time written reload 0 register and finally written reload 1 register. Condition 1: Start writing reload 0 register after latching the reload 0 register PWM period of the old PWM output period. Condition 2: Rewrite reload 1 register before latching PWM period of the new PWM output period and start writing reload 0 register after latching PWM period. (2) Reload register updates in TIO PWM output mode In PWM output mode, when the timer remains idle, the reload 0 and reload 1 registers are updated at the same time data are written to the respective registers. But when the timer is operating, the reload 1 register is updated by updating the reload 0 register. However, if the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have been written to the respective registers. F/F TO TIOnRL0 TIOnRL1 Internal bus Reload 1 Reload 1 WR Reload 0 WR Reload 1 Buffer 16-bit counterPrescaler output Reload 0 PWM mode control (Note1) Note 1: It is transferd from reload 1 register to reload 1 buffer when reload 0 register is reloaded after updating reload 0 register during counter operation. Figure 10.4.10 PWM Circuit Diagram

10-11532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 To update PWM period correctly, take either one of the following measures.  Identify the completion timing of PWM period by reading counter value at writing reload 1 register and reload 0 register, and then start writing reload 1 register and reload 0 register without crossing PWM period.  When writing to reload 1 register and reload 0 register by using interruption, set the prescaler value of counter as small as possible. By doing this, write to reload 1 register and reload 0 register later than the counter to be H'FFFF in the PWM period.  Writing reload 1 register and reload 0 register is performed under the period, less than one time per PWM period. (Extend the reload register's rewrite period against PWM period.) (3) Notes on using TIO PWM output mode The following describes precautions to be observed when using TIO PWM output mode.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF but changes to "reload register value -1" at the next count clock timing.  Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated before F/F output is inverted after writing to the enable bit. Figure 10.4.11 Update timing of PWM period Count clock Counter H'FFFF H'0000 F/F output Underflow (1st time) Reload 0 register (Note 2) (Note 1) Reload 1 register PWM period (Note 1) Note 1: The value that "the reload 0 register -1" is reloaded. Note 2: The value that "the reload 1 buffer -1" is reloaded. Notes: . : Indicate sampling points. . This diagram does not show detailed timing information. Reload 1 buffer Condition 1 Old PWM output period Condition 2 New PWM putput period Reloading "reload 0 register" (Loading PWM period) Reloading "reload 0 register" (Loading PWM period) Underflow (2nd time) Underflow (2nd time)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.4.12 Reload 0 and Reload 1 Register Updates in PWM Output Mode (a) When reload register updates take effect in the current period (reflected in the next period) Count clock H'FFFF H'7FFF H'8000 Timing at which reload 0 is updated Operation by new reload value written Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (Reload 1 data latched) H'1000 H'2000 H'8000 H'9000 Timing at which PWM period latched and reload 1 buffer is updated. Reload 0 register Reload 1 register Counter Interrupt due to underflow F/F output Reload 1 buffer H'9000 H'1000 H'8000 H'9000 H'0001 H'FFFF H'1000 H'7FFF H'2000 H'8000 H'9000 H'7FFEH'0000 H'2000 H'9000 New PWM output period Old PWM output period Enlarged view New PWM output period Note:  This diagram does not show detailed timing information. H'1000 H'0FFF H'2000 H'8000 H'9000 (b) When reload register updates take effect in the next period (reflected one period later) Operation by old reload value H'1000 H'2000 H'8000 H'9000 H'0FFE H'2000 H'9000 Write to reload 1 Write to reload 0 (Reload 1 data latched) Timing at which reload 0 is updated PWM period latched Count clock Reload 0 register Reload 1 register Counter Interrupt due to underflow Reload 0 register Reload 1 register F/F output F/F output Reload 1 buffer H'1000 H'2000 H'9000 H'0001 H'FFFF H'1000 H'0FFF H'8000 H'9000 H'0FFEH'0000 H'2000 Old PWM output period Old PWM output period Old PWM output period Enlarged view

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10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function)

(1) Outline of TIO single-shot output mode In single-shot output mode, the timer generates a pulse in width of "reload 0 register set value + 1" only once and then stops. When the timer is enabled "by writing to the enable bit in software or by external input "after setting the reload 0 register, the counter is loaded with the content of the "reload 0 register -1" and starts counting synchronously with the count clock at the next cycle. The counter counts down and when the minimum count is reached, stops upon underflow. The F/F output waveform in single-shot output mode is inverted "F/F output level changes from "L" to "H" or vice versa" at startup and upon underflow, generating a single-shot pulse waveform in width of "reload 0 register set value + 1" only once. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) upon underflow of the counter. The count value is "reload 0 register set value + 1." (For counting operation, see also Section 10.3.9, “Operation of TOP Single-shot Output Mode.” ) (2) Notes on using TIO single-shot output mode The following describes precautions to be observed when using TIO single-shot output mode.  If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.  If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated before F/F output is inverted after writing to the enable bit.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 H'FFFF H'0000 H'A000 H'A000 (Note 2) DMA transfer request (Note 1) DMA transfer request due to underflow Count clock Enabled (by writing to the enable bit or by external input) F/F output Disabled (by underflow) (Unused) TIO interrupt request Enable bit Reload 0 register Counter Reload 1 register Undefined value Data inverted by enable Data inverted by underflow TIO interrupt request due to underflow Note 1: Only TIO8 and TIO9 can be generated. Note 2: The value that "reload 0 register - 1" is reloaded. Note:  This diagram does not show detailed timing information. Figure 10.4.13 Typical Operation in TIO Single-shot Output Mode (without Correction Function)

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10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function)

(1) Outline of TIO delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of "reload 0 register set value + 1" after a finite time equal to "counter set value + 1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock. At the cycle after the first counter underflow, it is loaded with "the reload 0 register value -1" and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter underflows first time and next, generating a single-shot pulse wave- form in width of "reload 0 register set value + 1" after a finite time equal to "first set value of counter + 1" only once. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) upon the first and next underflows of the counter. The "counter set value + 1" and "reload 0 register set value + 1" are effective as count values. (For counting operation, see also Section 10.3.10, “Operation of TOP Delayed Single-shot Output Mode.”) (2) Notes on using TIO delayed single-shot output mode The following describes precautions to be observed when using TIO delayed single-shot output mode.  If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.  If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  If the counter is accessed for read ar the cycle of underflow, the counter value is read out as H’FFFF but changes to "reload register value -1" at the next count clock timing.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 H'FFFF H'0000 H'A000 H'F000 H'F000 DMA transfer request due to underflow DMA transfer request due to underflow TIO interrupt request due to underflow TIO interrupt request due to underflow DMA transfer request (Note 1) Underflow (first time) Count down from the counter set value Underflow (second time) Count down from the reload 0 register set value Count clock F/F output (Unused) TIO interrupt request Enable bit Reload 0 register Counter Reload 1 register Enabled (by writing to the enable bit or by external input) Data inverted by underflow Data inverted by underflow (Note 2) Note 1: Only TIO8 and TIO9 can be generated. Note 2: The value that "reload 0 register - 1" is reloaded. Note:  This diagram does not show detailed timing information. Figure 10.4.14 Typical Operation in TIO Delayed Single-shot Output Mode (without Correction Function)

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10.4.14 Operation in TIO Continuous Output Mode (without Correction Function)

(1) Outline of TIO continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and the next cycle when the counter underflows, it is loaded with the value that "the reload 0 register -1." Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose wave- form is inverted in width of "reload 0 register set value + 1." When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. The cycle after this under- flow causes the counter to be loaded with the content of "the reload 0 register -1" and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The timing for reloading to counter is the cycle after underflow. The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8 and TIO9) each time the counter underflows. The "counter set value + 1" and "reload 0 register set value + 1" are effective as count values. (For counting operation, see also Section 10.3.11, “Operation of TOP Continuous Output Mode.”) (2) Notes on using TIO continuous output mode The following describes precautions to be observed when using TIO continuous output mode.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  If the counter is accessed for read at the cycle of underflow, the counter value is read out as H’FFFF but changes to "reload register value -1" at the next count clock timing.  Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated before F/F output is inverted after writing to the enable bit.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 H'FFFF H'0000 H'E000 H'A000 H'E000 H'DFFF H'DFFF Data inverted by enable Data inverted by underflow Data inverted by underflow DMA transfer request (Note 1) DMA transfer request due to underflow TIO interrupt request due to underflow TIO interrupt request due to underflow DMA transfer request due to underflow (Unused) Count clock F/F output TIO interrupt request Enable bit Reload 0 register Counter Reload 1 register Underflow (first time) Count down from the counter set value Underflow (second time) Enabled (by writing to the enable bit or by external input) (Note 2) Note 1: Only TIO8 and TIO9 can be generated. Note 2: The value that "reload 0 register - 1" is reloaded. Note:  This diagram does not show detailed timing information. (Note 2) Figure 10.4.15 Typical Operation in TIO Continuous Output Mode (without Correction Function)

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10.5.1 Outline of TMS

TMS (Timer Measure Small) is an input-related 16-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table below and the diagram in the next page show specifications and a block diagram of TMS, respec- tively. Table 10.5.1 Specifications of TMS (Input-Related 16-Bit Timer) Item Specification Number of channels 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) Counter 16-bit up-counter × 2 Measure register 16-bit measure register × 8 Timer startup Started by writing to the enable bit in software Interrupt request generation Can be generated by a counter overflow

10.5.2 Outline of TMS Operation

In TMS, when the timer is enabled (by writing to the enable bit in software), the counter starts operating. The counter is a 16-bit up-counter, where when a measure signal is entered from an external device, the counter value is latched into each measure register. The counter stops counting at the same time count is disabled by writing to the enable bit in software. TIN and TMS interrupt requests can be generated by external measure signal input and counter overflow, respectively.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 3 2 1 0 3 2 1 0 clk TMS 0 S ovf cap3 cap2 cap1 cap0 S S S S TCLK3 (P127) TCLK3S S S S S S TIN16S TIN17S TIN16 (P130) TIN17 (P131) TIN18STIN18 (P132) TIN19STIN19 (P133) DMA2 IRQ10 IRQ10 IRQ10 IRQ10 0 1 2 3 IRQ7 S 3 2 1 0 3 2 1 0 0 1 2 3 clk TMS 1 ovf cap3 cap2 cap1 cap0 IRQ7 DMA4 Clock bus Input event bus Output event bus : Selector Measure register 3Counter (16-bit) Counter (16-bit) Measure register 2 Measure register 1 Measure register 0 Measure register 3 Measure register 2 Measure register 1 Measure register 0 Figure 10.5.1 Block Diagram of TMS (Input-Related 16-Bit Timer)

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10.5.3 TMS Related Register Map

Shown below is a TMS related register map. TMS Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 03C0 TMS0 Counter 10-127 (TMS0CT) H'0080 03C2 TMS0 Measure 3 Register 10-127 (TMS0MR3) H'0080 03C4 TMS0 Measure 2 Register 10-127 (TMS0MR2) H'0080 03C6 TMS0 Measure 1 Register 10-127 (TMS0MR1) H'0080 03C8 TMS0 Measure 0 Register 10-127 (TMS0MR0) H'0080 03CA TMS0 Control Register TMS1 Control Register 10-126 (TMS0CR) (TMS1CR) (Use inhibited area) H'0080 03D0 TMS1 Counter 10-127 (TMS1CT) H'0080 03D2 TMS1 Measure 3 Register 10-127 (TMS1MR3) H'0080 03D4 TMS1 Measure 2 Register 10-127 (TMS1MR2) H'0080 03D6 TMS1 Measure 1 Register 10-127 (TMS1MR1) H'0080 03D8 TMS1 Measure 0 Register 10-127 (TMS1MR0) <Count clock-dependent delay>

• Because the timer operates synchronously with the count clock, there is a count clock-dependent delay from when the timer is enabled till when it actually starts operating. Figure 10.5.2 Count Clock-Dependent Delay BCLK Count clock Enable Count clock period Count clock-dependent delay Write to the enable bit

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 8 9 1 01 11 21 31 4 b 1 5 TMS1SS0 TMS1SS1 TMS1SS2 TMS1SS3 TMS1CKS TMS1CEN 00000000 b 0 123456 b 7 TMS0SS0 TMS0SS1 TMS0SS2 TMS0SS3 TMS0CKS TMS0CEN 00000000

10.5.4 TMS Control Registers

The TMS control registers are used to select TMS0/1 input events and count clock sources, as well as control count enable. Following two TMS control registers are included:  TMS0 Control Register (TMS0CR)  TMS1 Control Register (TMS1CR) TMS0 Control Register (TMS0CR) <Address: H’0080 03CA> <Upon exiting reset: H’00> b Bit Name Function R W

0 TMS0SS0 0: Does not use measure input source R W

TMS0 measure 0 source select bit 1: Input event bus 0

1 TMS0SS1 0: Does not use measure input source R W

TMS0 measure 1 source select bit 1: Input event bus 1

2 TMS0SS2 0: Does not use measure input source R W

TMS0 measure 2 source select bit 1: Input event bus 2

3 TMS0SS3 0: Does not use measure input source R W

TMS0 measure 3 source select bit 1: Input event bus 3 4, 5 TMS0CKS 00: External input TCLK3 R W TMS0 clock source select bit 01: Clock bus 0 10: Clock bus 1 11: Clock bus 3 6 No function assigned. Fix to "0." 00

7 TMS0CEN 0: Stop count R W

TMS0 count enable bit 1: Start count TMS1 Control Register (TMS1CR) <Address: H’0080 03CB> <Upon exiting reset: H’00> b Bit Name Function R W

8 TMS1SS0 0: External input TIN19 R W

TMS1 measure 0 source select bit 1: Input event bus 0

9 TMS1SS1 0: External input TIN18 R W

TMS1 measure 1 source select bit 1: Input event bus 1

10 TMS1SS2 0: External input TIN17 R W

TMS1 measure 2 source select bit 1: Input event bus 2

11 TMS1SS3 0: External input TIN16 R W

TMS1 measure 3 source select bit 1: Input event bus 3 12 No function assigned. Fix to "0." 00

13 TMS1CKS 0: Clock bus 0 R W

TMS1 clock source select bit 1: Clock bus 3 14 No function assigned. Fix to "0." 00

15 TMS1CEN 0: Stop count R W

TMS1 count enable bit 1: Start count

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10.5.5 TMS Counters (TMS0CT, TMS1CT)

TMS0 Counter (TMS0CT) <Address: H’0080 03C0> TMS1 Counter (TMS1CT) <Address: H’0080 03D0> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TMS0CT, TMS1CT 16-bit counter value R W Note:  These registers must always be accessed in halfwords. The TMS counters are a 16-bit up-counter, which starts counting when the timer is enabled (by writing to the enable bit in software). The counters can be read on-the-fly.

10.5.6 TMS Measure Registers (TMS0MR3–0, TMS1MR3–0)

TMS0 Measure 3 Register (TMS0MR3) <Address: H’0080 03C2> TMS0 Measure 2 Register (TMS0MR2) <Address: H’0080 03C4> TMS0 Measure 1 Register (TMS0MR1) <Address: H’0080 03C6> TMS0 Measure 0 Register (TMS0MR0) <Address: H’0080 03C8> TMS1 Measure 3 Register (TMS1MR3) <Address: H’0080 03D2> TMS1 Measure 2 Register (TMS1MR2) <Address: H’0080 03D4> TMS1 Measure 1 Register (TMS1MR1) <Address: H’0080 03D6> TMS1 Measure 0 Register (TMS1MR0) <Address: H’0080 03D8> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TMS0MR3-TMS0MR0 16-bit measured value R – TMS1MR3-TMS1MR0 Notes:  These registers are a read-only register.  These registers can be accessed in either byte or halfword. The TMS measure registers are used to latch counter contents upon event input. The TMS measure registers are a read-only register. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TMS0MR3–TMS0MR0 , TMS1MR3–TMS1MR0 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TMS0CT, TMS1CT

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.5.7 Operation of TMS Measure Input

(1) Outline of TMS measure input In TMS measure input, when the timer is enabled (by writing to the enable bit in software), it starts counting up synchronously with the count clock. Then when event input to TMS is detected while the timer is operat- ing, the counter value is latched into measure registers 0–3. The timer stops counting at the same time count is disabled by writing to the enable bit. A TIN interrupt request can be generated by measure signal input from an external device. A TMS interrupt request can be generated when the counter overflows. Count clock Counter H'FFFF H'0000 Enabled (by writing to the enable bit) Measure event 1 occurs Undefined Enable bit Note:  This diagram does not show detailed timing information. Measure 0 register H'8000 Overflow occurs TIN19 interrupt request H'C000 Measure 1 register TIN18 interrupt request Measure event 0 occurs TMS interrupt request due to overflow H'6000 H'D000 H'6000H'8000 Undefined value Undefined H'D000H'C000 Measure event 1 occurs Measure event 0 occurs Figure 10.5.3 Typical Operation of TMS Measure Input (2) Notes on using TMS measure input The following describes precautions to be observed when using TMS measure input.  If measure event input and write to the counter occur in the same clock period, the write value is set in the counter while at the same time latched into the measure register.

10-12932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.6.1 Block Diagram of TML (Input-Related 32-Bit Timer) 3 2 1 0 3 2 1 0 S S S S TIN20S TIN21S TIN20 (P134) TIN21 (P135) TIN22STIN22 (P136) TIN23STIN23 (P137) IRQ11 IRQ11 IRQ11 IRQ11 0 1 2 3 S 3 2 1 0 3 2 1 0 0 1 2 3 clk TML0 cap3 cap2 cap1 cap0 S S S S S TIN30S TIN31S TIN30 (P34) TIN31 (P35) TIN32STIN32 (P36) TIN33STIN33 (P37) IRQ18 IRQ18 IRQ18 IRQ18 clk TML1 cap3 cap2 cap1 cap0 S DMA5 DMA common AD0TRG Clock bus Input event bus Output event bus : Selector Measure register 3Counter (32-bit) Measure register 2 Measure register 1 Measure register 0 Measure register 3 Measure register 2 Measure register 1 Measure register 0 Counter (32-bit) BCLK

10.6.1 Outline of TML

TML (Timer Measure Large) is an input-related 32-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table and diagram below show specifications and a block diagram of TML, respectively. Table 10.6.1 Specifications of TML (Input-Related 32-Bit Timer) Item Specification Number of channels 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) Input clock BCLK/4 (10.0 MHz when f(BCLK) = 40 MHz), BCLK/2 (20.0 MHz when f(BCLK) = 40 MHz) or clock bus 1 input Counter 32-bit up-counter × 2 Measure register 32-bit measure register × 8 Timer startup Start counting after exiting the reset state

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.6.2 Outline of TML Operation

In TML, the timer starts counting upon deassertion of the reset input signal. The counter included in the timer is a 32-bit up-counter, where when a measure event signal is entered from an external device, the counter value at that point in time is stored in each 32-bit measure register. When the reset input signal is deasserted, the counter starts operating with a BCLK/4 clock, and cannot be stopped once it has started. The counter is idle only when the microcomputer remains reset. A TIN interrupt request can be generated by external measure signal input. However, no TML counter overflow interrupts are available.

10.6.3 TML Related Register Map

Shown below is a TML related register map. TML Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 03E0 TML0 Counter (Upper) 10-132 (TML0CT) (TML0CTH) H'0080 03E2 (Lower) (TML0CTL) (Use inhibited area) H'0080 03EA (Use inhibited area) TML0 Control Register 10-131 (TML0CR) (Use inhibited area) H'0080 03F0 TML0 Measure 3 Register (Upper) 10-132 (TML0MR3) (TML0MR3H) H'0080 03F2 (Lower) (TML0MR3L) H'0080 03F4 TML0 Measure 2 Register (Upper) 10-132 (TML0MR2) (TML0MR2H) H'0080 03F6 (Lower) (TML0MR2L) H'0080 03F8 TML0 Measure 1 Register (Upper) 10-132 (TML0MR1) (TML0MR1H) H'0080 03FA (Lower) (TML0MR1L) H'0080 03FC TML0 Measure 0 Register (Upper) 10-132 (TML0MR0) (TML0MR0H) H'0080 03FE (Lower) (TML0MR0L) H'0080 0FE0 TML1 Counter (Upper) 10-132 (TML1CT) (TML1CTH) H'0080 0FE2 (Lower) (TML1CTL) (Use inhibited area) H'0080 0FEA (Use inhibited area) TML1 Control Register 10-131 (TML1CR) (Use inhibited area) H'0080 0FF0 TML1 Measure 3 Register (Upper) 10-132 (TML1MR3) (TML1MR3H) H'0080 0FF2 (Lower) (TML1MR3L) H'0080 0FF4 TML1 Measure 2 Register (Upper) 10-132 (TML1MR2) (TML1MR2H) H'0080 0FF6 (Lower) (TML1MR2L) H'0080 0FF8 TML1 Measure 1 Register (Upper) 10-132 (TML1MR1) (TML1MR1H) H'0080 0FFA (Lower) (TML1MR1L) H'0080 0FFC TML1 Measure 0 Register (Upper) 10-132 (TML1MR0) (TML1MR0H) H'0080 0FFE (Lower) (TML1MR0L)

10-13132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 8 9 1 01 11 21 31 4 b 1 5 TML0SS0 TML0SS1 TML0SS2 TML0SS3 TML0CKS 00000000 b 8 9 1 01 11 21 31 4 b 1 5 TML1SS0 TML1SS1 TML1SS2 TML1SS3 TML1CKS 00000000

10.6.4 TML Control Registers

TML0 Control Register (TML0CR) <Address: H’0080 03EB> <Upon exiting reset: H’00> b Bit Name Function R W

8 TML0SS0 0: External input TIN23 R W

TML0 measure 0 source select bit 1: Input event bus 0

9 TML0SS1 0: External input TIN22 R W

TML0 measure 1 source select bit 1: Input event bus 1

10 TML0SS2 0: External input TIN21 R W

TML0 measure 2 source select bit 1: Input event bus 2

11 TML0SS3 0: External input TIN20 R W

TML0 measure 3 source select bit 1: Input event bus 3 12–14 No function assigned. Fix to "0." 00

15 TML0CKS 0: BCLK/2 or BCLK/4 (Note 1) R W

TML0 clock source select bit 1: Clock bus 1 Note 1: To select BCLK/2 or BCLK/4, use the PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit. For details, refer to Section 10.2.2, “Common Count Clock Select Function.” TML1 Control Register (TML1CR) <Address: H’0080 0FEB> <Upon exiting reset: H’00> b Bit Name Function R W

8 TML1SS0 0: External input TIN33 R W

TML1 measure 0 source select bit 1: Input event bus 0

9 TML1SS1 0: External input TIN32 R W

TML1 measure 1 source select bit 1: Input event bus 1

10 TML1SS2 0: External input TIN31 R W

TML1 measure 2 source select bit 1: Input event bus 2

11 TML1SS3 0: External input TIN30 R W

TML1 measure 3 source select bit 1: Input event bus 3 12–14 No function assigned. Fix to "0." 00

15 TML1CKS 0: BCLK/2 or BCLK/4 (Note 1) R W

TML1 clock source select bit 1: Clock bus 1 Note 1: To select BCLK/2 or BCLK/4, use the PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit. For details, refer to Section 10.2.2, “Common Count Clock Select Function.” The TML control register is used to select TML input event and count clock.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.6.5 TML Counters

TML0 Counter (TML0CT) <Address: H’0080 03E0> TML1 Counter (TML1CT) <Address: H’0080 0FE0> <Upon exiting reset: Undefined> b Bit Name Function R W 0–31 TML0CT 32-bit counter value R W Note:  These registers must always be accessed wordwise (in 32 bits) beginning with the word boundary (low-order address B'00). The TML counters are a 32-bit up-counter, which starts counting upon deassertion of the reset input signal. The counters can be read during operation.

10.6.6 TML Measure Registers

TML0 Measure 3 Register (TML0MR3) <Address: H’0080 03F0> TML0 Measure 2 Register (TML0MR2) <Address: H’0080 03F4> TML0 Measure 1 Register (TML0MR1) <Address: H’0080 03F8> TML0 Measure 0 Register (TML0MR0) <Address: H’0080 03FC> TML1 Measure 3 Register (TML1MR3) <Address: H’0080 0FF0> TML1 Measure 2 Register (TML1MR2) <Address: H’0080 0FF4> TML1 Measure 1 Register (TML1MR1) <Address: H’0080 0FF8> TML1 Measure 0 Register (TML1MR0) <Address: H’0080 0FFC> <Upon exiting reset: Undefined> b Bit Name Function R W 0–31 TML0MR3–TML0MR0, TML1MR3–TML1MR0 32-bit measure register value R – Notes:  These registers are a read-only register.  These registers must always be accessed wordwise (in 32 bits) beginning with the word boundary (low-order address B'00). The TML measure registers are a 32-bit register, which is used to latch the counter content upon event input. The TML measure registers can only be read, and cannot be written to. b16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b31 (16 low-order bits) b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TML0CT, TML1CT (16 high-order bits) b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TML0MR3-TML0MR0,TML1MR3-TML1MR0 (16 high-order bits) b16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b31 (16 low-order bits)

10-13332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.6.7 Operation of TML Measure Input

(1) Outline of TML measure input In TML measure input, when the reset input signal is deasserted, the counter starts counting up synchro- nously with the count clock. Upon event input to measure registers 0–3, the counter value is latched into each measure register. A TIN interrupt request can be generated by measure signal input from an external device. However, no TML counter overflow interrupts are available. Figure 10.6.2 Typical Operation of TML Measure Input Count clock Counter (32-bit) H'FFFF FFFF H'0000 0000 Enabled (by deassertion of reset) Undefined Reset Note: • This diagram does not show detailed timing information. Measure 0 register Overflow occurs TIN23 interrupt request Measure 1 register TIN22 interrupt request Measure event 0 occurs H'8000 0000 H'C000 0000 H'8000 0000 H'6000 0000 H'6000 0000 H'D000 0000 Undefined value Undefined H'C000 0000 H'D000 0000 Measure event 1 occurs Measure event 0 occurs Measure event 1 occurs

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) Notes on using TML measure input The following describes precautions to be observed when using TML measure input.  If measure event input and write to the counter occur in the same clock period, the write value is set in the counter, whereas the up-count value (before being rewritten) is latched into the measure register.  If clock bus 1 is selected and any clock other than BCLK/2 or BCLK/4 (Note 1) is used for the timer, by divided by internal prescaler PRS1, the value captured into the measure register is one count larger the counter value. During the count clock to BCLK/2 or BCLK/4 (Note 1) period interval, however, the cap- tured value is exactly the counter value. The diagram below shows the relationship between counter operation and the valid data that can be captured. Note 1: To select BCLK/2 or BCLK/4, use the PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit. For details, refer to Section 10.2.2, “Common Count Clock Select Function.” Counter BAC D E F A BCDE  When BCLK/2 or BCLK/4 is selected (Note 1) BCLK/2 or BCLK/4 (Note 1) BCLK/2 or BCLK/4 (Note 1) Captured Counter BAC  When clock bus 1 is selected Count clock Captured BC D F Note 1: To select BCLK/2 or BCLK/4, use the PRS012CKS (prescaler 0-2, TML0,1 supplied clock select) bit. For details, refer to Section 10.2.2, "Common Count Clock Select Function." Figure 10.6.3 Mistimed Counter Value and the Captured Value

10 10.7 TID (Input-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-13532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.7.1 Outline of TID

TID (Timer Input Derivation) is an input-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time:

• Fixed period count mode  Event count mode  Multiply-by-4 event count mode  Up/down event count mode The table below and the diagram in the next page show specifications and a block diagram of TID, respectively. Table 10.7.1 Specifications of TID (Input-Related 16-Bit Timer) Item Specification Number of channels 2 channels Counter 16-bit up/down-counter Reload register 16-bit reload register Timer startup Started by writing to the enable bit in software Operation mode <Input modes>  Fixed period count mode  Event count mode  Multiply-by-4 event count mode  Up/down event count mode Interrupt request generation Can be generated by counter underflow and overflow DMA transfer request generation Can be generated by counter underflow and overflow

10 10.7 TID (Input-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-13732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.7.2 TID Related Register Map

Shown below is a TID related register map. TID Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 078C TID0 Counter 10-140 (TID0CT) H'0080 078E TID0 Reload Register 10-140 (TID0RL) H'0080 07D0 TID0 Control & Prescaler 3 Enable Register 10-138 (TID0PRS3EN) H'0080 0B8C TID1 Counter 10-140 (TID1CT) H'0080 0B8E TID1 Reload Register 10-140 (TID1RL) H'0080 0BD0 TID1 Control & Prescaler 4 Enable Register 10-139 (TID1PRS4EN)

10 10.7 TID (Input-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.7.3 TID Control & Prescaler Enable Registers

TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) <Address: H’0080 07D1> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 TID0M 000: Fixed period count mode R W TID0 operation mode select bit 001: Fixed period count mode 010: Multiply-by-4 event count mode 011: Event count mode 100: Fixed period count mode 101: Fixed period count mode 110: Multiply-by-4 event count mode 111: Up/down event count mode

11 TID0CEN 0: Stop TID0 count R W

TID0 count enable bit 1: Start TID0 count 12–14 TOU0ENS 000: Disable event enable R W TOU0 enable source select bit 001: Disable event enable 010: TID0 underflow/overflow 011: TOU0_7 underflow 100: Disable event enable 101: Disable event enable 110: Output event bus 0 111: External input TIN25 signal

15 PRS3EN 0: Stop prescaler 3 count R W

Prescaler 3 enable bit 1: Start prescaler 3 count Note:  Operation mode can only be set or changed while the counter is inactive. The TID0 Control & Prescaler 3 Enable Register is used to select TID0 operation mode (Fixed period count, Event count, Multiply-by-4 event count or Up/down event count mode), as well as select TOU0_0–7 timer enable sources and control prescaler 3 startup. b 8 9 1 01 11 21 31 4 b 1 5 TID0M TID0CEN TOU0ENS PRS3EN 00000000

10 10.7 TID (Input-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-13932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) <Address: H’0080 0BD1> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 TID1M 000: Fixed period count mode R W TID1 operation mode select bit 001: Fixed period count mode 010: Multiply-by-4 event count mode 011: Event count mode 100: Fixed period count mode 101: Fixed period count mode 110: Multiply-by-4 event count mode 111: Up/down event count mode

11 TID1CEN 0: Stop TID1 count R W

TID1 count enable bit 1: Start TID1 count 12–14 TOU1ENS 000: Disable event enable R W TOU1 enable source select bit 001: Disable event enable 010: TID1 underflow/overflow 011: TOU1_7 underflow 100: Disable event enable 101: Disable event enable 110: TOU0 startup source (Note 1) (The enable source selected by TOU0ENS) 111: External input TIN27 signal

15 PRS4EN 0: Stop prescaler 4 count R W

Prescaler 4 enable bit 1: Start prescaler 4 count Note 1: Any event must be selected using the TOU0 enable source select bit. Note:  Operation mode can only be set or changed while the counter is inactive. The TID1 Control & Prescaler 4 Enable Register is used to select TID1 operation mode (Fixed period count, Event count, Multiply-by-4 event count or Up/down event count mode), as well as select TOU1_0–7 timer enable sources and control prescaler 4 startup. b 8 9 1 01 11 21 31 4 b 1 5 TID1M TID1CEN T0U1ENS PRS4EN 00000000

10 10.7 TID (Input-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.7.4 TID Counters (TID0CT and TID1CT)

TID0 Counter (TID0CT) <Address: H’0080 078C> TID1 Counter (TID1CT) <Address: H’0080 0B8C> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TID0CT, TID1CT 16-bit counter value R W Note:  These registers must always be accessed in halfwords. The TID counters are a 16-bit up/down-counter. After the timer is enabled (by writing to the enable bit in software), the counter starts counting synchronously with the count clock.

10.7.5 TID Reload Registers (TID0RL and TID1RL)

TID0 Reload Register (TID0RL) <Address: H’0080 078E> TID1 Reload Register (TID1RL) <Address: H’0080 0B8E> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TID0RL,TID1RL 16-bit reload register value R W Note:  These registers must always be accessed in halfwords. The TID reload registers are used to reload data into the TID counter registers (TID0CT and TID1CT). The content of "the reload register -1" is loaded into the counter synchronously with the count clock in the following timing:  At the next cycle when the counter is enabled in fixed period count mode  At the next cycle when the counter has underflowed in fixed period count mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TID0CT, TID1CT b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TID0RL, TID1RL

10 10.7 TID (Input-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-14132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.7.6 Outline of Each Mode of TID

Each mode of TID is outlined below. TID modes can be selected from the following, only one at a time. (1) Fixed period count mode In fixed period count mode, the timer uses a reload register to generate an interrupt request at intervals of "reload register set value + 1." Note:  TINn cannot be used as a clock source. When the timer is enabled (by writing to the enable bit in software) after setting the reload register (initial value being undefined), the counter is loaded with the content of "the reload register -1" and starts counting synchronously with the count clock at the next cycle. The counter counts down and when it underflows after reaching the minimum count, the counter is loaded with the content of "the reload register -1" and continues counting. To stop the counter, disable count by writing to the enable bit in software. An interrupt request and a DMA transfer request can be generated each time the counter underflows. The "reload register set value + 1" is effective as count value. H'(E000-1) Count clock Counter Enabled (by writing to the enable bit) Underflow (first time) TID0 interrupt request due to underflow Enable bit Reload register Underflow (second time) Undefined value DMA transfer request due to underflow (Note 1) Note 1: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. (Note 1) (Note 1) H'FFFF H'0000 H'E000 Counter Figure 10.7.3 Typical Operation in TID Fixed Period Count Mode

10 10.7 TID (Input-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-14332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (3) Multiply-by-4 event count mode In multiply-by-4 event count mode, the timer uses two external input signals in pairs (TIN24 and TIN25 or TIN26 and TIN27) as the clock sources for the counter. The count direction is switched between up-count and down-count depending on the status of the two input signals. By detecting the rising and falling edges on both of the two external input signals, the timer generates clock pulses synchronized to the microcomputer’s internal clock. When after setting the counter the timer is en- abled (by writing to the enable bit in software), the counter starts counting synchronously with the generated clock. To know whether the counter counts up or counts down, see Table 10.7.2 below. An interrupt request and a DMA transfer request can be generated when the counter underflows or overflows. To stop the counter, disable count by writing to the enable bit in software or fix the external input signals either "H" or "L." Table 10.7.2 Count Direction during Multiply-by-4 Event Count Mode TIN24 (TIN26) TIN25 (TIN27) Input H H L L H L L H Up-count Down-count Count Direction

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.1 Outline of TOU

TOU (Timer Output Unification) is an output-related 24-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time. <Output modes without correction function>

• PWM output mode
• Single-shot PWM output mode
• Delayed single-shot output mode
• Single-shot output mode
• Continuous output mode The table below and the diagram in the next page show specifications and a block diagram of TOU, respectively. Table 10.8.1 Specifications of TOU (Output-Related 24-Bit Timer) Item Specification Number of channels 16 channels (8 channels × 2 circuit blocks) Counter 24-bit down-counter (or 16-bit down counter when in PWM output or single-shot PWM output mode) Reload register 24-bit reload register (or 16-bit reload register when in PWM output or single-shot PWM output mode) Timer startup TOU0:
• Writing to the enable bit in software
• TID0 underflow/overflow signal
• TOU0_7 underflow signal
• Output event bus 0 signal
• External input TIN25 signal TOU1:
• Writing to the enable bit in software
• TID1 underflow/overflow signal
• TOU1_7 underflow signal
• TOU0 cause of start signal (Event enable must be selected by TOU0)
• External input TIN27 signal Mode switching <Output modes without correction function>
• PWM output mode
• Single-shot PWM output mode
• Delayed single-shot output mode
• Single-shot output mode
• Continuous output mode Interrupt request generation Can be generated by a counter underflow DMA transfer request generation Can be generated by a counter underflow

10-14732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TIN16/PWMOFF0 (P130) TIN24 (P103) TIN25 (P104) TIN17/PWMOFF1 (P131) TIN26 (P73) TIN27 (P72) TO21 (P00/P87) TO22 (P01/P86) TO23 (P02/P85) TO24 (P03/P84) TO25 (P04/P83) TO26 (P05/P82) TO27 (P06/P175) TO28 (P07/P174) TO29 (P10/P110) TO30 (P11/P111) TO31 (P12/P112) TO32 (P13/P113) TO33 (P14/P114) TO34 (P15/P115) TO35 (P16/P116) TO36 (P17/P117) IRQ11 IRQ11 IRQ11 IRQ11 DMA5 DMA6 DMA7 DMA8 DMA9 DMA0 DMA4 DMA1 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ14 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ15 BCLK BCLK DMA3 DMA1 DMA0 TOU0_0 (24-bit)clk en udf TOU0_1 (24-bit)clk en udf TOU0_2 (24-bit)clk en udf TOU0_3 (24-bit)clk en udf TOU0_4 (24-bit)clk en udf TOU0_5 (24-bit)clk en udf TOU0_6 (24-bit)clk en udf TOU0_7 (24-bit)clk en udf TID 0clk CLK1 CLK2 ovf udf TOU1_0 (24-bit)clk en udf TOU1_1 (24-bit)clk en udf TOU1_2 (24-bit)clk en udf TOU1_3 (24-bit)clk en udf TOU1_4 (24-bit)clk en udf TOU1_5 (24-bit)clk en udf TOU1_6 (24-bit)clk en udf TOU1_7 (24-bit)clk en udf TID 1clk CLK1 CLK2 ovf udf TIN25S PWMOFF1S PWMOFF0S PO1DIS PO0DIS TIN24S PRS3 F/F29 F/F30 F/F31 F/F32 F/F33 F/F34 F/F35 F/F36 F/F21 F/F22 F/F23 F/F24 F/F25 F/F26 F/F27 F/F28S TIN27S TIN26S PRS4 S S S Output event bus Figure 10.8.1 Block Diagram of TOU (Output-Related 24-Bit Timer)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.2 Outline of Each Mode of TOU

Each mode of TOU is outlined below. Modes on each TOU channel can be selected from the following, only one at a time. (1) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. During PWM output mode, the timer operates as a 16-bit timer. When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the value that "the reload 0 register -1" and starts counting down synchronously with the count clock. At the cycle after first time the counter underflows, it is loaded with the contents that "the reload 1 register -1" and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The "reload 0 register set value + 1" and "reload 1 register set value + 1" respectively are effective as count values. Stopping timer and count disable writing to enable bit occur at same time.(Stopping time is not synchronized with PWM output period.) The F/F output waveform in PWM output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter starts counting and each time it underflows. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). An interrupt request and DMA transfer request can be generated at even-numbered occurrences of under- flow after the counter is enabled. (2) Single-shot PWM output mode (without correction function) In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle only once. During PWM output mode, the timer operates as a 16-bit timer. When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts counting down synchronously with the count clock. At the cycle after the first time the counter underflows, it is loaded with the value that "the reload 1 register -1" and continues counting. The counter stops when it underflows next time. The "reload 0 register set value + 1" and "reload 1 register set value + 1" respectively are effective as count values. The timer can be stopped in software, in which case it stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in single-shot PWM output mode is inverted (F/F output level changes from "L" to "H" or vice versa) each time the counter underflows. (Unlike in PWM output mode, the F/F output is not inverted when the counter is enabled.) An interrupt request and DMA transfer request can be generated when the counter underflows second time after being enabled. (3) Delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of "reload register set value + 1" after a finite time equal to "counter set value + 1" only once and then stops. When the timer is enabled after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. At the cycle after the first time the counter underflows, it is loaded with the value that "the reload register -1" and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of "reload register set value + 1" after a finite time equal to "first set value of counter + 1" only once. An interrupt request and DMA transfer request can be generated when the counter underflows first time and next.

10-14932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 BCLK Count clock Enable F/F operation (Note 1) Count clock period Count clock-dependent delay Write to the enable bit Note 1: This applies to the case where F/F output is inverted when the timer is enabled. Inverted Figure 10.8.2 Count Clock Dependent Delay (4) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of "reload register set value + 1" only once and then stops. When the timer is enabled after setting the reload register, the counter is loaded with the content of "the reload register -1" and starts counting synchronously with the count clock at the next cycle. The counter counts down and when the minimum count is reached, stops upon underflow. The F/F output waveform in single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of "reload register set value + 1" only once. An interrupt request and DMA transfer request can be generated when the counter underflows. (5) Continuous output mode (without correction function) In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the value that the reload register. Thereafter, this operation is repeated each time the counter underflows, thus generating inverted consecutive pulses in width of "reload register set value + 1." When the timer is enabled after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. At the cycle after this underflow causes the counter to be loaded with the content of "the reload register -1" and start counting over again at the next cycle. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request and DMA transfer request can be generated each time the counter underflows. <Count clock-dependent delay>

• Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated by the time when the timer actually starts operating after writing the enable bit. In operation mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is inverted.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.3 TOU Related Register Map

Shown below is a TOU related register map. TOU Related Register Map (1/3) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0520 PWM Output 0 Disable Control Register GA PWM Output 0 Disable Level Control Register GA 10-168 (PO0DISGACR) (PO0LVGACR) 10-171 H'0080 0522 PWM Output 1 Disable Control Register GA PWM Output 1 Disable Level Control Register GA 10-168 (PO1DISGACR) (PO1LVGACR) 10-171 H'0080 0524 (Use inhibited area) H'0080 0526 PWMOFF 0 Function Enable Register PWMOFF 1 Function Enable Register 10-173 (PWMOFF0EN) (PWMOFF1EN) H'0080 0780 PWM Output 0 Disable Control Register GB PWM Output 0 Disable Level Control Register GB 10-168 (PO0DISGBCR) (PO0LVGBCR) 10-171 H'0080 0782 PWM Output 1 Disable Control Register GB PWM Output 1 Disable Level Control Register GB 10-169 (PO1DISGBCR) (PO1LVGBCR) 10-171 H'0080 0790 TOU0_0 Counter (Upper) 10-157 (TOU00CTW) (TOU00CTH) H'0080 0792 (Lower) 10-159 (TOU00CT) H'0080 0794 TOU0_0 Reload Register TOU0_0 Reload 1 Register 10-160 (TOU00RLW) (TOU00RL1) 10-162 H'0080 0796 TOU0_0 Reload 0 Register 10-161 (TOU00RL0) H'0080 0798 TOU0_1 Counter (Upper) 10-157 (TOU01CTW) (TOU01CTH) H'0080 079A (Lower) 10-159 (TOU01CT) H'0080 079C TOU0_1 Reload Register TOU0_1 Reload 1 Register 10-160 (TOU01RLW) (TOU01RL1) 10-162 H'0080 079E TOU0_1 Reload 0 Register 10-161 (TOU01RL0) H'0080 07A0 TOU0_2 Counter (Upper) 10-157 (TOU02CTW) (TOU02CTH) H'0080 07A2 (Lower) 10-159 (TOU02CT) H'0080 07A4 TOU0_2 Reload Register TOU0_2 Reload 1 Register 10-160 (TOU02RLW) (TOU02RL1) 10-162 H'0080 07A6 TOU0_2 Reload 0 Register 10-161 (TOU02RL0) H'0080 07A8 TOU0_3 Counter (Upper) 10-157 (TOU03CTW) (TOU03CTH) H'0080 07AA (Lower) 10-159 (TOU03CT) H'0080 07AC TOU0_3 Reload Register TOU0_3 Reload 1 Register 10-160 (TOU03RLW) (TOU03RL1) 10-162 H'0080 07AE TOU0_3 Reload 0 Register 10-161 (TOU03RL0) H'0080 07B0 TOU0_4 Counter (Upper) 10-157 (TOU04CTW) (TOU04CTH) H'0080 07B2 (Lower) 10-159 (TOU04CT) H'0080 07B4 TOU0_4 Reload Register TOU0_4 Reload 1 Register 10-160 (TOU04RLW) (TOU04RL1) 10-162 H'0080 07B6 TOU0_4 Reload 0 Register 10-161 (TOU04RL0)

10-15132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TOU Related Register Map (2/3) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 07B8 TOU0_5 Counter (Upper) 10-157 (TOU05CTW) (TOU05CTH) H'0080 07BA (Lower) 10-159 (TOU05CT) H'0080 07BC TOU0_5 Reload Register TOU0_5 Reload 1 Register 10-160 (TOU05RLW) (TOU05RL1) 10-162 H'0080 07BE TOU0_5 Reload 0 Register 10-161 (TOU05RL0) H'0080 07C0 TOU0_6 Counter (Upper) 10-157 (TOU06CTW) (TOU06CTH) H'0080 07C2 (Lower) 10-159 (TOU06CT) H'0080 07C4 TOU0_6 Reload Register TOU0_6 Reload 1 Register 10-160 (TOU06RLW) (TOU06RL1) 10-162 H'0080 07C6 TOU0_6 Reload 0 Register 10-161 (TOU06RL0) H'0080 07C8 TOU0_7 Counter (Upper) 10-157 (TOU07CTW) (TOU07CTH) H'0080 07CA (Lower) 10-159 (TOU07CT) H'0080 07CC TOU0_7 Reload Register TOU0_7 Reload 1 Register 10-160 (TOU07RLW) (TOU07RL1) 10-162 H'0080 07CE TOU0_7 Reload 0 Register 10-161 (TOU07RL0) H'0080 07D4 Shorting Prevention Function F/F21–26 Protect Register 10-155 (SHFF2126P) H'0080 07D6 Shorting Prevention Function F/F21–26 Data Register 10-156 (SHFF2126D) H'0080 07D8 TOU0 Control Register 1 10-153 (TOU0CR1) H'0080 07DA TOU0 Control Register 0 10-153 (TOU0CR0) H'0080 07DC (Use inhibited area) TOU0 Enable Protect Register 10-163 (TOU0PRO) H'0080 07DE (Use inhibited area) TOU0 Count Enable Register 10-164 (TOU0CEN) H'0080 07E0 PWMOFF0 Input Processing Control Register 10-166 (PWMOFF0CR) H'0080 0B90 TOU1_0 Counter (Upper) 10-157 (TOU10CTW) (TOU10CTH) H'0080 0B92 (Lower) 10-159 (TOU10CT) H'0080 0B94 TOU1_0 Reload Register TOU1_0 Reload 1 Register 10-160 (TOU10RLW) (TOU10RL1) 10-162 H'0080 0B96 TOU1_0 Reload 0 Register 10-161 (TOU10RL0) H'0080 0B98 TOU1_1 Counter (Upper) 10-157 (TOU11CTW) (TOU11CTH) H'0080 0B9A (Lower) 10-159 (TOU11CT) H'0080 0B9C TOU1_1 Reload Register TOU1_1 Reload 1 Register 10-160 (TOU11RLW) (TOU11RL1) 10-162 H'0080 0B9E TOU1_1 Reload 0 Register 10-161 (TOU11RL0)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TOU Related Register Map (3/3) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0BA0 TOU1_2 Counter (Upper) 10-157 (TOU12CTW) (TOU12CTH) H'0080 0BA2 (Lower) 10-159 (TOU12CT) H'0080 0BA4 TOU1_2 Reload Register TOU1_2 Reload 1 Register 10-160 (TOU12RLW) (TOU12RL1) 10-162 H'0080 0BA6 TOU1_2 Reload 0 Register 10-161 (TOU12RL0) H'0080 0BA8 TOU1_3 Counter (Upper) 10-157 (TOU13CTW) (TOU13CTH) H'0080 0BAA (Lower) 10-159 (TOU13CT) H'0080 0BAC TOU1_3 Reload Register TOU1_3 Reload 1 Register 10-160 (TOU13RLW) (TOU13RL1) 10-162 H'0080 0BAE TOU1_3 Reload 0 Register 10-161 (TOU13RL0) H'0080 0BB0 TOU1_4 Counter (Upper) 10-157 (TOU14CTW) (TOU14CTH) H'0080 0BB2 (Lower) 10-159 (TOU14CT) H'0080 0BB4 TOU1_4 Reload Register TOU1_4 Reload 1 Register 10-160 (TOU14RLW) (TOU14RL1) 10-162 H'0080 0BB6 TOU1_4 Reload 0 Register 10-161 (TOU14RL0) H'0080 0BB8 TOU1_5 Counter (Upper) 10-157 (TOU15CTW) (TOU15CTH) H'0080 0BBA (Lower) 10-159 (TOU15CT) H'0080 0BBC TOU1_5 Reload Register TOU1_5 Reload 1 Register 10-160 (TOU15RLW) (TOU15RL1) 10-162 H'0080 0BBE TOU1_5 Reload 0 Register 10-161 (TOU15RL0) H'0080 0BC0 TOU1_6 Counter (Upper) 10-157 (TOU16CTW) (TOU16CTH) H'0080 0BC2 (Lower) 10-159 (TOU16CT) H'0080 0BC4 TOU1_6 Reload Register TOU1_6 Reload 1 Register 10-160 (TOU16RLW) (TOU16RL1) 10-162 H'0080 0BC6 TOU1_6 Reload 0 Register 10-161 (TOU16RL0) H'0080 0BC8 TOU1_7 Counter (Upper) 10-157 (TOU17CTW) (TOU17CTH) H'0080 0BCA (Lower) 10-159 (TOU17CT) H'0080 0BCC TOU1_7 Reload Register TOU1_7 Reload 1 Register 10-160 (TOU17RLW) (TOU17RL1) 10-162 H'0080 0BCE TOU1_7 Reload 0 Register 10-161 (TOU17RL0) H'0080 0BD4 Shorting Prevention Function F/F29–34 Protect Register 10-155 (SHFF2934P) H'0080 0BD6 Shorting Prevention Function F/F29–34 Data Register 10-156 (SHFF2934D) H'0080 0BD8 TOU1 Control Register 1 10-154 (TOU1CR1) H'0080 0BDA TOU1 Control Register 0 10-154 (TOU1CR0) H'0080 0BDC (Use inhibited area) TOU1 Enable Protect Register 10-163 (TOU1PRO) H'0080 0BDE (Use inhibited area) TOU1 Count Enable Register 10-164 (TOU1CEN) H'0080 0BE0 PWMOFF1 Input Processing Control Register 10-166 (PWMOFF1CR)

10-15332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU00M0 TOU01M0 TOU02M0 TOU03M0 TOU04M0 TOU05M0 TOU06M0 TOU07M0 0000000000000000 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU0 PRS3 TOU0 TOU00 TOU01 TOU02 TOU03 TOU04 TOU05 TOU06 TOU07 CKS CKS SHEN M1 M1 M1 M1 M1 M1 M1 M1 0000000000000000

10.8.4 TOU Control Registers

TOU0 Control Register 0 (TOU0CR0) <Address: H’0080 07DA> <Upon exiting reset: H’0000> b Bit Name Function R W 0, 1 TOU00M0 (TOU0_0 operation mode select 0 bit) 00: Single-shot output mode R W 2, 3 TOU01M0 (TOU0_1 operation mode select 0 bit) 01: Single-shot PWM output mode 4, 5 TOU02M0 (TOU0_2 operation mode select 0 bit) or delayed single-shot output mode (Note 1) 6, 7 TOU03M0 (TOU0_3 operation mode select 0 bit) 10: Continuous output mode 8, 9 TOU04M0 (TOU0_4 operation mode select 0 bit) 11: PWM output mode 10, 11 TOU05M0 (TOU0_5 operation mode select 0 bit) 12, 13 TOU06M0 (TOU0_6 operation mode select 0 bit) 14, 15 TOU07M0 (TOU0_7 operation mode select 0 bit) Note 1: Use TOU0 Control Register 1 to select between these two modes. Notes: • This register must always be accessed in halfwords.

• Operation mode can only be set or changed while the counter is inactive. TOU0 Control Register 1 (TOU0CR1) <Address: H’0080 07D8> <Upon exiting reset: H’0000> b Bit Name Function R W

0 TOU0CKS 0: Use prescaler 3 R W

TOU0 clock source select bit 1: Use external clock (TIN24)

1 PRS3CKS 0: BCLK/4 R W

Prescaler 3 supplied clock select bit 1: BCLK 2–6 No function assigned. Fix to "0." 00

7 TOU0SHEN 0: Disable shorting prevention function R W

TOU0 shorting prevention function enable bit 1: Enable shorting prevention function

8 TOU00M1 (TOU0_0 operation mode select 1 bit) 0: Single-shot PWM output mode R W

9 TOU01M1 (TOU0_1 operation mode select 1 bit) 1: Delayed single-shot output mode

10 TOU02M1 (TOU0_2 operation mode select 1 bit)

11 TOU03M1 (TOU0_3 operation mode select 1 bit)

12 TOU04M1 (TOU0_4 operation mode select 1 bit)

13 TOU05M1 (TOU0_5 operation mode select 1 bit)

14 TOU06M1 (TOU0_6 operation mode select 1 bit)

15 TOU07M1 (TOU0_7 operation mode select 1 bit)

Notes: • This register must always be accessed in halfwords.

• Operation mode and the short preventiion function can only be set or changed while the counter is inactive. TOU0 Control Registers 0 and 1 are used to select operation modes of TOU0_0–7. To select prescaler 3 as the clock source for TOU0, make sure the TID0 Control & Prescaler 3 Enable Register’s prescaler 3 enable bit is set to "1." For details, see Section 10.7.3, “TID Control & Prescaler Enable Registers.” Note: • Before setting up or modifying the TOU control register, be sure to stop the relevant timer by writing "0" to its count enable bit.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TOU1 PRS4 TOU1 TOU10 TOU11 TOU12 TOU13 TOU14 TOU15 TOU16 TOU17 CKS CKS SHEN M1 M1 M1 M1 M1 M1 M1 M1 0000000000000000 b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TOU10M0 TOU11M0 TOU12M0 TOU13M0 TOU14M0 TOU15M0 TOU16M0 TOU17M0 0000000000000000 TOU1 Control Register 0 (TOU1CR0) <Address: H’0080 0BDA> <Upon exiting reset: H’0000> b Bit Name Function R W 0, 1 TOU10M0 (TOU1_0 operation mode select 0 bit) 00: Single-shot output mode R W 2, 3 TOU11M0 (TOU1_1 operation mode select 0 bit) 01: Single-shot PWM output mode 4, 5 TOU12M0 (TOU1_2 operation mode select 0 bit) or delayed single-shot output mode (Note 1) 6, 7 TOU13M0 (TOU1_3 operation mode select 0 bit) 10: Continuous output mode 8, 9 TOU14M0 (TOU1_4 operation mode select 0 bit) 11: PWM output mode 10, 11 TOU15M0 (TOU1_5 operation mode select 0 bit) 12, 13 TOU16M0 (TOU1_6 operation mode select 0 bit) 14, 15 TOU17M0 (TOU1_7 operation mode select 0 bit) Note 1: Use TOU1 Control Register 1 to select between these two modes. Notes: • This register must always be accessed in halfwords.

• Operation mode can only be set or changed while the counter is inactive. TOU1 Control Register 1 (TOU1CR1) <Address: H’0080 0BD8> <Upon exiting reset: H’0000> b Bit Name Function R W

0 TOU1CKS 0: Use prescaler 4 R W

TOU1 clock source select bit 1: Use external clock (TIN26)

1 PRS4CKS 0: BCLK/4 R W

Prescaler 4 supplied clock select bit 1: BCLK 2–6 No function assigned. Fix to "0." 00

7 TOU1SHEN 0: Disable shorting prevention function R W

TOU1 shorting prevention function enable bit 1: Enable shorting prevention function

8 TOU10M1 (TOU1_0 operation mode select 1 bit) 0: Single-shot PWM output mode R W

9 TOU11M1 (TOU1_1 operation mode select 1 bit) 1: Delayed single-shot output mode

10 TOU12M1 (TOU1_2 operation mode select 1 bit)

11 TOU13M1 (TOU1_3 operation mode select 1 bit)

12 TOU14M1 (TOU1_4 operation mode select 1 bit)

13 TOU15M1 (TOU1_5 operation mode select 1 bit)

14 TOU16M1 (TOU1_6 operation mode select 1 bit)

15 TOU17M1 (TOU1_7 operation mode select 1 bit)

Note 1: This register must always be accessed in halfwords. Note: • Operation mode and shorting prevention function can only be set or changed while the counter is inactive. TOU1 Control Registers 0 and 1 are used to select operation modes of TOU1_0–7. To select prescaler 4 as the clock source for TOU1, make sure the TID1 Control & Prescaler 4 Enable Register’s prescaler 4 enable bit is set to "1." For details, see Section 10.7.3, “TID Control & Prescaler Enable Registers.” Note: • Before setting up or modifying the TOU control register, be sure to stop the relevant timer by writing "0" to its count enable bit.

10-15532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456 b 7 SHFP29 SHFP30 SHFP31 SHFP32 SHFP33 SHFP34 00000000 b 0 123456 b 7 SHFP21 SHFP22 SHFP23 SHFP24 SHFP25 SHFP26 00000000

10.8.5 Shorting Prevention Function Registers

Shorting Prevention Function F/F21-26 Protect Register (SHFF2126P) <Address: H’0080 07D4> <Upon exiting reset: H’00> b Bit Name Function R W

0 SHFP21 0: Enable write to shorting prevention function F/F output bit R W

Shorting prevention function F/F21 protect bit 1: Disable write to shorting prevention function F/F output bit

1 SHFP22

Shorting prevention function F/F22 protect bit

2 SHFP23

Shorting prevention function F/F23 protect bit

3 SHFP24

Shorting prevention function F/F24 protect bit

4 SHFP25

Shorting prevention function F/F25 protect bit

5 SHFP26

Shorting prevention function F/F26 protect bit 6, 7 No function assigned. Fix to "0." 00 Shorting Prevention Function F/F29–34 Protect Register (SHFF2934P) <Address: H’0080 0BD4> <Upon exiting reset: H’00> b Bit Name Function R W

0 SHFP29 0: Enable write to shorting prevention function F/F output bit R W

Shorting prevention function F/F29 protect bit 1: Disable write to shorting prevention function F/F output bit

1 SHFP30

Shorting prevention function F/F30 protect bit

2 SHFP31

Shorting prevention function F/F31 protect bit

3 SHFP32

Shorting prevention function F/F32 protect bit

4 SHFP33

Shorting prevention function F/F33 protect bit

5 SHFP34

Shorting prevention function F/F34 protect bit 6, 7 No function assigned. Fix to "0." 00 These registers control write to each shorting prevention function F/F (flip-flop) by enabling or disabling. If write to any F/F is disabled, writing to the shorting prevention F/F data register has no efect.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Shorting Prevention Function F/F21-26 Data Register (SHFF2126D) <Address: H’0080 07D6> <Upon exiting reset: H’00> b Bit Name Function R W

0 SHFD21 0: Shorting prevention function F/F output data = 0 R W

Shorting prevention function F/F21 data bit 1: Shorting prevention function F/F output data = 1

1 SHFD22

Shorting prevention function F/F22 data bit

2 SHFD23

Shorting prevention function F/F23 data bit

3 SHFD24

Shorting prevention function F/F24 data bit

4 SHFD25

Shorting prevention function F/F25 data bit

5 SHFD26

Shorting prevention function F/F26 data bit 6, 7 No function assigned. Fix to "0." 00 Shorting Prevention Function F/F29–34 Data Register (SHFF2934D) <Address: H’0080 0BD6> <Upon exiting reset: H’00> b Bit Name Function R W

0 SHFD29 0: Shorting prevention function F/F output data = 0 R W

Shorting prevention function F/F29 data bit 1: Shorting prevention function F/F output data = 1

1 SHFD30

Shorting prevention function F/F30 data bit

2 SHFD31

Shorting prevention function F/F31 data bit

3 SHFD32

Shorting prevention function F/F32 data bit

4 SHFD33

Shorting prevention function F/F33 data bit

5 SHFD34

Shorting prevention function F/F34 data bit 6, 7 No function assigned. Fix to "0." 00 These registers are used to set output in each shorting prevention function F/F (flip-flop). The F/F data register can only be operated on when the F/F protect register described earlier is enabled for write. b 0 123456 b 7 SHFD21 SHFD22 SHFD23 SHFD24 SHFD25 SHFD26 00000000 b 0 123456 b 7 SHFD29 SHFD30 SHFD31 SHFD32 SHFD33 SHFD34 00000000

10-15732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.6 TOU Counters

The TOU counters are functionally different depending on the timer’s operation mode. (1) TOU counters during single-shot output, delayed single-shot output and continuous output modes TOU0_0 Counter (TOU00CTW) <Address: H’0080 0790> TOU0_1 Counter (TOU01CTW) <Address: H’0080 0798> TOU0_2 Counter (TOU02CTW) <Address: H’0080 07A0> TOU0_3 Counter (TOU03CTW) <Address: H’0080 07A8> TOU0_4 Counter (TOU04CTW) <Address: H’0080 07B0> TOU0_5 Counter (TOU05CTW) <Address: H’0080 07B8> TOU0_6 Counter (TOU06CTW) <Address: H’0080 07C0> TOU0_7 Counter (TOU07CTW) <Address: H’0080 07C8> TOU1_0 Counter (TOU10CTW) <Address: H’0080 0B90> TOU1_1 Counter (TOU11CTW) <Address: H’0080 0B98> TOU1_2 Counter (TOU12CTW) <Address: H’0080 0BA0> TOU1_3 Counter (TOU13CTW) <Address: H’0080 0BA8> TOU1_4 Counter (TOU14CTW) <Address: H’0080 0BB0> TOU1_5 Counter (TOU15CTW) <Address: H’0080 0BB8> TOU1_6 Counter (TOU16CTW) <Address: H’0080 0BC0> TOU1_7 Counter (TOU17CTW) <Address: H’0080 0BC8> <Upon exiting reset: Undefined> b Bit Name Function R W 0–7 No function assigned. Fix to "0" 00 8–31 TOU00CTW-TOU07CTW, 24-bit counter value R W TOU10CTW-TOU17CTW Note: • These registers must always be accessed wordwise (in 32 bits) beginning with the word boundary (low-order address B'00) . b16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b31 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU00CTW-TOU07CTW, TOU10CTW-TOU17CTW

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The TOU counters operate as a 24-bit down-counter when in single-shot output, delayed single-shot output or continuous output mode. After the timer is enabled (by writing to the enable bit in software or upon occurrence of the event selected by the TOU enable source select bit), the counter starts counting synchronously with the count clock. Bits 8–15 and bits 16–31 are the 8 high-order and the 16 low-order bits of the counter, respec- tively. Bits 0–7 are ignored. When writing to the counter separately in high and low-order bits, rewrite the 8 high-order bits first and then the 16 low-order bits. The 8 high-order bits become effective when the 16 low-order bits are rewritten. If the counter is rewritten in the reverse order beginning with the 16 low-order bits, the value of the 8 high-order bits is not reflected until the next time the 16 low-order bits are rewritten. If the 8 high-order bits are read before the CPU has finished rewriting the 16 low-order bits after rewriting the 8 high-order bits. The read value shows the previous data (when not counting) or the current count of the previous data (when count is in progress), and not the new rewritten data. If the counter is written to in 32-bit units, it is rewritten successively in order of the 8 high-order bits and then the 16 low-order bits automatically. During PWM output or single-shot PWM output mode, the TOU counters operate as a 16-bit down-counter where only the 16 low-order bits are effective. For details, see Section 10.8.6, Paragraph (2), “TOU counters during PWM output and single-shot PWM output modes.”

10-15932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) TOU counters during PWM output and single-shot PWM output modes TOU0_0 Counter (TOU00CT) <Address: H’0080 0792> TOU0_1 Counter (TOU01CT) <Address: H’0080 079A> TOU0_2 Counter (TOU02CT) <Address: H’0080 07A2> TOU0_3 Counter (TOU03CT) <Address: H’0080 07AA> TOU0_4 Counter (TOU04CT) <Address: H’0080 07B2> TOU0_5 Counter (TOU05CT) <Address: H’0080 07BA> TOU0_6 Counter (TOU06CT) <Address: H’0080 07C2> TOU0_7 Counter (TOU07CT) <Address: H’0080 07CA> TOU1_0 Counter (TOU10CT) <Address: H’0080 0B92> TOU1_1 Counter (TOU11CT) <Address: H’0080 0B9A> TOU1_2 Counter (TOU12CT) <Address: H’0080 0BA2> TOU1_3 Counter (TOU13CT) <Address: H’0080 0BAA> TOU1_4 Counter (TOU14CT) <Address: H’0080 0BB2> TOU1_5 Counter (TOU15CT) <Address: H’0080 0BBA> TOU1_6 Counter (TOU16CT) <Address: H’0080 0BC2> TOU1_7 Counter (TOU17CT) <Address: H’0080 0BCA> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TOU00CT–TOU07CT, 16-bit counter value R W TOU10CT–TOU17CT Note: • These registers must always be accessed in halfwords. The TOU counters operate as a 16-bit down-counter when in PWM output or single-shot PWM output mode. After the timer is enabled (by writing to the enable bit in software or upon occurrence of the event selected by the TOU enable source select bit), the counter starts counting synchronously with the count clock. During single-shot output, delayed single-shot output and continuous output modes, the TOU counters operate as a 24-bit down-counter, with the 8 high-order bits added. For details, see Section 10.8.6, Paragraph (1), “TOU counters during single-shot output, delayed single-shot output and continuous output modes.” b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU00CT–TOU07CT, TOU10CT–TOU17CT

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.7 TOU Reload Registers

The TOU reload registers are used to load data into the TOU counters. These registers are functionally differ- ent depending on the timer’s operation mode. (1) TOU reload registers during single-shot output, delayed single-shot output and continuous output modes TOU0_0 Reload Register (TOU00RLW) <Address: H'0080 0794> TOU0_1 Reload Register (TOU01RLW) <Address: H'0080 079C> TOU0_2 Reload Register (TOU02RLW) <Address: H'0080 07A4> TOU0_3 Reload Register (TOU03RLW) <Address: H'0080 07AC> TOU0_4 Reload Register (TOU04RLW) <Address: H'0080 07B4> TOU0_5 Reload Register (TOU05RLW) <Address: H'0080 07BC> TOU0_6 Reload Register (TOU06RLW) <Address: H'0080 07C4> TOU0_7 Reload Register (TOU07RLW) <Address: H'0080 07CC> TOU1_0 Reload Register (TOU10RLW) <Address: H'0080 0B94> TOU1_1 Reload Register (TOU11RLW) <Address: H'0080 0B9C> TOU1_2 Reload Register (TOU12RLW) <Address: H'0080 0BA4> TOU1_3 Reload Register (TOU13RLW) <Address: H'0080 0BAC> TOU1_4 Reload Register (TOU14RLW) <Address: H'0080 0BB4> TOU1_5 Reload Register (TOU15RLW) <Address: H'0080 0BBC> TOU1_6 Reload Register (TOU16RLW) <Address: H'0080 0BC4> TOU1_7 Reload Register (TOU17RLW) <Address: H'0080 0BCC> <Upon exiting reset: Undefined> b Bit Name Function R W 0–7 No function assigned. Fix to "0." 00 8–31 TOU00RLW–TOU07RLW, 24-bit reload register value R W TOU10RLW–TOU17RLW Note: • These registers must always be accessed wordwise (in 32 bits) beginning with the word boundary (low-order address B'00) . During single-shot output, delayed single-shot output and continuous output modes, TOU operates as a 24-bit timer. The value set in the 24 low-order bits of the reload register is loaded into the counter. Bits 8–15 and bits 16–31 are the 8 high-order and the 16 low-order bits of the counter, respectively. Bits 0–7 are ignored. The content of "the reload register -1" is loaded into the counter synchronously with the count clock at the following timing:

• At the next cycle when the counter is enabled in single-shot output mode
• At the next cycle when the counter has underflowed in delayed single-shot output or continuous output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. During PWM output and single-shot PWM output modes, the TOU reload register operates as 16-bit reload 0 and reload 1 registers. For details, see Section 10.8.7, Paragraph (2), “TOU reload registers during PWM output and single-shot PWM output modes.” b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TOU00RLW-TOU07RLW, TOU10RLW-TOU17RLW b16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b31

10-16132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) TOU reload registers during PWM output and single-shot PWM output modes TOU0_0 Reload 0 Register (TOU00RL0) <Address: H'0080 0796> TOU0_1 Reload 0 Register (TOU01RL0) <Address: H'0080 079E> TOU0_2 Reload 0 Register (TOU02RL0) <Address: H'0080 07A6> TOU0_3 Reload 0 Register (TOU03RL0) <Address: H'0080 07AE> TOU0_4 Reload 0 Register (TOU04RL0) <Address: H'0080 07B6> TOU0_5 Reload 0 Register (TOU05RL0) <Address: H'0080 07BE> TOU0_6 Reload 0 Register (TOU06RL0) <Address: H'0080 07C6> TOU0_7 Reload 0 Register (TOU07RL0) <Address: H'0080 07CE> TOU1_0 Reload 0 Register (TOU10RL0) <Address: H'0080 0B96> TOU1_1 Reload 0 Register (TOU11RL0) <Address: H'0080 0B9E> TOU1_2 Reload 0 Register (TOU12RL0) <Address: H'0080 0BA6> TOU1_3 Reload 0 Register (TOU13RL0) <Address: H'0080 0BAE> TOU1_4 Reload 0 Register (TOU14RL0) <Address: H'0080 0BB6> TOU1_5 Reload 0 Register (TOU15RL0) <Address: H'0080 0BBE> TOU1_6 Reload 0 Register (TOU16RL0) <Address: H'0080 0BC6> TOU1_7 Reload 0 Register (TOU17RL0) <Address: H'0080 0BCE> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TOU00RL0–TOU07RL0, 16-bit reload register value R W TOU10RL0–TOU17RL0 Note: • These registers must always be accessed in halfwords. During PWM output and single-shot PWM output modes, TOU operates as a 16-bit timer. Use the reload 0 register to set the 16-bit value to be loaded into the counter when it is enabled. The content of "the reload 0 register -1" is loaded into the counter synchronously with the count clock at the following timing:

• At the next cycle when the counter is enabled
• At the next cycle when the count value set in the reload 1 register has underflowed in PWM output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. If the value "H'FFFF" is set in the reload register, F/F output will not be inverted, making it possible to produce a 0% or 100% duty-cycle PWM output. For details, see Section 10.8.19, “0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.” During single-shot output, delayed single-shot output and continuous output modes, the reload 0 and reload 1 registers are combined for use as a 24-bit reload register. For details, see Section 10.8.7, Paragraph (1), “TOU reload registers during single-shot output, delayed single-shot output and continuous output modes.” b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU00RL0–TOU07RL0, TOU10RL0–TOU17RL0

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 TOU0_0 Reload 1 Register (TOU00RL1) <Address: H'0080 0794> TOU0_1 Reload 1 Register (TOU01RL1) <Address: H'0080 079C> TOU0_2 Reload 1 Register (TOU02RL1) <Address: H'0080 07A4> TOU0_3 Reload 1 Register (TOU03RL1) <Address: H'0080 07AC> TOU0_4 Reload 1 Register (TOU04RL1) <Address: H'0080 07B4> TOU0_5 Reload 1 Register (TOU05RL1) <Address: H'0080 07BC> TOU0_6 Reload 1 Register (TOU06RL1) <Address: H'0080 07C4> TOU0_7 Reload 1 Register (TOU07RL1) <Address: H'0080 07CC> TOU1_0 Reload 1 Register (TOU10RL1) <Address: H'0080 0B94> TOU1_1 Reload 1 Register (TOU11RL1) <Address: H'0080 0B9C> TOU1_2 Reload 1 Register (TOU12RL1) <Address: H'0080 0BA4> TOU1_3 Reload 1 Register (TOU13RL1) <Address: H'0080 0BAC> TOU1_4 Reload 1 Register (TOU14RL1) <Address: H'0080 0BB4> TOU1_5 Reload 1 Register (TOU15RL1) <Address: H'0080 0BBC> TOU1_6 Reload 1 Register (TOU16RL1) <Address: H'0080 0BC4> TOU1_7 Reload 1 Register (TOU17RL1) <Address: H'0080 0BCC> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TOU00RL1–TOU07RL1, 16-bit reload register value R W TOU10RL1–TOU17RL1 Note: • These registers must always be accessed in halfwords. During PWM output and single-shot PWM output modes, TOU operates as a 16-bit timer. Use the reload 1 register to set the 16-bit value to be loaded into the counter when the count value set in the reload 1 register has underflowed. The content of "the reload 1 register -1" is loaded into the counter synchronously with the count clock at the following timing:

• At the next cycle when the count value set in the reload 0 register has underflowed in PWM output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. If the value "H'FFFF" is set in the reload register, F/F output will not be inverted, making it possible to produce a 0% or 100% duty-cycle PWM output. For details, see Section 10.8.19, “0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.” During single-shot output, delayed single-shot output and continuous output modes, the reload 0 and reload 1 registers are combined for use as a 24-bit reload register. For details, see Section 10.8.7, Paragraph (1), “TOU reload registers during single-shot output, delayed single-shot output and continuous output modes.” b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU00RL1–TOU07RL1, TOU10RL1–TOU17RL1

10-16332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 8 9 1 01 11 21 31 4 b 1 5 TOUn0PRO TOUn1PRO TOUn2PRO TOUn3PRO TOUn4PRO TOUn5PRO TOUn6PRO TOUn7PRO 00000000

10.8.8 TOU Enable Protect Registers

TOU0 Enable Protect Register (TOU0PRO) <Address: H'0080 07DD> TOU1 Enable Protect Register (TOU1PRO) <Address: H'0080 0BDD> <Upon exiting reset: H’00> b Bit Name Function R W

8 TOUn0PRO 0: Enable rewrite R W

TOUn_0 enable protect bit 1: Disable rewrite

9 TOUn1PRO

TOUn_1 enable protect bit

10 TOUn2PRO

TOUn_2 enable protect bit

11 TOUn3PRO

TOUn_3 enable protect bit

12 TOUn4PRO

TOUn_4 enable protect bit

13 TOUn5PRO

TOUn_5 enable protect bit

14 TOUn6PRO

TOUn_6 enable protect bit

15 TOUn7PRO

TOUn_7 enable protect bit The TOU enable protect registers control rewriting of the TOU count enable bit described in Section 10.8.9, “TOU Count Enable Registers,” by enabling or disabling rewrite.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 8 9 1 01 11 21 31 4 b 1 5 TOUn0CEN TOUn1CEN TOUn2CEN TOUn3CEN TOUn4CEN TOUn5CEN TOUn6CEN TOUn7CEN 00000000

10.8.9 TOU Count Enable Registers

TOU0 Count Enable Register (TOU0CEN) <Address: H’0080 07DF> TOU1 Count Enable Register (TOU1CEN) <Address: H'0080 0BDF> <Upon exiting reset: H’00> b Bit Name Function R W

8 TOUn0CEN 0: Stop count R W

TOUn_0 count enable bit 1: Enable count

9 TOUn1CEN

TOUn_1 count enable bit

10 TOUn2CEN

TOUn_2 count enable bit

11 TOUn3CEN

TOUn_3 count enable bit

12 TOUn4CEN

TOUn_4 count enable bit

13 TOUn5CEN

TOUn_5 count enable bit

14 TOUn6CEN

TOUn_6 count enable bit

15 TOUn7CEN

TOUn_7 count enable bit The TOU count enable registers control operation of the TOU counters. To enable any TOU counter in soft- ware, enable its corresponding enable protect bit for rewrite and set the count enable bit by writing "1." To stop any TOU counter, enable its corresponding enable protect bit for rewrite and reset the count enable bit by writing "0." In single-shot output, single-shot PWM output or delayed single-shot output mode, when the counter stops due to occurrence of an underflow, the count enable bit is automatically reset to "0." Therefore, the TOU count enable register when accessed for read serves as a status register indicating whether the counter is operating or idle.

10-16532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.3 Configuration of the TOU0 Enable Circuit WR bn TOU0m enable protect (TOU0mPRO) WR TOU0m enable TOU0 enable source selection (TOU0ENS) (TOU0mCEN) TOU0m enable control F/F F/F Event enable disable TID0_udf/ovf TOU0_7udf Output event bus 0 TIN25S EN-ON WR bn (TOU1mPRO) WR EN-ON (TOU1mCEN) F/F F/F TID1_udf/ovf TOU1_7udf TIN27STID0_udf/ovf TOU0_7udf TIN25S TOU1m enable protect TOU0 enable source selection (TOU0ENS) Event enable disable Output event bus 0 Event enable disable TOU1 enable source selection (TOU1ENS) TOU1m enable TOU1m enable control Figure 10.8.4 Configuration of the TOU1 Enable Circuit

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.10 PWMOFF Input Processing Control Registers

PWMOFF0 Input Processing Control Register (PWMOFF0CR) <Address: H'0080 07E0> <Upon exiting reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0." 00

4 PWMOFF0SP – 0 W

PWMOFF0S write control bit 5–7 PWMOFF0S 000: Input has no effect R W PWMOFF0 input processing control bit 001: Rising edge 010: Falling edge 011: Both edges 10X: "L" level 11X: "H" level PWMOFF1 Input Processing Control Register (PWMOFF1CR) <Address: H'0080 0BE0> <Upon exiting reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0." 00

4 PWMOFF1SP – 0 W

PWMOFF1S write control bit 5–7 PWMOFF1S 000: Input has no effect R W PWMOFF1 input processing control bit 001: Rising edge 010: Falling edge 011: Both edges 10X: "L" level 11X: "H" level The PWMOFF input processing control registers are used to set the active edge or level entered for PWM output disable control from an external pin. For details about the PWM output disable function, see Section 10.8.20, “PWM Output Disable Function.” To set the PWMOFF input processing control bits, follow the procedure described below. 1. Write data "1" to the PWMOFFnS write control bit (PWMOFFnSP). 2. After 1 above, write data "0" to the PWMOFFnS write control bit (PWMOFFnSP) and the set value to the PWMOFF input processing control bits (PWMOFFnS). Note: • If theare are Writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and 2, the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the writing value is not reflected. Therefore, disable interrupts and DMA transfers before setting. However the writing cycle from RTD and DRI are not effected. b 0 123456 b 7 PWMOFF0SP PWMOFF0S 00000000 b 0 123456 b 7 PWMOFF1SP PWMOFF1S 00000000

10-16732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 If a write cycle to any other area occurs during this interval, the value that was set in the PWMOFFnS bits is not reflected. (Note 1) PWMOFFnSP "1" PWMOFFnSP "0" PWMOFFnS Set value

• Example of correct settings  Cases where settings have no effect Because a write cycle to other area exists, the set value is not reflected. (Note 1) PWMOFFnSP "1" Write to other area (1) (2) PWMOFFnSP "1" PWMOFFnSP "1" Because these two consecutive writes comprise a pair, the next set value is not reflected. PWMOFFnSP "0" PWMOFFnS Set value PWMOFFnSP "0" PWMOFFnS Set value Note 1: The writing cycle to the other area is the writing cycle from CPU, DMA, SDI (tool), NBD to any other area.The writing cycle from RTD and DRI do not effect. Figure 10.8.5 PWMOFFnS Setting Procedure

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.11 PWM Output Disable Control Registers

PWM Output 0 Disable Control Register GA (PO0DISGACR) <Address: H’0080 0520> <Upon exiting reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0." 00

6 PO0DISGAP – 0 W

PO0DISGA write control bit

7 PO0DISGA 0: Enable output R W

P87/TO21–P82/TO26 output disable select bit 1: Disable output PWM Output 1 Disable Control Register GA (PO1DISGACR) <Address: H'0080 0522> <Upon exiting reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0." 00

6 PO1DISGAP – 0 W

PO1DISGA write control bit

7 PO1DISGA 0: Enable output R W

P110/TO29–P115/TO34 output disable select bit 1: Disable output PWM Output 0 Disable Control Register GB (PO0DISGBCR) <Address: H’0080 0780> <Upon exiting reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0." 00

6 PO0DISGBP – 0 W

PO0DISGB write control bit

7 PO0DISGB 0: Enable output R W

P00/TO21–P05/TO26 output disable select bit 1: Disable output b 0 123456 b 7 PO0DISGAP PO0DISGA 00000000 b 0 123456 b 7 PO1DISGAP PO1DISGA 00000000 b 0 123456 b 7 PO0DISGBP PO0DISGB 00000000 PWM output disable control register is a register which performs disable control of the PWM output from TO 21~26 and TO29~TO34 terminal. Refer to the "10.8.20 PWM Output Disable Function" for the details of PWM Output Disable Function. The procedure of setting up a POnDISGm bit is described blow. 1. Set POnDISGmP Bit of POnDISGmCR as "1" and write it. 2. Write "0" in POnDISGmP Bit and write setting value in POnDISGm Bit. Note: • If theare are writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and 2, the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the writing value is not reflected. Therefore, disable interrupts and DMA transfers before setting. However the writing cycle from RTD and DRI are not effected.

10-16932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456 b 7 PO1DISGBP PO1DISGB 00000000 PWM Output 1 Disable Control Register GB (PO1DISGBCR) <Address: H'0080 0782> <Upon exiting reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0." 00

6 PO1DISGBP – 0 W

PO1DISGB write control bit

7 PO1DISGB 0: Enable output R W

P10/TO29–P15/TO34 output disable select bit 1: Disable output These registers control output from the respective corresponding pins by enabling or disabling it. These pins can be used to control three-phase PWM output using the TOU timer. Three-phase PWM output can be forcibly disabled (placed in the high-impedance state) by controlling this register. This function can be used for all of output modes or port outputs of TOU. However, use for other modes (external bus, SIO mode, DRI mode and TOP output modes (TO0-TO5) port inputs) is prohibited. For details, see Section 10.8.20, “PWM Output Disable Function.” Also, if this register is accessed for read, it serves as a status register indicating whether PWM output is disabled. To set this register, follow the procedure described below. (In the case of register Gm) 1. Write data "1" to the POnDISGm write control bit (POnDISGmP). 2. After 1 above, write data "0" to the POnDISGm write control bit (POnDISGmP) and data "0" or "1" to the output disable select bit (POnDISGm). Note: • If theare are writing cycles from CPU, DMA, SDI (tool), NBD to any other area between 1 and 2, the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the writing value is not reflected. Therefore, disable interrupts and DMA transfers before setting. However the writing cycle from RTD and DRI are not effected.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.6 POnDISGm Setting Procedure If a write cycle to any other area occurs during this interval, the value that was set in the POnDISGm bit is not reflected. (Note 1) POnDISGmP "1" POnDISGmP "0" POnDISGm Set value  Example of correct settings  Cases where settings have no effect Because a write cycle to other area exists, the set value is not reflected. (Note 1) POnDISGmP "1" Write to other area POnDISGmP "0" POnDISGm Set value (1) (2) POnDISGmP "1" POnDISGmP "1" POnDISGmP "0" POnDISGm Set value Because these two consecutive writes comprise a pair, the next set value is not reflected. Note 1: The writing cycle to the other area is the writing cycle from CPU, DMA, SDI (tool), NBD to any other area. The writing cycle from RTD and DRI do not effect.

10-17132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 8 9 1 01 11 21 31 4 b 1 5 PO0LVSELGAPO0LVENGA 00000000

10.8.12 PWM Output Disable Level Control Registers

PWM Output 0 Disable Level Control Register GA (PO0LVGACR) <Address: H'0080 0521> <Upon exiting reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0." 00

14 PO0LVSELGA 0: Select "L" output disable level R W

P87/TO21–P82/TO26 output disable level select bit 1: Select "H" output disable level

15 PO0LVENGA 0: Disable selected output disable level R W

Output disable level enable/disable select bit 1: Enable selected output disable level PWM Output 1 Disable Level Control Register GA (PO1LVGACR) <Address: H'0080 0523> <Upon exiting reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0." 00

14 PO1LVSELGA 0: Select "L" output disable level R W

P110/TO29–P115/TO34 output disable level select bit 1: Select "H" output disable level

15 PO1LVENGA 0: Disable selected output disable level R W

Output disable level enable/disable select bit 1: Enable selected output disable level PWM Output 0 Disable Level Control Register GB (PO0LVGBCR) <Address: H'0080 0781> <Upon exiting reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0." 00

14 PO0LVSELGB 0: Select "L" output disable level R W

P00/TO21–P05/TO26 output disable level select bit 1: Select "H" output disable level

15 PO0LVENGB 0: Disable selected output disable level R W

Output disable level enable/disable select bit 1: Enable selected output disable level PWM Output 1 Disable Level Control Register GB (PO1LVGBCR) <Address: H'0080 0783> <Upon exiting reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0." 00

14 PO1LVSELGB 0: Select "L" output disable level R W

P10/TO29–P15/TO34 output disable level select bit 1: Select "H" output disable level

15 PO1LVENGB 0: Disable selected output disable level R W

Output disable level enable/disable select bit 1: Enable selected output disable level b 8 9 1 01 11 21 31 4 b 1 5 PO0LVSELGB PO0LVENGB 00000000 b 8 9 1 01 11 21 31 4 b 1 5 PO1LVSELGB PO1LVENGB 00000000 b 8 9 1 01 11 21 31 4 b 1 5 PO1LVSELGAPO1LVENGA 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The output disable level select function allows output from a port to be forcibly disabled (placed in the high- impedance state) depending on the output state of that port. This function may be used to determine whether three-phase PWM output signals are simultaneously on. Furthermore, this function may be used for double-verification of ports because it works depending on the output state of ports. This function can be used for all of output modes or port outputs of TOU. However, use for other modes (external bus, SIO mode, DRI mode and TOP output modes (TO0-TO5) port inputs) is prohibited. For details, see Section 10.8.20, “PWM Output Disable Function.” (1) POnLVSEL (Output Disable Level Select) bit (Bit 14) This bit specifies the level ("H" or "L") at which port output is to be disabled. Set this bit to "0" to disable port output when its level is "L", or "1" to disable port output when its level is "H". The following shows the conditions under which port output is turned off depending on the port’s output state. 1) PO0LVSEL = 0 If any one of the following conditions hold true, TO21–TO26 outputs (TOU0_0–TOU0_5 output pins) are disabled.

• TO21 (TOU0_0 output pin) output and TO22 (TOU0_1 output pin) output both are at the "L" level
• TO23 (TOU0_2 output pin) output and TO24 (TOU0_3 output pin) output both are at the "L" level
• TO25 (TOU0_4 output pin) output and TO26 (TOU0_5 output pin) output both are at the "L" level 2) PO0LVSEL = 1 If any one of the following conditions hold true, TO21–TO26 outputs (TOU0_0–TOU0_5 output pins) are disabled.
• TO21 (TOU0_0 output pin) output and TO22 (TOU0_1 output pin) output both are at the "H" level
• TO23 (TOU0_2 output pin) output and TO24 (TOU0_3 output pin) output both are at the "H" level
• TO25 (TOU0_4 output pin) output and TO26 (TOU0_5 output pin) output both are at the "H" level 3) PO1LVSEL = 0 If any one of the following conditions hold true, TO29–P185/TO34 outputs (TOU1_0–TOU1_5 output pins) are disabled.
• TO29 (TOU1_0 output pin) output and TO30 (TOU1_1 output pin) output both are at the "L" level
• TO31 (TOU1_2 output pin) output and TO32 (TOU1_3 output pin) output both are at the "L" level
• TO33 (TOU1_4 output pin) output and TO34 (TOU1_5 output pin) output both are at the "L" level 4) PO1LVSEL = 1 If any one of the following conditions hold true, TO29–TO34 outputs (TOU1_0–TOU1_5 output pins) are disabled.
• TO29 (TOU1_0 output pin) output and TO30 (TOU1_1 output pin) output both are at the "H" level
• TO31 (TOU1_2 output pin) output and TO32 (TOU1_3 output pin) output both are at the "H" level
• TO33 (TOU1_4 output pin) output and TO34 (TOU1_5 output pin) output both are at the "H" level (2) POnLVEN (Output Disable Level Enable/Disable Select) bit (Bit 15) This bit enables or disables the output disable level that was selected with the POnLVSEL bit. Setting this bit to "1" enables the output disable level selected with the POnLVSEL bit; setting this bit to "0" disables the output disable level selected with the POnLVSEL bit.

10-17332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 b 0 123456 b 7 PWMOFF0 PWMOFF0 GBEN GAEN 00000000

10.8.13 PWMOFF Function Enable Registers

PWMOFF0 Function Enable Register (PWMOFF0EN) <Address: H'0080 0526> <Upon exiting reset: H’00> b Bit Name Function R W

0 PWMOFF0GBEN 0: Disable PWMOFF0 function R W

P00–P05PWMOFF function select bit 1: Enable PWMOFF0 function

1 PWMOFF0GAEN 0: Disable PWMOFF0 function R W

P87–P82PWMOFF function select bit 1: Enable PWMOFF0 function 2–7 No function assigned. Fix to "0." 00 PWMOFF1 Function Enable Register (PWMOFF1EN) <Address: H'0080 0527> <Upon exiting reset: H’00> b Bit Name Function R W

8 PWMOFF1GBEN 0: Disable PWMOFF1 function R W

P10–P15PWMOFF function select bit 1: Enable PWMOFF1 function

9 PWMOFF1GAEN 0: Disable PWMOFF1 function R W

P110–P115PWMOFF function select bit 1: Enable PWMOFF1 function 10–15 No function assigned. Fix to "0." 00 These registers enable or disable the PWM output disable function that was selected with the PWMOFF input pin. This function can be used for all of output modes or port outputs of TOU. However, use for other modes (external bus, SIO mode, DRI mode and TOP output modes (TO0-TO5) port inputs) is prohibited. For details, see Section 10.8.20, “PWM Output Disable Function.” b 8 9 1 01 11 21 31 4 b 1 5 PWMOFF1 PWMOFF1 GBEN GAEN 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.14 Operation in TOU PWM Output Mode (without Correction Function)

(1) Outline of TOU PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle.When PWM output mode, it is operated as a 16 bit timer. When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the value that "the reload 0 register -1" and starts counting down synchronously with the count clock at the next cycle. The next cycle after the first time the counter underflows, it is loaded with the value that "the reload 1 register -1" and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The "reload 0 register set value + 1" and "reload 1 register set value + 1" respectively are effective as count values. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter starts counting and each time it underflows. An interrupt request and DMA transfer request can be generated at even-numbered occurrences of underflow after the counter is enabled. If the value "H'FFFF" is set in either the reload 0 register or the reload 1 register, F/F output will not be inverted although an interrupt request is generated upon underflow, making it possible to produce a 0% or 100% duty-cycle PWM output. Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. However, startup requests to other timers are not delayed. For details, see Section 10.8.19, “0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.” Note that TOU’s PWM output mode does not have the count correction function.

10-17532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.7 Typical Operation in PWM Output Mode H'A000 H'(A000-1) H'C000 H'A000 H'(A000-1) Count clock Enabled (by writing to the enable bit or by external input) Underflow (first time) Enable bit Reload 0 register Underflow (second time) Reload 1 register Reload 1 buffer Undefined value (Note 2) DMA transfer request F/F output (Note 4) Interrupt request due to underflow One count clock equivalent delay Note 1: The value that "reload 0 register - 1" is reloaded. Note 2: The value that "reload 1 register - 1" is reloaded. Note 3: When reload0 is reloaded after updating reload0 register, reload 1 buffer is tranferd. Note 4: Updating of reload 0 and reload 1 during timer operation does not effect PWM waveform that is outputting at present. Updating is reflected at the next PWM period after updating reload 0 register. Note:  This diagram does not show detailed timing information. (Note 1) (Note 1) H'FFFF H'0000 H'A000 H'(C000-1) H'C000 H'C000 H'A000 Counter Count down from the reload 0 register set value Count down from the reload 1 register set value Data inverted by enable Data inverted by underflow Data inverted by underflow PWM output period One count clock equivalent delay One count clock equivalent delay (Note 3) (Note 3) Count down from the reload 0 register set value

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) Reload register updates in TOU PWM output mode In PWM output mode, when the timer remains idle, the reload 0 and reload 1 registers are updated at the same time data are written to the respective registers. While the timer is operating, the reload 1 register is updated when reload 0 register is reloaded after updating the reload 0 register. However, if the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have been written to the respective registers. TOUnRL1 F/F TO TOUnRL0 Internal bus Reload 1 Reload 1 WR Reload 0 WR Reload 1 Buffer 16-bit counterPrescaler output Reload 0 PWM mode control (Note 1) Note 1: It is transferd from reload 1 register to reload 1 buffer when reload 0 register is reloaded after updating reload 0 register during counter operation. Figure 10.8.8 PWM Circuit Diagram To rewrite the reload 0 and reload 1 registers while the timer is operating, rewrite the reload 1 register first and then the reload 0 register. That way, the reload 0 and reload 1 registers both are updated synchro- nously with PWM period, from which the timer starts operating. This operation can normally be performed collectively by accessing 32-bit addresses beginning with the reload 1 register address wordwise. (Data are automatically written to the reload 1 and then the reload 0 registers in succession.) If the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have been written to the respective registers, and not the reload values being actually used. When altering PWM period by rewriting the reload registers, if the PWM period terminates before the CPU finishes writing to reload 0 register, the PWM period is not altered in the current session and the data written to the register is reflected in the next period. When operating in the PWM output mode, writing the reload 0 register and reloard 1 register more than twice within the PWM period and meet the following conditions at the same time, the PWM waveform is output with the value that the last time written reload 0 register and finally written reload 1 register. Condition 1: Start writing reload 0 register after latching the reload 0 register PWM period of the old PWM output period. Condition 2: Rewrite reload 1 register before latching PWM period of the new PWM output period and start writing reload 0 register after latching PWM period.

10-17732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 To update PWM period correctly, take either one of the following measures.

• Identify the completion timing of PWM period by reading counter value at writing reload 1 register and reload 0 register, and then start writing reload 1 register and reload 0 register without crossing PWM period.
• When writing to reload 1 register and reload 0 register by using interruption, set the prescaler value of counter as small as possible. By doing this, write to reload 1 register and reload 0 register later than the counter to be H'FFFF in the PWM period.
• Writing reload 1 register and reload 0 register is performed under the period, less than one time per PWM period. (Extend the reload register's rewrite period against PWM period.) (3) Notes on using TOU PWM output mode The following describes precautions to be observed when using TOU PWM output mode.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.
• If the counter is accessed for read to the cycle of underflow, the counter value is read out as H'FFFF but changes to “reload register value -1” at the next count clock timing.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is in- cluded before F/F output is inverted after the timer is enabled. Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. How- ever, startup requests to other timers are not delayed. For details, see Section 10.8.19, “0% or 100% Duty- Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.” Figure 10.8.9 Update timing of PWM period Count clock Counter H'FFFF H'0000 F/F output Underflow (1st time) Reload 0 register (Note 2) (Note 1) Reload 1 register PWM period (Note 1) Note 1: The value that "the reload 0 register -1" is reloaded. Note 2: The value that "the reload 1 buffer -1" is reloaded. Notes: . : Indicate sampling points. . This diagram does not show detailed timing information. Reload 1 buffer Condition 1 Old PWM output period Condition 2 New PWM putput period Reloading "reload 0 register" (Loading PWM period) Reloading "reload 0 register" (Loading PWM period) Underflow (2nd time) Underflow (2nd time)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.10 Reload 0 and Reload 1 Register Updates in PWM Output Mode H'0001 H'FFFF H'1000 H'7FFF H'2000 H'8000 H'9000 H'1000 H'2000 H'8000 H'9000 H'7FFEH'0000 H'2000 H'9000 H'0001 H'FFFF H'1000 H'8000 H'9000 H'1000 H'2000 H'9000 H'0000 H'2000 Enlarged view Old PWM output period New PWM output period New PWM output period Enlarged view Old PWM output period Old PWM output period (a) When reload register updates take effect in the current period (reflected in the next period) Timing at which reload 0 register is updated Operation by new reload value written Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (Reload 1 data latched) PWM period latched and timing at which reload 1 buffer is updated Count clock Reload 0 register Reload 1 register Counter Interrupt due to underflow F/F output Reload 1 buffer H'0FFF H'2000 (b) When reload register updates take effect in the next period (reflected one period later) Operation by old reload value H'8000 H'0FFE H'9000 Note:  This diagram does not show detailed timing information. Count clock Reload 0 register Reload 1 register Counter Interrupt due to underflow Timing at which reload 0 register is updated Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (Reload 1 data latched) F/F output PWM period latched Reload 1 buffer Old PWM output period

10-17932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.11 Reload 0 and Reload 1 Register Updates in PWM Output Mode (For 0% or 100% Duty-Cycle Wave Output) H'FFFF FFFF FFFF H'1000 FFFF H'9000 H'9000 (a) When reload register updates take effect in the current period (reflected in the next period) Timing at which reload 0 register is updated Operation by new reload value written Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (Reload 1 data latched) PWM period latched and timing at which reload 1 buffer is updated Count clock Reload 0 register Reload 1 register Counter Interrupt due to underflow F/F output Reload 1 buffer H'0FFF FFFF H'9000 H'2000 H'0FFE H'9000 (b) When reload register updates take effect in the next period (reflected one period later) Operation by old reload value Note:  This diagram does not show detailed timing information. Timing at which reload 0 register is updated Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (Reload 1 data latched) PWM period latched Count clock Reload 0 register Reload 1 register Counter Interrupt due to underflow F/F output Reload 1 buffer H'0001 H'FFFF H'1000 FFFF H'2000 FFFF H'9000 H'1000 H'2000 FFFF H'9000 8FFFH'0000 H'2000 H'9000 H'0001 H'FFFF H'1000 H'0FFF H'2000 FFFF H'9000 H'1000 H'2000 FFFF H'9000 H'0FFEH'0000 H'2000 Old PWM output period New PWM output period New PWM output period Enlarged view Enlarged view Old PWM output periodOld PWM output period Old PWM output period

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.15 Operation in TOU Single-shot PWM Output Mode (without Correction Function)

(1) Outline of TOU single-shot PWM output mode In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle only once. When PWM output mode, it is operated as a 16 bit timer. When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the value that "the reload 0 register -1" and starts counting down synchronously with the count clock at the next cycle. At the cycle after the first time the counter underflows, it is loaded with tthe value that "the reload 1 register -1" and continues counting. The counter stops when it underflows next time. The "reload 0 register set value + 1" and "reload 1 register set value + 1" respectively are effective as count values. The timer can be stopped in software, in which case it stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in single-shot PWM output mode is inverted (F/F output level changes from "L" to "H" or vice versa) each time the counter underflows. (Unlike in PWM output mode, the F/F output is not inverted when the counter is enabled.) An interrupt request and DMA transfer request can be generated when the counter underflows second time after being enabled. If the value "H'FFFF" is set in either the reload 0 register or the reload 1 register, F/F output will not be inverted although an interrupt request is generated upon underflow, making it possible to produce a 0% or 100% duty-cycle PWM output. Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. However, startup requests to other timers are not delayed. For details, see Section 10.8.19, “0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.” Note that TOU’s single-shot PWM output mode does not have the count correction function. (2) Notes on using TOU single-shot PWM output mode The following describes precautions to be observed when using TOU single-shot PWM output mode.

• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.
• If the counter is accessed for read at the cycle of underflow, the counter value is read out as H'FFFF but changes to “reload register value -1” at the next count clock timing.
• Updating of reload 0 and reload 1 during timer operation does not effect PWM waveform that is outputting at present. Updating is reflected at the next PWM period after updating reload 0 register. Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. How- ever, startup requests to other timers are not delayed. For details, see Section 10.8.19, “0% or 100% Duty- Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.”

10-18132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.12 Typical Operation in TOU Single-shot PWM Output Mode (without Correction Function) H'A000 H'F000 H'(A000-1) DMA transfer reqiest Count clock Enabled (by writing to the enable bit or by external input) F/F output Underflow (first time) Interrupt request due to underflow Enable bit Reload 0 register Underflow (second time) Reload 1 register One count clock equivalent delay Undefined value (Note 1) (Note 2) H'FFFF H'0000 H'A000 H'A000 H'F000 H'F000 H'(F000-1) Counter Data inverted by underflow Data inverted by underflow One count clock equivalent delay PWM output period Reload 1 buffer Note 1: The value that "reload 0 register - 1" is reloaded. Note 2: The value that "reload 1 buffer - 1" is reloaded. Note 3: Updating of reload 0 and reload 1 during timer operation does not effect PWM waveform that is outputting at present. Updating is reflected at the next PWM period after updating reload 0 register. Note:  This diagram does not show detailed timing information.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.16 Operation in TOU Delayed Single-shot Output Mode (without Correction Function)

(1) Outline of TOU delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of "reload register set value + 1" after a finite time equal to "counter set value + 1" only once and then stops. When the timer is enabled after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. At the cycle after the first time the counter underflows, it is loaded with the value that "the reload register -1" and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter underflows first time and next, generating a single-shot pulse wave- form in width of "reload register set value + 1" after a finite time equal to "first set value of counter + 1" only once. An interrupt request can be generated when the counter underflows first time and next. The "counter set value + 1" and "reload register set value + 1" respectively are effective as count values. (For counting operation, see also Section 10.3.10, “Operation of TOP Delayed Single-shot Output Mode.”) (2) Notes on using TOU delayed single-shot output mode The following describes precautions to be observed when using TOU delayed single-shot output mode.

• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.
• If the counter is accessed for read at the cycle of underflow, the counter value is read as H'FF FFFF but changes to “reload register value -1” at the next count clock timing.
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is in- cluded before F/F output is inverted after the timer is enabled.

10-18332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.13 Typical Operation in TOU Delayed Single-shot Output Mode (without Correction Function) H'FF FFFF H'00 0000 H'10 F000 H'08 A000 H'10 F000 H'(10 F000-1) Data inverted by underflow Data inverted by underflow DMA transfer request Count clock Enabled (by writing to the enable bit or by external input) F/F output Underflow (first time) Interrupt request due to underflow Enable bit Underflow (second time) Counter Reload register Count down from the counter set value (Note 1) Note 1: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.17 Operation in TOU Single-shot Output Mode (without Correction Function)

(1) Outline of TOU single-shot output mode In single-shot output mode, the timer generates a pulse in width of "reload register set value + 1" only once and then stops. When the timer is enabled after setting the reload register, the counter is loaded with the content of "the reload register -1" and starts counting synchronously with the count clock at the next cycle. The counter counts down and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from "L" to "H" or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of "reload register set value + 1" only once. An interrupt request and DMA request can be generated when the counter underflows. The count value is "reload register set value + 1." (For counting operation, see also Section 10.3.9, “Opera- tion of TOP Single-shot Output Mode.”) (2) Notes on using TOU single-shot output mode The following describes precautions to be observed when using TOU single-shot output mode.

• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled.
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.
• Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated before F/F output is inverted after writing the enable bit.

10-18532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.14 Typical Operation in TOU Single-shot Output Mode (without Correction Function) H'FF FFFF H'00 0000 H'55 AA00 H'55 AA00 Data inverted by enable Data inverted by underflow H'(55 AA00-1) DMA transfer request Count clock Enabled (by writing to the enable bit or by external input) F/F output Interrupt request due to underflow Enable bit Reload register Counter Undefined value (Note 1) Note 1: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.18 Operation in TOU Continuous Output Mode (without Correction Function)

(1) Outline of TOU continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of "reload register set value + 1." When the timer is enabled after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. At the next cycle after this underflow causes the counter to be loaded with the content of "the reload register -1" and start counting over again. Thereafter, this operation is repeated each time an under- flow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request and DMA request can be generated each time the counter underflows. The "counter set value + 1" and "reload register set value + 1" are effective as count values. (For counting operation, see also Section 10.3.11, “Operation of TOP Continuous Output Mode.”) (2) Notes on using TOU continuous output mode The following describes precautions to be observed when using TOU continuous output mode.

• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.
• If the counter is accessed for read at the cycle of underflow, the counter value is read out as H'FF FFFF but changes to “reload register value -1” at the next count clock timing.
• Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated before F/F output is inverted after writing the enable bit.

10-18732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.15 Typical Operation in TOU Continuous Output Mode (without Correction Function) H'FF FFFF H'FF 0000 H'0E 0000 H'0A 0000 H'0E 0000 H'(0E 000-1) Data inverted by enable Data inverted by underflow Data inverted by underflow DMA transfer request Underflow (first time) Count down from the counter set value Underflow (second time) Count clock Enabled (by writing to the enable bit or by external input) F/F output Interrupt request due to underflow Enable bit Reload register Counter (Note 1) Note 1: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. H'(0E 000-1) (Note 1)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 10.8.19 0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes During PWM output or single-shot PWM output mode, if the value "H'FFFF" is written to the reload 0 or reload 1 register, F/F output will not be inverted, making it possible to produce a 0% or 100% duty-cycle PWM output. Because determination is made to see if the reload value is "H'FFFF" during PWM output or single-shot PWM output mode, following precautions must be observed. (1) Because the counter counts one even when detecting 0% or 100% duty-cycle, one of the two reload registers must have set in it one less than the intended value in order for a constant-cycle waveform to be produced. Example: If the desired output cycle is 10 counts Cycle ratio 50% : 50% 80% : 20% 90% : 10% 100% : 0% Count ratio 5 : 5 8 : 2 9 : 1 10 : 0 Register set values 0004 : 0004 0007 : 0001 0008 : 0000 0009 : FFFF Because the counter counts n + 1, the values actually set in the respective registers must be one less than the intended value. (2) Because setting the value "H'FFFF" in the reload register produces a 0% or 100% duty-cycle, it is impossible to count the exact "H'FFFF." (3) Setting the value "H'FFFF" in both reload 0 and reload 1 registers is inhibited. (4) Writing the value "H'FFFF" to the counter while in operation is inhibited. (5) Even for a 0% or 100% duty-cycle, interrupt requests and startup registers to other timers are generated. (6) Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is gener- ated. However, startup requests to other timers are not delayed. 0008: FFFF The counter counts one without invert- ing F/F output after detecting "FFFF." For this reason, the value to be set in the register must be "0008," and not "0009."

10-18932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.16 Typical Operation in PWM Output Mode (Reload 0 Register: H’FFFF) Enabled (by writing to the enable bit or by external input) Underflow Superficial underflow H'FFFF H'0000 H'FFFF H'E000 H'(E000-1) H'(FFFF-1)H'(FFFF-1) H'(E000-1) H'E000 Data not invertedData not inverted Data not inverted Counter Undefined value DMA transfer request Enable bit Reload 0 register Reload 1 register F/F output Interrupt request due to underflow Timing at which startup requests to other timers are generated Count clock (Note 1) Note 1: The value that "reload 0 register - 1" is reloaded. Note 2: Because reload 0 redister is H'FFFF, pseudo underflow occurs and the value that "reload 1 register - 1" is reloaded. Notes:  This diagram does not show detailed timing information.  This diagram is shown with respect to the one-count-clock delayed out. (Note 1) (Note 2) (Note 2)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.17 Typical Operation in PWM Output Mode (Reload 1 Register: H’FFFF) Enabled (by writing to the enable bit or by external input) Count clock Enable bit Underflow Superficial underflow H'FFFF H'0000 H'E000 H'E000 H'(E000-1) H'(FFFF-1) H'(FFFF-1) H'(E000-1) H'FFFF Reload 0 register Reload 1 register Interrupt request due to underflow F/F output Data not invertedData inverted by enable Data not inverted Counter Undefined value DMA transfer request Timing at which startup requests to other timers are generated H'(E000-1) (Note 3) Note 1: The value that "reload 0 register - 1" is reloaded. Note 2: The value that "reload 1 register - 1" is reloaded. Note 3: Because reload 1 redister is H'FFFF, pseudo underflow occurs and the value that "reload 0 register - 1" is reloaded. Notes:  This diagram does not show detailed timing information.  This diagram is shown with respect to the one-count-clock delayed out. (Note 2) (Note 1) (Note 3) (Note 2)

10-19132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.18 Typical Operation in Single-shot PWM Output Mode (Reload 0 Register: H’FFFF) Underflow H'FFFF H'0000 H'FFFF H'E000 H'E000 Data inverted by underflow Data inverted by enable Counter Enabled (by writing to the enable bit or by external input) Superficial underflow DMA transfer request Undefined value Enable bit Reload 0 register Reload 1 register F/F output Interrupt request due to underflow Count clock Timing at which startup requests to other timers are generated H'(FFFF-1) H'(E000-1) Note 1: The value that "reload 0 register - 1" is reloaded. Note 2: Because reload 0 redister is H'FFFF, pseudo underflow occurs and the value that "reload 1 register - 1" is reloaded. Notes:  This diagram does not show detailed timing information.  This diagram is shown with respect to the one-count-clock delayed out. (Note 1) (Note 2)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.19 Typical Operation in Single-shot PWM Output Mode (Reload 1 Register: H’FFFF) Count clock Enable bit H'FFFF H'0000 H'E000 H'E000 H'FFFF Reload 0 register Reload 1 register Interrupt request due to underflow F/F output Data not inverted Counter Enabled (by writing to the enable bit or by external input) Underflow Superficial underflow Undefined value DMA transfer request Timing at which startup requests to other timers are generated Note 1: The value that "reload 0 register - 1" is reloaded. Note 2: The value that "reload 1 register - 1" is reloaded. Note 3: Because reload 0 redister is H'FFFF, pseudo underflow occurs. Notes:  This diagram does not show detailed timing information.  This diagram is shown with respect to the one-count-clock delayed out. H'(FFFF-1) (Note 2) H'(E000-1) (Note 1) (Note 3)

10-19332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.20 PWM Output Disable Function

The microcomputer has the function to forcibly disable outputs from the P87(P00)/TO21–P82(P05)/TO26 and P110(P10)/TO29–P115(P15)/TO34 that respectively are the output pins for the TOU0_0–TOU0_5 and TOU1_0– TOU1_5 timers. This function may be used as a protective function when a fault condition such as short-circuiting is detected during three-phase PWM control. This function can be used for all of output modes or port outputs of TOU. However, use for other modes (external bus, SIO mode, DRI mode and TOP output modes (TO0-TO5) port inputs) is prohibited. Figure 10.8.19 shows the circuit configurations of the PWM output disable function. SET F/F RD PWMOFF0S IRQ10 TMS1(Cap3) WR Address PO0DISGACR(WR) PO0LVSELGA IRQ10 TMS1(Cap2) WR Address PO1DISGACR(WR) PO1LVSELGA PO1LVENGA PO0DISGA P130/TIN16/PWMOFF0 P131/TIN17/PWMOFF1 TIN17S PWMOFF1S Level detection Edge detection Level detection Edge detection P87/TO21 P86/TO22 P85/TO23 P84/TO24 P83/TO25 P82/TO26 P175/TO27 P174/TO28 P87/TO21(internal) P86/TO22(internal) P85/TO23(internal) P84/TO24(internal) P83/TO25(internal) P82/TO26(internal) P175/TO27(internal) P174/TO28(internal) P87/TO21(internal) P86/TO22(internal) P85/TO23(internal) P84/TO24(internal) P83/TO25(internal) P82/TO26(internal) P110/TO29(internal) P111/TO30(internal) P112/TO31(internal) P113/TO32(internal) P114/TO33(internal) P115/TO34(internal) P110/TO29 P111/TO30 P112/TO31 P113/TO32 P114/TO33 P115/TO34 P116/TO35 P117/TO36 P110/TO29(internal) P111/TO30(internal) P112/TO31(internal) P113/TO32(internal) P114/TO33(internal) P115/TO34(internal) P116/TO35(internal) P117/TO36(internal) F/F F/F F/FF/F TIN16S PO0LVENGA F/F F/F F/FF/F b7 F/F RD SET PO1DISGA F/F PWMOFF0GAEN F/F PWMOFF1GAEN Figure 10.8.20 Circuit Configurations of the PWM Output Disable Function (Pin Group A)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 RD IRQ10 PO0LVSELGB RD TMS1(Cap2) WR Address PO1DISGBCR(WR) PO1LVSELGB PO1LVENGB PO1DISGB P130/TIN16/PWMOFF0 Level detection Edge detection Level detection Edge detection P00/TO21(internal) P01/TO22(internal) P02/TO23(internal) P03/TO24(internal) P04/TO25(internal) P05/TO26(internal) P06/TO27(internal) P07/TO28(internal) P10/TO29(internal) P11/TO30(internal) P12/TO31(internal) P13/TO32(internal) P14/TO33(internal) P15/TO34(internal) P16/TO35(internal) P17/TO36(internal) P00/TO21(internal) P01/TO22(internal) P02/TO23(internal) P03/TO24(internal) P04/TO25(internal) P05/TO26(internal) P10/TO29(internal) P11/TO30(internal) P12/TO31(internal) P13/TO32(internal) P14/TO33(internal) P15/TO34(internal) F/F F/F F/FF/F TIN16S TMS1(Cap3) WR Address PO0DISGBCR(WR) PO0LVENGB F/F F/F F/FF/F IRQ10 P131/TIN17/PWMOFF1 TIN17S PWMOFF1S F/F P00/TO21 P01/TO22 P02/TO23 P03/TO24 P04/TO25 P05/TO26 P06/TO27 P07/TO28 SET PO0DISGB F/F P10/TO29 P11/TO30 P12/TO31 P13/TO32 P14/TO33 P15/TO34 P16/TO35 P17/TO36 SET F/F PWMOFF0GBEN F/F PWMOFF1GBEN PWMOFF0S Figure 10.8.21 Circuit Configurations of the PWM Output Disable Function (Pin Group B)

10-19532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 There are following three methods to disable PWM outputs. (1) Using the signal entered from an external pin (TIN16/PWMOFF0 or TIN17/PWMOFF1) to disable PWM outputs The input signal on the external pin (TIN16/PWMOFF0) may be used to disable outputs from the ports P87(P00)/TO21–P82(P05)/TO26 that are provided for the PWM outputs of the timer TOU0_0–TOU0_5. Simi- larly, the input signal on the external pin (TIN17/PWMOFF1) may be used to disable outputs from the ports P110(P10)/TO29–P115(P15)/TO34 that are provided for the PWM outputs of the timer TOU1_0–TOU1_5. When selecting rising or falling or both edges at PWMOFFnS bit of PWMOFFn Input Procedure Con- trol Register (PWMOFFnCR) When edge detecting in extarnal pin (TIN16/PWMOFF0, TIN17/PWMOFF1, TIN33/PWMOFF2), PWM output is disabed. At that time POnDISGm bit of PWM Output n Disable Control Gm register is set to "1." Restoring PWM output enable status is done by "0" clearing POnDISGm bit of PWM Output n Disable Control Gm Register (POnDISGmCR). When selecting "L" level or "H" level at PWMOFFnS bit of PWMOFFn Input Procedure Control Regis- ter (PWMOFFnCR) During inputting PWM output disable level to extarrnal pin (TIN16/PWMOFF0, TIN17/PWMOFF1, TIN33/ PWMOFF2), PWM output is disabled.At that time POnDISGm bit of PWM Output n Disable Control Gm Register is set to "1." Restoring PWM output enable status is done by exiting inputting PWM output disable level. At that time setting value written in last time is read out from POnDISGmbit of PWM Output n Disable Control Gm Register (POnDISGmCR). Note: • When write to POnDISGm bit of PWM Output n Disable Control Gm Register druing input- ting PWM output disable level to extarrnal pin (TIN16/PWMOFF0, TIN17/PWMOFF1, TIN33/PWMOFF2), the value written is stored in the register. However, if read out, "1" is read out. Then upon exiting PWM output disable level to external pin, it is possible to read out the contents of setting POnDISGm bit, PWM output is controled by following the set- ting value. To disable PWM outputs by using the input signal on the external pin (TIN16/PWMOFF0 or TIN17/ PWMOFF1), set up the PWMOFFn Input Processing Control Register (PWMOFFnCR) and the PWMOFFn Function Enable Register (PWMOFFnEN) as described below. When using the signal inputted from TIN16/PWMOFF0 to disable PWM outputs 1. Write data "1" to the PWMOFF0CR register PWMOFF0SP bit. 2. After 1 above, write data "0" to the PWMOFF0SP bit and then write setting value ("000," "001," "010," "011," "10X" or "11X") to the PWMOFF0S bit in succession. 3. Enable the PWMOFF0 function by writing "1" to either or both of the PWMOFF0GAEN bits and PWMOFF0GBEN bits of the PWMOFF0EN register. Note: • If theare are CPU, DMA, SDI, Writing cycle from NBD to any other area between 1 and 2, the continuous setting ( A pair of two consecutive is 1 set for writing operation) is disabled and the writing value is not reflected. Therefore, disable interrupts and DMA transfers before setting. However the writing cycle from RTD and DRI is not effected. When using TIN17/PWMOFF1 to disable PWM outputs 1. Write data "1" to the PWMOFF1CR register PWMOFF1SP bit. 2. After 1 above, write data "0" to the PWMOFF1SP bit and then write setting value ("000," "001," "010," "011," "10X" or "11X") to the PWMOFF1S bit in succession. 3. Enable the PWMOFF1 function by writing "1" to either or both of the PWMOFF1GAEN and PWMOFF1GBEN bits of the PWMOFF1EN register.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Note: • If theare are CPU, DMA, SDI, and Writing cycle from NBD to any other area between 1 and 2, the continuous setting (A pair of two consecutive is 1 set for writing operation) is dis- abled and the writing value is not reflected. Therefore, disable interrupts and DMA trans- fers before setting. However, the writing cycle from RTD and DRI are not effected. (2) Using the PWM Output Disable Control Registers to disable PWM outputs The PWM Output 0 Disable Control Gm Register (PO0DISGACR, PO0DISGBCR) may be used to disable outputs from the ports P87(P00)/TO21–P82(P05)/TO26 that are provided for the PWM outputs of the timer TOU0_0–TOU0_5. Similarly, the PWM Output 1 Disable Control Gm Register (PO1DISGACR, PO1DISGBCR) may be used to disable outputs from the ports P110(P10)/TO29–P115(P15)/TO34 that are provided for the PWM outputs of the timer TOU1_0–TOU1_5. To disable PWM output by the PWM Output Disable Control Gm Register (POnDISGACR, POnDISCBCR) set as described below. When using the PWM Output 0 Disable Control Register (PO0DISGACR, PO0DISGBCR) to disable PWM outputs 1. Set the PO0DISGACR(PO0DISGBCR) register PO0DISGAP(PO0DISGBP) bit to “1.” 2. After 1 above, set the PO0DISGAP(PO0DISGBP) bit to “0” and then the PO0DISGA(PO0DISGB) bit to “1” (output disabled). Note: • If a write cycle to any other area ocurs between 1 and 2, the setting of the PO0DISGA (PO0DISGB) bit has no effect. When using the PWM Output 1 Disable Control Register (PO1DISGACR, PO1DISGBCR) to disable PWM outputs 1. Set the PO1DISGACR(PO1DISGBCR) register PO1DISGAP(PO1DISGBP) bit to “1.” 2. After 1 above, set the PO1DISGAP(PO1DISGBP) bit to “0” and then the PO1DISGA(PO1DISGB) bit to “1” (output disabled). Note: • If a write cycle to any other area ocurs between 1 and 2, the setting of the PO1DISGA (PO1DISGB) bit has no effect. (3) Using the pin level on ports P87(P00)/TO21–P82(P05)/TO26 or P110(P10)/TO29–P115(P15)/TO34 to disable PWM outputs The pin level ("H" or "L" level) on ports P87(P00)/TO21–P82(P05)/TO26 may be used to disable outputs from the ports P87(P00)/TO21–P82(P05)/TO26 that are provided for the PWM outputs of the timer TOU0_0–TOU0_5. Similarly, the pin level ("H" or "L" level) on ports P110(P10)/TO29–P115(P15)/TO34 may be used to disable outputs from the ports P110(P10)/TO29–P115(P15)/TO34 that are provided for the PWM outputs of the timer TOU1_0–TOU1_5 . After detecting PWM output disable level from port P87(P00)/TO21-P82(P05)/TO26, P110(P10)/ TO29~P115(P15)/TO34, PWM output is disabled. During PWM Output Disable, POnDISGmbit of PWM Output n Disable Control Gm Register is set to "1." Restoring output enable status is done by exiting outputting PWM output disable level from port P87(P00)/ TO21-P82(P05)/TO26, P110(P10)/TO29-P115(P15)/TO34 and then by "0" clearing POnDISGm bit of PWM Output n Disable Gm Register (POnDISGmCR ). Note: • If POnDISGmbit in PWM Output n Disable Control Gm Register is written during PWM Output Disable level outputting from port P87(P00)/TO21-P82(P05)/TO26, P110(P10)/ TO29-P115(P15)/TO34, that operation of writing has no effect.

10-19732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 To disable PWM outputs using the pin level of ports, set up the PWM Output Disable Level Control Register (POnLVGACR, POnLVGBCR) and PWMOFF Function Enable Register (PWMOFFnEN) as described below. When using the P87(P00)/TO21–P82(P05)/TO26 port level to disable PWM outputs 1. Using the PO0LVGACR(PO0LVGBCR) register PO0LVSELGA(PO0LVSELGB) bit, select the "H" or "L" level at which PWM output is to be disabled. 2. Set the PO0LVENGA(PO0LVENGB) bit to "1" (the selected output disable level effective). 3. Enable the PWMOFF0 function by writing "1" to either or both of the PWMOFF0GAEN and PWMOFF0GBEN bits of the PWMOFF0EN. When using the P110(P10)/TO29–P115(P15)/TO34 port level to disable PWM outputs 1. Using the PO1LVGACR(PO1LVGBCR) register PO1LVSELGA(PO1LVSELGB) bit, select the "H" or "L" level at which PWM output is to be disabled. 2. Set the PO1LVENGA(PO1LVENGB) bit to "1" (the selected output disable level effective). 3. Enable the PWMOFF1 function by writing "1" to either or both of the PWMOFF1GAEN and PWMOFF1GBEN bits of the PWMOFF1EN.

10.8.21 Shorting Prevention Function

Before setting the shorting-prevention function enable/disable bit, be sure to stop the TOUn_0 through TOUn_ 5 counters. (Setting this bit while the timer is enabled for counting is prohibited.) When the shorting-prevention function is enabled, make sure each timer is run in either of the following opera- tion modes. (Using timers in any other modes is prohibited.) TOUn_0 (2, 4)Single-shot PWM mode TOUn_1 (3, 5)Single-shot output mode When the shorting-prevention function is enabled, the TOUn enable source select bits of TOUn_1 (3, 5) have no effect, so that these timers are invoked by an underflow of TOUn_0 (2, 4). Use the TOUn_1 (3, 5) reload register to set the shorting-prevention time. At this time, note that the shorting- prevention time actually is the set value of the reload register + 3. The set value of the reload register must satisfy the condition given below. Set value of the TOUn_1 (3, 5) reload register ≤≤≤≤≤ set value of the TOUn_0 (2, 4) reload 1 register – 4 Before the shorting-prevention function can be enabled, designated values must be set in the F/F data register and the F/F data register for the shorting-prevention function.

• To output a "H" level signal first Set a "1" in the F/F data register and a "0" in the F/F data register for the shorting-prevention function.
• To output a "L" level signal first Set a "0" in the F/F data register and a "1" in the F/F data register for the shorting-prevention function. If the same value is set in the F/F data register and the F/F data register for the shorting-prevention function, a fixed-level signal is output. When the shorting-prevention function is enabled, writing H’FFFF to the TOUn_0 (2, 4) reload register 0 or the TOUn_0 (2, 4) reload register 1 is prohibited.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.22 Schematic Operation of Shorting Prevention Function H'FFFF H'0000 H'A000 H'F000 Undefined value H'FFFF H'0000 H'0010 Count clock Enable bit Reload 0 register Reload 1 register TOUn interrupt request Counter Enable bit Reload register Counter Shorting-prevention periodShorting-prevention period TOUn_0 (2, 4) F/F output TOUn_1 (3, 5) F/F output TOUn_0 (2, 4) TOUn_1 (3, 5) Startup at 3 clocks later Startup at 3 clocks later Enabled (By writing to the enble bit or by external input) H'(F000-1) H'(A000-1) Count down from the reload 0 register set value Count down from the reload 1 register set value Count down from the reload 0 register set value H'0010 H'F000 Count down from the reload 0 register set value Undefined value Note 1: The value that "reload 0 register - 1" is reloaded. Note 2: The value that "reload 1 register - 1" is reloaded. Note 3: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. H'(0010-1) (Note 3) H'(0010-1) (Note 3) (Note 1) (Note 2)

10-19932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 To enable the shorting-prevention function when it is necessary to forcibly fix output in software, follow the procedure described below. (1) Write "0" to the TOUn_0/1 (2/3, 4/5) count enable bit. (2) Set a “value to prevent shorting” in the F/F data register and a “value to be fixed” in the F/F data register for the shorting-prevention function. (3) Write "1" to the TOUn_1 (3, 5) count enable bit. In this case, the shorting-prevention time is as follows: Time before TOUn_1 (3, 5) count is enabled after writing F/F data + TOUn_1 (3, 5) reload register set value + 1 To stop counters in software, make sure TOUn_0/1 (2/3, 4/5) are made to stop counting at the same time. Stopping counters individually is prohibited. Before writing "1" to the TOUn_1 (3, 5) count enable bit, make sure TOUn_0 (2, 4) and TOUn_1 (3, 5) both have stopped counting.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 10.8.23 Schematic Operation for the Case Where the Output is Fixed Forcibly in Software H'FFFF H'0000 Undefined value H'FFFF H'0000 H'0010 Count clock Enable bit Counter Enable bit Reload register Counter Shorting-prevention periodShorting-prevention period TOUn_0 (2, 4) F/F output TOUn_1 (3, 5) F/F output TOUn_0 (2, 4) TOUn_1 (3, 5) Enabled (By writing to the enble bit or by external input) H'(0010-1) (Note 3) H'(0010-1) (Note 3) Count down from the reload register set value H'0010 H'0010 Count down from the reload register set value Undefined (1) Count stop (TOUn_0 (2, 4), TOUn_1 (3, 5)) (2) Writing F/F data/ shorting-prevention F/F data (3) Count enable (TOUn_1 (3, 5)) F/F data value output Shorting- prevention F/F data value output Note 1: The value that "reload0 register - 1" is reloaded. Note 2: The value that "reload1 register - 1" is reloaded. Note 3: The value that "reload register - 1" is reloaded. Note:  This diagram does not show detailed timing information. (Note 1) (Note 2)

10-20132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

10.8.22 Example Application for Using the 32192/32195/32196 in Motor Control

The two-channel TOU timers incorporated in the 32192/32195/32196 help to reduce software burdens during motor control. The following shows an example application for using these timers in motor control. The three-phase motor control waveform is produced by starting TOU in accordance with the fixed 20 kHz TOU startup timing generated by TID. The single-shot PWM function included in TOU enables any desired output waveform to be configured easily by storing waveform data only when the data needs to be rewritten. Note that the transistor shorting prevention time can be provided by changing the set time of TOU in software or using the shorting prevention function. 32192 32195 32196 Power-MOS MotorU V W TOU TOU TOU TOU TOU TOU Circuit board Figure 10.8.24 System Configuration Diagram clk TOUn_0 clk TOUn_1 clk TOUn_2 clk TOUn_3 clk TOUn_4 clk TOUn_5 F/F F/F F/F F/F F/F F/F TO(U) PRS EN EN EN EN EN EN clk udfTIDn Single-shot PWM Single-shot PWM Single-shot PWM Single-shot PWM Single-shot PWM Single-shot PWM Fixed period udf udf udf udf udf udf TO(/U) TO(V) TO(/V) TO(W) TO(/W) 20 kHz generated Startup Note:  When the shorting-prevention function is enabled, make sure that TOUn_1 (3, 5) is set to run in single-shot output mode. Figure 10.8.25 Timer Connections When Used for Three-Phase Motor Control U V W 20KHzTOU start TO(U) TO(/U) TO(V) TO(/V) TO(W) TO(/W) Delay Single shot Delay Single shot : Shorting prevention time Figure 10.8.26 Conceptual Diagram of Motor Control

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 This page is blank for reasons of layout.

11.1 Outline of A/D Converter

11.2 A/D Converter Related Registers

11.3 Functional Description of A/D Converter

11.4 Inflow Current Bypass Circuit

11.5 Notes on the A/D Converter

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The 32192/32195/32196 contains 10-bit resolution A/D Converter of the successive approximation type. The A/ D converter has 16 analog input pins (channels) AD0IN0–AD0IN15. In addition to performing conversion indi- vidually on each channel, the A/D Converter can perform conversion successively on all of N channels (N = 1– 16) as a single group. The conversion result can be read out in either 10 or 8 bits. There are following conversion and operation modes for the A/D conversion: (1) Conversion Modes

• A/D conversion mode : Ordinary mode in which analog input voltages are converted into digital quantities.
• Comparator mode (Note 1) : A mode in which analog input voltage is compared with a preset comparison voltage to find only the relative magnitude of two quantities. (Useful in only single operation mode) (2) Operation Modes
• Single mode : Analog input voltage on one channel is A/D converted once or comparated (Note 1) with a given quantity.
• Scan mode : Analog input voltages on two or more selected channels (in N channel units, N = 1–16) are sequentially A/D converted. Single-shot scan mode : Scan operation is performed for one cycle. Continuous scan mode : Scan operation is repeated until stopped. (3) Special Operation Modes
• Forcible single mode execution during scan mode : Conversion is forcibly executed in single mode (compara- tor mode) during scan operation.
• Scan mode start after single mode execution : Scan operation is started subsequently after executing conversion in single mode.
• Conversion restart : A/D conversion being executed in single or scan mode is restarted. (4) Sample-and-Hold Function The analog input voltage is sampled when starting A/D conversion, and A/D conversion is performed on the sampled voltage. This function can be enabled or disabled as necessary. (5) Simultaneous Sampling Function Two channels are sampled at the same time, and 2-channel continuous A/D conversion is able to be carried out for the sampled voltage. (6) A/D Disconnection Detection Assist Function To suppress influences of the analog input voltage leakage from any preceding channel during scan mode operation, a function is incorporated that helps to fix the electric charge on the chopper amp capacitor to the given state (AVCC0 or GND) before starting A/D conversion. This function provides a sure and reliable means of detecting a disconnection in the wiring patterns connecting to the analog input pins.

11-332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (7) Inflow Current Bypass Circuit If an overvoltage or negative voltage is applied to any analog input channel which is currently inactive, a current flows into or out of the analog input channel currently being A/D converted via the internal circuit, causing the conversion accuracy to degrade. To solve this problem, the A/D Converter incorporates a circuit that bypasses such inflow current. This circuit is always enabled. (8) Conversion Speed The A/D conversion speed is shown in Table 11.1.1 below. The A/D conversion speed is decided by selecting combination such as with or without Sample-and-Hold and selecting Normal or Fast Sample-and-Hold, select- ing Slow or Fast mode, selecting Normal or Double speed. Conversion speed of comparator mode is decided by selecting combination such as selecting Slow or Fast mode, selecting Normal or Double speed. (9) Interrupt Request and DMA Transfer Request Generation Functions An A/D conversion interrupt or DMA transfer request can be generated each time A/D conversion (single mode operation, single-shot scan operation or one cycle of continuous operation) or comparate operation is completed. Note 1: To discriminate between the comparison performed internally by the successive approximation- type A/D Converter and that performed in comparator mode using the same A/D Converter as a comparator, the comparison in comparator mode is referred to in this manual as “comparate.” Table 11.1.1 Outline of the A/D Converter (1/2) Item Description Analog input 16 channels x 1 A/D conversion method Successive approximation method Resolution 10 bits (Conversion result can be read out in either 8 or 10 bits) Absolute accuracy Sample-and-hold is disabled Slow mode Normal speed ± 2LSB (Note 1) Double speed ± 2LSB (Note 2) Fast mode Normal speed ± 3LSB Double speed ± 3LSB Normal Sample-and-hold is enabled, Slow mode Normal speed ± 2LSB Simultaneous sampling is disabled Double speed ± 2LSB Fast mode Normal speed ± 3LSB Double speed ± 3LSB Fast Sample-and-hold is enabled, Slow mode Normal speed ± 3LSB Simultaneous sampling is disabled Double speed ± 3LSB Fast mode Normal speed ± 3LSB Double speed ± 8LSB Normal Sample-and-hold is enabled, Slow mode Normal speed ± 3LSB Simultaneous sampling is enabled Double speed ± 3LSB Fast mode Normal speed ± 3LSB Double speed ± 3LSB Fast Sample-and-hold is enabled, Slow mode Normal speed ± 3LSB Simultaneous sampling is enabled Double speed ± 3LSB Fast mode Normal speed ± 3LSB Double speed ± 8LSB

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 11.1.1 Outline of the A/D Converter (2/2) Item Description Conversion mode A/D Conversion, comparator mode Operation mode Single mode, Scan one shot mode, Scan continuous mode Conversion start trigger Software start Started by setting the A/D conversion start bit to "1" Hardware start A/D0 Converter MJT (input event bus 2), MJT (input event bus 3), MJT (output event bus 3) and MJT (TIN23) Conversion During single mode Slow mode Normal speed 598 x BCLK 14.95µs speed (When sample-and-hold disabled/ Double speed 346 x BCLK 8.65µs (Note 1) When normal sample-and-hold enabled) Fast mode Normal speed 262 x BCLK 6.55µs (Note 2) Double speed 178 x BCLK 4.45µs During single mode Slow mode Normal speed 382 x BCLK 9.55µs (When fast sample-and-hold enabled) Double speed 202 x BCLK 5.05µs Fast mode Normal speed 190 x BCLK 4.75µs Double speed 106 x BCLK 2.65µs During comparator mode Slow mode Normal speed 94 x BCLK 2.35µs Double speed 58 x BCLK 1.45µs Fast mode Normal speed 46 x BCLK 1.15µs Double speed 34 x BCLK 0.85µs Sample-and-hold function Sample-and-hold function can be enabled or disabled as necessary. Simultaneous When Sample-and-hold function is effective, 2 channel simultaneous sampling function can be sampling function selected. A/D disconnection Influences of the analog input voltage leakage from any preceding channel during scan detection assist function mode operation are suppressed. Interrupt request Generated when A/D con version (single mode operation, single-shot scan operation or one cycle of generation function continuous operation) or comparate operation is completed. DMA transfer request Generated when A/D con version (single mode operation, single-shot scan operation or one cycle of generation function continuous operation) or comparate operation is completed. Note 1: Condition for stamdard value : f(XIN)=20MHz, VCCE=VCCBUS=VDDE=AVCC0=5.12V, VCCER=3.3V±0.3V, Ta=-40°C to +105°C, 2BCLK mode Note 2: The conversion accuracy stipulated here refers to that of the microcomputer alone, with influences of the power supply wiring and noise on the board not taken into account.

11-532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 11.1.1 Block Diagram of the A/D Converter AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 Selector Interrupt requestAVSS0 VREF0 10-bit A/D Successive Approximation Register (AD0SAR) 10-bit A/D0 Data Register 0 10-bit A/D0 Data Register 1 A/D0 Single Mode Register A/D0 Comparate Data Register A/D Control Circuit

• Mode selection  Channel selection  Conversion time selection  Flag control  Interrupt control 10-bit D/A Converter Comparator AD0IN8 AD0IN9 AD0N10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 AD0CMP AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0DT12 AD0DT13 AD0DT14 AD0DT15 DMA transfer request Successive Approximation-type A/D Converter Unit Internal data bus A/D0 Scan Mode RegisterAD0SCM0,1 AD0SIM0,1,2 AVCC0 10-bit readout 8-bit readout Shifter 10-bit A/D0 Data Register 2 10-bit A/D0 Data Register 3 10-bit A/D0 Data Register 4 10-bit A/D0 Data Register 5 10-bit A/D0 Data Register 6 10-bit A/D0 Data Register 7 10-bit A/D0 Data Register 8 10-bit A/D0 Data Register 9 10-bit A/D0 Data Register 10 10-bit A/D0 Data Register 11 10-bit A/D0 Data Register 12 10-bit A/D0 Data Register 13 10-bit A/D0 Data Register 14 10-bit A/D0 Data Register 15 Input event bus 2 Input event bus 3 Output event bus 3 TIN23S S S ADCTRG1 ADSTRG1 DMA0, DMA common Sample & hold control circuit S Comparator Sample & hold control circuit

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 11.1.2 Operation in Single Mode (A/D Conversion) A/D conversion interrupt or DMA transfer request Note 1: A/D0 conversion start: Software trigger → Started by setting the A/D0 conversion start bit to "1" Hardware trigger → Started by input event bus 3, input event bus 2, output event bus 3 or TIN23S signal input ADiINn Completed ADiDTn 10-bit A/Di Data Register Conversion starts (Note 1) i=0 n=0–15

11.1.1 Conversion Modes

The A/D Converter has two conversion modes: “A/D Conversion mode” and “Comparator mode.” (1) A/D Conversion Mode In A/D conversion mode, the analog input voltage on a specified channel is A/D converted. In single mode, A/D conversion is performed on a channel selected by the A/D Single Mode Register 1 analog input pin select bit. In scan mode, A/D conversion is performed on channels selected by A/D Scan Mode Register 1 according to settings of A/D Scan Mode Register 0. The conversion result is stored in each channel’s corresponding 10-bit A/D Data Register. There is also an 8-bit A/D Data Register for each channel, from which 8-bit A/D conversion results can be read out. An A/D conversion interrupt or DMA transfer request can be generated when A/D conversion in single mode is completed, as well as when one cycle of scan loop in scan mode is completed. (2) Comparator Mode In comparator mode, the analog input voltage on a specified channel is “comparated” (compared) with the successive approximation register value, and the result (relative magnitude of two values) is returned to a flag. The channel to be comparated is selected using the A/D Single Mode Register 1 analog input pin select bit. The result of comparate operation is flagged ("0" or "1") by setting the A/D Comparate Data Register bit that corresponds to the selected channel. An A/D conversion interrupt or DMA transfer request can be generated when comparate operation is completed.

11.1.2 Operation Modes

There are two operation modes for the A/D Converter: “Single mode” and “Scan mode.” When comparator mode is selected as A/D conversion mode, only single mode can be used. (1) Single Mode In single mode, the analog input voltage on one selected channel is A/D converted or comparated once. An A/D conversion interrupt or DMA transfer request can be generated when A/D conversion or comparate operation is completed.

11-732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 A/D conversion interrupt or DMA transfer request ADiIN0 Completed here when operating in single-shot scan mode ADiDT010-bit A/Di Data Register Conversion starts (Note 1) ADiIN1 ADiINn-1 ADiINn ADiDT1 ADiDTn-1 ADiDTn During continuous scan mode <n-channel scan> i= 0 n=0–15 Note 1: A/D0 conversion start: Software trigger → Started by setting the A/D0 conversion start bit to "1" Hardware trigger → Started by input event bus 3, input event bus 2, output event bus 3 or TIN23S signal input Figure 11.1.4 Operation of A/D Conversion in Scan Mode Figure 11.1.3 Operation in Single Mode (Comparate) (2) Scan Mode In scan mode, the analog input voltages from channel 0 to the channel selected by the A/D Scan Mode Register 1 scan loop select bit (channels 0–15) are sequentially A/D converted. There are two types of scan mode: “Single-shot scan mode” in which A/D conversion is completed after performing one cycle of scan operation, and “Continuous scan mode” in which scan operation is continued until halted by setting the A/D scan mode register 0’s A/D conversion stop bit to "1." These types of scan mode are selected using A/D Scan Mode Register 0. The channels to be scanned are selected using A/D Scan Mode Register 1. The selected channels are scanned sequentially beginning with channel 0. An A/D conversion interrupt or DMA transfer request can be generated when one cycle of scan operation is completed. A/D conversion interrupt or DMA transfer request Note 1: Comparate operation is started by writing a comparison value to the Successive Approximation Register (ADiSAR) ADiINn Completed ADiCMP A/Di Comparate Data Register Conversion starts (Note 1) ADiSAR A/D Successive Approximation Register Comparate result ADiCMP=0 (ANn > ADiSAR) ADiCMP=1 (ANn < ADiSAR) i=0 n=0–15

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 … … Table 11.1.2 Registers in Which Scan Mode A/D Conversion Results Are Stored Scan Mode Register 1 Selected channels Selected channels A/D conversion result channel selection for single-shot scan for continuous scan storage register B'0000:0 ADiIN0 ADiIN0 10-bit A/Di Data Register 0 (ADiIN0) Completed ADiIN0 10-bit A/Di Data Register 0 (Repeated until forcibly terminated) B'0001:1 ADiIN0 ADiIN0 10-bit A/Di Data Register 0 (ADiIN1) ADiIN1 ADiIN1 10-bit A/Di Data Register 1 Completed ADiIN0 10-bit A/Di Data Register 0 (Repeated until forcibly terminated) B'0010:2 ADiIN0 ADiIN0 10-bit A/Di Data Register 0 (ADiIN2) ADiIN1 ADiIN1 10-bit A/Di Data Register 1 ADiIN2 ADiIN2 10-bit A/Di Data Register 2 Completed ADiIN0 10-bit A/Di Data Register 0 (Repeated until forcibly terminated) B'0011:3 ADiIN0 ADiIN0 10-bit A/Di Data Register 0 (ADiIN3) ADiIN1 ADiIN1 10-bit A/Di Data Register 1 ADiIN2 ADiIN2 10-bit A/Di Data Register 2 ADiIN3 ADiIN3 10-bit A/Di Data Register 3 Completed ADiIN0 10-bit A/Di Data Register 0 (Repeated until forcibly terminated) B'XXXX:n ADiIN0 ADiIN0 10-bit A/Di Data Register 0 (ADiINn) ADiIN1 ADiIN1 10-bit A/Di Data Register 1 ADiIN2 ADiIN2 10-bit A/Di Data Register 2 n≤15 ... ADiINn ADiINn 10-bit A/Di Data Register n Completed ADiIN0 10-bit A/Di Data Register 0 (Repeated until forcibly terminated) (i=0)

11-932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.1.3 Special Operation Modes

(1) Forcible single mode execution during scan mode In this special operation mode, single mode conversion (A/D conversion or comparate) is forcibly executed on a specified channel during scan mode operation. For A/D conversion mode, the conversion result is stored in the A/D Data Register corresponding to the specified channel, whereas for comparate mode, the comparison result is stored in the 10-bit A/D Comparate Data Register. When the A/D conversion or comparate operation on a specified channel finishes, scan mode A/D conversion is restarted from where it was canceled during scan operation. To start single mode conversion during scan mode operation in software, choose a software trigger using the Single Mode Register 0 A/D conversion start trigger select bit. Then, for A/D conversion, set the said register’s A/D conversion start bit to "1." For comparate mode, write a comparison value to the A/D Succes- sive Approximation Register (AD0SAR) during scan mode operation. To start single mode conversion during scan mode operation in hardware, choose a hardware trigger using the Single Mode Register 0 A/D conversion start trigger select bit. Then enter the hardware trigger selected with the said register. An A/D conversion interrupt or DMA transfer request can be generated when conversion on a specified channel or one cycle of scan operation is completed. Figure 11.1.5 Forcible Single Mode Execution during Scan Mode A/D conversion interrupt or DMA transfer request ADiIN0 ADiDT010-bit A/Di Data Register Scan mode conversion starts ADiIN1 ADiDT1 ADiDT5 Note 1: The canceled convert operation on channel 2 is reexecuted from the beginning. <To perform single mode conversion on channel ADiIN5 during ADiIN2 conversion in n-channel single-shot scan mode> CompletedADiIN2 ADiINn ADiDT2 ADiDTn ADiIN5 Forcible single mode execution starts (Note 1) ADiIN2 i=0 n=0–15

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 11.1.6 Scan Mode Start after Single Mode Execution A/D conversion interrupt or DMA transfer request ADiIN0 ADiDT010-bit A/Di Data Register Instructed to start scan mode conversion ADiIN1 ADiDT1ADiDT5 <To start n-channel single-shot scan mode subsequently after single mode conversion on channel ADiIN5> CompletedADiINn-1 ADiINn ADiDTn-1 ADiDTn ADiIN5 Single mode conversion starts i=0 n=0–15 (2) Scan mode start after single mode execution In this special operation mode, scan operation is started subsequently after executing single mode conver- sion (A/D conversion or comparate). To start this mode in software, choose a software trigger using the A/D Scan Mode Register 0 A/D conver- sion start trigger select bit. Then set the said register’s A/D conversion start bit to "1" during single mode conversion operation. To start this mode in hardware, choose a hardware trigger using the A/D Scan Mode Register 0 A/D conver- sion start trigger select bit. Then enter the hardware trigger selected with the said register during single mode conversion operation. If a hardware trigger is selected using the A/D conversion start trigger select bit in both A/D Single Mode Register 0 and A/D Scan Mode Register 0 and the selected hardware triggers are entered, the A/D Con- verter first performs single mode conversion and then scan mode conversion in succession. An A/D conversion interrupt or DMA transfer request can be generated when single mode conversion on a specified channel or one cycle of scan operation is completed.

11-1132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (3) Conversion restart In this special operation mode, operation being executed in single or scan mode is stopped in the middle and reexecuted from the beginning. When in single mode, set the A/D Single Mode Register 0 A/D conversion start bit to "1" again or enter a hardware trigger during A/D conversion or comparate operation, and the operation being executed is re- started over again. When in scan mode, set the A/D Scan Mode Register 0 A/D conversion start bit to "1" again or enter a hardware trigger signal during scan operation, and the channel being converted is canceled and A/D con- version is performed from channel 0 over again. Figure 11.1.7 Conversion Restart during Single Mode Operation A/D conversion interrupt or DMA transfer request Single mode ADiIN5 conversion starts ADiDT5 <To restart single mode ADiIN5 conversion> Completed Single mode ADiIN5 restarts ADiIN5 ADiIN5 10-bit A/Di Data Register i=0 Figure 11.1.8 Conversion Restart during Scan Operation A/D conversion interrupt or DMA transfer request ADiIN0 ADiDT010-bit A/Di Data Register Scan mode conversion starts ADiIN1 ADiDT1 <To restart during ADiIN2 conversion in n-channel single-shot scan mode> CompletedADiINn-1 ADiINn ADiDTn-1 ADiDTn Scan mode restarts ADiIN2 ADiIN0 ADiDT0 ADiIN1 ADiDT1 i=0 n=0–15

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.1.4 A/D Converter Interrupt and DMA Transfer Requests

The A/D Converter can generate an A/D conversion interrupt or DMA transfer request each time A/D conver- sion (single mode operation, single-shot scan operation or one cycle of continuous operation) or comparate operation is completed. The A/D Single Mode Register 0 and A/D Scan Mode Register 0 are used to select between A/D conversion interrupt and DMA transfer requests. Figure 11.1.9 Selecting between Interrupt and DMA Transfer Requests

11.1.5 Sample-and-Hold Function

The analog input voltage that was sampled immediately after A/D conversion started is held on, and A/D conversion is performed on that seized voltage. The A/D conversion time in “normal” sample-and-hold mode is the same as in conventional A/D conversion mode of the 32170, etc. The A/D conversion time in “fast” sample-and-hold mode is significantly short, allowing to obtain conversion results more quickly than ever. Scan mode (when one cycle of scan is completed) Single mode (when A/D conversion or comparate operation is completed) A/D conversion interrupt request (To the Interrupt Controller) DMA transfer request (To the DMAC) A/D Scan Mode Register 0 interrupt/DMA transfer request select bit A/D Single Mode Register 0 interrupt/DMA transfer request select bit

11-1332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.1.6 Simultaneous Sampling Function

When the sample-and-hold function is effective, 2 channel Simultaneous Sampling Function can be used, and A/D conversion is carried out with 2-channel continually for the sampled voltage. Figure 11.1.10 Single Mode when Simultaneous Sampling is Effective Figure 11.1.11 Forcible Single Mode Execution during Scanning when Simultaneous Sampling is Effective CompletedConversion starts A/D conversion interrupt or DMA transfer request <When Channel 0 (A/D0 single mode register 1 setting) and Channel 15 (A/D0 single mode register 2 setting) were sampled simultaneously> ADiIN0 ADiIN15 ADiIN15 (Only sampling) i=0 A/D conversion interrupt or DMA transfer request ADiIN0Scan conversion starts ADiIN1 <When Channel 0 (A/D0 single mode register 1 setting) and Channel 15 (A/D0 single mode register 2 setting) were sampled simultaneously> ADiIN2 ADiIN3 Single mode execution request ADiIN2 ADiIN0 ADiIN15 ADiIN15 (Only sampling) i=0

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 11.1.13 Single Mode Restart when Simultaneous Sampling is Effective A/D conversion interrupt or DMA transfer request Conversion starts <When Channel 0 (A/D0 single mode register 1 setting) and Channel 15 (A/D0 single mode register 2 setting) were sampled simultaneously> Single mode re-execution request ADiIN0 ADiIN0 ADiIN15 ADiIN15 (Only sampling) Completed Conversion starts Single mode re-execution request ADiIN0 ADiIN0 ADiIN15 ADiIN15 (Only sampling) CompletedADiIN0 i=0 Figure 11.1.12 Scanning Start after Single Mode Execution when Simultaneous Sampling is Effective A/D conversion interrupt or DMA transfer request Conversion starts <When Channel 0 (A/D0 single mode register 1 setting) and Channel 15 (A/D0 single mode register 2 setting) were sampled simultaneously> ADiIN0 ADiIN1 Scan mode execution request ADiIN0 ADiIN15 ADiIN15 (Only sampling) i=0

11-1532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Shown below is an A/D converter related register map. A/D Converter Related Register Map (1/2) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0080 A/D0 Single Mode Register 0 A/D0 Single Mode Register 1 11-17 (AD0SIM0) (AD0SIM1) 11-19 H'0080 0082 (Use inhibited area) A/D0 Single Mode Register 2 11-21 (AD0SIM2) H'0080 0084 A/D0 Scan Mode Register 0 A/D0 Scan Mode Register 1 11-22 (AD0SCM0) (AD0SCM1) 11-24 H'0080 0086 A/D0 Disconnection Detection Assist Function Control Register A/D0 Conversion Speed Control Register 11-27 (AD0DDACR) (AD0CVSCR) 11-26 H'0080 0088 A/D0 Successive Approximation Register 11-31 (AD0SAR) H'0080 008A A/D0 Disconnection Detection Assist Method Select Register 11-28 (AD0DDASEL) H'0080 008C A/D0 Comparate Data Register 11-32 (AD0CMP) H'0080 008E (Use inhibited area) H'0080 0090 10-bit A/D0 Data Register 0 11-33 (AD0DT0) H'0080 0092 10-bit A/D0 Data Register 1 11-33 (AD0DT1) H'0080 0094 10-bit A/D0 Data Register 2 11-33 (AD0DT2) H'0080 0096 10-bit A/D0 Data Register 3 11-33 (AD0DT3) H'0080 0098 10-bit A/D0 Data Register 4 11-33 (AD0DT4) H'0080 009A 10-bit A/D0 Data Register 5 11-33 (AD0DT5) H'0080 009C 10-bit A/D0 Data Register 6 11-33 (AD0DT6) H'0080 009E 10-bit A/D0 Data Register 7 11-33 (AD0DT7) H'0080 00A0 10-bit A/D0 Data Register 8 11-33 (AD0DT8) H'0080 00A2 10-bit A/D0 Data Register 9 11-33 (AD0DT9) H'0080 00A4 10-bit A/D0 Data Register 10 11-33 (AD0DT10) H'0080 00A6 10-bit A/D0 Data Register 11 11-33 (AD0DT11) H'0080 00A8 10-bit A/D0 Data Register 12 11-33 (AD0DT12) H'0080 00AA 10-bit A/D0 Data Register 13 11-33 (AD0DT13) H'0080 00AC 10-bit A/D0 Data Register 14 11-33 (AD0DT14) H'0080 00AE 10-bit A/D0 Data Register 15 11-33 (AD0DT15) (Use inhibited area) H'0080 00D0 (Use inhibited area) 8-bit A/D0 Data Register 0 11-34 (AD08DT0) H'0080 00D2 (Use inhibited area) 8-bit A/D0 Data Register 1 11-34 (AD08DT1) H'0080 00D4 (Use inhibited area) 8-bit A/D0 Data Register 2 11-34 (AD08DT2) H'0080 00D6 (Use inhibited area) 8-bit A/D0 Data Register 3 11-34 (AD08DT3) H'0080 00D8 (Use inhibited area) 8-bit A/D0 Data Register 4 11-34 (AD08DT4) H'0080 00DA (Use inhibited area) 8-bit A/D0 Data Register 5 11-34 (AD08DT5) H'0080 00DC (Use inhibited area) 8-bit A/D0 Data Register 6 11-34 (AD08DT6)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 A/D Converter Related Register Map (2/2) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 00DE (Use inhibited area) 8-bit A/D0 Data Register 7 11-34 (AD08DT7) H'0080 00E0 (Use inhibited area) 8-bit A/D0 Data Register 8 11-34 (AD08DT8) H'0080 00E2 (Use inhibited area) 8-bit A/D0 Data Register 9 11-34 (AD08DT9) H'0080 00E4 (Use inhibited area) 8-bit A/D0 Data Register 10 11-34 (AD08DT10) H'0080 00E6 (Use inhibited area) 8-bit A/D0 Data Register 11 11-34 (AD08DT11) H'0080 00E8 (Use inhibited area) 8-bit A/D0 Data Register 12 11-34 (AD08DT12) H'0080 00EA (Use inhibited area) 8-bit A/D0 Data Register 13 11-34 (AD08DT13) H'0080 00EC (Use inhibited area) 8-bit A/D0 Data Register 14 11-34 (AD08DT14) H'0080 00EE (Use inhibited area) 8-bit A/D0 Data Register 15 11-34 (AD08DT15)

11-1732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.2.1 A/D Single Mode Register 0

A/D0 Single Mode Register 0 (AD0SIM0) <Address: H’0080 0080> 123456 b 7b0 ADSTRG0ADSTRG1 ADSSEL ADSREQ ADSSTT ADSSTPADSCMP 0 0001000 <Upon exiting reset: H’04> b Bit Name Function R W 0 ADSTRG1 (Note 1) Bits 0 and 2 are used to select an A/D hardware trigger. R W A/D hardware trigger select 1 bit b0 b2 0 0 : Input event bus 2 0 1 : Input event bus 3 1 0 : Output event bus 3 1 1 : TIN23S signal 1 No function assigned. Fix to "0." 00 2 ADSTRG0 (Note 1) Bits 0 and 2 are used to select an A/D hardware trigger. R W A/D hardware trigger select 0 bit (See the column for bit 0.)

3 ADSSEL 0: Software trigger R W

A/D conversion start trigger select bit 1: Hardware trigger (Note 2)

4 ADSREQ 0: A/D conversion interrupt request R W

A/D Interrupt/DMA transfer request select bit 1: DMA transfer request

5 ADSCMP 0: A/D conversion/comparate in progress R –

A/D conversion/comparate completed bit 1: A/D conversion/comparate completed

6 ADSSTP 0: No operation 0 W

A/D conversion stop bit 1: Stop A/D conversion

7 ADSSTT 0: No operation 0 W

A/D conversion start bit 1: Start A/D conversion Note 1: Two bits—bit 0 (A/D hardware trigger select 1) and bit 2 (A/D hardware trigger select 0)—are used to select an A/D hard ware trigger. Note 2: During comparator mode, hardware triggers, if any selected, are ignored and operation is started by a software trigger. A/D Single Mode Register 0 is used to control operation of the A/D Converter during single mode (including special mode, “Forcible single mode execution during scan mode”). (1) ADSTRG (A/D Hardware Trigger Select) bits (Bits 0, 2) These bits select a hardware trigger when A/D conversion by the A/D Converter is to be started in hardware. Select one from the following hardware trigger sources: A/D0 Converter: Input event bus 2 Input event bus 3 Output event bus 3 TIN23 edge select output The contents of these bits are ignored if a software trigger is selected by ADSSEL (A/D conversion start trigger select bit).

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) ADSSEL (A/D Conversion Start Trigger Select) bit (Bit 3) This bit selects whether to use a software or hardware trigger to start A/D conversion during single mode. If a software trigger is selected, A/D conversion is started by setting the ADSSTT (A/D conversion start) bit to "1." If a hardware trigger is selected, A/D conversion is started by the trigger source selected with the ADSTRG (hardware trigger select) bits. (3) ADSREQ (A/D Interrupt Request/DMA Transfer Request Select) bit (Bit 4) This bit selects whether to request an A/D conversion interrupt or a DMA transfer when single mode opera- tion (A/D conversion or comparate) is completed. If neither an interrupt nor a DMA transfer are used, choose to request an A/D conversion interrupt and use the A/D Conversion Interrupt Control Register of the Inter- rupt Controller (ICU) to mask the interrupt request, or choose to request a DMA transfer and use the DMA Channel Control Register to disable DMA transfers to be performed upon completion of A/D conversion. (4) ADSCMP (A/D Conversion/Comparate Completed) bit (Bit 5) This is a read-only bit, whose value when exiting the reset state is "1." This bit is "0" when the A/D Converter is performing single mode operation (A/D conversion or comparate) and is set to "1" when the operation finishes. This bit is also set to "1" when A/D conversion or comparate operation is forcibly terminated by setting the ADSSTP (A/D conversion stop) bit to "1" during A/D conversion or comparate operation. (5) ADSSTP (A/D Conversion Stop) bit (Bit 6) Setting this bit to "1" while the A/D Converter is performing single mode operation (A/D conversion or comparate) causes the operation being performed to stop. Manipulation of this bit is ignored while single mode operation is idle or scan mode operation is under way. Operation stops immediately after writing to this bit. If the A/D Successive Approximation Register is read after being stopped, the content read from the register is the value in the middle of conversion (not trans- ferred to the A/D Data Register). If the A/D conversion start bit and A/D conversion stop bit are set to "1" at the same time, the A/D conversion stop bit has priority. If this bit is set to "1" when performing single mode operation in special mode “Forcible single mode execu- tion during scan mode,” only single mode conversion stops and scan mode operation restarts. (6) ADSSTT (A/D Conversion Start) bit (Bit 7) If this bit is set to "1" when a software trigger has been selected with the ADSSEL (A/D conversion start trigger select) bit, the A/D Converter starts A/D conversion. If the A/D conversion start bit and A/D conversion stop bit are set to "1" at the same time, the A/D conversion stop bit has priority. If this bit is set to "1" again while performing single mode conversion, special operation mode “Conversion restart” is turned on, so that single mode conversion restarts. If this bit is set to "1" again while performing A/D conversion in scan mode, special operation mode “Forcible single mode execution during scan mode” is turned on, so that the channel being converted in scan mode is canceled and single mode conversion is performed. When the single mode conversion finishes, scan mode A/D conversion restarts beginning with the canceled channel.

11-1932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.2.2 A/D Single Mode Register 1

A/D0 Single Mode Register 1 (AD0SIM1) <Address: H’0080 0081> 9 1 01 11 21 31 4 b 1 5b8 ADSMSL ADSSPD ADSSHSL ANSEL 00000000 ADSSHSPD <Upon exiting reset: H’00> b Bit Name Function R W

8 ADSMSL 0: A/D0 conversion mode R W

A/D conversion mode select bit 1: Comparator mode

9 ADSSPD (Note 1) 0: Normal speed R W

A/D conversion speed select bit 1: Double speed

10 ADSSHSL 0: Disable sample-and-hold R W

A/D conversion method select bit 1: Enable sample-and-hold

11 ADSSHSPD (Note 2) 0: Normal sample-and-hold R W

A/D sample-and-hold conversion speed select bit 1: Fast sample-and-hold 12–15 ANSEL 0000 : Select ADiIN0 (i = 0) R W A/D analog input pin select bit 0001 : Select ADiIN1 0010 : Select ADiIN2 0011 : Select ADiIN3 0100 : Select ADiIN4 0101 : Select ADiIN5 0110 : Select ADiIN6 0111 : Select ADiIN7 1000 : Select ADiIN8 1001 : Select ADiIN9 1010 : Select ADiIN10 1011 : Select ADiIN11 1100 : Select ADiIN12 1101 : Select ADiIN13 1110 : Select ADiIN14 1111 : Select ADiIN15 Note 1: The A/D conversion speed is determined by a combination of ADSSPD, ADSSHSL and ADSSHSPD bits and the A/D Conversion Speed Control Register ADCVSD2 and ADCVSD bits. Note 2: Setting of this bit is effective when the sample-and-hold function is enabled by ADSSHSL bit. A/D Single Mode Register 1 is used to select operation mode, conversion speed and analog input pins when the A/D Converter is operating in single mode.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (1) ADSMSL (A/D Conversion Mode Select) bit (Bit 8) This bit selects A/D conversion mode when the A/D Converter is operating in single mode. Setting this bit to "0" selects A/D conversion mode, and setting this bit to "1" selects comparator mode. (2) ADSSPD (A/D Conversion Speed Select) bit (Bit 9) This bit selects the A/D conversion speed when the A/D Converter is operating in single mode. Setting this bit to "0" selects normal speed, and setting this bit to "1" selects double speed. (3) ADSSHSL (A/D Conversion Method Select) bit (Bit 10) This bit enables or disables the sample-and-hold function when the A/D Converter is operating in single mode. Setting this bit to "0" disables the sample-and-hold function, and setting this bit to "1" enables the sample-and-hold function. Setting of this bit has no effect if comparator mode is selected with the ADSMSL (A/D conversion mode select) bit. (4) ADSSHSPD (A/D Sample-and-Hold Speed Select) bit (Bit 11) When the A/D Converter’s sample-and-hold function is enabled, this bit selects a conversion speed. When this bit is "0," the conversion speed is the same as normal A/D conversion speed. When this bit is "1", conversion is performed at a speed faster than normal A/D conversion speed. Setting of this bit has no effect if the sample-and-hold function is disabled by setting the ADSSHSL (A/D conversion method select) bit to "0." For details about the conversion time, see Section 11.3.4, “Calculating the A/D Conversion Time.” (5) ANSEL (A/D Analog Input Pin Select) bits (Bits 12–15) These bits select the analog input pins when the A/D Converter is operating in single mode. A/D conversion or comparate operation is performed on the channels selected with these bits. If these bits are accessed for read, the value written to them is read out.

11-2132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.2.3 A/D Single Mode Register 2

A/D0 Single Mode Register 2 (AD0SIM2) <Address: H’0080 0083> 9 1 01 11 21 31 4 b 1 5b8 AD0SH2 AD0SEL2 00 0000 AD0SH2ST 0 0 <Upon exiting reset: H’00> b Bit Name Function R W

8 ADSH2 0: Simultaneous sampling invalid R W

A/D simultaneous sampling select bit (Note 1) 1: Simultaneous sampling valid

9 ADSH2ST 0: 2nd simultaneous sampling conversion not in progress R –

A/D simultaneous sampling status bit (Note 2) 1: 2nd simultaneous sampling conversion in progress 10, 11 No function assigned. Fix to "0." R0 12–15 ADSEL2 0000 : No channels selected R W A/D simultaneous sampling analog input pin | | select bit (Note 3) 0011 : No channels selected 1100 : Select AD0IN12 1101 : Select ADi0N13 1110 : Select ADi0N14 1111 : Select ADi0N15 Note 1: The A/D conversion mode/sample-and-hold function must be effective with single mode register 1. When the comparator mode/sample-and-hold function is invalid, set the AD0SH2 to "0" (Simultaneous sampling invalid). Note 2: The second conversion speed is the same as the first conversion speed. Note 3: When simultaneous sampling valid is selected, select from B'1100 to B'1111. Furthermore, when simultaneous sampling invalid is seledted, select from B'0000 to B'1011. The A/D single mode register 2 is provided to select simultaneous sampling valid or invalid in the single mode of A/D converter and analog input pin sampled at the same time. (1) ADSH2 (A/D Simultaneous Sampling Select) bit (Bit 8) This bit selects whether simultaneous sampling is valid or invalid” when the A/D converter is in single mode. By clearing this bit to “0,” simultaneous sampling becomes invalid and by setting it to “1,” simultaneous sampling becomes valid. (2) ADSH2ST (A/D Simultaneous Sampling Status) bit (Bit 9) This bit indicates that the number of times the A/D conversion is executed when simultaneous sampling is effective. The bit is set to "1" only when second conversion is in progress. (3) ADSEL2 (A/D Simultaneous Sampling Analog Input Pin Select) bit (Bits 12–15) These bits select a channel sampled at the same time when simultaneous sampling is effective.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.2.4 A/D Scan Mode Register 0

A/D0 Scan Mode Register 0 (AD0SCM0) <Address: H’0080 0084> <Upon exiting reset: H’04> b Bit Name Function R W

0 ADCTRG1 (Note 1) Bits 0 and 2 are used to select an A/D hardware trigger R W

A/D hardware trigger select 1 bit b0 b2 0 0 : Input event bus 2 0 1 : Input event bus 3 1 0 : Output event bus 3 1 1 : TIN23S signal

1 ADCMSL 0: Single-shot mode R W

A/D scan mode select bit 1: Continuous mode

2 ADCTRG0 Bits 0 and 2 are used to select an A/D hardware trigger R W

A/D hardware trigger select 0 bit (See the column for bit 0.)

3 ADCSEL 0: Software trigger R W

A/D conversion start trigger select bit 1: Hardware trigger

4 ADCREQ 0: A/D conversion interrupt request R W

A/D Interrupt/DMA transfer request select bit 1: DMA transfer request

5 ADCCMP 0: A/D conversion in progress R –

A/D conversion completed bit 1: A/D conversion completed

6 ADCSTP 0: No operation 0 W

A/D conversion stop bit 1: Stop A/D conversion

7 ADCSTT 0: No operation 0 W

A/D conversion start bit 1: Start A/D conversion Note 1: Two bits—bit 0 (A/D hardware trigger select 1) and bit 2 (A/D hardware trigger select 0)—are used to select an A/D hard ware trigger. A/D Scan Mode Register 0 is used to control operation of the A/D Converter during scan mode. (1) ADCTRG (A/D Hardware Trigger Select) bits (Bits 0 and 2) These bits select a hardware trigger when A/D conversion by the A/D Converter is to be started in hardware. Select one from the following hardware trigger sources: A/D0 Converter: Input event bus 2 Input event bus 3 Output event bus 3 TIN23 edge select output The contents of these bits are ignored if a software trigger is selected by ADCSEL (A/D conversion start trigger select bit). b 0 123456 b 7 ADCTRG1 ADCMSL ADCTRG0 ADCSEL ADCREQ ADCCMP ADCSTP ADCSTT 0 0000100

11-2332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) ADCMSL (A/D Scan Mode Select) bit (Bit 1) This bit selects scan mode of the A/D Converter between single-shot scan and continuous scan. Setting this bit to "0" selects single-shot scan mode, where the channels selected with the ANSCAN (A/D scan loop select) bits of the A/D0 Scan Mode Register 1 (AD0SCM1) are sequentially A/D converted and when A/D conversion on all selected channels is completed, the conversion operation stops. Setting this bit to "1" selects continuous scan mode, where after operation in single-shot scan mode fin- ishes, A/D conversion is reexecuted beginning with the first channel and continued until stopped by setting the ADCSTP (A/D conversion stop) bit to "1." (3) ADCSEL (A/D Conversion Start Trigger Select) bit (Bit 3) This bit selects whether to use a software or hardware trigger to start A/D conversion during scan mode. If a software trigger is selected, A/D conversion is started by setting the ADCSTT (A/D conversion start) bit to "1." If a hardware trigger is selected, A/D conversion is started by the trigger source selected with the ADCTRG (hardware trigger select) bits. (4) ADCREQ (A/D Interrupt Request/DMA Transfer Request Select) bit (Bit 4) This bit selects whether to request an A/D conversion interrupt or a DMA transfer when one cycle of scan mode operation is completed. If neither an interrupt nor a DMA transfer are used, choose to request an A/D conversion interrupt and use the A/D Conversion Interrupt Control Register of the Interrupt Controller (ICU) to mask the interrupt request, or choose to request a DMA transfer and use the DMA Channel Control Register to disable DMA transfers to be performed upon completion of A/D conversion. (5) ADCCMP (A/D Conversion Completed) bit (Bit 5) This is a read-only bit, whose value when exiting the reset state is "1." This bit is "0" when the A/D Converter is performing scan mode A/D conversion and is set to "1" when single-shot scan mode finishes or continu- ous scan mode is stopped by setting the ADCSTP (A/D conversion stop) bit to "1." (6) ADCSTP (A/D Conversion Stop) bit (Bit 6) Setting this bit to "1" while the A/D Converter is performing scan mode A/D conversion causes the operation being performed to stop. This bit is effective only for scan mode operation, and does not affect single mode operation even when single and scan modes both are active during special operation mode. Operation stops immediately after writing to this bit, and the A/D conversion being performed on any chan- nel is aborted in the middle, without transferring the result to the A/D data register. If the A/D conversion start bit and A/D conversion stop bit are set to "1" at the same time, the A/D conversion stop bit has priority. (7) ADCSTT (A/D Conversion Start) bit (Bit 7) This bit is used to start scan mode operation of the A/D Converter in software. Only when a software trigger has been selected with the ADCSEL (A/D conversion start trigger select) bit, setting this bit to "1" causes A/ D conversion to start. If the A/D conversion start bit and A/D conversion stop bit are set to "1" at the same time, the A/D conversion stop bit has priority. If this bit is set to "1" again while performing scan mode conversion, special operation mode “Conversion restart” is turned on, so that scan mode operation is restarted using the contents set by A/D Scan Mode Registers 0 and 1. If this bit is set to "1" again while performing A/D conversion in single mode, special operation mode “Scan mode start after single mode execution” is turned on, so that scan mode operation starts subsequently after single mode has finished.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.2.5 A/D Scan Mode Register 1

A/D0 Scan Mode Register 1 (AD0SCM1) <Address: H’0080 0085> <Upon exiting reset: H’00> b Bit Name Function R W 8 No function assigned. Fix to "0." 00

9 ADCSPD (Note 1) 0: Normal speed R W

A/D conversion speed select bit 1: Double speed

10 ADCSHSL 0: Disable sample-and-hold R W

A/D conversion method select bit 1: Enable sample-and-hold

11 ADCSHSPD (Note 2) 0: Normal sample-and-hold R W

A/D sample-and-hold conversion speed select bit 1: Fast sample-and-hold 12–15 ANSCAN <For write> R W A/D scan loop select bit ‘B0000–1111 (channels 0–15) <For read during conversion> (i = 0) 0000: Converting ADiIN0 0001: Converting ADiIN1 0010: Converting ADiIN2 0011: Converting ADiIN3 0100: Converting ADiIN4 0101: Converting ADiIN5 0110: Converting ADiIN6 0111: Converting ADiIN7 1000: Converting ADiIN8 1001: Converting ADiIN9 1010: Converting ADiIN10 1011: Converting ADiIN11 1100: Converting ADiIN12 1101: Converting ADiIN13 1110: Converting ADiIN14 1111: Converting ADiIN15 Note 1: The A/D conversion speed is determined by a combination of ADCSPD, ADCSHSL and ADCSHSPD bits and the A/D Conversion Speed Control Register AD0CVSD2 and AD0CVSD bits. Note 2: Setting of this bit is effective when the sample-and-hold function is enabled by ADCSHSL bit. A/D Scan Mode Register 1 is used to select operation mode, conversion speed and scan loop when the A/D Converter is operating in scan mode. The channels selected with the scan loop select bit are scanned sequen- tially beginning with channel 0 (n-channel scan). (1) ADCSPD (A/D Conversion Speed Select) bit (Bit 9) This bit selects an A/D conversion speed when the A/D Converter is operating in scan mode. Setting this bit to "0" selects normal speed, and setting this bit to "1" selects double speed. (2) ADCSHSL (A/D Conversion Method Select) bit (Bit 10) This bit enables or disables the sample-and-hold function when the A/D Converter is operating in scan mode. Setting this bit to "0" disables the sample-and-hold function, and setting this bit to "1" enables the sample-and-hold function. b 8 9 1 01 11 21 31 4 b 1 5 ADCSPD ADCSHSL ADCSHSPD ANSCAN 00000000

11-2532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (3) ADCSHSPD (A/D Sample-and-Hold Conversion Speed Select) bit (Bit 11) When the A/D Converter’s sample-and-hold function is enabled, this bit selects a conversion speed. When this bit is "0," the conversion speed is the same as normal A/D conversion speed. When this bit is "1," conversion is performed at a speed faster than normal A/D conversion speed. Setting of this bit has no effect if the sample-and-hold function is disabled by setting the ADCSHSL (A/D conversion method select) bit to "0." For details about the conversion time, see Section 11.3.4, “Calculating the A/D Conversion Time.” (4) ANSCAN (A/D Scan Loop Select) bits (Bits 12–15) The ANSCAN (A/D scan loop select) bits set the channels to be scanned during scan mode of the A/D Converter. The ANSCAN (A/D scan loop select) bits when accessed for read during scan operation serve as a status register indicating the channel being scanned. The value read from these bits during single mode is always B’0000. When it is read out by One shot mode after scan operation is compeleted, the channel value changed last time is read out. If A/D conversion is stopped by setting A/D Scan Mode Register 0 ADCSTP (A/D conversion stop) bit to "1" while executing scan mode, the value read from these bits indicates the channel whose A/D conversion has been canceled. Also, if read during single mode conversion of special operation mode “Forcible single mode execution during scan mode,” the value of these bits indicates the channel whose A/D conversion has been canceled in the middle of scan.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.2.6 A/D Conversion Speed Control Register

A/D0 Conversion Speed Control Register (AD0CVSCR) <Address: H’0080 0087> <Upon exiting reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0." 00

14 ADCVSD2 0: 2BCLK mode R W

A/D conversion speed control bit 2 1: Setting prihibited

15 ADCVSD (Note 1) 0: Slow mode R W

A/D conversion speed control bit 1: Fast mode Note 1: The A/D conversion speed is determined by a combination of AD0CVSD and AD0CVSD2 bits and A/D0 Single Mode Register 1’s ADSSPD bit during single mode, or a combination of AD0CVSD and AD0CVSD2 bits and A/D Scan Mode Register 1’s ADCSPD bit during scan mode. The A/D Conversion Speed Control Register controls the A/D conversion speed during single and scan modes of the A/D Converter. The A/D conversion speed is determined in combination with the conversion speed select bits (Double/Normal) in A/D Single Mode Register 1 and A/D Scan Mode Register 1. b 8 9 1 01 11 21 31 4 b 1 5 ADCVSD2 ADCVSD 00000000

11-2732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.2.7 A/D Disconnection Detection Assist Function Control Register

A/D0 Disconnection Detection Assist Function Control Register (AD0DDACR) <Address: H’0080 0086> <Upon exiting reset: H’00> b Bit Name Function R W 0–6 No function assigned. Fix to "0." 00

7 ADDDAEN (Note 1) 0: Disable A/D disconnection detection assist function R W

A/D disconnection detection assist function enable bit 1: Enable A/D disconnection detection assist function Note 1: For the A/D disconnection detection assist function to be enabled, the conversion start state (discharge or precharge) must be set using the A/D disconnection detection assist method select register after setting the ADDDAEN bit to "1." The A/D Disconnection Detection Assist Function Control Register is used to enable or disable the content of the A/D Disconnection Detection Assist Method Select Register. Note: • If any analog input wiring is disconnected, the conversion result varies depending on the circuits fitted external to the chip. This function must be fully evaluated in the actual application system before it can be used. b 0 123456 b 7 ADDDAEN 00000000

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.2.8 A/D Disconnection Detection Assist Method Select Register

A/D0 Disconnection Detection Assist Method Select Register (AD0DDASEL) <Address: H’0080 008A> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 ADDDA SEL0 ADDDA SEL1 ADDDA SEL2 ADDDA SEL3 ADDDA SEL4 ADDDA SEL6 ADDDA SEL7 ADDDA SEL8 ADDDA SEL9 ADDDA SEL10 ADDDA SEL11 ADDDA SEL12 ADDDA SEL13 ADDDA SEL14 ADDDA SEL15 ADDDA SEL5 <Upon exiting reset: Undefined> b Bit Name Function R W

0 ADDDASEL0 0: Discharge before conversion R W

Channel 0 disconnection detection assist method select bit 1: Precharge before conversion

1 ADDDASEL1

Channel 1 disconnection detection assist method select bit

2 ADDDASEL2

Channel 2 disconnection detection assist method select bit

3 ADDDASEL3

Channel 3 disconnection detection assist method select bit

4 ADDDASEL4

Channel 4 disconnection detection assist method select bit

5 ADDDASEL5

Channel 5 disconnection detection assist method select bit

6 ADDDASEL6

Channel 6 disconnection detection assist method select bit

7 ADDDASEL7

Channel 7 disconnection detection assist method select bit

8 ADDDASEL8

Channel 8 disconnection detection assist method select bit

9 ADDDASEL9

Channel 9 disconnection detection assist method select bit

10 ADDDASEL10

Channel 10 disconnection detection assist method select bit

11 ADDDASEL11

Channel 11 disconnection detection assist method select bit

12 ADDDASEL12

Channel 12 disconnection detection assist method select bit

13 ADDDASEL13

Channel 13 disconnection detection assist method select bit

14 ADDDASEL14

Channel 14 disconnection detection assist method select bit

15 ADDDASEL15

Channel 15 disconnection detection assist method select bit Notes: • This register must always be accessed in halfwords.

• For these bits to be enabled, the ADDDAEN bit (A/D Disconnection Detection Assist Function Control Register bit 7) must be set to "1" before setting these bits. In order to prevent the A/D conversion result from being affected by the analog input voltage leakage from any preceding channel, the A/D Disconnection Detection Assist Method Select Register is used to control the conversion start state by selecting whether to discharge or precharge the chopper amp capacitor before start- ing regular conversion operation.

11-2932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 11.2.1 shows an example of A/D disconnection detection assist method in which the conversion start of A/D disconnection detection assist method in which the conversion start state is set to the AVSS0 side (i.e., discharge before conversion is selected). Figure 11.2.1 Example of A/D Disconnection Detection on AVCC0 Side (Precharge Before Conversion Selected) Figure 11.2.2 Example of A/D Disconnection Detection on AVSS0 Side (Discharge Before Conversion Selected) Analog input ADiINn Precharge Broken wire R C Precharge control signal Chopper amp capacitor Discharge control signal Typical external circuit (Note 1) On Off Note 1: In case of broken wire, the conversion result varies with external circuits. Therefore, careful evaluation is required before this function can be used. ADDDAEN i=0 n=0-15 Analog input ADiINn Discharge Broken wire RC Precharge control signal Chopper amp capacitor Discharge control signal Typical external circuit (Note 1) Off On Note 1: In case of broken wire, the conversion result varies with external circuits. Therefore, careful evaluation is required before this function can be used. ADDDAEN i=0 n=0-15

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 11.2.3 A/D Disconnection Detection Assist Data (when Discharge Before Conversion Selected) Figure 11.2.4 A/D Disconnection Detection Assist Data (when Precharge Before Conversion Selected) Disconnection detection voltage (without sample-and-hold) 200 400 600 800 1000 1200 1400 1600 1800 2000 A/D conversion cycle [kHz] Voltage on disconnected port [mV] Scan mode: Disconnection detection enabled Scan mode: Disconnection detection disabled 0 20 40 60 80 100 120 Note:  Reference value when set as f(BCLK)=40MHz, set 2BCLK mode in ADCVSD2 bit of A/D0 conversion speed control register. 2900 3100 3300 3500 3700 3900 4100 4300 4500 4700 4900 5100 A/D conversion cycle [kHz] Voltage on disconnected port [mV] Disconnection detection voltage (without sample-and-hold) Note:  Reference value when set as f(BCLK)=40MHz, set 2BCLK mode in ADCVSD2 bit of A/D0 conversion speed control register. 0 20 40 60 80 100 120 Scan mode: Disconnection detection enabled Scan mode: Disconnection detection disabled

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11.2.9 A/D Successive Approximation Register

A/D0 Successive Approximation Register(AD0SAR) <Address: H’0080 0088> <Upon exiting reset: Undefined> b Bit Name Function R W 0–5 No function assigned. Fix to "0." 00 6–15 ADSAR • A/D successive approximation value (A/D conversion mode) R W A/D successive approximation value/comparison value • Comparison value (comparator mode) Note: • This register must always be accessed in halfwords. The A/D Successive Approximation Register (ADSAR) is used to read the conversion result of the A/D Con- verter when operating in A/D conversion mode or write a comparison value when operating in comparator mode. In A/D conversion mode, the successive approximation method is used to perform A/D conversion. With this method, the reference voltage VREF0 and analog input voltages are sequentially compared bitwise beginning with the high-order bit, and the comparison result is set in the A/D Successive Approximation Register (ADSAR) bits 6–15. When the A/D conversion has finished, the value of this register is transferred to the 10-bit A/D Data Register (ADDTn) corresponding to each converted channel. When this register is accessed for read in the middle of A/D conversion, the value read from the register indicates the intermediate result of conversion. In comparator mode, this register is used to write a comparison value (the voltage with which to “comparate”). Simultaneously with a write to this register, the A/D Converter starts comparing the voltage on the analog input pin selected with A/D Single Mode Register 1 and the value written in this register. After comparate operation, the result is stored in the A/D Comparate Data Register (ADCMP). Use the calculation formula shown below to find the comparison value to be written to the A/D Successive Approximation Register (ADSAR) during comparator mode. Comparison value = H’3FF x Comparate comparison voltage [V] VREF0 input voltage [V] b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 ADSAR

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.2.10 A/D Comparate Data Register

A/D0 Comparate Data Register (AD0CMP) <Address: H’0080 008C> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 AD CMP0 AD CMP1 AD CMP2 AD CMP3 AD CMP4 AD CMP6 AD CMP7 AD CMP8 AD CMP9 AD CMP10 AD CMP11 AD CMP12 AD CMP13 AD CMP14 AD CMP15 AD CMP5 <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 ADCMP0–ADCMP15 (Note 1) 0: Analog input voltage > comparison voltage R – A/D comparate result flag 1: Analog input voltage < comparison voltage Note 1: During comparator mode, the bits in this register correspond one for one to channels 0–15. Note: • This register must always be accessed in halfwords. When comparator mode is selected using the A/D Single Mode Register 1 ADSMSL (A/D conversion mode select) bit, the selected analog input voltage is compared with the value written to the A/D Successive Approxi- mation Register and the result is stored in the corresponding bit of this comparate data register. The bit or flag in this register is "0" when analog input voltage > comparison voltage, or "1" when analog input voltage < comparison voltage.

11-3332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 11.2.11 10-bit A/D Data Registers 10-bit A/D0 Data Register 0(AD0DT0) <Address: H’0080 0090> 10-bit A/D0 Data Register 1(AD0DT1) <Address: H’0080 0092> 10-bit A/D0 Data Register 2(AD0DT2) <Address: H’0080 0094> 10-bit A/D0 Data Register 3(AD0DT3) <Address: H’0080 0096> 10-bit A/D0 Data Register 4(AD0DT4) <Address: H’0080 0098> 10-bit A/D0 Data Register 5(AD0DT5) <Address: H’0080 009A> 10-bit A/D0 Data Register 6(AD0DT6) <Address: H’0080 009C> 10-bit A/D0 Data Register 7(AD0DT7) <Address: H’0080 009E> 10-bit A/D0 Data Register 8(AD0DT8) <Address: H’0080 00A0> 10-bit A/D0 Data Register 9(AD0DT9) <Address: H’0080 00A2> 10-bit A/D0 Data Register 10(AD0DT10) <Address: H’0080 00A4> 10-bit A/D0 Data Register 11(AD0DT11) <Address: H’0080 00A6> 10-bit A/D0 Data Register 12(AD0DT12) <Address: H’0080 00A8> 10-bit A/D0 Data Register 13(AD0DT13) <Address: H’0080 00AA> 10-bit A/D0 Data Register 14(AD0DT14) <Address: H’0080 00AC> 10-bit A/D0 Data Register 15(AD0DT15) <Address: H’0080 00AE> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 ADDT0-ADDT15 <Upon exiting reset: Undefined> b Bit Name Function R W 0–5 No function assigned. 00 6–15 ADDT0-ADDT15 10-bit A/D conversion result R – 10-bit A/D data Note: • These registers must always be accessed in halfwords. During single mode, the 10-bit A/D Data Registers are used to store the result of A/D conversion performed on each corresponding channel. During single-shot or continuous scan mode, the content of the A/D Successive Approximation Register is transferred to the 10-bit A/D Data Register for the corresponding channel when A/D conversion on each chan- nel has finished. Each 10-bit A/D Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 11.2.12 8-bit A/D Data Registers 8-bit A/D0 Data Register 0(AD08DT0) <Address: H’0080 00D1> 8-bit A/D0 Data Register 1(AD08DT1) <Address: H’0080 00D3> 8-bit A/D0 Data Register 2(AD08DT2) <Address: H’0080 00D5> 8-bit A/D0 Data Register 3(AD08DT3) <Address: H’0080 00D7> 8-bit A/D0 Data Register 4(AD08DT4) <Address: H’0080 00D9> 8-bit A/D0 Data Register 5(AD08DT5) <Address: H’0080 00DB> 8-bit A/D0 Data Register 6(AD08DT6) <Address: H’0080 00DD> 8-bit A/D0 Data Register 7(AD08DT7) <Address: H’0080 00DF> 8-bit A/D0 Data Register 8(AD08DT8) <Address: H’0080 00E1> 8-bit A/D0 Data Register 9(AD08DT9) <Address: H’0080 00E3> 8-bit A/D0 Data Register 10(AD08DT10) <Address: H’0080 00E5> 8-bit A/D0 Data Register 11(AD08DT11) <Address: H’0080 00E7> 8-bit A/D0 Data Register 12(AD08DT12) <Address: H’0080 00E9> 8-bit A/D0 Data Register 13(AD08DT13) <Address: H’0080 00EB> 8-bit A/D0 Data Register 14(AD08DT14) <Address: H’0080 00ED> 8-bit A/D0 Data Register 15(AD08DT15) <Address: H’0080 00EF> <Upon exiting reset: Undefined> b Bit Name Function R W 8–15 AD8DT0-AD8DT15 8-bit A/D conversion result R – 8-bit A/D data The A/D data register is used to store the 8-bit conversion data for the A/D converter. During single mode, the 8-bit A/D Data Registers store the result of A/D conversion performed on each corre- sponding channel. During single-shot or continuous scan mode, the content of the A/D Successive Approximation Register is transferred to the 8-bit A/D Data Register for the corresponding channel when A/D conversion on each channel has finished. Each 8-bit A/D Data Register retains the last conversion result until they receive the next conver- sion result transferred, allowing the content to be read out at any time. b 8 9 1 01 11 21 31 4 b 1 5 AD8DT0-AD8DT15

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11.3.1 How to Find Analog Input Voltages

The A/D Converter performs A/D conversion using a 10-bit successive approximation method. The equation shown below is used to calculate the actual analog input voltage from the digital value obtained by executing A/ D conversion. Analog input voltage [v] = A/D conversion result x VREF input voltage [V] 1,024 The A/D Converter is a 10-bit converter, providing a resolution of 1,024 discrete voltage levels. Because the reference voltage for the A/D Converter is the voltage applied to the VREF0 pin, make sure that an exact and stable constant-voltage power supply is connected to VREF0. Also make sure the analog circuit power supply and ground (AVCC0, AVSS0) are separated from those of the digital circuit, with sufficient noise prevention measures incorporated. For details about the conversion accuracy, see Section 11.3.5, “Accuracy of A/D Conversion.” Figure 11.3.1 Outline Block Diagram of the Successive Approximation-type A/D Converter Unit ADiIN0 ADiIN1 ADiIN2 ADiIN3 ADiIN4 ADiIN5 ADiIN6 ADiIN7 Selector AVSSi VREFi 10-bit A/Di Successive Approximation Register (ADiSAR) 10-bit A/Di Data Register A/Di Comparate Data Register A/D Control Circuit 10-bit D/A Converter Comparator ADiIN8 ADiIN9 ADiIN10 ADiIN11 ADiIN12 ADiIN13 ADiIN14 ADiIN15 ADiCMP ADiDT0–15 Successive Approximation-type A/D Converter Unit AVCCi Vref VIN Sample-and-Hold Control Circuit i=0

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.3.2 A/D Conversion by Successive Approximation Method

The A/D Converter use an A/D conversion start trigger (software or hardware) as they start A/D conversion. Once A/D conversion begins, the following operation is automatically performed. 1. During single mode, A/D Single Mode Register 0’s A/D conversion/comparate completion bit is cleared to "0." During scan mode, A/D Scan Mode Register 0’s A/D conversion completion bit is cleared to "0." 2. The content of the A/D Successive Approximation Register is cleared to H’0000. 3. The A/D Successive Approximation Register’s most significant bit (bit 6) is set to "1." 4. The comparison voltage, Vref (Note 1), is fed from the D/A Converter into the comparator. 5. The comparison voltage, Vref, and the analog input voltage, VIN, are compared, and the comparison result will be stored in bit 6. If Vref < VIN, then bit 6 = "1" If Vref > VIN, then bit 6 = "0" 6. Operations in 3 through 5 above are executed for all other bits from bit 7 to bit 15. 7. The value stored in the A/D Successive Approximation Register by the time comparison for bit 15 has finished is held in it as the A/D conversion result. b6 7 8 9 10 11 12 13 14 b15 1000000000 n9 1 0 0 0 0 0 0 0 0 n 9 n 8 10000000 n9 n8 n7 n6 n5 n4 n3 n2 n1 1 2nd comparison 3rd comparison 10th comparison Conversion completed n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 Result of 1st comparison Result of 2nd comparison If Vref > VIN, then nX = 0 If Vref < VIN, then nX = 1 A/D Successive Approximation Register (ADiSAR) i = 0 Figure 11.3.2 Changes of the A/D Successive Approximation Register during A/D Convert Operation Note 1: The comparison voltage, Vref (the voltage fed from the D/A Converter into the comparator), is determined according to changes of the A/D Successive Approximation Register content. Shown below are the equations used to calculate the comparison voltage, Vref.

• If the A/D Successive Approximation Register content = 0 Vref [V] = 0
• If the A/D Successive Approximation Register content = 1 to 1,023 Vref [V] = (reference voltage VREF0 / 1,024) × (A/D Successive Approximation Register content – 0.5)

11-3732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The conversion result is stored in the 10-bit A/D Data Register (AD0DTn) corresponding to each converted channel. There is also an 8-bit A/D Data Register (AD08DTn) for each channel, from which the 8 high-order bits of the 10-bit A/D conversion result can be read out. The following shows the procedure for A/D conversion by a successive approximation method in each operation mode. (1) Single mode The convert operation stops when comparison for the A/D Successive Approximation Register bit 15 is completed. The content (A/D conversion result) of the A/D Successive Approximation Register is trans- ferred to the 10-bit A/D Data Registers 0–15 for the converted channel. (2) Single-shot scan mode When comparison for the A/D Successive Approximation Register bit 15 on a specified channel is completed, the content of the A/D Successive Approximation Register is transferred to the corresponding 10-bit A/D Data Registers 0–15, and the convert operations in said steps 2 to 7 are reexecuted for the next channel to be converted. In single-shot scan mode, the convert operation stops when A/D conversion in one specified scan loop is completed. (3) Continuous scan mode When comparison for the A/D Successive Approximation Register bit 15 on a specified channel is completed, the content of the A/D Successive Approximation Register is transferred to the corresponding 10-bit A/D Data Reg- isters 0–15, and the convert operations in said steps 2 to 7 are reexecuted for the next channel to be converted. In continuous scan mode, the convert operation is executed continuously until scan operation is forcibly termi- nated by setting the A/D conversion stop bit (Scan Mode Register 0 bit 6) to "1."

11.3.3 Comparator Operation

When comparator mode (single mode only) is selected, the A/D Converter functions as a comparator which compares analog input voltages with the comparison voltage that is set by software. When a comparison value is written to the successive approximation register, the A/D Converter starts “comparating” the analog input voltage selected by the Single Mode Register 1 analog input select bit with the value written into the successive approximation register. Once comparate begins, the following operation is automatically executed. 1. The A/D conversion/comparate completion bit in the A/D Single Mode Register 0 is cleared to "0." 2. The comparison voltage, Vref (Note 1), is fed from the D/A Converter into the comparator. 3. The comparison voltage, Vref, and the analog input voltage, VIN, are compared, and the comparison result will be stored in the comparate result flag for the corresponding channel. If Vref < VIN, then the comparate result flag = 0 If Vref > VIN, then the comparate result flag = 1 4. The comparate operation is stopped after storing the comparison result. The comparison result is stored in the A/D Comparate Data Register (AD0CMP)’s corresponding bit. Note 1: The comparison voltage, Vref (the voltage fed from the D/A Converter into the comparator), is determined according to changes of the A/D Successive Approximation Register content. Shown below are the equations used to calculate the comparison voltage, Vref.

• If the A/D Successive Approximation Register content = 0 Vref [V] = 0
• If the A/D Successive Approximation Register content = 1 to 1,023 Vref [V] = (reference voltage VREF0 / 1,024) x (A/D0 Successive Approximation Register content – 0.5)

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

11.3.4 Calculating the A/D Conversion Time

The A/D conversion time is expressed by the sum of dummy cycle time and actual execution cycle time. The following shows each time factor necessary to calculate the conversion time. 1. Start dummy time A time from when the CPU executed the A/D conversion start instruction to when the A/D Converter starts A/D conversion 2. A/D conversion execution cycle time If sample-and-hold is enabled, the sampling time is included in this execution cycle time. 3. Comparate execution cycle time 4. End dummy time A time from when the A/D Converter has finished A/D conversion to when the CPU can stably read out the conversion result from the A/D data register. 5. Scan to scan dummy time A time during single-shot or continuous scan mode from when the A/D Converter has finished A/D conversion on a channel to when it starts A/D conversion on the next channel. The equation to calculate the A/D conversion time is as follows: A/D conversion time = Start dummy time + Execution cycle time (+ Scan to scan dummy time + Execution cycle time + Scan to scan dummy time + Execution cycle time + Scan to scan dummy time .... + Execution cycle time) + End dummy time Note: • Enclosed in ( ) are the conversion time required for the second and subsequent channels to be converted in scan mode. (1) Calculating the conversion time during A/D conversion mode The following schematically shows the method for calculating the conversion time during A/D conversion mode. Start dummy Execution cycle A/D conversion start trigger Convert operation starts Transferred to the A/D data register <Scan mode> End dummy Start dummy Execution cycle Execution cycle <Single mode> Completed Execution cycle End dummy Scan to scan dummy Scan to scan dummy (Channel 0) (Channel 1) (Last channel) Figure 11.3.3 Conceptual Diagram of A/D Conversion Time

11-3932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (2) Calculating the conversion time when sample-and-hold is enabled The following schematically shows the method for calculating the conversion time when the sample-and- hold function is enabled. Start dummy Execution cycle A/D conversion start trigger Convert operation starts End dummy Completed Sampling time Figure 11.3.4 Conceptual Diagram of A/D Conversion Time when Sample-and-Hold is Enabled Table 11.3.1 Conversion Clock Periods in A/D Conversion Mode when Sample-and-Hold is Disabled or Normal Sample-and-Hold is Enabled (Shortest Period) Unit: BCLK Conversion speed Start dummy Execution cycle End dummy Scan to scan dummy (Note 1) (Note 2) 2BCLK mode Slow mode Normal speed 8 588 2 8 Double speed 8 336 2 8 Fast mode Normal speed 8 252 2 8 Double speed 8 168 2 8 Note 1: The same applies to both software and hardware triggers. Note 2: Only during scan mode operation, execution time per channel is added. Table 11.3.2 Conversion Clock Periods in A/D Conversion Mode when Fast Sample-and-Hold is Enabled (Shortest Period) Unit: BCLK Conversion speed Start dummy Execution cycle End dummy Scan to scan dummy (Note 1) (Note 2) 2BCLK mode Slow mode Normal speed 8 372 2 8 Double speed 8 192 2 8 Fast mode Normal speed 8 180 2 8 Double speed 8 96 2 8 Note 1: The same applies to both software and hardware triggers. Note 2: Only during scan mode operation, execution time per channel is added.

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 11.3.3 Conversion Clock Periods in Comparate Mode (Shortest Period) Unit: BCLK Conversion speed Start dummy Execution cycle End dummy 2BCLK mode Slow mode Normal speed 8 84 2 Double speed 8 48 2 Fast mode Normal speed 8 36 2 Double speed 8 24 2 Start dummy Execution cycle A/D conversion start trigger Convert operation starts Transferred to the comparate data register End dummy Completed (3) Calculating the conversion time during comparator mode The following schematically shows the method for calculating the conversion time during comparator mode. Figure 11.3.5 Conceptual Diagram of A/D Conversion Time during Comparator Mode

11-4132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 11.3.4 Conversion Clock Periods for Simultaneous Sampling when Normal Sample-and-Hold is Enabled (Shortest Period) Unit: BCLK Conversion speed Start dummy Execution Channel to Execution End (Note 1) cycle 1 channel dummy cycle 2 dummy 2BCLK mode Slow mode Normal speed 8 588 8 588 2 Double speed 8 336 8 336 2 Fast mode Normal speed 8 252 8 252 2 Double speed 8 168 8 168 2 Note 1: The same applies to both software and hardware triggers. Table 11.3.5 Conversion Clock Periods for Simultaneous Sampling when Fast Sample-and-Hold is Enabled (Shortest Period) Unit: BCLK Conversion speed Start dummy Execution Channel to Execution End (Note 1) cycle 1 channel dummy cycle 2 dummy 2BCLK mode Slow mode Normal speed 8 372 8 372 2 Double speed 8 192 8 192 2 Fast mode Normal speed 8 180 8 180 2 Double speed 8 96 8 96 2 Note 1: The same applies to both software and hardware triggers. (4) Calculating the conversion time during simultaneous sampling conversion The following schematically shows the method for calculating the conversion time during the simultaneous sampling conversion. Figure 11.3.6 Conceptual Diagram of A/D Conversion Time during Simultaneous Sampling Conversion Start dummy End dummy Sampling time Sampling dummy time Channel to channel dummy Execution cycle 1 Start trigger Convert operation starts Completed Execution cycle 2

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (5) Total A/D conversion time A total A/D conversion time in various modes are shown in the table below. Table 11.3.6 A/D Conversion Time (Total Time) Unit: BCLK Conversion start method Conversion speed Conversion mode (Note 1) Conversion time When fast sample- and-hold enabled Software and 2BCLK Slow Normal Single mode 598 382 hardware triggers mode mode speed Single-shot scan, (596 × n)+2 (380 × n)+2 (Note 2) n-channel scan/continuous mode Comparator mode 94 94 Simultaneous sampling 1194 762 Double Single mode 346 202 speed Single-shot scan, (344 × n)+2 (200 × n)+2 n-channel scan/continuous mode Comparator mode 58 58 Simultaneous sampling 690 402 Fast Normal Single mode 262 190 mode speed Single-shot scan, (260 × n)+2 (188 × n)+2 n-channel scan/continuous mode Comparator mode 46 46 Simultaneous sampling 522 378 Double Single mode 178 106 speed Single-shot scan, (176 × n)+2 (104 × n)+2 n-channel scan/continuous mode Comparator mode 34 34 Simultaneous sampling 354 210 Note 1: For single mode and comparator mode, this indicates an A/D conversion or comparate time per channel. For single- shot and continuous scan modes, this indicates an A/D conversion time per scan loop, and for simultaneous sampling, this indicates total time for the first and second conversion. Note 2: This indicates a time from when a register write cycle has finished to when an A/D conversion completion interrupt request is generated, or a time from when an event bus or other MJT event has occurred to when an A/D conversion completion interrupt request is generated. Note: • During 2BCLK mode, 1-2BCLK cycle(s) will be additionally generated at each start/end dummy cycle to synchronize with the clock.

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11.3.5 Accuracy of A/D Conversion

The accuracy of the A/D Converter is indicated by an absolute accuracy. The absolute accuracy refers to a difference expressed by LSB between the output code obtained by A/D converting the analog input voltages and the output code expected for an A/D converter with ideal characteristics. The analog input voltages used during accuracy measurement are the midpoint values of the voltage width in which an A/D converter with ideal characteristics produces the same output code. If VREF0 = 5.12 V, for example, the width of 1 LSB for a 10-bit A/D converter is 5 mV, so that 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, 25 mV and so on are selected as midpoints of the analog input voltage. If an A/D converter is said to have the absolute accuracy of ±2 LSB, it means that if the input voltage is 25 mV, for example, the output code expected for an A/D converter with ideal characteristics is H’005, and the actual A/ D conversion result is in the range of H’003 to H’007. Note that the absolute accuracy includes zero and full- scale errors. When actually using the A/D Converter, the analog input voltages are in the range of AVSS0 to VREF0. Note, however, that low VREF0 voltages result in a poor resolution. Note also that output codes for the analog input voltages from VREF0 to AVCC0 are always H’3FF. H'000 H'001 H'002 H'003 H'3FE H'3FF A/D conversion result (hexade cimal) → Analog input voltage [V] VREF0 1024 x 1 Ideal A/D conversion characteristics A/D conversion characteristics with infinite resolution

0 VREF0

Figure 11.3.7 Ideal A/D Conversion Characteristics Relative to the 10-bit A/D Converter’s Analog Input Voltages

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 H'000 H'001 H'002 H'003 H'004 H'005 H'006 Output code (hexadecimal) → Analog input voltage [mV] Ideal A/D conversion characteristics A/D conversion characteristics with infinite resolution 5 1 01 52 02 53 03 54 04 55 05 5 H'007 H'008 H'009 H'00A H'00B +2 LSB -2 LSB Figure 11.3.8 Absolute Accuracy of A/D Converter

11-4532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 If when the A/D Converter is A/D converting a selected analog input an overvoltage exceeding the converter’s absolute maximum rating is applied to any unselected analog input, the selector for the unselected analog input is inadvertently turned on by that overvoltage. This causes current to leak to the selected analog input, and the accuracy of the A/D conversion result is thereby deteriorated. The Inflow Current Bypass Circuit fixes the internal signals of unselected analog inputs to the GND level, so that when an overvoltage is applied, this circuit lets the current flow into the GND and prevents it from leaking to the selected analog input. That way, the accuracy of the A/D conversion result is prevented from being deteriorated by overvoltages. This circuit is always active while the A/D Converter is operating, and does not need to be controlled in software. Unselected channel Selected channel To the internal logic of the A/D Converte r OFF ON OFF ON ON OFF Fixed to GND level External input latched into Assist circuit Figure 11.4.1 Configuration of the Inflow Current Bypass Circuit Figure 11.4.2 Example of an Inflow Current Bypass Circuit where AVCC0 + 0.7 V or More is Applied Unselected channel Selected channel To the internal logic of the A/D Converte r OFF ON OFF ON ON OFF Assist circuit AVCC0 + 0.7 V or more Leakage current generated Sensor input Leakage current generated Unaffected by leakage

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 11.4.3 Example of an Inflow Current Bypass Circuit where GND – 0.7 V or Less is Applied Table 11.4.1 Accuracy Errors (Reference Values) when Current is Injected into AD0IN0 Note: • Since the influence of the accuracy on a contiguity channel becomes large, do not inject an over-current into the channel selected in the A/D0 simultaneous sampling analog input selection bit (ADSEL2) of the A/D single mode register 2 (ADSIM2). (No channel is selected if "0000"to"1011" is set up in 2 bit of ADSEL(s).) Unselected channel Selected channel To the internal logic of the A/D Converter OFF ON OFF ON ON OFF Assist circuit GND - 0.7V or less Leakage current generated Sensor input Unaffected by leakage Leakage current generated AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0I N5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 A D0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 2 m A 422222222222222 1 m A 222222222222222 0 m A 222222222222222 - 1 m A 122222222222222 - 2 m A 022222222222222 Accuracy error on overcurrent injected ports (Unit: LSB) Analog input pin Injection current

11-4732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 11.5.1 Internal Equivalent Circuit of the Analog Input Part

• Forcible termination during scan operation If A/D conversion is forcibly terminated by setting the A/D conversion stop bit (ADCSTP) to "1" during scan mode operation and the A/D data register for the channel that was in the middle of conversion is accessed for read, the read value shows the last conversion result that had been transferred to the data register before the conversion was forcibly terminated.
• Modification of the A/D converter related registers If the content of any register—A/D Conversion Interrupt Control Register, Single or Scan Mode Registers or A/D Successive Approximation Register, except the A/D conversion stop bit—is modified in the middle of A/D conver- sion, the conversion result cannot be guaranteed. Therefore, do not modify the contents of these registers while A/D conversion is in progress, or be sure to restart A/D conversion if register contents have been modified.
• Handling of analog input signals When using the A/D Converter with its sample-and-hold function disabled, make sure the analog input level is fixed during A/D conversion.
• A/D conversion completed bit read timing To read the A/D conversion completed bit (the Single Mode Register 0 ADSCMP bit or the Scan Mode Register

0 ADCCMP bit), as well as the A/D simultaneous sampling status bit (the A/D0 Single Mode Register 2

ADSH2ST bit) immediately after A/D conversion has started or has been terminated by the A/D conversion stop bit, be sure to adjust the timing 6 BCLK periods by performing a dummy read of their registers before read.

• Regarding the analog input pins Figure 11.5.1 shows the internal equivalent circuit of the A/D Converter’s analog input part. To obtain accurate A/D conversion results, make sure the internal capacitor C2 of the A/D conversion circuit is charged up within a predetermined time (sampling time). To meet this sampling time requirement, it is recommended that a stabilizing capacitor C1 be connected external to the chip. The method for determining the necessary value of this external stabilizing capacitor with respect to the output impedance of an analog output device is described below. Also, an explanation is made of the case where the output impedance of an analog output device is low and the external stabilizing capacitor C1 is unnecessary.
• Rated value of the absolute accuracy The rated value of the absolute accuracy is the actual performance value of the microcomputer alone, with influences of the power supply wiring and noise on the board not taken into account. When designing the application system, use caution for the board layout by, for example, separating the analog circuit power supply and ground (AVCC, AVSS and VREF) from those of the digital circuit and incorporating measures to prevent the analog input pins from being affected by noise, etc. from other digital signals.

Approximation Register (ADiSAR) 10-bit D/A ConverterVREF0 V2 Cin : input pin capacitance (approx. 10 pF) R2 : parasitic resistance of the selector (1-2 KΩ ) C2 : comparator capacitance (approx. 2.9 pF) Selector R2i i1 i2→ ADINn C1E C1 : parasitic capacitance of the board + stabilizing capacitance R1 : resistance of analog output device Analog output device Cin E : voltage of analog output device V2 : voltage across C2 VREF0 : analog reference voltage

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Thus, for a 10-bit resolution A/D Converter where C2 = 2.9 pF, C1 is 0.06 µF or more. Use this value for reference when setting up C1. (b) Maximum value of the output impedance R1 when C1 is not added If the external capacitor C1 in Figure 11.5.1 is not used, examination must be made to see if the analog output device can fully charge C2 within a predetermined time. First, the equation to find i2 when C1 in Figure 11.5.1 does not exist is shown below. Cin ×R1+C2(R1+R2) Cin ×R1+C2(R1+R2) (a) Example for calculating the external stabilizing capacitor C1 (addition of this capacitor is recommended) Assuming the R1 in Figure 11.5.1 is infinitely large and that the current necessary to charge the internal capacitor C2 is supplied from C1, if the potential fluctuation, Vp, caused by capacitance division of C1 and C2 is to be within 0.1 LSB, then what amount of capacitance C1 should have. For a 10-bit A/D Converter where VREF0 is 5.12 V, 1 LSB determination voltage = 5.12 V / 1,024 = 5 mV. The potential fluctuation of 0.1 LSB means a 0.5 mV fluctuation. Vp is also obtained by the equation below: The relationship between the capacitance division of C1 and C2 and the potential fluctuation, Vp, is obtained by the equation below: C1 + C2Vp = × (E - V2) Eq. A-1 2Vp = Vp1 × < Eq. A-2i VREF0 10 × 2× x - 1 i = 0 where Vp1 = potential fluctuation in the first A/D conversion performed and x = 10 for a 10-bit resolution A/D converter When Eq. A-1 and Eq. A-2 are solved, the following results: E - V2 Vp1C1 = C2 { - 1 } Eq. A-3 x - 1 i = 0 ADINi Conversion time for the first bit Sampling time Comparison time Repeated (10 times) for 10 bits Second bit Sampling time When sample-and-hold is disabled * When sample-and-hold is enabled, the analog input is sampled for only the first bit. Figure 11.5.2 A/D Conversion Timing Diagram Figure 11.5.2 shows an A/D conversion timing diagram. C2 must be charged up within the sampling time shown in this diagram. When the sample-and-hold function is disabled, the sampling time for the second and subsequent bits is about half that of the first bit. The sampling times at the respective conversion speeds are listed in the table 11.5.1. Note that when the sample-and-hold function is enabled, the analog input is sampled for only the first bit.

11-4932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 11.5.1 Sampling Time (in Which C2 Needs to Be Charged) Conversion start method Conversion speed Sampling time Sampling time for the for the first bit 2nd and subsequent bits 2BCLK mode Single mode Slow mode Normal speed 55BCLK 27BCLK (when sample-and-hold Double speed 31BCLK 15BCLK disabled or normal Fast mode Normal speed 23BCLK 11BCLK sample-and-hod enabled Double speed 15BCLK 7BCLK Single mode Slow m ode Normal speed 55BCLK – (when fast sample- Double speed 31BCLK – and-hold enabled) Fast mode Normal speed 23BCLK – Double speed 15BCLK – Comparator mode Slow m ode Normal speed 55BCLK – Double speed 31BCLK – Fast mode Normal speed 23BCLK – Double speed 15BCLK – Simultaneous Slow mode Normal speed 55BCLK – sampling Double speed 31BCLK – Fast mode Normal speed 23BCLK – Double speed 15BCLK – Therefore, the time in which C2 needs to be charged is found from Eq. B-1, as follows: Sampling time (in which C2 needs to be charged) > Cin × R1 + C2(R1 + R2) Eq. B-2 Thus, the maximum value of R1 can be obtained as a criterion from the equation below. Note, however, that for single mode (when sample-and-hold is disabled), the sampling time for the second and subsequent bits (C2 charging time) must be applied. C2 charging time - C2 × R2 R1 < Cin + C2

32192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 This page is blank for reasons of layout.

12.1 Outline of Serial Interface

12.2 Serial Interface Related Registers

12.3 Transmit Operation in CSIO Mode

12.4 Receive Operation in CSIO Mode

12.5 Notes on Using CSIO Mode

12.6 Transmit Operation in UART Mode

12.7 Receive Operation in UART Mode

12.8 Fixed Period Clock Output Function

12.9 Notes on Using UART Mode

12-232192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 The 32192/32195/32196 contains a total of six serial interface channels, SIO0–SIO5. Channels SIO0, SIO1, SIO4 and SIO5 can be selected between CSIO mode (clock-synchronous serial interface) and UART mode (clock-asynchronous serial interface). Channels SIO2 and SIO3 are UART mode only.

• CSIO mode (clock-synchronous serial interface) Communication is performed synchronously with a transfer clock, using the same clock on both transmit and receive sides. The transfer data length can be selected within the range from 8 to 16 bits long.
• UART mode (clock-asynchronous serial interface) Communication is performed at any transfer rate in any transfer data format. The transfer data length can be selected from 7, 8 and 9 bits. Channels SIO0–SIO5 each have a transmit DMA transfer and a receive DMA transfer request. These serial interfaces, when combined with the internal DMA Controller (DMAC), allow serial communication to be performed at high speed, as well as reduce the data communication load of the CPU. Serial interface is outlined below. Table 12.1.1 Outline of Serial interface Item Description Number of channels CSIO mode/UART mode: 4 channels (SIO0, SIO1, SIO4, SIO5) UART only : 2 channels (SIO2, SIO3) Clock During CSIO mode : Internal clock or external clock as selected (Note 1), clock polarity can be selected During UART mode : Internal clock only Transfer mode Transmit half-duplex, receive half-duplex, transmit/receive full-duplex BRG count source f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BLCK)/256 (Note 2) (when internal clock selected) f(BCLK)/2, f(BCLK)/16, f(BCLK)/64, f(BCLK)/512 f(BCLK): Peripheral clock operating frequency Data format CSIO mode : Data length = selectable in the range of 8–16 bits Order of transfer = selectable from LSB first or MSB first UART mode : Start bit = 1 bit Character length = 7, 8 or 9 bits Parity bit = Added (odd, even) or not added Stop bit = 1 or 2 bits Order of transfer = selectable from LSB first or MSB first Baud rate CSIO mode : 152 bits/sec to 5 Mbits/sec (when f(BCLK) = 40 MHz/internal clock selected) (Note 1) Max 2.5 Mbits/sec (when f(BCLK) = 40 MHz/external clock selected) UART mode : 19 bits/sec to 2.5 Mbits/sec (when f(BCLK) = 40 MHz) Error detection CSIO mode : Overrun error only UART mode : Overrun, parity and framing errors (Occurrence of any of these errors is indicated by an error sum bit) Fixed period clock When using SIO0, SIO1, SIO4 and SIO5 as UART mode, this function outputs a divided-by-2 BRG output function clock from the SCLK pin. Note 1: The maximum input frequency of an external clock during CSIO mode is f(BCLK)/16. Note 2: If f(BCLK) is selected as the count source, the BRG set value is subject to limitations.

12-332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Table 12.1.2 Interrupt Generation Functions of Serial Interface Serial Interface Interrupt Request Cause ICU Interrupt Request Sources SIO0 transmit buffer empty or transmission finished SIO0 transmit interrupt SIO0 reception finished or receive error SIO0 receive interrupt SIO1 transmit buffer empty or transmission finished SIO1 transmit interrupt SIO1 reception finished or receive error SIO1 receive interrupt SIO2 transmit buffer empty or transmission finished SIO2,3 transmit/receive interrupt (group interrupt) SIO2 reception finished or receive error SIO2,3 transmit/receive interrupt (group interrupt) SIO3 transmit buffer empty or transmission finished SIO2,3 transmit/receive interrupt (group interrupt) SIO3 reception finished or receive error SIO2,3 transmit/receive interrupt (group interrupt) SIO4 transmit buffer empty or transmission finished SIO4,5 transmit/receive interrupt (group interrupt) SIO4 reception finished or receive error SIO4,5 transmit/receive interrupt (group interrupt) SIO5 transmit buffer empty or transmission finished SIO4,5 transmit/receive interrupt (group interrupt) SIO5 reception finished or receive error SIO4,5 transmit/receive interrupt (group interrupt) Note: • The transmission-finished interrupt is effective when the internal clock is selected in UART or CSIO mode. Table 12.1.3 DMA Transfer Request Generation Functions of Serial Interface Serial Interface DMA Transfer Request DMAC Input Channels SIO0 transmit buffer empty DMA3, DMA4 SIO0 reception finished DMA4 SIO1 transmit buffer empty DMA6 SIO1 reception finished DMA3, DMA6 SIO2 transmit buffer empty DMA7 SIO2 reception finished DMA5 SIO3 transmit buffer empty DMA7, DMA9 SIO3 reception finished DMA8 SIO4 transmit buffer empty DMA0 SIO4 reception finished DMA1 SIO5 transmit buffer empty DMA2 SIO5 reception finished DMA3

12-432192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SCLKI0/SCLKO0 Baud Rate Generator (BRG) Internal data bus CSIO mode When internal clock selected CSIO mode UART mode When internal clock selected RXD0 TXD0 Receive interrupt request Transmit/ Receive Control Circuit SIO0 Transmit Buffer Register SIO0 Transmit Shift Register Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request To DMA3, DMA4SIO0 Receive Shift Register SIO0 Receive Buffer Register When external clock selected When UART mode selected Notes: • When f(BCLK) is selected as BRG cout source, the BRG set value is subjected to limitations.  SIO2 and SIO3 do not have the SCLKI/SCLKO function. SCLKI1/SCLKO1 To DMA6 To the Interrupt Controller (ICU) SIO0 SIO1 SIO2 SIO3 RXD1 TXD1 Transmit/ Receive Control Circuit SIO1 Transmit Shift Register SIO1 Receive Shift Register To DMA7RXD2 TXD2 Transmit/ Receive Control Circuit SIO2 Transmit Shift Register SIO2 Receive Shift Register To DMA7, DMA9 RXD3 TXD3 Transmit/ Receive Control Circuit SIO3 Transmit Shift Register SIO3 Receive Shift Register Receive interrupt request Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request Receive interrupt request Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request Receive interrupt request Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request To the Interrupt Controller (ICU) To DMA8 To DMA5 To DMA3, DMA6 To DMA4 To the Interrupt Controller (ICU) BCLK 1/2 Clock Divider SIO4 SIO4 Transmit Shift Register SIO4 Receive Shift Register Receive interrupt request Transmit interrupt request SIO5 SIO5 Transmit Shift Register SIO5 Receive Shift Register RXD4 TXD4 RXD5 TXD5 Receive interrupt request Transmit interrupt request To the Interrupt Controller (ICU) SCLKI4/SCLKO4 SCLKI5/SCLKO5 To DMA0 Receive DMA transfer request Transmit DMA transfer request To DMA1 To DMA2 Receive DMA transfer request Transmit DMA transfer request To DMA3 Transmit/ Receive Control Circuit Transmit/ Receive Control Circuit Figure 12.1.1 Block Diagram of Serial Interfaces

12-532192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Shown below is a serial interface related register map. Serial Interface Related Register Map (1/2) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0100 SIO23 Interrupt Request Status Register SIO03 Interrupt Request Mask Register 12-9 (SI23STAT) (SI03MASK) 12-10 H'0080 0102 SIO03 Interrupt Request Source Select Register (Use inhibited area) 12-11 (SI03SEL) | (Use inhibited area) H'0080 0110 SIO0 Transmit Control Register SIO0 Transmit/Receive Mode Register 12-14 (S0TCNT) (S0MOD) 12-15 H'0080 0112 SIO0 Transmit Buffer Register 12-19 (S0TXB) H'0080 0114 SIO0 Receive Buffer Register 12-20 (S0RXB) H'0080 0116 SIO0 Receive Control Register SIO0 Baud Rate Register 12-21 (S0RCNT) (S0BAUR) 12-24 H'0080 0118 SIO0 Special Mode Register (Use inhibited area) 12-27 (S0SMOD) | (Use inhibited area) H'0080 0120 SIO1 Transmit Control Register SIO1 Transmit/Receive Mode Register 12-14 (S1TCNT) (S1MOD) 12-15 H'0080 0122 SIO1 Transmit Buffer Register 12-19 (S1TXB) H'0080 0124 SIO1 Receive Buffer Register 12-20 (S1RXB) H'0080 0126 SIO1 Receive Control Register SIO1 Baud Rate Register 12-21 (S1RCNT) (S1BAUR) 12-24 H'0080 0128 SIO1 Special Mode Register (Use inhibited area) 12-27 (S1SMOD) | (Use inhibited area) H'0080 0130 SIO2 Transmit Control Register SIO2 Transmit/Receive Mode Register 12-14 (S2TCNT) (S2MOD) 12-15 H'0080 0132 SIO2 Transmit Buffer Register 12-19 (S2TXB) H'0080 0134 SIO2 Receive Buffer Register 12-20 (S2RXB) H'0080 0136 SIO2 Receive Control Register SIO2 Baud Rate Register 12-21 (S2RCNT) (S2BAUR) 12-24 H'0080 0138 SIO2 Special Mode Register (Use inhibited area) 12-27 (S2SMOD) | (Use inhibited area) H'0080 0140 SIO3 Transmit Control Register SIO3 Transmit/Receive Mode Register 12-14 (S3TCNT) (S3MOD) 12-15 H'0080 0142 SIO3 Transmit Buffer Register 12-19 (S3TXB) H'0080 0144 SIO3 Receive Buffer Register 12-20 (S3RXB) H'0080 0146 SIO3 Receive Control Register SIO3 Baud Rate Register 12-21 (S3RCNT) (S3BAUR) 12-24 H'0080 0148 SIO3 Special Mode Register (Use inhibited area) 12-27 (S3SMOD) | (Use inhibited area) H'0080 0A00 SIO45 Interrupt Request Status Register SIO45 Interrupt Request Mask Register 12-9 (SI45STAT) (SI45MASK) 12-10 H'0080 0A02 SIO45 Interrupt Request Source Select Register (Use inhibited area) 12-11 (SI45SEL) | (Use inhibited area) H'0080 0A10 SIO4 Transmit Control Register SIO4 Transmit/Receive Mode Register 12-14 (S4TCNT) (S4MOD) 12-15 H'0080 0A12 SIO4 Transmit Buffer Register 12-19 (S4TXB) H'0080 0A14 SIO4 Receive Buffer Register 12-20 (S4RXB) H'0080 0A16 SIO4 Receive Control Register SIO4 Baud Rate Register 12-21 (S4RCNT) (S4BAUR) 12-24

12-632192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

12.2.1 SIO Interrupt Related Registers

The SIO interrupt related registers are used to control the interrupt request signals output from SIO to the Interrupt Controller (ICU), as well as select the source of each interrupt request. (1) Interrupt request status bit This status bit is used to determine whether an interrupt is requested. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0." Writing "1" has no effect; the bit retains the status it had before the write. Because this bit is unaffected by the interrupt request mask bit, it can also be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "1" to enable interrupt requests or "0" to disable interrupt requests. Figure 12.2.1 Interrupt Request Status and Mask Registers To the Interrupt Controller Interrupt request from each peripheral function Interrupt request status Data bus Set  Group interrupt Interrupt request mask clear F/F F/F Data=0 Serial Interface Related Register Map (2/2) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0A18 SIO4 Special Mode Register (Use inhibited area) 12-27 (S4SMOD) | (Use inhibited area) H'0080 0A20 SIO5 Transmit Control Register SIO5 Transmit/Receive Mode Register 12-14 (S5TCNT) (S5MOD) 12-15 H'0080 0A22 SIO5 Transmit Buffer Register 12-19 (S5TXB) H'0080 0A24 SIO5 Receive Buffer Register 12-20 (S5RXB) H'0080 0A26 SIO5 Receive Control Register SIO5 Baud Rate Register 12-21 (S5RCNT) (S5BAUR) 12-24 H'0080 0A28 SIO5 Special Mode Register (Use inhibited area) 12-27 (S5SMOD)

12-732192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 12.2.2 Example for Clearing Interrupt Request Status b4 5 b7 Interrupt request status Initial state Bit 6 event occurs Interrupt request Bit 4 event occurs Only bit 6 cleared Bit 4 data retained b4 5 b7 1 1 0 1 Write to the interrupt request status Example for clearing interrupt request status 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 Program example ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */  To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1: ISTAT1 (0x02 bit) To clear an interrupt request status, always be sure to write 1 to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. b4 5 6 b7 Interrupt request status Bit 6 event occurs Bit 4 event occurs Only bit 6 cleared Bit 4 also cleared 0 0 1 0 1 0 1 0 0 0 0 0 Read 0 0 1 0 0 0 0 0 Clear bit 6 (ANDing with 1101) Write ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */

12-832192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Receive DMA transfer request RFIN (Reception Finished bit) Note:  No reception-finished DMA transfer requests are generated if a receive error occurs. Figure 12.2.4 Reception-finished DMA Transfer Request (3) Selecting the source of an interrupt request The interrupt request signals sent from each SIO to the Interrupt Controller (ICU) are broadly classified into transmit interrupts and receive interrupts. Transmit interrupt requests can be generated when the transmit buffer is empty or transmission is finished, and the receive interrupt requests can be generated when recep- tion is finished or an receive error is detected, as selected by the Interrupt Request Source Select Registers (SI03SEL, SI45SEL). Notes: • No interrupt request signals are generated unless interrupts are generated by the SIO Interrupt Request Mask Register after enabling the TEN (Transmit Enable) bit or REN (Receive Enable) bit for the corresponding SIO.

• SIO2 and SIO3 together comprise one interrupt group, so do SIO4 and SIO5.
• The transmission-finished interrupt is effective when the internal clock is selected in UART or CSIO mode. (4) Notes on using transmit interrupts When the interupt request is enable in SIO Interrupt Request Mask Register and the transmit buffer empty interrupt is selected in SIO Interrupt Request Source Slect Resgister, a transmit interrupt request is gener- ated upon enabling the corresponding TEN (Transmit Enable) bit. (5) About DMA transfer requests from SIO Each SIO can generate a transmit DMA transfer and a reception-finished DMA transfer request. These DMA transfer requests can be generated by enabling each SIO’s corresponding TEN (Transmit Enable) bit or REN (Receive Enable) bit. When using DMA transfers to communicate with external devices, be sure to set the DMA Controller (DMAC) before enabling the TEN or REN bit. No reception-finished DMA transfer requests are generated if a receive error occurs.
• Transmit DMA transfer request Generated when the transmit buffer is empty and the TEN bit is enabled. TEN (Transmit Enable bit) TBE (Transmit Buffer Empty bit) Transmit DMA transfer request Figure 12.2.3 Transmit DMA Transfer Request
• Reception-finished DMA transfer request A DMA transfer request is generated when the receive buffer is filled.

12-932192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SIO23 Interrupt Request Status Register (SI23STAT) <Address: H’0080 0100> 123456 b 7b0 IRQT2 IRQR3 IRQT3IRQR2 00000 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0." 00

4 IRQT2 0: Interrupt not requested R (Note 1)

SIO2 transmit interrupt request status bit 1: Interrupt requested

5 IRQR2 0: Interrupt not requested R (Note 1)

SIO2 receive interrupt request status bit 1: Interrupt requested

6 IRQT3 0: Interrupt not requested R (Note 1)

SIO3 transmit interrupt request status bit 1: Interrupt requested

7 IRQR3 0: Interrupt not requested R (Note 1)

SIO3 receive interrupt request status bit 1: Interrupt requested Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. SIO45 Interrupt Request Status Register (SI45STAT) <Address: H’0080 0A00> 123456 b 7b0 IRQT4 IRQR5 IRQT5IRQR4 0000 0 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W

0 IRQT4 0: Interrupt not requested R (Note 1)

SIO4 transmit interrupt request status bit 1: Interrupt requested

1 IRQR4 0: Interrupt not requested R (Note 1)

SIO4 receive interrupt request status bit 1: Interrupt requested

2 IRQT5 0: Interrupt not requested R (Note 1)

SIO5 transmit interrupt request status bit 1: Interrupt requested

3 IRQR5 0: Interrupt not requested R (Note 1)

SIO5 receive interrupt request status bit 1: Interrupt requested 4–7 No function assigned. Fix to "0." 00 Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. These registers indicate the transmit/receive interrupt requests from each SIO. [Setting the interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the interrupt request status bit] This bit is cleared by writing "0" in software. Note: • If the status bit is set in hardware at the same time it is cleared in software, the former has priority and the status bit is set. When writing to the SIO Interrupt Request Status Register, make sure only the bits to be cleared are set to "0" and all other bits are set to "1." Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write.

12-1032192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SIO03 Interrupt Request Mask Register (SI03MASK) <Address: H’0080 0101> 9 1 01 11 21 31 4 b 1 5b8 T0MASK R0MASK T1MASK R1MASK T2MASK R2MASK T3MASK R3MASK 00000000 <Upon exiting reset: H’00> b Bit Name Function R W

8 T0MASK 0: Mask (disable) interrupt request R W

SIO0 transmit interrupt request enable bit 1: Enable interrupt request

9 R0MASK 0: Mask (disable) interrupt request R W

SIO0 receive interrupt request enable bit 1: Enable interrupt request

10 T1MASK 0: Mask (disable) interrupt request R W

SIO1 transmit interrupt request enable bit 1: Enable interrupt request

11 R1MASK 0: Mask (disable) interrupt request R W

SIO1 receive interrupt request enable bit 1: Enable interrupt request

12 T2MASK 0: Mask (disable) interrupt request R W

SIO2 transmit interrupt request enable bit 1: Enable interrupt request

13 R2MASK 0: Mask (disable) interrupt request R W

SIO2 receive interrupt request enable bit 1: Enable interrupt request

14 T3MASK 0: Mask (disable) interrupt request R W

SIO3 transmit interrupt request enable bit 1: Enable interrupt request

15 R3MASK 0: Mask (disable) interrupt request R W

SIO3 receive interrupt request enable bit 1: Enable interrupt request SIO45 Interrupt Request Mask Register (SI45MASK) <Address: H’0080 0A01> 9 1 01 11 21 31 4 b 1 5b8 T4MASK R5MASK T5MASKR4MASK 0000 0 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W

8 T4MASK 0: Mask (disable) interrupt request R W

SIO4 transmit interrupt request enable bit 1: Enable interrupt request

9 R4MASK 0: Mask (disable) interrupt request R W

SIO4 receive interrupt request enable bit 1: Enable interrupt request

10 T5MASK 0: Mask (disable) interrupt request R W

SIO5 transmit interrupt request enable bit 1: Enable interrupt request

11 R5MASK 0: Mask (disable) interrupt request R W

SIO5 receive interrupt request enable bit 1: Enable interrupt request 12–15 No function assigned. Fix to "0." 00 These registers enable or disable the interrupt requests generated by each SIO. Interrupt requests from any SIO are enabled by setting its corresponding interrupt request enable bit to "1."

12-1132192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 SIO03 Interrupt Request Source Select Register (SI03SEL) <Address: H’0080 0102> 123456 b 7b0 ISR0IST0 IST1 IST2 IST3 ISR3 ISR2ISR1 00000000 <Upon exiting reset: H’00> b Bit Name Function R W

0 IST0 0: Transmit buffer empty interrupt R W

SIO0 transmit interrupt request source select bit 1: Transmission finished interrupt

1 IST1 0: Transmit buffer empty interrupt R W

SIO1 transmit interrupt request source select bit 1: Transmission finished interrupt

2 IST2 0: Transmit buffer empty interrupt R W

SIO2 transmit interrupt request source select bit 1: Transmission finished interrupt

3 IST3 0: Transmit buffer empty interrupt R W

SIO3 transmit interrupt request source select bit 1: Transmission finished interrupt

4 ISR0 0: Reception finished interrupt R W

SIO0 receive interrupt request source select bit 1: Receive error interrupt

5 ISR1 0: Reception finished interrupt R W

SIO1 receive interrupt request source select bit 1: Receive error interrupt

6 ISR2 0: Reception finished interrupt R W

SIO2 receive interrupt request source select bit 1: Receive error interrupt

7 ISR3 0: Reception finished interrupt R W

SIO3 receive interrupt request source select bit 1: Receive error interrupt SIO45 Interrupt Request Source Select Register (SI45SEL) <Address: H’0080 0A02> 123456 b 7b0 ISR4IST4 IST5 ISR 5 00 00 0 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W

0 IST4 0: Transmit buffer empty interrupt R W

SIO4 transmit interrupt request source select bit 1: Transmission finished interrupt

1 IST5 0: Transmit buffer empty interrupt R W

SIO5 transmit interrupt request source select bit 1: Transmission finished interrupt 2, 3 No function assigned. Fix to "0." 00

4 ISR4 0: Reception finished interrupt R W

SIO4 receive interrupt request source select bit 1: Receive error interrupt

5 ISR5 0: Reception finished interrupt R W

SIO5 receive interrupt request source select bit 1: Receive error interrupt 6, 7 No function assigned. Fix to "0." 00 These registers select the source of interrupt requests generated by each SIO when transmit or receive opera- tion is completed.

12-1232192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 (1) SIOn transmit interrupt request source select bit [When set to "0"] The transmit buffer empty interrupt is selected. A transmit buffer empty interrupt request is generated when data is transferred from the transmit buffer register to the transmit shift register. Also, a transmit buffer empty interrupt request is generated when the TEN (Transmit Enable) bit is set to "1" (interrupt enabled). [When set to "1"] The transmission finished (transmit shift buffer empty) interrupt is selected. A transmission finished interrupt request is generated when all of the data in the transmit shift register has been transferred. Note: • Do not select the transmission finished interrupt when an external clock is selected in CSIO mode. (2) SIOn receive interrupt request source select bit [When set to "0"] The reception finished (receive buffer full) interrupt is selected. A reception finished interrupt request is also generated when a receive error (except overrun error) occurs. [When set to "1"] The receive error interrupt is selected. Following types of errors constitute a receive error:

• CSIO mode: Overrun error
• UART mode: Overrun, parity and framing errors

12-1332192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07 Figure 12.2.5 Block Diagram of SIO2,3 Transmit Interrupt Requests Figure 12.2.6 Block Diagram of SIO4,5 Transmit Interrupt Requests F/F F/F R3MASK IRQR3 F/F F/F T3MASK IRQT3 F/F F/F R2MASK IRQR2 F/F F/F T2MASK IRQT2 b15 b14 b13 b12 Data bus SIO2, 3 transmit/receive interrupt requests(Level) 4-source inputs <SI23STAT : H'0080 0100> <SI03MASK : H'0080 0101> F/F SIO2 reception finished SIO2 receive error ISR2 F/F SIO2 transmit buffer empty SIO2 transmission finished IST2 F/F SIO3 transmit buffer empty SIO3 transmission finished IST3 F/F SIO3 reception finished SIO3 receive error ISR3 <SI03SEL : H'0080 0102> F/F F/F R5MASK IRQR5 F/F F/F T5MASK IRQT5 F/F F/F R4MASK IRQR4 F/F F/F T4MASK IRQT4 b11 b10 Data bus SIO4, 5 transmit/receive interrupt requests(Level) 4-source inputs F/F SIO4 reception finished SIO4 receive error ISR4 F/F SIO4 transmit buffer empty SIO4 transmission finished IST4 F/F SIO5 transmit buffer empty SIO5 transmission finished IST5 F/F SIO5 reception finished SIO5 receive error ISR5 <SI45STAT : H'0080 0A00> <SI45MASK : H'0080 0A01> <SI45SEL : H'0080 0A02>

12-1432192/32195/32196 Group Hardware Manual Rev.1.10 REJ09B0123-0110 Apr.06.07

12.2.2 SIO Transmit Control Registers

SIO0 Transmit Control Register (S0TCNT) <Address: H'0080 0110> SIO1 Transmit Control Register (S1TCNT) <Address: H'0080 0120> SIO2 Transmit Control Register (S2TCNT) <Address: H'0080 0130> SIO3 Transmit Control Register (S3TCNT) <Address: H'0080 0140> SIO4 Transmit Control Register (S4TCNT) <Address: H'0080 0A10> SIO5 Transmit Control Register (S5TCNT) <Address: H'0080 0A20> 123456 b 7b0 TSTAT TBE TENCDIV 0 10 1 00 0 0 <Upon exiting reset: H’12> b Bit Name Function R W 0, 1 No function assigned. Fix to "0." 00 2, 3 CDIV b2 b3 (Note 1) R W BRG count source select bit 0 0: Select f(BCLK) or f(BCLK)/2 0 1: Select f(BCLK) or f(BCLK)/2 divided by 8 1 0: Select f(BCLK) or f(BCLK)/2 divided by 32 1 1: Select f(BCLK) or f(BCLK)/2 divided by 256 4 No function assigned. Fix to "0." 00

5 TSTAT 0: Transmission stopped and no data in transmit buffer register R –

Transmit status bit 1: Transmitting now or data present in transmit buffer register

6 TBE 0: Data present in transmit buffer register R –

Transmit buffer empty bit 1: No data in transmit buffer register

7 TEN 0: Disable transmission R W

Transmit enable bit 1: Enable transmission Note 1: The selection between f(BCLK) and f(BCLK)/2 is made with the SIOn Special Mode Register (SnSMOD). (1) CDIV (BRG count source select) bits (Bits 2 and 3) These bits select the count source for BRG (the Baud Rate Generator). (2) TSTAT (Transmit Status) bit (Bit 5) [Set condition] This bit is set to "1" by a write to the transmit buffer register while transmission is enabled. [Clear condition] This bit is cleared to "0" when transmission is idle (no data in the transmit shift register) and no data exists in the transmit buffer register. This bit is also cleared by clearing the transmit enable bit. (3) TBE (Transmit Buffer Empty) bit (Bit 6) [Set condition] This bit is set to "1" when data is transferred from the transmit buffer register to the transmit shift register and the transmit buffer register is thereby emptied. This bit is also set by clearing the transmit enable bit to "0." [Clear condition] This bit is cleared to "0" by writing data to the lower byte of the transmit buffer register while transmis- sion is enabled (TEN = "1"). (4) TEN (Transmit Enable) bit (Bit 7) Transmission is enabled by setting this bit to "1" and disabled by clearing this bit to "0." If this bit is cleared to "0" while transmitting data, the transmit operation stops.

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