32180

32180 RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

Mitsubishi 32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series User's Manual 3218032180 Group Rev. 1.0 Jan. 24, 2003 The latest version of this manual is published at the Mitsubishi microcomputer home page shown above. Please make sure you are using the latest version of the manual. http://www.infomicom.maec.co.jp/

Keep safety first in your circuit designs! Notes regarding these materials

• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. T rouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appro- priate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap.  These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.  Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, pro- grams, algorithms, or circuit application examples contained in these materials.  All information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distribu- tor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http:// www.mitsubishichips.com).  When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and prod- ucts. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.  Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon- ductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aero- space, nuclear, or undersea repeater use.  The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or repro- duce in whole or in part these materials.  If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be im- ported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.  Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

32180 Group User’s Manual

Rev. Date of Issue Contents of Revision Page Changes Made (1/1)

Revision History

1.0 Jan. 24, 2003 – First edition issued

 Guide to Understanding the Register Table (1) Bit number: Indicates a register’s bit number. (2) Register border: The registers enclosed with thick border lines must be accessed in halfwords or words. (3) Status after reset: The initial state of each register after reset is indicated in hexadecimal or binary. (4) Status after reset: The initial state of each register after reset is indicated bitwise. 0: This bit is “0” after reset. 1: This bit is “1” after reset. ?: This bit is undefined after reset. (5) The shaded bits mean that they have no functions assigned. (6) Read conditions: R: This bit can be accessed for read. ?: The value read from this bit is undefined. (Reading this bit has no effect.) 0: The value read from this bit is always “0”. 1: The value read from this bit is always “1”. (7) Write conditions: W: This bit can be accessed for write. N: This bit is write protected. 0: To write to this bit, always write “0”. 1: To write to this bit, always write “1”. –: Writing to this bit has no effect. (It does not matter whether this bit is set to “0” or “1” by writing in software.) Note: Care must be taken when writing to this bit. See Note in each register table. XXXRegister(XXX) <Address: H’XXXX XXXX> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 AAA BBB CCC 000 0 0 0 0 0 0 0 0 0 0 0 0 0 <After reset: H’0000> b Bit name Function R W 3–15 No function assigned. Fix to “0”.0 0 Note 1: Only writing “0” is effective. Writing “1” has no effect, in which case the bit retains the value it had before the write.  Notation of active-low pins (signals) The symbol “#” suffixed to the pin (or signal) names means that the pins (or signals) are active-low. Before Use (2) (4) (6) (7) (3) (1) (5)

(1) Table of contents CHAPTER 1 OVERVIEW CHAPTER 2 CPU CHAPTER 3 ADDRESS SPACE

(2) CHAPTER 4 EIT CHAPTER 5 INTERRUPT CONTROLLER (ICU) CHAPTER 6 INTERNAL MEMORY

(3) CHAPTER 7 RESET CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS CHAPTER 9 DMAC

(4) CHAPTER 10 MULTIJUNCTION TIMERS

(5) 10.8.17 0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes -10-192

(6) CHAPTER 11 A-D CONVERTERS CHAPTER 12 SERIAL I/O

(7) CHAPTER 13 CAN MODULE

(8) CHAPTER 14 REAL TIME DEBUGGER (RTD) CHAPTER 15 EXTERNAL BUS INTERFACE CHAPTER 16 WAIT CONTROLLER

(9) CHAPTER 17 RAM BACKUP MODE CHAPTER 18 OSCILLATOR CIRCUIT CHAPTER 19 JTAG CHAPTER 20 POWER SUPPLY CIRCUIT

(10) CHAPTER 21 ELECTRICAL CHARACTERISTICS CHAPTER 22 TYPICAL CHARACTERISTICS APPENDIX 1 MECHANICAL SPECIFICAITONS APPENDIX 2 INSTRUCTION PROCESSING TIME APPENDIX 3 PROCESSING OF UNUSED PINS APPENDIX 4 SUMMARY OF PRECAUTIONS

(11)

(12) This page is blank for reasons of layout.

1.1 Outline of the 32180 Group

1.2 Block Diagram

1.3 Pin Functions

1.4 Pin Assignments

32180 Group User’s Manual (Rev.1.0) The 32180 group (hereafter simply the 32180) belongs to the M32R/ECU series in the M32R family of Mitsubishi microcomputers. For details about the current development status of the 32180, please contact your nearest office of Mitsubishi or its distributor. Table 1.1.1 Product List Type Name ROM Size RAM Size Package Type Operating Ambient Temperature M32180F8VFP 1 Mbyte 48 Kbytes 240-pin QFP: 240P6Y-A (0.5 mm pitch) –40°C to 125°C (@64 MHz) M32180F8TFP 1 Mbyte 48 Kbytes 240-pin QFP: 240P6Y-A (0.5 mm pitch) –40°C to 85°C (@80 MHz)

1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU)

(1) Based on a RISC architecture  The 32180 is a group of 32-bit RISC single-chip microcomputers. The M32R-FPU in this group of microcomputers incorporates a fully IEEE 754-compliant, single-precision FPU in order to materialize the common instruction set and the high-precision arithmetic operation of the M32R CPU. The 32180 products listed in the above table are built around the M32R-FPU and incorporates flash memory, RAM and various peripheral functions, all integrated into a single chip.  The M32R-FPU is constructed based on a RISC architecture. Memory is accessed using load/store instructions, and various arithmetic/logic operations are executed using register-to-register operation instructions.  The internally has sixteen 32-bit general-purpose registers. The instruction set consists of 100 dis- crete instructions in total (83 instructions common to the M32R family plus 17 FPU and extended instructions). These instructions are either 16 bits or 32 bits long.  In addition to the ordinary load/store instructions, the M32R-FPU supports compound instructions such as Load & Address Update and Store & Address Update. These instructions help to speed up data transfers. (2) Five-stage pipelined processing  The M32R-FPU supports five-stage pipelined instruction processing consisting of Instruction Fetch, Decode, Execute, Memory Access and Write Back (processed in six stages when performing float- ing-point arithmetic). Not just load/store instructions and register-to-register operation instructions, but also floating-point arithmetic instructions and compound instructions such as Load & Address Update and Store & Address Update are executed in one CPUCLK period (which is equivalent to 12.5 ns when f(CPUCLK) = 80 MHz).  Although instructions are supplied to the execution stage in the order in which they were fetched, it is possible that if the load/store instruction supplied first is extended by wait cycles inserted in memory access, the subsequent register-to-register operation instruction will be executed before that instruc- tion. Using such a facility, which is known as the “out-of-order-completion” mechanism, the M32R- FPU is able to control instruction execution without wasting clock cycles. (3) Compact instruction code  The M32R-FPU supports two instruction formats: one 16 bits long, and one 32 bits long. Use of the 16-bit instruction format especially helps to suppress the code size of a program.  Moreover, the availability of 32-bit instructions makes programming easier and provides higher per- formance at the same clock speed than in architectures where the address space is segmented. For example, some 32-bit instructions allow control to jump to an address 32 Mbytes forward or backward from the currently executed address in one instruction, making programming easy.

32180 Group User’s Manual (Rev.1.0)

1.1.2 Built-in Multiplier/Accumulator

(1) Built-in high-speed multiplier  The M32R-FPU contains a 32 bits × 16 bits high-speed multiplier which enables the M32R-FPU to execute a 32 bits × 32 bits integral multiplication instruction in three CPUCLK periods. (2) DSP-comparable sum-of-products instructions  The M32R-FPU supports the following four types of sum-of-products calculation instructions (or multipli- cation instructions) which each can be executed in one CPUCLK period using a 56-bit accumulator. (1) 16 high-order bits of register × 16 high-order bits of register (2) 16 low-order bits of register × 16 low-order bits of register (3) All 32 bits of register × 16 high-order bits of register (4) All 32 bits of register × 16 low-order bits of register  The M32R-FPU has some special instructions to round the value stored in the accumulator to 16 or 32 bits or shift the accumulator value before storing in a register to have its digits adjusted. Because these instructions too are executed in one CPUCLK period, when used in combination with high- speed data transfer instructions such as Load & Address Update or Store & Address Update, they enable the M32R-FPU to exhibit superior data processing capability comparable to that of a DSP.

1.1.3 Built-in Single-precision FPU

 The M32R-FPU supports single-precision floating-point arithmetic fully compliant with IEEE 754 stan- dards. Specifically, five exceptions specified in IEEE 754 standards (Inexact, Underflow, Division by Zero, Overflow and Invalid Operation) and four rounding modes (round to nearest, round toward 0, round toward + Infinity and round toward – Infinity) are supported. What’s more, because general- purpose registers are used to perform floating-point arithmetic, the overhead associated with trans- ferring the operand data can be reduced.

1.1.4 Built-in Flash Memory and RAM

 The 32180 contains a RAM that can be accessed with zero wait state, allowing to design a high-speed embedded system.  The internal flash memory can be written to while mounted on a printed circuit board (on-board writ- ing). Use of flash memory facilitates development work, because the chip used at the development stage can be used directly in mass-production, allowing for a smooth transition from prototype to mass-production without the need to change the printed circuit board.  The internal flash memory can be rewritten as many as 100 times.  The internal flash memory has a virtual flash emulation function, allowing the internal RAM to be superficially mapped into part of the internal flash memory. When combined with the internal Real- Time Debugger (RTD) and the M32R family’s common debug interface (Scalable Debug Interface or SDI), this function makes the ROM table data tuning easy.  The internal RAM can be accessed for reading or rewriting data from an external device indepen- dently of the M32R-FPU by using the Real-Time Debugger. The external device is communicated using the Real-Time Debugger’s exclusive clock-synchronized serial I/O.

32180 Group User’s Manual (Rev.1.0)

1.1.5 Built-in Clock Frequency Multiplier

 The 32180 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1 below. XIN pin (8MHz-10MHz) BCLK (peripheral clock) (16MHz-20MHz) CPUCLK (CPU clock) (64MHz-80MHz) PLL Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier Table 1.1.2 Clock Functional Block Features CPUCLK  CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for the M32R-FPU core, internal flash memory and internal RAM. BCLK  Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency for the internal peripheral I/O and external data bus. Clock output (BCLK pin output)  A clock with the same frequency as f(BCLK) is output from this pin.

1.1.6 Powerful Peripheral Functions Built-in

(1) Multijunction timer (MJT) (2) 10-channel DMAC (3) Two 16-channel A-D converters (ADC) (4) 6-channel high-speed serial I/O (SIO) (5) Real-time debugger (RTD) (6) 8-level interrupt controller (ICU) (7) Three operation modes (8) Wait controller (9) 2-channel Full-CAN (10) M32R family’s common debug function (Scalable Debug Interface or SDI)

32180 Group User’s Manual (Rev.1.0) Figure 1.2.1 Block Diagram of the 32180 PLL Clock Generator Internal Bus Interface AddressData Internal RAM (48 Kbytes) Internal Flash Memory (1 Mbytes = 1,024 Kbytes) M32R-FPU Core (80 MHz) Multiplier/Accumulator (32 bits × 16 bits + 56 bits) DMAC (10 channels) Multijunction Timer (64 channels) Serial I/O (6 channels) A-D Converter × 2 (A-D0 : 10-bit converter, 16 channels) (A-D1 : 10-bit converter, 16 channels) Wait Controller Interrupt Controller (32 sources, 8 levels) Real-Time Debugger (RTD) External Bus Interface Internal 32-bit bus Input/output ports, 158 lines Full CAN (2 channels) Single-precision FPU (fully IEEE 754 compliant) Internal 16-bit bus Internal 32-bit bus Internal Power Supply Generator (VDC)

32180 Group User’s Manual (Rev.1.0) Table 1.2.1 Features of the 32180 (1/2) Functional Block Features M32R-FPU CPU core  Implementation: Five-stage pipelined instruction processing (processed in six stages when performing floating-point arithmetic)  Internal 32-bit structure of the core  Register configuration General-purpose registers: 32 bits × 16 registers Control registers: 32 bits × 6 registers  Instruction set 16 and 32-bit instruction formats 100 discrete instructions and six addressing modes  Internal multiplier/accumulator (32 bits × 16 bits + 56 bits)  Internal single-precision floating-point arithmetic unit (FPU) RAM  Capacity: 48 Kbytes, accessible with zero wait state  The internal RAM can be accessed for reading or rewriting data from the outside independently of the M32R-FPU by using the Real-Time Debugger, without ever causing the CPU performance to decrease. Flash memory  Capacity: 1 Mbytes (1,024 Kbytes), accessible with one wait state  Durability: Rewritable 100 times Bus specification  Fundamental bus cycle: 12.5 ns (when f(CPUCLK = 80 MHz)  Logical address space : 4 Gbytes linear  Internal bus specification : Internal 32-bit data bus (for CPU <-> internal flash memory and RAM access) (or accessed in 64 bits when accessing the internal flash memory for instructions) : Internal 16-bit data bus (for internal peripheral I/O access)  External area: Maximum 8 Mbytes (during processor mode)  Extended external area: Maximum 8 Mbytes (1 Mbytes + 2 Mbytes × 3 blocks during external extension mode)  External data address: 20-bit address  External data bus: 16-bit data bus  Shortest external bus access: 1 BCLK period during read, 1 BCLK period during write Multijunction timer (MJT) 64-channel multi-functional timer 16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels, 16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels, 16-bit input related up/down timer × 3 channels, and 24-bit output related timer × 24 channels  Flexible timer configuration is possible by interconnecting these timer channels.  Interrupt request: Counter underflow or overflow and rising or falling or both edges or high or low level from the TIN pin (These can be used as external interrupt inputs irrespective of timer operation.)  DMA transfer request: Counter underflow or overflow and rising or falling or both edges or high or low level from the TIN pin (These can be used as external DMA transfer request inputs irrespective of timer operation.) DMAC  Number of channels: 10  Transfers between internal peripheral I/O’s or internal RAM’s or between internal peripheral I/O and internal RAM are supported.  Capable of advanced DMA transfers when used in combination with internal peripheral I/O  Transfer request: Software or internal peripheral I/O (A-D converter, MJT, serial I/O or CAN)  DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a transfer on another channel.)  Interrupt request: DMA transfer counter register underflow

32180 Group User’s Manual (Rev.1.0) Table 1.2.1 Features of the 32180 (2/2) A-D converter (ADC)  16 channels: 10-bit resolution A-D converter × 2 blocks  Conversion modes: Ordinary conversion modes plus comparator mode  Operation modes: Single conversion mode and n-channel scan mode (n = 1–16)  Sample-and-hold function: Sample-and-hold function can be enabled or disabled as necessary.  A-D disconnection detection assist function: Influences of the analog input voltage wrapping around from any preceding channel during scan mode operation are suppressed.  An inflow current bypass circuit is built-in.  Can generate an interrupt or start DMA transfer upon completion of A-D conversion.  Either 8 or 10-bit conversion results can be read out.  Interrupt request: Completion of A-D conversion  DMA transfer request: Completion of A-D conversion Serial I/O (SIO)  6-channel serial I/O  Can be chosen to be clock-synchronized serial I/O or UART.  Data can be transferred at high speed (2 Mbits per second during clock-synchronized mode or 156 Kbits per second during UART mode when f(BCLK) = 20 MHz).  Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed  DMA transfer request: Reception completed or transmit buffer empty CAN  16 message slots × 2 blocks  Compliant with CAN specification 2.0B active.  Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off or single shot  DMA transfer request: Failed to send, transmission completed or reception completed Real-Time Debugger  Internal RAM can be rewritten or monitored independently of the CPU by entering a command (RTD) from the outside.  Comes with exclusive clock-synchronized serial ports.  Interrupt request: RTD interrupt command input Interrupt Controller (ICU) Controls interrupt requests from the internal peripheral I/O.  Supports 8-level interrupt priority including an interrupt disabled state.  External interrupt: 35 sources (SBI# and TIN0–TIN33)  TIN pin input sensing: Rising, falling or both edges or high or low level Wait Controller  Controls wait states for access to the extended external area.  Insertion of 0–7 wait states by setting up in software + wait state extension by entering WAIT# signal PLL  A multiply-by-8 clock generating circuit Clock  Maximum external input clock frequency (XIN) is 10.0 MHz. (Note 1)  CPUCLK: Operating clock for the M32R-FPU core, internal flash memory and internal RAM The maximum CPU clock is 80 MHz (when f(XIN) = 10 MHz).  BCLK: Operating clock for the internal peripheral I/O and external data bus The maximum peripheral clock is 20 MHz (peripheral module access when f(XIN) = 10 MHz).  Clock output (BCLK pin output): A clock with the same frequency as BCLK is output from this pin. JTAG  Boundary scan function VDC  Internal power supply generating circuit: Generates the internal power supply (2.5 V) from an external single power supply (5 or 3.3 V). Ports  Input/output pins: 158 pins  The port input threshold can be set in a program to one of three levels individually for each port group (with or without Schmitt circuit, selectable). Note 1: The maximum external input clock frequency (XIN) for the M32180F8VFP is 8.0 MHz.

32180 Group User’s Manual (Rev.1.0) Figure 1.3.1 Pin Function Diagram M32180F8VFP , M32180F8TFP Port 15 Port 16 Port 13 Port 14 Port 12 Port 4 P45/CS1# XIN XOUT VCNT OSC-VCC OSC-VSS P70/BCLK/WR# RESET# MOD0 MOD1 FP P220/CTX0 P221/CRX0 P224/A11/CS2# P225/A12/CS3# P222/CTX1 P223/CRX1 P226/CS2# P227/CS3# P150/TIN0-P157/TIN7 P160/TO21-P167/TO28 P180/TO29-P187/TO36 P190/TIN26-P196/TIN32 P210/TO37-P217/TO44 P197/TIN33/PWMOFF2 P130/TIN16/PWMOFF0 P131/TIN17/PWMOFF1 P132/TIN18-P137/TIN23 P140/TIN8-P147/TIN15 P124/TCLK0-P127/TCLK3 P93/TO16-P97/TO20 P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1 P103/TO11-P107/TO15 P110/TO0-P117/TO7 AD1IN0-AD1IN15 AD0IN0-AD0IN15 AVCC0, AVCC1 AVSS0, AVSS1 VREF0, VREF1 P61-P63 P65/SCLKI4/SCLKO4 P66/SCLKI5/SCLKO5 P67 SBI# VCCE EXCVCC VSS P44/CS0# P43/RD# P42/BHW#/BHE# P41/BLW#/BLE# P71/WAIT# P72/HREQ# P73/HACK# P20/A23-P27/A30 P30/A15-P37/A22 P46/A13, P47/A14 P00/DB0-P07/DB7 P10/DB8-P17/DB15 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P174/TXD2 P175/RXD2 P172/TIN24, P173/TIN25 P176/TXD3 P177/RXD3 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTMS JTCK JTRST JTDO JTDI VDDE EXCVDD VCC-BUS Bus control Bus control Address bus Address bus Bus control Data bus Serial I/O Serial I/O Serial I/O Serial I/O Serial I/O RTD Port 2 Port 3 Port 21 Port 22 Port 0 Port 1 Port 17 Port 18 Port 19 Port 20 Port 7 Port 8 JTAG Port 11 Port 10 Port 9 Multijunction timer Multijunction timer Multijunction timer Clock Reset Mode CAN CAN A-D converter Interrupt controller Port 6 Notes:  The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low.  : Operates with the VCCE power supply. : Operates with the VCC-BUS power supply. : Operates with the OSC-VCC power supply. VCCE VCCEVCC-BUSVCCE VCC-BUSVCC-BUSVCCE VCC-BUS VCCE VCCE OSC-VCC OSC-VCC

32180 Group User’s Manual (Rev.1.0) Table 1.3.1 Description of Pin Functions (1/5) Type Pin Name Signal Name Input/Output Description EXCVCC Internal power supply– This pin connects an external capacitor. VCC-BUS Bus power supply – Power supply for the bus control pins (5.0 V ± 0.5 V or 3.3 V ± 0.3 V). VDDE RAM power supply – Backup power supply for the internal RAM (5.0 V ± 0.5 V or 3.3 V ± 0.3 V). EXCVDD Internal power – This pin connects an external capacitor for the internal power supply of RAM supply of the internal RAM. VSS Ground – Connect all VSS pins to ground (GND). Clock XIN, Clock input Input These are clock input/output pins. A PLL-based ×8 frequency XOUT Clock output Output multiplier is included, which accepts as input a clock whose frequency is 1/8 of the internal CPU clock frequency. (XIN input is 10 MHz when f(CPUCLK) = 80 MHz.) BCLK System clock Output This pin outputs a clock whose frequency is twice that of the external input clock (XIN). (BCLK output is 20 MHz when f(CPUCLK) = 80 MHz.) Use this clock to synchronize the operation of external devices. OSC-VCC Clock power supply – Power supply for the oscillator circuit. Connect OSC-VCC to the main power supply. OSC-VSS Clock ground – Connect OSC-VSS to ground. VCNT PLL control – Connect a resistor and capacitor for control of the PLL circuit. Reset RESET# Reset Input Reset input pin for the internal circuit. Mode MOD0, Mode Input Set the microcomputer ’s operation mode. MOD1 MOD0 MOD1 Mode 0 0 Single-chip mode 0 1 External extension mode 1 0 Processor mode (Boot mode) (Note 1) 1 1 (Settings inhibited) Flash protect FP Flash protect Input This special pin protects the flash memory against rewrites in hardware. Address bus A11 –A30 Address bus Output Twenty address lines (A11 –A30) are included, allowing four blocks each up to 2 MB memory space to be connected external to the chip. A31 is not output. Note 1: Boot mode requires that the FP pin should be at the high level. For details about boot mode, see Chapter 6, “Internal Memory.”

32180 Group User’s Manual (Rev.1.0) Table 1.3.1 Description of Pin Functions (2/5) Type Pin Name Signal Name Input/Output Description Data bus DB0 –DB15 Data bus Input/output This 16-bit data bus is used to connect external devices. When writing in byte units during a write cycle, the output data at the invalid byte position is undefined. During a read cycle, data on the entire 16-bit bus is always read in. However, only the data at the valid byte position is transferred into the internal circuit. Bus control CS0# –CS3# Chip select Output These are chip select signals for external devices. RD# Read Output This signal is output when reading an external device. WR# Write Output This signal is output when writing to an external device. BHW#/BLW# Byte high/low write Output When writing to an external device, this signal indicates the valid byte position to which data is transferred. BHW# and BLW# correspond to the upper address side (bits 0–7 are valid) and the lower address side (bits 8–15 are valid), respectively. BHE# Byte high enable Output During an external device access, this signal indicates that the high-order data (bits 0–7) is valid. BLE# Byte low enable Output During an external device access, this signal indicates that the low-order data (bits 8–15) is valid. WAIT# Wait Input When accessing an external device, a low-level input on WAIT# pin extends the wait cycle. HREQ# Hold request Input This input is used by an external device to request control of the external bus. A low-level input on HREQ# pin places the CPU in a hold state. HACK# Hold acknowledge Output This signal notifies that the CPU has entered a hold state and relinquished control of the external bus. Multijunction TIN0–TIN33 Timer input Input Input pins for the multijunction timer. timer TO0 –TO44 Timer output Output Output pins for the multijunction timer. TCLK0 Timer clock Input Clock input pins for the multijunction timer. –TCLK3

32180 Group User’s Manual (Rev.1.0) Table 1.3.1 Description of Pin Functions (3/5) Type Pin Name Signal Name Input/Output Description A-D converter AVCC0, Analog power supply– AVCC0 and AVCC1 are the power supply for the A-D0 and AVCC1 the A-D1 converter, respectively. Connect AVCC0 and AVCC1 to the power supply rail. AVSS0, Analog ground – AVSS0 and AVSS1 are the analog ground for the A-D0 and AVSS1 the A-D1 converter, respectively. Connect AVSS0 and AVSS1 to ground. AD0IN0 Analog input Input 16-channel analog input pins for the A-D0 converter, i.e., –AD0IN15 the first block A-D converter. AD1IN0 Analog input Input 16-channel analog input pins for the A-D1 converter, i.e., –AD1IN15 the second block A-D converter. VREF0, Reference voltage Input VREF0 and VREF1 are the reference voltage input pin for VREF1 input the A-D0 and the A-D1 converter, respectively. Interrupt SBI# System break Input This is the system break interrupt (SBI) input pin for the controller interrupt interrupt controller. Serial I/O SCLKI0/ UART transmit/receiveInput/output When channel 0 is in UART mode: SCLKO0 clock output or CSIO This pin outputs a clock derived from BRG output by transmit/receive clock dividing it by 2. input/output When channel 0 is in CSIO mode: This pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected. SCLKI1/ UART transmit/receiveInput/output When channel 1 is in UART mode: SCLKO1 clock output or CSIO This pin outputs a clock derived from BRG output by transmit/receive clock dividing it by 2. input/output When channel 1 is in CSIO mode: This pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected. SCLKI4/ UART transmit/receiveInput/output When channel 4 is in UART mode: SCLKO4 clock output or CSIO This pin outputs a clock derived from BRG output by transmit/receive clock dividing it by 2. input/output When channel 4 is in CSIO mode: This pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected. SCLKI5/ UART transmit/receiveInput/output When channel 5 is in UART mode: SCLKO5 clock output or CSIO This pin outputs a clock derived from BRG output by transmit/receive clock dividing it by 2. input/output When channel 5 is in CSIO mode: This pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected.

32180 Group User’s Manual (Rev.1.0) Table 1.3.1 Description of Pin Functions (4/5) Type Pin Name Signal Name Input/Output Description Serial I/O TXD0 Transmit data Output Transmit data output pin for serial I/O channel 0. RXD0 Received data Input Received data input pin for serial I/O channel 0. TXD1 Transmit data Output Transmit data output pin for serial I/O channel 1. RXD1 Received data Input Received data input pin for serial I/O channel 1. TXD2 Transmit data Output Transmit data output pin for serial I/O channel 2. RXD2 Received data Input Received data input pin for serial I/O channel 2. TXD3 Transmit data Output Transmit data output pin for serial I/O channel 3. RXD3 Received data Input Received data input pin for serial I/O channel 3. TXD4 Transmit data Output Transmit data output pin for serial I/O channel 4. RXD4 Received data Input Received data input pin for serial I/O channel 4. TXD5 Transmit data Output Transmit data output pin for serial I/O channel 5. RXD5 Received data Input Received data input pin for serial I/O channel 5. Real-time RTDTXD RTD transmit data Output Serial data output pin for the real-time debugger. debugger RTDRXD RTD received data Input Serial data input pin for the real-time debugger. (RTD) RTDCLK RTD clock input Input Serial data transmit/receive clock input pin for the real-time debugger. RTDACK RTD acknowledge Output A low-level pulse is output from this pin synchronously with the start clock for the real-time debugger’s serial data output word. The low-level pulse width indicates the type of command/ data received by the real-time debugger. CAN CTX0, CTX1 Transmit data Output This pin outputs data from the CAN module. CRX0, CRX1 Received data Input This pin accepts as input the data for the CAN module. JTAG JTMS Test mode select Input Test mode select input to control the state transition of the test circuit. JTCK Test clock Input Clock input for the debug module and test circuit. JTRST Test reset Input Test reset input to initialize the test circuit asynchronously with device operation. JTDI Test data input Input This pin accepts as input the test instruction code or test data that is serially received. JTDO Test data output Output This pin outputs the test in struction code or test data serially.

32180 Group User’s Manual (Rev.1.0) Table 1.3.1 Description of Pin Functions (5/5) Type Pin Name Signal Name Input/Output Description Input/output P00 –P07 Input/output port 0 Input/output Programmable input/output port. ports P10 –P17 Input/output port 1 (Note 1) P20 –P27 Input/output port 2 P30–P37 Input/output port 3 P41–P47 Input/output port 4 P61–P63 Input/output port 6 P65–P67 P70–P77 Input/output port 7 P82–P87 Input/output port 8 P93–P97 Input/output port 9 P100–P107 Input/output port 10 P110–P117 Input/output port 11 P124–P127 Input/output port 12 P130–P137 Input/output port 13 P140–P147 Input/output port 14 P150–P157 Input/output port 15 P160–P167 Input/output port 16 P172–P177 Input/output port 17 P180–P187 Input/output port 18 P190–P197 Input/output port 19 P200–P203 Input/output port 20 P210–P217 Input/output port 21 P220–P227 Input/output port 22 Note 1: Input/output port 5 is reserved for future use. P221 and P223 are input-only ports.

32180 Group User’s Manual (Rev.1.0) Figure 1.4.1 Pin Assignment Diagram of the 240QFP (Top View) P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 P173/TIN25 P172/TIN24 FP MOD0 MOD1 EXCVDD VSS EXCVCC VDDE VSS VCCE VCC-BUS P17/DB15 P16/DB14 P15/DB13 P14/DB12 P13/DB11 P12/DB10 P11/DB9 P10/DB8 P07/DB7 P06/DB6 P05/DB5 P04/DB4 P03/DB3 P02/DB2 P01/DB1 P00/DB0 VSS P73/HACK# P72/HREQ# P71/WAIT# P70/BCLK/WR# P43/RD# P42/BHW#/BHE# P41/BLW#/BLE# VCC-BUS VSS AD1IN15 AD1IN14 AD1IN13 AD1IN12 AD1IN11 AD1IN10 AD1IN9 AD1IN8 AVSS1 AD1IN7 AD1IN6 AD1IN5 AD1IN4 AD1IN3 AD1IN2 AD1IN1 AD1IN0 VREF1 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P65/SCLKI4/SCLKO4 P66/SCLKI5/SCLKO5 P67 P210/TO37 P211/TO38 P212/TO39 P213/TO40 P214/TO41 P215/TO42 P216/TO43 P217/TO44 P160/TO21 P161/TO22 P162/TO23 P163/TO24 P164/TO25 P165/TO26 P166/TO27 P167/TO28 VSS VCCE VCC-BUS P226/CS2# P227/CS3# P44/CS0# P45/CS1# P224/A11/CS2# P225/A12/CS3# P46/A13 P47/A14 P30/A15 P31/A16 P32/A17 P33/A18 P34/A19 P35/A20 P36/A21 P37/A22 VSS P20/A23 P21/A24 P22/A25 P23/A26 P24/A27 P25/A28 P26/A29 P27/A30 VCC-BUS VSS VCCE P93/TO16 P94/TO17 P95/TO18 P96/TO19 M32180F8VFP M32180F8TFP 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 Package: 240P6Y-A (0.5-mm pitch) AVCC1 VSS VCCE P150/TIN0 P151/TIN1 P152/TIN2 P153/TIN3 P154/TIN4 P155/TIN5 P156/TIN6 P157/TIN7 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 P130/TIN16/PWMOFF0 P131/TIN17/PWMOFF1 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21 P136/TIN22 P137/TIN23 P220/CTX0 P221/CRX0 P222/CTX1 P223/CRX1 VCCE OSC-VSS VCNT OSC-VCC XIN OSC-VSS XOUT RESET# P180/TO29 P181/TO30 P182/TO31 P183/TO32 P184/TO33 P185/TO34 P186/TO35 P187/TO36 P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTDI JTDO JTRST JTCK JTMS P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1 P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15 P97/TO20 P117/TO7 P116/TO6 P115/TO5 P114/TO4 P113/TO3 P112/TO2 P111/TO1 P110/TO0 P147/TIN15 P146/TIN14 P145/TIN13 P144/TIN12 P143/TIN11 P142/TIN10 P141/TIN9 P140/TIN8 P197/TIN33/PWMOFF2 P196/TIN32 P195/TIN31 P194/TIN30 P193/TIN29 P192/TIN28 P191/TIN27 P190/TIN26 P127/TCLK3 P126/TCLK2 P125/TCLK1 P124/TCLK0 EXCVCC VSS VCCE VSS VSS VSS SBI# P63 P62 P61 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AVSS0 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 VREF0 AVCC0 VSS VCCE Note:  The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low.

32180 Group User’s Manual (Rev.1.0) The pins directed for input go to a high-impedance state (Hi-z) when reset. The term “when reset” means that input on RESET# pin is held low (the device remains reset), and that the RESET# pin is released back high (the device comes out of reset). Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (1/6) Note 1: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin. Pin State When Reset Port Other than port Other than port Function Type State during reset State at reset release

1 AVCC1 - AVCC1 - - AVCC1 - - -

2 VSS - VSS - - VSS - - -

3 VCCE - VCCE - - VCCE - - -

4 P150/TIN0 P150 TIN0 - Input/output P150 Input Hi-z Hi-z

5 P151/TIN1 P151 TIN1 - Input/output P151 Input Hi-z Hi-z

6 P152/TIN2 P152 TIN2 - Input/output P152 Input Hi-z Hi-z

7 P153/TIN3 P153 TIN3 - Input/output P153 Input Hi-z Hi-z

8 P154/TIN4 P154 TIN4 - Input/output P154 Input Hi-z Hi-z

9 P155/TIN5 P155 TIN5 - Input/output P155 Input Hi-z Hi-z

10 P156/TIN6 P156 TIN6 - Input/output P156 Input Hi-z Hi-z

11 P157/TIN7 P157 TIN7 - Input/output P157 Input Hi-z Hi-z

12 P200/TXD4 P200 TXD4 - Input/output P200 Input Hi-z Hi-z

13 P201/RXD4 P201 RXD4 - Input/output P201 Input Hi-z Hi-z

14 P202/TXD5 P202 TXD5 - Input/output P202 Input Hi-z Hi-z

15 P203/RXD5 P203 RXD5 - Input/output P203 Input Hi-z Hi-z

16 P130/TIN16/PWMOFF0 P130 TIN16/

PWMOFF0 - Input/output P130 Input Hi-z Hi-z

17 P131/TIN17/PWMOFF1 P131 TIN17/

PWMOFF1 - Input/output P131 Input Hi-z Hi-z

18 P132/TIN18 P132 TIN18 - Input/output P132 Input Hi-z Hi-z

19 P133/TIN19 P133 TIN19 - Input/output P133 Input Hi-z Hi-z

20 P134/TIN20 P134 TIN20 - Input/output P134 Input Hi-z Hi-z

21 P135/TIN21 P135 TIN21 - Input/output P135 Input Hi-z Hi-z

22 P136/TIN22 P136 TIN22 - Input/output P136 Input Hi-z Hi-z

23 P137/TIN23 P137 TIN23 - Input/output P137 Input Hi-z Hi-z

24 P220/CTX0 P220 CTX0 - Input/output P220 Input Hi-z Hi-z

25 P221/CRX0 P221 CRX0 - Input P221 Input Hi-z Hi-z

26 P222/CTX1 P222 CTX1 - Input/output P222 Input Hi-z Hi-z

27 P223/CRX1 P223 CRX1 - Input P223 Input Hi-z Hi-z

28 VCCE - VCCE - - VCCE - - -

29 OSC-VSS - OSC-VSS - - OSC-VSS - - -

30 VCNT - VCNT - - VCNT - - -

31 OSC-VCC - OSC-VCC - - OSC-VCC - - -

32 XIN - XIN - Input XIN Input - -

33 OSC-VSS - OSC-VSS - - OSC-VSS - - -

34 XOUT - XOUT - Output XOUT Output XOUT XOUT

35 RESET# - RESET# - Input RESET# Input Hi-z Hi-z

36 P180/TO29 P180 TO29 - Input/output P180 Input Hi-z Hi-z

37 P181/TO30 P181 TO30 - Input/output P181 Input Hi-z Hi-z

38 P182/TO31 P182 TO31 - Input/output P182 Input Hi-z Hi-z

39 P183/TO32 P183 TO32 - Input/output P183 Input Hi-z Hi-z

40 P184/TO33 P184 TO33 - Input/output P184 Input Hi-z Hi-z

41 P185/TO34 P185 TO34 - Input/output P185 Input Hi-z Hi-z

42 P186/TO35 P186 TO35 - Input/output P186 Input Hi-z Hi-z

43 P187/TO36 P187 TO36 - Input/output P187 Input Hi-z Hi-z

44 P74/RTDTXD P74 RTDTXD - Input/output P74 Input Hi-z Hi-z

45 P75/RTDRXD P75 RTDRXD - Input/output P75 Input Hi-z Hi-z

46 P76/RTDACK P76 RTDACK - Input/output P76 Input Hi-z Hi-z

47 P77/RTDCLK P77 RTDCLK - Input/output P77 Input Hi-z Hi-z

48 JTDI (Note 1) - JTDI - Input JTDI Input Hi-z Hi-z

49 JTDO (Note 1) - JTDO - Output JTDO Output Hi-z Hi-z

50 JTRST (Note 1) - JTRST - Input JTRST Input Hi-z Hi-z

No. Function Symbol Type

32180 Group User’s Manual (Rev.1.0) port Function Type State during reset State at reset release

51 JTCK (Note 1) - JTCK - Input JTCK Input Hi-z Hi-z

52 JTMS (Note 1) - JTMS - Input JTMS Input Hi-z Hi-z

53 P100/TO8 P100 TO8 - Input/output P100 Input Hi-z Hi-z

54 P101/TO9/TXD3 P101 TO9 TXD3 Input/output P101 Input Hi-z Hi-z

55 P102/TO10/CTX1 P102 TO10 CTX1 Input/output P102 Input Hi-z Hi-z

56 P103/TO11 P103 TO11 - Input/output P103 Input Hi-z Hi-z

57 P104/TO12 P104 TO12 - Input/output P104 Input Hi-z Hi-z

58 P105/TO13 P105 TO13 - Input/output P105 Input Hi-z Hi-z

59 P106/TO14 P106 TO14 - Input/output P106 Input Hi-z Hi-z

60 P107/TO15 P107 TO15 - Input/output P107 Input Hi-z Hi-z

61 VCCE - VCCE - - VCCE - - -

62 VSS - VSS - - VSS - - -

63 AVCC0 - AVCC0 - - AVCC0 - - -

64 VREF0 - VREF0 - - VREF0 - - -

65 AD0IN0 - AD0IN0 - Input AD0IN0 Input Hi-z Hi-z

66 AD0IN1 - AD0IN1 - Input AD0IN1 Input Hi-z Hi-z

67 AD0IN2 - AD0IN2 - Input AD0IN2 Input Hi-z Hi-z

68 AD0IN3 - AD0IN3 - Input AD0IN3 Input Hi-z Hi-z

69 AD0IN4 - AD0IN4 - Input AD0IN4 Input Hi-z Hi-z

70 AD0IN5 - AD0IN5 - Input AD0IN5 Input Hi-z Hi-z

71 AD0IN6 - AD0IN6 - Input AD0IN6 Input Hi-z Hi-z

72 AD0IN7 - AD0IN7 - Input AD0IN7 Input Hi-z Hi-z

73 AVSS0 - AVSS0 - - AVSS0 - - -

74 AD0IN8 - AD0IN8 - Input AD0IN8 Input Hi-z Hi-z

75 AD0IN9 - AD0IN9 - Input AD0IN9 Input Hi-z Hi-z

76 AD0IN10 - AD0IN10 - Input AD0IN10 Input Hi-z Hi-z

77 AD0IN11 - AD0IN11 - Input AD0IN11 Input Hi-z Hi-z

78 AD0IN12 - AD0IN12 - Input AD0IN12 Input Hi-z Hi-z

79 AD0IN13 - AD0IN13 - Input AD0IN13 Input Hi-z Hi-z

80 AD0IN14 - AD0IN14 - Input AD0IN14 Input Hi-z Hi-z

81 AD0IN15 - AD0IN15 - Input AD0IN15 Input Hi-z Hi-z

82 P61 P61 - - Input/output P61 Input Hi-z Hi-z

83 P62 P62 - - Input/output P62 Input Hi-z Hi-z

84 P63 P63 - - Input/output P63 Input Hi-z Hi-z

85 SBI# - SBI# - Input SBI# Input Hi-z Hi-z

86 VSS - VSS - - VSS - - -

87 VSS - VSS - - VSS - - -

88 VSS - VSS - - VSS - - -

89 VCCE - VCCE - - VCCE - - -

90 VSS - VSS - - VSS - - -

91 EXCVCC - EXCVCC - - EXCVCC - - -

92 P124/TCLK0 P124 TCLK0 - Input/output P124 Input Hi-z Hi-z

93 P125/TCLK1 P125 TCLK1 - Input/output P125 Input Hi-z Hi-z

94 P126/TCLK2 P126 TCLK2 - Input/output P126 Input Hi-z Hi-z

95 P127/TCLK3 P127 TCLK3 - Input/output P127 Input Hi-z Hi-z

96 P190/TIN26 P190 TIN26 - Input/output P190 Input Hi-z Hi-z

97 P191/TIN27 P191 TIN27 - Input/output P191 Input Hi-z Hi-z

98 P192/TIN28 P192 TIN28 - Input/output P192 Input Hi-z Hi-z

99 P193/TIN29 P193 TIN29 - Input/output P193 Input Hi-z Hi-z

100 P194/TIN30 P194 TIN30 - Input/output P194 Input Hi-z Hi-z

No. Function Symbol Type Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (2/6) Note 1: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin.

32180 Group User’s Manual (Rev.1.0) Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (3/6) Pin State When Reset Port Other than port Other than port Function Type State during reset State at reset release

101 P195/TIN31 P195 TIN31 - Input/output P195 Input Hi-z Hi-z

102 P196/TIN32 P196 TIN32 - Input/output P196 Input Hi-z Hi-z

103 P197/TIN33/PWMOFF2 P197 TIN33/

PWMOFF2 - Input/output P197 Input Hi-z Hi-z

104 P140/TIN8 P140 TIN8 - Input/output P140 Input Hi-z Hi-z

105 P141/TIN9 P141 TIN9 - Input/output P141 Input Hi-z Hi-z

106 P142/TIN10 P142 TIN10 - Input/output P142 Input Hi-z Hi-z

107 P143/TIN11 P143 TIN11 - Input/output P143 Input Hi-z Hi-z

108 P144/TIN12 P144 TIN12 - Input/output P144 Input Hi-z Hi-z

109 P145/TIN13 P145 TIN13 - Input/output P145 Input Hi-z Hi-z

110 P146/TIN14 P146 TIN14 - Input/output P146 Input Hi-z Hi-z

111 P147/TIN15 P147 TIN15 - Input/output P147 Input Hi-z Hi-z

112 P110/TO0 P110 TO0 - Input/output P110 Input Hi-z Hi-z

113 P111/TO1 P111 TO1 - Input/output P111 Input Hi-z Hi-z

114 P112/TO2 P112 TO2 - Input/output P112 Input Hi-z Hi-z

115 P113/TO3 P113 TO3 - Input/output P113 Input Hi-z Hi-z

116 P114/TO4 P114 TO4 - Input/output P114 Input Hi-z Hi-z

117 P115/TO5 P115 TO5 - Input/output P115 Input Hi-z Hi-z

118 P116/TO6 P116 TO6 - Input/output P116 Input Hi-z Hi-z

119 P117/TO7 P117 TO7 - Input/output P117 Input Hi-z Hi-z

120 P97/TO20 P97 TO20 - Input/output P97 Input Hi-z Hi-z

121 P96/TO19 P96 TO19 - Input/output P96 Input Hi-z Hi-z

122 P95/TO18 P95 TO18 - Input/output P95 Input Hi-z Hi-z

123 P94/TO17 P94 TO17 - Input/output P94 Input Hi-z Hi-z

124 P93/TO16 P93 TO16 - Input/output P93 Input Hi-z Hi-z

125 VCCE - VCCE - - VCCE - - -

126 VSS - VSS - - VSS - - -

127 VCC-BUS - VCC-BUS - - VCC-BUS - - -

external extension modes P27 Input Hi-z Hi-z During processor mode A30 Output Hi-z Undefined During single-chip and external extension modes P26 Input Hi-z Hi-z During processor mode A29 Output Hi-z Undefined During single-chip and external extension modes P25 Input Hi-z Hi-z During processor mode A28 Output Hi-z Undefined During single-chip and external extension modes P24 Input Hi-z Hi-z During processor mode A27 Output Hi-z Undefined During single-chip and external extension modes P23 Input Hi-z Hi-z During processor mode A26 Output Hi-z Undefined During single-chip and external extension modes P22 Input Hi-z Hi-z During processor mode A25 Output Hi-z Undefined During single-chip and external extension modes P21 Input Hi-z Hi-z During processor mode A24 Output Hi-z Undefined During single-chip and external extension modes P20 Input Hi-z Hi-z During processor mode A23 Output Hi-z Undefined

136 VSS - VSS - - VSS - - -

external extension modes P37 Input Hi-z Hi-z During processor mode A22 Output Hi-z Undefined During single-chip and external extension modes P36 Input Hi-z Hi-z During processor mode A21 Output Hi-z Undefined During single-chip and external extension modes P35 Input Hi-z Hi-z During processor mode A20 Output Hi-z Undefined 130 Input/output 138 - Input/output P24

133 P22/A25 P22

No. P27/A30 P26/A29 Input/output - Input/output A28 - Input/output

131 P24/A27

132 P23/A26 P23 A26

134 P21/A24 P21 A24

• Input/output - Input/output - Input/output A25 - Input/output

135 P20/A23

137 P37/A22 P37 A22

• Input/output139 P35/A20 P35 A20 P36/A21 P36 A21

32180 Group User’s Manual (Rev.1.0) Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (4/6) Pin State When Reset Port Other than port Other than port Function Type State during reset State at reset release During single-chip and external extension modes P34 Input Hi-z Hi-z During processor mode A19 Output Hi-z Undefined During single-chip and external extension modes P33 Input Hi-z Hi-z During processor mode A18 Output Hi-z Undefined During single-chip and external extension modes P32 Input Hi-z Hi-z During processor mode A17 Output Hi-z Undefined During single-chip and external extension modes P31 Input Hi-z Hi-z During processor mode A16 Output Hi-z Undefined During single-chip and external extension modes P30 Input Hi-z Hi-z During processor mode A15 Output Hi-z Undefined During single-chip and external extension modes P47 Input Hi-z Hi-z During processor mode A14 Output Hi-z Undefined During single-chip and external extension modes P46 Input Hi-z Hi-z During processor mode A13 Output Hi-z Undefined During single-chip and external extension modes P225 Input Hi-z Hi-z During processor mode A12 Output Hi-z Undefined During single-chip and external extension modes P224 Input Hi-z Hi-z During processor mode A11 Output Hi-z Undefined During single-chip and external extension modes P45 Input Hi-z Hi-z During processor mode CS1# Output Hi-z High level During single-chip and external extension modes P44 Input Hi-z Hi-z During processor mode CS0# Output Hi-z High level During single-chip and external extension modes P227 Input Hi-z Hi-z During processor mode CS3# Output Hi-z High level During single-chip and external extension modes P226 Input Hi-z Hi-z During processor mode CS2# Output Hi-z High level

153 VCC-BUS VCC-BUS - VCC-BUS - - -

154 VCCE - VCCE - - VCCE - - -

155 VSS - VSS - - VSS - - -

156 P167/TO28 P167 TO28 - Input/output P167 Input Hi-z Hi-z

157 P166/TO27 P166 TO27 - Input/output P166 Input Hi-z Hi-z

158 P165/TO26 P165 TO26 - Input/output P165 Input Hi-z Hi-z

159 P164/TO25 P164 TO25 - Input/output P164 Input Hi-z Hi-z

160 P163/TO24 P163 TO24 - Input/output P163 Input Hi-z Hi-z

161 P162/TO23 P162 TO23 - Input/output P162 Input Hi-z Hi-z

162 P161/TO22 P161 TO22 - Input/output P161 Input Hi-z Hi-z

163 P160/TO21 P160 TO21 - Input/output P160 Input Hi-z Hi-z

164 P217/TO44 P217 TO44 - Input/output P217 Input Hi-z Hi-z

165 P216/TO43 P216 TO43 - Input/output P216 Input Hi-z Hi-z

166 P215/TO42 P215 TO42 - Input/output P215 Input Hi-z Hi-z

167 P214/TO41 P214 TO41 - Input/output P214 Input Hi-z Hi-z

168 P213/TO40 P213 TO40 - Input/output P213 Input Hi-z Hi-z

169 P212/TO39 P212 TO39 - Input/output P212 Input Hi-z Hi-z

170 P211/TO38 P211 TO38 - Input/output P211 Input Hi-z Hi-z

171 P210/TO37 P210 TO37 - Input/output P210 Input Hi-z Hi-z

172 P67 P67 - - Input/output P67 Input Hi-z Hi-z

173 P66/SCLKI5/SCLKO5 P66 SCLKI5 SCLKO5 Input/output P66 Input Hi-z Hi-z

174 P65/SCLKI4/SCLKO4 P65 SCLKI4 SCLKO4 Input/output P65 Input Hi-z Hi-z

175 P87/SCLKI1/SCLKO1 P87 SCLKI1 SCLKO1 Input/output P87 Input Hi-z Hi-z

No. Function -CS1# P224 A11 CS2# 146 Input/output

150 P44/CS0# P44 CS0# - Input/output

149 P45/CS1# P45

• Input/output P225 A12 CS3# Input/output P46/A13 P46 A13 - Input/output

144 P30/A15

145 P47/A14 P47 A14

• Input/output - Input/output Input/output

143 P31/A16 P31 A16

142 P32/A17 P32 A17

• Input/output Input/output

141 P33/A18 P33 A18

140 P34/A19 P34 A19

P225/A12/CS3#147

148 P224/A11/CS2#

P227/CS3# P226/CS2# P227 P226 Input/output Input/output CS3# CS2# -

32180 Group User’s Manual (Rev.1.0) Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (5/6) Pin State When Reset Port Other than port Other than port Function Type State during reset State at reset release

176 P86/RXD1 P86 RXD1 - Input/output P86 Input Hi-z Hi-z

177 P85/TXD1 P85 TXD1 - Input/output P85 Input Hi-z Hi-z

178 P84/SCLKI0/SCLKO0 P84 SCLKI0 SCLKO0 Input/output P84 Input Hi-z Hi-z

179 P83/RXD0 P83 RXD0 - Input/output P83 Input Hi-z Hi-z

180 P82/TXD0 P82 TXD0 - Input/output P82 Input Hi-z Hi-z

181 P174/TXD2 P174 TXD2 - Input/output P174 Input Hi-z Hi-z

182 P175/RXD2 P175 RXD2 - Input/output P175 Input Hi-z Hi-z

183 P176/TXD3 P176 TXD3 - Input/output P176 Input Hi-z Hi-z

184 P177/RXD3 P177 RXD3 - Input/output P177 Input Hi-z Hi-z

185 P173/TIN25 P173 TIN25 - Input/output P173 Input Hi-z Hi-z

186 P172/TIN24 P172 TIN24 - Input/output P172 Input Hi-z Hi-z

187 FP - FP - Input FP Input Hi-z Hi-z

188 MOD0 - MOD0 - Input MOD0 Input Hi-z Hi-z

189 MOD1 - MOD1 - Input MOD1 Input Hi-z Hi-z

190 EXCVDD - EXCVDD - - EXCVDD - - -

191 VSS - VSS - - VSS - - -

192 EXCVCC - EXCVCC - - EXCVCC - - -

193 VDDE - VDDE - - VDDE - - -

194 VSS - VSS - - VSS - - -

195 VCCE - VCCE - - VCCE - - -

196 VCC-BUS - VCC-BUS - - VCC-BUS - - -

external extension modes P17 Input Hi-z Hi-z During processor mode DB15 Input/output Hi-z Hi-z During single-chip and external extension modes P16 Input Hi-z Hi-z During processor mode DB14 Input/output Hi-z Hi-z During single-chip and external extension modes P15 Input Hi-z Hi-z During processor mode DB13 Input/output Hi-z Hi-z During single-chip and external extension modes P14 Input Hi-z Hi-z During processor mode DB12 Input/output Hi-z Hi-z During single-chip and external extension modes P13 Input Hi-z Hi-z During processor mode DB11 Input/output Hi-z Hi-z During single-chip and external extension modes P12 Input Hi-z Hi-z During processor mode DB10 Input/output Hi-z Hi-z During single-chip and external extension modes P11 Input Hi-z Hi-z During processor mode DB9 Input/output Hi-z Hi-z During single-chip and external extension modes P10 Input Hi-z Hi-z During processor mode DB8 Input/output Hi-z Hi-z During single-chip and external extension modes P07 Input Hi-z Hi-z During processor mode DB7 Input/output Hi-z Hi-z During single-chip and external extension modes P06 Input Hi-z Hi-z During processor mode DB6 Input/output Hi-z Hi-z During single-chip and external extension modes P05 Input Hi-z Hi-z During processor mode DB5 Input/output Hi-z Hi-z During single-chip and external extension modes P04 Input Hi-z Hi-z During processor mode DB4 Input/output Hi-z Hi-z During single-chip and external extension modes P03 Input Hi-z Hi-z During processor mode DB3 Input/output Hi-z Hi-z During single-chip and external extension modes P02 Input Hi-z Hi-z During processor mode DB2 Input/output Hi-z Hi-z Input/output - Input/output - Input/output Symbol Type Condition

197 P17/DB15 P17 DB15

No. Function

198 P16/DB14 P16 DB14

• Input/output

199 P15/DB13

200 P14/DB12 P14 DB12

201 P13/DB11 P13 DB11

• Input/output

202 P12/DB10 P12 DB10

• Input/output - Input/output - Input/output

203 P11/DB9

204 P10/DB8 P10 DB8

205 P07/DB7 P07 DB7

206 P06/DB6 P06 DB6

• Input/output - Input/output - Input/output P05 DB5 - Input/outputP04 DB4 - Input/output

209 P03/DB3

210 P02/DB2 P02 DB2

207 P05/DB5

208 P04/DB4

32180 Group User’s Manual (Rev.1.0) Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (6/6) Pin State When Reset Port Other than port Other than port Function Type State during reset State after reset During single-chip and external extension modes P01 Input Hi-z Hi-z During processor mode DB1 Input/output Hi-z Hi-z During single-chip and external extension modes P00 Input Hi-z Hi-z During processor mode DB0 Input/output Hi-z Hi-z

213 VSS - VSS - - VSS - - -

214 P73/HACK# P73 HACK# - Input/output P73 Input Hi-z Hi-z

215 P72/HREQ# P72 HREQ# - Input/output P72 Input Hi-z Hi-z

216 P71/WAIT# P71 WAIT# - Input/output P71 Input Hi-z Hi-z

217 P70/BCLK/WR# P70 BCLK WR# Input/output P70 Input Hi-z Hi-z

During single-chip mode P43 Input Hi-z Hi-z During external extension and processor modes RD# Output Hi-z High level During single-chip mode P42 Input Hi-z Hi-z During external extension and processor modes BHW#/BHE# Output Hi-z High level During single-chip mode P41 Input Hi-z Hi-z During external extension and processor modes BLW#/BLE# Output Hi-z High level

221 VCC-BUS - VCC-BUS - - VCC-BUS - - -

223 AD1IN15 - AD1IN15 - Input AD1IN15 Input Hi-z Hi-z

224 AD1IN14 - AD1IN14 - Input AD1IN14 Input Hi-z Hi-z

225 AD1IN13 - AD1IN13 - Input AD1IN13 Input Hi-z Hi-z

226 AD1IN12 - AD1IN12 - Input AD1IN12 Input Hi-z Hi-z

227 AD1IN11 - AD1IN11 - Input AD1IN11 Input Hi-z Hi-z

228 AD1IN10 - AD1IN10 - Input AD1IN10 Input Hi-z Hi-z

229 AD1IN9 - AD1IN9 - Input AD1IN9 Input Hi-z Hi-z

230 AD1IN8 - AD1IN8 - Input AD1IN8 Input Hi-z Hi-z

231 AVSS1 - AVSS1 - - AVSS1 - - -

232 AD1IN7 - AD1IN7 - Input AD1IN7 Input Hi-z Hi-z

233 AD1IN6 - AD1IN6 - Input AD1IN6 Input Hi-z Hi-z

234 AD1IN5 - AD1IN5 - Input AD1IN5 Input Hi-z Hi-z

235 AD1IN4 - AD1IN4 - Input AD1IN4 Input Hi-z Hi-z

236 AD1IN3 - AD1IN3 - Input AD1IN3 Input Hi-z Hi-z

237 AD1IN2 - AD1IN2 - Input AD1IN2 Input Hi-z Hi-z

238 AD1IN1 - AD1IN1 - Input AD1IN1 Input Hi-z Hi-z

239 AD1IN0 - AD1IN0 - Input AD1IN0 Input Hi-z Hi-z

240 VREF1 - VREF1 - - VREF1 - - -

218 P43/RD# P43 RD#

212 P00/DB0 P00 DB0

211 P01/DB1

No. Function Condition - Input/output BLE# Input/output - Input/output BHE# Input/output219 P42/BHW#/BHE#

220 P41/BLW#/BLE# P41 BLW#

P42 BHW#

2.1 CPU Registers

2.2 General-purpose Registers

2.3 Control Registers

2.4 Accumulator

2.5 Program Counter

2.6 Data Formats

2.7 Supplementary Explanation for BSET, BCLR,

LOCK and UNLOCK Instruction Execution

2.8 Precautions on CPU

2-2 32180 Group User’s Manual (Rev.1.0) CPU There are 6 control registers which are the Processor Status Word Register (PSW), the Condition Bit Register (CBR), the Interrupt Stack Pointer (SPI), the User Stack Pointer (SPU), the Backup PC (BPC) and the Floating- point Status Register (FPSR). The dedicated MVTC and MVFC instructions are used for writing and reading these control registers. In addition, the SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instruction. Figure 2.3.1 Control Registers The M32R-FPU has 16 general-purpose registers, 6 control registers, an accumulator and a program counter. The accumulator is of 56-bit configuration, and all other registers are of 32-bit configuration. The 16 general-purpose registers (R0–R15) are of 32-bit width and are used to retain data and base address, as well as for integer calculations, floating-point operations, etc. R14 is used as the link register and R15 as the stack pointer. The link register is used to store the return address when executing a subroutine call instruction. The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) are alternately represented by R15 depending on the value of the Stack Mode (SM) bit in the Processor Status Word Register (PSW). After reset, the value of the general-purpose registers is undefined. Figure 2.2.1 General-purpose Registers b0b0 b31 R10 R11 R12 R13 R14 (Link register) R15 (Stack pointer) (Note 1) Note 1: The stack pointer functions as either the SPI or the SPU depending on the value of the SM bit in the PSW. b31 Backup PC BPCCR6 b31 PSW CBR SPI SPU CR0 CR1 CR2 CR3 Processor Status Word Register Condition Bit Register Interrupt Stack Pointer User Stack Pointer CRn Notes:  CRn (n = 0-3, 6 and 7) denotes the control register number.  The dedicated MVTC and MVFC instructions are used for writing and reading these control registers.  The SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instructions. Floating-point Status RegisterFPSRCR7

2-3 32180 Group User’s Manual (Rev.1.0) CPU

2.3.1 Processor Status Word Register: PSW (CR0)

7654321 8 9 10 11 12 13 14 b15b0 ?? 00000?00000000 BC SM IE C 23 24 25 26 27 28 29 30 b3117 18 19 20 21 22b16 BIEBSM BPSW field 0 0 PSW field <After reset: B’0000 0000 0000 0000 ??00 000? 0000 0000> b Bit Name Function R W 0–15 No function assigned. Fix to "0". 00

16 BSM Saves value of SM bit when EIT occurs R W

17 BIE Saves value of IE bit when EIT occurs R W

18–22 No function assigned. Fix to "0". 00

23 BC Saves value of C bit when EIT occurs R W

24 SM 0: Uses R15 as the interrupt stack pointer R W

Stack Mode Bit 1: Uses R15 as the user stack pointer

25 IE 0: Does not accept interrupt R W

Interrupt Enable Bit 1: Accepts interrupt 26–30 No function assigned. Fix to "0". 00

31 C Indicates carry, borrow or overflow resulting R W

Condition Bit from operations (instruction dependent) The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs. The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and the Condition (C) bit. The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt Enable (BIE) bit and the Backup Condition (BC) bit. After reset, BSM, BIE and BC are undefined. All other bits are "0".

2-4 32180 Group User’s Manual (Rev.1.0) CPU

2.3.2 Condition Bit Register: CBR (CR1)

The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value written to the PSW register’s C bit is reflected in this register. The register can only be read. (Writing to the register with the MVTC instruction is ignored.) After reset, the value of CBR is H’0000 0000. b0 b31

0000000000000000000000000000000 CCBR

2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3)

The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) retain the address of the current stack pointer. These registers can be accessed as the general-purpose register R15. R15 switches between repre- senting the SPI and SPU depending on the value of the Stack Mode (SM) bit in the PSW. After reset, the values of the SPI and SPU are undefined. b0 b31 SPI SPI b0 b31 SPU SPU

2.3.4 Backup PC: BPC (CR6)

The Backup PC (BPC) is used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31 is fixed to "0". When an EIT occurs, the register sets either the PC value when the EIT occurred or the PC value for the next instruction depending on the type of EIT. The BPC value is loaded to the PC when the RTE instruction is executed. However, the values of the lower 2 bits of the PC are always "00" when returned. (PC always returns to the word-aligned address.) After reset, the value of the BPC is undefined. b0 b31 0BPCBPC

2-5 32180 Group User’s Manual (Rev.1.0) CPU

2.3.5 Floating-point Status Register: FPSR (CR7)

2 3 4 5 6 7 8 9 10 11 12 13 14 b151b0 00 00000100000000 EV DN CE CX CU CZ CO CV RM 18 19 20 21 22 23 24 25 26 27 28 29 30 b3117b16 EUEX FS FX FU FZ FO FV EZ EO <After reset: H’0000 0100> b Bit Name Function R W 0 FS Reflects the logical sum of FU, FZ, FO and FV. R – Floating-point Exception Summary Bit

1 FX Set to "1" when an inexact exception occurs (if EIT processing is R W

Inexact Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software.

2 FU Set to "1" when an underflow exception occurs (if EIT processing is R W

Underflow Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software.

3 FZ Set to "1" when a zero divide exception occurs (if EIT processing is R W

Zero Divide Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software.

4 FO Set to "1" when an overflow exception occurs (if EIT processing is R W

Overflow Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software.

5 FV Set to "1" when an invalid operation exception occurs (if EIT processing R W

Invalid Operation Exception Flag is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. 6–16 No function assigned. Fix to "0". 00 17 EX 0: Mask EIT processing to be executed when an inexact exception occurs. R W Inexact Exception Enable Bit 1: Execute EIT processing when an inexact exception occurs.

18 EU 0: Mask EIT processing to be executed when an underflow exception R W

Underflow Exception Enable Bit occurs. 1: Execute EIT processing when an underflow exception occurs.

19 EZ 0: Mask EIT processing to be executed when a zero divide exception R W

Zero Divide Exception Enable Bit occurs. 1: Execute EIT processing when a zero divide exception occurs.

20 EO 0: Mask EIT processing to be executed when an overflow exception R W

Overflow Exception Enable Bit occurs. 1: Execute EIT processing when an overflow exception occurs.

21 EV 0: Mask EIT processing to be executed when an invalid operation R W

Invalid Operation Exception Enable Bit exception occurs. 1: Execute EIT processing when an invalid operation exception occurs. 22 No function assigned. Fix to "0". 00 23 DN 0: Handle the denormalized number as a denormalized number. R W Denormalized Number Zero Flush Bit 1: Handle the denormalized number as zero. (Note 2) 24 CE 0: No unimplemented operation exception occurred. R (Note 3) Unimplemented Operation 1: An unimplemented operation exception occurred. When the bit is Exception Cause Bit set to "1", the execution of an FPU operation instruction will clear it to "0". 25 CX 0: No inexact exception occurred. R (Note 3) Inexact Exception Cause Bit 1: An inexact exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0".

2-6 32180 Group User’s Manual (Rev.1.0) CPU

26 CU 0: No underflow exception occurred R (Note 3)

Underflow Exception Cause Bit 1: An underflow exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 27 CZ 0: No zero divide exception occurred. R (Note 3) Zero Divide Exception Cause Bit 1: A zero divide exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 28 CO 0: No overflow exception occurred. R (Note 3) Overflow Exception Cause Bit 1: An overflow exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 29 CV 0: No invalid operation exception occurred. R (Note 3) Invalid Operation Exception Cause Bit 1: An invalid operation exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 30, 31 RM 00: Round to nearest R W Rounding Mode Selection Bit 01: Round toward Zero 10: Round toward + Infinity 11: Round toward – Infinity Note 1: The phrase “If EIT processing unexecuted” means whenever one of the exceptions occurs, enable bits 17 to 21 are set to "0" which masks the EIT processing so that it cannot be executed. If two exceptions occur at the same time and their corresponding exception enable bits are set differently (one enabled, and the other masked), EIT processing is executed. In this case, these two flags do not change state regardless of the enable bits settings. Note 2: If a denormalized number is given to the operand when DN = "0", an unimplemented exception occurs. Note 3: This bit is cleared by writing "0". Writing "1" has no effect (the bit retains the value it had before the write).

2-7 32180 Group User’s Manual (Rev.1.0) CPU The Accumulator (ACC) is a 56-bit register used for DSP function instructions. The accumulator is handled as a 64-bit register when accessed for read or write. When reading data from the accumulator, the value of bit 8 is sign-extended. When writing data to the accumulator, bits 0 to 7 are ignored. The accumulator is also used for the multiply instruction “MUL, ” in which case the accumulator value is destroyed by instruction execution. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the high-order 32 bits (bits 0–31) and the low-order 32 bits (bits 32–63), respectively. Use the MVFACHI, MVFACLO and MVFACMI instructions for reading data from the accumulator. The MVFACHI, MVFACLO and MVFACMI instructions read data from the high-order 32 bits (bits 0–31), the low-order 32 bits (bits 32–63) and the middle 32 bits (bits 16–47), respectively. After reset, the value of accumulator is undefined. 15b0 16 7 8 31 32 47 48 b63 ACC (Note 1) Read range of MVFACMI instruction Write and read ranges of MVTACLO and MVFACLO instructions Write and read ranges of MVTACHI and MVFACHI instructions Note 1: When read, bits 0 to 7 always show the sign-extended value of the value of bit 8. Writing to this bit field is ignored. The Program Counter (PC) is a 32-bit counter that retains the address of the instruction being executed. Since the M32R FPU instruction starts with even-numbered addresses, the LSB (bit 31) is always "0". After reset, the value of PC is H’0000 0000. b0 b31 0PCPC

2-8 32180 Group User’s Manual (Rev.1.0) CPU

2.6.1 Data Types

The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16 and 32-bit integers and single-precision floating-point numbers. The signed integers are represented by 2’s complements. Figure 2.6.1 Data Types Signed byte (8-bit) integer Unsigned byte (8-bit) integer Signed halfword (16-bit) integer Unsigned halfword (16-bit) integer Signed word (32-bit) integer Unsigned word (32-bit) integer Single-precision floating-point number b15 b15 b31 b31 S S S b0 b1 b8 b9 b31 SE F S: Sign bit; E: Exponent field; F: Fraction field

2-9 32180 Group User’s Manual (Rev.1.0) CPU

2.6.2 Data Formats

(1) Data formats in registers The data sizes in the M32R-FPU registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) to a word (32-bit) quantity before being loaded in the register. When storing data from a register into a memory, the 32-bit data, the 16-bit data on the LSB side and the 8- bit data on the LSB side of the register are stored into memory by the ST, STH and STB instructions, respectively. Figure 2.6.2 Data Formats in Registers Rn b0 b31 <Load> Byte Rn b0 b31 Halfword Rn b0 b31 Word Sign-extended (LDB instruction) or zero-extended (LDUB instruction) From memory (LDB, LDUB instructions) <Store> Rn b0 b31 Byte Rn b0 b31 Halfword Rn b0 b31 Word To memory (STB instruction) To memory (STH instruction) To memory (ST instruction) From memory (LDH, LDUH instructions) From memory (LD instruction) Sign-extended (LDH instruction) or zero-extended (LDUH instruction)

2-10 32180 Group User’s Manual (Rev.1.0) CPU (H'01) Byte endian (H'01234567) Big endian Little endian Note:  Even when bits are arranged in big endian, H'01 is not B'10000000. HH HL LH LL H'01 H'23 H'45 H'67 LL LH HL HH H'67 H'45 H'23 H'01 B'0000001 b0 b7 B'0000001 b7 b0 Figure 2.6.4 General Endian System (2) Data formats in memory The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). Although byte data can be located at any address, halfword and word data must be located at the addresses aligned with a halfword boundary (least significant address bit = "0") or a word boundary (two low-order address bits = "00"), respectively. If an attempt is made to access memory data that overlaps the halfword or word bound- ary, an address exception occurs. Figure 2.6.3 Data Formats in Memory (3) Endian The diagrams below show a general endian system and the endian adopted for the M32R family of Mitsubishi microcomputers. Address Byte Halfword Word +0 address +1 address +2 address +3 address b0 b31 Byte Byte Byte Byte Halfword Halfword Word 7 8 15 16 23 24 b0 15 b0 b31 b31

2-11 32180 Group User’s Manual (Rev.1.0) CPU  Constant transfer LD24 Rdest, #imm24 LDI Rdest, #imm16 LDI Rdest, #imm8 SETH Rdest, #imm16 b23b0 Rdest imm24 b31b0 LD24 Rdest, #imm24 b15b0 Rdest imm16 b31b0 SETH Rdest, #imm16 00 00  Register to register transfer MV Rdest, Rsrc  Control register transfer MVFC Rdest, CRsrc MVTC Rsrc, CRdest Rsrc b31b0 Rdest b31b0 Rsrc b31b0 CRdest b31b0 MVTC Rsrc, CRdest MV Rdest, Rsrc Note:  The condition bit C changes state when data is written to CR0 (PSW) using the MVTC instruction. Figure 2.6.6 Transfer Instructions Little/little LL LH HL HH Big/big HH HL LH LL Little/big HH HL LH LL Endian (bit/byte) Data arrangement Mitsubishi microcomputer family name 7700 and M16C families M32R family 31–247–02 3 –1615–80 –72 4 –318–15 16 –23Bit number Example: 0x01234567 .byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67 Note:  The M32R family uses the big endian for both bits and bytes. 7–031–24 15 –823–16 Figure 2.6.5 Endian Adopted for the M32R Family (4) Transfer instructions

2-12 32180 Group User’s Manual (Rev.1.0) CPU (5) Transfer from memory (signed) to registers  Signed 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc  Signed 16 bits LD24 Rsrc, #label LDH Rdest, @Rsrc  Signed 8 bits LD24 Rsrc, #label LDB Rdest, @Rsrc label Rdest b31b0+0 +1 +2 +3 Rdestlabel 00 00 FF FF Determined by MSB b31b0 +0 +1 +2 +3 Rdestlabel 00 00 00 FF FF FF b31b0 +0 +1 +2 +3 Determined by MSB Memory Register 0: Positive number 1: Negative number 0: Positive number 1: Negative number  Unsigned 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc  Unsigned 16 bits LD24 Rsrc, #label LDUB Rdest, @Rsrc  Unsigned 8 bits LD24 Rsrc, #label LDUH Rdest, @Rsrc Rdest 00 00 b31b0 label +0 +1 +2 +3 label +0 +1 +2 +3 Rdest b31b0 label +0 +1 +2 +3 Rdest 00 00 00 b31b0 Memory Register Figure 2.6.7 Transfer from Memory (Signed) to Registers (6) Transfer from memory (unsigned) to registers Figure 2.6.8 Transfer from Memory (Unsigned) to Registers

2-13 32180 Group User’s Manual (Rev.1.0) CPU (7) Notes on data transfer When transferring data, be aware that data arrangements in registers and memory are different.  Word data (32 bits) +0 +1 +2 +3 b0 b31 HH HL LH LL b0 b31 HH HL LH LL  Halfword data (16 bits) +0 +1 +2 +3 b0 b31 H L b0 b15 H L  Byte data (8 bits) +0 +1 +2 +3 b0 b31 b0 b7 (R0–R15) (R0–R15) (R0–R15) +0 +1 +2 +3 b0 b31 b8 b15 (R0–R15) +0 +1 +2 +3 b0 b31 b16 b23 (R0–R15) +0 +1 +2 +3 b0 b31 b24 b31 (R0–R15) +0 +1 +2 +3 b0 b31 H L b16 b31 H L (R0–R15) Data in registers Data in memory Figure 2.6.9 Difference in Data Arrangements

2-14 32180 Group User’s Manual (Rev.1.0) CPU

2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK

The LOCK bit is set when executing the BSET or BCLR instruction, and is cleared when the BSET or BCLR instruction finishes. The LOCK instruction sets the LOCK bit, as well as performs an ordinary load operation. The UNLOCK instruction is used to clear the LOCK bit. The LOCK bit is located inside the CPU, and cannot directly be accessed for read or write by users. This bit controls granting of bus control requested by devices other than the CPU.  When LOCK bit = "0" Control of the bus requested by devices other than the CPU is granted  When LOCK bit = "1" Control of the bus requested by devices other than the CPU is denied In the 32180 group, control of the bus may be requested by devices other than the CPU in the following two cases:  When DMA transfer is requested by the internal DMAC  When HREQ# input is pulled low to request that the CPU be placed in a hold state

• Usage Notes for 0 Division Instruction Problem and Conditions Inaccurate calculations for the instructions listed in (2) will result from execution of the 0 division instruction under the conditions described in (1). (1) If 0 division calculation is executed when the divisor = 0 for instructions DIV, DIVU, REM and REMU, (2) the result will be inaccurate calculations for any of the following instructions that are executed immedi- ately after 0 division: ADDV, ADDX, ADD, ADDI, ADDV3, ADD3, CMP, CMPU, CMPI, CMPUI, SUBV, SUBX, SUB, DIV, DIVU, REM, REMU. Countermeasure Assuming that the 0 division occurrence itself is not expected by the system and therefore is the cause of miscalculations, before executing division or remainder instructions, do a 0 check on the divisor to make sure 0 division does not occur.

2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution

3.1 Outline of the Address Space

3.2 Operation Modes

3.3 Internal ROM and Extended External Areas

3.4 Internal RAM and SFR Areas

3.5 EIT Vector Entry

3.6 ICU Vector Table

3.7 Notes on Address Space

32180 Group User’s Manual (Rev.1.0) The logical addresses of the M32R are always handled in 32 bits, providing a linear address space of up to 4 Gbytes. The address space of the M32R/ECU consists of the following: (1) User space  Internal ROM area  Extended external area  Internal RAM area  SFR (Special Function Register) area (2) System space (not open to the user) (1) User space The 2 Gbytes from the address H’0000 0000 to the address H’7FFF FFFF comprise the user space. Located in this space are the internal ROM area, an extended external area, the internal RAM area and the SFR (Special Function Register) area (in which a set of internal peripheral I/O registers exist). Of these, the internal ROM and extended external areas are located differently depending on mode settings as will be described later. (2) System space The 2 Gbytes from the address H’8000 0000 to the address H’FFFF FFFF comprise the system space. This space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and cannot be used by the user.

32180 Group User’s Manual (Rev.1.0) Logical address H'0000 0000 H'7FFF FFFF H'8000 0000

2 Gbytes

H'FFFF FFFF User space System space

16 Mbytes

1 Mbytes

(Note 1) C S0 area CS1 area CS2 area CS3 area SFR area

16 Kbytes

48 Kbytes

64 Kbytes

H'0000 0000 H'000F FFFF H'0010 0000 H'001F FFFF H'0020 0000 H'003F FFFF H'0040 0000 H'005F FFFF H'0060 0000 H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 H'0080 FFFF H'0081 0000 H'0081 FFFF H'0082 0000 Ghost area in 128-Kbyte units H'00FF FFFF Note 1: This area is located differently depending on how chip mode is set. Figure 3.1.1 Address Space

32180 Group User’s Manual (Rev.1.0) The microcomputer is placed in one of the following modes depending on how CPU operation mode is set by MOD0 and MOD1 pins. The operation mode used for rewriting the internal flash memory is described separately in Section 6.5, “Programming the Internal Flash Memory.” Table 3.2.1 Operation Mode Settings MOD0 MOD1 Operation mode (Note 2) VSS VSS Single-chip mode VSS VCCE External extension mode VCCE VSS Processor mode (FP = VSS) VCCE VCCE Reserved (use inhibited) Note 1: Connect VCCE and VSS to the VCCE input power supply and ground, respectively. Note 2: For the operation mode used to rewrite the internal flash memory (FP = VCCE) which is not shown in the above table, see Section 6.5, “Programming the Internal Flash Memory.” The internal ROM and extended external areas are located differently depending on how operation mode is set. (All other areas in the address space are located the same way.) The diagram below shows how the internal ROM and extended external areas are mapped into the address space in each operation mode. (For flash rewrite mode, see Section 6.5, “Programming the Internal Flash Memory.”) Figure 3.2.1 Internal ROM and Extended External Area Address Mapping of the M32180F8 in Each Operation Mode CS0 area CS0 area CS1 area CS2 area CS3 area CS1 area CS2 area CS3 area <Single-chip mode> <External extension mode> <Processor mode> Non-CS0 area Extended external area Extended external area H'0000 0000 H'000F FFFF H'0010 0000 H'001F FFFF H'0020 0000 H'003F FFFF H'0040 0000 H'005F FFFF H'007F FFFF H'0060 0000 Internal R O M area (1 Mbytes) Internal R O M area (1 Mbytes)

32180 Group User’s Manual (Rev.1.0) The 8-Mbyte area in the user space from the address H’0000 0000 to the address H’007F FFFF comprise the internal ROM and extended external areas. For the address mapping of these areas that differs with each opera- tion mode, see Section 3.2, “Operation Modes.”

3.3.1 Internal ROM Area

The internal ROM is allocated to the addresses shown below. Located at the beginning of this area is the EIT vector entry (and the ICU vector table). Table 3.3.1 Internal ROM Allocation Address Type Name Size Allocation Address M32180F8 1 Mbytes H ’0000 0000 to H’000F FFFF

3.3.2 Extended External Area

The extended external area is only available when external extension or processor mode is selected by opera- tion mode settings. When accessing the extended external area, the control signals necessary to access exter- nal devices are output. The CS0# through CS3# signals are output corresponding to the address mapping of the extended external area. The CS0#, CS1#, CS2# and CS3# signals are output for the CS0, CS1, CS2 and CS3 areas, respectively. Table 3.3.2 Address Mapping of the Extended External Area in Each Operation Mode Operation Mode Address Mapping of Extended External Area Single-chip mode None External extension mode Addresses H ’0010 0000 to H’001F FFFF (CS0 area: 1 Mbytes) Addresses H’0020 0000 to H’003F FFFF (CS1 area: 2 Mbytes) Addresses H’0040 0000 to H’005F FFFF (CS2 area: 2 Mbytes) Addresses H’0060 0000 to H’007F FFFF (CS3 area: 2 Mbytes) Processor mode Addresses H ’0000 0000 to H’001F FFFF (CS0 area: 2 Mbytes) Addresses H’0020 0000 to H’003F FFFF (CS1 area: 2 Mbytes) Addresses H’0040 0000 to H’005F FFFF (CS2 area: 2 Mbytes) Addresses H’0060 0000 to H’007F FFFF (CS3 area: 2 Mbytes)

32180 Group User’s Manual (Rev.1.0) The 8-Mbyte area from the address H’0080 0000 to the address H’00FF FFFF comprise the internal RAM and SFR (Special Function Register) areas. Of these, the space that the user can actually use is a 128-Kbyte area from the address H’0080 0000 to the address H’0081 FFFF. The other areas here are ghosts in 128-Kbyte units. (Do not use the ghost area intentionally during programming.)

3.4.1 Internal RAM Area

The internal RAM area is allocated to the addresses shown below. Table 3.4.1 Internal RAM Allocation Address Type Name Size Allocation Address M32180F8 48 Kbytes H ’0080 4000 to H’0080 FFFF

3.4.2 SFR (Special Function Register) Area

The addresses H’0080 0000 to H’0080 3FFFF comprise the SFR (Special Function Register) area. Located in this area are the internal peripheral I/O registers. Figure 3.4.1 Internal RAM and SFR (Special Function Register) Areas of the M32180F8 SFR area (16 Kbytes) Internal RAM (48 Kbytes) Virtual flash emulation areas separated in 4-Kbyte units can be allocated here. For details, see Section 6.6. H'0080 0000 H'0080 3FFF H'0080 4000 H'0080 FFFF H'0080 7FFF H'0080 8000

32180 Group User’s Manual (Rev.1.0) Note:  The Real-time Debugger (RTD) is an independent module that is operated from the outside, and is transparent to the CPU. Interrupt Controller (ICU) A-D0 C onverter Serial I/O 0–3 Wait C ontroller Flash control MJT (common part) M JT(TOP ) M JT(TIO ) M JT(TMS ) M JT(TML 0) DMA C Input/output port 07 8 1 5 +0 address +1 address H'0080 0000 H'0080 007E H'0080 00EE H'0080 0100 H'0080 0146 H'0080 0180 H'0080 0186 H'0080 01E0 H'0080 01F8 H'0080 0200 H'0080 023E H'0080 0240 H'0080 02FE H'0080 0300 H'0080 03BE H'0080 03C0 H'0080 03D8 H'0080 03E0 H'0080 03FE H'0080 0400 H'0080 0478 H'0080 0700 H'0080 077F H'0080 0080 Multijunction timer (MJT) Serial I/O 4–5 A-D1 C onverter M JT(TID1) M JT(TOU1 ) M JT(TID2) M JT(TID0) M JT(TOU0 ) M JT(TOU2 ) M JT(TML1 ) C AN 0 C AN 1 07 8 1 5 +0 address +1 address H'0080 078C H'0080 078E H'0080 07E2 H'0080 0A00 H'0080 0A26 H'0080 0A80 H'0080 0AE E H'0080 0B8C H'0080 0B8E H'0080 0B90 H'0080 0BE2 H'0080 0C8C H'0080 0C8E H'0080 0C90 H'0080 0C E2 H'0080 0FE0 H'0080 0FFE H'0080 1000 H'0080 11FE H'0080 1400 H'0080 15FE H'0080 0790 Multijunction timer (MJT) Multijunction timer (MJT) Figure 3.4.2 Outline Mapping of the SFR Area

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (1/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0000 Interrupt Vector Register 5-5 (IVECT) H'0080 0002 (Use inhibited area) H'0080 0004 Interrupt Request Mask Register (Use inhibited area) 5-6 (IMASK) H'0080 0006 SBI Control Register (SBICR) (Use inhibited area) 5-7 (SBICR) (Use inhibited area) H'0080 0060 CAN0 Transmit/Receive & Error Interrupt Control RegisterTIN30–33 Input Interrupt Control Register 5-8 (ICAN0CR) (ITIN3033CR) H'0080 0062 TID2 Output Interrupt Control Register A-D1 Conversion Interrupt Control Register 5-8 (ITID2CR) (IAD1CCR) H'0080 0064 SIO4, 5 Transmit/Receive Interrupt Control Register TOU1, 2 Output Interrupt Control Register 5-8 (ISIO45CR) (ITOU12CR) H'0080 0066 TID1 Output Interrupt Control Register RTD Interrupt Control Register 5-8 (ITID1CR) (IRTDCR) H'0080 0068 SIO2, 3 Transmit/Receive Interrupt Control Register DMA5 –9 Interrupt Control Register 5-8 (ISIO23CR) (IDMA59CR) H'0080 006A TOU0 Output Interrupt Control Register TID0 Output Interrupt Control Register 5-8 (ITOU0CR) (ITID0CR) H'0080 006C A-D0 Conversion Interrupt Control Register SIO0 Transmit Interrupt Control Register 5-8 (IAD0CCR) (ISIO0TXCR) H'0080 006E SIO0 Receive Interrupt Control Register SIO1 Transmit Interrupt Control Register 5-8 (ISIO0RXCR) (ISIO1TXCR) H'0080 0070 SIO1 Receive Interrupt Control Register DMA0 –4 Interrupt Control Register 5-8 (ISIO1RXCR) (IDMA04CR) H'0080 0072 TIO0 –3 Output Interrupt Control Register TOP6, 7 Output Interrupt Control Register 5-8 (ITIO03CR) (ITOP67CR) H'0080 0074 TOP0 –5 Output Interrupt Control Register TIO8, 9 Output Interrupt Control Register 5-8 (ITOP05CR) (ITIO89CR) H'0080 0076 TIO4 –7 Output Interrupt Control Register TOP10 Output Interrupt Control Register 5-8 (ITIO47CR) (ITOP10CR) H'0080 0078 TOP8, 9 Output Interrupt Control Register TMS0, 1 Output Interrupt Control Register 5-8 (ITOP89CR) (ITMS01CR) H'0080 007A TIN7 –11 Input Interrupt Control Register TIN0 –2 Input Interrupt Control Register 5-8 (ITIN711CR) (ITIN02CR) H'0080 007C TIN12 –19 Input Interrupt Control Register TIN20 –29 Input Interrupt Control Register 5-8 (ITIN1219CR) (ITIN2029CR) H'0080 007E TIN3 –6 Input Interrupt Control RegisterCAN1 Transmit/Receive & Error Interrupt Control Register 5-8 (ITIN36CR) (ICAN1CR) H'0080 0080 A-D0 Single Mode Register 0 A-D0 Single Mode Register 1 11-16 (AD0SIM0) (AD0SIM1) 11-18 H'0080 0082 (Use inhibited area) H'0080 0084 A-D0 Scan Mode Register 0 A-D0 Scan Mode Register 1 11-20 (AD0SCM0) (AD0SCM1) 11-22 H'0080 0086 A-D0 Disconnection Detection Assist Function Control RegisterA-D0 Conversion Speed Control Register 11-25 (AD0DDACR) (AD0CVSCR) 11-24 H'0080 0088 A-D0 Successive Approximation Register 11-29 (AD0SAR) H'0080 008A A-D0 Disconnection Detection Assist Method Select Register 11-26 (AD0DDASEL) H'0080 008C A-D0 Comparate Data Register 11-30 (AD0CMP) H'0080 008E (Use inhibited area) H'0080 0090 10-bit A-D0 Data Register 0 11-31 (AD0DT0) H'0080 0092 10-bit A-D0 Data Register 1 11-31 (AD0DT1) H'0080 0094 10-bit A-D0 Data Register 2 11-31 (AD0DT2) H'0080 0096 10-bit A-D0 Data Register 3 11-31 (AD0DT3) H'0080 0098 10-bit A-D0 Data Register 4 11-31 (AD0DT4) H'0080 009A 10-bit A-D0 Data Register 5 11-31 (AD0DT5)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (2/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 009C 10-bit A-D0 Data Register 6 11-31 (AD0DT6) H'0080 009E 10-bit A-D0 Data Register 7 11-31 (AD0DT7) H'0080 00A0 10-bit A-D0 Data Register 8 11-31 (AD0DT8) H'0080 00A2 10-bit A-D0 Data Register 9 11-31 (AD0DT9) H'0080 00A4 10-bit A-D0 Data Register 10 11-31 (AD0DT10) H'0080 00A6 10-bit A-D0 Data Register 11 11-31 (AD0DT11) H'0080 00A8 10-bit A-D0 Data Register 12 11-31 (AD0DT12) H'0080 00AA 10-bit A-D0 Data Register 13 11-31 (AD0DT13) H'0080 00AC 10-bit A-D0 Data Register 14 11-31 (AD0DT14) H'0080 00AE 10-bit A-D0 Data Register 15 11-31 (AD0DT15) (Use inhibited area) H'0080 00D0 (Use inhibited area) 8-bit A-D0 Data Register 0 11-32 (AD08DT0) H'0080 00D2 (Use inhibited area) 8-bit A-D0 Data Register 1 11-32 (AD08DT1) H'0080 00D4 (Use inhibited area) 8-bit A-D0 Data Register 2 11-32 (AD08DT2) H'0080 00D6 (Use inhibited area) 8-bit A-D0 Data Register 3 11-32 (AD08DT3) H'0080 00D8 (Use inhibited area) 8-bit A-D0 Data Register 4 11-32 (AD08DT4) H'0080 00DA (Use inhibited area) 8-bit A-D0 Data Register 5 11-32 (AD08DT5) H'0080 00DC (Use inhibited area) 8-bit A-D0 Data Register 6 11-32 (AD08DT6) H'0080 00DE (Use inhibited area) 8-bit A-D0 Data Register 7 11-32 (AD08DT7) H'0080 00E0 (Use inhibited area) 8-bit A-D0 Data Register 8 11-32 (AD08DT8) H'0080 00E2 (Use inhibited area) 8-bit A-D0 Data Register 9 11-32 (AD08DT9) H'0080 00E4 (Use inhibited area) 8-bit A-D0 Data Register 10 11-32 (AD08DT10) H'0080 00E6 (Use inhibited area) 8-bit A-D0 Data Register 11 11-32 (AD08DT11) H'0080 00E8 (Use inhibited area) 8-bit A-D0 Data Register 12 11-32 (AD08DT12) H'0080 00EA (Use inhibited area) 8-bit A-D0 Data Register 13 11-32 (AD08DT13) H'0080 00EC (Use inhibited area) 8-bit A-D0 Data Register 14 11-32 (AD08DT14) H'0080 00EE (Use inhibited area) 8-bit A-D0 Data Register 15 11-32 (AD08DT15) (Use inhibited area) H'0080 0100 SIO23 Interrupt Request Status Register SIO03 Interrupt Request Enable Register 12-9 (SI23STAT) (SI03EN) 12-10 H'0080 0102 SIO03 Interrupt Request Source Select Register (Use inhibited area) 12-11 (SI03SEL) (Use inhibited area) H'0080 0110 SIO0 Transmit Control Register SIO0 Transmit/Receive Mode Register 12-14 (S0TCNT) (S0MOD) 12-15 H'0080 0112 SIO0 Transmit Buffer Register 12-18 (S0TXB) H'0080 0114 SIO0 Receive Buffer Register 12-19 (S0RXB)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (3/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0116 SIO0 Receive Control Register SIO0 Baud Rate Register 12-20 (S0RCNT) (S0BAUR) 12-23 (Use inhibited area) H'0080 0120 SIO1 Transmit Control Register SIO1 Transmit/Receive Mode Register 12-14 (S1TCNT) (S1MOD) 12-15 H'0080 0122 SIO1 Transmit Buffer Register 12-18 (S1TXB) H'0080 0124 SIO1 Receive Buffer Register 12-19 (S1RXB) H'0080 0126 SIO1 Receive Control Register SIO1 Baud Rate Register 12-20 (S1RCNT) (S1BAUR) 12-23 (Use inhibited area) H'0080 0130 SIO2 Transmit Control Register SIO2 Transmit/Receive Mode Register 12-14 (S2TCNT) (S2MOD) 12-15 H'0080 0132 SIO2 Transmit Buffer Register 12-18 (S2TXB) H'0080 0134 SIO2 Receive Buffer Register 12-19 (S2RXB) H'0080 0136 SIO2 Receive Control Register SIO2 Baud Rate Register 12-20 (S2RCNT) (S2BAUR) 12-23 (Use inhibited area) H'0080 0140 SIO3 Transmit Control Register SIO3 Transmit/Receive Mode Register 12-14 (S3TCNT) (S3MOD) 12-15 H'0080 0142 SIO3 Transmit Buffer Register 12-18 (S3TXB) H'0080 0144 SSIO3 Receive Buffer Register 12-19 (S3RXB) H'0080 0146 SIO3 Receive Control Register SIO3 Baud Rate Register 12-20 (S3RCNT) (S3BAUR) 12-23 (Use inhibited area) H'0080 0180 CS0 Area Wait Control Register CS1 Area Wait Control Register 16-4 (CS0WTCR) (CS1WTCR) H'0080 0182 CS2 Area Wait Control Register CS3 Area Wait Control Register 16-4 (CS2WTCR) (CS3WTCR) (Use inhibited area) H'0080 01E0 Flash Mode Register Flash Status Register 1 6-4 (FMOD) (FSTAT1) 6-5 H'0080 01E2 Flash Control Register 1 Flash Control Register 2 6-7 (FCNT1) (FCNT2) 6-8 H'0080 01E4 Flash Control Register 3 Flash Control Register 4 6-9 (FCNT3) (FCNT4) H'0080 01E6 (Use inhibited area) H'0080 01E8 Virtual Flash S Bank Register 0 6-11 (FESBANK0) H'0080 01EA Virtual Flash S Bank Register 1 6-11 (FESBANK1) H'0080 01EC Virtual Flash S Bank Register 2 6-11 (FESBANK2) H'0080 01EE Virtual Flash S Bank Register 3 6-11 (FESBANK3) H'0080 01F0 Virtual Flash S Bank Register 4 6-11 (FESBANK4) H'0080 01F2 Virtual Flash S Bank Register 5 6-11 (FESBANK5) H'0080 01F4 Virtual Flash S Bank Register 6 6-11 (FESBANK6) H'0080 01F6 Virtual Flash S Bank Register 7 6-11 (FESBANK7) (Use inhibited area) H'0080 0200 (Use inhibited area) Clock Bus & Input Event Bus Control Register 10-16 (CKIEBCR) H'0080 0202 Prescaler Register 0 Prescaler Register 1 10-12 (PRS0) (PRS1)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (4/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0204 Prescaler Register 2 Output Event Bus Control Register 10-12 (PRS2) (OEBCR) 10-17 (Use inhibited area) H'0080 0210 TCLK Input Processing Control Register 10-20 (TCLKCR) H'0080 0212 TIN0 –4 Input Processing Control Register 10-21 (TIN04CR) H'0080 0214 TIN5 –8 Input Processing Control Register 10-22 (TIN58CR) H'0080 0216 TIN9 –11 Input Processing Control Register 10-23 (TIN911CR) H'0080 0218 TIN12 –19 Input Processing Control Register 10-24 (TIN1219CR) H'0080 021A TIN20 –23, TIN30–33 Input Processing Control Register 10-24 (TIN2023_3033CR) (Use inhibited area) H'0080 0220 F/F6 –15 Source Select Register 10-28 (FF615S) H'0080 0222 (Use inhibited area) F/F16 –19 Source Select Register 10-29 (FF1619S) H'0080 0224 F/F0 –15 Protect Register 10-30 (FF015P) H'0080 0226 F/F0 –15 Data Register 10-32 (FF015D) H'0080 0228 (Use inhibited area) F/F16 –20 Protect Register 10-30 (FF1620P) H'0080 022A (Use inhibited area) F/F16 –20 Data Register 10-32 (FF1620D) (Use inhibited area) H'0080 0230 TOP0 –5 Interrupt Request Status Register TOP0 –5 Interrupt Request Mask Register 10-39 (TOP05IST) (TOP05IMA) H'0080 0232 TOP6, 7 Interrupt Request Mask & Status Register TOP8, 9 Interrupt Request Mask & Status Register 10-41 (TOP67IMS) (TOP89IMS) 10-42 H'0080 0234 TIO0 –3 Interrupt Request Mask & Status Register TIO4–7 Interrupt Request Mask & Status Register 10-43 (TIO03IMS) (TIO47IMS) 10-44 H'0080 0236 TIO8, 9 Interrupt Request Mask & Status Register TMS0, 1 Interrupt Request Mask & Status Register 10-45 (TIO89IMS) (TMS01IMS) 10-46 H'0080 0238 TIN0 –2 Interrupt Request Mask & Status Register TIN3–6 Interrupt Request Mask & Status Register 10-47 (TIN02IMS) (TIN36IMS) 10-48 H'0080 023A TIN7 –11 Interrupt Request Status Register TIN7 –11 Interrupt Request Mask Register 10-49 (TIN711IST) (TIN711IMA) H'0080 023C TIN12 –19 Interrupt Request Status Register TIN12 –19 Interrupt Request Mask Register 10-51 (TIN1219IST) (TIN1219IMA) H'0080 023E TIN20 –23 Interrupt Request Mask & Status Register TIN30–33 Interrupt Request Mask & Status Register 10-53 (TIN2023IMS) (TIN3033IMS) 10-57 H'0080 0240 TOP0 Counter 10-75 (TOP0CT) H'0080 0242 TOP0 Reload Register 10-76 (TOP0RL) H'0080 0244 (Use inhibited area) H'0080 0246 TOP0 Correction Register 10-77 (TOP0CC) (Use inhibited area) H'0080 0250 TOP1 Counter 10-75 (TOP1CT) H'0080 0252 TOP1 Reload Register 10-76 (TOP1RL) H'0080 0254 (Use inhibited area) H'0080 0256 TOP1 Correction Register 10-77 (TOP1CC) (Use inhibited area)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (5/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0260 TOP2 Counter 10-75 (TOP2CT) H'0080 0262 TOP2 Reload Register 10-76 (TOP2RL) H'0080 0264 (Use inhibited area) H'0080 0266 TOP2 Correction Register 10-77 (TOP2CC) (Use inhibited area) H'0080 0270 TOP3 Counter 10-75 (TOP3CT) H'0080 0272 TOP3 Reload Register 10-76 (TOP3RL) H'0080 0274 (Use inhibited area) H'0080 0276 TOP3 Correction Register 10-77 (TOP3CC) (Use inhibited area) H'0080 0280 TOP4 Counter 10-75 (TOP4CT) H'0080 0282 TOP4 Reload Register 10-76 (TOP4RL) H'0080 0284 (Use inhibited area) H'0080 0286 TOP4 Correction Register 10-77 (TOP4CC) (Use inhibited area) H'0080 0290 TOP5 Counter 10-75 (TOP5CT) H'0080 0292 TOP5 Reload Register 10-76 (TOP5RL) H'0080 0294 (Use inhibited area) H'0080 0296 TOP5 Correction Register 10-77 (TOP5CC) H'0080 0298 (Use inhibited area) H'0080 029A TOP0 –5 Control Register 0 10-71 (TOP05CR0) H'0080 029C (Use inhibited area) TOP0 –5 Control Register 1 10-71 (TOP05CR1) (Use inhibited area) H'0080 02A0 TOP6 Counter 10-75 (TOP6CT) H'0080 02A2 TOP6 Reload Register 10-76 (TOP6RL) H'0080 02A4 (Use inhibited area) H'0080 02A6 TOP6 Correction Register 10-77 (TOP6CC) H'0080 02A8 (Use inhibited area) H'0080 02AA TOP6, 7 Control Register 10-73 (TOP67CR) (Use inhibited area) H'0080 02B0 TOP7 Counter 10-75 (TOP7CT) H'0080 02B2 TOP7 Reload Register 10-76 (TOP7RL) H'0080 02B4 (Use inhibited area) H'0080 02B6 TOP7 Correction Register 10-77 (TOP7CC) (Use inhibited area)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (6/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 02C0 TOP8 Counter 10-75 (TOP8CT) H'0080 02C2 TOP8 Reload Register 10-76 (TOP8RL) H'0080 02C4 (Use inhibited area) H'0080 02C6 TOP8 Correction Register 10-77 (TOP8CC) (Use inhibited area) H'0080 02D0 TOP9 Counter 10-75 (TOP9CT) H'0080 02D2 TOP9 Reload Register 10-76 (TOP9RL) H'0080 02D4 (Use inhibited area) H'0080 02D6 TOP9 Correction Register 10-77 (TOP9CC) (Use inhibited area) H'0080 02E0 TOP10 Counter 10-75 (TOP10CT) H'0080 02E2 TOP10 Reload Register 10-76 (TOP10RL) H'0080 02E4 (Use inhibited area) H'0080 02E6 TOP10 Correction Register 10-77 (TOP10CC) H'0080 02E8 (Use inhibited area) H'0080 02EA TOP8–10 Control Register 10-74 (TOP810CR) (Use inhibited area) H'0080 02FA TOP External Enable Permit Register 10-78 (TOPEEN) H'0080 02FC TOP Enable Protect Register 10-78 (TOPPRO) H'0080 02FE TOP Count Enable Register 10-79 (TOPCEN) H'0080 0300 TIO0 Counter 10-109 (TIO0CT) H'0080 0302 (Use inhibited area) H'0080 0304 TIO0 Reload 1 Register 10-111 (TIO0RL1) H'0080 0306 TIO0 Reload 0/ Measure Register 10-110 (TIO0RL0) (Use inhibited area) H'0080 0310 TIO1 Counter 10-109 (TIO1CT) H'0080 0312 (Use inhibited area) H'0080 0314 TIO1 Reload 1 Register 10-111 (TIO1RL1) H'0080 0316 TIO1 Reload 0/ Measure Register 10-110 (TIO1RL0) H'0080 0318 (Use inhibited area) H'0080 031A TIO0–3 Control Register 0 10-102 (TIO03CR0) H'0080 031C (Use inhibited area) TIO0–3 Control Register 1 10-103 (TIO03CR1) (Use inhibited area) H'0080 0320 TIO2 Counter 10-109 (TIO2CT) H'0080 0322 (Use inhibited area)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (7/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0324 TIO2 Reload 1 Register 10-111 (TIO2RL1) H'0080 0326 TIO2 Reload 0/ Measure Register 10-110 (TIO2RL0) (Use inhibited area) H'0080 0330 TIO3 Counter 10-109 (TIO3CT) H'0080 0332 (Use inhibited area) H'0080 0334 TIO3 Reload 1 Register 10-111 (TIO3RL1) H'0080 0336 TIO3 Reload 0/ Measure Register 10-110 (TIO3RL0) (Use inhibited area) H'0080 0340 TIO4 Counter 10-109 (TIO4CT) H'0080 0343 (Use inhibited area) H'0080 0344 TIO4 Reload 1 Register 10-111 (TIO4RL1) H'0080 0346 TIO4 Reload 0/ Measure Register 10-110 (TIO4RL0) H'0080 0348 (Use inhibited area) H'0080 034A TIO4 Control Register TIO5 Control Register 10-104 (TIO4CR) (TIO5CR) 10-106 (Use inhibited area) H'0080 0350 TIO5 Counter 10-109 (TIO5CT) H'0080 0352 (Use inhibited area) H'0080 0354 TIO5 Reload 1 Register 10-111 (TIO5RL1) H'0080 0356 TIO5 Reload 0/ Measure Register 10-110 (TIO5RL0) (Use inhibited area) H'0080 0360 TIO6 Counter 10-109 (TIO6CT) H'0080 0362 (Use inhibited area) H'0080 0364 TIO6 Reload 1 Register 10-111 (TIO6RL1) H'0080 0366 TIO6 Reload 0/ Measure Register 10-110 (TIO6RL0) H'0080 0368 (Use inhibited area) H'0080 036A TIO6 Control Register TIO7 Control Register 10-107 (TIO6CR) (TIO7CR) 10-108 (Use inhibited area) H'0080 0370 TIO7 Counter 10-109 (TIO7CT) H'0080 0372 (Use inhibited area) H'0080 0374 TIO7 Reload 1 Register 10-111 (TIO7RL1) H'0080 0376 TIO7 Reload 0/ Measure Register 10-110 (TIO7RL0) (Use inhibited area) H'0080 0380 TIO8 Counter 10-109 (TIO8CT) H'0080 0382 (Use inhibited area) H'0080 0384 TIO8 Reload 1 Register 10-111 (TIO8RL1)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (8/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0386 TIO8 Reload 0/ Measure Register 10-110 (TIO8RL0) H'0080 0388 (Use inhibited area) H'0080 038A TIO8 Control Register TIO9 Control Register 10-108 (TIO8CR) (TIO9CR) 10-109 (Use inhibited area) H'0080 0390 TIO9 Counter 10-109 (TIO9CT) H'0080 0392 (Use inhibited area) H'0080 0394 TIO9 Reload 1 Register 10-111 (TIO9RL1) H'0080 0396 TIO9 Reload 0/ Measure Register 10-110 (TIO9RL0) (Use inhibited area) H'0080 03BC TIO Enable Protect Register 10-112 (TIOPRO) H'0080 03BE TIO Count Enable Register 10-113 (TIOCEN) H'0080 03C0 TMS0 Counter 10-130 (TMS0CT) H'0080 03C2 TMS0 Measure 3 Register 10-130 (TMS0MR3) H'0080 03C4 TMS0 Measure 2 Register 10-130 (TMS0MR2) H'0080 03C6 TMS0 Measure 1 Register 10-130 (TMS0MR1) H'0080 03C8 TMS0 Measure 0 Register 10-130 (TMS0MR0) H'0080 03CA TMS0 Control Register TMS1 Control Register 10-129 (TMS0CR) (TMS1CR) (Use inhibited area) H'0080 03D0 TMS1 Counter 10-130 (TMS1CT) H'0080 03D2 TMS1 Measure 3 Register 10-130 (TMS1MR3) H'0080 03D4 TMS1 Measure 2 Register 10-130 (TMS1MR2) H'0080 03D6 TMS1 Measure 1 Register 10-130 (TMS1MR1) H'0080 03D8 TMS1 Measure 0 Register 10-130 (TMS1MR0) (Use inhibited area) H'0080 03E0 TML0 Counter (Upper) 10-135 (TML0CT) H'0080 03E2 (Lower) (Use inhibited area) H'0080 03EA (Use inhibited area) TML0 Control Register 10-134 (TML0CR) (Use inhibited area) H'0080 03F0 TML0 Measure 3 Register (Upper) 10-135 (TML0MR3) H'0080 03F2 (Lower) H'0080 03F4 TML0 Measure 2 Register (Upper) 10-135 (TML0MR2) H'0080 03F6 (Lower) H'0080 03F8 TML0 Measure 1 Register (Upper) 10-135 (TML0MR1) H'0080 03FA (Lower)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (9/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 03FC TML0 Measure 0 Register (Upper) 10-135 (TML0MR0) H'0080 03FE (Lower) H'0080 0400 DMA0 –4 Interrupt Request Status Register DMA0 –4 Interrupt Request Mask Register 9-24 (DM04ITST) (DM04ITMK) 9-25 (Use inhibited area) H'0080 0408 DMA5 –9 Interrupt Request Status Register DMA5 –9 Interrupt Request Mask Register 9-24 (DM59ITST) (DM59ITMK) 9-25 (Use inhibited area) H'0080 0410 DMA0 Channel Control Register 0 DMA0 Channel Control Register 1 9-6 (DM0CNT0) (DM0CNT1) H'0080 0412 DMA0 Source Address Register 9-19 (DM0SA) H'0080 0414 DMA0 Destination Address Register 9-20 (DM0DA) H'0080 0416 DMA0 Transfer Count Register 9-21 (DM0TCT) H'0080 0418 DMA5 Channel Control Register 0 DMA5 Channel Control Register 1 9-11 (DM5CNT0) (DM5CNT1) H'0080 041A DMA5 Source Address Register 9-19 (DM5SA) H'0080 041C DMA5 Destination Address Register 9-20 (DM5DA) H'0080 041E DMA5 Transfer Count Register 9-21 (DM5TCT) H'0080 0420 DMA1 Channel Control Register 0 DMA1 Channel Control Register 1 9-7 (DM1CNT0) (DM1CNT1) H'0080 0422 DMA1 Source Address Register 9-19 (DM1SA) H'0080 0424 DMA1 Destination Address Register 9-20 (DM1DA) H'0080 0426 DMA1 Transfer Count Register 9-21 (DM1TCT) H'0080 0428 DMA6 Channel Control Register 0 DMA6 Channel Control Register 1 9-12 (DM6CNT0) (DM6CNT1) H'0080 042A DMA6 Source Address Register 9-19 (DM6SA) H'0080 042C DMA6 Destination Address Register 9-20 (DM6DA) H'0080 042E DMA6 Transfer Count Register 9-21 (DM6TCT) H'0080 0430 DMA2 Channel Control Register 0 DMA2 Channel Control Register 1 9-8 (DM2CNT0) (DM2CNT1) H'0080 0432 DMA2 Source Address Register 9-19 (DM2SA) H'0080 0434 DMA2 Destination Address Register 9-20 (DM2DA) H'0080 0436 DMA2 Transfer Count Register 9-21 (DM2TCT) H'0080 0438 DMA7 Channel Control Register 0 DMA7 Channel Control Register 1 9-13 (DM7CNT0) (DM7CNT1) H'0080 043A DMA7 Source Address Register 9-19 (DM7SA) H'0080 043C DMA7 Destination Address Register 9-20 (DM7DA) H'0080 043E DMA7 Transfer Count Register 9-21 (DM7TCT) H'0080 0440 DMA3 Channel Control Register 0 DMA3 Channel Control Register 1 9-9 (DM3CNT0) (DM3CNT1) H'0080 0442 DMA3 Source Address Register 9-19 (DM3SA) H'0080 0444 DMA3 Destination Address Register 9-20 (DM3DA) H'0080 0446 DMA3 Transfer Count Register 9-21 (DM3TCT) H'0080 0448 DMA8 Channel Control Register 0 DMA8 Channel Control Register 1 9-14 (DM8CNT0) (DM8CNT1)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (10/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 044A DMA8 Source Address Register 9-19 (DM8SA) H'0080 044C DMA8 Destination Address Register 9-20 (DM8DA) H'0080 044E DMA8 Transfer Count Register 9-21 (DM8TCT) H'0080 0450 DMA4 Channel Control Register 0 DMA4 Channel Control Register 1 9-10 (DM4CNT0) (DM4CNT1) H'0080 0452 DMA4 Source Address Register 9-19 (DM4SA) H'0080 0454 DMA4 Destination Address Register 9-20 (DM4DA) H'0080 0456 DMA4 Transfer Count Register 9-21 (DM4TCT) H'0080 0458 DMA9 Channel Control Register 0 DMA9 Channel Control Register 1 9-15 (DM9CNT0) (DM9CNT1) H'0080 045A DMA9 Source Address Register 9-19 (DM9SA) H'0080 045C DMA9 Destination Address Register 9-20 (DM9DA) H'0080 045E DMA9 Transfer Count Register 9-21 (DM9TCT) H'0080 0460 DMA0 Software Request Generation Register 9-18 (DM0SRI) H'0080 0462 DMA1 Software Request Generation Register 9-18 (DM1SRI) H'0080 0464 DMA2 Software Request Generation Register 9-18 (DM2SRI) H'0080 0466 DMA3 Software Request Generation Register 9-18 (DM3SRI) H'0080 0468 DMA4 Software Request Generation Register 9-18 (DM4SRI) (Use inhibited area) H'0080 0470 DMA5 Software Request Generation Register 9-18 (DM5SRI) H'0080 0472 DMA6 Software Request Generation Register 9-18 (DM6SRI) H'0080 0474 DMA7 Software Request Generation Register 9-18 (DM7SRI) H'0080 0476 DMA8 Software Request Generation Register 9-18 (DM8SRI) H'0080 0478 DMA9 Software Request Generation Register 9-18 (DM9SRI) (Use inhibited area) H'0080 0700 P0 Data Register P1 Data Register 8-7 (P0DATA) (P1DATA) H'0080 0702 P2 Data Register P3 Data Register 8-7 (P2DATA) (P3DATA) H'0080 0704 P4 Data Register (Use inhibited area) 8-7 (P4DATA) H'0080 0706 P6 Data Register P7 Data Register 8-7 (P6DATA) (P7DATA) H'0080 0708 P8 Data Register P9 Data Register 8-7 (P8DATA) (P9DATA) H'0080 070A P10 Data Register P11 Data Register 8-7 (P10DATA) (P11DATA) H'0080 070C P12 Data Register P13 Data Register 8-7 (P12DATA) (P13DATA) H'0080 070E P14 Data Register P15 Data Register 8-7 (P14DATA) (P15DATA) H'0080 0710 P16 Data Register P17 Data Register 8-7 (P16DATA) (P17DATA) H'0080 0712 P18 Data Register P19 Data Register 8-7 (P18DATA) (P19DATA) H'0080 0714 P20 Data Register P21 Data Register 8-7 (P20DATA) (P21DATA) H'0080 0716 P22 Data Register (Use inhibited area) 8-7 (P22DATA)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (11/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0720 P0 Direction Register P1 Direction Register 8-8 (P0DIR) (P1DIR) H'0080 0722 P2 Direction Register P3 Direction Register 8-8 (P2DIR) (P3DIR) H'0080 0724 P4 Direction Register (Use inhibited area) 8-8 (P4DIR) H'0080 0726 P6 Direction Register P7 Direction Register 8-8 (P6DIR) (P7DIR) H'0080 0728 P8 Direction Register P9 Direction Register 8-8 (P8DIR) (P9DIR) H'0080 072A P10 Direction Register P11 Direction Register 8-8 (P10DIR) (P11DIR) H'0080 072C P12 Direction Register P13 Direction Register 8-8 (P12DIR) (P13DIR) H'0080 072E P14 Direction Register P15 Direction Register 8-8 (P14DIR) (P15DIR) H'0080 0730 P16 Direction Register P17 Direction Register 8-8 (P16DIR) (P17DIR) H'0080 0732 P18 Direction Register P19 Direction Register 8-8 (P18DIR) (P19DIR) H'0080 0734 P20 Direction Register P21 Direction Register 8-8 (P20DIR) (P21DIR) H'0080 0736 P22 Direction Register (Use inhibited area) 8-8 (P22DIR) (Use inhibited area) H'0080 0740 P0 Operation Mode Register P1 Operation Mode Register 8-9 (P0MOD) (P1MOD) H'0080 0742 P2 Operation Mode Register P3 Operation Mode Register 8-10 (P2MOD) (P3MOD) H'0080 0744 P4 Operation Mode Register Port Input Special Function Control Register 8-11 (P4MOD) (PICNT) 8-21 H'0080 0746 P6 Operation Mode Register P7 Operation Mode Register 8-11 (P6MOD) (P7MOD) 8-12 H'0080 0748 P8 Operation Mode Register P9 Operation Mode Register 8-12 (P8MOD) (P9MOD) 8-13 H'0080 074A P10 Operation Mode Register P11 Operation Mode Register 8-13 (P10MOD) (P11MOD) 8-14 H'0080 074C P12 Operation Mode Register P13 Operation Mode Register 8-14 (P12MOD) (P13MOD) 8-15 H'0080 074E P14 Operation Mode Register P15 Operation Mode Register 8-15 (P14MOD) (P15MOD) 8-16 H'0080 0750 P16 Operation Mode Register P17 Operation Mode Register 8-16 (P16MOD) (P17MOD) 8-17 H'0080 0752 P18 Operation Mode Register P19 Operation Mode Register 8-17 (P18MOD) (P19MOD) 8-18 H'0080 0754 P20 Operation Mode Register P21 Operation Mode Register 8-18 (P20MOD) (P21MOD) 8-19 H'0080 0756 P22 Operation Mode Register (Use inhibited area) 8-19 (P22MOD) (Use inhibited area) H'0080 0760 Port Group 0, 1 Input Level Setting Register Port Group 2, 3 Input Level Setting Register 8-25 (PG01LEV) (PG23LEV) H'0080 0762 Port Group 4, 5 Input Level Setting Register Port Group 6, 7 Input Level Setting Register 8-25 (PG45LEV) (PG67LEV) H'0080 0764 Port Group 8 Input Level Setting Register (Use inhibited area) 8-25 (PG8LEV) (Use inhibited area) H'0080 076A P10 Peripheral Output Select Register (Use inhibited area) 8-20 (P10SMOD) (Use inhibited area) H'0080 0776 P22 Peripheral Output Select Register (Use inhibited area) 8-20 (P22SMOD) (Use inhibited area) H'0080 077E (Use inhibited area) Bus Mode Control Register 15-9 (BUSMODC)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (12/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0780 PWM Output 0 Disable Control Register PWM Output 0 Disable Level Control Register 10-174 (PO0DISCR) (PO0LVCR) 10-177 H'0080 0782 PWM Output 1 Disable Control Register PWM Output 1 Disable Level Control Register 10-174 (PO1DISCR) (PO1LVCR) 10-177 H'0080 0784 PWM Output 2 Disable Control Register PWM Output 2 Disable Level Control Register 10-175 (PO2DISCR) (PO2LVCR) 10-177 H'0080 0786 Clock Control Register (Use inhibited area) 18-5 (CLKCR) (Use inhibited area) H'0080 078C TID0 Counter 10-144 (TID0CT) H'0080 078E TID0 Reload Register 10-144 (TID0RL) H'0080 0790 TOU0_0 Counter (Upper) 10-161 (TOU00CTW) (TOU00CTH) H'0080 0792 (Lower) 10-163 (TOU00CT) H'0080 0794 TOU0_0 Reload Register TOU0_0 Reload 1 Register 10-164 (TOU00RLW) (TOU00RL1) 10-167 H'0080 0796 TOU0_0 Reload 0 Register 10-166 (TOU00RL0) H'0080 0798 TOU0_1 Counter (Upper) 10-161 (TOU01CTW) (TOU01CTH) H'0080 079A (Lower) 10-163 (TOU01CT) H'0080 079C TOU0_1 Reload Register TOU0_1 Reload 1 Register 10-164 (TOU01RLW) (TOU01RL1) 10-167 H'0080 079E TOU0_1 Reload 0 Register 10-166 (TOU01RL0) H'0080 07A0 TOU0_2 Counter (Upper) 10-161 (TOU02CTW) (TOU02CTH) H'0080 07A2 (Lower) 10-163 (TOU02CT) H'0080 07A4 TOU0_2 Reload Register TOU0_2 Reload 1 Register 10-164 (TOU02RLW) (TOU02RL1) 10-167 H'0080 07A6 TOU0_2 Reload 0 Register 10-166 (TOU02RL0) H'0080 07A8 TOU0_3 Counter (Upper) 10-161 (TOU03CTW) (TOU03CTH) H'0080 07AA (Lower) 10-163 (TOU03CT) H'0080 07AC TOU0_3 Reload Register TOU0_3 Reload 1 Register 10-164 (TOU03RLW) (TOU03RL1) 10-167 H'0080 07AE TOU0_3 Reload 0 Register 10-166 (TOU03RL0) H'0080 07B0 TOU0_4 Counter (Upper) 10-161 (TOU04CTW) (TOU04CTH) H'0080 07B2 (Lower) 10-163 (TOU04CT) H'0080 07B4 TOU0_4 Reload Register TOU0_4 Reload 1 Register 10-164 (TOU04RLW) (TOU04RL1) 10-167 H'0080 07B6 TOU0_4 Reload 0 Register 10-166 (TOU04RL0) H'0080 07B8 TOU0_5 Counter (Upper) 10-161 (TOU05CTW) (TOU05CTH) H'0080 07BA (Lower) 10-163 (TOU05CT) H'0080 07BC TOU0_5 Reload Register TOU0_5 Reload 1 Register 10-164 (TOU05RLW) (TOU05RL1) 10-167 H'0080 07BE TOU0_5 Reload 0 Register 10-166 (TOU05RL0) H'0080 07C0 TOU0_6 Counter (Upper) 10-161 (TOU06CTW) (TOU06CTH) H'0080 07C2 (Lower) 10-163 (TOU06CT)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (13/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 07C4 TOU0_6 Reload Register TOU0_6 Reload 1 Register 10-164 (TOU06RLW) (TOU06RL1) 10-167 H'0080 07C6 TOU0_6 Reload 0 Register 10-166 (TOU06RL0) H'0080 07C8 TOU0_7 Counter (Upper) 10-161 (TOU07CTW) (TOU07CTH) H'0080 07CA (Lower) 10-163 (TOU07CT) H'0080 07CC TOU0_7 Reload Register TOU0_7 Reload 1 Register 10-164 (TOU07RLW) (TOU07RL1) 10-167 H'0080 07CE TOU0_7 Reload 0 Register 10-166 (TOU07RL0) H'0080 07D0 Prescaler Register 3 TID0 Control & Prescaler 3 Enable Register 10-12 (PRS3) (TID0PRS3EN) 10-141 H'0080 07D2 TOU0 Interrupt Request Mask Register TOU0 Interrupt Request Status Register 10-58 (TOU0IMA) (TOU0IST) H'0080 07D4 (Use inhibited area) F/F21 –28 Protect Register 10-31 (FF2128P) H'0080 07D6 (Use inhibited area) F/F21 –28 Data Register 10-33 (FF2128D) H'0080 07D8 TOU0 Control Register 1 10-158 (TOU0CR1) H'0080 07DA TOU0 Control Register 0 10-158 (TOU0CR0) H'0080 07DC (Use inhibited area) TOU0 Enable Protect Register 10-168 (TOU0PRO) H'0080 07DE (Use inhibited area) TOU0 Count Enable Register 10-169 (TOU0CEN) H'0080 07E0 PWMOFF0 Input Processing Control Register TIN24, 25 Input Processing Control Register 10-171 (PWMOFF0CR) (TIN2425CR) 10-25 H'0080 07E2 TIN24, 25 Interrupt Request Mask Register TIN24, 25 Interrupt Request Status Register 10-53 (TIN2425IMA) (TIN2425IST) (Use inhibited area) H'0080 0A00 SIO45 Interrupt Request Status Register SIO45 Interrupt Request Enable Register 12-9 (SI45STAT) (SI45EN) 12-10 H'0080 0A02 SIO45 Interrupt Source Select Register (Use inhibited area) 12-11 (SI45SEL) (Use inhibited area) H'0080 0A10 SIO4 Transmit Control Register SIO4 Transmit/Receive Mode Register 12-14 (S4TCNT) (S4MOD) 12-15 H'0080 0A12 SIO4 Transmit Buffer Register 12-18 (S4TXB) H'0080 0A14 SIO4 Receive Buffer Register 12-19 (S4RXB) H'0080 0A16 SIO4 Receive Control Register SIO4 Baud Rate Register 12-20 (S4RCNT) (S4BAUR) 12-23 (Use inhibited area) H'0080 0A20 SIO5 Transmit Control Register SIO5 Transmit/Receive Mode Register 12-14 (S5TCNT) (S5MOD) 12-15 H'0080 0A22 SIO5 Transmit Buffer Register 12-18 (S5TXB) H'0080 0A24 SIO5 Receive Buffer Register 12-19 (S5RXB) H'0080 0A26 SIO5 Receive Control Register SIO5 Baud Rate Register 12-20 (S5RCNT) (S5BAUR) 12-23 (Use inhibited area) H'0080 0A80 A-D1 Single Mode Register 0 A-D1 Single Mode Register 1 11-16 (AD1SIM0) (AD1SIM1) 11-18 H'0080 0A82 (Use inhibited area) H'0080 0A84 A-D1 Scan Mode Register 0 A-D1 Scan Mode Register 1 11-20 (AD1SCM0) (AD1SCM1) 11-22 H'0080 0A86 A-D1 Disconnection Detection Assist Function Control RegisterA-D1 Conversion Speed Control Register 11-25 (AD1DDACR) (AD1CVSCR) 11-24 H'0080 0A88 A-D1 Successive Approximation Register 11-29 (AD1SAR)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (14/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0A8A A-D1 Disconnection Detection Assist Method Select Register 11-26 (AD1DDASEL) H'0080 0A8C A-D1 Comparate Data Register 11-30 (AD1CMP) H'0080 0A8E (Use inhibited area) H'0080 0A90 10-bit A-D1 Data Register 0 11-31 (AD1DT0) H'0080 0A92 10-bit A-D1 Data Register 1 11-31 (AD1DT1) H'0080 0A94 10-bit A-D1 Data Register 2 11-31 (AD1DT2) H'0080 0A96 10-bit A-D1 Data Register 3 11-31 (AD1DT3) H'0080 0A98 10-bit A-D1 Data Register 4 11-31 (AD1DT4) H'0080 0A9A 10-bit A-D1 Data Register 5 11-31 (AD1DT5) H'0080 0A9C 10-bit A-D1 Data Register 6 11-31 (AD1DT6) H'0080 0A9E 10-bit A-D1 Data Register 7 11-31 (AD1DT7) H'0080 0AA0 10-bit A-D1 Data Register 8 11-31 (AD1DT8) H'0080 0AA2 10-bit A-D1 Data Register 9 11-31 (AD1DT9) H'0080 0AA4 10-bit A-D1 Data Register 10 11-31 (AD1DT10) H'0080 0AA6 10-bit A-D1 Data Register 11 11-31 (AD1DT11) H'0080 0AA8 10-bit A-D1 Data Register 12 11-31 (AD1DT12) H'0080 0AAA 10-bit A-D1 Data Register 13 11-31 (AD1DT13) H'0080 0AAC 10-bit A-D1 Data Register 14 11-31 (AD1DT14) H'0080 0AAE 10-bit A-D1 Data Register 15 11-31 (AD1DT15) (Use inhibited area) H'0080 0AD0 (Use inhibited area) 8-bit A-D1 Data Register 0 11-32 (AD18DT0) H'0080 0AD2 (Use inhibited area) 8-bit A-D1 Data Register 1 11-32 (AD18DT1) H'0080 0AD4 (Use inhibited area) 8-bit A-D1 Data Register 2 11-32 (AD18DT2) H'0080 0AD6 (Use inhibited area) 8-bit A-D1 Data Register 3 11-32 (AD18DT3) H'0080 0AD8 (Use inhibited area) 8-bit A-D1 Data Register 4 11-32 (AD18DT4) H'0080 0ADA (Use inhibited area) 8-bit A-D1 Data Register 5 11-32 (AD18DT5) H'0080 0ADC (Use inhibited area) 8-bit A-D1 Data Register 6 11-32 (AD18DT6) H'0080 0ADE (Use inhibited area) 8-bit A-D1 Data Register 7 11-32 (AD18DT7) H'0080 0AE0 (Use inhibited area) 8-bit A-D1 Data Register 8 11-32 (AD18DT8) H'0080 0AE2 (Use inhibited area) 8-bit A-D1 Data Register 9 11-32 (AD18DT9) H'0080 0AE4 (Use inhibited area) 8-bit A-D1 Data Register 10 11-32 (AD18DT10) H'0080 0AE6 (Use inhibited area) 8-bit A-D1 Data Register 11 11-32 (AD18DT11) H'0080 0AE8 (Use inhibited area) 8-bit A-D1 Data Register 12 11-32 (AD18DT12) H'0080 0AEA (Use inhibited area) 8-bit A-D1 Data Register 13 11-32 (AD18DT13) H'0080 0AEC (Use inhibited area) 8-bit A-D1 Data Register 14 11-32 (AD18DT14)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (15/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0AEE (Use inhibited area) 8-bit A-D1 Data Register 15 11-32 (AD18DT15) (Use inhibited area) H'0080 0B8C TID1 Counter 10-144 (TID1CT) H'0080 0B8E TID1 Reload Register 10-144 (TID1RL) H'0080 0B90 TOU1_0 Counter (Upper) 10-161 (TOU10CTW) (TOU10CTH) H'0080 0B92 (Lower) 10-163 (TOU10CT) H'0080 0B94 TOU1_0 Reload Register TOU1_0 Reload 1 Register 10-164 (TOU10RLW) (TOU10RL1) 10-167 H'0080 0B96 TOU1_0 Reload 0 Register 10-166 (TOU10RL0) H'0080 0B98 TOU1_1 Counter (Upper) 10-161 (TOU11CTW) (TOU11CTH) H'0080 0B9A (Lower) 10-163 (TOU11CT) H'0080 0B9C TOU1_1 Reload Register TOU1_1 Reload 1 Register 10-164 (TOU11RLW) (TOU11RL1) 10-167 H'0080 0B9E TOU1_1 Reload 0 Register 10-166 (TOU11RL0) H'0080 0BA0 TOU1_2 Counter (Upper) 10-161 (TOU12CTW) (TOU12CTH) H'0080 0BA2 (Lower) 10-163 (TOU12CT) H'0080 0BA4 TOU1_2 Reload Register TOU1_2 Reload 1 Register 10-164 (TOU12RLW) (TOU12RL1) 10-167 H'0080 0BA6 TOU1_2 Reload 0 Register 10-166 (TOU12RL0) H'0080 0BA8 TOU1_3 Counter (Upper) 10-161 (TOU13CTW) (TOU13CTH) H'0080 0BAA (Lower) 10-163 (TOU13CT) H'0080 0BAC TOU1_3 Reload Register TOU1_3 Reload 1 Register 10-164 (TOU13RLW) (TOU13RL1) 10-167 H'0080 0BAE TOU1_3 Reload 0 Register 10-166 (TOU13RL0) H'0080 0BB0 TOU1_4 Counter (Upper) 10-161 (TOU14CTW) (TOU14CTH) H'0080 0BB2 (Lower) 10-163 (TOU14CT) H'0080 0BB4 TOU1_4 Reload Register TOU1_4 Reload 1 Register 10-164 (TOU14RLW) (TOU14RL1) 10-167 H'0080 0BB6 TOU1_4 Reload 0 Register 10-166 (TOU14RL0) H'0080 0BB8 TOU1_5 Counter (Upper) 10-161 (TOU15CTW) (TOU15CTH) H'0080 0BBA (Lower) 10-163 (TOU15CT) H'0080 0BBC TOU1_5 Reload Register TOU1_5 Reload 1 Register 10-164 (TOU15RLW) (TOU15RL1) 10-167 H'0080 0BBE TOU1_5 Reload 0 Register 10-166 (TOU15RL0) H'0080 0BC0 TOU1_6 Counter (Upper) 10-161 (TOU16CTW) (TOU16CTH) H'0080 0BC2 (Lower) 10-163 (TOU16CT) H'0080 0BC4 TOU1_6 Reload Register TOU1_6 Reload 1 Register 10-164 (TOU16RLW) (TOU16RL1) 10-167 H'0080 0BC6 TOU1_6 Reload 0 Register 10-166 (TOU16RL0) H'0080 0BC8 TOU1_7 Counter (Upper) 10-161 (TOU17CTW) (TOU17CTH) H'0080 0BCA (Lower) 10-163 (TOU17CT)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (16/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0BCC TOU1_7 Reload Register TOU1_7 Reload 1 Register 10-164 (TOU17RLW) (TOU17RL1) 10-167 H'0080 0BCE TOU1_7 Reload 0 Register 10-166 (TOU17RL0) H'0080 0BD0 Prescaler Register 4 TID1 Control & Prescaler 4 Enable Register 10-12 (PRS4) (TID1PRS4EN) 10-142 H'0080 0BD2 TOU1 Interrupt Request Mask Register TOU1 Interrupt Request Status Register 10-60 (TOU1IMA) (TOU1IST) H'0080 0BD4 (Use inhibited area) F/F29 –36 Protect Register 10-31 (FF2936P) H'0080 0BD6 (Use inhibited area) F/F29 –36 Data Register 10-33 (FF2936D) H'0080 0BD8 TOU1 Control Register 1 10-159 (TOU1CR1) H'0080 0BDA TOU1 Control Register 0 10-159 (TOU1CR0) H'0080 0BDC (Use inhibited area) TOU1 Enable Protect Register 10-168 (TOU1PRO) H'0080 0BDE (Use inhibited area) TOU1 Count Enable Register 10-169 (TOU1CEN) H'0080 0BE0 PWMOFF1 Input Processing Control Register TIN26, 27 Input Processing Control Register 10-171 (PWMOFF1CR) (TIN2627CR) 10-25 H'0080 0BE2 TIN26, 27 Interrupt Request Mask Register TIN26, 27 Interrupt Request Status Register 10-54 (TIN2627IMA) (TIN2627IST) (Use inhibited area) H'0080 0C8C TID2 Counter 10-144 (TID2CT) H'0080 0C8E TID2 Reload Register 10-144 (TID2RL) H'0080 0C90 TOU2_0 Counter (Upper) 10-161 (TOU20CTW) (TOU20CTH) H'0080 0C92 (Lower) 10-163 (TOU20CT) H'0080 0C94 TOU2_0 Reload Register TOU2_0 Reload 1 Register 10-164 (TOU20RLW) (TOU20RL1) 10-167 H'0080 0C96 TOU2_0 Reload 0 Register 10-166 (TOU20RL0) H'0080 0C98 TOU2_1 Counter (Upper) 10-161 (TOU21CTW) (TOU21CTH) H'0080 0C9A (Lower) 10-163 (TOU21CT) H'0080 0C9C TOU2_1 Reload Register TOU2_1 Reload 1 Register 10-164 (TOU21RLW) (TOU21RL1) 10-167 H'0080 0C9E TOU2_1 Reload 0 Register 10-166 (TOU21RL0) H'0080 0CA0 TOU2_2 Counter (Upper) 10-161 (TOU22CTW) (TOU22CTH) H'0080 0CA2 (Lower) 10-163 (TOU22CT) H'0080 0CA4 TOU2_2 Reload Register TOU2_2 Reload 1 Register 10-164 (TOU22RLW) (TOU22RL1) 10-167 H'0080 0CA6 TOU2_2 Reload 0 Register 10-166 (TOU22RL0) H'0080 0CA8 TOU2_3 Counter (Upper) 10-161 (TOU23CTW) (TOU23CTH) H'0080 0CAA (Lower) 10-163 (TOU23CT) H'0080 0CAC TOU2_3 Reload Register TOU2_3 Reload 1 Register 10-164 (TOU23RLW) (TOU23RL1) 10-167 H'0080 0CAE TOU2_3 Reload 0 Register 10-166 (TOU23RL0) H'0080 0CB0 TOU2_4 Counter (Upper) 10-161 (TOU24CTW) (TOU24CTH) H'0080 0CB2 (Lower) 10-163 (TOU24CT) H'0080 0CB4 TOU2_4 Reload Register TOU2_4 Reload 1 Register 10-164 (TOU24RLW) (TOU24RL1) 10-167 H'0080 0CB6 TOU2_4 Reload 0 Register 10-166 (TOU24RL0)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (17/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0CB8 TOU2_5 Counter (Upper) 10-161 (TOU25CTW) (TOU25CTH) H'0080 0CBA (Lower) 10-163 (TOU25CT) H'0080 0CBC TOU2_5 Reload Register TOU2_5 Reload 1 Register 10-164 (TOU25RLW) (TOU25RL1) 10-167 H'0080 0CBE TOU2_5 Reload 0 Register 10-166 (TOU25RL0) H'0080 0CC0 TOU2_6 Counter (Upper) 10-161 (TOU26CTW) (TOU26CTH) H'0080 0CC2 (Lower) 10-163 (TOU26CT) H'0080 0CC4 TOU2_6 Reload Register TOU2_6 Reload 1 Register 10-164 (TOU26RLW) (TOU26RL1) 10-167 H'0080 0CC6 TOU2_6 Reload 0 Register 10-166 (TOU26RL0) H'0080 0CC8 TOU2_7 Counter (Upper) 10-161 (TOU27CTW) (TOU27CTH) H'0080 0CCA (Lower) 10-163 (TOU27CT) H'0080 0CCC TOU2_7 Reload Register TOU2_7 Reload 1 Register 10-164 (TOU27RLW) (TOU27RL1) 10-167 H'0080 0CCE TOU2_7 Reload 0 Register 10-166 (TOU27RL0) H'0080 0CD0 Prescaler Register 5 TID2 Control & Prescaler 5 Enable Register 10-12 (PRS5) (TID2PRS5EN) 10-143 H'0080 0CD2 TOU2 Interrupt Request Mask Register TOU2 Interrupt Request Status Register 10-61 (TOU2IMA) (TOU2IST) H'0080 0CD4 (Use inhibited area) F/F37–44 Protect Register 10-31 (FF3744P) H'0080 0CD6 (Use inhibited area) F/F37–44 Data Register 10-34 (FF3744D) H'0080 0CD8 TOU2 Control Register 1 10-160 (TOU2CR1) H'0080 0CDA TOU2 Control Register 0 10-160 (TOU2CR0) H'0080 0CDC (Use inhibited area) TOU2 Enable Protect Register 10-168 (TOU2PRO) H'0080 0CDE (Use inhibited area) TOU2 Count Enable Register 10-169 (TOU2CEN) H'0080 0CE0 PWMOFF2 Input Processing Control Register TIN28, 29 Input Processing Control Register 10-172 (PWMOFF2CR) (TIN2829CR) 10-25 H'0080 0CE2 TIN28, 29 Interrupt Request Mask Register TIN28, 29 Interrupt Request Status Register 10-54 (TIN2829IMA) (TIN2829IST) (Use inhibited area) H'0080 0FE0 TML1 Counter (Upper) 10-135 (TML1CT) H'0080 0FE2 (Lower) (Use inhibited area) H'0080 0FEA (Use inhibited area) TML1 Control Register 10-134 (TML1CR) (Use inhibited area) H'0080 0FF0 TML1 Measure 3 Register (Upper) 10-135 (TML1MR3) H'0080 0FF2 (Lower) H'0080 0FF4 TML1 Measure 2 Register (Upper) 10-135 (TML1MR2) H'0080 0FF6 (Lower) H'0080 0FF8 TML1 Measure 1 Register (Upper) 10-135 (TML1MR1) H'0080 0FFA (Lower)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (18/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0FFC TML1 Measure 0 Register (Upper) 10-135 (TML1MR0) H'0080 0FFE (Lower) (Use inhibited area) H'0080 1000 CAN0 Control Register 13-15 (CAN0CNT) H'0080 1002 CAN0 Status Register 13-18 (CAN0STAT) H'0080 1004 CAN0 Frame Format Select Register 13-21 (CAN0FFS) H'0080 1006 CAN0 Configuration Register 13-22 (CAN0CONF) H'0080 1008 CAN0 Timestamp Count Register 13-24 (CAN0TSTMP) H'0080 100A CAN0 Receive Error Count Register CAN0 Transmit Error Count Register 13-25 (CAN0REC) (CAN0TEC) H'0080 100C CAN0 Slot Interrupt Request Status Register 13-29 (CAN0SLIST) H'0080 100E (Use inhibited area) H'0080 1010 CAN0 Slot Interrupt Request Enable Register 13-30 (CAN0SLIEN) H'0080 1012 (Use inhibited area) H'0080 1014 CAN0 Error Interrupt Request Status Register CAN0 Error Interrupt Request Enable Register 13-31 (CAN0ERIST) (CAN0ERIEN) 13-32 H'0080 1016 CAN0 Baud Rate Prescaler CAN0 Cause of Error Register 13-26 (CAN0BRP) (CAN0EF) 13-45 H'0080 1018 CAN0 Mode Register CAN0 DMA Transfer Request Select Register 13-46 (CAN0MOD) (CAN0DMARQ) 13-47 (Use inhibited area) H'0080 1028 CAN0 Global Mask Register Standard ID 0 CAN0 Global Mask Register Standard ID 1 13-48 (C0GMSKS0) (C0GMSKS1) H'0080 102A CAN0 Global Mask Register Extended ID 0 CAN0 Global Mask Register Extended ID 1 13-49 (C0GMSKE0) (C0GMSKE1) H'0080 102C CAN0 Global Mask Register Extended ID 2 (Use inhibited area) 13-50 (C0GMSKE2) H'0080 102E (Use inhibited area) H'0080 1030 CAN0 Local Mask Register A Standard ID 0 CAN0 Local Mask Register A Standard ID 1 13-48 (C0LMSKAS0) (C0LMSKAS1) H'0080 1032 CAN0 Local Mask Register A Extended ID 0 CAN0 Local Mask Register A Extended ID 1 13-49 (C0LMSKAE0) (C0LMSKAE1) H'0080 1034 CAN0 Local Mask Register A Extended ID 2 (Use inhibited area) 13-50 (C0LMSKAE2) H'0080 1036 (Use inhibited area) H'0080 1038 CAN0 Local Mask Register B Standard ID 0 CAN0 Local Mask Register B Standard ID 1 13-48 (C0LMSKBS0) (C0LMSKBS1) H'0080 103A CAN0 Local Mask Register B Extended ID 0 CAN0 Local Mask Register B Extended ID 1 13-49 (C0LMSKBE0) (C0LMSKBE1) H'0080 103C CAN0 Local Mask Register B Extended ID 2 (Use inhibited area) 13-50 (C0LMSKBE2) H'0080 103E (Use inhibited area) H'0080 1040 CAN0 Single Shot Mode Control Register 13-52 (CAN0SSMODE) H'0080 1042 (Use inhibited area) H'0080 1044 CAN0 Single-Shot Interrupt Request Status Register 13-33 (CAN0SSIST) H'0080 1046 (Use inhibited area) H'0080 1048 CAN0 Single-Shot Interrupt Request Enable Register 3-34 (CAN0SSIEN) H'0080 1050 CAN0 Message Slot 0 Control Register CAN0 Message Slot 1 Control Register 13-53 (C0MSL0CNT) (C0MSL1CNT)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (19/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1052 CAN0 Message Slot 2 Control Register CAN0 Message Slot 3 Control Register 13-53 (C0MSL2CNT) (C0MSL3CNT) H'0080 1054 CAN0 Message Slot 4 Control Register CAN0 Message Slot 5 Control Register 13-53 (C0MSL4CNT) (C0MSL5CNT) H'0080 1056 CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register 13-53 (C0MSL6CNT) (C0MSL7CNT) H'0080 1058 CAN0 Message Slot 8 Control Register CAN0 Message Slot 9 Control Register 13-53 (C0MSL8CNT) (C0MSL9CNT) H'0080 105A CAN0 Message Slot 10 Control Register CAN0 Message Slot 11 Control Register 13-53 (C0MSL10CNT) (C0MSL11CNT) H'0080 105C CAN0 Message Slot 12 Control Register CAN0 Message Slot 13 Control Register 13-53 (C0MSL12CNT) (C0MSL13CNT) H'0080 105E CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register 13-53 (C0MSL14CNT) (C0MSL15CNT) (Use inhibited area) H'0080 1100 CAN0 Message Slot 0 Standard ID 0 CAN0 Message Slot 0 Standard ID 1 13-57 (C0MSL0SID0) (C0MSL0SID1) 13-58 H'0080 1102 CAN0 Message Slot 0 Extended ID 0 CAN0 Message Slot 0 Extended ID 1 13-59 (C0MSL0EID0) (C0MSL0EID1) 13-60 H'0080 1104 CAN0 Message Slot 0 Extended ID 2 CAN0 Message Slot 0 Data Length Register 13-61 (C0MSL0EID2) (C0MSL0DLC) 13-62 H'0080 1106 CAN0 Message Slot 0 Data 0 CAN0 Message Slot 0 Data 1 13-63 (C0MSL0DT0) (C0MSL0DT1) 13-64 H'0080 1108 CAN0 Message Slot 0 Data 2 CAN0 Message Slot 0 Data 3 13-65 (C0MSL0DT2) (C0MSL0DT3) 13-66 H'0080 110A CAN0 Message Slot 0 Data 4 CAN0 Message Slot 0 Data 5 13-67 (C0MSL0DT4) (C0MSL0DT5) 13-68 H'0080 110C CAN0 Message Slot 0 Data 6 CAN0 Message Slot 0 Data 7 13-69 (C0MSL0DT6) (C0MSL0DT7) 13-70 H'0080 110E CAN0 Message Slot 0 Timestamp 13-71 (C0MSL0TSP) H'0080 1110 CAN0 Message Slot 1 Standard ID 0 CAN0 Message Slot 1 Standard ID 1 13-57 (C0MSL1SID0) (C0MSL1SID1) 13-58 H'0080 1112 CAN0 Message Slot 1 Extended ID 0 CAN0 Message Slot 1 Extended ID 1 13-59 (C0MSL1EID0) (C0MSL1EID1) 13-60 H'0080 1114 CAN0 Message Slot 1 Extended ID 2 CAN0 Message Slot 1 Data Length Register 13-61 (C0MSL1EID2) (C0MSL1DLC) 13-62 H'0080 1116 CAN0 Message Slot 1 Data 0 CAN0 Message Slot 1 Data 1 13-63 (C0MSL1DT0) (C0MSL1DT1) 13-64 H'0080 1118 CAN0 Message Slot 1 Data 2 CAN0 Message Slot 1 Data 3 13-65 (C0MSL1DT2) (C0MSL1DT3) 13-66 H'0080 111A CAN0 Message Slot 1 Data 4 CAN0 Message Slot 1 Data 5 13-67 (C0MSL1DT4) (C0MSL1DT5) 13-68 H'0080 111C CAN0 Message Slot 1 Data 6 CAN0 Message Slot 1 Data 7 13-69 (C0MSL1DT6) (C0MSL1DT7) 13-70 H'0080 111E CAN0 Message Slot 1 Timestamp 13-71 (C0MSL1TSP) H'0080 1120 CAN0 Message Slot 2 Standard ID 0 CAN0 Message Slot 2 Standard ID 1 13-57 (C0MSL2SID0) (C0MSL2SID1) 13-58 H'0080 1122 CAN0 Message Slot 2 Extended ID 0 CAN0 Message Slot 2 Extended ID 1 13-59 (C0MSL2EID0) (C0MSL2EID1) 13-60 H'0080 1124 CAN0 Message Slot 2 Extended ID 2 CAN0 Message Slot 2 Data Length Register 13-61 (C0MSL2EID2) (C0MSL2DLC) 13-62 H'0080 1126 CAN0 Message Slot 2 Data 0 CAN0 Message Slot 2 Data 1 13-63 (C0MSL2DT0) (C0MSL2DT1) 13-64 H'0080 1128 CAN0 Message Slot 2 Data 2 CAN0 Message Slot 2 Data 3 13-65 (C0MSL2DT2) (C0MSL2DT3) 13-66 H'0080 112A CAN0 Message Slot 2 Data 4 CAN0 Message Slot 2 Data 5 13-67 (C0MSL2DT4) (C0MSL2DT5) 13-68 H'0080 112C CAN0 Message Slot 2 Data 6 CAN0 Message Slot 2 Data 7 13-69 (C0MSL2DT6) (C0MSL2DT7) 13-70 H'0080 112E CAN0 Message Slot 2 Timestamp 13-71 (C0MSL2TSP) H'0080 1130 CAN0 Message Slot 3 Standard ID 0 CAN0 Message Slot 3 Standard ID 1 13-57 (C0MSL3SID0) (C0MSL3SID1) 13-58 H'0080 1132 CAN0 Message Slot 3 Extended ID 0 CAN0 Message Slot 3 Extended ID 1 13-59 (C0MSL3EID0) (C0MSL3EID1) 13-60 H'0080 1134 CAN0 Message Slot 3 Extended ID 2 CAN0 Message Slot 3 Data Length Register 13-61 (C0MSL3EID2) (C0MSL3DLC) 13-62

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (20/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1136 CAN0 Message Slot 3 Data 0 CAN0 Message Slot 3 Data 1 13-63 (C0MSL3DT0) (C0MSL3DT1) 13-64 H'0080 1138 CAN0 Message Slot 3 Data 2 CAN0 Message Slot 3 Data 3 13-65 (C0MSL3DT2) (C0MSL3DT3) 13-66 H'0080 113A CAN0 Message Slot 3 Data 4 CAN0 Message Slot 3 Data 5 13-67 (C0MSL3DT4) (C0MSL3DT5) 13-68 H'0080 113C CAN0 Message Slot 3 Data 6 CAN0 Message Slot 3 Data 7 13-69 (C0MSL3DT6) (C0MSL3DT7) 13-70 H'0080 113E CAN0 Message Slot 3 Timestamp 13-71 (C0MSL3TSP) H'0080 1140 CAN0 Message Slot 4 Standard ID 0 CAN0 Message Slot 4 Standard ID 1 13-57 (C0MSL4SID0) (C0MSL4SID1) 13-58 H'0080 1142 CAN0 Message Slot 4 Extended ID 0 CAN0 Message Slot 4 Extended ID 1 13-59 (C0MSL4EID0) (C0MSL4EID1) 13-60 H'0080 1144 CAN0 Message Slot 4 Extended ID 2 CAN0 Message Slot 4 Data Length Register 13-61 (C0MSL4EID2) (C0MSL4DLC) 13-62 H'0080 1146 CAN0 Message Slot 4 Data 0 CAN0 Message Slot 4 Data 1 13-63 (C0MSL4DT0) (C0MSL4DT1) 13-64 H'0080 1148 CAN0 Message Slot 4 Data 2 CAN0 Message Slot 4 Data 3 13-65 (C0MSL4DT2) (C0MSL4DT3) 13-66 H'0080 114A CAN0 Message Slot 4 Data 4 CAN0 Message Slot 4 Data 5 13-67 (C0MSL4DT4) (C0MSL4DT5) 13-68 H'0080 114C CAN0 Message Slot 4 Data 6 CAN0 Message Slot 4 Data 7 13-69 (C0MSL4DT6) (C0MSL4DT7) 13-70 H'0080 114E CAN0 Message Slot 4 Timestamp 13-71 (C0MSL4TSP) H'0080 1150 CAN0 Message Slot 5 Standard ID 0 CAN0 Message Slot 5 Standard ID 1 13-57 (C0MSL5SID0) (C0MSL5SID1) 13-58 H'0080 1152 CAN0 Message Slot 5 Extended ID 0 CAN0 Message Slot 5 Extended ID 1 13-59 (C0MSL5EID0) (C0MSL5EID1) 13-60 H'0080 1154 CAN0 Message Slot 5 Extended ID 2 CAN0 Message Slot 5 Data Length Register 13-61 (C0MSL5EID2) (C0MSL5DLC) 13-62 H'0080 1156 CAN0 Message Slot 5 Data 0 CAN0 Message Slot 5 Data 1 13-63 (C0MSL5DT0) (C0MSL5DT1) 13-64 H'0080 1158 CAN0 Message Slot 5 Data 2 CAN0 Message Slot 5 Data 3 13-65 (C0MSL5DT2) (C0MSL5DT3) 13-66 H'0080 115A CAN0 Message Slot 5 Data 4 CAN0 Message Slot 5 Data 5 13-67 (C0MSL5DT4) (C0MSL5DT5) 13-68 H'0080 115C CAN0 Message Slot 5 Data 6 CAN0 Message Slot 5 Data 7 13-69 (C0MSL5DT6) (C0MSL5DT7) 13-70 H'0080 115E CAN0 Message Slot 5 Timestamp 13-71 (C0MSL5TSP) H'0080 1160 CAN0 Message Slot 6 Standard ID 0 CAN0 Message Slot 6 Standard ID 1 13-57 (C0MSL6SID0) (C0MSL6SID1) 13-58 H'0080 1162 CAN0 Message Slot 6 Extended ID 0 CAN0 Message Slot 6 Extended ID 1 13-59 (C0MSL6EID0) (C0MSL6EID1) 13-60 H'0080 1164 CAN0 Message Slot 6 Extended ID 2 CAN0 Message Slot 6 Data Length Register 13-61 (C0MSL6EID2) (C0MSL6DLC) 13-62 H'0080 1166 CAN0 Message Slot 6 Data 0 CAN0 Message Slot 6 Data 1 13-63 (C0MSL6DT0) (C0MSL6DT1) 13-64 H'0080 1168 CAN0 Message Slot 6 Data 2 CAN0 Message Slot 6 Data 3 13-65 (C0MSL6DT2) (C0MSL6DT3) 13-66 H'0080 116A CAN0 Message Slot 6 Data 4 CAN0 Message Slot 6 Data 5 13-67 (C0MSL6DT4) (C0MSL6DT5) 13-68 H'0080 116C CAN0 Message Slot 6 Data 6 CAN0 Message Slot 6 Data 7 13-69 (C0MSL6DT6) (C0MSL6DT7) 13-70 H'0080 116E CAN0 Message Slot 6 Timestamp 13-71 (C0MSL6TSP) H'0080 1170 CAN0 Message Slot 7 Standard ID 0 CAN0 Message Slot 7 Standard ID 1 13-57 (C0MSL7SID0) (C0MSL7SID1) 13-58 H'0080 1172 CAN0 Message Slot 7 Extended ID 0 CAN0 Message Slot 7 Extended ID 1 13-59 (C0MSL7EID0) (C0MSL7EID1) 13-60 H'0080 1174 CAN0 Message Slot 7 Extended ID 2 CAN0 Message Slot 7 Data Length Register 13-61 (C0MSL7EID2) (C0MSL7DLC) 13-62 H'0080 1176 CAN0 Message Slot 7 Data 0 CAN0 Message Slot 7 Data 1 13-63 (C0MSL7DT0) (C0MSL7DT1) 13-64 H'0080 1178 CAN0 Message Slot 7 Data 2 CAN0 Message Slot 7 Data 3 13-65 (C0MSL7DT2) (C0MSL7DT3) 13-66 H'0080 117A CAN0 Message Slot 7 Data 4 CAN0 Message Slot 7 Data 5 13-67 (C0MSL7DT4) (C0MSL7DT5) 13-68

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (21/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 117C CAN0 Message Slot 7 Data 6 CAN0 Message Slot 7 Data 7 13-69 (C0MSL7DT6) (C0MSL7DT7) 13-70 H'0080 117E CAN0 Message Slot 7 Timestamp 13-71 (C0MSL7TSP) H'0080 1180 CAN0 Message Slot 8 Standard ID 0 CAN0 Message Slot 8 Standard ID 1 13-57 (C0MSL8SID0) (C0MSL8SID1) 13-58 H'0080 1182 CAN0 Message Slot 8 Extended ID 0 CAN0 Message Slot 8 Extended ID 1 13-59 (C0MSL8EID0) (C0MSL8EID1) 13-60 H'0080 1184 CAN0 Message Slot 8 Extended ID 2 CAN0 Message Slot 8 Data Length Register 13-61 (C0MSL8EID2) (C0MSL8DLC) 13-62 H'0080 1186 CAN0 Message Slot 8 Data 0 CAN0 Message Slot 8 Data 1 13-63 (C0MSL8DT0) (C0MSL8DT1) 13-64 H'0080 1188 CAN0 Message Slot 8 Data 2 CAN0 Message Slot 8 Data 3 13-65 (C0MSL8DT2) (C0MSL8DT3) 13-66 H'0080 118A CAN0 Message Slot 8 Data 4 CAN0 Message Slot 8 Data 5 13-67 (C0MSL8DT4) (C0MSL8DT5) 13-68 H'0080 118C CAN0 Message Slot 8 Data 6 CAN0 Message Slot 8 Data 7 13-69 (C0MSL8DT6) (C0MSL8DT7) 13-70 H'0080 118E CAN0 Message Slot 8 Timestamp 13-71 (C0MSL8TSP) H'0080 1190 CAN0 Message Slot 9 Standard ID 0 CAN0 Message Slot 9 Standard ID 1 13-57 (C0MSL9SID0) (C0MSL9SID1) 13-58 H'0080 1192 CAN0 Message Slot 9 Extended ID 0 CAN0 Message Slot 9 Extended ID 1 13-59 (C0MSL9EID0) (C0MSL9EID1) 13-60 H'0080 1194 CAN0 Message Slot 9 Extended ID 2 CAN0 Message Slot 9 Data Length Register 13-61 (C0MSL9EID2) (C0MSL9DLC) 13-62 H'0080 1196 CAN0 Message Slot 9 Data 0 CAN0 Message Slot 9 Data 1 13-63 (C0MSL9DT0) (C0MSL9DT1) 13-64 H'0080 1198 CAN0 Message Slot 9 Data 2 CAN0 Message Slot 9 Data 3 13-65 (C0MSL9DT2) (C0MSL9DT3) 13-66 H'0080 119A CAN0 Message Slot 9 Data 4 CAN0 Message Slot 9 Data 5 13-67 (C0MSL9DT4) (C0MSL9DT5) 13-68 H'0080 119C CAN0 Message Slot 9 Data 6 CAN0 Message Slot 9 Data 7 13-69 (C0MSL9DT6) (C0MSL9DT7) 13-70 H'0080 119E CAN0 Message Slot 9 Timestamp 13-71 (C0MSL9TSP) H'0080 11A0 CAN0 Message Slot 10 Standard ID 0 CAN0 Message Slot 10 Standard ID 1 13-57 (C0MSL10SID0) (C0MSL10SID1) 13-58 H'0080 11A2 CAN0 Message Slot 10 Extended ID 0 CAN0 Message Slot 10 Extended ID 1 13-59 (C0MSL10EID0) (C0MSL10EID1) 13-60 H'0080 11A4 CAN0 Message Slot 10 Extended ID 2 CAN0 Message Slot 10 Data Length Register 13-61 (C0MSL10EID2) (C0MSL10DLC) 13-62 H'0080 11A6 CAN0 Message Slot 10 Data 0 CAN0 Message Slot 10 Data 1 13-63 (C0MSL10DT0) (C0MSL10DT1) 13-64 H'0080 11A8 CAN0 Message Slot 10 Data 2 CAN0 Message Slot 10 Data 3 13-65 (C0MSL10DT2) (C0MSL10DT3) 13-66 H'0080 11AA CAN0 Message Slot 10 Data 4 CAN0 Message Slot 10 Data 5 13-67 (C0MSL10DT4) (C0MSL10DT5) 13-68 H'0080 11AC CAN0 Message Slot 10 Data 6 CAN0 Message Slot 10 Data 7 13-69 (C0MSL10DT6) (C0MSL10DT7) 13-70 H'0080 11AE CAN0 Message Slot 10 Timestamp 13-71 (C0MSL10TSP) H'0080 11B0 CAN0 Message Slot 11 Standard ID 0 CAN0 Message Slot 11 Standard ID 1 13-57 (C0MSL11SID0) (C0MSL11SID1) 13-58 H'0080 11B2 CAN0 Message Slot 11 Extended ID 0 CAN0 Message Slot 11 Extended ID 1 13-59 (C0MSL11EID0) (C0MSL11EID1) 13-60 H'0080 11B4 CAN0 Message Slot 11 Extended ID 2 CAN0 Message Slot 11 Data Length Register 13-61 (C0MSL11EID2) (C0MSL11DLC) 13-62 H'0080 11B6 CAN0 Message Slot 11 Data 0 CAN0 Message Slot 11 Data 1 13-63 (C0MSL11DT0) (C0MSL11DT1) 13-64 H'0080 11B8 CAN0 Message Slot 11 Data 2 CAN0 Message Slot 11 Data 3 13-65 (C0MSL11DT2) (C0MSL11DT3) 13-66 H'0080 11BA CAN0 Message Slot 11 Data 4 CAN0 Message Slot 11 Data 5 13-67 (C0MSL11DT4) (C0MSL11DT5) 13-68 H'0080 11BC CAN0 Message Slot 11 Data 6 CAN0 Message Slot 11 Data 7 13-69 (C0MSL11DT6) (C0MSL11DT7) 13-70 H'0080 11BE CAN0 Message Slot 11 Timestamp 13-71 (C0MSL11TSP) H'0080 11C0 CAN0 Message Slot 12 Standard ID 0 CAN0 Message Slot 12 Standard ID 1 13-57 (C0MSL12SID0) (C0MSL12SID1) 13-58

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (22/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 11C2 CAN0 Message Slot 12 Extended ID 0 CAN0 Message Slot 12 Extended ID 1 13-59 (C0MSL12EID0) (C0MSL12EID1) 13-60 H'0080 11C4 CAN0 Message Slot 12 Extended ID 2 CAN0 Message Slot 12 Data Length Register 13-61 (C0MSL12EID2) (C0MSL12DLC) 13-62 H'0080 11C6 CAN0 Message Slot 12 Data 0 CAN0 Message Slot 12 Data 1 13-63 (C0MSL12DT0) (C0MSL12DT1) 13-64 H'0080 11C8 CAN0 Message Slot 12 Data 2 CAN0 Message Slot 12 Data 3 13-65 (C0MSL12DT2) (C0MSL12DT3) 13-66 H'0080 11CA CAN0 Message Slot 12 Data 4 CAN0 Message Slot 12 Data 5 13-67 (C0MSL12DT4) (C0MSL12DT5) 13-68 H'0080 11CC CAN0 Message Slot 12 Data 6 CAN0 Message Slot 12 Data 7 13-69 (C0MSL12DT6) (C0MSL12DT7) 13-70 H'0080 11CE CAN0 Message Slot 12 Timestamp 13-71 (C0MSL12TSP) H'0080 11D0 CAN0 Message Slot 13 Standard ID 0 CAN0 Message Slot 13 Standard ID 1 13-57 (C0MSL13SID0) (C0MSL13SID1) 13-58 H'0080 11D2 CAN0 Message Slot 13 Extended ID 0 CAN0 Message Slot 13 Extended ID 1 13-59 (C0MSL13EID0) (C0MSL13EID1) 13-60 H'0080 11D4 CAN0 Message Slot 13 Extended ID 2 CAN0 Message Slot 13 Data Length Register 13-61 (C0MSL13EID2) (C0MSL13DLC) 13-62 H'0080 11D6 CAN0 Message Slot 13 Data 0 CAN0 Message Slot 13 Data 1 13-63 (C0MSL13DT0) (C0MSL13DT1) 13-64 H'0080 11D8 CAN0 Message Slot 13 Data 2 CAN0 Message Slot 13 Data 3 13-65 (C0MSL13DT2) (C0MSL13DT3) 13-66 H'0080 11DA CAN0 Message Slot 13 Data 4 CAN0 Message Slot 13 Data 5 13-67 (C0MSL13DT4) (C0MSL13DT5) 13-68 H'0080 11DC CAN0 Message Slot 13 Data 6 CAN0 Message Slot 13 Data 7 13-69 (C0MSL13DT6) (C0MSL13DT7) 13-70 H'0080 11DE CAN0 Message Slot 13 Timestamp 13-71 (C0MSL13TSP) H'0080 11E0 CAN0 Message Slot 14 Standard ID 0 CAN0 Message Slot 14 Standard ID 1 13-57 (C0MSL14SID0) (C0MSL14SID1) 13-58 H'0080 11E2 CAN0 Message Slot 14 Extended ID 0 CAN0 Message Slot 14 Extended ID 1 13-59 (C0MSL14EID0) (C0MSL14EID1) 13-60 H'0080 11E4 CAN0 Message Slot 14 Extended ID 2 CAN0 Message Slot 14 Data Length Register 13-61 (C0MSL14EID2) (C0MSL14DLC) 13-62 H'0080 11E6 CAN0 Message Slot 14 Data 0 CAN0 Message Slot 14 Data 1 13-63 (C0MSL14DT0) (C0MSL14DT1) 13-64 H'0080 11E8 CAN0 Message Slot 14 Data 2 CAN0 Message Slot 14 Data 3 13-65 (C0MSL14DT2) (C0MSL14DT3) 13-66 H'0080 11EA CAN0 Message Slot 14 Data 4 CAN0 Message Slot 14 Data 5 13-67 (C0MSL14DT4) (C0MSL14DT5) 13-68 H'0080 11EC CAN0 Message Slot 14 Data 6 CAN0 Message Slot 14 Data 7 13-69 (C0MSL14DT6) (C0MSL14DT7) 13-70 H'0080 11EE CAN0 Message Slot 14 Timestamp 13-71 (C0MSL14TSP) H'0080 11F0 CAN0 Message Slot 15 Standard ID 0 CAN0 Message Slot 15 Standard ID 1 13-57 (C0MSL15SID0) (C0MSL15SID1) 13-58 H'0080 11F2 CAN0 Message Slot 15 Extended ID 0 CAN0 Message Slot 15 Extended ID 1 13-59 (C0MSL15EID0) (C0MSL15EID1) 13-60 H'0080 11F4 CAN0 Message Slot 15 Extended ID 2 CAN0 Message Slot 15 Data Length Register 13-61 (C0MSL15EID2) (C0MSL15DLC) 13-62 H'0080 11F6 CAN0 Message Slot 15 Data 0 CAN0 Message Slot 15 Data 1 13-63 (C0MSL15DT0) (C0MSL15DT1) 13-64 H'0080 11F8 CAN0 Message Slot 15 Data 2 CAN0 Message Slot 15 Data 3 13-65 (C0MSL15DT2) (C0MSL15DT3) 13-66 H'0080 11FA CAN0 Message Slot 15 Data 4 CAN0 Message Slot 15 Data 5 13-67 (C0MSL15DT4) (C0MSL15DT5) 13-68 H'0080 11FC CAN0 Message Slot 15 Data 6 CAN0 Message Slot 15 Data 7 13-69 (C0MSL15DT6) (C0MSL15DT7) 13-70 H'0080 11FE CAN0 Message Slot 15 Timestamp 13-71 (C0MSL15TSP) (Use inhibited area) H'0080 1400 CAN1 Control Register 13-15 (CAN1CNT) H'0080 1402 CAN1 Status Register 13-18 (CAN1STAT) H'0080 1404 CAN1 Frame Format Select Register 13-21 (CAN1FFS)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (23/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1406 CAN1 Configuration Register 13-22 (CAN1CONF) H'0080 1408 CAN1 Timestamp Count Register 13-24 (CAN1TSTMP) H'0080 140A CAN1 Receive Error Count Register CAN1 Transmit Error Count Register 13-25 (CAN1REC) (CAN1TEC) H'0080 140C CAN1 Slot Interrupt Request Status Register 13-29 (CAN1SLIST) H'0080 140E (Use inhibited area) H'0080 1410 CAN1 Slot Interrupt Request Enable Register 13-30 (CAN1SLIEN) H'0080 1412 (Use inhibited area) H'0080 1414 CAN1 Error Interrupt Request Status Register CAN1 Error Interrupt Request Enable Register 13-31 (CAN1ERIST) (CAN1ERIEN) 13-32 H'0080 1416 CAN1 Baud Rate Prescaler CAN1 Cause of Error Register 13-26 (CAN1BRP) (CAN1EF) 13-45 H'0080 1418 CAN1 Mode Register (Use inhibited area) 13-46 (CAN1MOD) (Use inhibited area) H'0080 1428 CAN1 Global Mask Register Standard ID 0 CAN1 Global Mask Register Standard ID 1 13-48 (C1GMSKS0) (C1GMSKS1) H'0080 142A CAN1 Global Mask Register Extended ID 0 CAN1 Global Mask Register Extended ID 1 13-49 (C1GMSKE0) (C1GMSKE1) H'0080 142C CAN1 Global Mask Register Extended ID 2 (Use inhibited area) 13-50 (C1GMSKE2) H'0080 142E (Use inhibited area) H'0080 1430 CAN1 Local Mask Register A Standard ID 0 CAN1 Local Mask Register A Standard ID 1 13-48 (C1LMSKAS0) (C1LMSKAS1) H'0080 1432 CAN1 Local Mask Register A Extended ID 0 CAN1 Local Mask Register A Extended ID 1 13-49 (C1LMSKAE0) (C1LMSKAE1) H'0080 1434 CAN1 Local Mask Register A Extended ID 2 (Use inhibited area) 13-50 (C1LMSKAE2) H'0080 1436 (Use inhibited area) H'0080 1438 CAN1 Local Mask Register B Standard ID 0 CAN1 Local Mask Register B Standard ID 1 13-48 (C1LMSKBS0) (C1LMSKBS1) H'0080 143A CAN1 Local Mask Register B Extended ID 0 CAN1 Local Mask Register B Extended ID 1 13-49 (C1LMSKBE0) (C1LMSKBE1) H'0080 143C CAN1 Local Mask Register B Extended ID 2 (Use inhibited area) 13-50 (C1LMSKBE2) H'0080 143E (Use inhibited area) H'0080 1440 CAN1 Single-Shot Mode Control Register 13-52 (CAN1SSMODE) H'0080 1442 (Use inhibited area) H'0080 1444 CAN1 Single-Shot Interrupt Request Status Register 13-33 (CAN1SSIST) H'0080 1446 (Use inhibited area) H'0080 1448 CAN1 Single-Shot Interrupt Request Enable Register 13-34 (CAN1SSIEN) (Use inhibited area) H'0080 1450 CAN1 Message Slot 0 Control Register CAN1 Message Slot 1 Control Register 13-53 (C1MSL0CNT) (C1MSL1CNT) H'0080 1452 CAN1 Message Slot 2 Control Register CAN1 Message Slot 3 Control Register 13-53 (C1MSL2CNT) (C1MSL3CNT) H'0080 1454 CAN1 Message Slot 4 Control Register CAN1 Message Slot 5 Control Register 13-53 (C1MSL4CNT) (C1MSL5CNT) H'0080 1456 CAN1 Message Slot 6 Control Register CAN1 Message Slot 7 Control Register 13-53 (C1MSL6CNT) (C1MSL7CNT) H'0080 1458 CAN1 Message Slot 8 Control Register CAN1 Message Slot 9 Control Register 13-53 (C1MSL8CNT) (C1MSL9CNT) H'0080 145A CAN1 Message Slot 10 Control Register CAN1 Message Slot 11 Control Register 13-53 (C1MSL10CNT) (C1MSL11CNT)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (24/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 145C CAN1 Message Slot 12 Control Register CAN1 Message Slot 13 Control Register 13-53 (C1MSL12CNT) (C1MSL13CNT) H'0080 145E CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register 13-53 (C1MSL14CNT) (C1MSL15CNT) (Use inhibited area) H'0080 1500 CAN1 Message Slot 0 Standard ID 0 CAN1 Message Slot 0 Standard ID 1 13-57 (C1MSL0SID0) (C1MSL0SID1) 13-58 H'0080 1502 CAN1 Message Slot 0 Extended ID 0 CAN1 Message Slot 0 Extended ID 1 13-59 (C1MSL0EID0) (C1MSL0EID1) 13-60 H'0080 1504 CAN1 Message Slot 0 Extended ID 2 CAN1 Message Slot 0 Data Length Register 13-61 (C1MSL0EID2) (C1MSL0DLC) 13-62 H'0080 1506 CAN1 Message Slot 0 Data 0 CAN1 Message Slot 0 Data 1 13-63 (C1MSL0DT0) (C1MSL0DT1) 13-64 H'0080 1508 CAN1 Message Slot 0 Data 2 CAN1 Message Slot 0 Data 3 13-65 (C1MSL0DT2) (C1MSL0DT3) 13-66 H'0080 150A CAN1 Message Slot 0 Data 4 CAN1 Message Slot 0 Data 5 13-67 (C1MSL0DT4) (C1MSL0DT5) 13-68 H'0080 150C CAN1 Message Slot 0 Data 6 CAN1 Message Slot 0 Data 7 13-69 (C1MSL0DT6) (C1MSL0DT7) 13-70 H'0080 150E CAN1 Message Slot 0 Timestamp 13-71 (C1MSL0TSP) H'0080 1510 CAN1 Message Slot 1 Standard ID 0 CAN1 Message Slot 1 Standard ID 1 13-57 (C1MSL1SID0) (C1MSL1SID1) 13-58 H'0080 1512 CAN1 Message Slot 1 Extended ID 0 CAN1 Message Slot 1 Extended ID 1 13-59 (C1MSL1EID0) (C1MSL1EID1) 13-60 H'0080 1514 CAN1 Message Slot 1 Extended ID 2 CAN1 Message Slot 1 Data Length Register 13-61 (C1MSL1EID2) (C1MSL1DLC) 13-62 H'0080 1516 CAN1 Message Slot 1 Data 0 CAN1 Message Slot 1 Data 1 13-63 (C1MSL1DT0) (C1MSL1DT1) 13-64 H'0080 1518 CAN1 Message Slot 1 Data 2 CAN1 Message Slot 1 Data 3 13-65 (C1MSL1DT2) (C1MSL1DT3) 13-66 H'0080 151A CAN1 Message Slot 1 Data 4 CAN1 Message Slot 1 Data 5 13-67 (C1MSL1DT4) (C1MSL1DT5) 13-68 H'0080 151C CAN1 Message Slot 1 Data 6 CAN1 Message Slot 1 Data 7 13-69 (C1MSL1DT6) (C1MSL1DT7) 13-70 H'0080 151E CAN1 Message Slot 1 Timestamp 13-71 (C1MSL1TSP) H'0080 1520 CAN1 Message Slot 2 Standard ID 0 CAN1 Message Slot 2 Standard ID 1 13-57 (C1MSL2SID0) (C1MSL2SID1) 13-58 H'0080 1522 CAN1 Message Slot 2 Extended ID 0 CAN1 Message Slot 2 Extended ID 1 13-59 (C1MSL2EID0) (C1MSL2EID1) 13-60 H'0080 1524 CAN1 Message Slot 2 Extended ID 2 CAN1 Message Slot 2 Data Length Register 13-61 (C1MSL2EID2) (C1MSL2DLC) 13-62 H'0080 1526 CAN1 Message Slot 2 Data 0 CAN1 Message Slot 2 Data 1 13-63 (C1MSL2DT0) (C1MSL2DT1) 13-64 H'0080 1528 CAN1 Message Slot 2 Data 2 CAN1 Message Slot 2 Data 3 13-65 (C1MSL2DT2) (C1MSL2DT3) 13-66 H'0080 152A CAN1 Message Slot 2 Data 4 CAN1 Message Slot 2 Data 5 13-67 (C1MSL2DT4) (C1MSL2DT5) 13-68 H'0080 152C CAN1 Message Slot 2 Data 6 CAN1 Message Slot 2 Data 7 13-69 (C1MSL2DT6) (C1MSL2DT7) 13-70 H'0080 152E CAN1 Message Slot 2 Timestamp 13-71 (C1MSL2TSP) H'0080 1530 CAN1 Message Slot 3 Standard ID 0 CAN1 Message Slot 3 Standard ID 1 13-57 (C1MSL3SID0) (C1MSL3SID1) 13-58 H'0080 1532 CAN1 Message Slot 3 Extended ID 0 CAN1 Message Slot 3 Extended ID 1 13-59 (C1MSL3EID0) (C1MSL3EID1) 13-60 H'0080 1534 CAN1 Message Slot 3 Extended ID 2 CAN1 Message Slot 3 Data Length Register 13-61 (C1MSL3EID2) (C1MSL3DLC) 13-62 H'0080 1536 CAN1 Message Slot 3 Data 0 CAN1 Message Slot 3 Data 1 13-63 (C1MSL3DT0) (C1MSL3DT1) 13-64 H'0080 1538 CAN1 Message Slot 3 Data 2 CAN1 Message Slot 3 Data 3 13-65 (C1MSL3DT2) (C1MSL3DT3) 13-66 H'0080 153A CAN1 Message Slot 3 Data 4 CAN1 Message Slot 3 Data 5 13-67 (C1MSL3DT4) (C1MSL3DT5) 13-68 H'0080 153C CAN1 Message Slot 3 Data 6 CAN1 Message Slot 3 Data 7 13-69 (C1MSL3DT6) (C1MSL3DT7) 13-70 H'0080 153E CAN1 Message Slot 3 Timestamp 13-71 (C1MSL3TSP)

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (25/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1540 CAN1 Message Slot 4 Standard ID 0 CAN1 Message Slot 4 Standard ID 1 13-57 (C1MSL4SID0) (C1MSL4SID1) 13-58 H'0080 1542 CAN1 Message Slot 4 Extended ID 0 CAN1 Message Slot 4 Extended ID 1 13-59 (C1MSL4EID0) (C1MSL4EID1) 13-60 H'0080 1544 CAN1 Message Slot 4 Extended ID 2 CAN1 Message Slot 4 Data Length Register 13-61 (C1MSL4EID2) (C1MSL4DLC) 13-62 H'0080 1546 CAN1 Message Slot 4 Data 0 CAN1 Message Slot 4 Data 1 13-63 (C1MSL4DT0) (C1MSL4DT1) 13-64 H'0080 1548 CAN1 Message Slot 4 Data 2 CAN1 Message Slot 4 Data 3 13-65 (C1MSL4DT2) (C1MSL4DT3) 13-66 H'0080 154A CAN1 Message Slot 4 Data 4 CAN1 Message Slot 4 Data 5 13-67 (C1MSL4DT4) (C1MSL4DT5) 13-68 H'0080 154C CAN1 Message Slot 4 Data 6 CAN1 Message Slot 4 Data 7 13-69 (C1MSL4DT6) (C1MSL4DT7) 13-70 H'0080 154E CAN1 Message Slot 4 Timestamp 13-71 (C1MSL4TSP) H'0080 1550 CAN1 Message Slot 5 Standard ID 0 CAN1 Message Slot 5 Standard ID 1 13-57 (C1MSL5SID0) (C1MSL5SID1) 13-58 H'0080 1552 CAN1 Message Slot 5 Extended ID 0 CAN1 Message Slot 5 Extended ID 1 13-59 (C1MSL5EID0) (C1MSL5EID1) 13-60 H'0080 1554 CAN1 Message Slot 5 Extended ID 2 CAN1 Message Slot 5 Data Length Register 13-61 (C1MSL5EID2) (C1MSL5DLC) 13-62 H'0080 1556 CAN1 Message Slot 5 Data 0 CAN1 Message Slot 5 Data 1 13-63 (C1MSL5DT0) (C1MSL5DT1) 13-64 H'0080 1558 CAN1 Message Slot 5 Data 2 CAN1 Message Slot 5 Data 3 13-65 (C1MSL5DT2) (C1MSL5DT3) 13-66 H'0080 155A CAN1 Message Slot 5 Data 4 CAN1 Message Slot 5 Data 5 13-67 (C1MSL5DT4) (C1MSL5DT5) 13-68 H'0080 155C CAN1 Message Slot 5 Data 6 CAN1 Message Slot 5 Data 7 13-69 (C1MSL5DT6) (C1MSL5DT7) 13-70 H'0080 155E CAN1 Message Slot 5 Timestamp 13-71 (C1MSL5TSP) H'0080 1560 CAN1 Message Slot 6 Standard ID 0 CAN1 Message Slot 6 Standard ID 1 13-57 (C1MSL6SID0) (C1MSL6SID1) 13-58 H'0080 1562 CAN1 Message Slot 6 Extended ID 0 CAN1 Message Slot 6 Extended ID 1 13-59 (C1MSL6EID0) (C1MSL6EID1) 13-60 H'0080 1564 CAN1 Message Slot 6 Extended ID 2 CAN1 Message Slot 6 Data Length Register 13-61 (C1MSL6EID2) (C1MSL6DLC) 13-62 H'0080 1566 CAN1 Message Slot 6 Data 0 CAN1 Message Slot 6 Data 1 13-63 (C1MSL6DT0) (C1MSL6DT1) 13-64 H'0080 1568 CAN1 Message Slot 6 Data 2 CAN1 Message Slot 6 Data 3 13-65 (C1MSL6DT2) (C1MSL6DT3) 13-66 H'0080 156A CAN1 Message Slot 6 Data 4 CAN1 Message Slot 6 Data 5 13-67 (C1MSL6DT4) (C1MSL6DT5) 13-68 H'0080 156C CAN1 Message Slot 6 Data 6 CAN1 Message Slot 6 Data 7 13-69 (C1MSL6DT6) (C1MSL6DT7) 13-70 H'0080 156E CAN1 Message Slot 6 Timestamp 13-71 (C1MSL6TSP) H'0080 1570 CAN1 Message Slot 7 Standard ID 0 CAN1 Message Slot 7 Standard ID 1 13-57 (C1MSL7SID0) (C1MSL7SID1) 13-58 H'0080 1572 CAN1 Message Slot 7 Extended ID 0 CAN1 Message Slot 7 Extended ID 1 13-59 (C1MSL7EID0) (C1MSL7EID1) 13-60 H'0080 1574 CAN1 Message Slot 7 Extended ID 2 CAN1 Message Slot 7 Data Length Register 13-61 (C1MSL7EID2) (C1MSL7DLC) 13-62 H'0080 1576 CAN1 Message Slot 7 Data 0 CAN1 Message Slot 7 Data 1 13-63 (C1MSL7DT0) (C1MSL7DT1) 13-64 H'0080 1578 CAN1 Message Slot 7 Data 2 CAN1 Message Slot 7 Data 3 13-65 (C1MSL7DT2) (C1MSL7DT3) 13-66 H'0080 157A CAN1 Message Slot 7 Data 4 CAN1 Message Slot 7 Data 5 13-67 (C1MSL7DT4) (C1MSL7DT5) 13-68 H'0080 157C CAN1 Message Slot 7 Data 6 CAN1 Message Slot 7 Data 7 13-69 (C1MSL7DT6) (C1MSL7DT7) 13-70 H'0080 157E CAN1 Message Slot 7 Timestamp 13-71 (C1MSL7TSP) H'0080 1580 CAN1 Message Slot 8 Standard ID 0 CAN1 Message Slot 8 Standard ID 1 13-57 (C1MSL8SID0) (C1MSL8SID1) 13-58 H'0080 1582 CAN1 Message Slot 8 Extended ID 0 CAN1 Message Slot 8 Extended ID 1 13-59 (C1MSL8EID0) (C1MSL8EID1) 13-60 H'0080 1584 CAN1 Message Slot 8 Extended ID 2 CAN1 Message Slot 8 Data Length Register 13-61 (C1MSL8EID2) (C1MSL8DLC) 13-62

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (26/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1586 CAN1 Message Slot 8 Data 0 CAN1 Message Slot 8 Data 1 13-63 (C1MSL8DT0) (C1MSL8DT1) 13-64 H'0080 1588 CAN1 Message Slot 8 Data 2 CAN1 Message Slot 8 Data 3 13-65 (C1MSL8DT2) (C1MSL8DT3) 13-66 H'0080 158A CAN1 Message Slot 8 Data 4 CAN1 Message Slot 8 Data 5 13-67 (C1MSL8DT4) (C1MSL8DT5) 13-68 H'0080 158C CAN1 Message Slot 8 Data 6 CAN1 Message Slot 8 Data 7 13-69 (C1MSL8DT6) (C1MSL8DT7) 13-70 H'0080 158E CAN1 Message Slot 8 Timestamp 13-71 (C1MSL8TSP) H'0080 1590 CAN1 Message Slot 9 Standard ID 0 CAN1 Message Slot 9 Standard ID 1 13-57 (C1MSL9SID0) (C1MSL9SID1) 13-58 H'0080 1592 CAN1 Message Slot 9 Extended ID 0 CAN1 Message Slot 9 Extended ID 1 13-59 (C1MSL9EID0) (C1MSL9EID1) 13-60 H'0080 1594 CAN1 Message Slot 9 Extended ID 2 CAN1 Message Slot 9 Data Length Register 13-61 (C1MSL9EID2) (C1MSL9DLC) 13-62 H'0080 1596 CAN1 Message Slot 9 Data 0 CAN1 Message Slot 9 Data 1 13-63 (C1MSL9DT0) (C1MSL9DT1) 13-64 H'0080 1598 CAN1 Message Slot 9 Data 2 CAN1 Message Slot 9 Data 3 13-65 (C1MSL9DT2) (C1MSL9DT3) 13-66 H'0080 159A CAN1 Message Slot 9 Data 4 CAN1 Message Slot 9 Data 5 13-67 (C1MSL9DT4) (C1MSL9DT5) 13-68 H'0080 159C CAN1 Message Slot 9 Data 6 CAN1 Message Slot 9 Data 7 13-69 (C1MSL9DT6) (C1MSL9DT7) 13-70 H'0080 159E CAN1 Message Slot 9 Timestamp 13-71 (C1MSL9TSP) H'0080 15A0 CAN1 Message Slot 10 Standard ID 0 CAN1 Message Slot 10 Standard ID 1 13-57 (C1MSL10SID0) (C1MSL10SID1) 13-58 H'0080 15A2 CAN1 Message Slot 10 Extended ID 0 CAN1 Message Slot 10 Extended ID 1 13-59 (C1MSL10EID0) (C1MSL10EID1) 13-60 H'0080 15A4 CAN1 Message Slot 10 Extended ID 2 CAN1 Message Slot 10 Data Length Register 13-61 (C1MSL10EID2) (C1MSL10DLC) 13-62 H'0080 15A6 CAN1 Message Slot 10 Data 0 CAN1 Message Slot 10 Data 1 13-63 (C1MSL10DT0) (C1MSL10DT1) 13-64 H'0080 15A8 CAN1 Message Slot 10 Data 2 CAN1 Message Slot 10 Data 3 13-65 (C1MSL10DT2) (C1MSL10DT3) 13-66 H'0080 15AA CAN1 Message Slot 10 Data 4 CAN1 Message Slot 10 Data 5 13-67 (C1MSL10DT4) (C1MSL10DT5) 13-68 H'0080 15AC CAN1 Message Slot 10 Data 6 CAN1 Message Slot 10 Data 7 13-69 (C1MSL10DT6) (C1MSL10DT7) 13-70 H'0080 15AE CAN1 Message Slot 10 Timestamp 13-71 (C1MSL10TSP) H'0080 15B0 CAN1 Message Slot 11 Standard ID 0 CAN1 Message Slot 11 Standard ID 1 13-57 (C1MSL11SID0) (C1MSL11SID1) 13-58 H'0080 15B2 CAN1 Message Slot 11 Extended ID 0 CAN1 Message Slot 11 Extended ID 1 13-59 (C1MSL11EID0) (C1MSL11EID1) 13-60 H'0080 15B4 CAN1 Message Slot 11 Extended ID 2 CAN1 Message Slot 11 Data Length Register 13-61 (C1MSL11EID2) (C1MSL11DLC) 13-62 H'0080 15B6 CAN1 Message Slot 11 Data 0 CAN1 Message Slot 11 Data 1 13-63 (C1MSL11DT0) (C1MSL11DT1) 13-64 H'0080 15B8 CAN1 Message Slot 11 Data 2 CAN1 Message Slot 11 Data 3 13-65 (C1MSL11DT2) (C1MSL11DT3) 13-66 H'0080 15BA CAN1 Message Slot 11 Data 4 CAN1 Message Slot 11 Data 5 13-67 (C1MSL11DT4) (C1MSL11DT5) 13-68 H'0080 15BC CAN1 Message Slot 11 Data 6 CAN1 Message Slot 11 Data 7 13-69 (C1MSL11DT6) (C1MSL11DT7) 13-70 H'0080 15BE CAN1 Message Slot 11 Timestamp 13-71 (C1MSL11TSP) H'0080 15C0 CAN1 Message Slot 12 Standard ID 0 CAN1 Message Slot 12 Standard ID 1 13-57 (C1MSL12SID0) (C1MSL12SID1) 13-58 H'0080 15C2 CAN1 Message Slot 12 Extended ID 0 CAN1 Message Slot 12 Extended ID 1 13-59 (C1MSL12EID0) (C1MSL12EID1) 13-60 H'0080 15C4 CAN1 Message Slot 12 Extended ID 2 CAN1 Message Slot 12 Data Length Register 13-61 (C1MSL12EID2) (C1MSL12DLC) 13-62 H'0080 15C6 CAN1 Message Slot 12 Data 0 CAN1 Message Slot 12 Data 1 13-63 (C1MSL12DT0) (C1MSL12DT1) 13-64 H'0080 15C8 CAN1 Message Slot 12 Data 2 CAN1 Message Slot 12 Data 3 13-65 (C1MSL12DT2) (C1MSL12DT3) 13-66 H'0080 15CA CAN1 Message Slot 12 Data 4 CAN1 Message Slot 12 Data 5 13-67 (C1MSL12DT4) (C1MSL12DT5) 13-68

32180 Group User’s Manual (Rev.1.0) SFR Area Register Map (27/27) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 15CC CAN1 Message Slot 12 Data 6 CAN1 Message Slot 12 Data 7 13-69 (C1MSL12DT6) (C1MSL12DT7) 13-70 H'0080 15CE CAN1 Message Slot 12 Timestamp 13-71 (C1MSL12TSP) H'0080 15D0 CAN1 Message Slot 13 Standard ID 0 CAN1 Message Slot 13 Standard ID 1 13-57 (C1MSL13SID0) (C1MSL13SID1) 13-58 H'0080 15D2 CAN1 Message Slot 13 Extended ID 0 CAN1 Message Slot 13 Extended ID 1 13-59 (C1MSL13EID0) (C1MSL13EID1) 13-60 H'0080 15D4 CAN1 Message Slot 13 Extended ID 2 CAN1 Message Slot 13 Data Length Register 13-61 (C1MSL13EID2) (C1MSL13DLC) 13-62 H'0080 15D6 CAN1 Message Slot 13 Data 0 CAN1 Message Slot 13 Data 1 13-63 (C1MSL13DT0) (C1MSL13DT1) 13-64 H'0080 15D8 CAN1 Message Slot 13 Data 2 CAN1 Message Slot 13 Data 3 13-65 (C1MSL13DT2) (C1MSL13DT3) 13-66 H'0080 15DA CAN1 Message Slot 13 Data 4 CAN1 Message Slot 13 Data 5 13-67 (C1MSL13DT4) (C1MSL13DT5) 13-68 H'0080 15DC CAN1 Message Slot 13 Data 6 CAN1 Message Slot 13 Data 7 13-69 (C1MSL13DT6) (C1MSL13DT7) 13-70 H'0080 15DE CAN1 Message Slot 13 Timestamp 13-71 (C1MSL13TSP) H'0080 15E0 CAN1 Message Slot 14 Standard ID 0 CAN1 Message Slot 14 Standard ID 1 13-57 (C1MSL14SID0) (C1MSL14SID1) 13-58 H'0080 15E2 CAN1 Message Slot 14 Extended ID 0 CAN1 Message Slot 14 Extended ID 1 13-59 (C1MSL14EID0) (C1MSL14EID1) 13-60 H'0080 15E4 CAN1 Message Slot 14 Extended ID 2 CAN1 Message Slot 14 Data Length Register 13-61 (C1MSL14EID2) (C1MSL14DLC) 13-62 H'0080 15E6 CAN1 Message Slot 14 Data 0 CAN1 Message Slot 14 Data 1 13-63 (C1MSL14DT0) (C1MSL14DT1) 13-64 H'0080 15E8 CAN1 Message Slot 14 Data 2 CAN1 Message Slot 14 Data 3 13-65 (C1MSL14DT2) (C1MSL14DT3) 13-66 H'0080 15EA CAN1 Message Slot 14 Data 4 CAN1 Message Slot 14 Data 5 13-67 (C1MSL14DT4) (C1MSL14DT5) 13-68 H'0080 15EC CAN1 Message Slot 14 Data 6 CAN1 Message Slot 14 Data 7 13-69 (C1MSL14DT6) (C1MSL14DT7) 13-70 H'0080 15EE CAN1 Message Slot 14 Timestamp 13-71 (C1MSL14TSP) H'0080 15F0 CAN1 Message Slot 15 Standard ID 0 CAN1 Message Slot 15 Standard ID 1 13-57 (C1MSL15SID0) (C1MSL15SID1) 13-58 H'0080 15F2 CAN1 Message Slot 15 Extended ID 0 CAN1 Message Slot 15 Extended ID 1 13-59 (C1MSL15EID0) (C1MSL15EID1) 13-60 H'0080 15F4 CAN1 Message Slot 15 Extended ID 2 CAN1 Message Slot 15 Data Length Register 13-61 (C1MSL15EID2) (C1MSL15DLC) 13-62 H'0080 15F6 CAN1 Message Slot 15 Data 0 CAN1 Message Slot 15 Data 1 13-63 (C1MSL15DT0) (C1MSL15DT1) 13-64 H'0080 15F8 CAN1 Message Slot 15 Data 2 CAN1 Message Slot 15 Data 3 13-65 (C1MSL15DT2) (C1MSL15DT3) 13-66 H'0080 15FA CAN1 Message Slot 15 Data 4 CAN1 Message Slot 15 Data 5 13-67 (C1MSL15DT4) (C1MSL15DT5) 13-68 H'0080 15FC CAN1 Message Slot 15 Data 6 CAN1 Message Slot 15 Data 7 13-69 (C1MSL15DT6) (C1MSL15DT7) 13-70 H'0080 15FE CAN1 Message Slot 15 Timestamp 13-71 (C1MSL15TSP)

32180 Group User’s Manual (Rev.1.0) The EIT vector entry is located at the beginning of the internal ROM/extended external areas. The branch instruc- tion for jumping to the start address of each EIT event processing handler is written here. Note that it is the branch instruction and not the jump address itself that is written here. For details, see Chapter 4, “EIT.” H'0000 0040 H'0000 0044 H'0000 0048 H'0000 004C H'0000 0050 H'0000 0054 H'0000 0058 H'0000 005C H'0000 0060 H'0000 0064 H'0000 0068 H'0000 006C H'0000 0070 H'0000 0074 H'0000 0078 H'0000 007C H'0000 0080 H'0000 0090 H'0000 0030 H'0000 0020 H'0000 0010 H'0000 0000 H'0000 0034 H'0000 0038 H'0000 003C H'0000 0024 H'0000 0028 H'0000 002C H'0000 0004 H'0000 0008 H'0000 000C H'0000 0014 H'0000 0018 H'0000 001C TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 AE (Address Exception) EI (External Interrupt) (Note 1) RI (Reset Interrupt) SBI (System Break Interrupt) RIE (Reserved Instruction Exception) FPE (Floating-Point Exception) 0 31 Note 1: When flash entry bit = 1 (flash E/W enable mode), the EI vector entry is located at H'0080 4000. Figure 3.5.1 EIT Vector Entry

32180 Group User’s Manual (Rev.1.0) The ICU vector table is used by the internal interrupt controller of the microcomputer. This table has the addresses shown below, at which the start addresses of interrupt handlers for the interrupt requests from respective internal peripheral I/Os are set. For details, see Chapter 5, “Interrupt Controller.” ICU Vector Table Memory Map (1/2) Address +0 address +1 address b0 b7 b8 b15 H'0000 0094 TIN3 –6 Input Interrupt Handler Start Address (A0–A15) H'0000 0096 TIN3 –6 Input Interrupt Handler Start Address (A16–A31) H'0000 0098 TIN20 –29 Input Interrupt Handler Start Address (A0–A15) H'0000 009A TIN20 –29 Input Interrupt Handler Start Address (A16–A31) H'0000 009C TIN12 –19 Input Interrupt Handler Start Address (A0–A15) H'0000 009E TIN12 –19 Input Interrupt Handler Start Address (A16–A31) H'0000 00A0 TIN0 –2 Input Interrupt Handler Start Address (A0–A15) H'0000 00A2 TIN0 –2 Input Interrupt Handler Start Address (A16–A31) H'0000 00A4 TIN7 –11 Input Interrupt Handler Start Address (A0–A15) H'0000 00A6 TIN7 –11 Input Interrupt Handler Start Address (A16–A31) H'0000 00A8 TMS0, 1 Output Interrupt Handler Start Address (A0 –A15) H'0000 00AA TMS0, 1 Output Interrupt Handler Start Address (A16 –A31) H'0000 00AC TOP8, 9 Output Interrupt Handler Start Address (A0 –A15) H'0000 00AE TOP8, 9 Output Interrupt Handler Start Address (A16 –A31) H'0000 00B0 TOP10 Output Interrupt Handler Start Address (A0 –A15) H'0000 00B2 TOP10 Output Interrupt Handler Start Address (A16 –A31) H'0000 00B4 TIO4 –7 Output Interrupt Handler Start Address (A0–A15) H'0000 00B6 TIO4 –7 Output Interrupt Handler Start Address (A16–A31) H'0000 00B8 TIO8, 9 Output Interrupt Handler Start Address (A0 –A15) H'0000 00BA TIO8, 9 Output Interrupt Handler Start Address (A16 –A31) H'0000 00BC TOP0 –5 Output Interrupt Handler Start Address (A0–A15) H'0000 00BE TOP0 –5 Output Interrupt Handler Start Address (A16–A31) H'0000 00C0 TOP6, 7 Output Interrupt Handler Start Address (A0 –A15) H'0000 00C2 TOP6, 7 Output Interrupt Handler Start Address (A16 –A31) H'0000 00C4 TIO0 –3 Output Interrupt Handler Start Address (A0–A15) H'0000 00C6 TIO0 –3 Output Interrupt Handler Start Address (A16–A31) H'0000 00C8 DMA0 –4 Interrupt Handler Start Address (A0–A15) H'0000 00CA DMA0 –4 Interrupt Handler Start Address (A16–A31) H'0000 00CC SIO1 Receive Interrupt Handler Start Address (A0 –A15) H'0000 00CE SIO1 Receive Interrupt Handler Start Address (A16 –A31) H'0000 00D0 SIO1 Transmit Interrupt Handler Start Address (A0 –A15) H'0000 00D2 SIO1 Transmit Interrupt Handler Start Address (A16 –A31) H'0000 00D4 SIO0 Receive Interrupt Handler Start Address (A0 –A15) H'0000 00D6 SIO0 Receive Interrupt Handler Start Address (A16 –A31)

32180 Group User’s Manual (Rev.1.0) ICU Vector Table Memory Map (2/2) Address +0 address +1 address b0 b7 b8 b15 H'0000 00D8 SIO0 Transmit Interrupt Handler Start Address (A0 –A15) H'0000 00DA SIO0 Transmit Interrupt Handler Start Address (A16 –A31) H'0000 00DC A-D0 Conversion Interrupt Handler Start Address (A0 –A15) H'0000 00DE A-D0 Conversion Interrupt Handler Start Address (A16 –A31) H'0000 00E0 TID0 Input Interrupt Handler Start Address (A0 –A15) H'0000 00E2 TID0 Input Interrupt Handler Start Address (A16 –A31) H'0000 00E4 TOU0 Output Interrupt Handler Start Address (A0 –A15) H'0000 00E6 TOU0 Output Interrupt Handler Start Address (A16 –A31) H'0000 00E8 DMA5 –9 Interrupt Handler Start Address (A0–A15) H'0000 00EA DMA5 –9 Interrupt Handler Start Address (A16–A31) H'0000 00EC SIO2, 3 Transmit/receive Interrupt Handler Start Address (A0 –A15) H'0000 00EE SIO2, 3 Transmit/receive Interrupt Handler Start Address (A16 –A31) H'0000 00F0 RTD Interrupt Handler Start Address (A0 –A15) H'0000 00F2 RTD Interrupt Handler Start Address (A16 –A31) H'0000 00F4 TID1 Input Interrupt Handler Start Address (A0 –A15) H'0000 00F6 TID1 Input Interrupt Handler Start Address (A16 –A31) H'0000 00F8 TOU1 + TOU2 Output Interrupt Handler Start Address (A0 –A15) H'0000 00FA TOU1 + TOU2 Output Interrupt Handler Start Address (A16 –A31) H'0000 00FC SIO4, 5 Transmit/receive Interrupt Handler Start Address (A0 –A15) H'0000 00FE SIO4, 5 Transmit/receive Interrupt Handler Start Address (A16 –A31) H'0000 0100 A-D1 Conversion Interrupt Handler Start Address (A0 –A15) H'0000 0102 A-D1 Conversion Interrupt Handler Start Address (A16 –A31) H'0000 0104 TID2 Input Interrupt Handler Start Address (A0 –A15) H'0000 0106 TID2 Input Interrupt Handler Start Address (A16 –A31) H'0000 0108 TIN30 –33 Input Interrupt Handler Start Address (A0–A15) H'0000 010A TIN30 –33 Input Interrupt Handler Start Address (A16–A31) H'0000 010C CAN0 Transmit/receive & Error Interrupt Handler Start Address (A0 –A15) H'0000 010E CAN0 Transmit/receive & Error Interrupt Handler Start Address (A16 –A31) H'0000 0110 CAN1 Transmit/receive & Error Interrupt Handler Start Address (A0 –A15) H'0000 0112 CAN1 Transmit/receive & Error Interrupt Handler Start Address (A16 –A31)

32180 Group User’s Manual (Rev.1.0)

3.7 Notes about Address Space

• Virtual flash emulation function The microcomputer has the function to map 4-Kbyte memory blocks beginning with the address H’0080 8000 into areas (S banks) of the internal flash memory that are divided in 4-Kbyte units. This functions is referred to as the virtual flash emulation function. This function allows the data located in 4-Kbyte blocks of the internal RAM to be changed with the flash memory contents at the addresses specified by the Virtual Flash Bank Register. For details about this function, see Section 6.6, “Virtual Flash Emulation Function.”

4.1 Outline of EIT

4.2 EIT Events

4.3 EIT Processing Procedure

4.4 EIT Processing Mechanism

4.5 Acceptance of EIT Events

4.6 Saving and Restoring the PC and PSW

4.7 EIT Vector Entry

4.8 Exception Processing

4.9 Interrupt Processing

4.10 Trap Processing

4.11 EIT Priority Levels

4.12 Example of EIT Processing

4.13 Precautions on EIT

32180 Group User’s Manual (Rev.1.0) If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. Events like this one are referred to by a generic name as EIT (Exception, Interrupt and Trap). (1) Exception This is an event related to the context being executed. It is generated by an error or violation during instruction execution. This type of event includes Address Exception (AE), Reserved Instruction Exception (RIE) and Floating- Point Exception (FPE). (2) Interrupt This is an event generated irrespective of the context being executed. It is generated by a hardware-derived signal from an external source, as well as by the internal peripheral I/O. This type of event includes Reset Interrupt (RI), System Break Interrupt (SBI) and External Interrupt (EI). (3) Trap This refers to a software interrupt generated by executing a TRAP instruction. This type of event is intentionally generated in a program as in the OS’s system call by the programmer. Figure 4.1.1 Classification of EITs EIT Exception (Exception) Reserved Instruction Exception (RIE) Address Exception (AE) Floating-Point Exception (FPE) Reset Interrupt (RI) System Break Interrupt (SBI) External Interrupt (EI) Trap (TRAP) Interrupt (Interrupt) Trap (Trap)

32180 Group User’s Manual (Rev.1.0)

4.2.1 Exception

(1) Reserved Instruction Exception (RIE) Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (unimplemented instruction) is detected. (2) Address Exception (AE) Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions. (3) Floating-point Exception (FPE) Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions specified in the IEEE 754 standard (OVF/UDF/IXCT/DIV0/IVLD) is detected. Each exception processing is outlined below. 1) Overflow Exception (OVF) The exception occurs when the absolute value of the operation result exceeds the largest describable precision in the floating-point format. The following table shows the operation results when an OVF oc- curs. Table 4.2.1 Operation Results When an OVF Occurred Operation Result (Content of the Destination Register) When the OVF EIT processing is masked (Note 1) When the OVF EIT processing is executed (Note 2) + + M A X - - I n f i n i t y + +Infinity - - M A X + + M A X - - M A X + +Infinity - - I n f i n i t y No change Sign of the Result -Infinity +Infinity Rounding Mode Nearest /i0 /i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 Note 1: When the overflow exception enable (EO) bit (FPSR register bit 20) = "0" Note 2: When the overflow exception enable (EO) bit (FPSR register bit 20) = "1" Note:  If an OVF occurs while EIT processing for OVF is masked, an IXCT occurs at the same time.  +MAX = H’7F7F FFFF, –MAX = H’FF7F FFFF 2) Underflow Exception (UDF) The exception occurs when the absolute value of the operation result is less than the largest describable precision in the floating-point format. The following table shows the operation results when a UDF occurs. Table 4.2.2 Operation Results when a UDF Occurred Operation Result (Content of the Destination Register) When UDF EIT processing is masked (Note 1) When UDF EIT processing is executed (Note 2) DN = 0: An unimplemented exception occurs DN = 1: 0 is returned No change /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0 /i0 /i0 /i0 /i0 Note 1: When the underflow exception enable (EU) bit (FPSR register bit 18) = "0" Note 2: When the underflow exception enable (EU) bit (FPSR register bit 18) = "1"

32180 Group User’s Manual (Rev.1.0) Operation Result (Content of the Destination Register) When the DIV0 EIT processing is masked (Note 1) When the DIV0 EIT processing is executed (Note 2) Nonzero finite value +-Infinity (Sign is derived by exclusive ORing the signs of the divisor and dividend.) No change Dividend /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0/i0/i0 /i0/i0 /i0/i0 Dividend Behavior

0 An invalid operation exception occurs

Infinity No exceptions occur (with the result = "Infinity") /i0 /i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0 /i0 /i0 Note 1: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "0" Note 2: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "1" Please note that the DIV0 EIT processing does not occur in the following conditions. Table 4.2.5 Cases in Which No DIV0 Occur 3) Inexact Exception (IXCT) The exception occurs when the operation result differs from a result led out with an infinite range of precision. The following table shows the operation results and the respective conditions in which each IXCT occurs. Table 4.2.3 Operation Results when an IXCT Occurred Note 1: When the inexact exception enable (EX) bit (FPSR register bit 17) = "0" Note 2: When the inexact exception enable (EX) bit (FPSR register bit 17) = "1" 4) Zero Division Exception (DIV0) The exception occurs when a finite nonzero value is divided by zero. The following table shows the operation results when a DIV0 is occurs. Table 4.2.4 Operation Results When a DIV0 Occurred Operation Result (Content of the Destination Register) When the IXCT EIT processing for is masked (Note 1) When the IXCT EIT processing is executed (Note 2) Overflow occurs in OVF masked condition Reference OVF operation results No change Rounding occurs Rounded value No change Occurrence Condition /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0 /i0 /i0 /i0 /i0 /i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0 /i0 /i0 /i0 /i0/i0 /i0/i0 /i0/i0 /i0/i0

32180 Group User’s Manual (Rev.1.0) 5) Invalid Operation Exception (IVLD) The exception occurs when an invalid operation is executed. The following table shows the operation results and the respective conditions in which each IVLD occurs. Table 4.2.6 Operation Results When an IVLD Occurred Note 1: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "0" Note 2: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "1" Note:  NaN (Not a Number) SNaN (Signaling NaN): a NaN in which the MSB of the decimal fraction is "0". When SNaN is used as the source operand in an operation, an IVLD occurs. SNaNs are useful in identifying program bugs when used as the initial value in a variable. However, SNaNs cannot be generated by hardware. QNaN (Quiet NaN): a NaN in which the MSB of the decimal fraction is "1". Even when QNaN is used as the source operand in an operation, an IVLD will not occur (excluding comparison and format conversion). Because a result can be checked by the arithmetic operations, QNaN allows the user to debug without executing an EIT processing. QNaNs are created by hardware. 6) Unimplemented Exception (UIPL) The exception occurs when the denormalized number zero flush (DN) bit (FPSR register bit 23) = "0" and a denormalized number is given as an operation operand. (Note 1) Because the UIPL has no enable bits available, it cannot be masked when they occur. The destination register remains unchanged. Note 1: A UDF occurs when the intermediate result of an operation is a denormalized number, in which case if the DN bit (FPSR register bit 23) = "0", an UIPL occurs.

4.2.2 Interrupt

(1) Reset Interrupt (RI) Reset Interrupt (RI) is always accepted by entering the RESET# signal. The reset interrupt is assigned the highest priority. For details about the reset interrupt, see Chapter 7, “Reset.” (2) System Break Interrupt (SBI) System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. This interrupt can only be used in cases when after interrupt processing, control will not return to the program that was being executed when the interrupt occurred. (3) External Interrupt (EI) External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt controller. The interrupt controller manages these interrupts by assigning each one of eight priority levels including an interrupt-disabled state. Operation Result (Content of the Destination Register) When the IVLD EIT processing is masked (Note 1) When the IVLD EIT processing is executed (Note 2) When an integer conversion overflowed When FTOI instruction was executed Return value when pre-conversion signed bit is: "0": H7FFF FFFF "1": H 8000 0000 When NaN or Infinity was converted into an integer When FTOS instruction was executed Return value when pre-conversion signed bit is: "0": H 0000 7FFF "1": H FFFF 8000 Comparison results (comparison invalid) QNaN No change Occurrence Condition Operation for SNaN operand +Infinity-(+Infinity), -Infinity-(-Infinity) 0 x Infinity 0 / 0, Infinity / Infinity When < or > comparison was performed on NaN /i0 /i0 /i0 /i0 /i0 /i0 /i0/i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0 /i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0/i0

32180 Group User’s Manual (Rev.1.0)

4.2.3 Trap

Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector addresses are provided corresponding to TRAP instruction operands 0–15. EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except for a rest interrupt, is shown below. Figure 4.3.1 Outline of the EIT Processing Procedure When an EIT is accepted, the CPU branches to the EIT vector after hardware preprocessing (as will be described later). The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction for the EIT handler (not the jump address itself) is written. In the hardware preprocessing, the PC is transferred to the BPC (backup PC), and the content of the PSW register’s PSW field is transferred to the BPSW field in that register. Other necessary operations must be performed in the user-created EIT handler. These include saving the BPC and PSW registers (including the BPSW field) and the general-purpose registers to be used in the EIT handler to the stack. In addition, the accumulator and the FPSR register must be saved to the stack as necessary. Remember that all these registers must be saved to the stack in a program by the user. When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute the RTE instruction. Control is thereby returned from the EIT processing to the program that was being executed when the EIT occurred. (This does not apply to the System Break Interrupt, however.) In the hardware postprocessing, the BPC is returned to the PC, and the content of the PSW register’s BPSW field is returned to the PSW field in that register. Note that the values stored in the BPC and the PSW register’s BPSW field after executing the RTE instruction are undefined. Instruction A PC →BPC PSW →BPSW EIT vector entry EIT handler except for SBI RTE instruction Program suspended and EIT request accepted Instruction processing-canceled type (RIE, AE) Instruction processing-completed type (FPE, EI, TRAP) Program execution restarted EIT request generated Hardware preprocessing BPC, PSW, FPSR and general-purpose registers are saved to the stack Branch instruction General-purpose registers, PSW, FPSR and BPC are restored from the stack Hardware postprocessing (SBI) Program terminated or system is reset User-created EIT handler BPSW →PSW BPC →PC Processing by handler Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields. (Note 1) (Note 1) SBI (System Break Interrupt processing) Instruction B Instruction C Instruction C Instruction D

32180 Group User’s Manual (Rev.1.0) The EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/ Os. It also has the backup registers for the PC and PSW (the BPC register and the BPSW field of the PSW register). The EIT processing mechanism is shown below. Figure 4.4.1 EIT Processing Mechanism Interrupt controller (ICU) SBI EIInternal peripheral I/Os RESET# RI AE, RIE, FPE, TRAP IE flag (PSW) M32R CPU core SBI# Low High Priority SBI EI RI M32R/ECU PSW register PSWBPSW BPC register PC register

32180 Group User’s Manual (Rev.1.0) When an EIT event occurs, the CPU suspends the program it has hitherto been executing and branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are accepted are shown below. Table 4.5.1 Acceptance of EIT Events EIT Event Type of Processing Acceptance Timing Values Set in BPC Register Reserved Instruction Instruction processing- During instruction execution PC value of the instruction that Exception (RIE) canceled type generated RIE Address Exception (AE) Instruction processing- During instruction execution PC value of the instruction that canceled type generated AE Floating-Point Exception Instruction processing- Break in instructions PC value of the instruction that (FPE) completed type generated FPE + 4 Reset Interrupt (RI) Instruction processing- Each machine cycle Undefined value aborted type System Break Interrupt Instruction processing- Break in instructions PC value of the next instruction (SBI) completed type (word boundary only) External Interrupt (EI) Instruction processing- Break in instructions PC value of the next instruction completed type (word boundary only) Trap (TRAP) Instruction processing- Break in instructions PC value of TRAP instruction + 4 completed type The following describes operation of the microcomputer at the time when it accepts an EIT and when it executes the RTE instruction. (1) Hardware preprocessing when an EIT is accepted [1] Save the PSW register’s SM, IE and C bits in its backup field. BSM ← SM BIE ← IE BC ← C [2] Update the PSW register’s SM, IE and C bits SM ← Remains unchanged (RIE, AE, FPE, TRAP) or cleared to "0" (SBI, EI, RI) IE ← Cleared to "0" C ← Cleared to "0" [3] Save the PC register BPC ← PC [4] Set the vector address in the PC register Branches to the EIT vector and executes the branch (BRA) instruction written in it, thereby transferring control to the user-created EIT handler. (2) Hardware postprocessing when the RTE instruction is executed [A] Restore the PSW register’s SM, IE and C bits from its backup field. SM ← BSM IE ← BIE C ← BC [B] Restore the PC register from the BPC register. PC ← BPC Note:  The values stored in the BPC and the PSW register’s BSM, BIE and BC bits after executing the RTE instruction are undefined.

32180 Group User’s Manual (Rev.1.0) [1] Saving the SM, IE and C bits BSM BIE BC SM IE C [2] Updating the SM, IE and C bits SM IE C Unchanged or 0 [3] Saving the PC BPC PC← [4] Setting the vector address in the PC PC Vector address← [B] Restoring the PC from the BPC register The value stored in the BPC register after executing the RTE instruction is undefined. [A] Restoring the SM, IE and C bits from the backup field SM IE C The values stored in the BSM, BIE and BC bits after executing the RTE instruction are undefined. BSM BIE BC [1] [A] [B] [2] [3] [4] Figure 4.6.1 Saving and Restoring the PC and PSW 16 17 23 24 25 31(LSB)15870(MSB) SM IE CBCBSM BIE 00000000000000000000000000PSW BPSW field PSW field

32180 Group User’s Manual (Rev.1.0) The EIT vector entry is located in the user space beginning with the address H’0000 0000. The table below lists the EIT vector entry. Table 4.7.1 EIT Vector Entry Name Abbreviation Vector Address SM IE BPC Reset Interrupt RI H'0000 0000 (Note 1) 0 0 Undefined System Break SBI H'0000 0010 0 0 PC of the next instruction Interrupt Reserved Instruction RIE H'0000 0020 Unchanged 0 PC of the inst ruction that generated RIE Exception Address Exception AE H'0000 0030 Unchanged 0 PC of the inst ruction that generated RIE Trap TRAP0 H'0000 0040 Unchanged 0 PC of TRAP instruction + 4 TRAP1 H'0000 0044 Unchanged 0 PC of TRAP instruction + 4 TRAP2 H'0000 0048 Unchanged 0 PC of TRAP instruction + 4 TRAP3 H'0000 004C Unchanged 0 PC of TRAP instruction + 4 TRAP4 H'0000 0050 Unchanged 0 PC of TRAP instruction + 4 TRAP5 H'0000 0054 Unchanged 0 PC of TRAP instruction + 4 TRAP6 H'0000 0058 Unchanged 0 PC of TRAP instruction + 4 TRAP7 H'0000 005C Unchanged 0 PC of TRAP instruction + 4 TRAP8 H'0000 0060 Unchanged 0 PC of TRAP instruction + 4 TRAP9 H'0000 0064 Unchanged 0 PC of TRAP instruction + 4 TRAP10 H'0000 0068 Unchanged 0 PC of TRAP instruction + 4 TRAP11 H'0000 006C Unchanged 0 PC of TRAP instruction + 4 TRAP12 H'0000 0070 Unchanged 0 PC of TRAP instruction + 4 TRAP13 H'0000 0074 Unchanged 0 PC of TRAP instruction + 4 TRAP14 H'0000 0078 Unchanged 0 PC of TRAP instruction + 4 TRAP15 H'0000 007C Unchanged 0 PC of TRAP instruction + 4 External Interrupt EI H'0000 0080 (Note 2) 0 0 PC of the next instruction Floating-Point Exception FPE H'0000 0090 Unchanged 0 PC of the instruction that generated FPE + 4 Note 1: During boot mode, the CPU starts executing the boot program after reset. For details, see Section 6.5, “Programming the Internal Flash Memory.” Note 2: During flash E/W enable mode, this vector address is moved to the beginning of the internal RAM (address H’0080 4000). For details, see Section 6.5, “Programming the Internal Flash Memory.”

32180 Group User’s Manual (Rev.1.0)

4.8.1 Reserved Instruction Exception (RIE)

[Occurrence Conditions] Reserved Instruction Exception (RIE) occurs when a reserved instruction (unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a reserved instruction exception occurs, the instruction that generated it is not executed. If an exter- nal interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved instruction exception that is accepted. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC The PC value of the instruction that generated the reserved instruction exception is set in the BPC register. For example, if the instruction that generated the reserved instruction exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction that generated the reserved instruction exception is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.) Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE) H'00 Address RIE occurredH'04 H'08 H'0C +0 +1 +2 +3 H'00 Address RIE occurredH'04 H'08 H'0C +0 +1 +2 +3 Return address BPC H'06BPC H'04 Return address

32180 Group User’s Manual (Rev.1.0) (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0020 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0020 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from a word-boundary instruction including the instruction that generated a RIE (see Figure 4.8.1). Except when using reserved instruction exceptions intentionally, occurrence of a reserved instruc- tion exception suggests that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the reserved instruction exception handler to the program that was being executed when the exception occurred.

4.8.2 Address Exception (AE)

[Occurrence Conditions] Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions. The following lists the combination of instructions and accessed addresses that may cause address exceptions to occur.  Two low-order address bits accessed in the LDH, LDUH or STH instruction are ‘01’ or ‘11’  Two low-order address bits accessed in the LD, ST, LOCK or UNLOCK instruction are ‘01,’ ‘10’ or ‘11’ When an address exception occurs, memory access by the instruction that generated the exception is not performed. If an external interrupt is requested at the same time an address exception is detected, it is the address exception that is accepted. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC The PC value of the instruction that generated the address exception is set in the BPC register. For ex- ample, if the instruction that generated the address exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction that generated the address exception is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.)

32180 Group User’s Manual (Rev.1.0) Figure 4.8.2 Example of a Return Address for Address Exception (AE) (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0030 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0030 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from a word-boundary instruction including the instruction that generated an AE (see Figure 4.8.2). Except when using address exceptions intentionally, occurrence of an address exception suggests that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the address exception handler to the program that was being executed when the exception occurred.

4.8.3 Floating-Point Exception (FPE)

[Occurrence Conditions] Floating-Point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions specified in IEEE 754 standards (OVF, UDF, IXCT, DIV0 or IVLD) is detected. Note, however, that the EIT processing described below is executed only when the exception that occurred is one whose exception enable bit in the FPSR register is set to "1" or an unimplemented exception. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 H'00 Address AE occurredH'04 H'08 H'0C +0 +1 +2 +3 H'00 Address AE occurredH'04 H'08 H'0C +0 +1 +2 +3 BPC H'06BPC H'04 Return address Return address

32180 Group User’s Manual (Rev.1.0) (3) Saving the PC The PC value of the instruction that generated the FPE exception + 4 is set in the BPC register. Because all of the instructions that generate an FPE exception are 32 bits long, the address to which the RTE returns is always the instruction next to the one that generated the FPE exception. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0090 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0090 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC, PSW and FPSR registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed.

32180 Group User’s Manual (Rev.1.0)

4.9.1 Reset Interrupt (RI)

[Occurrence Conditions] A reset interrupt is unconditionally accepted in any machine cycle by pulling the RESET# input signal low. The reset interrupt is assigned the highest priority among all EITs. [EIT Processing] (1) Initializing SM, IE and C bits The PSW register’s SM, IE and C bits are initialized as shown below. SM ← 0 IE ← 0 C ← 0 For the reset interrupt, the values of SM, IE and C bits are undefined. (2) Branching to the EIT vector entry The CPU branches to the address H’0000 0000 in the user space. However, when operating in boot mode, the CPU jumps to the boot program. For details, see Section 6.5, “Programming the Internal Flash Memory.” (3) Jumping from the EIT vector entry to the user program The CPU executes the instruction written by the user at the address H’0000 0000 of the EIT vector entry. In the reset vector entry, be sure to initialize the PSW and SPI registers before jumping to the start address of the user program.

4.9.2 System Break Interrupt (SBI)

System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt cannot be masked by the PSW register IE bit. Therefore, the system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred. [Occurrence Conditions] A system break interrupt is accepted by a falling edge on SBI# input pin. (The system break interrupt cannot be masked by the PSW register IE bit.) In no case will a system break interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately after branching.) Note also that because of the instruction processing-completed type, a system break interrupt is accepted after the instruction is completed.

32180 Group User’s Manual (Rev.1.0) Order in which instructions are executed 32-bit instruction Address 1000 Address 1002 Address 1004 Address 1000 Interrupt may be accepted Interrupt cannot be accepted 16-bit instruction Interrupt may be accepted Interrupt may be accepted Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving the PC The address of the next instruction (always on word boundary) following one in which the interrupt was detected is stored in the BPC register. If the interrupt was detected in a branch instruction, then the next instruction is one that exists at the jump address. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0010 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0010 of the EIT vector entry to jump to the start address of the user-created handler. The system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred.

32180 Group User’s Manual (Rev.1.0) Figure 4.9.2 Timing at Which External Interrupt (EI) is Accepted [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving the PC The content of the PC register (always on word boundary) is saved to the BPC register. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0080 in the user space. However, when operating in flash E/W enable mode, the CPU goes to the beginning of the internal RAM (address H’0080 4000). (For details, see Section 6.5, “Programming the Internal Flash Memory.”) This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0080 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary.

4.9.3 External Interrupt (EI)

An external interrupt is generated upon an interrupt request which is output by the microcomputer’s internal interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority levels. For details, see Chapter 5, “Interrupt Controller.” For details about the interrupt request sources, see each section in which the relevant internal peripheral I/O is described. [Occurrence Conditions] External interrupts are managed based on interrupt requests from each internal peripheral I/O by the microcomputer’s internal interrupt controller, and are sent to the CPU via the interrupt controller. The CPU checks these interrupt requests at a break in instructions residing on word boundaries, and when an interrupt request is detected and the PSW register IE flag = "1", accepts it as an external interrupt. In no case will an external interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately after branching.) Order in which instructions are executed 32-bit instruction Address 1000 Address 1002 Address 1004 Address 1008 Interrupt may be accepted Interrupt cannot be accepted 16-bit instruction Interrupt may be accepted Interrupt may be accepted

32180 Group User’s Manual (Rev.1.0) (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed.

4.10.1 Trap

[Occurrence Conditions] Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen traps are generated, each corresponding to one of TRAP instruction operands 0–15. Accordingly, sixteen vector entries are provided. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC When the trap instruction is executed, the PC value of TRAP instruction + 4 is set in the BPC register. For example, if the TRAP instruction is located at address 4, the value H’08 is set in the BPC register. Similarly, if the TRAP instruction is located at address 6, the value H’0A is set in the BPC register. The value of the BPC register bit 30 indicates whether the trap instruction resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 8. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.) Figure 4.10.1 Example of a Return Address for Trap (TRAP) H'00 Address H'04 H'08 H'0C +0 +1 +2 +3 H'00 Address H'04 H'08 H'0C +0 +1 +2 +3 BPC H'0ABPC H'08 TRAP instruction Return address Return address TRAP instruction

32180 Group User’s Manual (Rev.1.0) (4) Branching to the EIT vector entry The CPU branches to the addresses H’0000 0040–H ’0000 007C in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the addresses H’0000 0040–H ’0000 007C of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user- created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from the next word-boundary instruction including the instruction that generates a trap (see Figure 4.10.1). The table below lists the priority levels of EIT events. When two or more EITs occur simultaneously, the event with the highest priority is accepted first. Table 4.11.1 Priority of EIT Events and How Returned from EIT Priority EIT Event Type of Processing Values Set in BPC Register 1 (Highest) Reset Interrupt (RI) Instruction processing-aborted type Undefined

2 Address Exception (AE) Instruction processing-canceled type PC of the instruction that

Reserved Instruction Instruction processing-canceled type PC of the instruction that Exception (RIE) generated AE Floating-Point Exception Instruction processing-completed type PC of the instruction that (FPE) generated FPE + 4 Trap (TRAP) Instruction processing-completed type TRAP instruction + 4

3 System Break Interrupt Instruction processing-completed type PC of the next instruction

(SBI)

4 External Interrupt (EI) Instruction processing-completed type PC of the next instruction

Note that for External Interrupt (EI), the priority levels of interrupt requests from each peripheral I/O are set by the microcomputer’s internal interrupt controller. For details, see Chapter 5, “Interrupt Controller.”

32180 Group User’s Manual (Rev.1.0) (1) When RIE, AE, FPE, SBI, EI or TRAP occurs singly Figure 4.12.1 Processing of Events When RIE, AE, FPE, SBI, EI or TRAP Occurs Singly (2) When RIE, AE, FPE or TRAP and EI occur simultaneously Figure 4.12.2 Processing of Events When RIE, AE, FPE or TRAP and EI Occur Simultaneously RTE instruction IE = 0 RIE, AE, FPE or TRAP is accepted first. BPC register = Return address AIE = 1 RIE, AE, FPE or TRAP and EI occur simultaneously Return address A: IE = 1 IE = 0 IE = 1 RTE instruction : EIT handler EI is accepted next. BPC register = Return address A RTE instruction IE = 0 IE = 1 BPC register = Return address A IE = 1 RIE, AE, FPE, SBI, EI or TRAP occurs singly Return address A: If IE = 0, no events but reset and SBI are accepted. : EIT handler

32180 Group User’s Manual (Rev.1.0) Figure 4.12.3 Example of EIT Processing BRA instruction RTE EIT handler EIT vector entry Program being executed Save BPC to the stack Save PSW to the stack Save general-purpose registers to the stack Processing by EIT handler Restore general-purpose registers from the stack Restore PSW from the stack Restore BPC from the stack EIT event occurs (SBI) System Break Interrupt (SBI) processing Program terminated or system reset (Other than SBI) PC →BPC PSW →BPSWHardware preprocessing Hardware postprocessingBPSW →PSW BPC →PC (Note 1) (Note 1) Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields.

32180 Group User’s Manual (Rev.1.0) The Address Exception (AE) requires caution because if one of the instructions that use “register indirect + register update” addressing mode (following three) generates an address exception when it is executed, the values of the registers to be automatically updated (Rsrc and Rsrc2) become undefined. Except that the values of Rsrc and Rsrc2 become undefined, these instructions behave the same way as when used in other addressing modes.  Applicable instructions LD Rdest, @Rsrc+ ST Rsrc1, @-Rsrc2 ST Rsrc1, @+Rsrc2 If the above case applies, consider the fact that the register values become undefined when you design the processing to be performed after executing said instructions. (If an address exception occurs, it means that the system has some fatal fault already existing in it. Therefore, address exceptions must be used on condition that control will not be returned from the address exception handler to the program that was being executed when the exception occurred.)

INTERRUPT CONTROLLER (ICU)

5.1 Outline of the Interrupt Controller

5.2 ICU Related Registers

5.3 Interrupt Request Sources in Internal

5.4 ICU Vector Table

5.5 Description of Interrupt Operation

5.6 Description of System Break Interrupt (SBI)

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0) The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are sent to the M32R CPU as external interrupts (EI). The maskable interrupts from internal peripheral I/Os are managed by assigning them one of eight priority levels including an interrupt-disabled state. If two or more interrupt requests with the same priority level occur at the same time, their priorities are resolved by predetermined hardware priority. The source of an interrupt request generated in internal peripheral I/Os is identified by reading the relevant interrupt status register provided for internal peripheral I/Os. On the other hand, the system break interrupt (SBI) is recognized when a low-going transition occurs on the SBI# signal input pin. This interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer, so that it is always accepted irrespective of the PSW register IE bit status. When the CPU has finished servicing an SBI, shut down or reset the system without returning to the program that was being executed when the interrupt occurred. Specifications of the Interrupt Controller are outlined below. Table 5.1.1 Outline of the Interrupt Controller (ICU) Item Specification Interrupt request source Maskable interrupt requests from internal peripheral I/Os: 32 sources (Note 1) System break interrupt request: 1 source (entered from SBI# pin) Priority management 8 priority levels including an interrupt-disabled state (However, interrupts with the same priority level have their priorities resolved by fixed hardware priority.) Note 1: There are actually a total of 179 interrupt request resources when counted individually, which are grouped into 32 interrupt request resources.

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0) Interrupt Vector Register (IVECT) Interrupt Request Mask Register (IMASK) NEW_IMASK External Interrupt (EI) request generated (maskable) IMASK compari- son ILEVEL System Break Interrupt (SBI) request generated (nonmaskable) SBI# EI SBI Interrupt Controller Interrupt Control Register SBI Control Register (SBICR) SBIREQ IREQ IREQ IREQ IREQ IREQ IREQ Peripheral circuits Edge Interrupt control circuit Edge Edge Level Interrupt request Interrupt request Interrupt request Level Level To the CPU core To the CPU core Interrupt control circuit Interrupt control circuit Priority resolved by interrupt priority levels set Priority resolved by fixed hardware priority Figure 5.1.1 Block Diagram of the Interrupt Controller

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0) The diagram below shows a register map associated with the Interrupt Controller (ICU). ICU Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0000 Interrupt Vector Register 5-5 (IVECT) H'0080 0002 (Use inhibited area) H'0080 0004 Interrupt Request Mask Register (Use inhibited area) 5-6 (IMASK) H'0080 0006 SBI Control Register (Use inhibited area) 5-7 (SBICR) (Use inhibited area) H'0080 0060 CAN0 Transmit/Receive & Error Interrupt Control RegisterTIN30–33 Input Interrupt Control Register 5-8 (ICAN0CR) (ITIN3033CR) H'0080 0062 TID2 Output Interrupt Control Register A-D1 Conversion Interrupt Control Register 5-8 (ITID2CR) (IAD1CCR) H'0080 0064 SIO4,5 Transmit/Receive Interrupt Control Register TOU1,2 Output Interrupt Control Register 5-8 (ISIO45CR) (ITOU12CR) H'0080 0066 TID1 Output Interrupt Control Register RTD Interrupt Control Register 5-8 (ITID1CR) (IRTDCR) H'0080 0068 SIO2,3 Transmit/Receive Interrupt Control Register DMA5 –9 Interrupt Control Register 5-8 (ISIO23CR) (IDMA59CR) H'0080 006A TOU0 Output Interrupt Control Register TID0 Output Interrupt Control Register 5-8 (ITOU0CR) (ITID0CR) H'0080 006C A-D0 Conversion Interrupt Control Register SIO0 Transmit Interrupt Control Register 5-8 (IAD0CCR) (ISIO0TXCR) H'0080 006E SIO0 Receive Interrupt Control Register SIO1 Transmit Interrupt Control Register 5-8 (ISIO0RXCR) (ISIO1TXCR) H'0080 0070 SIO1 Receive Interrupt Control Register DMA0 –4 Interrupt Control Register 5-8 (ISIO1RXCR) (IDMA04CR) H'0080 0072 TIO0 –3 Output Interrupt Control Register TOP6,7 Output Interrupt Control Register 5-8 (ITIO03CR) (ITOP67CR) H'0080 0074 TOP0 –5 Output Interrupt Control Register TOP8,9 Output Interrupt Control Register 5-8 (ITOP05CR) (ITOP89CR) H'0080 0076 TIO4 –7 Output Interrupt Control Register TOP10 Output Interrupt Control Register 5-8 (ITIO47CR) (ITOP10CR) H'0080 0078 TOP8,9 Output Interrupt Control Register TMS0,1 Output Interrupt Control Register 5-8 (ITOP89CR) (ITMS01CR) H'0080 007A TIN7 –11 Input Interrupt Control Register TIN0 –2 Input Interrupt Control Register 5-8 (ITIN711CR) (ITIN02CR) H'0080 007C TIN12 –19 Input Interrupt Control Register TIN20 –29 Input Interrupt Control Register 5-8 (ITIN1219CR) (ITIN2029CR) H'0080 007E TIN3 –6 Input Interrupt Control Register CAN1 Transmit/Receive & Error Interrupt Control Register 5-8 (ITIN36CR) (ICAN1CR)

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0)

5.2.1 Interrupt Vector Register

Interrupt Vector Register (IVECT) <Address: H ’0080 0000> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 IVECT <After reset: Undefined> b Bit Name Function R W

8 IVECT W hen an interrupt request is accepted, the 16-low-order R N

16 low-order bits of ICU vector table addressbits of the ICU vector table address for the accepted interrupt request source are stored in this register. Note:  This register must always be accessed in halfwords (2 bytes). (This is a read-only register.) The Interrupt Vector Register (IVECT) is used when an interrupt request is accepted to store the 16-low-order bits of the ICU vector table address for the accepted interrupt request source. Before this function can work, the ICU vector table (addresses H’0000 0094 through H’0000 0113) must have set in it the start addresses of interrupt handlers for each internal peripheral I/O. When an interrupt request is accepted, the 16-low-order bits of the ICU vector table address for the accepted interrupt request source are stored in the IVECT register. In the EIT handler, read the content of this IVECT register using the LDH instruction to get the ICU vector table address. When the IVECT register is read, operations (1) to (4) below are automatically performed in hardware. (1) The interrupt priority level of the accepted interrupt request source (ILEVEL) is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.) (2) The interrupt request bit for the accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources). (3) The interrupt request (EI) to the CPU core is deasserted. (4) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Notes:  Do not read the Interrupt Vector Register (IVECT) in the EIT handler unless interrupts are disabled (PSW register IE bit = "0"). In the EIT handler, furthermore, read the Interrupt Request Mask Register (IMASK) first before reading the IVECT register.  To reenable interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register (IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts. (The ICU vector table readout in the EI handler processing example in Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O is an access to the internal ROM and, there- fore, does not require adding a dummy access.)

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0)

5.2.2 Interrupt Request Mask Register

Interrupt Request Mask Register (IMASK) <Address: H ’0080 0004> 123456 b 7b0 IMASK 1110 0 0 0 0 <After reset: H’07> b Bit Name Function R W 0–4 No function assigned. Fix to "0" 00 5–7 IMASK 000: Disable maskable interrupts R W Interrupt mask bit 001: Accept interrupts with priority level 0 010: Accept interrupts with priority levels 0–1 011: Accept interrupts with priority levels 0–2 100: Accept interrupts with priority levels 0–3 101: Accept interrupts with priority levels 0–4 110: Accept interrupts with priority levels 0–5 111: Accept interrupts with priority levels 0–6 The Interrupt Request Mask Register (IMASK) is used to finally determine whether or not to accept an interrupt request after comparing its priority with the priority levels (Interrupt Control Register ILEVEL bits) that have been set for each interrupt request source. When the Interrupt Vector Register (IVECT) described above is read, the interrupt priority level of the accepted interrupt request source is set in this IMASK register as a new mask value. When any value is written to the IMASK register, operations (1) to (2) below are automatically performed in hardware. (1) The interrupt request (EI) to the CPU core is deasserted. (2) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Notes:  Do not write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts are disabled (PSW register IE bit = "0").  To reenable interrupts (by setting the IE bit to "1") after writing to the Interrupt Request Mask Register (IMASK), perform a dummy access to the internal memory, etc. before reenabling inter- rupts.

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0)

5.2.3 SBI (System Break Interrupt) Control Register

SBI (System Break Interrupt) Control Register (SBICR) <Address: H ’0080 0006> 123456 b 7b0 SBIREQ 00 0 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 0–6 No function assigned. Fix to "0" 00

7 SBIREQ 0: SBI not requested R (Note 1)

SBI request bit 1: SBI requested Note 1: This bit can only be cleared (see below) The System Break Interrupt (SBI) is an interrupt request generated by a falling edge on the SBI# signal input pin. When a falling edge on the SBI# signal input pin is detected and this bit is set to "1", a system break interrupt (SBI) request is generated to the CPU. This bit cannot be set to "1" in software, it can only be cleared. To clear this bit to "0", follow the procedure described below. 1. Write "1" to the SBI request bit. 2. Write "0" to the SBI request bit. Note:  Unless this bit is set to "1", do not perform the above clearing operation.

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0)

5.2.4 Interrupt Control Registers

CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) <Address: H ’0080 0060> TIN30–33 Input Interrupt Control Register (ITIN3033CR) <Address: H ’0080 0061> TID2 Output Interrupt Control Register (ITID2CR) <Address: H ’0080 0062> A-D1 Conversion Interrupt Control Register (IAD1CCR) <Address: H ’0080 0063> SIO4,5 Transmit/Receive Interrupt Control Register (ISIO45CR) <Address: H ’0080 0064> TOU1,2 Output Interrupt Control Register (ITOU12CR) <Address: H ’0080 0065> TID1 Output Interrupt Control Register (ITID1CR) <Address: H ’0080 0066> RTD Interrupt Control Register (IRTDCR) <Address: H ’0080 0067> SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) <Address: H ’0080 0068> DMA5 –9 Interrupt Control Register (IDMA59CR) <Address: H ’0080 0069> TOU0 Output Interrupt Control Register (ITOU0CR) <Address: H ’0080 006A> TID0 Output Interrupt Control Register (ITID0CR) <Address: H ’0080 006B> A-D0 Conversion Interrupt Control Register (IAD0CCR) <Address: H ’0080 006C> SIO0 Transmit Interrupt Control Register (ISIO0TXCR) <Address: H ’0080 006D> SIO0 Receive Interrupt Control Register (ISIO0RXCR) <Address: H ’0080 006E> SIO1 Transmit Interrupt Control Register (ISIO1TXCR) <Address: H ’0080 006F> SIO1 Receive Interrupt Control Register (ISIO1RXCR) <Address: H ’0080 0070> DMA0 –4 Interrupt Control Register (IDMA04CR) <Address: H ’0080 0071> TIO0–3 Output Interrupt Control Register (ITIO03CR) <Address: H ’0080 0072> TOP6,7 Output Interrupt Control Register (ITOP67CR) <Address: H ’0080 0073> TOP0 –5 Output Interrupt Control Register (ITOP05CR) <Address: H ’0080 0074> TIO8,9 Output Interrupt Control Register (ITIO89CR) <Address: H ’0080 0075> TIO4–7 Output Interrupt Control Register (ITIO47CR) <Address: H ’0080 0076> TOP10 Output Interrupt Control Register (ITOP10CR) <Address: H ’0080 0077> TOP8,9 Output Interrupt Control Register (ITOP89CR) <Address: H ’0080 0078> TMS0,1 Output Interrupt Control Register (ITMS01CR) <Address: H ’0080 0079> TIN7–11 Input Interrupt Control Register (ITIN711CR) <Address: H ’0080 007A> TIN0–2 Input Interrupt Control Register (ITIN02CR) <Address: H ’0080 007B> TIN12–19 Input Interrupt Control Register (ITIN1219CR) <Address: H ’0080 007C> TIN20–29 Input Interrupt Control Register (ITIN2029CR) <Address: H ’0080 007D> TIN3–6 Input Interrupt Control Register (ITIN36CR) <Address: H ’0080 007E> CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR) <Address: H ’0080 007F>

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0) 9 1 01 11 21 31 4 b 1 5 )(b8 123456 b 7b0 ILEVELIREQ 0 1110 0 0 0 <After reset: H’07> b Bit Name Function R W 0–2 No function assigned. Fix to "0" 00 (8–10)

3 IREQ <When edge recognized> R W

(11) Interrupt request bit At read 0: Interrupt not requested 1: Interrupt requested At write 0: Clear interrupt request 1: Generate interrupt request <When level-recognized> R 0 At read 0: Interrupt not requested 1: Interrupt requested 4 No function assigned. Fix to "0" 00 (12) 5–7 ILEVEL 000: Interrupt priority level 0 R W (13–15) Interrupt priority level bits 001: Interrupt priority level 1 010: Interrupt priority level 2 011: Interrupt priority level 3 100: Interrupt priority level 4 101: Interrupt priority level 5 110: Interrupt priority level 6 111: Interrupt priority level 7 (interrupt disabled) (1) IREQ (Interrupt Request) bit (Bit 3 or 11) When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Re- quest) bit is set to "1". This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for level-recognized interrupt request sources). Also, when this bit is set by an edge-recognized interrupt re- quest generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not cleared in the case of level-recognized interrupt request). If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Register (IVECT) at the same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority. Note:  External Interrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External Interrupt (EI) to the CPU core can only be deasserted by the following operation: (1) Reset (2) IVECT register read (3) Write to the IMASK register

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0) Figure 5.2.1 Configuration of the Interrupt Control Register (Edge-recognized Type) Figure 5.2.2 Configuration of the Interrupt Control Register (Level-recognized Type) (2) ILEVEL (Interrupt Priority Level) (Bits 5–7 or bits 13–15) These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set these bits to ‘111’ to disable or any value ‘000’ through ‘110’ to enable the interrupt from some internal peripheral I/O. When an interrupt occurs, the Interrupt Controller resolves priority between this interrupt and other interrupt sources based on ILEVEL settings and finally compares priority with the IMASK value to determine whether to forward an EI request to the CPU or keep the interrupt request pending. The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts are accepted. Table 5.2.1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 (ILEVEL = "000") Accepted when IMASK is 1 –7 1 (ILEVEL = "001") Accepted when IMASK is 2 –7 2 (ILEVEL = "010") Accepted when IMASK is 3 –7 3 (ILEVEL = "011") Accepted when IMASK is 4 –7 4 (ILEVEL = "100") Accepted when IMASK is 5 –7 5 (ILEVEL = "101") Accepted when IMASK is 6 –7 6 (ILEVEL = "110") Accepted when IMASK is 7 7 (ILEVEL = "111") Not accepted (interrupts disabled) Interrupt request from each internal peripheral I/O Interrupt enabled ILEVEL (levels 0-7) Data bus Bits 5-7 or bits 13-15 F/F Set Set/clear IREQ Interrupt priority resolving circuit F/F Reset IVECT read IMASK write Clear To the CPU core Bit 3 or 11 Set EI Interrupt request from each group internal peripheral I/O Interrupt enabled b3, b11Data bus b5-b7, b13-b15 Read IREQ Read-only circuit ILEVEL (levels 0-7) Group interrupt Interrupt priority resolving circuit F/F Clear To the CPU coreSet EI Reset IVECT read IMASK write

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0)

5.3 Interrupt Request Sources in Internal Peripheral I/O

The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O, A-D converter, RTD and CAN. For details about these interrupts, see each section in which the relevant internal peripheral I/O is described. Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O Interrupt Request Sources Contents Number of ICU Type of I nput Input Sources Source ( Note 1) TIN3–6 input interrupt request TIN3–TIN6 inputs 4 Level-recognized TIN20–29 input interrupt request TIN20–TIN29 inputs 10 Level-recognized TIN12–19 input interrupt request TIN12–TIN19 inputs 8 Level-recognized TIN0–2 input interrupt request TIN0–TIN2 inputs 3 Level-recognized TIN7–11 input interrupt request TIN7–TIN11 inputs 5 Level-recognized TMS0,1 output interrupt request TMS0, TMS1 output 2 Level-recognized TOP8,9 output interrupt request TOP8, TOP9 output 2 Level-recognized TOP10 output interrupt request TOP10 output 1 Edge-recognized TIO4–7 output interrupt request TIO4–TIO7 outputs 4 Level-recognized TIO8,9 output interrupt request TIO8, TIO9 outputs 2 Level-recognized TOP0 –5 output interrupt request TOP0–TOP5 outputs 6 Level-recognized TOP6,7 output interrupt request TOP6–TOP7 outputs 2 Level-recognized TIO0–3 output interrupt request TIO0–TIO3 outputs 4 Level-recognized DMA0-4 interrupt request DMA0 –4 transfer completed 5 Level-recognized SIO1 receive interrupt request SIO1 reception-completed or receive error interrupt 1 Edge-recognized SIO1 transmit interrupt requestSIO1 transmission-completed or transmit buffer empty 1 Edge-recognized interrupt SIO0 receive interrupt request SIO0 reception-completed or receive error interrupt 1 Edge-recognized SIO0 transmit interrupt requestSIO0 transmission-completed or transmit buffer empty 1 Edge-recognized interrupt A-D0 conversion interrupt requestA-D0 converter’s scan mode one-shot operation, 1 Edge-recognized single mode or comparate mode completed TID0 output interrupt request TID0 output 1 Edge-recognized TOU0 output interrupt request TOU0_0–TOU0_7 outputs 8 Level-recognized DMA5 –9 interrupt request DMA5 –9 transfer completed 5 Level-recognized SIO2,3 transmit/receive interrupt SIO2,3 reception-completed or receive error interrupt, 4 Level-recognized request transmission-completed or transmit buffer empty interrupt RTD interrupt request RTD interrupt generation command 1 Edge-recognized TID1 output interrupt request TID1 output 1 Edge-recognized TOU1,2 output interrupt request TOU1_0–TOU1_7 outputs, TOU2_0–TOU2_7 outputs 16 Level-recognized SIO4,5 transmit/receive interrupt SIO4,5 reception-completed or receive error interrupt, 4 Level-recognized request transmission-completed or transmit buffer empty interrupt A-D1 conversion interrupt requestA-D1 converter’s scan mode one-shot operation, 1 Edge-recognized single mode or comparate mode completed TID2 output interrupt request TID2 output 1 Edge-recognized TIN30–33 input interrupt request TIN30–TIN33 inputs 4 Level-recognized CAN0 transmit/receive & errorCAN0 transmission or reception completed, CAN0 error 35 Level-recognized interrupt request passive, CAN0 error bus-off, CAN0 bus error, single shot CAN1 transmit/receive & errorCAN1 transmission or reception completed, CAN1 error 35 Level-recognized interrupt request passive, CAN1 error bus-off, CAN1 bus error, single shot Note 1: ICU type of input source  Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU.  Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held low. For this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software.

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0) The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The 32-source interrupt requests are assigned the following vector table addresses. Table 5.4.1 ICU Vector Table Addresses Interrupt Request Source ICU Vector Table Addresses TIN3–6 input interrupt request H'0000 0094 – H'0000 0097 TIN20–29 input interrupt request H'0000 0098 – H'0000 009B TIN12–19 input interrupt request H'0000 009C – H'0000 009F TIN0–2 input interrupt request H'0000 00A0 – H'0000 00A3 TIN7–11 input interrupt request H'0000 00A4 – H'0000 00A7 TMS0,1 output interrupt request H'0000 00A8 – H'0000 00AB TOP8,9 output interrupt request H'0000 00AC – H'0000 00AF TOP10 output interrupt request H'0000 00B0 – H'0000 00B3 TIO4–7 output interrupt request H'0000 00B4 – H'0000 00B7 TIO8,9 output interrupt request H'0000 00B8 – H'0000 00BB TOP0 –5 output interrupt request H'0000 00BC – H'0000 00BF TOP6,7 output interrupt request H'0000 00C0 – H'0000 00C3 TIO0–3 output interrupt request H'0000 00C4 – H'0000 00C7 DMA0 –4 interrupt request H'0000 00C8 – H'0000 00CB SIO1 receive interrupt request H'0000 00CC – H'0000 00CF SIO1 transmit interrupt request H'0000 00D0 – H'0000 00D3 SIO0 receive interrupt request H'0000 00D4 – H'0000 00D7 SIO0 transmit interrupt request H'0000 00D8 – H'0000 00DB A-D0 conversion interrupt request H'0000 00DC – H'0000 00DF TID0 output interrupt request H'0000 00E0 – H'0000 00E3 TOU0 output interrupt request H'0000 00E4 – H'0000 00E7 DMA5 –9 interrupt request H'0000 00E8 – H'0000 00EB SIO2,3 transmit/receive interrupt request H'0000 00EC – H'0000 00EF RTD interrupt request H'0000 00F0 – H'0000 00F3 TID1 output interrupt request H'0000 00F4 – H'0000 00F7 TOU1,2 output interrupt request H'0000 00F8 – H'0000 00FB SIO4,5 transmit/receive interrupt request H'0000 00FC – H'0000 00FF A-D1 conversion interrupt request H'0000 0100 – H'0000 0103 TID2 output interrupt request H'0000 0104 – H'0000 0107 TIN30–33 input interrupt request H'0000 0108 – H'0000 010B CAN0 transmit/receive & error interrupt request H'0000 010C– H'0000 010F CAN1 transmit/receive & error interrupt request H'0000 0110– H'0000 0113

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0) Figure 5.5.1 Example of Priority Resolution when Accepting Interrupt Requests

5.5.1 Acceptance of Internal Peripheral I/O Interrupts

An interrupt request from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set in the Interrupt Control Register and the IMASK value of the Interrupt Request Mask Register. If its priority is higher than the IMASK value, the interrupt request is accepted. However, if two or more interrupt requests occur simultaneously, the Interrupt Controller resolves priority between these interrupt requests follow- ing the procedure described below. 1) The ILEVEL values set in the Interrupt Control Registers for the respective internal peripheral I/Os are compared with each other. 2) If the ILEVEL values are the same, priorities are resolved according to the predetermined hardware priority. 3) The ILEVEL and IMASK values are compared. If two or more interrupt requests occur simultaneously, the Interrupt Controller first compares their priority levels set in each Interrupt Control Register’s ILEVEL bit to select an interrupt request that has the highest priority. If the interrupt requests have the same ILEVEL value, their priorities are resolved according to the hardware fixed priority. The interrupt request thus selected has its ILEVEL value compared with the IMASK value and if its priority is higher than the IMASK value, the Interrupt Controller sends an EI request to the CPU. Interrupt requests may be masked by setting the Interrupt Request Mask Register and the Interrupt Control Register’s ILEVEL bit (disabled at level 7) provided for each internal peripheral I/O and the PSW register IE bit. Level (ILEVEL) Resolve priority according to hardware priority Compare with IMASK value TIN3-6 input interrupt request TIO4-7 output interrupt request TOP8,9 output interrupt request SIO0 transmit interrupt request DMA0-4 interrupt request A-D0 conversion interrupt request (ILEVEL settings) Level 3 Level 4 Level 5 Level 3 Level 1 Level 3 Not requested Requested Requested Requested Requested Requested Hardware fixed priority Accept interrupt if PSW register IE bit = 1 Level 3 Level 3 Level 3 Can be accepted when IMASK = 4-7 1) 2) 3)

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0) Table 5.5.1 Hardware Fixed Priority Levels Priority Interrupt Request Source ICU Vector Table Address ICU Type of Input Source High TIN3 –6 input interrupt request H'0000 0094 – H'0000 0097 Level-recognized TIN20–29 input interrupt request H'0000 0098 – H'0000 009B Level-recognized TIN12–19 input interrupt request H'0000 009C – H'0000 009F Level-recognized TIN0–2 input interrupt request H'0000 00A0 – H'0000 00A3 Level-recognized TIN7–11 input interrupt request H'0000 00A4 – H'0000 00A7 Level-recognized TMS0,1 output interrupt request H'0000 00A8 – H'0000 00AB Level-recognized TOP8,9 output interrupt request H'0000 00AC – H'0000 00AF Level-recognized TOP10 output interrupt request H'0000 00B0 – H'0000 00B3 Edge-recognized TIO4–7 output interrupt request H'0000 00B4 – H'0000 00B7 Level-recognized TIO8,9 output interrupt request H'0000 00B8 – H'0000 00BB Level-recognized TOP0 –5 output interrupt request H'0000 00BC – H'0000 00BF Level-recognized TOP6,7 output interrupt request H'0000 00C0 – H'0000 00C3 Level-recognized TIO0–3 output interrupt request H'0000 00C4 – H'0000 00C7 Level-recognized DMA0 –4 interrupt request H'0000 00C8 – H'0000 00CB Level-recognized SIO1 receive interrupt request H'0000 00CC – H'0000 00CF Edge-recognized SIO1 transmit interrupt request H'0000 00D0 – H'0000 00D3 Edge-recognized SIO0 receive interrupt request H'0000 00D4 – H'0000 00D7 Edge-recognized SIO0 transmit interrupt request H'0000 00D8 – H'0000 00D8 Edge-recognized A-D0 conversion interrupt request H'0000 00DC – H'0000 00DF Edge-recognized TID0 output interrupt request H'0000 00E0 – H'0000 00E3 Edge-recognized TOU0 output interrupt request H'0000 00E4 – H'0000 00E7 Level-recognized DMA5 –9 interrupt request H'0000 00E8 – H'0000 00EB Level-recognized SIO2,3 transmit/receive interrupt request H'0000 00EC– H'0000 00EF Level-recognized RTD interrupt request H'0000 00F0 – H'0000 00F3 Edge-recognized TID1 output interrupt request H'0000 00F4 – H'0000 00F7 Edge-recognized TOU1,2 output interrupt request H'0000 00F8 – H'0000 00FB Level-recognized SIO4,5 transmit/receive interrupt request H'0000 00FC– H'0000 00FF Level-recognized A-D1 conversion interrupt request H'0000 0100 – H'0000 0103 Edge-recognized TID2 output interrupt request H'0000 0104 – H'0000 0107 Edge-recognized TIN30–33 input interrupt request H'0000 0108 – H'0000 010B Level-recognized CAN0 transmit/receive & error interrupt H'0000 010C– H'0000 010F Level-recognized request CAN1 transmit/receive & error interrupt H'0000 0110– H'0000 0113 Level-recognized Low request Table 5.5.2 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 (ILEVEL = "000") Accepted when IMASK is 1 –7 1 (ILEVEL = "001") Accepted when IMASK is 2 –7 2 (ILEVEL = "010") Accepted when IMASK is 3 –7 3 (ILEVEL = "011") Accepted when IMASK is 4 –7 4 (ILEVEL = "100") Accepted when IMASK is 5 –7 5 (ILEVEL = "101") Accepted when IMASK is 6 –7 6 (ILEVEL = "110") Accepted when IMASK is 7 7 (ILEVEL = "111") Not accepted (interrupts disabled)

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0)

5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers

(1) Branching to the interrupt handler Upon accepting an interrupt request, the CPU branches to the EIT vector entry after performing the hardware preprocessing as described in Section 4.3, “EIT Processing Procedure.” The EIT vector entry for External Interrupt (EI) is located at the address H’0000 0080. This address is where the instruction (not the jump address itself) for branching to the beginning of the interrupt handler routine for external interrupt requests is written. (2) Processing in the External Interrupt (EI) handler A typical operation of the External Interrupt (EI) handler (for interrupts from internal peripheral I/O) is shown in Figure 5.5.2. [1] Saving each register to the stack Save the BPC, PSW and general-purpose registers to the stack. Also, save the accumulator and FPSR register to the stack as necessary. [2] Reading the Interrupt Request Mask Register (IMASK) and saving to the stack Read the Interrupt Request Mask Register and save its content to the stack. [3] Reading the Interrupt Vector Register (IVECT) Read the Interrupt Vector Register. This register holds the 16 low-order address bits of the ICU vector table for the accepted interrupt request source that was stored in it when accepting an interrupt request. When the Interrupt Vector Register is read, the following processing is automatically performed in hardware:  The interrupt priority level of the accepted interrupt request (ILEVEL) is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.)  The accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources).  The interrupt request (EI) to the CPU core is dropped.  The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). [4] Reading and overwriting the Interrupt Request Mask Register (IMASK) Read the Interrupt Request Mask Register and overwrite it with the read value. This write to the IMASK register causes the following processing to be automatically performed in hardware:  The interrupt request (EI) to the CPU core is dropped.  The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Note:  Processing in [4] here is unnecessary when multiple interrupts are to be enabled in [6] below. [5] Reading the ICU vector table Read the ICU vector table for the accepted interrupt request source. The relevant ICU vector table address can be obtained by zero-extending the content of the Interrupt Vector Register that was read in [3] (i.e., the 16 low-order address bits of the ICU vector table for the accepted interrupt request source). The ICU vector table must have set in it the start address of the interrupt handler for the interrupt request source concerned.) [6] Enabling multiple interrupts To enable another higher priority interrupt while processing the accepted interrupt (i.e., enabling multiple interrupts), set the PSW register IE bit to "1". [7] Branching to the internal peripheral I/O interrupt handler Branch to the start address of the interrupt handler that was read out in [5]. [8] Processing in the internal peripheral I/O interrupt handler [9] Disabling interrupts Clear the PSW register IE bit to "0" to disable interrupts.

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0) [10] Restoring the Interrupt Request Mask Register (IMASK) Restore the Interrupt Request Mask Register that was saved to the stack in [2]. [11] Restoring registers from the stack Restore the registers that were saved to the stack in [1]. [12] Completion of external interrupt processing Execute the RTE instruction to complete the external interrupt processing. The program returns to the state in which it was before the currently processed interrupt request was accepted. (3) Identifying the source of the interrupt request generated If any internal peripheral I/O has two or more interrupt request sources, check the Interrupt Request Status Register provided for each internal peripheral I/O to identify the source of the interrupt request generated. (4) Enabling multiple interrupts To enable multiple interrupts in the interrupt handler, set the PSW register IE (Interrupt Enable) bit to enable interrupt requests to be accepted. However, before writing "1" to the IE bit, be sure to save each register (BPC, PSW, general-purpose registers and IMASK) to the stack. Note:  Before enabling multiple interrupts, read the Interrupt Vector Register (IVECT) and then the ICU vector table, as shown in Figure 5.5.2, “Typical Handler Operation for Interrupts from Internal Peripheral I/O.”

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0) Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O Note 1: For operations at EIT acceptance and return from EIT, also see Section 4.3, "EIT Processing Procedure." Note 2: Do not read the Interrupt Vector Register (IVECT) or write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts are disabled (PSW register IE bit = 0). Note 3: When multiple interrupts are disabled, execute processing in [4]. Processing in [4] is unnecessary if multiple interrupts are enabled by executing processing in [6] and [9]. Note 4: To enable multiple interrupts, execute processing in [6] and [9]. Note 5: To reenable interrupts (by setting the IE bit to 1) after reading the Interrupt Vector Register (IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts. In the example here, there is no need to add a dummy access because the ICU vector table is read after reading the IVECT register. Similarly, to reenable interrupts (by setting the IE bit to 1) after writing to the Interrupt Request Mask Register (IMASK), perform a dummy access to the internal memory, etc. before reenabling interrupts. H'0000 0080 BRA instruction Read Interrupt Vector Register (IVECT) Read ICU vector table Branch to the interrupt handler for each internal peripheral I/O RTE H'0080 0004 H'0000 0094 H'0000 0113 Interrupt handler EI (External Interrupt) handler EI (External Interrupt) vector entry Interrupt handler start address Program being executed Interrupt generated IVECT Save BPC to the stack Save PSW to the stack Save general-purpose registers to the stack Restore BPC from the stack Restore PSW from the stack Restore general-purpose registers from the stack Read and save Interrupt Request Mask Register (IMASK) to the stack IMASK H'0080 0000 Set PSW register IE bit to 1 Clear PSW register IE bit to 0 Restore Interrupt Request Mask Register (IMASK) from the stack [1] [2] [3] [5] [7] [8] [9] [6] [10] [11] ICU vector table (Note 1) (Note 1) Hardware preprocessing when EIT is accepted Hardware postprocessing when RTE instruction is executed Read and overwrite Interrupt Request Mask Register (IMASK) [4] [12] (Note 2) (Note 2) (Note 3) (Note 4) (Note 5) (Note 4) (Note 2) Interrupt handler [1] to [12]: Processing of EI by interrupt handler

INTERRUPT CONTROLLER (ICU) 32180 Group User’s Manual (Rev.1.0)

5.6 Description of System Break Interrupt (SBI) Operation

5.6.1 Acceptance of SBI

System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt is accepted anytime upon detec- tion of a falling edge on the SBI# signal input pin no matter how the PSW register IE bit is set, and cannot be masked.

5.6.2 SBI Processing by Handler

When the system break interrupt generated has been serviced, shut down or reset the system without returning to the program that was being executed when the interrupt occurred. Figure 5.6.1 Typical SBI Operation H'0000 0010 BRA instruction SBI (System Break Interrupt) handler SBI (System Break Interrupt) vector entry Program being executed SBI generated Processing to shut down the system (Note 1) Note 1: Do not return to the program that was being executed when the interrupt occurred. Shut down or reset the system

6.1 Outline of the Internal Memory

6.2 Internal RAM

6.3 Internal Flash Memory

6.4 Registers Associated with the Internal

6.5 Programming the Internal Flash Memory

6.6 Virtual Flash Emulation Function

6.7 Connecting to A Serial Programmer

6.8 Internal Flash Memory Protect Function

6.9 Precautions To Be Taken when Rewriting

32180 Group User’s Manual (Rev.1.0) The 32180 internally contains the following types of memory:  48-Kbyte RAM  1-Mbyte (1,024-Kbyte) flash memory Specifications of the internal RAM are shown below. Table 6.2.1 Specifications of the Internal RAM Item Specification Size 48 Kbytes Location address H’0080 4000 to H’0080 FFFF Wait insertion Operates with zero wait states Internal bus connection Connected by 32-bit bus Dual port By using the Real-Time Debugger (RTD), data can be read (monitored) or written to any area of the internal RAM via serial communication from external devices independently of the CPU. (See Chapter 14, “Real-Time Debugger.”) Notes:  Immediately after power-on reset (for the power-on case in which VDDE also goes up from GND), the value of the RAM is undefined.  If the RAM is reset during RAM backup (power for only VDDE is on), the RAM retains the value it had immediately before being reset. Specifications of the internal flash memory are shown below. Table 6.3.1 Specifications of the Internal Flash Memory Item Specification Size 1 Mbytes (1,024 Kbytes) Location address H’0000 0000 to H’000F FFFF Wait insertion Operates with one wait state Durability Can be rewritten 100 times Internal bus connection Instruction access: Connected by 64-bit bus (Transfer rates equivalent to zero wait states on 32-bit bus are possible.) Data access: Connected by 32-bit bus Other Virtual flash emulation function is incorporated. (See Section 6.6, “Virtual Flash Emulation Function.”)

32180 Group User’s Manual (Rev.1.0) H'0000 0000 H'0000 4000 H'0000 6000 H'0000 8000 H'0001 0000 H'0002 0000 H'0003 0000 H'0004 0000 H'0005 0000 H'0006 0000 H'0007 0000 H'0008 0000 H'0009 0000 H'000A 0000 H'000B 0000 H'000C 0000 H'000D 0000 H'000E 0000 H'000F 0000 H'000F FFFF 16KB 8KB 8KB 32KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8 Block 9 Block 10 Block 11 Block 12 Block 13 Block 14 Block 15 Block 16 Block 17 Block 18 Unequal blocks Equal blocks Internal flash memory area of the M32180F8 (1,024 Kbytes) Figure 6.3.1 Block Configuration of the M32180F8’s Internal Flash Memory

32180 Group User’s Manual (Rev.1.0)

6.4 Registers Associated with the Internal Flash Memory

A register map associated with the internal flash memory is shown below. Internal Flash Memory Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 01E0 Flash Mode Register Flash Status Register 1 6-4 (FMOD) (FSTAT1) 6-5 H'0080 01E2 Flash Control Register 1 Flash Control Register 2 6-7 (FCNT1) (FCNT2) 6-8 H'0080 01E4 Flash Control Register 3 Flash Control Register 4 6-9 (FCNT3) (FCNT4) H'0080 01E6 (Use inhibited area) H'0080 01E8 Virtual Flash S Bank Register 0 6-11 (FESBANK0) H'0080 01EA Virtual Flash S Bank Register 1 6-11 (FESBANK1) H'0080 01EC Virtual Flash S Bank Register 2 6-11 (FESBANK2) H'0080 01EE Virtual Flash S Bank Register 3 6-11 (FESBANK3) H'0080 01F0 Virtual Flash S Bank Register 4 6-11 (FESBANK4) H'0080 01F2 Virtual Flash S Bank Register 5 6-11 (FESBANK5) H'0080 01F4 Virtual Flash S Bank Register 6 6-11 (FESBANK6) H'0080 01F6 Virtual Flash S Bank Register 7 6-11 (FESBANK7)

6.4.1 Flash Mode Register

Flash Mode Register (FMOD) <Address: H ’0080 01E0> 123456 b 7b0 FPMOD ?0 0 0 0 0 0 0 <After reset: H’0?> b Bit Name Function R W 0–6 No function assigned. Fix to "0" 00

7 FPMOD 0: FP pin = "low" R –

External FP pin status bit 1: FP pin = "high" The Flash Mode Register (FMOD) is a read-only status register, with its FPMOD bit indicating the FP (Flash Protect) pin status. The internal flash memory is enabled for programming or erase operation only when FPMOD = "1", and is protected against programming or erase operation when FPMOD = "0".

32180 Group User’s Manual (Rev.1.0)

6.4.2 Flash Status Registers

There are two registers to indicate the status of the internal flash memory: Flash Status Register 1 (FSTAT1) located in the SFR area (H’0080 01E1) and Flash Status Register 2 (FSTAT2) included in the internal flash memory. Use these two status registers (FSTAT1 and FSTAT2) to control the programming or erase operation performed on the internal flash memory. Flash Status Register 1 (FSTAT1) <Address: H ’0080 01E1> 9 1 01 11 21 31 4 b 1 5b8 FSTAT 10 0 0 0 0 0 0 <After reset: H’01> b Bit Name Function R W 8–14 No function assigned. Fix to "0". 00

15 FSTAT 0: Busy R –

Ready/busy status bit 1: Ready Flash Status Register 1 (FSTAT1) is a read-only status register used to know the status of the programming or erase operation performed on the internal flash memory. When FSTAT = "0" (busy), the internal flash memory is being programmed or erased, during which time do not start a new programming or erase operation on it. When FSTAT = "1" (ready), a new programming or erase operation can be started on it. Furthermore, while FSTAT = "0" (busy), do not operate on the FCNT4 register FRESET bit described later.

6.4.3 Flash Status Register 2 (FSTAT2)

Flash Status Register 2 (FSTAT2) 9 1 01 11 21 31 4 b 1 5b8 WRERR2WRERR1ERASEFBUSY 1 00 00 0 0 0 <After reset: H’80> b Bit Name Function R W

8 FBUSY 0: Being programmed or erased R –

Flash busy bit 1: Ready state 9 No function assigned. Fix to "0". 00

10 ERASE 0: Erase normally operating or terminated R –

Erase status confirmation bit 1: Erase error occurred

11 WRERR1 0: Programming normally operating or terminated R –

Write status confirmation bit 1 1: Programming error occurred

12 WRERR2 0: Programming normally operating or terminated R –

Write status confirmation bit 2 1: Over-programming occurred 13–15 No function assigned. Fix to "0". 00

32180 Group User’s Manual (Rev.1.0) This status register is included in the internal flash memory, and can be enabled for read by writing the Read Status command (H’7070) to any address of the internal flash memory. For details, see Section 6.5, “Program- ming the Internal Flash Memory.” Flash Status Register 2 (FSTAT2) consists of the following four read-only status bits that indicate the operation condition of the internal flash memory. (1) FBUSY (Flash Busy) bit (Bit 8) The FBUSY bit is used to determine whether the operation on the internal flash memory is finished when it is being programmed or erased. When FBUSY = "0", it means that the programming or erase operation is being executed; when FBUSY = "1", the operation is finished. (2) ERASE (Erase status) bit (Bit 10) The ERASE bit is used to determine after execution of processing whether the erase operation performed on the internal flash memory resulted in an error. When ERASE = "0", it means that the erase operation termi- nated normally; when ERASE = "1", the erase operation terminated in an error. (3) WRERR1 (Write status 1) bit (Bit 11) The WRERR1 bit is used to determine after completion of processing whether the programming operation performed on the internal flash memory resulted in an error. When WRERR1 = "0", it means that the pro- gramming operation terminated normally; when WRERR1 = "1", the programming operation terminated in an error. The condition under which WRERR1 is set to "1" is when any bit other than those that must be "0" is found to be "0" by comparison between the write data and the data in the internal flash memory. (4) WRERR2 (Write status 2) bit (Bit 12) The WRERR2 bit is used to determine after execution of processing whether the programming operation performed on the internal flash memory resulted in an error. When WRERR2 = "0", it means that the pro- gramming operation terminated normally; when WRERR2 = "1", the programming operation terminated in an error. The condition under which WRERR2 is set to "1" is when the internal flash memory cannot be written to even by repeating the programming operation a specified number of times.

32180 Group User’s Manual (Rev.1.0)

6.4.4 Flash Control Registers

Flash Control Register 1 (FCNT1) <Address: H ’0080 01E2> 123456 b 7b0 FEMMODFENTRY 0 00 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00

3 FENTRY 0: Normal read R W

Flash E/W enable mode entry bit 1: Program/erase enable 4–6 No function assigned. Fix to "0". 00

7 FEMMOD 0: Normal mode R W

Virtual flash emulation mode bit 1: Virtual flash emulation mode Flash Control Register 1 (FCNT1) consists of the following two bits to control the internal flash memory. (1) FENTRY (Flash Mode Entry) bit (Bit 3) The FENTRY bit controls entry to flash E/W enable mode. Flash E/W enable mode can only be entered when FENTRY = "1". To set the FENTRY bit to "1", write "0" and then "1" to the FENTRY bit in succession while the FP pin = "high". To clear the FENTRY bit, check to see that the FSTAT1 register FSTAT bit = "1" (ready) and then write "0" to the FENTRY bit. Note that the following operations cannot be performed while programming or erasing the internal flash memory (FSTAT1 register FSTAT bit = "0" (busy)). If one of these operations is attempted, the FENTRY bit is cleared to "0" in hardware. 1) Writing "0" to the FENTRY bit 2) Entering a low-level signal to the FP pin 3) Entering a low-level signal to the RESET# pin When running a program resident in the internal flash memory while the FENTRY bit = "0", the EI vector entry is located at the address H’0000 0080 of the internal flash memory. When running the flash write/erase program in the RAM while the FENTRY bit = "1", the EI vector entry is located at the address H’0080 4000 of the RAM, allowing the flash programming/erase operation to be controlled using interrupts. Table 6.4.1 Changes of the EI Vector Entry by FENTRY FENTRY EI Vector Entry Address

0 Internal flash memory area H'0000 0080

1 Internal RAM area H'0080 4000

(2) FEMMOD (Virtual Flash Emulation Mode) bit (Bit 7) The FEMMOD bit controls entry to virtual flash emulation mode. Virtual flash emulation mode is entered by setting the FEMMOD bit to "1" while the FENTRY bit = "0". (For details, see Section 6.6, “Virtual Flash Emulation Function.”)

32180 Group User’s Manual (Rev.1.0) FPROT = 0 FENTRY = 1 YES NO FENTRY = 1 FPROT = 1 FPROT is not set to 1 if a write cycle to any other area occurs during this time. FPRO T = 0 FPRO T = Figure 6.4.1 Protection Unlocking Flow Flash Control Register 2 (FCNT2) <Address: H ’0080 01E3> 9 1 01 11 21 31 4 b 1 5b8 FPROT 00 0 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 8–14 No function assigned. Fix to "0". 00

15 FPROT 0: Protection by lock bit effective R W

Unlock bit 1: Protection by lock bit invalidated Flash Control Register 2 (FCNT2) controls invalidation of the internal flash memory protection by a lock bit (protection against programming/erase operation). Protection of the internal flash memory is invalidated by setting the FPROT bit to "1", so that any blocks protected by a lock bit can now be programmed or erased. To set the FPROT bit to "1", write "0" and then "1" to the FPROT bit in succession while the FENTRY bit = "1". To clear the FPROT bit to "0", write "0" to the FPROT bit. If one of the following operations is attempted, the FPROT bit is cleared to "0". 1) Writing "0" to the FPROT bit 2) Entering a low-level signal to the FP pin 3) Clearing the FENTRY bit to "0" 4) Entering a low-level signal to the RESET# pin

32180 Group User’s Manual (Rev.1.0) Flash Control Register 3 (FCNT3) <Address: H’0080 01E4> 123456 b 7b0 FELEVEL 00 0 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 0–6 No function assigned. Fix to "0". 00

7 FELEVEL 0: Normal level R W

Erase margin-up bit 1: Raise erase margin up Flash Control Register 3 (FCNT3) controls the depth of erase levels when erasing the internal flash memory with one of erase commands. The internal flash memory erase level can be deepened by setting the FELEVEL bit to "1". Flash Control Register 4 (FCNT4) <Address: H ’0080 01E5> 9 1 01 11 21 31 4 b 1 5b8 FRESET 00 0 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 8–14 No function assigned. Fix to "0". 00

15 FRESET 0: No operation R W

Flash reset bit 1: Reset Flash Control Register 4 (FCNT4) controls initializing each status bit of Flash Status Register 2 (FSTAT2) or canceling a programming/erase operation. Setting the FRESET bit to "1" initializes each status bit of the FSTAT2 register or cancels a programming/erase operation. The FRESET bit is effective only when the FENTRY bit = "1". If the FENTRY bit = "0", the FRESET bit informa- tion is ignored. When programming or easing the internal flash memory, make sure the FRESET bit remains "0". An example for clearing each status of FSTAT2 during a programming/erase operation, and an example for forcibly terminating (canceling) a programming/erase operation due to time-out are shown below.

32180 Group User’s Manual (Rev.1.0) Figure 6.4.2 Example of FCNT4 Register Operation 1 (Clearing each status of the FSTAT2 register) FRESET = 1 YES NO FENTRY = 1 Program/erase the flash memory Error found FRESET = 0 Program/erase the flash memory FENTRY = 0 * At this point in time, the FSTAT1 register FSTAT bit = 1 (ready). Programming/erase operation terminated normally FRESET = 1 FRESET = 0 Forcibly terminate Flash programming/erase operation has timed out Figure 6.4.3 Example of FCNT4 Register Operation 2 (Forcibly terminating operation when programming/ erasing the internal flash memory)

32180 Group User’s Manual (Rev.1.0)

6.4.5 Virtual Flash S Bank Registers

Virtual Flash S Bank Register 0 (FESBANK0) <Address: H ’0080 01E8> Virtual Flash S Bank Register 1 (FESBANK1) <Address: H ’0080 01EA> Virtual Flash S Bank Register 2 (FESBANK2) <Address: H ’0080 01EC> Virtual Flash S Bank Register 3 (FESBANK3) <Address: H ’0080 01EE> Virtual Flash S Bank Register 4 (FESBANK4) <Address: H ’0080 01F0> Virtual Flash S Bank Register 5 (FESBANK5) <Address: H ’0080 01F2> Virtual Flash S Bank Register 6 (FESBANK6) <Address: H ’0080 01F4> Virtual Flash S Bank Register 7 (FESBANK7) <Address: H ’0080 01F6> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 MODENS SBANKAD 0 000000000 0 0 0 0 0 0 <After reset: H’0000> b Bit Name Function R W

0 MODENS 0: Disable virtual flash emulation function R W

Virtual flash emulation enable bit 1: Enable virtual flash emulation function 1–7 No function assigned. Fix to "0". 00

8 SBANKAD Start address A12 –A19 of the relevant S bank R W

Note:  These registers must always be accessed in halfwords. (1) MODENS (Virtual Flash Emulation Enable) bit (Bit 0) The MODENS bit can be set to "1" after entering virtual flash emulation mode (by setting the FEMMOD bit to "1" while the FENTRY bit = "0"). This causes the virtual flash emulation function to be enabled for the S bank area selected by the SBANKAD bits. (2) SBANKAD (S Bank Address) bits (Bits 8–15) The SBANKAD bits are provided for selecting one of the S banks that are separated every 4 KB. Use these SBANKAD bits to set the eight bits A12–A19 of the 32-bit start address of the desired S bank. Note:  For details, see Section 6.6, “Virtual Flash Emulation Function.”

32180 Group User’s Manual (Rev.1.0) Figure 6.5.1 EI Vector Entry during Flash E/W Enable Mode EI vector entry (H'0000 0080) Internal ROM area Internal RAM H'0000 0000 H'00FF FFFF H'0080 4000 Internal ROM area Internal RAM H'0080 3FFF Flash E/W enable mode (FENTRY = 1) Normal mode (FENTRY = 0) H'0000 0000 H'0080 3FFF EI vector entry (H'0080 4000)H'0080 4000 H'00FF FFFF

6.5.1 Outline of Internal Flash Memory Programming

To program or erase the internal flash memory, there are following two methods to choose depending on the situation: (1) When the flash write/erase program does not exist in the internal flash memory (2) When the flash write/erase program already exists in the internal flash memory For (1), set the FP pin = "high", MOD0 = "high" and MOD1 = "low" to enter boot mode. In this case, the CPU starts running the boot program immediately after reset. The boot program transfers the flash write/erase program into the internal RAM. After the transfer, jump to a location in the RAM and use the RAM-resident program to set the Flash Control Register 1 (FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in boot mode + flash E/W enable mode). When the above is done, use the flash write/erase program that has been transferred into the internal RAM to program or erase the internal flash memory. For (2), set the FP pin = "high", MOD0 = "low" and MOD1 = "low" to enter single-chip mode. Transfer the flash write/erase program from the internal flash memory in which it has been prepared into the internal RAM. After the transfer, jump to the RAM and use the program transferred into the RAM to set the Flash Control Register 1 (FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in single-chip mode + flash E/W enable mode). When the above is done, use the flash write/erase program that has been transferred into the internal RAM to program or erase the internal flash memory. Or flash E/W enable mode can be entered from external extension mode by setting the FP pin = "high", MOD0 = "low" and MOD1 = "high". During flash E/W enable mode (FP pin = 1, FENTRY = 1), the EIT vector entry for External Interrupt (EI) is relocated to the start address (H’0080 4000) of the internal RAM. During normal mode, it is located in the flash area (H’0000 0080).

32180 Group User’s Manual (Rev.1.0) Figure 6.5.2 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase program does not exist in it) (1) When the flash write/erase program does not exist in the internal flash memory In this case, the boot program is used to program or erase the internal flash memory. To transfer the write data, use serial I/O1 in clock-synchronized serial mode. To program or erase the internal flash memory using a flash programmer, follow the procedure described below. SIO1 CPU SIO1 CPU Flash write/ erase program MOD1 = L SIO1 CPU RAM Flash memory FP = L or H RAM RAM <Step 1>  Initial state (Flash write/erase program nonexistent in the internal flash memory) <Step 2>  Set the FP pin high, MOD0 pin high and MOD1 pin low to place the flash memory in boot mode + flash E/W enable mode.  Dessert reset signal and start up with the boot program.  Transfer the flash write/erase program into the RAM.  Jump to the flash write/erase program in the RAM. <Step 3>  Using the flash write/erase program in the RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1.  Program or erase the internal flash memory using the flash write/erase program.  When finished, reset MOD0 low and jump to the internal flash memory or apply a reset to enter normal mode. M32R/ECU M32R/ECU M32R/ECU External device (e.g., flash programmer) External device (e.g., flash programmer) Flash memory Flash write data Flash memory MOD0 = L Boot program Boot program Boot program MOD1 = LFP = H MOD0 = H MOD1 = LFP = H MOD0 = H RESET = L RESET = H RESET = H Flash write/ erase program Write data Write data Write data External device (e.g., flash programmer)

32180 Group User’s Manual (Rev.1.0) RESET# pin MOD0 pin FENTRY bit FP pin MOD1 pin POWER ON Mode selected Reset signal deasserted (Boot program starts) Mode selected Reset signal deasserted Flash programming/erasing by the boot program Settings by the boot program Figure 6.5.3 Internal Flash Memory Write/Erase Timing (when the flash write/erase program does not exist in it)

32180 Group User’s Manual (Rev.1.0) Figure 6.5.4 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase program already exists in it) (2) When the flash write/erase program already exists in the internal flash memory In this case, the flash write/erase program prepared in the internal flash memory is used to program or erase the internal flash memory. For programming/erase operation here, use the internal peripheral circuits in the manner suitable for the programming system. (All resources of the internal peripheral circuits such as the data bus, serial I/O and ports can be used.) The following shows an example for programming or erasing the internal flash memory by using serial I/O0 in single-chip mode. SIO0 CPU Flash write/ erase program SIO0 CPU Flash write/ erase program MOD1 = L SIO0 CPU RAM Flash write/ erase program FP = L or H Write data RAM RAM <Step 1>  Initial state (Flash write/erase program existing in the internal flash memory)  An ordinary program in the internal flash memory is being executed. <Step 2>  Set the FP pin high, MOD1 pin low and MOD0 pin low to place the flash memory in single-chip + flash E/W enable mode.  After determining the FP pin and MOD1 pin levels, transfer the flash write/erase program from the internal flash memory area into the RAM.  Jump to the flash write/erase program in the RAM. <Step 3>  Using the flash write/erase program in the RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1.  Program or erase the internal flash memory using the flash write/erase program in the RAM.  When finished, jump to the program in the flash memory or apply a reset to enter normal mode. M32R/ECU M32R/ECU M32R/ECU External device External device External device Flash memory Flash write data Flash memory MOD0 = L MOD1 = LFP = H MOD0 = L MOD1 = LFP = H MOD0 = L Write data Write data

32180 Group User’s Manual (Rev.1.0) RESET# pin MOD0 pin FENTRY bit FP pin High or low High or low (single-chip or external extension)MOD1 pin Low High or low Flash programming/erasing by the flash write/erase program Flash rewrite starts Flash mode turned on Flash mode turned off Flash write/erase program transferred into the RAM Figure 6 .5.5 Internal Flash Memory Write/Erase Timing (when the flash write/erase program already exists in it)

32180 Group User’s Manual (Rev.1.0)

6.5.2 Controlling Operation Modes during Flash Programming

The microcomputer’s operation mode is set by MOD0, MOD1 and Flash Control Register 1 (FCNT1) FENTRY bit. The table below lists operation modes that may be used when programming or erasing the internal flash memory. Table 6.5.1 Operation Modes Set during Flash Programming/Erase FP MOD0 MOD1 FENTRY (Note 1) Operation Mode Reset Vector Entry EI Vector Entry 0 0 0 0 Single-chip mode Start address of internal Flash area 1 0 0 0 flash memory (H'0000 0080) (H'0000 0000) 0 1 0 0 Processor mode Start address of externalExternal area area (H'0000 0000) (H'0000 0080) 0 0 1 0 External extension Start address of internal Flash area 1 0 1 0 mode flash memory (H'0000 0080) (H'0000 0000) 1 0 0 1 Single-chip mode Start address of internal Beginning of internal RAM + flash E/W enable flash memory (H'0080 4000) (H'0000 0000) 1 1 0 0 Boot mode B oot program starts Flash area running (H '0000 0080) 1 1 0 1 Boot mode + flash B oot program starts Beginning of internal RAM E/W enable running (H '0080 4000) 1 0 1 1 External extension Start address of internal Beginning of internal RAM mode + flash E/W flash memory (H'0080 4000) enable (H'0000 0000) – 11 – Use inhibited –– Note 1: Indicates the Flash Control Register 1 (FCNT1) FENTRY bit status (– denotes “Don ’t care”). However, if FP = "0", writing "1" to FENTRY only results in it cleared to "0". (1) Flash E/W enable mode Flash E/W enable mode is a mode in which the internal flash memory can be programmed or erased. In flash E/W enable mode, no programs can be executed in the internal flash memory. Therefore, the necessary program must be transferred into the internal RAM before entering flash E/W enable mode, so that it can be executed in the RAM. (2) Entering flash E/W enable mode Flash E/W enable mode can only be entered when operating in single-chip, external extension or boot mode. Furthermore, it is only when the FP pin = "high" and the Flash Control Register 1 (FCNT1) FENTRY bit = "1" that flash E/W enable mode can be entered. Flash E/W enable mode cannot be entered when operating in processor mode or the FP pin = "low". (3) Detecting the MOD0 and MOD1 pin levels The MOD0 and MOD1 pin levels ("high" or "low") can be known by checking the P8 Data Register (Port Data Register, H’0080 0708) MOD0DT and MOD1DT bits.

32180 Group User’s Manual (Rev.1.0)

6.5.3 P8 Data Register

P8 Data Register (P8DATA) <Address: H ’0080 0708> 123456 b 7b0 P87DTP86DTP85DTP84DTP83DTP82DTMOD1DTMOD0DT <After reset: Undefined> b Bit Name Function R W

0 MOD0DT 0: MOD0 pin = "low" R –

MOD0 data bit 1: MOD0 pin = "high"

1 MOD1DT 0: MOD1 pin = "low" R –

MOD1 data bit 1: MOD1 pin = "high"

2 P82DT At read R W

Port P82 data bit Depends on how the Port Direction Register is set

3 P83DT  If direction bit = "0" (input mode)

Port P83 data bit 0: Port input pin = "low"

4 P84DT 1: Port input pin = "high"

Port P84 data bit  If direction bit = "1" (output mode) (Note 1)

5 P85DT 0: Port output latch = "0" / Port pin level = "low"

Port P85 data bit 1: Port output latch = "1" / Port pin level = "high"

6 P86DT At write

Port P86 data bit Write to the port output latch

7 P87DT

Note 1: To select the port data to read, use the Port Input Special Function Control Register’s port input data select bit (PISEL).

32180 Group User’s Manual (Rev.1.0) Figure 6.5.6 Procedure for Entering Flash E/W Enable Mode END START Enter one of the following modes:  Single-chip mode  Boot mode  External extension mode Transfer the flash write/erase program into the internal RAM Set the Flash Control Register in SFR area (FCNT1, H'0080 01E2) FENTRY bit to 0 Set the Flash Control Register in SFR area (FCNT1, H'0080 01E2) FENTRY bit to 1 Execute flash write/erase command and various read commands (Note 1) Switched to the flash write/erase program Wait for 1 µs (using a hardware or software timer) Jump to the flash memory or apply reset Switched to normal mode Check MOD0/1 and FP pin levels OK NO END FMOD(H'0080 01E0) FPMOD P8DATA(H'0080 0708) D0 = MOD0DT D1 = MOD1DT Note 1: For details about each command, see Section 6.5.4, "Procedure for Programming/Erasing the Internal Flash Memory." → Go to flash E/W enable mode

32180 Group User’s Manual (Rev.1.0)

6.5.4 Procedure for Programming/Erasing the Internal Flash Memory

To program or erase the internal flash memory, set up chip mode to enter flash E/W enable mode and execute the flash write/erase program in the internal RAM into which it has been transferred from the internal flash memory. In flash E/W enable mode, because the internal flash memory cannot be accessed for read as in normal mode, no programs present in it can be executed. Therefore, the flash write/erase program must be made available in the internal RAM before entering flash E/W enable mode. (Once flash E/W enable mode is entered into, only flash commands and no other commands can be used to access the internal flash memory.) To access the internal flash memory in flash E/W enable mode, issue commands for the internal flash memory address to be operated on. The table below lists the commands that can be issued in flash E/W enable mode. Note:  During flash E/W enable mode, the internal flash memory cannot be accessed for read or write wordwise. Table 6.5.2 Commands in Flash E/W Enable Mode Command Name Issued Command Data Read Array command H'FFFF Page Program command H'4141 Lock Bit Program command H'7777 Block Erase command H'2020 Erase All Unlocked Blocks command H'A7A7 Read Status Register command H'7070 Clear Status Register command H'5050 Read Lock Bit Status command H'7171 Verify command (Note 1) H'D0D0 Note 1:  This command is used in conjunction with Lock Bit Program, Block Erase and Erase All Unlocked Blocks operations.  This command must be issued immediately after the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command.  If the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is followed by the Read Array com- mand (H’FFFF), the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is canceled.  If the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is followed by other than the Verify (H'D0D0) or Read Array (H'FFFF) command, the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is not executed normally and terminated in error. (1) Read Array command Writing the command (H’FFFF) to any address of the internal flash memory places it in read mode. Then read the desired flash memory address, and the content of that address will be read out. Before exiting flash E/W enable mode, always be sure to execute the Read Array command. Write the Read Array command (H'FFFF) to any address of the internal flash memory Read the desired flash memory address END Figure 6.5.7 Read Array Command

32180 Group User’s Manual (Rev.1.0) Read any address of the internal flash memory (Note 3) to check for programming error (see Figure 6.4.2) Last address? YES NO START Write the program data to the internal flash memory address to be programmed (Note 1) Write the next program data to the previously programmed address + 2 Write the Page Program command (H'4141) to any address of the internal flash memory Internal flash memory is programmed by Page Program (Note 2) Finished programming one page? NO YES Wait for 1 µs (using a hardware or software timer) FSTAT bit = 1 TIME OUT? 0.5s YES NO Forcibly terminated (see Figure 6.4.3.) YES NO To next page Note 1: Start programming from the beginning of a 256-byte boundary (lower address H'00). Note 2: When a programming operation started, the internal flash memory is automatically readied to run the Read Status command, so that there is no need to enter the Read Status command until another command is entered. Note 3: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check for programming error. Figure 6.5.8 Page Program Command (2) Page Program command The internal flash memory is programmed one page at a time, each page consisting of 256 bytes (lower addresses H’00 to H’FF). To program the flash memory, write the Page Program command (H’4141) to any address of the internal flash memory and then the program data to the address to be programmed. The protected flash memory blocks cannot be accessed for write by the Page Program command. Page programming is automatically performed by the internal control circuit, and whether the Page Program command has finished can be known by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (See Section 6.4.2, “Flash Status Registers.”) While the FSTAT bit = "0" (busy), the next programming (by the Page Program command) cannot be performed.

32180 Group User’s Manual (Rev.1.0) (3) Lock Bit Program command The internal flash memory can be protected against programming/erase operation one block at a time. The Lock Bit Program command is provided for protecting the flash memory blocks. Write the Lock Bit Program command (H’7777) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to the last even address of the flash memory block to be protected, and this memory block is thereby protected against programming/erase operation. To remove protection, use the Flash Control Register 2 (FCNT2) FPROT bit to invalidate protection by a block bit (see Section 6.4.3, “Flash Control Registers”) and erase the flash memory block whose protection is to be removed. (The content of that memory block is also erased.) Executing a programming/erase operation on flash memory blocks protected by a lock bit results in an error. If erased, the FSTAT2 register ERASE bit is set to "1" (erase error occurred); if programmed, the FSTAT2 register WRERR1 bit is set to "1" (programming error occurred). The table below lists the target flash memory blocks and their addresses to be specified when writing the Verify command. Table 6.5.3 M32180F8 Target Blocks and Specified Addresses Target Block Specified Address

0 H'0000 3FFE

1 H'0000 5FFE

2 H'0000 7FFE

3 H'0000 FFFE

4 H'0001 FFFE

5 H'0002 FFFE

6 H'0003 FFFE

7 H'0004 FFFE

8 H'0005 FFFE

9 H'0006 FFFE

10 H'0007 FFFE

11 H'0008 FFFE

12 H'0009 FFFE

13 H'000A FFFE

14 H'000B FFFE

15 H'000C FFFE

16 H'000D FFFE

17 H'000E FFFE

18 H'000F FFFE

32180 Group User’s Manual (Rev.1.0) END Read any address of the internal flash memory (Note 2) to check for programming error (see Figure 6.4.2) START Write the Verify command (H'D0D0) to the last even address of the flash memory block to be protected Write the Lock Bit Program command (H'7777) to any address of the internal flash memory Lock bit is programmed by Lock Bit Program (Note 1) Wait for 1 µs (using a hardware or software timer) FSTAT bit = 1 TIME OUT? 0.5s YES NO Forcibly terminated (see Figure 6.4.3.) YES NO Note 1: When a programming operation started, the internal flash memory is automatically readied to run the Read Status command, so that there is no need to enter the Read Status command until another command is entered. Note 2: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check for programming error. Figure 6.5.9 Lock Bit Program Command

32180 Group User’s Manual (Rev.1.0) END Read any address of the internal flash memory (Note 2) to check for programming error (see Figure 6.4.2) START Write the Verify command (H'D0D0) to the last even address of the flash memory block to be erased Write the Block Erase command (H'2020) to any address of the internal flash memory Internal flash memory contents are erased by the Block Erase command (Note 1) Wait for 1 µs (using a hardware or software timer) FSTAT bit = 1 TIME OUT? YES NO Forcibly terminated (see Figure 6.4.3.) YES NO Note 1: When an erase operation started, the internal flash memory is automatically readied to run the Read Status command, so that there is no need to enter the Read Status command until another command is entered. Note 2: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check for programming error. Figure 6.5.10 Block Erase Command (4) Block Erase command The Block Erase command erases the content of the internal flash memory one block at a time. To perform this operation, write the Block Erase command (H’2020) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to the last even address of the flash memory block to be erased (see Table 6.5.3, “M32180F8 Target Blocks and Specified Addresses”). The protected flash memory blocks cannot be erased by the Block Erase command. Block erase operation is automatically performed by the internal control circuit, and whether the Block Erase command has finished can be known by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (See Section 6.4.2, “Flash Status Registers.”) While the FSTAT bit = "0" (busy), the next block erase operation (by the Block Erase command) cannot be performed.

32180 Group User’s Manual (Rev.1.0) (5) Erase All Unlocked Blocks command The Erase All Unlocked Blocks command erases all flash memory blocks that are not protected. To erase all unlocked blocks, write the command (H’A7A7) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to any address of the internal flash memory, and all unlocked memory blocks are thereby erased. Read any address of the internal flash memory Note 2 to check for erase error (see Figure 6.4.2) START Write the Verify command (H'D0D0) to any address of the internal flash memory Write the Erase All Unlocked Blocks command (H'A7A7) to any address of the internal flash memory Flash memory contents are erased by Erase All Unlocked Blocks (Note 1) Wait for 1 µs (using a hardware or software timer) FSTAT bit = 1 TIME OUT? 10s YES NO Forcibly terminated (see Figure 6.4.3.) YES NO Note 1: When an erase operation started, the internal flash memory is automatically readied to run the Read Status command, so that there is no need to enter the Read Status command until another command is entered. Note 2: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check for programming error. Figure 6.5.11 Erase All Unlocked Blocks Command

32180 Group User’s Manual (Rev.1.0) Write the Read Status command (H'7070) to any address of the internal flash memory Read any address of the internal flash memory END Figure 6.5.12 Read Status Command (7) Clear Status Register command The Clear Status Register command clears the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to "0". Write the Clear Status Register command (H’5050) to any address of the internal flash memory, and Flash Status Register 2 is thereby initialized. If an error occurs when programming or erasing the internal flash memory and the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) or WRERR2 (write status 2) bit is set to "1", the next programming or erase operation cannot be executed unless each status bit is cleared to "0". START Write the Clear Status Register command (H'5050) to any address of the internal flash memory END Figure 6.5.13 Clear Status Register Command (6) Read Status command The Read Status command reads the content of Flash Status Register 2 (FSTAT2) that indicates whether flash memory programming or erase operation has terminated normally. To read Flash Status Register 2, write the Read Status command (H’7070) to any address of the internal flash memory. Next, read any ad- dress of the internal flash memory, and Flash Status Register 2 (FSTAT2) will be read out.

32180 Group User’s Manual (Rev.1.0) Write the Read Lock Bit Status command (H'7171) to any address of the internal flash memory Read the last even address of the flash memory block to be checked END Figure 6.5.14 Read Lock Bit Status Command (8) Read Lock Bit Status command The Read Lock Bit Status command is provided for checking whether a flash memory block is protected against programming/erase operation. Write the Read Lock Bit Status command (H’7171) to any address of the internal flash memory. Next, read the last even address of the flash memory block to be checked (see Table 6.5.3, “M32180F8 Target Blocks and Specified Addresses”), and the read data shows whether the target block is protected. If the FLBST0 (lock bit 0) and FLBST1 (lock bit 1) in the read data both are "0", it means that the target memory block is protected. If the FLBST0 (lock bit 0) and FLBST1 (lock bit 1) both are "1", it means that the target memory block is not protected.

32180 Group User’s Manual (Rev.1.0) Lock Bit Status Register (FLBST) b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 FLBST 0 FLBST 1 <After reset: Undefined> b Bit Name Function R W 0 No function assigned. ? –

1 FLBST0 0: Protected R –

Lock bit 0 1: Not protected 2–8 No function assigned. ? –

9 FLBST1 0: Protected R –

Lock bit 1 1: Not protected (Same content as FLBST0 is output) 10–15 No function assigned. ? – The Lock Bit Status Register is a read-only register, which is included for each memory block independently of one another. The following shows how the lock bits in this register are set. a) Setting the lock bit to "0" (protected) Issue the Lock Bit Program command (H’7777) to the memory block to be protected. b) Setting the lock bit to "1" (not protected) Set the Flash Control Register 2 FPROT bit to invalidate protection by a block bit, then issue the Block Erase command (H ’2020) or Erase All Unlocked Blocks command (H’A7A7) to erase the memory block which is to be unprotected. This is the only way to set the lock bit to "1". In no way can the lock bit alone be set to "1". c) Lock bit status after reset Because the lock bits are nonvolatile, they are unaffected by a reset and power-off.

32180 Group User’s Manual (Rev.1.0)

6.5.5 Flash Programming Time (Reference)

The following shows the time needed to program internal flash memory for reference. (1) Time required for transfer by SIO (for a transfer data size of 1,024 KB) 1/57,600 bps × 1 (frame) × 11 (number of bits transferred) × 1,024 KB = approx. 200.2 [s] (2) Time required for programming the flash memory 1,024 KB / 256-byte block × 8 ms = approx. 32.8 [s] (3) Time required for erasing the entire area 50 ms × 19 (blocks) = approx. 950 [ms] (4) Total flash programming time (entire 1,024 KB area) When communicating at 57,600 bps via UART, the flash programming time can be ignored because it is very short compared to the serial communication time. Therefore, the total flash programming time can be calcu- lated using the equation below. (1) + (3) = approx. 201 [s] If the transfer time can be ignored by speeding up the serial communication or by other means, the fastest programming time possible can be calculated using the equation below. (2) + (3) = approx. 34 [s]

32180 Group User’s Manual (Rev.1.0) The microcomputer has the function to map 4-Kbyte memory blocks beginning with the address H’0080 8000 into areas (S banks) of the internal flash memory that are divided in 4-Kbyte units. This functions is referred to as the Virtual Flash Emulation Function. This function allows the data located in 4-Kbyte blocks of the internal RAM to be changed with the contents of internal flash memory at the addresses specified by the Virtual Flash Bank Register. That way, the relevant RAM data can read out by reading the content of internal flash memory. For applications that require modifying the contents of internal flash memory (e.g., data table) during operation, this function enables dynamic data modification without the need to modify the relevant RAM data. The RAM blocks allocated for virtual flash emulation can be accessed for read and write the same way as in usual RAM. This function, when used in combination with the microcomputer’s internal Real-Time Debugger (RTD), allows the data table, etc. created in the internal flash memory to be referenced or rewritten from the outside, thereby facili- tating data table tuning from an external device. Note:  Before programming/erasing the internal flash memory, always be sure to exit this virtual flash emulation mode. H'0080 4000 H'0080 8000 H'0080 9000 H'0080 A000 H'0080 B000 H'0080 C000 H'0080 D000 H'0080 E000 H'0080 F000 RAM bank block 0 (FESBANK0)

4 Kbytes

(FESBANK1) (FESBANK2) (FESBANK3) (FESBANK4) (FESBANK5) (FESBANK6) (FESBANK7) (Cannot be used for virtual flash emulation) Internal RAM area Figure 6.6.1 Internal RAM Bank Configuration of the M32180F8

32180 Group User’s Manual (Rev.1.0)

6.6.1 Virtual Flash Emulation Area

The following shows the internal flash memory areas in which the Virtual Flash Emulation Function is useful. Using the Virtual Flash S Bank Register (FESBANK0–FESBANK7), select one among all S banks of internal flash memory that are divided in 4-Kbyte units (by setting the eight start address bits A12–A19 of the desired S bank in the Virtual Flash S Bank Register SBANKAD bits). Then set the Virtual Flash S Bank Register’s flash emulation enable bit (MODENS) to "1", and the selected S bank area will be replaced with 4-Kbyte blocks of the internal RAM beginning with the address H’0080 8000, up to eight such blocks in all. Notes:  If the same bank area is set in two or more Virtual Flash S Bank Registers (FESBANK0– FESBANK7) and each register’s flash emulation enable bit (MODENS) is set to "1" (enabled), the bank is assigned the corresponding internal RAM area (4-Kbyte) according to the priority of Virtual Flash S Bank Registers given below. FESBANK0 > FESBANK1 > FESBANK2 > FESBANK3 > FESBANK4 > FESBANK5 > FESBANK6 > FESBANK7  During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the flash emulation areas set in the internal flash memory.  Before reading any flash emulation area after setting the Flash Control Register 1 (FCNT1) flash emulation mode bit (FEMMOD) to "1", be sure to check that the flash emulation mode bit (FEMMOD) has been set to "1" by reading it once.  Before reading any flash emulation area after setting the Virtual Flash S Bank Register (FESBANK0 –FESBANK7) flash emulation enable bit (MODENS) and bank address bits (SBANKAD), be sure to check that those MODENS and SBANKAD bits have been set to the intended values by reading them once.

32180 Group User’s Manual (Rev.1.0) (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes) S bank 253 (4 Kbytes) S bank 254 (4 Kbytes) S bank 255 (4 Kbytes) H'0000 0000 H'0000 1000 H'0000 2000 H'000F D000 H'000F E000 H'000F F000 <Internal flash> H'0080 8000 H'0080 9000 H'0080 A000 H'0080 B000 H'0080 C000 H'0080 D000 H'0080 E000 H'0080 F000 H'0080 4000 <Internal RAM> Notes:  If the same bank area is set in two or more Virtual Flash S Bank Registers (FESBANK0-FESBANK7) and each register's flash emulation enable bit (MODENS) is set to 1, the bank is assigned the corresponding internal RAM area in order of priority: FESBANK0 > FESBANK1 > FESBANK2 > FESBANK3 > FESBANK4 > FESBANK5 > FESBANK6 > FESBANK7.  If any 4-Kbyte area (S bank) specified by the Virtual Flash S Bank Register is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the flash emulation areas set in the internal flash memory. Figure 6.6.2 Virtual Flash Emulation Area of the M32180F8 S bank S bank 0 S bank 254 S bank 255 S bank 1 S bank 2 Start address of S bank in flash memory Values set in S bank address (SBANKAD) bits H'0000 0000 (Note 1) H'0000 1000 (Note 1) H'0000 2000 (Note 1) H'000F E000 (Note 1) H'000F F000 (Note 1) H'00 H'01 H'02 H'FE H'FF Note 1: Set the eight start address bits A12-A19 of each S bank of internal flash memory that is divided in 4-Kbyte units in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. Figure 6.6.3 Values Set in the M32180F8’s Virtual Flash S Bank Register

32180 Group User’s Manual (Rev.1.0)

6.6.2 Entering Virtual Flash Emulation Mode

To enter virtual flash emulation mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit by writing "1". After entering virtual flash emulation mode, set the Virtual Flash S Bank Register MODENS bit to "1" to enable the Virtual Flash Emulation Function. Even during virtual flash emulation mode, the internal RAM area (H’0080 8000 through H’0080 FFFF) can be accessed the same way as in usual internal RAM. Set RAM location address in Virtual Flash S Bank Register SBANKADn ← Address A12–A19 Write flash data to RAM Enable virtual flash emulation MODENS ← 1 Settings completed Enter virtual flash emulation mode FEMMOD ← 1 Settings start Figure 6.6.4 Virtual Flash Emulation Mode Sequence

32180 Group User’s Manual (Rev.1.0)

6.6.3 Application Example of Virtual Flash Emulation Mode

By using two RAM areas that have been set in the same flash area by the Virtual Flash Emulation Function, the data in the flash memory can be replaced successively. Figure 6.6.5 Application Example of Virtual Flash Emulation Mode (1/2) Replace area Flash memory RAM block 0 Data write to RAM0 RAM block 1 (1) Operation when reset Replaced Data write to RAM1 (2) Programming operation using RAM block 0 Flash memory Initial value Initial value RAM block 0 RAM block 1 Replaced (3) Programming operation switched from RAM block 0 to RAM block 1 Flash memory Initial value RAM block 0 RAM block 1 RAM block 1Bank xx Bank xx Bank xx Bank xx specified Bank xx specified Bank xx specified (settings invalid) RAM block 0 RAM block 0

32180 Group User’s Manual (Rev.1.0) Replaced (4) Programming operation using RAM block 1 Flash memory Initial value RAM block 0 RAM block 1 RAM block 1Bank xx Bank xx specified Replaced (5) Programming operation switched from RAM block 1 to RAM block 0 RAM block 0 Flash memory Initial value RAM block 0 RAM block 1 RAM block 1Bank xx Bank xx specified Bank xx specified (settings invalid) (6) Go to (2) Note: Enclosed in are the valid area. (Bank specification cleared) Data write to RAM0 Figure 6.6.6 Application Example of Virtual Flash Emulation Mode (2/2)

32180 Group User’s Manual (Rev.1.0) For the internal flash memory to be rewritten in boot mode + flash E/W enable mode by using a general-purpose serial programmer, several pins on the microcomputer must be processed to make them suitable for the serial programmer, as shown below. Table 6.7.1 Processing Microcomputer Pins before Using a Serial Programmer Pin Name Pin No. Function Remark SCLKI1 175 Transfer clock input Need to be pulled high RXD1 176 Serial data input (received data) Need to be pulled high TXD1 177 Serial data output (transmit data) P84 178 Transmit/receive enable output Need to be pulled high FP 187 Flash memory protect Connect to the main power supply MOD0 188 Operation mode 0 Connect to the main power supply MOD1 189 Operation mode 1 Connect to ground RESET# 35 Reset After setting MOD0/MOD1, ground and back to main power supply JTRST 50 JTAG reset Pull low via resistor XIN 32 Clock input XOUT 34 Clock output VCNT 30 Control input for PLL circuit OSC-VCC 31 PLL circuit power supply Connect to the main power supply OSC-VSS 29, 33 PLL circuit ground Connect to ground VREF0 64 VREF1 240 AVCC0 63 AVCC1 1 AVSS0 73 AVSS1 231 VDDE 193 RAM backup power supply Connect to the main power supply VCCE 3, 28, 61, 89, 125, 154, 193 Main power supply 5 V +- 10% or 3.3 V +- 10% VCC-BUS 127, 153, 196, 221 Bus power supply Depends on the target system EXCVCC EXCVDD 91, 192

190 Internal power supply Need to be grounded to earth via

VSS 2, 62, 86, 87, 88, 90, 126, 155, 191, 194, 213, 222Ground 0V Analog ground Connect to ground Reference voltage input for A-D converter Connect to the main power supply Analog power supply Connect to the main power supply

32180 Group User’s Manual (Rev.1.0) Figure 6.7.1 Pin Connection Diagram The diagram below shows an example of a user system configuration which has had a serial programmer con- nected. After the user system is powered on, the serial programmer writes to the internal flash memory in clock- synchronized serial mode. No communication problems associated with the oscillator frequency may occur. If the system uses any pins that are to be connected to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the ad- dresses H’0000 0084 through H’0000 008F as an area in which to check the ID for flash memory protection. If the internal flash memory needs to be protected, set any ID in this area. 2kΩ 32180 VCNT XOUT XIN JTRST MOD1 OSC-VSS AVSS0, AVSS1 VSS RESET# FP MOD0 P84/SCLKI0/SCLKO0 P87/SCLKI1/SCLKO1 P86/RXD1 P85/TXD1 VCC-BUS EXCVDD EXCVCC VREF0, VREF1 AVCC0, AVCC1 OSC-VCC VDDE VCCE Connect to the user system power supply rail Connect to the VCCE (5 or 3.3 V) power supply rail Main power supply Connect to the VCCE (5 or 3.3V) power supply rail Main power supply (for reference) RxD (input) TxD (output) SCLK0 (output) BUSY (input) MOD0 (output) FP (output) RESET (output) GND (common) ConnectorFlash programmer signals To system circuit Set microcomputer operating conditions User system board Notes:  Turn on the power for the user system before writing to the internal flash memory.  If P84-P87 are used in the system circuit, connection to a serial programmer must be taken into consideration.  SBI# must be fixed high or low to ensure that no interrupts will be generated.  The pullup resistance values of P84, P86 and P87 must be selected to suit the system design condition.  The typical pullup resistance values of P84, P86 and P87 4.7 to 10 KΩ.  The status of any other ports that are not shown here will not affect flash memory programming.  Make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes while rewriting the internal flash memory.

32180 Group User’s Manual (Rev.1.0) The internal flash memory has the following four types of protect functions to prevent it from being inadvertently rewritten or illegally copied, programmed or erased. (1) Flash memory protect ID When using a tool to program/erase the internal flash memory such as a general-purpose programmer or emu- lator, the ID entered by a tool and the ID stored in the internal flash memory are collated. Unless the correct ID is entered, no programming/erase operations can be performed. (For some tools, tool execution is enabled after erasing the entire flash memory area, and the internal flash memory becomes accessible for write.) (2) Protection by FP pin The internal flash memory is protected in hardware against programming/erase operation by pulling the FP (Flash Protect) pin low. Furthermore, because the FP pin level can be known by reading the Flash Mode Regis- ter (FMOD)’s FPMOD (external FP pin status) bit in the flash write/erase program, the internal flash memory can also be protected in software. For systems that do not require protection by setting external pins, the FP pin may be fixed high to simplify the operation to program/erase the internal flash memory. (3) Protection by FENTRY bit Flash E/W enable mode cannot be entered into unless the Flash Control Register 1 (FCNT1)’s FENTRY (flash mode entry) bit is set to "1". To set the FENTRY bit to "1", write "0" and then "1" in succession while the FP pin is high. (4) Protection by a lock bit Any block of internal flash memory can be protected by setting the lock bit provided for it to "0". That memory block is disabled against programming/erase operation.

32180 Group User’s Manual (Rev.1.0)

6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory

The following describes precautions to be taken when programming/erasing the internal flash memory.  When the internal flash memory is programmed or erased, a high voltage is generated internally. Because mode transitions during programming/erase operation may cause the chip to break down, make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes.  If the system uses any pins that are to be used by a general-purpose programming/erase tool, care must be taken to prevent adverse effects on the system when the tool is connected.  If the internal flash memory needs to be protected while using a general-purpose programming/erase tool, set any ID in the flash memory protect ID verification area (H’0000 0084 to H’0000 008F).  If the internal flash memory does not need to be protected while using a general-purpose programming/erase tool, fill the entire flash memory protect ID verification area (H’0000 0084 to H’0000 008F) with H’FF.  If the Flash Status Register 2 (FSTAT2)’s each error status is to be cleared (initialized to H’80) by resetting the Flash Control Register 4 (FCNT4) FRESET bit, check to see that the Flash Status Register 1 (FSTAT1) FSTAT bit = "1" (ready) before clearing the error status.  Before resetting the Flash Control Register 1 (FCNT1) FENTRY bit from "1" to "0", check to see that the Flash Status Register 1 (FSTAT1) FSTAT bit = "1" (ready) or the Flash Status Register 2 (FSTAT2) FBUSY bit = "1" (ready).  Do not clear the FENTRY bit if the Flash Status Register 1 (FSTAT1) FSTAT bit = "0" (busy) or the Flash Status Register 2 (FSTAT2) FBUSY bit = "0" (being programmed or erased).

32180 Group User’s Manual (Rev.1.0) This page is blank for reasons of layout.

7.1 Outline of Reset

7.2 Reset Operation

7.3 Internal State Immediately after Reset

7.4 Things to Be Considered after Reset

32180 Group User’s Manual (Rev.1.0) The microcomputer is reset by applying a low-level signal to the RESET# input pin. The microcomputer is gotten out of a reset state by releasing the RESET# input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the CPU starts executing from the reset vector entry. When a low-level signal in width of more than 200 ns (a duration needed for noise cancellation) is applied to the RESET# pin, the microcomputer is reset. At this time, pins on the microcomputer are reset (see the Pin State When Reset in Table 1.4.1, “Pin Assignments”), and an internal bus hold request signal is output internally. Fur- thermore, the internal circuits (including the CPU) are reset 9–10 BCLK periods later. When the RESET# input is returned high, the microcomputer pins get out of a reset state and the internal bus hold request is deasserted 17–18 BCLK periods later. Then the internal circuits get out of a reset state 15 BCLK periods after that. Internal circuit reset signal Flip-flop Counter RESET# Extended for a duration during which the RESET# input is held low 17–18BCLK 15BCLK 9–10BCLK RESET# pin Reset signal (internal signal) past the noise canceller Pin reset (Note 2) and internal bus hold request (internal signal) Internal circuit reset (internal signal) Duration needed for noise cancellation (Note 1) 200ns Note 1: If the low level duration of the reset signal is less than 200 ns, it is cancelled by the noise canceller. Note 2: The port-related registers also are reset. Figure 7.2.2 Reset Sequence Figure 7.2.1 Reset Circuit

32180 Group User’s Manual (Rev.1.0)

7.2.1 Reset at Power-on

When powering on the microcomputer, hold the RESET# signal input pin low until the rated power supply volt- age is reached and the microcomputer’s internal x8 clock generator becomes oscillating stably.

7.2.2 Reset during Operation

To reset the microcomputer during operation, hold the RESET# signal input pin low for more than 200 ns.

7.2.3 Reset at Entering RAM Backup Mode

To prevent the RAM access by the CPU or DMA from becoming interrupted by a reset, first an internal bus hold request is output internally after accepting the reset input. Then the internal circuits are reset after the internal bus is placed in a hold state. Note:  Reset input at entering RAM backup mode cannot be used in the following cases (because the internal bus hold request may not be accepted and the RAM contents may be corrupted):  When the lock bit = 1 (see Section 2.7, “Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution”)  When executing any instruction present in external memory

7.2.4 Reset Vector Relocation during Flash Programming

When the reset signal is deasserted (released back high) after entering boot mode, the CPU starts executing the boot program. For details, see Section 6.5, “Programming the Internal Flash Memory.”

32180 Group User’s Manual (Rev.1.0) The table below lists the internal state of the microcomputer immediately after it has gotten out of a reset state. For details about the initial register state of each internal peripheral I/O, see each section in this manual in which the relevant internal peripheral I/O is described. Table 7.3.1 Internal State Immediately after Reset Register State after Reset PSW (CR0) B'0000 0000 0000 0000 ??00 000? 0000 0000 (BSM, BIE, BC bits = undefined) CBR (CR1) H'0000 0000 (C bits = 0) SPI (CR2) Undefined SPU (CR3) Undefined BPC (CR6) Undefined FPSR (CR7) H'0000 0100 (Only DN bit = 1) PC H'0000 0000 (Executed beginning with the address H ’0000 0000) (Note 1) R0 –R15 Undefined ACC (accumulator) Undefined RAM Undefined when reset at power-on. (However, if the RAM is gotten out of reset after returning from backup mode, it retains the content it had before being reset.) Note 1: When in boot mode, the CPU executes the boot program.

• Input/output ports After reset, the microcomputer’s input/output ports are disabled against input in order to prevent current from flowing through the port. To use any ports in input mode, set the Port Input Special Function Control Register (PICNT) PIEN0 bit to enable them for input. For details, see Section 8.3, “Input/Output Port Related Registers.”

8.1 Outline of Input/Output Ports

8.2 Selecting Pin Functions

8.3 Input/Output Port Related Registers

8.4 Port Input Level Switching Function

8.5 Port Peripheral Circuits

8.6 Precautions on Input/Output Ports

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) The 32810 has a total of 158 input/output ports from P0 to P22 (except P5, which is reserved for future use). These input/output ports can be used as input or output ports by setting the respective direction registers. Each input/output port is a dual-function or triple-function pin, sharing the pin with other internal peripheral I/O or extended external bus signal line. Pin functions are selected depending on the current operation mode or by setting the input/output port operation mode registers. (If any internal peripheral I/O has still another function, it is also necessary to set the register provided for that peripheral I/O.) The microcomputer also has a port input function enable bit that can be used to prevent current from flowing into the input ports. This helps to simplify the software and hardware processing to be performed immediately after reset or during flash programming. Note that before any ports can be used in input mode, this port input function enable bit must be set accordingly. The input/output ports are outlined below. Table 8.1.1 Outline of Input/Output Ports Item Specification Number of ports Total 158 ports P0 : P00–P07 (8 ports) P1 : P10–P17 (8 ports) P2 : P20–P27 (8 ports) P3 : P30–P37 (8 ports) P4 : P41–P47 (7 ports) P6 : P61–P63, P65–P67 (6 ports) P7 : P70–P77 (8 ports) P8 : P82–P87 (6 ports) P9 : P93–P97 (5 ports) P10 : P100–P107 (8 ports) P11 : P110–P117 (8 ports) P12 : P124–P127 (4 ports) P13 : P130–P137 (8 ports) P14 : P140–P147 (8 ports) P15 : P150–P157 (8 ports) P16 : P160–P167 (8 ports) P17 : P172–P177 (6 ports) P18 : P180–P187 (8 ports) P19 : P190–P197 (8 ports) P20 : P200–P203 (4 ports) P21 : P210–P217 (8 ports) P22 : P220–P227 (8 ports) Port function The input/output ports can individually be set for input or output mode using the direction control register provided for each input/output port. (However, P221 and P223 are input-only ports.) Pin function Shared with peripheral I/O or extended external signals to serve dual-functions (or shared with two or more peripheral I/O functions to serve triple-functions) Pin function P0–P4, P224–P227: Depends on the CPU operation mode (that is set by MOD0 and MOD1 pins). (Note 1) selection P6–P22: As set by each input/output port’s operation mode register. (However, peripheral I/O pin functions are selected by peripheral I/O registers.) Note 1: If the CPU operation mode is external extension mode, P0–P3, P44–P47 and P224–P227 initially are input/output port pins, and are switched to extended external signal pin functions by setting the respective port operation mode registers. P41–P43, when in external extension mode, serve as dedicated external bus interface signal pins.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) Each input/output port serves dual functions sharing the pin with other internal peripheral I/O or extended external bus signal line (or triple functions sharing the pin with two or more peripheral I/O functions). Pin functions are selected depending on the current operation mode or by setting the input/output port operation mode registers. P0–P4 and P224–P227, when the CPU is set to operate in processor mode, all are switched to serve as signal pins for external access. The CPU operation mode is determined depending on how the MOD0 and MOD1 pins are set (see the table below). Table 8.2.1 CPU Operation Modes and P0–P4 and P224–P227 Pin Functions MOD0 MOD1 Operation Mode P0–P4 and P224–P227 Pin Function VSS VSS Single-chip mode Input/output port pin VSS VCCE External extension mode Input/output port pin or extended external signal pin (Note 1) VCCE VSS Processor mode (FP pin = VSS) Extended external signal pin VCCE VCCE Reserved (use inhibited) – Note 1: P41–P43 serve as dedicated external bus interface signal pins. Note:  VCCE and VSS are connected to 5 or 3.3 V and GND, respectively. Each input/output port has their functions switched between input/output port pins and internal peripheral I/O pins by setting the respective port operation mode registers. If any internal peripheral I/O has two or more pin functions, use the register provided for that peripheral I/O to select the desired pin function. Note that FP and MOD1 pin settings during internal flash memory programming do not affect the pin functions.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) (Reserved) CPU operation mode settings (Note 1) (Note 1) DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 A23 A24 A25 A26 A27 A28 A29 A30 A15 A16 A17 A18 A19 A20 A21 A22 TO16 TO17 TO18 TO19 TO20 TO9 / TO10 / TO8 TO11 TO12 TO13 TO14 TO15 TXD3 (Note 2) CTX1(Note 2) A11 / A12 / CTX0 CRX0 CTX1 CRX1 CS2# CS3# CS2# (Note 2) CS3#(Note 2) TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 TCLK0 TCLK1 TCLK2 TCLK3 TIN0 TIN1 TIN2 TIN3 TIN4 TIN5 TIN6 TIN7 TO21 TO22 TO23 TO24 TO25 TO26 TO27 TO28 TO29 TO30 TO31 TO32 TO33 TO34 TO35 TO36 TIN33/ TIN26 TIN27 TIN28 TIN29 TIN30 TIN31 TIN32 PWMOFF2 TXD4 RXD4 TXD5 RXD5 TO37 TO38 TO39 TO40 TO41 TO42 TO43 TO44 TIN8 TIN9 TIN10 TIN11 TIN12 TIN13 TIN14 TIN15 TIN24 TIN25 TXD2 RXD2 TXD3 RXD3 MOD0 MOD1 SCLKI0 / SCLKI1 / TXD0 RXD0 TXD1 RXD1 (Note 3) (Note 3) SCLKO0 SCLKO1 BLW# / BHW# / RD# CS0# CS1# A13 A14 BLE# BHE# BCLK / WAIT# HREQ# HACK# RTDTXD RTDRXD RTDACK RTDCLK WR# SBI# SCLKI4 / SCLKI5 / (P61) (P62) (P63) (P67) (Note 3) SCLKO4 SCLKO5 TIN16/ TIN17/ TIN18 TIN19 TIN20 TIN21 TIN22 TIN23 PWMOFF0 PWMOFF1 Note 1: During processor mode, these ports are switched to function as extended external signal pins. During external extension mode, only P41-P43 are switched to function as external bus interface pins. Other pins become input/output port pins when reset, so that some of these pins, if needed, must be set to function as external bus interface pins. Note 2: These are triple-function pins. Their desired output function must be selected using the peripheral output select register. Note 3: These ports cannot be used for input/output port function. The SBI#, MOD0 and MOD1 pin input levels can be read from these ports. Figure 8.2.1 Input/Output Ports and Pin Function Assignments

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) The input/output port related registers included in the microcomputer consists of the port data register, port direc- tion register and port operation mode register. Note that P5 is reserved for future use. The tables below show an input/output port related register map. Input/Output Port Related Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0700 P0 Data Register P1 Data Register 8-7 (P0DATA) (P1DATA) H'0080 0702 P2 Data Register P3 Data Register 8-7 (P2DATA) (P3DATA) H'0080 0704 P4 Data Register (Use inhibited area) 8-7 (P4DATA) H'0080 0706 P6 Data Register P7 Data Register 8-7 (P6DATA) (P7DATA) H'0080 0708 P8 Data Register P9 Data Register 8-7 (P8DATA) (P9DATA) H'0080 070A P10 Data Register P11 Data Register 8-7 (P10DATA) (P11DATA) H'0080 070C P12 Data Register P13 Data Register 8-7 (P12DATA) (P13DATA) H'0080 070E P14 Data Register P15 Data Register 8-7 (P14DATA) (P15DATA) H'0080 0710 P16 Data Register P17 Data Register 8-7 (P16DATA) (P17DATA) H'0080 0712 P18 Data Register P19 Data Register 8-7 (P18DATA) (P19DATA) H'0080 0714 P20 Data Register P21 Data Register 8-7 (P20DATA) (P21DATA) H'0080 0716 P22 Data Register (Use inhibited area) 8-7 (P22DATA) (Use inhibited area) H'0080 0720 P0 Direction Register P1 Direction Register 8-8 (P0DIR) (P1DIR) H'0080 0722 P2 Direction Register P3 Direction Register 8-8 (P2DIR) (P3DIR) H'0080 0724 P4 Direction Register (Use inhibited area) 8-8 (P4DIR) H'0080 0726 P6 Direction Register P7 Direction Register 8-8 (P6DIR) (P7DIR) H'0080 0728 P8 Direction Register P9 Direction Register 8-8 (P8DIR) (P9DIR) H'0080 072A P10 Direction Register P11 Direction Register 8-8 (P10DIR) (P11DIR) H'0080 072C P12 Direction Register P13 Direction Register 8-8 (P12DIR) (P13DIR) H'0080 072E P14 Direction Register P15 Direction Register 8-8 (P14DIR) (P15DIR) H'0080 0730 P16 Direction Register P17 Direction Register 8-8 (P16DIR) (P17DIR) H'0080 0732 P18 Direction Register P19 Direction Register 8-8 (P18DIR) (P19DIR) H'0080 0734 P20 Direction Register P21 Direction Register 8-8 (P20DIR) (P21DIR) H'0080 0736 P22 Direction Register (Use inhibited area) 8-8 (P22DIR)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) Input/Output Port Related Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0740 P0 Operation Mode Register P1 Operation Mode Register 8-9 (P0MOD) (P1MOD) H'0080 0742 P2 Operation Mode Register P3 Operation Mode Register 8-10 (P2MOD) (P3MOD) H'0080 0744 P4 Operation Mode Register Port Input Special Function Control Register 8-11 (P4MOD) (PICNT) 8-21 H'0080 0746 P6 Operation Mode Register P7 Operation Mode Register 8-11 (P6MOD) (P7MOD) 8-12 H'0080 0748 P8 Operation Mode Register P9 Operation Mode Register 8-12 (P8MOD) (P9MOD) 8-13 H'0080 074A P10 Operation Mode Register P11 Operation Mode Register 8-13 (P10MOD) (P11MOD) 8-14 H'0080 074C P12 Operation Mode Register P13 Operation Mode Register 8-14 (P12MOD) (P13MOD) 8-15 H'0080 074E P14 Operation Mode Register P15 Operation Mode Register 8-15 (P14MOD) (P15MOD) 8-16 H'0080 0750 P16 Operation Mode Register P17 Operation Mode Register 8-16 (P16MOD) (P17MOD) 8-17 H'0080 0752 P18 Operation Mode Register P19 Operation Mode Register 8-17 (P18MOD) (P19MOD) 8-18 H'0080 0754 P20 Operation Mode Register P21 Operation Mode Register 8-18 (P20MOD) (P21MOD) 8-19 H'0080 0756 P22 Operation Mode Register (Use inhibited area) 8-19 (P22MOD) (Use inhibited area) H'0080 0760 Port Group 0,1 Input Level Setting Register Port Group 2,3 Input Level Setting Register 8-25 (PG01LEV) (PG23LEV) H'0080 0762 Port Group 4,5 Input Level Setting Register Port Group 6,7 Input Level Setting Register 8-25 (PG45LEV) (PG67LEV) H'0080 0764 Port Group 8 Input Level Setting Register (Use inhibited area) 8-25 (PG8LEV) (Use inhibited area) H'0080 076A P10 Peripheral Output Select Register (Use inhibited area) 8-20 (P10SMOD) (Use inhibited area) H'0080 0776 P22 Peripheral Output Select Register (Use inhibited area) 8-20 (P22SMOD)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0)

8.3.1 Port Data Registers

P0 Data Register (P0DATA) <Address: H ’0080 0700> P1 Data Register (P1DATA) <Address: H ’0080 0701> P2 Data Register (P2DATA) <Address: H ’0080 0702> P3 Data Register (P3DATA) <Address: H ’0080 0703> P4 Data Register (P4DATA) <Address: H ’0080 0704> P6 Data Register (P6DATA) <Address: H ’0080 0706> P7 Data Register (P7DATA) <Address: H ’0080 0707> P8 Data Register (P8DATA) <Address: H ’0080 0708> P9 Data Register (P9DATA) <Address: H ’0080 0709> P10 Data Register (P10DATA) <Address: H ’0080 070A> P11 Data Register (P11DATA) <Address: H ’0080 070B> P12 Data Register (P12DATA) <Address: H ’0080 070C> P13 Data Register (P13DATA) <Address: H ’0080 070D> P14 Data Register (P14DATA) <Address: H ’0080 070E> P15 Data Register (P15DATA) <Address: H ’0080 070F> P16 Data Register (P16DATA) <Address: H ’0080 0710> P17 Data Register (P17DATA) <Address: H ’0080 0711> P18 Data Register (P18DATA) <Address: H ’0080 0712> P19 Data Register (P19DATA) <Address: H ’0080 0713> P20 Data Register (P20DATA) <Address: H ’0080 0714> P21 Data Register (P21DATA) <Address: H ’0080 0715> P22 Data Register (P22DATA) <Address: H ’0080 0716> 9 10 11 12 13 14 b15)(b8 123456 b 7b0 Pn0DT Pn1DT Pn2DT Pn3DT Pn4DT Pn5DT Pn6DT Pn7DT n = 0–22 (not including P5) <After reset: Undefined> b Bit Name Function R W 0(b8) Pn0DT <At read> R W Port Pn0 data bit Depends on how the Port Direction Register is set 1(b9) Pn1DT If direction bit = "0" (input mode) R W Port Pn1 data bit 0: Port input pin = "low" 2(b10) Pn2DT 1: Port input pin = "high" R W Port Pn2 data bit If direction bit = "1" (output mode) (Note 1) 3(b11) Pn3DT 0: Port output latch = "0" / Port pin level = "low" R W Port Pn3 data bit 1: Port output latch = "1" / Port pin level = "high" 4(b12) Pn4DT <At write> R W Port Pn4 data bit Write to the port output latch 5(b13) Pn5DT RW Port Pn5 data bit 6(b14) Pn6DT RW Port Pn6 data bit 7(b15) Pn7DT RW Port Pn7 data bit Note 1: To select the port data to read, use the Port Input Special Function Control Register’s port input data select bit (PISEL). Notes:  No data bits are provided for the following ports (read as "0", writing has no effect): P40, P60, P90–P92, P120–P123, P170, P171, P204–P207  The SBI# pin level can be read out by reading the P64DT bit. Writing to the P64DT bit has no effect.  The MOD0 and MOD1 pin levels can be read out by reading the P80DT and P81DT bits, respectively. Writing to the P80DT and P81DT bits has no effect.  P221 and P223 are input-only ports. Writing to the P221DT and P223DT bits has no effect.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0)

8.3.2 Port Direction Registers

P0 Direction Register (P0DIR) <Address: H ’0080 0720> P1 Direction Register (P1DIR) <Address: H ’0080 0721> P2 Direction Register (P2DIR) <Address: H ’0080 0722> P3 Direction Register (P3DIR) <Address: H ’0080 0723> P4 Direction Register (P4DIR) <Address: H ’0080 0724> P6 Direction Register (P6DIR) <Address: H ’0080 0726> P7 Direction Register (P7DIR) <Address: H ’0080 0727> P8 Direction Register (P8DIR) <Address: H ’0080 0728> P9 Direction Register (P9DIR) <Address: H ’0080 0729> P10 Direction Register (P10DIR) <Address: H ’0080 072A> P11 Direction Register (P11DIR) <Address: H ’0080 072B> P12 Direction Register (P12DIR) <Address: H ’0080 072C> P13 Direction Register (P13DIR) <Address: H ’0080 072D> P14 Direction Register (P14DIR) <Address: H ’0080 072E> P15 Direction Register (P15DIR) <Address: H ’0080 072F> P16 Direction Register (P16DIR) <Address: H ’0080 0730> P17 Direction Register (P17DIR) <Address: H ’0080 0731> P18 Direction Register (P18DIR) <Address: H ’0080 0732> P19 Direction Register (P19DIR) <Address: H ’0080 0733> P20 Direction Register (P20DIR) <Address: H ’0080 0734> P21 Direction Register (P21DIR) <Address: H ’0080 0735> P22 Direction Register (P22DIR) <Address: H ’0080 0736> 9 10 11 12 13 14 b15)(b8 123456 b 7b0 Pn0DR Pn1DR Pn2DR Pn3DR Pn4DR Pn5DR Pn6DR Pn7DR 00000000 n = 0–22 (not including P5) <After reset: H’00> b Bit Name Function R W 0(b8) Pn0DR (Port Pn0 direction bit) 0: Input mode R W 1(b9) Pn1DR (Port Pn1 direction bit) 1: Output mode R W 2(b10) Pn2DR (Port Pn2 direction bit) RW 3(b11) Pn3DR (Port Pn3 direction bit) RW 4(b12) Pn4DR (Port Pn4 direction bit) RW 5(b13) Pn5DR (Port Pn5 direction bit) RW 6(b14) Pn6DR (Port Pn6 direction bit) RW 7(b15) Pn7DR (Port Pn7 direction bit) RW Notes:  No direction bits are provided for the following ports (read as 0, writing has no effect): P40, P60, P64, P80, P81, P90–P92, P120–P123, P170, P171, P204–P207, P221, P223  After reset, all ports are set for input mode.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0)

8.3.3 Port Operation Mode Registers

P0 Operation Mode Register (P0MOD) <Address: H ’0080 0740> 123456 b 7b0 P00MD P01MD P02MD P03MD P04MD P05MD P06MD P07MD 00000000 <After reset: H’00> b Bit Name Function R W

0 P00MD 0: P00 R W

Port P00 operation mode bit 1: DB0

1 P01MD 0: P01 R W

Port P01 operation mode bit 1: DB1

2 P02MD 0: P02 R W

Port P02 operation mode bit 1: DB2

3 P03MD 0: P03 R W

Port P03 operation mode bit 1: DB3

4 P04MD 0: P04 R W

Port P04 operation mode bit 1: DB4

5 P05MD 0: P05 R W

Port P05 operation mode bit 1: DB5

6 P06MD 0: P06 R W

Port P06 operation mode bit 1: DB6

7 P07MD 0: P07 R W

Port P07 operation mode bit 1: DB7 Note:  P0 Operation Mode Register is useful only when the CPU operates in external extension mode. P1 Operation Mode Register (P1MOD) <Address: H ’0080 0741> 9 1 01 11 21 31 4 b 1 5b8 P10MD P11MD P12MD P13MD P14MD P15MD P16MD P17MD 00000000 <After reset: H’00> b Bit Name Function R W

8 P10MD 0: P10 R W

Port P10 operation mode bit 1: DB8

9 P11MD 0: P11 R W

Port P11 operation mode bit 1: DB9

10 P12MD 0: P12 R W

Port P12 operation mode bit 1: DB10

11 P13MD 0: P13 R W

Port P13 operation mode bit 1: DB11

12 P14MD 0: P14 R W

Port P14 operation mode bit 1: DB12

13 P15MD 0: P15 R W

Port P15 operation mode bit 1: DB13

14 P16MD 0: P16 R W

Port P16 operation mode bit 1: DB14

15 P17MD 0: P17 R W

Port P17 operation mode bit 1: DB15 Note:  P1 Operation Mode Register is useful only when the CPU operates in external extension mode.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) P2 Operation Mode Register (P2MOD) <Address: H ’0080 0742> 123456 b 7b0 P20MD P21MD P22MD P23MD P24MD P25MD P26MD P27MD 00000000 <After reset: H’00> b Bit Name Function R W

0 P20MD 0: P20 R W

Port P20 operation mode bit 1: A23

1 P21MD 0: P21 R W

Port P21 operation mode bit 1: A24

2 P22MD 0: P22 R W

Port P22 operation mode bit 1: A25

3 P23MD 0: P23 R W

Port P23 operation mode bit 1: A26

4 P24MD 0: P24 R W

Port P24 operation mode bit 1: A27

5 P25MD 0: P25 R W

Port P25 operation mode bit 1: A28

6 P26MD 0: P26 R W

Port P26 operation mode bit 1: A29

7 P27MD 0: P27 R W

Port P27 operation mode bit 1: A30 Note:  P2 Operation Mode Register is useful only when the CPU operates in external extension mode. P3 Operation Mode Register (P3MOD) <Address: H ’0080 0743> 9 1 01 11 21 31 4 b 1 5b8 P30MD P31MD P32MD P33MD P34MD P35MD P36MD P37MD 00000000 <After reset: H’00> b Bit Name Function R W

8 P30MD 0: P30 R W

Port P30 operation mode bit 1: A15

9 P31MD 0: P31 R W

Port P31 operation mode bit 1: A16

10 P32MD 0: P32 R W

Port P32 operation mode bit 1: A17

11 P33MD 0: P33 R W

Port P33 operation mode bit 1: A18

12 P34MD 0: P34 R W

Port P34 operation mode bit 1: A19

13 P35MD 0: P35 R W

Port P35 operation mode bit 1: A20

14 P36MD 0: P36 R W

Port P36 operation mode bit 1: A21

15 P37MD 0: P37 R W

Port P37 operation mode bit 1: A22 Note:  P3 Operation Mode Register is useful only when the CPU operates in external extension mode.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) P4 Operation Mode Register (P4MOD) <Address: H ’0080 0744> 123456 b 7b0 P44MD P45MD P46MD P47MD 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00

4 P44MD 0: P44 R W

Port P44 operation mode bit 1: CS0#

5 P45MD 0: P45 R W

Port P45 operation mode bit 1: CS1#

6 P46MD 0: P46 R W

Port P46 operation mode bit 1: A13

7 P47MD 0: P47 R W

Port P47 operation mode bit 1: A14 Note:  P4 Operation Mode Register is useful only when the CPU operates in external extension mode. P6 Operation Mode Register (P6MOD) <Address: H ’0080 0746> 123456 b 7b0 P65M D P66MD 0 00 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 0–4 No function assigned. Fix to "0". 00

5 P65MD 0: P65 R W

Port P65 operation mode bit 1: SCLKI4/SCLKO4

6 P66MD 0: P66 R W

Port P66 operation mode bit 1: SCLKI5/SCLKO5 7 No function assigned. Fix to "0". 00 Notes:  Port P60 is nonexistent.  P61–P63 and P67 are always input/output ports (single-function pins).  Port P64 is the SBI# input-only pin. The pin level can be known by reading the data register for P64.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) P7 Operation Mode Register (P7MOD) <Address: H ’0080 0747> 9 1 01 11 21 31 4 b 1 5b8 P70MD P71MD P72MD P73MD P74MD P75MD P76MD P77MD 00000000 <After reset: H’00> b Bit Name Function R W

8 P70MD 0: P70 R W

Port P70 operation mode bit 1: BCLK/WR#

9 P71MD 0: P71 R W

Port P71 operation mode bit 1: WAIT#

10 P72MD 0: P72 R W

Port P72 operation mode bit 1: HREQ#

11 P73MD 0: P73 R W

Port P73 operation mode bit 1: HACK#

12 P74MD 0: P74 R W

Port P74 operation mode bit 1: RTDTXD

13 P75MD 0: P75 R W

Port P75 operation mode bit 1: RTDRXD

14 P76MD 0: P76 R W

Port P76 operation mode bit 1: RTDACK

15 P77MD 0: P77 R W

Port P77 operation mode bit 1: RTDCLK P8 Operation Mode Register (P8MOD) <Address: H ’0080 0748> 123456 b 7b0 P82MD P83MD P84MD P85MD P86MD P87MD 0000000 0 <After reset: H’00> b Bit Name Function R W 0,1 No function assigned. Fix to "0". 00

2 P82MD 0: P82 R W

Port P82 operation mode bit 1: TXD0

3 P83MD 0: P83 R W

Port P83 operation mode bit 1: RXD0

4 P84MD 0: P84 R W

Port P84 operation mode bit 1: SCLKI0/SCLKO0

5 P85MD 0: P85 R W

Port P85 operation mode bit 1: TXD1

6 P86MD 0: P86 R W

Port P86 operation mode bit 1: RXD1

7 P87MD 0: P87 R W

Port P87 operation mode bit 1: SCLKI1/SCLKO1 Note:  Ports P80 and P81 are nonexistent.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) P9 Operation Mode Register (P9MOD) <Address: H ’0080 0749> 9 1 01 11 21 31 4 b 1 5b8 P93MD P94MD P95MD P96MD P97MD 000000 0 0 <After reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 P93MD 0: P93 R W

Port P93 operation mode bit 1: TO16

12 P94MD 0: P94 R W

Port P94 operation mode bit 1: TO17

13 P95MD 0: P95 R W

Port P95 operation mode bit 1: TO18

14 P96MD 0: P96 R W

Port P96 operation mode bit 1: TO19

15 P97MD 0: P97 R W

Port P97 operation mode bit 1: TO20 Note:  Ports P90–P92 are nonexistent. P10 Operation Mode Register (P10MOD) <Address: H ’0080 074A> 123456 b 7b0 P103MDP102MDP101MDP100MD P104MD P105MD P106MD P107MD 00000000 <After reset: H’00> b Bit Name Function R W

0 P100MD 0: P100 R W

Port P100 operation mode bit 1: TO8

1 P101MD 0: P101 R W

Port P101 operation mode bit 1: TO9/TXD3 (Note 1)

2 P102MD 0: P102 R W

Port P102 operation mode bit 1: TO10/CTX1 (Note 1)

3 P103MD 0: P103 R W

Port P103 operation mode bit 1: TO11

4 P104MD 0: P104 R W

Port P104 operation mode bit 1: TO12

5 P105MD 0: P105 R W

Port P105 operation mode bit 1: TO13

6 P106MD 0: P106 R W

Port P106 operation mode bit 1: TO14

7 P107MD 0: P107 R W

Port P107 operation mode bit 1: TO15 Note 1: These functions are selected using the P10 Peripheral Output Select Register.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) P11 Operation Mode Register (P11MOD) <Address: H ’0080 074B> 9 1 01 11 21 31 4 b 1 5b8 P113MDP112MDP111MDP110MD P114MD P115MD P116MD P117MD 00000000 <After reset: H’00> b Bit Name Function R W

8 P110MD 0: P110 R W

Port P110 operation mode bit 1: TO0

9 P111MD 0: P111 R W

Port P111 operation mode bit 1: TO1

10 P112MD 0: P112 R W

Port P112 operation mode bit 1: TO2

11 P113MD 0: P113 R W

Port P113 operation mode bit 1: TO3

12 P114MD 0: P114 R W

Port P114 operation mode bit 1: TO4

13 P115MD 0: P115 R W

Port P115 operation mode bit 1: TO5

14 P116MD 0: P116 R W

Port P116 operation mode bit 1: TO6

15 P117MD 0: P117 R W

Port P117 operation mode bit 1: TO7 P12 Operation Mode Register (P12MOD) <Address: H ’0080 074C> 123456 b 7b0 P124MD P125MD P126MD P127MD 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00

4 P124MD 0: P124 R W

Port P124 operation mode bit 1: TCLK0

5 P125MD 0: P125 R W

Port P125 operation mode bit 1: TCLK1

6 P126MD 0: P126 R W

Port P126 operation mode bit 1: TCLK2

7 P127MD 0: P127 R W

Port P127 operation mode bit 1: TCLK3 Note:  Ports P120–P123 are nonexistent.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) P13 Operation Mode Register (P13MOD) <Address: H ’0080 074D> 9 1 01 11 21 31 4 b 1 5b8 P133MDP132MDP131MDP130MD P134MD P135MD P136MD P137MD 00000000 <After reset: H’00> b Bit Name Function R W

8 P130MD 0: P130 R W

Port P130 operation mode bit 1: TIN16/PWMOFF0 (Note 1)

9 P131MD 0: P131 R W

Port P131 operation mode bit 1: TIN17/PWMOFF1 (Note 1)

10 P132MD 0: P132 R W

Port P132 operation mode bit 1: TIN18

11 P133MD 0: P133 R W

Port P133 operation mode bit 1: TIN19

12 P134MD 0: P134 R W

Port P134 operation mode bit 1: TIN20

13 P135MD 0: P135 R W

Port P135 operation mode bit 1: TIN21

14 P136MD 0: P136 R W

Port P136 operation mode bit 1: TIN22

15 P137MD 0: P137 R W

Port P137 operation mode bit 1: TIN23 Note 1: TIN and PWMOFF inputs both are enabled. P14 Operation Mode Register (P14MOD) <Address: H ’0080 074E> 123456 b 7b0 P144MD P145MD P146MD P147MDP140MD P141MD P142MD P143MD 00000000 <After reset: H’00> b Bit Name Function R W

0 P140MD 0: P140 R W

Port P140 operation mode bit 1: TIN8

1 P141MD 0: P141 R W

Port P141 operation mode bit 1: TIN9

2 P142MD 0: P142 R W

Port P142 operation mode bit 1: TIN10

3 P143MD 0: P143 R W

Port P143 operation mode bit 1: TIN11

4 P144MD 0: P144 R W

Port P144 operation mode bit 1: TIN12

5 P145MD 0: P145 R W

Port P145 operation mode bit 1: TIN13

6 P146MD 0: P146 R W

Port P146 operation mode bit 1: TIN14

7 P147MD 0: P147 R W

Port P147 operation mode bit 1: TIN15

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) P15 Operation Mode Register (P15MOD) <Address: H ’0080 074F> 9 1 01 11 21 31 4 b 1 5b8 P153MDP152MDP151MDP150MD P154MD P155MD P156MD P157MD 00000000 <After reset: H’00> b Bit Name Function R W

8 P150MD 0: P150 R W

Port P150 operation mode bit 1: TIN0

9 P151MD 0: P151 R W

Port P151 operation mode bit 1: TIN1

10 P152MD 0: P152 R W

Port P152 operation mode bit 1: TIN2

11 P153MD 0: P153 R W

Port P153 operation mode bit 1: TIN3

12 P154MD 0: P154 R W

Port P154 operation mode bit 1: TIN4

13 P155MD 0: P155 R W

Port P155 operation mode bit 1: TIN5

14 P156MD 0: P156 R W

Port P156 operation mode bit 1: TIN6

15 P157MD 0: P157 R W

Port P157 operation mode bit 1: TIN7 P16 Operation Mode Register (P16MOD) <Address: H ’0080 0750> 123456 b 7b0 P164MD P165MD P166MD P167MDP160MD P161MD P162MD P163MD 00000000 <After reset: H’00> b Bit Name Function R W

0 P160MD 0: P160 R W

Port P160 operation mode bit 1: TO21

1 P161MD 0: P161 R W

Port P161 operation mode bit 1: TO22

2 P162MD 0: P162 R W

Port P162 operation mode bit 1: TO23

3 P163MD 0: P163 R W

Port P163 operation mode bit 1: TO24

4 P164MD 0: P164 R W

Port P164 operation mode bit 1: TO25

5 P165MD 0: P165 R W

Port P165 operation mode bit 1: TO26

6 P166MD 0: P166 R W

Port P166 operation mode bit 1: TO27

7 P167MD 0: P167 R W

Port P167 operation mode bit 1: TO28

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) P17 Operation Mode Register (P17MOD) <Address: H ’0080 0751> 9 1 01 11 21 31 4 b 1 5b8 P173MDP172MD P174MD P175MD P176MD P177MD 0000000 0 <After reset: H’00> b Bit Name Function R W 8,9 No function assigned. Fix to "0". 00

10 P172MD 0: P172 R W

Port P172 operation mode bit 1: TIN24

11 P173MD 0: P173 R W

Port P173 operation mode bit 1: TIN25

12 P174MD 0: P174 R W

Port P174 operation mode bit 1: TXD2

13 P175MD 0: P175 R W

Port P175 operation mode bit 1: RXD2

14 P176MD 0: P176 R W

Port P176 operation mode bit 1: TXD3

15 P177MD 0: P177 R W

Port P177 operation mode bit 1: RXD3 Note:  Ports P170 and P171 are nonexistent. P18 Operation Mode Register (P18MOD) <Address: H ’0080 0752> 123456 b 7b0 P184MD P185MD P186MD P187MDP180MD P181MD P182MD P183MD 00000000 <After reset: H’00> b Bit Name Function R W

0 P180MD 0: P180 R W

Port P180 operation mode bit 1: TO29

1 P181MD 0: P181 R W

Port P181 operation mode bit 1: TO30

2 P182MD 0: P182 R W

Port P182 operation mode bit 1: TO31

3 P183MD 0: P183 R W

Port P183 operation mode bit 1: TO32

4 P184MD 0: P184 R W

Port P184 operation mode bit 1: TO33

5 P185MD 0: P185 R W

Port P185 operation mode bit 1: TO34

6 P186MD 0: P186 R W

Port P186 operation mode bit 1: TO35

7 P187MD 0: P187 R W

Port P187 operation mode bit 1: TO36

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) P19 Operation Mode Register (P19MOD) <Address: H ’0080 0753> 9 1 01 11 21 31 4 b 1 5b8 P193MDP192MDP191MDP190MD P194MD P195MD P196MD P197MD 00000000 <After reset: H’00> b Bit Name Function R W

8 P190MD 0: P190 R W

Port P190 operation mode bit 1: TIN26

9 P191MD 0: P191 R W

Port P191 operation mode bit 1: TIN27

10 P192MD 0: P192 R W

Port P192 operation mode bit 1: TIN28

11 P193MD 0: P193 R W

Port P193 operation mode bit 1: TIN29

12 P194MD 0: P194 R W

Port P194 operation mode bit 1: TIN30

13 P195MD 0: P195 R W

Port P195 operation mode bit 1: TIN31

14 P196MD 0: P196 R W

Port P196 operation mode bit 1: TIN32

15 P197MD 0: P197 R W

Port P197 operation mode bit 1: TIN33/PWMOFF2 (Note 1) Note 1: TIN and PWMOFF inputs both are enabled. P20 Operation Mode Register (P20MOD) <Address: H ’0080 0754> 123456 b 7b0 P200MD P201MD P202MD P203MD 0000 0 0 0 0 <After reset: H’00> b Bit Name Function R W

0 P200MD 0: P200 R W

Port P200 operation mode bit 1: TXD4

1 P201MD 0: P201 R W

Port P201 operation mode bit 1: RXD4

2 P202MD 0: P202 R W

Port P202 operation mode bit 1: TXD5

3 P203MD 0: P203 R W

Port P203 operation mode bit 1: RXD5 4–7 No function assigned. Fix to "0". 00 Note:  Ports P204–P207 are nonexistent.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) P21 Operation Mode Register (P21MOD) <Address: H ’0080 0755> 9 1 01 11 21 31 4 b 1 5b8 P213MDP212MDP211MDP210MD P214MD P215MD P216MD P217MD 00000000 <After reset: H’00> b Bit Name Function R W

8 P210MD 0: P210 R W

Port P210 operation mode bit 1: TO37

9 P211MD 0: P211 R W

Port P211 operation mode bit 1: TO38

10 P212MD 0: P212 R W

Port P212 operation mode bit 1: TO39

11 P213MD 0: P213 R W

Port P213 operation mode bit 1: TO40

12 P214MD 0: P214 R W

Port P214 operation mode bit 1: TO41

13 P215MD 0: P215 R W

Port P215 operation mode bit 1: TO42

14 P216MD 0: P216 R W

Port P216 operation mode bit 1: TO43

15 P217MD 0: P217 R W

Port P217 operation mode bit 1: TO44 P22 Operation Mode Register (P22MOD) <Address: H ’0080 0756> 123456 b 7b0 P220MD P222MD P223MD P224MD P225MD P226MD P227MD 0 000000 0 <After reset: H’00> b Bit Name Function R W

0 P220MD 0: P220 R W

Port P220 operation mode bit 1: CTX0 1 No function assigned. Fix to "0". 00

2 P222MD 0: P222 R W

Port P222 operation mode bit 1: CTX1

3 P223MD 0: P223 R W

Port P223 operation mode bit 1: CRX1

4 P224MD 0: P224 R W

Port P224 operation mode bit (Note 1) 1: A11/CS2# (Note 2)

5 P225MD 0: P225 R W

Port P225 operation mode bit (Note 1) 1: A12/CS3# (Note 2)

6 P226MD 0: P226 R W

Port P226 operation mode bit (Note 1) 1: CS2#

7 P227MD 0: P227 R W

Port P227 operation mode bit (Note 1) 1: CS3# Note 1: Port P224–P227 operation mode bits are useful only when the CPU operates in external extension mode. Note 2: These functions are selected using the P22 Peripheral Output Select Register. Note:  P221 is the CAN input-only pin.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0)

8.3.4 Port Peripheral Output Select Registers

P10 Peripheral Output Select Register (P10SMOD) <Address: H ’0080 076A> 123456 b 7b0 P101 SMD P102 SM D 0 0 0 0 0 0 00 <After reset: H’00> b Bit Name Function R W 0 No function assigned. Fix to "0". 00

1 P101SMD 0: TO9 R W

Port P101 peripheral output select mode bit 1: TXD3

2 P102SMD 0: TO10 R W

Port P102 peripheral output select mode bit 1: CTX1 3–7 No function assigned. Fix to "0". 00 P22 Peripheral Output Select Register (P22SMOD) <Address: H ’0080 0776> 123456 b 7b0 P224 SM D P225 SM D 0 0 0 00 0 0 0 <After reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00

4 P224SMD 0: A11 R W

Port P224 peripheral output select mode bit 1: CS2#

5 P225SMD 0: A12 R W

Port P225 peripheral output select mode bit 1: CS3# 6–7 No function assigned. Fix to "0". 00

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0)

8.3.5 Port Input Special Function Control Register

Port Input Special Function Control Register (PICNT) <Address: H ’0080 0745> 9 1 01 11 21 31 4 b 1 5b8 PIEN0PISELXSTA T 0 000 0 0 0 0 <After reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 XSTAT 0: XIN oscillating R (Note 1)

XIN oscillation status bit 1: XIN inactive 12–13 No function assigned. Fix to "0". 00

14 PISEL 0: Content of port output latch R W

Port input data select bit 1: Port pin level

15 PIEN0 0: Disable input R W

Port input enable bit 1: Enable input Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. (1) XSTAT (XIN oscillation status) bit (Bit 11) 1) Conditions under which XSTAT is set to "1" XSTAT is set to "1" upon detecting that XIN oscillation has stopped. When XIN remains at the same level for a predetermined time (3 BCLK periods up to 4 BCLK periods), XIN oscillation is assumed to have stopped. When operating normally, XIN changes state (high or low) once every BCLK period. 2) Conditions under which XSTAT is cleared to "0" XSTAT is cleared to "0" by a system reset or by writing "0". If XSTAT is cleared at the same time it is set in (1) above, the former has priority. Writing "1" to XSTAT is ignored. 3) Method for using XSTAT to detect XIN oscillation stoppage Because the M32R/ECU internally contains a PLL, the internal clock remains active even when XIN oscilla- tion has stopped. By reading XSTAT without clearing it never once after reset, it is possible to know whether XIN has ever stopped since the reset signal was deasserted. Similarly, by reading XSTAT after clearing it by writing "0", it is possible to know the current oscillating status of XIN. (However, there must be an interval of at least 5 BCLK periods (20 CPU clock periods) between read and write.)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) (1) To know whether XIN oscillation has ever stopped after being reset Write XSTAT = 0 (2) To know the current status of XIN oscillation Wait for 20 CPU clock periods or more Read XSTAT Wait before inspecting XSTAT Figure 8.3.1 Procedure for Setting XSTAT (2) PISEL (Port input data select) bit (Bit 14) When the Port Direction Register is set for output, this bit selects the target data to be read from the Port Data Register. This bit is unaffected by the Port Operation Mode Register. Table 8.3.1 PISEL Bit Settings and the Target Data To Be Read from the Port Data Register Direction Register PISEL Settings Target Data to Be Read 0 (input) 0/1 Port pin level 1 (output) 0 Port output latch

1 Port pin level

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) (3) PIEN0 (Port input enable) bit (Bit 15) This bit is used to prevent current from flowing into the port input pins. Because the input/output ports are disabled against input after reset, if any ports need to be used in input mode they must be enabled for input by setting this bit to "1". When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a low-level input applied. Consequently, if a peripheral input function is selected for any port (uncontrolled pin) while disabled against input by using the Port Operation Mode Register, the port may operate unexpect- edly due to the low-level input on it. The following shows the procedure for selecting a peripheral input function. (1) Enable the port for input when its pin level is valid (high or low) (2) Select a function using the port operation mode bit During boot mode, the pins shared with serial I/O functions are enabled for input and can therefore be protected against current flowing in from the pins other than serial I/O functions during flash programming by clearing PIEN0. The table below lists the pins that can be controlled by the PIEN0 bit in each operation mode. Table 8.3.2 Pins Controllable by PIEN0 Bit Mode Name Controllable Pins Uncontrolled Pins P00–P07, P10–P17, P20–P27 P221, P223, P30–P37, P41–P47, P61–P63 FP, MOD0, MOD1, SBI#, RESET# Single-chip P65 –P67, P70–P77, P82–P87 P93–P97, P100–P107, P110–P117 P124–P127, P130–P137, P140–P147 P150–P157, P160–P167, P172–P177 P180–P187, P190–P197, P200–P203 P210–P217, P220–P222, P224–P227 P61–P63, P65–P67, P70–P77 P00 –P07, P10–P17 P82–P87, P93–P97, P100–P107 P20 –P27, P30–P37 External extension P110 –P117, P124–P127, P130–P137 P41 –P47, P221, P223–P227 Microprocessor P140 –P147, P150–P157, P160–P167 FP, MOD0, MOD1, SBI#, RESET# P172–P177, P180–P187, P190–P197 P200–P203, P210–P217, P220 P222 P00–P07, P10–P17, P20–P27 P65, P66, P82 –P87, P101 P30–P37, P41–P47, P61–P63 P135 –P136, P174–P177, P200–P203 Boot P67, P70 –P77, P93–P97 P221, P223, (single-chip) P100, P102 –P107, P110–P117, P124–P127 FP, MOD0, MOD1, SBI#, RESET# P130–P134, P137, P140–P147, P150–P157 P160–P167, P172–P173, P180–P187 P190–P197, P210–P217, P220 P222, P224–P227

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) The port input level switching function allows the port threshold to be switched to one of three voltage levels (with or without Schmitt as selected) in units of the following port group. Group 0: P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P70–P73, P224-P227 Group 1: P65–P67, P82–P87, P172–P177 Group 2: P160–P167, P210–P217 Group 3: P93–P97, P110–P117 Group 4: P124–P127, P140–P147, P190–P197 Group 5: P61–P63, SBI# Group 6: P74–P77, P180–P187, P100–P107 Group 7: P136, P220–P223 Group 8: P130–P135, P137, P150–P157, P200–P203 Figure 8.4.1 Port Input Level Switching Groups P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 P173/TIN25 P172/TIN24 FP MOD0 MOD1 EXCVDD VSS EXCVCC VDDE VSS VCCE VCC-BUS P17/DB15 P16/DB14 P15/DB13 P14/DB12 P13/DB11 P12/DB10 P11/DB9 P10/DB8 P07/DB7 P06/DB6 P05/DB5 P04/DB4 P03/DB3 P02/DB2 P01/DB1 P00/DB0 VSS P73/HACK# P72/HREQ# P71/WAIT# P70/BCLK/WR# P43/RD# P42/BHW#/BHE# P41/BLW#/BLE# VCC-BUS VSS AD1IN15 AD1IN14 AD1IN13 AD1IN12 AD1IN11 AD1IN10 AD1IN9 AD1IN8 AVSS1 AD1IN7 AD1IN6 AD1IN5 AD1IN4 AD1IN3 AD1IN2 AD1IN1 AD1IN0 VREF1 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P65/SCLKI4/SCLKO4 P66/SCLKI5/SCLKO5 P67 P210/TO37 P211/TO38 P212/TO39 P213/TO40 P214/TO41 P215/TO42 P216/TO43 P217/TO44 P160/TO21 P161/TO22 P162/TO23 P163/TO24 P164/TO25 P165/TO26 P166/TO27 P167/TO28 VSS VCCE VCC-BUS P226/CS2# P227/CS3# P44/CS0# P45/CS1# P224/A11/CS2# P225/A12/CS3# P46/A13 P47/A14 P30/A15 P31/A16 P32/A17 P33/A18 P34/A19 P35/A20 P36/A21 P37/A22 VSS P20/A23 P21/A24 P22/A25 P23/A26 P24/A27 P25/A28 P26/A29 P27/A30 VCC-BUS VSS VCCE P93/TO16 P94/TO17 P95/TO18 P96/TO19 M32180F8VFP M32180F8TFP 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 AVCC1 VSS VCCE P150/TIN0 P151/TIN1 P152/TIN2 P153/TIN3 P154/TIN4 P155/TIN5 P156/TIN6 P157/TIN7 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 P130/TIN16/PWMOFF0 P131/TIN17/PWMOFF1 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21 P136/TIN22 P137/TIN23 P220/CTX0 P221/CRX0 P222/CTX1 P223/CRX1 VCCE OSC-VSS VCNT OSC-VCC XIN OSC-VSS XOUT RESET# P180/TO29 P181/TO30 P182/TO31 P183/TO32 P184/TO33 P185/TO34 P186/TO35 P187/TO36 P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTDI JTDO JTRST JTCK JTMS P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1 P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15 P97/TO20 P117/TO7 P116/TO6 P115/TO5 P114/TO4 P113/TO3 P112/TO2 P111/TO1 P110/TO0 P147/TIN15 P146/TIN14 P145/TIN13 P144/TIN12 P143/TIN11 P142/TIN10 P141/TIN9 P140/TIN8 P197/TIN33/PWMOFF2 P196/TIN32 P195/TIN31 P194/TIN30 P193/TIN29 P192/TIN28 P191/TIN27 P190/TIN26 P127/TCLK3 P126/TCLK2 P125/TCLK1 P124/TCLK0 EXCVCC VSS VCCE VSS VSS VSS SBI# P63 P62 P61 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AVSS0 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 VREF0 AVCC0 VSS VCCE Port group 0 Port group 0 Port group 8 Port group 7 Port group 8 Port group 7 Port group 6 Port group 6 Port group 3 Port group 4 Port group 5 Port group 1 Port group 2 Port group 0 Port group 0

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) Port Group 0,1 Input Level Setting Register (PG01LEV) <Address: H ’0080 0760> 123456 b 7b0 WF0SEL PT0SEL VT0SEL0 VT0SEL1 WF1SEL PT1SEL VT1SEL0 VT1SEL1 00010001 Port Group 2,3 Input Level Setting Register (PG23LEV) <Address: H ’0080 0761> 9 1 01 11 21 31 4 b 1 5b8 WF2SEL PT2SEL VT2SEL0 VT2SEL1 WF3SEL PT3SEL VT3SEL0 VT3SEL1 00010001 Port Group 4,5 Input Level Setting Register (PG45LEV) <Address: H ’0080 0762> 123456 b 7b0 WF4SEL PT4SEL VT4SEL0 VT4SEL1 WF5SEL PT5SEL VT5SEL0 VT5SEL1 00010001 Port Group 6,7 Input Level Setting Register (PG67LEV) <Address: H ’0080 0763> 9 1 01 11 21 31 4 b 1 5b8 WF6SEL PT6SEL VT6SEL0 VT6SEL1 WF7SEL PT7SEL VT7SEL0 VT7SEL1 00010001 Port Group 8 Input Level Setting Register (PG8LEV) <Address: H ’0080 0764> 123456 b 7b0 WF8SEL PT8SEL VT8SEL0 VT8SEL1 0001 0 0 0 0 Note:  The PG8LEV register bits 4–7 have no functions assigned. <After reset: B’0001> b Bit Name Function R W 0(4) WFnSEL 0: Select standard input for each pin R W 8(12) Group n dual-function input select bit 1: Select threshold switching function 1(5) PTnSEL 0: Select CMOS input R W 9(13) Group n port input select bit 1: Select Schmitt input 2–3 VTnSEL <When PTnSEL = "0" (CMOS input selected)> R W (6–7) Group n input threshold select bit 00: Select 0.35 VCCE 10–11 01: Select 0.5 VCCE (14–15) 10: Select 0.7 VCCE 11: Settings inhibited <When PTnSEL = "1" (Schmitt input selected)> 00: VT+ = 0.5 VCCE VT– = 0.35 VCCE 01: Settings inhibited 10: VT+ = 0.7 VCCE VT– = 0.35 VCCE 11: VT+ = 0.7 VCCE VT– = 0.5VCCE Note:  The following ports operate with the VCC-BUS power supply, and not with the VCCE power supply. Therefore, the reference voltages for these ports are the VCC-BUS input voltage. P00 –P07, P10–P17, P20–P27, P30–P37, P41–P47, P70–P73, P224–P227

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) Figure 8.4.2 Port Level Switching Function 0.7VCCE 0.5VCCE 0.35VCCE CMOS S S S S S WFnSEL PTnSEL VTnSELL Threshold Input function enable Standard input level for each peripheral function pin

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) Figures 8.5.1 through 8.5.4 show the peripheral circuit diagrams of the input/output ports described in the preced- ing pages. Figure 8.5.1 Port Peripheral Circuit Diagram (1) Data bus Operation mode register Input function enable Peripheral function input Port output latch Direction register Input data select bit Port level switching function (Standard: peripheral TTL) P44(CS0#) P45(CS1#) P70(BCLK/WR#) P82(TXD0) P85(TXD1) P93–P97(TO16–TO20) P100(TO8) P103–P107(TO11–TO15) P110–P117(TO0–TO7) P166, P167(TO27, TO28) P174(TXD2) P176(TXD3) P186, P187(TO35, TO36) P200(TXD4) P202(TXD5) P216, P217(TO43, TO44) P220(CTX0) P222(CTX1) P226(CS2#) P227(CS3#) P00–P07(DB0 –DB7) P10–P17(DB8 –DB15) P20–P27(A23–A30) P30–P37(A15–A22) P46, P47(A13, A14) P71(WAIT#) P73(HACK#) P74(RTDTXD) P76(RTDACK) P224(A11/CS2#) P225(A12/CS3#) (Note 1) Data bus Operation mode register Input function enable Peripheral function input Port output latch Direction register Input data select bit Port level switching function (No peripheral input) (Note 1) Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Notes:  During processor mode, P00-P07, P10-P17, P20-P27, P30-P37, P45-P47, P224, and P225 are external bus interface control signal pins, but their functional description in this block diagram is omitted.  Although P224 and P225 serve triple functions, their functional description in this block diagram is omitted.  The circle denotes a pin.  The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage.  The input capacitance of each pin is approximately 10 pF .

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) Figure 8.5.2 Port Peripheral Circuit Diagram (2) function (Standard: peripheral Schmitt) P72(HREQ#) P75(RTDRXD) P77(RTDCLK) P83(RXD0) P86(RXD1) P124–P127(TCLK0 –TCLK3) P132–P137(TIN18–TIN23) P140–P147(TIN8–TIN15) P150–P157(TIN0–TIN7) P172, P173(TIN24, TIN25) P175(RXD2) P177(RXD3) P190, P196(TIN26, TIN32) P201(RXD4) P203(RXD5) P223(CRX1) (Note 1) Data bus Port level switching function (No peripheral input) (Note 1) Peripheral output select register Peripheral function output 1 Peripheral function output 2 P101(TO9/TXD3) P102(TO10/CTX1) Data bus Peripheral function input 1 Port level switching function (Standard: peripheral Schmitt) P130(TIN16/PWMOFF0) P131(TIN17/PWMOFF1) P197(TIN33/PWMOFF2) (Note 1) Peripheral function input 2 Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Notes: P223 is an input mode-only port.  The circle denotes a pin.  The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage.  The input capacitance of each pin is approximately 10 pF . Operation mode register Input function enable Port output latch Direction register Input data select bit Operation mode register Input function enable Port output latch Direction register Input data select bit Operation mode register Input function enable Port output latch Direction register Input data select bit

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) function (Standard: peripheral Schmitt) Port level switching function (No peripheral input) P65(SCLKI4/SCLKO4) P66(SCLKI5/SCLKO5) P84(SCLKI0/SCLKO0) P87(SCLKI1/SCLKO1) P41(BLW#/BLE#) P42(BHW#/BHE#) P43(RD#) P61–P63 P67 Data bus (Note 1) (Note 1) P160–P165(TO21–TO26) P180–P185(TO29–TO34) P210–P215(TO37–TO42) Data bus Operation mode register Input function enable Peripheral function output Port output latch Direction register Input data select bit Port level switching function (No peripheral input) (Note 1) PWM output disable Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Notes:  During processor and external extension modes, P41-P43 are external bus interface control signal pins, but their functional description in this block diagram is omitted.  The circle denotes a pin.  The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage.  The input capacitance of each pin is approximately 10 pF . Input function enable Port output latch Direction register Input data select bit Port output latch Direction register Input function enable Operation mode register Figure 8.5.3 Port Peripheral Circuit Diagram (3)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) OSC-VCC, VCCE, VDDE VCC-BUS, EXCVCC, EXCVDD MOD0, MOD1 FP JTDI, JTCK, JTMS JTDO RESET#, XIN, JTRST Output control SBI# P221(CRX0) Data bus (DB0–DB15) SBI#, CRX0 Notes:  The circle denotes a pin.  The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. Figure 8.5.4 Port Peripheral Circuit Diagram (4)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0)  When using input/output ports in output mode Because the value of the Port Data Register is undefined after reset, the Port Data Register must have its initial value set in it before the Port Direction Register can be set for output. Conversely, if the Port Direction Register is set for output before setting data in the Port Data Register, the Port Data Register outputs an undefined value until any data is written into it.  About the port input disable function Because the input/output ports are disabled against input after reset, they must be enabled for input by setting the Port Input Enable (PIEN0) bit to "1" before their input functions can be used. When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a low-level input applied. Consequently, if a peripheral input function is selected for any port (uncontrolled pin) while disabled against input by using the Port Operation Mode Register, the port may operate unexpectedly due to the low-level input on it.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 32180 Group User’s Manual (Rev.1.0) This page is blank for reasons of layout.

9.1 Outline of the DMAC

9.2 DMAC Related Registers

9.3 Functional Description of the DMAC

9.4 Precautions about the DMAC

32180 Group User’s Manual (Rev.1.0) The microcomputer internally contains a 10-channel DMAC (Direction Memory Access Controller). It allows data to be transferred at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, or between internal RAMs, as initiated by a software trigger or requested from an internal peripheral I/O. Table 9.1.1 Outline of the DMAC Item Description Number of channels 10 channels Transfer request sources  Software trigger  Request from internal peripheral I/Os: A-D converter, multijunction timer, serial I/O (reception completed, transmit buffer empty) or CAN  DMA channels can be cascaded (Note 1) Maximum number of 65,536 times times transferred Transferable address  64 Kbytes (address space from H’0080 0000 to H’0080 FFFF) space  Transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs are supported. Transfer data size 16 or 8 bits Transfer method Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual- address transfer Transfer mode Single transfer mode Direction of transfer One of three modes can be selected for the source and destination:  Address fixed  Address incremental  Ring buffered Channel priority DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9 (Priority is fixed) Maximum transfer rate 13.3 Mbytes per second (when internal peripheral clock BCLK = 20 MHz) Interrupt request Group interrupt request can be generated when each transfer count register underflows. Transfer area 64 Kbytes from H’0080 0000 to H’0080 FFFF (Transferable in the entire RAM/SFR area) Note 1: The DMA channels can be cascaded in the manner described below.  Start DMA transfer on DMA1 upon completion of one DMA transfer on DMA0  Start DMA transfer on DMA5 upon completion of all DMA transfers on DMA0 (upon underflow of the transfer count register)  Start DMA transfer on DMA2 upon completion of one DMA transfer on DMA1  Start DMA transfer on DMA0 upon completion of one DMA transfer on DMA2  Start DMA transfer on DMA3 upon completion of one DMA transfer on DMA2  Start DMA transfer on DMA4 upon completion of one DMA transfer on DMA3  Start DMA transfer on DMA6 upon completion of one DMA transfer on DMA5  Start DMA transfer on DMA7 upon completion of one DMA transfer on DMA6  Start DMA transfer on DMA5 upon completion of one DMA transfer on DMA7  Start DMA transfer on DMA8 upon completion of one DMA transfer on DMA7  Start DMA transfer on DMA9 upon completion of one DMA transfer on DMA8

9-3 32180 Group User’s Manual (Rev.1.0) Figure 9.1.1 Block Diagram of the DMAC S S S S S S S S S S S DMA0 udf end DMA1 udf end DMA2 udf end DMA3 udf end DMA4 udf end DMA5 udf end DMA6 udf end DMA7 udf end DMA8 udf end DMA9 udf end S S S S S S S S S AD0 conversion completed TIO8_udf TIN0S TID0_udf/ovf CAN0_S0/S15 TIN3S TID1_udf/ovf AD0 conversion completed TIO8_udf Software start TIN13S Software start TIN18S Software start SIO0_TXD SIO1_RXD Software start SIO0_RXD Software start Software start DMA0 –4 interrupt DMA5 –9 interrupt SIO2_RXD SIO1_TXD TIN1S Software start SIO2_TXD TIN2S Software start SIO3_RXD Software start SIO3_TXD TIN8S Software start CAN0_S1/S14 TID2_udf/ovf TIN0S AD1 conversion completed TIN19S SIO0_TXD TOU1_7irq TIN20S TOU0_0irq TOU2_7irq TOU0_1irq SIO1_RXD SIO3_TXD TOU0_2irq TOU0_6irq TIN7S AD1 conversion completed TOU0_7irq 0123 Input event bus Output event bus 3210 3210 0123

32180 Group User’s Manual (Rev.1.0) The diagram below shows a memory map of the DMAC related registers. DMAC Related Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0400 DMA0 –4 Interrupt Request Status Register DMA0 –4 Interrupt Request Mask Register 9-24 (DM04ITST) (DM04ITMK) 9-25 (Use inhibited area) H'0080 0408 DMA5 –9 Interrupt Request Status Register DMA5 –9 Interrupt Request Mask Register 9-24 (DM59ITST) (DM59ITMK) 9-25 (Use inhibited area) H'0080 0410 DMA0 Channel Control Register 0 DMA0 Channel Control Register 1 9-6 (DM0CNT0) (DM0CNT1) H'0080 0412 DMA0 Source Address Register 9-19 (DM0SA) H'0080 0414 DMA0 Destination Address Register 9-20 (DM0DA) H'0080 0416 DMA0 Transfer Count Register 9-21 (DM0TCT) H'0080 0418 DMA5 Channel Control Register 0 DMA5 Channel Control Register 1 9-11 (DM5CNT0) (DM5CNT1) H'0080 041A DMA5 Source Address Register 9-19 (DM5SA) H'0080 041C DMA5 Destination Address Register 9-20 (DM5DA) H'0080 041E DMA5 Transfer Count Register 9-21 (DM5TCT) H'0080 0420 DMA1 Channel Control Register 0 DMA1 Channel Control Register 1 9-7 (DM1CNT0) (DM1CNT1) H'0080 0422 DMA1 Source Address Register 9-19 (DM1SA) H'0080 0424 DMA1 Destination Address Register 9-20 (DM1DA) H'0080 0426 DMA1 Transfer Count Register 9-21 (DM1TCT) H'0080 0428 DMA6 Channel Control Register 0 DMA6 Channel Control Register 1 9-12 (DM6CNT0) (DM6CNT1) H'0080 042A DMA6 Source Address Register 9-19 (DM6SA) H'0080 042C DMA6 Destination Address Register 9-20 (DM6DA) H'0080 042E DMA6 Transfer Count Register 9-21 (DM6TCT) H'0080 0430 DMA2 Channel Control Register 0 DMA2 Channel Control Register 1 9-8 (DM2CNT0) (DM2CNT1) H'0080 0432 DMA2 Source Address Register 9-19 (DM2SA) H'0080 0434 DMA2 Destination Address Register 9-20 (DM2DA) H'0080 0436 DMA2 Transfer Count Register 9-21 (DM2TCT) H'0080 0438 DMA7 Channel Control Register 0 DMA7 Channel Control Register 1 9-13 (DM7CNT0) (DM7CNT1) H'0080 043A DMA7 Source Address Register 9-19 (DM7SA) H'0080 043C DMA7 Destination Address Register 9-20 (DM7DA) H'0080 043E DMA7 Transfer Count Register 9-21 (DM7TCT)

9-5 32180 Group User’s Manual (Rev.1.0) DMAC Related Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0440 DMA3 Channel Control Register 0 DMA3 Channel Control Register 1 9-9 (DM3CNT0) (DM3CNT1) H'0080 0442 DMA3 Source Address Register 9-19 (DM3SA) H'0080 0444 DMA3 Destination Address Register 9-20 (DM3DA) H'0080 0446 DMA3 Transfer Count Register 9-21 (DM3TCT) H'0080 0448 DMA8 Channel Control Register 0 DMA8 Channel Control Register 1 9-14 (DM8CNT0) (DM8CNT1) H'0080 044A DMA8 Source Address Register 9-19 (DM8SA) H'0080 044C DMA8 Destination Address Register 9-20 (DM8DA) H'0080 044E DMA8 Transfer Count Register 9-21 (DM8TCT) H'0080 0450 DMA4 Channel Control Register 0 DMA4 Channel Control Register 1 9-10 (DM4CNT0) (DM4CNT1) H'0080 0452 DMA4 Source Address Register 9-19 (DM4SA) H'0080 0454 DMA4 Destination Address Register 9-20 (DM4DA) H'0080 0456 DMA4 Transfer Count Register 9-21 (DM4TCT) H'0080 0458 DMA9 Channel Control Register 0 DMA9 Channel Control Register 1 9-15 (DM9CNT0) (DM9CNT1) H'0080 045A DMA9 Source Address Register 9-19 (DM9SA) H'0080 045C DMA9 Destination Address Register 9-20 (DM9DA) H'0080 045E DMA9 Transfer Count Register 9-21 (DM9TCT) H'0080 0460 DMA0 Software Request Generation Register 9-18 (DM0SRI) H'0080 0462 DMA1 Software Request Generation Register 9-18 (DM1SRI) H'0080 0464 DMA2 Software Request Generation Register 9-18 (DM2SRI) H'0080 0466 DMA3 Software Request Generation Register 9-18 (DM3SRI) H'0080 0468 DMA4 Software Request Generation Register 9-18 (DM4SRI) (Use inhibited area) H'0080 0470 DMA5 Software Request Generation Register 9-18 (DM5SRI) H'0080 0472 DMA6 Software Request Generation Register 9-18 (DM6SRI) H'0080 0474 DMA7 Software Request Generation Register 9-18 (DM7SRI) H'0080 0476 DMA8 Software Request Generation Register 9-18 (DM8SRI) H'0080 0478 DMA9 Software Request Generation Register 9-18 (DM9SRI)

32180 Group User’s Manual (Rev.1.0)

9.2.1 DMA Channel Control Registers

DMA0 Channel Control Register 0 (DM0CNT0) <Address: H ’0080 0410> 123456 b 7b0 SADSL0 DADSL0MDSEL0 TREQF0 REQSL0 TENL0 TSZSL0 000000 00 <After reset: H’00> b Bit Name Function R W

0 MDSEL0 0: Normal mode R W

DMA0 transfer mode select bit 1: Ring buffer mode

1 TREQF0 0: Transfer not requested R(Note 1)

DMA0 transfer request flag bit 1: Transfer requested 2, 3 REQSL0 00: Software start or one DMA2 transfer completed R W DMA0 transfer request source select bit 01: A-D0 conversion completed 10: MJT (TIO8_udf) 11: Extended DMA0 transfer request source select (DMA0 Channel Control Register 1)

4 TENL0 0: Disable transfer R W

DMA0 transfer enable bit 1: Enable transfer

5 TSZSL0 0: 16 bits R W

DMA0 transfer size select bit 1: 8 bits

6 SADSL0 0: Fixed R W

DMA0 source address direction select bit 1: Increment

7 DADSL0 0: Fixed R W

DMA0 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA0 Channel Control Register 1 (DM0CNT1) <Address: H ’0080 0411> 9 1 01 11 21 31 4 b 1 5b8 REQESEL0 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12–15 REQESEL0 0000: MJT (input event bus 2) R W Extended DMA0 transfer request source select bit 0001: MJT (TID0_udf/ovf) 0010: CAN (CAN0_S0/S15) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited 1111: Settings inhibited | |

9-7 32180 Group User’s Manual (Rev.1.0) DMA1 Channel Control Register 0 (DM1CNT0) <Address: H ’0080 0420> 123456 b 7b0 SADSL1 DADSL1MDSEL1 TREQF1 REQSL1 TENL1 TSZSL1 000000 00 <After reset: H’00> b Bit Name Function R W

0 MDSEL1 0: Normal mode R W

DMA1 transfer mode select bit 1: Ring buffer mode

1 TREQF1 0: Transfer not requested R(Note 1)

DMA1 transfer request flag bit 1: Transfer requested 2, 3 REQSL1 00: Software start R W DMA1 transfer request source select bit 01: MJT (output event bus 0) 10: MJT (TIN13S) 11: Extended DMA1 transfer request source select (DMA1 Channel Control Register 1)

4 TENL1 0: Disable transfer R W

DMA1 transfer enable bit 1: Enable transfer

5 TSZSL1 0: 16 bits R W

DMA1 transfer size select bit 1: 8 bits

6 SADSL1 0: Fixed R W

DMA1 source address direction select bit 1: Increment

7 DADSL1 0: Fixed R W

DMA1 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA1 Channel Control Register 1 (DM1CNT1) <Address: H ’0080 0421> 9 1 01 11 21 31 4 b 1 5b8 REQESEL1 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12–15 REQESEL1 0000: One DMA0 transfer completed R W Extended DMA1 transfer request source select bit 0001: MJT(TIN3S) 0010: MJT(TID1_udf/ovf) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited 1111: Settings inhibited | |

32180 Group User’s Manual (Rev.1.0) DMA2 Channel Control Register 0 (DM2CNT0) <Address: H ’0080 0430> 123456 b 7b0 SADSL2 DADSL2MDSEL2 TREQF2 REQSL2 TENL2 TSZSL2 00000000 <After reset: H’00> b Bit Name Function R W

0 MDSEL2 0: Normal mode R W

DMA2 transfer mode select bit 1: Ring buffer mode

1 TREQF2 0: Transfer not requested R(Note 1)

DMA2 transfer request flag bit 1: Transfer requested 2, 3 REQSL2 00: Software start R W DMA2 transfer request source select bit 01: MJT (output event bus 1) 10: MJT (TIN18S) 11: Extended DMA2 transfer request source select (DMA2 Channel Control Register 1)

4 TENL2 0: Disable transfer R W

DMA2 transfer enable bit 1: Enable transfer

5 TSZSL2 0: 16 bits R W

DMA2 transfer size select bit 1: 8 bits

6 SADSL2 0: Fixed R W

DMA2 source address direction select bit 1: Increment

7 DADSL2 0: Fixed R W

DMA2 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA2 Channel Control Register 1 (DM2CNT1) <Address: H ’0080 0431> 9 10 11 12 13 14 b15b8 REQESEL2 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12–15 REQESEL2 0000: One DMA1 transfer completed R W Extended DMA1 transfer request source select bit 0001: MJT(TID2_udf/ovf) 0010: CAN(CAN0_S1/S14) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited 1111: Settings inhibited | |

9-9 32180 Group User’s Manual (Rev.1.0) DMA3 Channel Control Register 0 (DM3CNT0) <Address: H ’0080 0440> 123456 b 7b0 SADSL3 DADSL3MDSEL3 TREQF3 REQSL3 TENL3 TSZSL3 00000000 <After reset: H’00> b Bit Name Function R W

0 MDSEL3 0: Normal mode R W

DMA3 transfer mode select bit 1: Ring buffer mode

1 TREQF3 0: Transfer not requested R(Note 1)

DMA3 transfer request flag bit 1: Transfer requested 2, 3 REQSL3 00: Software start R W DMA3 transfer request source select bit 01: SIO0_TXD (transmit buffer empty) 10: SIO1_RXD 11: Extended DMA3 transfer request source select (DMA3 Channel Control Register 1)

4 TENL3 0: Disable transfer R W

DMA3 transfer enable bit 1: Enable transfer

5 TSZSL3 0: 16 bits R W

DMA3 transfer size select bit 1: 8 bits

6 SADSL3 0: Fixed R W

DMA3 source address direction select bit 1: Increment

7 DADSL3 0: Fixed R W

DMA3 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA3 Channel Control Register 1 (DM3CNT1) <Address: H ’0080 0441> 9 10 11 12 13 14 b15b8 REQESEL3 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12–15 REQESEL3 0000: MJT(TIN0) R W Extended DMA3 transfer request source select bit 0001: One DMA2 transfer completed 0010: AD1 conversion completed 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited 1111: Settings inhibited | |

32180 Group User’s Manual (Rev.1.0) DMA4 Channel Control Register 0 (DM4CNT0) <Address: H ’0080 0450> 123456 b 7b0 SADSL4 DADSL4MDSEL4 TREQF4 REQSL4 TENL4 TSZSL4 00000000 <After reset: H’00> b Bit Name Function R W

0 MDSEL4 0: Normal mode R W

DMA4 transfer mode select bit 1: Ring buffer mode

1 TREQF4 0: Transfer not requested R(Note 1)

DMA4 transfer request flag bit 1: Transfer requested 2, 3 REQSL4 00: Software start R W DMA4 transfer request source select bit 01: One DMA3 transfer completed 10: SIO0_RXD 11: Extended DMA4 transfer request source select (DMA4 Channel Control Register 1)

4 TENL4 0: Disable transfer R W

DMA4 transfer enable bit 1: Enable transfer

5 TSZSL4 0: 16 bits R W

DMA4 transfer size select bit 1: 8 bits

6 SADSL4 0: Fixed R W

DMA4 source address direction select bit 1: Increment

7 DADSL4 0: Fixed R W

DMA4 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA4 Channel Control Register 1 (DM4CNT1) <Address: H ’0080 0451> 9 10 11 12 13 14 b15b8 REQESEL4 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12–15 REQESEL4 0000: MJT(TIN19S) R W Extended DMA4 transfer request source select bit 0001: SIO0_TXD (transmit buffer empty) 0010: MJT(TOU1_7irq) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited 1111: Settings inhibited | |

9-11 32180 Group User’s Manual (Rev.1.0) DMA5 Channel Control Register 0 (DM5CNT0) <Address: H ’0080 0418> 123456 b 7b0 SADSL5 DADSL5MDSEL5 TREQF5 REQSL5 TENL5 TSZSL5 00000000 <After reset: H’00> b Bit Name Function R W

0 MDSEL5 0: Normal mode R W

DMA5 transfer mode select bit 1: Ring buffer mode

1 TREQF5 0: Transfer not requested R(Note 1)

DMA5 transfer request flag bit 1: Transfer requested 2, 3 REQSL5 00: Software start or one DMA7 transfer completed R W DMA5 transfer request source select bit 01: All DMA0 transfers completed 10: SIO2_RXD 11: Extended DMA5 transfer request source select (DMA5 Channel Control Register 1)

4 TENL5 0: Disable transfer R W

DMA5 transfer enable bit 1: Enable transfer

5 TSZSL5 0: 16 bits R W

DMA5 transfer size select bit 1: 8 bits

6 SADSL5 0: Fixed R W

DMA5 source address direction select bit 1: Increment

7 DADSL5 0: Fixed R W

DMA5 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA5 Channel Control Register 1 (DM5CNT1) <Address: H ’0080 0419> 9 10 11 12 13 14 b15b8 REQESEL5 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12–15 REQESEL5 0000: MJT(TIN20S) R W Extended DMA5 transfer request source select bit 0001: MJT(TOU0_0irq) 0010: MJT(TOU2_7irq) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited 1111: Settings inhibited | |

32180 Group User’s Manual (Rev.1.0) DMA6 Channel Control Register 0 (DM6CNT0) <Address: H ’0080 0428> 123456 b 7b0 SADSL6 DADSL6MDSEL6 TREQF6 REQSL6 TENL6 TSZSL6 00000000 <After reset: H’00> b Bit Name Function R W

0 MDSEL6 0: Normal mode R W

DMA6 transfer mode select bit 1: Ring buffer mode

1 TREQF6 0: Transfer not requested R(Note 1)

DMA6 transfer request flag bit 1: Transfer requested 2, 3 REQSL6 00: Software start R W DMA6 transfer request source select bit 01: SIO1_TXD (transmit buffer empty) 10: MJT(TIN1S) 11: Extended DMA6 transfer request source select (DMA6 Channel Control Register 1)

4 TENL6 0: Disable transfer R W

DMA6 transfer enable bit 1: Enable transfer

5 TSZSL6 0: 16 bits R W

DMA6 transfer size select bit 1: 8 bits

6 SADSL6 0: Fixed R W

DMA6 source address direction select bit 1: Increment

7 DADSL6 0: Fixed R W

DMA6 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA6 Channel Control Register 1 (DM6CNT1) <Address: H ’0080 0429> 9 10 11 12 13 14 b15b8 REQESEL6 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12–15 REQESEL6 0000: One DMA5 transfer completed R W Extended DMA6 transfer request source select bit 0001: MJT(TOU0_1irq) 0010: SIO1_RXD 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited 1111: Settings inhibited | |

9-13 32180 Group User’s Manual (Rev.1.0) DMA7 Channel Control Register 0 (DM7CNT0) <Address: H ’0080 0438> 123456 b 7b0 SADSL7 DADSL7MDSEL7 TREQF7 REQSL7 TENL7 TSZSL7 00000000 <After reset: H’00> b Bit Name Function R W

0 MDSEL7 0: Normal mode R W

DMA7 transfer mode select bit 1: Ring buffer mode

1 TREQF7 0: Transfer not requested R(Note 1)

DMA7 transfer request flag bit 1: Transfer requested 2, 3 REQSL7 00: Software start R W DMA7 transfer request source select bit 01: SIO2_TXD (transmit buffer empty) 10: MJT(TIN2S) 11: Extended DMA7 transfer request source select (DMA7 Channel Control Register 1)

4 TENL7 0: Disable transfer R W

DMA7 transfer enable bit 1: Enable transfer

5 TSZSL7 0: 16 bits R W

DMA7 transfer size select bit 1: 8 bits

6 SADSL7 0: Fixed R W

DMA7 source address direction select bit 1: Increment

7 DADSL7 0: Fixed R W

DMA7 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA7 Channel Control Register 1 (DM7CNT1) <Address: H ’0080 0439> 9 10 11 12 13 14 b15b8 REQESEL7 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12–15 REQESEL7 0000: One DMA6 transfer completed R W Extended DMA7 transfer request source select bit 0001: MJT(TOU0_2irq) 0010: SIO3_TXD (transmit buffer empty) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited 1111: Settings inhibited | |

32180 Group User’s Manual (Rev.1.0) DMA8 Channel Control Register 0 (DM8CNT0) <Address: H ’0080 0448> 123456 b 7b0 SADSL8 DADSL8MDSEL8 TREQF8 REQSL8 TENL8 TSZSL8 00000000 <After reset: H’00> b Bit Name Function R W

0 MDSEL8 0: Normal mode R W

DMA8 transfer mode select bit 1: Ring buffer mode

1 TREQF8 0: Transfer not requested R(Note 1)

DMA8 transfer request flag bit 1: Transfer requested 2, 3 REQSL8 00: Software start R W DMA8 transfer request source select bit 01: MJT (input event bus 0) 10: SIO3_RXD 11: Extended DMA8 transfer request source select (DMA8 Channel Control Register 1)

4 TENL8 0: Disable transfer R W

DMA8 transfer enable bit 1: Enable transfer

5 TSZSL8 0: 16 bits R W

DMA8 transfer size select bit 1: 8 bits

6 SADSL8 0: Fixed R W

DMA8 source address direction select bit 1: Increment

7 DADSL8 0: Fixed R W

DMA8 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA8 Channel Control Register 1 (DM8CNT1) <Address: H ’0080 0449> 9 10 11 12 13 14 b15b8 REQESEL8 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12–15 REQESEL8 0000: MJT(TIN7S) R W Extended DMA8 transfer request source select bit 0001: MJT(TOU0_6irq) 0010: One DMA7 transfer completed 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited 1111: Settings inhibited | |

9-15 32180 Group User’s Manual (Rev.1.0) DMA9 Channel Control Register 0 (DM9CNT0) <Address: H ’0080 0458> 123456 b 7b0 SADSL9 DADSL9MDSEL9 TREQF9 REQSL9 TENL9 TSZSL9 00000000 <After reset: H’00> b Bit Name Function R W

0 MDSEL9 0: Normal mode R W

DMA9 transfer mode select bit 1: Ring buffer mode

1 TREQF9 0: Transfer not requested R(Note 1)

DMA9 transfer request flag bit 1: Transfer requested 2, 3 REQSL9 00: Software start R W DMA9 transfer request source select bit 01: SIO3_TXD (transmit buffer empty) 10: MJT(TIN8S) 11: Extended DMA9 transfer request source select (DMA9 Channel Control Register 1)

4 TENL9 0: Disable transfer R W

DMA9 transfer enable bit 1: Enable transfer

5 TSZSL9 0: 16 bits R W

DMA9 transfer size select bit 1: 8 bits

6 SADSL9 0: Fixed R W

DMA9 source address direction select bit 1: Increment

7 DADSL9 0: Fixed R W

DMA9 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA9 Channel Control Register 1 (DM9CNT1) <Address: H ’0080 0459> 9 10 11 12 13 14 b15b8 REQESEL9 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12–15 REQESEL9 0000: One DMA8 transfer completed R W Extended DMA9 transfer request source select bit 0001: MJT(TOU0_7irq) 0010: AD1 conversion completed 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited 1111: Settings inhibited | |

32180 Group User’s Manual (Rev.1.0) The DMA Channel Control Register consists of the bits to select DMA transfer mode on each channel, set the DMA transfer request flag, select the cause or source of DMA request and enable DMA transfer, as well as those to set the transfer size and the source/destination address directions. [DMnCNT0 Register] (1) MDSELn (DMAn Transfer Mode Select) bit (Bit 0) When performing DMA transfer in single transfer mode, this bit selects normal mode or ring buffer mode. Setting this bit to "0" selects normal mode and setting it to "1" selects ring buffer mode. In ring buffer mode, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. In this case, the Transfer Count Register counts in free-run mode, during which time transfer operation is continued until the transfer enable bit is reset to "0" (to disable transfer). In ring buffer mode, no interrupt is generated at completion of DMA transfer. (2) TREQFn (DMAn Transfer Request Flag) bit (Bit 1) This flag is set to "1" when a DMA transfer request occurs, and is cleared to "0" when the transfer for that transfer request is completed. Reading this flag helps to know DMA transfer requests on each channel. Writing "0" to this bit clears the generated DMA transfer request. Writing "1" has no effect; the bit retains the value it had before the write. If a new DMA transfer request occurs on a channel for which the DMA transfer request flag has already been set to "1", the next DMA transfer request is not accepted until the transfer being performed on that channel is completed. (3) REQSLn (DMAn Transfer Request Source Select) bits (Bits 2–3) These bits select the cause or source of DMA transfer request on each DMA channel. (4) TENLn (DMAn Transfer Enable) bit (Bit 4) Setting this bit to "1" enables transfer, and the channel is made ready for DMA transfer. When all transfers on that channel are completed (i.e., the Transfer Counter Register underflows), the bit is cleared to "0". Setting this bit to "0" disables transfer. However, if a transfer request has already been accepted, transfers on that channel are not disabled until after the requested transfer is completed. (5) TSZSLn (DMAn Transfer Size Select) bit (Bit 5) This bit selects the number of bits to be transferred in one DMA transfer operation (the unit of one transfer). The unit of one transfer is 16 bits when TSZSL = "0" or 8 bits when TSZSL = "1". (6) SADSLn (DMAn Source Address Direction Select) bit (Bit 6) This bit selects the direction in which the source address changes. This mode can be selected from two choices: Address fixed or Address incremental. (7) DADSLn (DMAn Destination Address Direction Select) bit (Bit 7) This bit selects the direction in which the destination address changes. This mode can be selected from two choices: Address fixed or Address incremental. [DMnCNT1 Register] (1) REQESELn (Extended DMAn Transfer Request Source Select) bits (Bits 12–15) These bits select the cause or source of extended DMA transfer request on each DMA channel. Note:  The extended DMA transfer request sources selected by the REQESELn (Extended DMAn Transfer Request Source Select) bits have no effect unless the “Extended” DMA transfer re- quest source is selected with the DMA Channel Control Register’s DMA Request Source Se- lect (REQSLn) bits.

9-17 32180 Group User’s Manual (Rev.1.0) Figure 9.2.1 Block Diagram of Extended DMAn Transfer Request Source Selection

32180 Group User’s Manual (Rev.1.0)

9.2.2 DMA Software Request Generation Registers

DMA0 Software Request Generation Register (DM0SRI) <Address: H ’0080 0460> DMA1 Software Request Generation Register (DM1SRI) <Address: H ’0080 0462> DMA2 Software Request Generation Register (DM2SRI) <Address: H ’0080 0464> DMA3 Software Request Generation Register (DM3SRI) <Address: H ’0080 0466> DMA4 Software Request Generation Register (DM4SRI) <Address: H ’0080 0468> DMA5 Software Request Generation Register (DM5SRI) <Address: H ’0080 0470> DMA6 Software Request Generation Register (DM6SRI) <Address: H ’0080 0472> DMA7 Software Request Generation Register (DM7SRI) <Address: H ’0080 0474> DMA8 Software Request Generation Register (DM8SRI) <Address: H ’0080 0476> DMA9 Software Request Generation Register (DM9SRI) <Address: H ’0080 0478> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 DM0SRI –DM9SRI <After reset: Undefined> b Bit Name Function R W 0–15 DM0SRI –DM9SRI DMA transfer request is generated by writing any H W DMA software request generation bits data to these bits. Note:  This register may be accessed in either bytes or halfwords. The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA transfer request can be generated by writing any data to this register when “Software start” has been selected for the cause of DMA transfer request. (1) DM0SRI–DM9SRI (DMA Software Request Generation) bits A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in byte (8 bits) beginning with an even or odd address when “Software start” is selected as the cause of DMA transfer request (by setting the DMAn Channel Control Register 0 bits 2–3 to ‘00’).

9-19 32180 Group User’s Manual (Rev.1.0)

9.2.3 DMA Source Address Registers

DMA0 Source Address Register (DM0SA) <Address: H ’0080 0412> DMA1 Source Address Register (DM1SA) <Address: H ’0080 0422> DMA2 Source Address Register (DM2SA) <Address: H ’0080 0432> DMA3 Source Address Register (DM3SA) <Address: H ’0080 0442> DMA4 Source Address Register (DM4SA) <Address: H ’0080 0452> DMA5 Source Address Register (DM5SA) <Address: H ’0080 041A> DMA6 Source Address Register (DM6SA) <Address: H ’0080 042A> DMA7 Source Address Register (DM7SA) <Address: H ’0080 043A> DMA8 Source Address Register (DM8SA) <Address: H ’0080 044A> DMA9 Source Address Register (DM9SA) <Address: H ’0080 045A> b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 DM0SA –DM9SA <After reset: Undefined> b Bit Name Function R W 0–15 DM0SA –DMA9SA Source address bits A16 –A31 R W (A0–A15 are fixed to H’0080) Note:  This register must always be accessed in halfwords. The DMA Source Address Register is used to set the source address of DMA transfer in such a way that bit 0 and bit 5 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the values read from this register are always the current value. When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Source Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. (1) DM0SA–DM9SA (Source Address bits A16–A31) Set this register to specify the source address of DMA transfer in the internal I/O or RAM space from the address H’0080 0000 to the address H’0080 FFFF. The 16 high-order source address bits (A0–A15) are always fixed to H’0080. Use this register to set the 16 low-order source address bits (with bit 0 corresponding to the source address A16, and bit 15 corresponding to the source address A31).

32180 Group User’s Manual (Rev.1.0)

9.2.4 DMA Destination Address Registers

DMA0 Destination Address Register (DM0DA) <Address: H ’0080 0414> DMA1 Destination Address Register (DM1DA) <Address: H ’0080 0424> DMA2 Destination Address Register (DM2DA) <Address: H ’0080 0434> DMA3 Destination Address Register (DM3DA) <Address: H ’0080 0444> DMA4 Destination Address Register (DM4DA) <Address: H ’0080 0454> DMA5 Destination Address Register (DM5DA) <Address: H ’0080 041C> DMA6 Destination Address Register (DM6DA) <Address: H ’0080 042C> DMA7 Destination Address Register (DM7DA) <Address: H ’0080 043C> DMA8 Destination Address Register (DM8DA) <Address: H ’0080 044C> DMA9 Destination Address Register (DM9DA) <Address: H ’0080 045C> b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 DM0DA –DM9DA <After reset: Undefined> b Bit Name Function R W 0–15 DM0DA –DM9DA Destination address bits A16 –A31 R W (A0–A15 are fixed to H’0080) Note:  This register must always be accessed in halfwords The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the values read from this register are always the current value. When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Destination Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. (1) DM0DA–DM9DA (Destination Address bits A16–A31) Set this register to specify the destination address of DMA transfer in the internal I/O or RAM space from the address H’0080 0000 to the address H’0080 FFFF. The 16 high-order destination address bits (A0–A15) are always fixed to H’0080. Use this register to set the 16 low-order destination address bits (with bit 0 corresponding to the destination address A16, and bit 15 corresponding to the destination address A31).

9-21 32180 Group User’s Manual (Rev.1.0)

9.2.5 DMA Transfer Count Registers

DMA0 Transfer Count Register (DM0TCT) <Address: H ’0080 0416> DMA1 Transfer Count Register (DM1TCT) <Address: H ’0080 0426> DMA2 Transfer Count Register (DM2TCT) <Address: H ’0080 0436> DMA3 Transfer Count Register (DM3TCT) <Address: H ’0080 0446> DMA4 Transfer Count Register (DM4TCT) <Address: H ’0080 0456> DMA5 Transfer Count Register (DM5TCT) <Address: H ’0080 041E> DMA6 Transfer Count Register (DM6TCT) <Address: H ’0080 042E> DMA7 Transfer Count Register (DM7TCT) <Address: H ’0080 043E> DMA8 Transfer Count Register (DM8TCT) <Address: H ’0080 044E> DMA9 Transfer Count Register (DM9TCT) <Address: H ’0080 045E> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 DM0TCT –DM15TCT <After reset: Undefined> b Bit Name Function R W 0–15 DM0TCT –DM9TCT DMA transfer count R W (Has no effect during ring buffer mode) Note:  This register must always be accessed in halfwords. The DMA Transfer Count Register is used to set the number of times data is transferred on each channel. However, the value in this register has no effect during ring buffer mode. The transfer count is the (value set in the transfer count register + 1). Because the DMA Transfer Count Register is comprised of a current register, the values read from this register are always the current value. (However, if the register is read in a cycle immediately after transfer, the value obtained is one that was stored in the count register before the transfer began.) When transfer finishes, this count register underflows and the value read from it is H’FFFF. When transfer is enabled, this register is protected in hardware and cannot be accessed for write. During ring buffer mode, the transfer count register counts down in free-run mode and continues counting until transfer is disabled. No interrupt is generated at underflow. If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all trans- fers on a channel are completed (i.e., the transfer count register underflows), transfer on the cascaded channel starts. The DMA Transfer Count Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined.

32180 Group User’s Manual (Rev.1.0)

9.2.6 DMA Interrupt Related Registers

The DMA interrupt related registers are used to control the interrupt request signals sent from the DMAC to the Interrupt Controller. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt request mask bit, it can be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "0" to enable interrupt requests or "1" to disable interrupt requests. Figure 9.2.2 Interrupt Request Status and Mask Registers To the Interrupt Controller Interrupt request from each peripheral function Interrupt request status Data bus Set Group interrupt Interrupt request enabled clear F/F F/F Data = 0

9-23 32180 Group User’s Manual (Rev.1.0) Figure 9.2.3 Example for Clearing Interrupt Request Status b4 5 b7 Interrupt request status Initial state Event occurs on bit 6 Interrupt request Event occurs on bit 4 Only bit 6 cleared Bit 4 data retained b4 5 b7 1 1 0 1 Write to the interrupt request status Example for clearing interrupt request status 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 Program example ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */  To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. b4 5 6 b7 Interrupt request status Event occurs on bit 6 Event occurs on bit 4 Only bit 6 cleared Bit 4 also cleared 0 0 1 0 1 0 1 0 0 0 0 0 Read 0 0 1 0 0 0 0 0 Clear bit 6 (AND'ing with 1101) Write ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */

32180 Group User’s Manual (Rev.1.0) DMA0 –4 Interrupt Request Status Register (DM04ITST) <Address: H ’0080 0400> 123456 b 7b0 DMITST4 DMITST3 DMITST1 DMITST0DMITST2 000000 0 0 <After reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00

3 DMITST4 (DMA4 interrupt request status bit) 0: Interrupt not requested R(Note 1)

4 DMITST3 (DMA3 interrupt request status bit) 1: Interrupt requested

5 DMITST2 (DMA2 interrupt request status bit)

6 DMITST1 (DMA1 interrupt request status bit)

7 DMITST0 (DMA0 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA5 –9 Interrupt Request Status Register (DM59ITST) <Address: H ’0080 0408> 123456 b 7b0 DMITST9 DMITST8 DMITST6 DMITST5DMITST7 000000 0 0 <After reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00

3 DMITST9 (DMA9 interrupt request status bit) 0: Interrupt not requested R(Note 1)

4 DMITST8 (DMA8 interrupt request status bit) 1: Interrupt requested

5 DMITST7 (DMA7 interrupt request status bit)

6 DMITST6 (DMA6 interrupt request status bit)

7 DMITST5 (DMA5 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. The Interrupt Request Status Register helps to know the status of interrupt requests on each channel. If the DMAn interrupt request status bit (n = 0–9) is set to "1", it means that a DMA interrupt request on the corresponding channel has been generated. (1) DMITSTn (DMAn Interrupt Request Status) bit (n = 0–9) [Setting the DMAn interrupt request status bit] This bit is set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing "0" in software. Note:  The DMAn interrupt request status bit cannot be cleared by writing "0" to the DMA Interrupt Control Register’s “interrupt request bit” included in the Interrupt Controller. When writing to the DMA Interrupt Request Status Register, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write.

9-25 32180 Group User’s Manual (Rev.1.0) DMA0 –4 Interrupt Request Mask Register (DM04ITMK) <Address: H ’0080 0401> 9 10 11 12 13 14 b15b8 DMITMK4 DMITMK3 DMITMK1 DMITMK0DMITMK2 000000 0 0 <After reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 DMITMK4 (DMA4 interrupt request mask bit) 0: Enable interrupt request R W

12 DMITMK3 (DMA3 interrupt request mask bit) 1: Mask (disable) interrupt request

13 DMITMK2 (DMA2 interrupt request mask bit)

14 DMITMK1 (DMA1 interrupt request mask bit)

15 DMITMK0 (DMA0 interrupt request mask bit)

DMA5 –9 Interrupt Request Mask Register (DM59ITMK) <Address: H ’0080 0409> 9 10 11 12 13 14 b15b8 DMITMK9 DMITMK8 DMITMK6 DMITMK5DMITMK7 000000 0 0 <After reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 DMITMK9 (DMA9 interrupt request mask bit) 0: Enable interrupt request R W

12 DMITMK8 (DMA8 interrupt request mask bit) 1: Mask (disable) interrupt request

13 DMITMK7 (DMA7 interrupt request mask bit)

14 DMITMK6 (DMA6 interrupt request mask bit)

15 DMITMK5 (DMA5 interrupt request mask bit)

The DMA Interrupt Request Mask Register is used to mask interrupt requests on each DMA channel. (1) DMITMKn (DMAn Interrupt Request Mask) bit (n = 0–9) Setting the DMAn interrupt request mask bit to "1" masks the interrupt requests on DMAn channel. However, if an interrupt request occurs, the DMAn interrupt request status bit is always set to "1" irrespective of the contents of this mask register.

32180 Group User’s Manual (Rev.1.0) F/F F/F DMITMK5 DMITST5 F/F F/F DMITMK6 DMITST6 F/F F/F DMITMK7 DMITST7 F/F F/F DMITMK8 DMITST8 F/F F/F DMITMK9 DMITST9 b15 b14 b13 b12 b11 Data bus DMA9UDF DMA8UDF DMA7UDF DMA6UDF DMA5UDF DMA transfer interrupt request 1(Level) 5-source inputs DM59ITST (H'0080 0408) DM59ITMK (H'0080 0409) Figure 9.2.5 Block Diagram of DMA Transfer Interrupt Request 1 F/F F/F DMITMK0 DMITST0 F/F F/F DMITMK1 DMITST1 F/F F/F DMITMK2 DMITST2 F/F F/F DMITMK3 DMITST3 F/F F/F DMITMK4 DMITST4 b15 b14 b13 b12 b11 Data bus DMA4UDF DMA3UDF DMA2UDF DMA1UDF DMA0UDF DMA transfer interrupt request 0(Level) 5-source inputs DM04ITST (H'0080 0400) DM04ITMK (H'0080 0401) Figure 9.2.4 Block Diagram of DMA Transfer Interrupt Request 0

9-27 32180 Group User’s Manual (Rev.1.0)

9.3.1 DMA Transfer Request Sources

For each DMA channel (channels 0–9), DMA transfer can be requested from two or more sources. There are various causes or sources of DMA transfer request, so that DMA transfer can be started by a request from some internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all transfers on another DMA channel (cascade mode). The causes or sources of DMA transfer requests are selected using the transfer request source select bits REQSLn on each channel (DMAn Channel Control Register 0 bits 2–3) or the extended transfer request source select bits REQESELn (DMAn Channel Control Register 1 bits 12–15). The tables below list the causes or sources of DMA transfer requests on each channel. Table 9.3.1 DMA Transfer Request Sources and Generation Timings on DMA0 REQSL0 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start or one DMA2 When any data is written to the DMA0 Software Request Generation Register transfer completed (software start) or when one DMA2 transfer is completed (cascade mode) 0 1 A-D0 conversion completed When A-D0 conversion is completed 1 0 MJT (TIO8_udf) When MJT TIO8 underflows 1 1 Extended DMA0 transfer request The source selected by the DMA0 Channel Control Register 1 (DM0CNT1) source selected REQESEL0 bits (see below) REQESEL0 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 MJT (input event bus 2) When MJT input event bus 2 signal is generated

0001 MJT (TID0_udf/ovf) When MJT TID0 underflow/overflow occurs

0010 CAN (CAN0_S0/S15) When CAN0 slot 0 transmission failed or slot 15 transmission reception finished

0011 MJT (input event bus 1) When MJT input event bus 1 signal is generated

0100 MJT (input event bus 3) When MJT input event bus 3 signal is generated

0101 MJT (output event bus 2) When MJT output event bus 2 signal is generated

0110 MJT (output event bus 3) When MJT output event bus 3 signal is generated

0111 A-D0 conversion completed When A-D0 conversion is completed

1000 MJT (TIN0 input signal) When MJT TIN0 input signal is generated

1001 MJT (TIO8_udf) When MJT TIO8 underflow occurs

| Settings inhibited – 1111

32180 Group User’s Manual (Rev.1.0) Table 9.3.2 DMA Transfer Request Sources and Generation Timings on DMA1 REQSL1 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA1 Software Request Generation Register 0 1 MJT (output event bus 0) When MJT output event bus 0 signal is generated 1 0 MJT (TIN13 input signal) When MJT TIN13 input signal is generated 1 1 Extended DMA1 transfer request The source selected by the DMA1 Channel Control Register 1 (DM1CNT1) source selected REQESEL1 bits (see below) REQESEL1 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 One DMA0 transfer completed When one DMA0 transfer is completed (cascade mode)

0001 MJT (TIN3 input signal) When MJT TIN3 input signal is generated

0010 MJT (TID1_udf/ovf) When MJT TID1 underflow/overflow occurs

| Settings inhibited – 1111 Table 9.3.3 DMA Transfer Request Sources and Generation Timings on DMA2 REQSL2 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA2 Software Request Generation Register 0 1 MJT (output event bus 1) When MJT output event bus 1 signal is generated 1 0 MJT (TIN18 input signal) When MJT TIN18 input signal is generated 1 1 Extended DMA2 transfer request The source selected by the DMA2 Channel Control Register 1 (DM2CNT1) source selected REQESEL2 bits (see below) REQESEL2 DMA Transfer Request Source DMA Transfer Request Generation Timing

0001 MJT(TID2_udf/ovf) When MJT TID2 underflow/overflow occurs

0010 CAN(CAN0_S1/S14) When CAN0 slot 1 transmission failed or slot 14 transmission reception finished

| Settings inhibited – 1111

9-29 32180 Group User’s Manual (Rev.1.0) Table 9.3.4 DMA Transfer Request Sources and Generation Timings on DMA3 REQSL3 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA3 Software Request Generation Register 0 1 Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty 1 0 Serial I/O1 (reception completed) When serial I/O1 reception is completed 1 1 Extended DMA3 transfer request The source selected by the DMA3 Channel Control Register 1 (DM3CNT1) source selected REQESEL3 bits (see below) REQESEL3 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 MJT (TIN0 input signal) When MJT TIN0 input signal is generated

0001 One DMA2 transfer completed When one DMA2 transfer is completed (cascade mode)

0010 A-D1 conversion completed When A-D1 conversion is completed

| Settings inhibited – 1111 Table 9.3.5 DMA Transfer Request Sources and Generation Timings on DMA4 REQSL4 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA4 Software Request Generation Register 0 1 One DMA3 transfer completed When one DMA3 transfer is completed (cascade mode) 1 0 Serial I/O0 (reception completed) When serial I/O0 reception is completed 1 1 Extended DMA4 transfer request The source selected by the DMA4 Channel Control Register 1 (DM4CNT1) source selected REQESEL4 bits (see below) REQESEL4 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 MJT (TIN19 input signal) When MJT TIN19 input signal is generated

0001 Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty

0010 MJT (TOU1_7irq) MJT TOU1_7 interrupt source

| Settings inhibited – 1111

32180 Group User’s Manual (Rev.1.0) Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5 REQSL5 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start or one DMA7 When any data is written to the DMA5 Software Request Generation Register transfer completed (software start) or when one DMA7 transfer is completed (cascade mode) 0 1 All DMA0 transfers completed When all DMA0 transfers are completed (cascade mode) 1 0 Serial I/O2 (reception completed) When serial I/O2 reception is completed 1 1 Extended DMA5 transfer request The source selected by the DMA5 Channel Control Register 1 (DM5CNT1) source selected REQESEL5 bits (see below) REQESEL5 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 MJT (TIN20 input signal) When MJT TIN20 input signal is generated

0001 MJT (TOU0_0irq) MJT TOU0_0 interrupt source

0010 MJT (TOU2_7irq) MJT TOU2_7 interrupt source

| Settings inhibited – 1111 Table 9.3.7 DMA Transfer Request Sources and Generation Timings on DMA6 REQSL6 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA4 Software Request Generation Register 0 1 Serial I/O1 (transmit buffer empty) When serial I/O1 transmit buffer is empty 1 0 MJT (TIN1 input signal) When MJT TIN1 input signal is generated 1 1 Extended DMA6 transfer request The source selected by the DMA6 Channel Control Register 1 (DM6CNT1) source selected REQESEL6 bits (see below) REQESEL6 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 One DMA5 transfer completed When one DMA5 transfer is completed (cascade mode)

0001 MJT (TOU0_1irq) MJT TOU0_1 interrupt source

0010 Serial I/O1 (reception completed) When serial I/O1 reception is completed

| Settings inhibited – 1111

9-31 32180 Group User’s Manual (Rev.1.0) Table 9.3.8 DMA Transfer Request Sources and Generation Timings on DMA7 REQSL7 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA7 Software Request Generation Register 0 1 Serial I/O2 (transmit buffer empty) When serial I/O2 transmit buffer is empty 1 0 MJT (TIN2 input signal) When MJT TIN2 input signal is generated 1 1 Extended DMA7 transfer request The source selected by the DMA7 Channel Control Register 1 (DM7CNT1) source selected REQESEL7 bits (see below) REQESEL7 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 One DMA6 transfer completed When one DMA6 transfer is completed (cascade mode)

0001 MJT (TOU0_2irq) MJT TOU0_2 interrupt source

0010 Serial I/O3 (reception completed) When serial I/O3 reception is completed

| Settings inhibited – 1111 Table 9.3.9 DMA Transfer Request Sources and Generation Timings on DMA8 REQSL8 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA8 Software Request Generation Register 0 1 MJT (input event bus 0) When MJT input event bus 0 signal is generated 1 0 Serial I/O3 (reception completed) When serial I/O3 reception is completed 1 1 Extended DMA8 transfer request The source selected by the DMA8 Channel Control Register 1 (DM8CNT1) source selected REQESEL8 bits (see below) REQESEL8 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 MJT (TIN7 input signal) When MJT TIN7 input signal is generated

0001 MJT (TOU0_6irq) MJT TOU0_6 interrupt source

0010 One DMA7 transfer completed When one DMA7 transfer is completed (cascade mode)

| Settings inhibited – 1111

32180 Group User’s Manual (Rev.1.0) Table 9.3.10 DMA Transfer Request Sources and Generation Timings on DMA9 REQSL9 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA9 Software Request Generation Register 0 1 Serial I/O3 (transmit buffer empty) When serial I/O3 transmit buffer is empty 1 0 MJT (TIN8 input signal) When MJT TIN8 input signal is generated 1 1 Extended DMA9 transfer request The source selected by the DMA9 Channel Control Register 1 (DM9CNT1) source selected REQESEL9 bits (see below) REQESEL9 DMA Transfer Request Source DMA Transfer Request Generation Timing

0000 One DMA8 transfer completed When one DMA8 transfer is completed (cascade mode)

0001 MJT (TOU0_7irq) MJT TOU0_7 interrupt source

0010 A-D0 conversion completed When A-D0 conversion is completed

| Settings inhibited – 1111

9-33 32180 Group User’s Manual (Rev.1.0) DMA transfer starts as requested by internal peripheral I/O DMA transfer processing starts Transfer count register underflows Interrupt request generated Set DMA0 Channel Control Register 0 Set DMA0-4 Interrupt Request Status Registers 0 and 1 Set DMA0 Channel Control Registers 0 and 1 Set DMA0 Source Address Register Set DMA0 Destination Address Register Set DMA0 Count Register Setting DMAC-related registers Starting DMA transfer DMA transfer completed  Transfers disabled  Interrupt request status bits cleared Set DMA0-4 Interrupt Request Mask Register  Source address of transfer  Destination address of transfer  Number of times DMA transfer is performed  Transfer mode, request source, transfer size, address direction and transfer enable DMA operation completed  Interrupt request enabled Set the interrupt controller's DMA0-4 Interrupt Control Register  Interrupt priority level Setting interrupt controller-related registers Figure 9.3.1 Example of a DMA Transfer Processing Procedure

9.3.2 DMA Transfer Processing Procedure

Shown below is an example of how to control DMA transfer in cases when performing transfer on DMA channel 0.

32180 Group User’s Manual (Rev.1.0) Figure 9.3.2 Gaining and Releasing Control of the Internal Bus One DMA transfer DMAC CPU Internal bus arbitration (requests from the DMAC) Internal bus R: Read W: Write R W R W R W Requested Gained Requested Gained Requested Gained One DMA transfer One DMA transfer Released Released Released

9.3.3 Starting DMA

Use the DMAn Channel Control Register 0 REQSL (DMA transfer request source select) and DMAn Channel Control Register 1 REQESEL (extended DMA transfer request source select) bits to set the cause or source of DMA transfer request. To enable DMA, set the TENL (DMA transfer enable) bit to "1". DMA transfer begins when the specified cause or source of DMA transfer request becomes effective after setting the TENL (DMA transfer enable) bit to "1". Note:  If the transfer request source selected by the REQSL (DMA transfer request source select) and REQESEL (extended DMA transfer request source select) bits is MJT (TIN input signal), the time required for DMA transfer to begin after detecting the rising or falling or both edges of the TIN input signal is three cycles (150 ns when the internal peripheral clock = 20 MHz) at the shortest. Or, depending on the preceding or following bus usage condition, up to five cycles (250 ns when the internal peripheral clock = 20 MHz) may be required. (However, this applies when the external bus, HOLD and the LOCK instruction all are unused.) To ensure that changes of the TIN input signal state will be detected correctly, make sure the TIN input signal is held active for a duration of more than 7tc (BCLK)/2. (For details, see Section 21.7, “AC Characteristics (when VCCE = 5 V),” and Section 21.8, “AC Characteristics (when VCCE = 3.3 V).”)

9.3.4 DMA Channel Priority

DMA0 has the highest priority. The priority of this and other channels is shown below. DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9 This order of priority is fixed and cannot be changed. Among channels on which DMA transfer is requested, the channel that has the highest priority is selected.

9.3.5 Gaining and Releasing Control of the Internal Bus

For any channel, control of the internal bus is gained and released in “single transfer DMA” mode. In single transfer DMA, the DMAC gains control of the internal bus (in one peripheral clock cycle) when DMA transfer request is accepted and after executing one DMA transfer (in one read and one write internal clock cycle), returns bus control to the CPU. The diagram below shows the operation in single transfer DMA.

9-35 32180 Group User’s Manual (Rev.1.0)

9.3.6 Transfer Units

Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one DMA transfer.

9.3.7 Transfer Counts

Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be performed up to 65,536 times. The value of the DMA Transfer Count Register is decremented by one every time one transfer unit is transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-run mode, with the value set in it ignored.

9.3.8 Address Space

The address space in which data can be transferred by DMA is 64 Kbytes of internal peripheral I/O or RAM space (H’0080 0000 through H’0080 FFFF) for both source and destination. To set the source and destination addresses on each DMA channel, use the DMA Source Address Register and DMA Destination Address Register.

9.3.9 Transfer Operation

(1) Dual-address transfer Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and one for destination write access. (The transfer data is taken into the DMAC’s internal temporary register before being transferred.) (2) Bus protocol and bus timing Because the bus interface is shared with the CPU, DMA transfer is performed with the same bus protocol and the same bus timing as when peripheral modules are accessed by the CPU. (3) Transfer rate Transfer is performed using a total of three peripheral clock cycles, one cycle to gain control of the bus and one read and one write cycle to perform one transfer. Therefore, the maximum transfer rate is calculated by the equation below: Maximum transfer rate [bytes per second] = 2 bytes × 1 1/f(BCLK) × 3 cycles (4) Address count direction and address changes The direction in which the source and destination addresses are counted as transfer proceeds (“Address fixed” or “Address incremental”) is set for each channel using the SADSL (source address direction select) and DADSL (destination address direction select) bits. When the transfer size is 16 bits, the address is incremented by two for each DMA transfer performed; when the transfer size is 8 bits, the address is incremented by one. Table 9.3.11 Address Count Direction and Address Changes Address Count Direction Transfer Unit Address Change for One DMA Address fixed 8 bits 0 16 bits 0 Address incremental 8 bits +1 16 bits +2

32180 Group User’s Manual (Rev.1.0) Figure 9.3.3 Transfer Byte Positions (7) Ring buffer mode When ring buffer mode is selected, transfer begins from the transfer start address and after performing transfers 32 times, control returns to the transfer start address, from which transfer operation is repeated. In this case, however, the five low-order bits of the ring buffer start address must always be B’00000 (if transfer size = 16 bits, the six low-order bits must be B’000000). The following describes how addresses are incremented in ring buffer mode. [1] When the transfer size is 8 bits The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented by one at a time. When as transfer proceeds the five low-order bits reach B’11111, they are recycled to B’00000 by the next increment operation, thus returning to the start address again. [2] When the transfer size is 16 bits The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented by two at a time. When as transfer proceeds the six low-order bits reach B’111110, they are recycled to B’000000 by the next increment operation, thus returning to the start address again. If the source address has been set to be incremented, it is the source address that recycles to the start address; if the destination address has been set to be incremented, it is the destination address that recycles to the start address. If both source and destination addresses have been set to be incremented, both ad- dresses recycle to the start address. However, the start address on either side must have their five low-order bits initially set to B’00000 (if transfer size = 16 bits, the six low-order bits must be B’000000). During ring buffer mode, the transfer count register is ignored. Once DMA operation starts, the counter operates in free-run mode, and the transfer continues until the transfer enable bit is cleared to "0" (to disable transfer). (5) Transfer count value The transfer count value is decremented one at a time, irrespective of the size of transfer unit (8 or 16 bits). (6) Transfer byte positions When the transfer unit is 8 bits, the LSB of the address register is effective for both source and destination. (Therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address or vice versa.) When the transfer unit is 16 bits, the LSB of the address register (= bit 15) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus. The diagram below shows the valid byte positions in DMA transfer. b0 b7 b8 b15 8 bits +0 +1 Source Destination <When transfer size = 8 bits> 8 bits 8 bits 8 bits 16 bits 16 bits b0 b7 b8 b15 +0 +1 <When transfer size = 16 bits>

9-37 32180 Group User’s Manual (Rev.1.0) Figure 9.3.4 Example of How Addresses Are Incremented in 32-channel Ring Buffer Mode

9.3.10 End of DMA and Interrupt

In normal mode, DMA transfer is terminated by an underflow of the transfer count register. When transfer fin- ishes, the transfer enable bit is cleared to "0" and transfers are thereby disabled. Also, an interrupt request is generated at completion of transfer. However, if interrupt requests on any channel have been masked by the DMA Interrupt Request Mask Register, no interrupt requests are generated on that channel. During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the transfer enable bit is cleared to "0" (to disable transfer). In this case, therefore, no interrupt requests are gener- ated at completion of DMA transfer. Nor are these DMA transfer-completed interrupt requests are generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit.

9.3.11 Each Register Status after Completion of DMA Transfer

When DMA transfer is completed, the status of the source and destination address registers becomes as fol- lows: (1) Address fixed  The values set in the address registers before DMA transfer started remain intact (fixed). (2) Address incremental  For 8-bit transfer, the values of the address registers are the last transfer address + 1.  For 16-bit transfer, the values of the address registers are the last transfer address + 2. The transfer count register at completion of DMA transfer is in an underflow state (H’FFFF). Therefore, before another DMA transfer can be performed, the transfer count register must be set newly again, except when trying to perform transfers 65,536 times (H’FFFF). <When transfer size = 8 bits> Transfer count Transfer address

1 H'0080 1000

2 H'0080 1001

3 H'0080 1002

31 H'0080 101E

32 H'0080 101F

↓ ↓ ↓ ↓ <When transfer size = 16 bits> Transfer count Transfer address

2 H'0080 1002

3 H'0080 1004

31 H'0080 103C

32 H'0080 103E

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32180 Group User’s Manual (Rev.1.0)  About writing to the DMAC related registers Because DMA transfer involves exchanging data via the internal bus, the DMAC related registers basically can only be accessed for write immediately after reset or when transfer is disabled (transfer enable bit = "0"). When transfer is enabled, do not write to the DMAC related registers, except the DMA transfer enable bit, the transfer request flag and the DMA Transfer Count Register that is protected in hardware. This is a precaution necessary to ensure stable DMA operation. The table below lists the registers that can or cannot be accessed for write. Table 9.4.1 DMAC Related Registers That Can or Cannot Be Accessed for Write Status Transfer enable bit Transfer request flag Other DMAC related registers Transfer enabled Can be accessed Can be accessed Cannot be accessed Transfer disabled Can be accessed Can be accessed Can be accessed Even for registers that can exceptionally be written to while transfer is enabled, the following conditions must be observed: (1) DMA Channel Control Register 0 transfer enable bit and transfer request flag For all other bits in this register, be sure to write the same data that those bits had before the write. Note, however, that only writing "0" is effective for the transfer request flag. (2) DMA Transfer Count Register When transfer is enabled, this register is protected in hardware, so that any data rewritten to it is ignored. (3) Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer Although this operation means accessing the DMAC related registers while DMA is enabled, there is no problem. Note, however, that no data can be transferred by DMA to the DMAC related registers on the currently active channel itself.  Manipulating the DMAC related registers by DMA transfer When manipulating the DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related registers with the initial values by DMA transfer), do not write to the DMAC related registers on the currently active channel through that channel. (If this precaution is neglected, device operation cannot be guaranteed.) It is only the DMAC related registers on other channels that can be rewritten by means of DMA transfer. (For example, the DMAn Source Address and DMAn Destination Address Registers on channel 1 can be rewritten by DMA transfer through channel 0.)  About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register, be sure to write "1" to all bits, except those to be cleared. Writing "1" to any bits in this register has no effect, so that they retain the data they had before the write.  About the stable operation of DMA transfer To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except the channel control register’s transfer enable bit, unless transfer is disabled. One exception is that even when transfer is enabled, the DMA Source Address and DMA Destination Address Registers can be rewritten by DMA transfer from one channel to another.

10.1 Outline of Multijunction Timers

10.2 Common Units of Multijunction Timers

10.3 TOP (Output-Related 16-Bit Timer)

10.4 TIO (Input/Output-Related 16-Bit Timer)

10.5 TMS (Input-Related 16-Bit Timer)

10.6 TML (Input-Related 32-Bit Timer)

10.7 TID (Input-Related 16-Bit Timer)

10.8 TOU (Output-Related 24-Bit Timer)

32180 Group User’s Manual (Rev.1.0) The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to being used as a single unit, the timers can be internally connected to each other. This capability allows for highly flexible timer configuration, making it possible to meet various application needs. It is because the timers are connected to the internal event buses at multiple points that they are called the “multijunction” timers. The 32180 has six types of MJT as listed in the table below, providing a total of 64-channel timers. Table 10.1.1 Outline of MJT Name Type No. of Channels Description TOP Output-related 11 One of three output modes can be selected by software. (Timer 16-bit timer <With correction function> OutPut) (down-counter)  Single-shot output mode  Delayed single-shot output mode <Without correction function>  Continuous output mode TIO Input/output-related 10 One of three input modes or four output modes can be selected (Timer 16-bit timer by software. Input (down-counter) <Input modes> OutPut)  Measure clear input mode  Measure free-run input mode  Noise processing input mode <Output modes without correction function>  PWM output mode  Single-shot output mode  Delayed single-shot output mode  Continuous output mode TMS Input-related 8 16-bit input measure timer (Timer 16-bit timer Measure (up-counter) Small) TML Input-related 8 32-bit input measure timer (Timer 32-bit timer Measure (up-counter) Large) TID Input-related 3 One of four input modes can be selected by software. (Timer 16-bit timer  Fixed period mode Input (up/down-counter))  Event count mode Derivation)  Multiply-by-4 event count mode  Up/down event count mode TOU Output-related 24 One of five output modes can be selected by software. (Timer 24-bit timer <Without correction function> output (down-counter)  PWM output mode Unification)  Single-shot PWM mode  Delayed single-shot output mode  Single-shot output mode  Continuous output mode

32180 Group User’s Manual (Rev.1.0) Table 10.1.2 Interrupt Generation Functions of MJT Signal Name MJT Interrupt Request Source Source of Interrupt No. of ICU Input Sources IRQ0 TIO0–3 output TIO0–3 output interrupt 4 IRQ1 TOP6, TOP7 output TOP6, 7 output interrupt 2 IRQ2 TOP0–5 output TOP0–5 output interrupt 6 IRQ3 TIO8, TIO9 output TIO8, 9 output interrupt 2 IRQ4 TIO4–7 output TIO4–7 output interrupt 4 IRQ5 TOP10 output TOP10 output interrupt 1 IRQ6 TOP8, TOP9 output TOP8, 9 output interrupt 2 IRQ7 TMS0, TMS1 output TMS0, 1 output interrupt 2 IRQ8 TIN7–TIN11 input TIN7–TIN11 input interrupt 5 IRQ9 TIN0–TIN2 input TIN0–2 input interrupt 3 IRQ10 TIN12–TIN19 input TIN12–19 input interrupt 8 IRQ11 TIN20–TIN23 input TIN20–23 input interrupt 4 IRQ12 TIN3–TIN6 input TIN3–6 input interrupt 4 IRQ13 TOU0_0–TOU0_7 output TOU0 output interrupt 8 IRQ14 TID0 output TID0 output interrupt 1 IRQ15 TID1 output TID1 output interrupt 1 IRQ16 TOU1_0–TOU1_7 output, TOU1 + TOU2 output interrupt 16 TOU2_0–TOU2_7 output IRQ17 TID2 output TID2 output interrupt 1 IRQ18 TIN30–TIN33 input TIN30–TIN33 input interrupt 4 Table 10.1.3 DMA Transfer Request Generation by MJT Corresponding DMAC Channel No. DMA Transfer Request Source DMA0 TIO8_udf Input event bus 2 TID0_udf/ovf Common transfer request source (see Table 10.1.4) DMA1 Output event bus 0 TIN13 input signal TIN3 input signal TID1_udf/ovf Common transfer request source (see Table 10.1.4) DMA2 Output event bus 1 TIN18 input signal TID2_udf/ovf Common transfer request source (see Table 10.1.4) DMA3 TIN0 input signal Common transfer request source (see Table 10.1.4) DMA4 TIN19 input signal TOU1_7irq Common transfer request source (see Table 10.1.4) DMA5 TIN20 input signal TOU0_0irq TOU2_7irq Common transfer request source (see Table 10.1.4)

32180 Group User’s Manual (Rev.1.0) DMA6 TIN1 input signal TOU0_1irq Common transfer request source (see Table 10.1.4) DMA7 TIN2 input signal TOU0_2irq Common transfer request source (see Table 10.1.4) DMA8 Input event bus 0 TIN7 input signal TOU0_6irq Common transfer request source (see Table 10.1.4) DMA9 TIN8 input signal TOU0_7irq Common transfer request source (see Table 10.1.4) Table 10.1.4 DMA Transfer Request Generation by MJT (Common) Corresponding DMAC Channel No. DMA Transfer Request Source DMAn Input event bus 1 Input event bus 3 Output event bus 2 Output event bus 3 TIN0 input signal TIO8_udf Table 10.1.5 A-D Conversion Start Request by MJT Signal Name A-D Conversion Start Request Source A-D Converter AD0TRG Input event bus 2, input event bus 3, Can be input to A-D0 conversion start trigger output event bus 3, TIN23 AD1TRG Input event bus 2, input event bus 3, Can be input to A-D1 conversion start trigger TID1udf/ovf, TIN23

32180 Group User’s Manual (Rev.1.0) Figure 10.1.1 Block Diagram of MJT (1/4) TCLK0 (P124) TIN0 (P150) BCLK/2 TIN1 (P151) TIN2 (P152) TIN3 (P153) TIN4 (P154) TIN5 (P155) TIN6 (P156) TCLK1 (P125) TIN7 (P157) TCLK2 (P126) TIN8 (P140) TIN9 (P141) TIN10 (P142) TIN11 (P143) TO0 (P110) TO1 (P111) TO2 (P112) TO3 (P113) TO4 (P114) TO5 (P115) TO6 (P116) TO7 (P117) TO8 (P100) TO9 (P101) TO10 (P102) TO11 (P103) TO12 (P104) TO13 (P105) TO14 (P106) TO15 (P107) TO16 (P93) TO17 (P94) TO18 (P95) TO19 (P96) TO20 (P97) IRQ9 DMA3,DMA commom IRQ9 DMA6 IRQ9 DMA7 IRQ12 DMA1 IRQ12 IRQ12 IRQ12 IRQ8 DMA8 IRQ8 DMA9 IRQ8 IRQ8 IRQ8 IRQ2 IRQ2 IRQ2 IRQ2 IRQ2 IRQ2 IRQ1 IRQ1 IRQ6 IRQ6 IRQ5 IRQ0 IRQ0 IRQ0 IRQ0 IRQ4 IRQ4 IRQ4 IRQ4 DMA0 DMA common IRQ3 IRQ3 : Prescalers : Output flip-flop : SelectorSF/FPRS0 –5 TOP 0clk en udf TOP 1clk en udf TOP 2clk en udf TOP 3clk en udf TOP 4clk en udf TOP 5clk en udf TOP 6clk en udf TOP 7clk en udf TOP 8clk en udf TOP 9clk en udf TOP 10clk en udf TIO 0clk en/cap udf TIO 1clk en/cap udf TIO 2clk en/cap udf TIO 3clk en/cap udf TIO 4clk en/cap udf TIO 5clk en/cap udf TIO 6clk en/cap udf TIO 7clk en/cap udf TIO 8clk en/cap udf TIO 9clk en/cap udf S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S TIN0S TCLK0S F/F10 F/F11 F/F12 F/F13 F/F14 F/F15 F/F16 F/F17 F/F18 F/F19 F/F20 F/F0 F/F1 F/F2 F/F3 F/F4 F/F5 F/F6 F/F7 F/F8 F/F9 TIN1S TIN2S TIN3S TIN4S TIN5S TIN6S S S S PRS0 PRS1 PRS2 TCLK1S TIN7S TCLK2S TIN8S TIN9S TIN10S TIN11S S S S 3210 3210 0123 3210 3210 0123 Clock bus Input event bus Output event bus Notes:  IRQ0-18 denotes interrupt signals, of which the same number represents the same group of interrupts.  DMA0-9 and DMA common denote DMA request signals to the DMAC.  AD0TRGa and AD1TRG denote trigger signals to the A-D0 and A-D1 converters, respectively.

32180 Group User’s Manual (Rev.1.0) TCLK3 (P127) TIN12 (P144) TIN13 (P145) TIN14 (P146) TIN15 (P147) TIN16/PWMOFF0 (P130) TIN17/PWMOFF1 (P131) TIN18 (P132) TIN19 (P133) BCLK/2 TIN20 (P134) TIN21 (P135) TIN22 (P136) TIN23 (P137) BCLK/2 TIN30 (P194) TIN31 (P195) TIN32 (P196) TIN33/PWMOFF2 (P197) IRQ10 IRQ10 DMA1 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 DMA2 IRQ10 DMA4 IRQ11 DMA5 IRQ11 IRQ11 IRQ11 (To A-D0 converter) AD0TRG (To A-D1 converter)AD1TRG IRQ18 IRQ18 IRQ18 IRQ18 AD0TRG (to A-D0 converter)/ AD1TRG (to A-D1 converter) AD0TRG (to A-D0 converter)/ AD1TRG (to A-D1 converter) AD0TRG (to A-D0 converter) IRQ7 IRQ7 TMS 0clk cap3 cap2 cap1 cap0 ovfS TIN12S TIN13S TIN14S TIN15S TCLK3S S S S S TMS 1clk cap3 cap2 cap1 cap0 ovf TIN16S TIN17S TIN18S TIN19S S S S S S TML 0(32-bit)clk cap3 cap2 cap1 cap0 TIN20S TIN21S TIN22S TIN23S S S S S S TML 1(32-bit)clk cap3 cap2 cap1 cap0 TIN30S TIN31S TIN32S TIN33S S S S S S 3210 3210 0123 3210 3210 0123 Clock bus Input event bus Output event bus Figure 10.1.2 Block Diagram of MJT (2/4)

32180 Group User’s Manual (Rev.1.0) TIN16/PWMOFF0 (P130) BCLK/2 TIN24 (P172) TIN25 (P173) TIN17/PWMOFF1 (P131) BCLK/2 TIN26 (P190) TIN27 (P191) TIN33/PWMOFF2 (P197) BCLK/2 TIN28 (P192) TIN29 (P193) TO21 (P160) TO22 (P161) TO23 (P162) TO24 (P163) TO25 (P164) TO26 (P165) TO27 (P166) TO28 (P167) TO29 (P180) TO30 (P181) TO31 (P182) TO32 (P183) TO33 (P184) TO34 (P185) TO35 (P186) TO36 (P187) TO37 (P210) TO38 (P211) TO39 (P212) TO40 (P213) TO41 (P214) TO42 (P215) TO43 (P216) TO44 (P217) IRQ11 IRQ11 IRQ11 IRQ11 IRQ11 IRQ11 DMA5 DMA6 DMA7 DMA8 DMA9 DMA0 DMA4 DMA1 DMA5 DMA2 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ14 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ15, AD1TRG (to A-D0 converter) IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ17 TOU0_0 (24-bit)clk en udf TOU0_1 (24-bit)clk en udf TOU0_2 (24-bit)clk en udf TOU0_3 (24-bit)clk en udf TOU0_4 (24-bit)clk en udf TOU0_5 (24-bit)clk en udf TOU0_6 (24-bit)clk en udf TOU0_7 (24-bit)clk en udf TID 0clkCLK1 CLK2 ovf udf TOU1_0 (24-bit)clk en udf TOU1_1 (24-bit)clk en udf TOU1_2 (24-bit)clk en udf TOU1_3 (24-bit)clk en udf TOU1_4 (24-bit)clk en udf TOU1_5 (24-bit)clk en udf TOU1_6 (24-bit)clk en udf TOU1_7 (24-bit)clk en udf TID 1clkCLK1 CLK2 ovf udf TOU2_0 (24-bit)clk en udf TOU2_1 (24-bit)clk en udf TOU2_2 (24-bit)clk en udf TOU2_3 (24-bit)clk en udf TOU2_4 (24-bit)clk en udf TOU2_5 (24-bit)clk en udf TOU2_6 (24-bit)clk en udf TOU2_7 (24-bit)clk en udf TID 2clkCLK1 CLK2 ovf udf F/F37 F/F38 F/F39 F/F40 F/F41 F/F42 F/F43 F/F44 TIN25S PWMOFF1S PWMOFF2S PWMOFF0S PO1DIS PO2DIS PO0DOS TIN24S PRS3 F/F29 F/F30 F/F31 F/F32 F/F33 F/F34 F/F35 F/F36 F/F21 F/F22 F/F23 F/F24 F/F25 F/F26 F/F27 F/F28S TIN27S TIN26S PRS4 S TIN29S TIN28S PRS5 S S S S Output event bus Figure 10.1.3 Block Diagram of MJT (3/4)

32180 Group User’s Manual (Rev.1.0) Figure 10.1.4 Block Diagram of MJT (4/4) S S S S S S S S S S S DMA0 udf end DMA1 udf end DMA2 udf end DMA3 udf end DMA4 udf end DMA5 udf end DMA6 udf end DMA7 udf end DMA8 udf end DMA9 udf end S S S S S S S S S AD0 conversion completed TIO8_udf TIN0S TID0_udf/ovf CAN0_S0/S15 TIN3S TID1_udf/ovf AD0 conversion completed TIO8_udf Software start TIN13S Software start TIN18S Software start SIO0_TXD SIO1_RXD Software start SIO0_RXD Software start Software start DMA0 –4 interrupt DMA5 –9 interrupt SIO2_RXD SIO1_TXD TIN1S Software start SIO2_TXD TIN2S SIO3_RXD Software start SIO3_TXD TIN8S Software start CAN0_S1/S14 TID2_udf/ovf TIN0S AD1 conversion completed TIN19S SIO0_TXD TOU1_7irq TIN20S TOU0_0irq TOU2_7irq TOU0_1irq SIO1_RXD SIO3_TXD TOU0_2irq TOU0_6irq TIN7S AD1 conversion completed TOU0_7irq 0123 Input event bus Output event bus 3210 3210 0123

32180 Group User’s Manual (Rev.1.0) The common units of MJT include the following:  Prescaler Unit  Clock Bus and Input/Output Event Bus Control Unit  Input Processing Control Unit  Output Flip-flop Control Unit  Interrupt Control Unit

32180 Group User’s Manual (Rev.1.0)

10.2.1 MJT Common Unit Register Map

The table below shows a common unit register map of MJT. MJT Common Unit Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0200 (Use inhibited area) Clock Bus & Input Event Bus Control Register 10-16 (CKIEBCR) H'0080 0202 Prescaler Register 0 Prescaler Register 1 10-12 (PRS0) (PRS1) H'0080 0204 Prescaler Register 2 Output Event Bus Control Register 10-12 (PRS2) (OEBCR) 10-17 (Use inhibited area) H'0080 0210 TCLK Input Processing Control Register 10-20 (TCLKCR) H'0080 0212 TIN0 –4 Input Processing Control Register 10-21 (TIN04CR) H'0080 0214 TIN5 –8 Input Processing Control Register 10-22 (TIN58CR) H'0080 0216 TIN9 –11 Input Processing Control Register 10-23 (TIN911CR) H'0080 0218 TIN12 –19 Input Processing Control Register 10-24 (TIN1219CR) H'0080 021A TIN20 –23, TIN30–33 Input Processing Control Register 10-24 (TIN2023_3033CR) (Use inhibited area) H'0080 0220 F/F6 –15 Source Select Register 10-28 (FF615S) H'0080 0222 (Use inhibited area) F/F16 –19 Source Select Register 10-29 (FF1619S) H'0080 0224 F/F0 –15 Protect Register 10-30 (FF015P) H'0080 0226 F/F0 –15 Data Register 10-32 (FF015D) H'0080 0228 (Use inhibited area) F/F16 –20 Protect Register 10-30 (FF1620P) H'0080 022A (Use inhibited area) F/F16 –20 Data Register 10-32 (FF1620D) (Use inhibited area) H'0080 0230 TOP0 –5 Interrupt Request Status Register TOP0 –5 Interrupt Request Mask Register 10-39 (TOP05IST) (TOP05IMA) H'0080 0232 TOP6,7 Interrupt Request Mask & Status Register TOP8,9 Interrupt Request Mask & Status Register 10-41 (TOP67IMS) (TOP89IMS) 10-42 H'0080 0234 TIO0 –3 Interrupt Request Mask & Status Register TIO4–7 Interrupt Request Mask & Status Register 10-43 (TIO03IMS) (TIO47IMS) 10-44 H'0080 0236 TIO8,9 Interrupt Request Mask & Status Register TMS0,1 Interrupt Request Mask & Status Register 10-45 (TIO89IMS) (TMS01IMS) 10-46 H'0080 0238 TIN0 –2 Interrupt Request Mask & Status Register TIN3–6 Interrupt Request Mask & Status Register 10-47 (TIN02IMS) (TIN36IMS) 10-48 H'0080 023A TIN7 –11 Interrupt Request Status Register TIN7 –11 Interrupt Request Mask Register 10-49 (TIN711IST) (TIN711IMA) H'0080 023C TIN12 –19 Interrupt Request Status Register TIN12 –19 Interrupt Request Mask Register 10-51 (TIN1219IST) (TIN1219IMA) H'0080 023E TIN20 –23 Interrupt Request Mask & Status Register TIN30–33 Interrupt Request Mask & Status Register 10-53 (TIN2023IMS) (TIN3033IMS) 10-57 H'0080 07D0 Prescaler Register 3 TID0 Control & Prescaler 3 Enable Register 10-12 (PRS3) (TID0PRS3EN) 10-141 H'0080 07D2 TOU0 Interrupt Request Mask Register TOU0 Interrupt Request Status Register 10-58 (TOU0IMA) (TOU0IST) H'0080 07D4 (Use inhibited area) F/F21 –28 Protect Register 10-31 (FF2128P) H'0080 07D6 (Use inhibited area) F/F21 –28 Data Register 10-33 (FF2128D)

32180 Group User’s Manual (Rev.1.0) MJT Common Unit Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 07E0 PWMOFF0 Input Processing Control Register TIN24,25 Input Processing Control Register 10-171 (PWMOFF0CR) (TIN2425CR) 10-25 H'0080 07E2 TIN24,25 Interrupt Request Mask Register TIN24,25 Interrupt Request Status Register 10-53 (TIN2425IMA) (TIN2425IST) H'0080 0BD0 Prescaler Register 4 TID1 Control & Prescaler 4 Enable Register 10-12 (PRS4) (TID1PRS4EN) 10-142 H'0080 0BD2 TOU1 Interrupt Request Mask Register TOU1 Interrupt Request Status Register 10-60 (TOU1IMA) (TOU1IST) H'0080 0BD4 (Use inhibited area) F/F29–36 Protect Register 10-31 (FF2936P) H'0080 0BD6 (Use inhibited area) F/F29–36 Data Register 10-33 (FF2936D) H'0080 0BE0 PWMOFF1 Input Processing Control Register TIN26,27 Input Processing Control Register 10-171 (PWMOFF1CR) (TIN2627CR) 10-25 H'0080 0BE2 TIN26,27 Interrupt Request Mask Register TIN26,27 Interrupt Request Status Register 10-54 (TIN2627IMA) (TIN2627IST) H'0080 0CD0 Prescaler Register 5 TID2 Control & Prescaler 5 Enable Register 10-12 (PRS5) (TID2PRS5EN) 10-143 H'0080 0CD2 TOU2 Interrupt Request Mask Register TOU2 Interrupt Request Status Register 10-61 (TOU2IMA) (TOU2IST) H'0080 0CD4 (Use inhibited area) F/F37–44 Protect Register 10-31 (FF3744P) H'0080 0CD6 (Use inhibited area) F/F37–44 Data Register 10-34 (FF3744D) H'0080 0CE0 PWMOFF2 Input Processing Control Register TIN28,29 Input Processing Control Register 10-172 (PWMOFF2CR) (TIN2829CR) 10-25 H'0080 0CE2 TIN28,29 Interrupt Request Mask Register TIN28,29 Interrupt Request Status Register 10-54 (TIN2829IMA) (TIN2829IST)

32180 Group User’s Manual (Rev.1.0)

10.2.2 Prescaler Unit

The Prescalers PRS0–5 area an 8-bit counter, which generates clocks supplied to each timer (TOP, TIO, TMS, TML, TID and TOU) from the internal peripheral clock (BCLK) divided by 2 (10 MHz when f(BCLK) = 20 MHz). The values of prescaler registers are initialized to H’00 immediately after reset. When the set value of any prescaler register is rewritten, the prescaler starts operating with the new value at the same time it has underflowed. Values H’00 to H’FF can be set in the prescaler register. The prescaler’s divide-by ratio is given by the equation below: Prescaler divide-by ratio = 1 prescaler set value + 1 Prescaler Register 0 (PRS0) <Address: H ’0080 0202> Prescaler Register 1 (PRS1) <Address: H ’0080 0203> Prescaler Register 2 (PRS2) <Address: H ’0080 0204> Prescaler Register 3 (PRS3) <Address: H ’0080 07D0> Prescaler Register 4 (PRS4) <Address: H ’0080 0BD0> Prescaler Register 5 (PRS5) <Address: H ’0080 0CD0> 9 1 01 11 21 31 4 b 1 5b8 123456 b 7b0 PRS0 –PRS5 00000000 <After reset: H’00> b Bit Name Function R W 0–7 PRS0 –PRS5 Set the prescaler divide-by value R W (8–15) Prescaler Prescaler Registers 0–2 start counting immediately after reset. Prescaler Registers 3–5 each are activated by setting the TID0 Control & Prescaler 3 Enable Register, TID1 Control & Prescaler 4 Enable Register or TID2 Control & Prescaler 5 Enable Register’s prescaler-n enable (PRSnEN) bit to "1" (count start), upon which the prescaler register value is reloaded and the prescaler starts counting. For details, see Section 10.7, “TID (Input- Related 16-Bit Timer).” If the prescaler register is accessed for read during operation, the value written into it, not the current count, is read out.

32180 Group User’s Manual (Rev.1.0)

10.2.3 Clock Bus and Input/Output Event Bus Control Unit

(1) Clock bus The clock bus is provided for supplying clock to each timer, and is comprised of four lines of clock bus 0–3. Each timer can use these clock bus signals as clock input signals. The table below lists the signals that can be fed into the clock bus. Table 10.2.1 Acceptable Clock Bus Signals Clock Bus Acceptable Signal

3 TCLK0 input

2 Internal prescaler (PRS2) or TCLK3 input

1 Internal prescaler (PRS1)

0 Internal prescaler (PRS0)

(2) Input event bus The input event bus is provided for supplying a count enable signal or measure capture signal to each timer, and is comprised of four lines of input event bus 0–3. Each timer can use these input event bus signals as enable (or capture) input. Furthermore, they can also be used as request signals to start A-D conversion or DMA transfer. The table below lists the signals that can be fed into the input event bus. Table 10.2.2 Connectable (Acceptable) Input Event Bus Signals Input Event Bus Connectable (Acceptable) Signal (Note 1)

3 TIN3 input, output event bus 2 or TIO7 underflow signal

2 TIN0 input, TIN2 input or TIN4 input

1 TIO6 underflow signal

0 TIO5 underflow signal

Note 1: For the destination (output) to which the input event bus signals are connected, see Figure 10.1.1, “Block Diagram of MJT.” (3) Output event bus The output event bus has the underflow signal from each timer connected to it, and is comprised of four lines of output event bus 0–3. Output event bus signals are connected to output flip-flops, and can also be con- nected to the A-D converter and DMAC. Furthermore, output event bus 2 can be connected to input event bus 3. The table below lists the signals that can be connected to the output event bus. Table 10.2.3 Connectable (Acceptable) Output Event Bus Signals Input Event Bus Connectable (Acceptable) Signal (Note 1)

3 TOP8, TIO3, TIO4 or TIO8 underflow signal

2 TOP9 or TIO2 underflow signal

1 TOP7 or TIO1 underflow signal

0 TOP6 or TIO0 underflow signal

Note 1: For the destination (output) to which the output event bus signals are connected, see Figure 10.1.1, “Block Diagram of MJT.” Note that the signals from each timer to the output event bus (and TIO5, 6 signals to the input event bus) are generated with the timing shown in Table 10.2.4, and not the timing at which signals are output from the timer to the output flip-flop.

32180 Group User’s Manual (Rev.1.0) Table 10.2.4 Timing at Which Signals are Generated to the Output Event Bus by Each Timer Timer Mode Timing at which signals are generated to the output event bus TOP Single-shot output mode When the counter underflows Delayed single-shot output mode When the counter underflows Continuous output mode When the counter underflows TIO(Note 1) Measure clear input mode When the counter underflows Measure free-run input mode When the counter underflows Noise processing input mode When the counter underflows PWM output mode When the counter underflows Single-shot output mode When the counter underflows Delayed single-shot output mode When the counter underflows Continuous output mode When the counter underflows TMS (16-bit measure input) No signals generated TML (32-bit measure input) No signals generated TID Fixed period mode No signals generated Event count mode No signals generated Multiply-by-4 event count mode No signals generated Up/down event count mode No signals generated TOU PWM output mode No signals generated Single-shot PWM mode No signals generated Delayed single-shot output mode No signals generated Single-shot output mode No signals generated Continuous output mode No signals generated Note 1: TIO5–7 output an underflow signal to the input event bus.

32180 Group User’s Manual (Rev.1.0) Figure 10.2.1 Conceptual Diagram of the Clock Bus and Input/Output Event Bus Clock bus Input event bus TCLK0S 3 2 1 0 TCLK0 (P124) TIN0 (P150) TIN2 (P152) TIN3 (P153) TIN4 (P154) TIN5 (P155) TIN6 (P156) PRS1 PRS0 PRS0 –2 : Prescaler 3 2 1 0 3 2 1 0 3 2 1 0 PRS2 TCLK3 (P127) udfTIO 5 udfTIO 6 S Output event bus 0 1 2 3 udfTIO 7 clk en udfTOP 6 clk en udfTOP 7 clk en udfTOP 8 clk en udfTOP 9 udfTIO 0 udfTIO 1 udfTIO 2 udfTIO 3 udfTIO 4 udfTIO 8 0 1 2 3 S : Selector TCLK3S TIN0S TIN2S TIN3S TIN4S TIN5S TIN6S BCLK/2

32180 Group User’s Manual (Rev.1.0) The Clock Bus and Input/Output Event Bus Control Unit has the following registers:  Clock Bus & Input Event Bus Control Register (CKIEBCR)  Output Event Bus Control Register (OEBCR) Clock Bus & Input Event Bus Control Register (CKIEBCR) <Address: H ’0080 0201> 9 1 01 11 21 31 4 b 1 5b8 CKB2SIEB0SIEB1SIEB3S IEB2S 000000 0 0 <After reset: H’00> b Bit Name Function R W 8, 9 IEB3S 00: Select external input 3 (TIN3) R W Input event bus 3 input select bit 01: – ditto – 10: Select output event bus 2 11: Select TIO7 output 10, 11 IEB2S 00: Select external input 0 (TIN0) R W Input event bus 2 input select bit 01: Select external input 2 (TIN2) 10: Select external input 4 (TIN4) 11: – ditto –

12 IEB1S 0: Select external input 5 (TIN5) R W

Input event bus 1 input select bit 1: Select TIO6 output

13 IEB0S 0: Select external input 6 (TIN6) R W

Input event bus 0 input select bit 1: Select TIO5 output 14 No function assigned. Fix to "0". 00

15 CKB2S 0: Select prescaler 2 R W

Clock bus 2 input select bit 1: Select external clock 3 (TCLK3) The CKIEBCR register is used to select the clock source (external input or prescaler) supplied to the clock bus and the count enable/capture signal (external input or output event bus) supplied to the input event bus.

32180 Group User’s Manual (Rev.1.0) Output Event Bus Control Register (OEBCR) <Address: H ’0080 0205> 9 1 01 11 21 31 4 b 1 5b8 OEB0SO EB1SOEB3S O EB2S 00 0 0 0000 <After reset: H’00> b Bit Name Function R W 8, 9 OEB3S 00: Select TOP8 output R W Output event bus 3 input select bit 01: Select TIO3 output 10: Select TIO4 output 11: Select TIO8 output 10 No function assigned. Fix to "0". 00

11 OEB2S 0: Select TOP9 output R W

Output event bus 2 input select bit 1: Select TIO2 output 12 No function assigned. Fix to "0". 00

13 OEB1S 0: Select TOP7 output R W

Output event bus 1 input select bit 1: Select TIO1 output 14 No function assigned. Fix to "0". 00

15 OEB0S 0: Select TOP6 output R W

Output event bus 0 input select bit 1: Select TIO0 output The OEBCR register is used to select the timer (TOP or TIO) whose underflow signal is supplied to the output event bus.

10.2.4 Input Processing Control Unit

The Input Processing Control Unit processes TCLK and TIN input signals to the MJT. In TCLK input processing, it selects the source of TCLK signal, and for external input, it selects the active edge (rising or falling or both) or level (high or low) of the signal, at which to generate the clock signal supplied to the clock bus. In TIN input processing, the unit selects the active edge (rising or falling or both) or level (high or low) of the signal, at which to generate the enable, measure or count source signal for each timer or the signal supplied to each event bus. Following input processing registers are included:  TLCK Input Processing Control Register (TCLKCR)  TIN0–4 Input Processing Control Register (TIN04CR)  TIN5–8 Input Processing Control Register (TIN58CR)  TIN9–11 Input Processing Control Register (TIN911CR)  TIN12–19 Input Processing Control Register (TIN1219CR)  TIN20–23, TIN30–33 Input Processing Control Register (TIN2023_3033CR)  TIN24,25 Input Processing Control Register (TIN2425CR)  TIN26,27 Input Processing Control Register (TIN2627CR)  TIN28,29 Input Processing Control Register (TIN2829CR)

32180 Group User’s Manual (Rev.1.0) Count clock Count clock Count clock BCLK/2 Count clock BCLK/2 TCLK TCLK Count clock TCLK TCLK TCLK Count clock BCLK/2 Item Function BCLK/2 Rising edge Falling edge Both edges Low level High level (1) Functions of TCLK Input Processing Control Registers

32180 Group User’s Manual (Rev.1.0) (2) Functions of TIN Input Processing Control Registers Internal edge signal Internal edge signal Internal edge signal Prescaler output period or TCLK input period TIN TIN Internal edge signal TIN TIN TIN Internal edge signal Prescaler output period or TCLK input period Item Function Rising edge Falling edge Both edges Low level High level

32180 Group User’s Manual (Rev.1.0) TLCK Input Processing Control Register (TCLKCR) <Address: H ’0080 0210> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TCLK3S TCLK2S TCLK1S TCLK0S 0 0 0 0 0 0 0 0 0 000 0 0 00 <After reset: H’0000> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00 2, 3 TCLK3S 00: BCLK/2 R W TCLK3 input processing select bit 01: Rising edge 10: Falling edge 11: Both edges 4 No function assigned. Fix to "0". 00 5–7 TCLK2S 000: Disable input R W TCLK2 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 8 No function assigned. Fix to "0". 00 9–11 TCLK1S 000: Disable input R W TCLK1 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 12,13 No function assigned. Fix to "0". 00 14,15 TCLK0S 00: BCLK/2 R W TCLK0 input processing select bit 01: Rising edge 10: Falling edge 11: Both edges110 Note:  This register must always be accessed in halfwords.

32180 Group User’s Manual (Rev.1.0) TIN0–4 Input Processing Control Register (TIN04CR) <Address: H ’0080 0212> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIN4S TIN 3S TIN2S TIN0S TIN1S 0 000 0 0 0 0 0 0 000000 <After reset: H’0000> b Bit Name Function R W 0 No function assigned. Fix to "0". 00 1–3 TIN4S 000: Disable input R W TIN4 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 4 No function assigned. Fix to "0". 00 5–7 TIN3S 000: Disable input R W TIN3 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 8,9 No function assigned. Fix to "0". 00 10,11 TIN2S 00: Disable input R W TIN2 input processing select bit 01: Rising edge 10: Falling edge 11: Both edges 12,13 TIN1S 00: Disable input R W TIN1 input processing select bit 01: Rising edge 10: Falling edge 11: Both edges 14,15 TIN0S 00: Disable input R W TIN0 input processing select bit 01: Rising edge 10: Falling edge 11: Both edges Note:  This register must always be accessed in halfwords.

32180 Group User’s Manual (Rev.1.0) TIN5–8 Input Processing Control Register (TIN58CR) <Address: H ’0080 0214> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIN8S TIN7S TIN6S TIN5S 0 00 0 0 0 0 0 0 0 00 0 000 <After reset: H’0000> b Bit Name Function R W 0 No function assigned. Fix to "0". 00 1–3 TIN8S 000: Disable input R W TIN8 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 4 No function assigned. Fix to "0". 00 5–7 TIN7S 000: Disable input R W TIN7 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 8 No function assigned. Fix to "0". 00 9–11 TIN6S 000: Disable input R W TIN6 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 12 No function assigned. Fix to "0". 00 13–15 TIN5S 000: Disable input R W TIN5 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level Note:  This register must always be accessed in halfwords.

32180 Group User’s Manual (Rev.1.0) TIN9–11 Input Processing Control Register (TIN911CR) <Address: H ’0080 0216> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIN11S TIN10S TIN9S 0 0 0 0 0 0 0 0 0 0 00 0 000 <After reset: H’0000> b Bit Name Function R W 0–4 No function assigned. Fix to "0". 00 5–7 TIN11S 000: Disable input R W TIN11 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 8 No function assigned. Fix to "0". 00 9–11 TIN10S 000: Disable input R W TIN10 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 12 No function assigned. Fix to "0". 00 13–15 TIN9S 000: Disable input R W TIN9 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level Note:  This register must always be accessed in halfwords.

32180 Group User’s Manual (Rev.1.0) TIN12–19 Input Processing Control Register (TIN1219CR) <Address: H ’0080 0218> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIN19S TIN18S TIN17S TIN16S TIN15S TIN14S TIN13S TIN12S 0000000000000000 <After reset: H’0000> b Bit Name Function R W 0, 1 TIN19S (TIN19 input processing select bit) 00: Disable input R W 2, 3 TIN18S (TIN18 input processing select bit) 01: Rising edge 4, 5 TIN17S (TIN17 input processing select bit) 10: Falling edge 6, 7 TIN16S (TIN16 input processing select bit) 11: Both edges 8, 9 TIN15S (TIN15 input processing select bit) 10, 11 TIN14S (TIN14 input processing select bit) 12, 13 TIN13S (TIN13 input processing select bit) 14, 15 TIN12S (TIN12 input processing select bit) Note:  This register must always be accessed in halfwords. TIN20–23, TIN30–33 Input Processing Control Register (TIN2023_3033CR) <Address: H’0080 021A> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIN33S TIN32S TIN31S TIN30S TIN23S TIN22S TIN21S TIN20S 0000000000000000 <After reset: H’0000> b Bit Name Function R W 0, 1 TIN33S (TIN33 input processing select bit) 00: Disable input R W 2, 3 TIN32S (TIN32 input processing select bit) 01: Rising edge 4, 5 TIN31S (TIN31 input processing select bit) 10: Falling edge 6, 7 TIN30S (TIN30 input processing select bit) 11: Both edges 8, 9 TIN23S (TIN23 input processing select bit) 10, 11 TIN22S (TIN22 input processing select bit) 12, 13 TIN21S (TIN21 input processing select bit) 14, 15 TIN20S (TIN20 input processing select bit) Note:  This register must always be accessed in halfwords.

32180 Group User’s Manual (Rev.1.0) TIN24, 25 Input Processing Control Register (TIN2425CR) <Address: H ’0080 07E1> 9 1 01 11 21 31 4 b15b8 TIN24STIN25S 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12, 13 TIN25S (TIN25 input processing select bit) 00: Disable input R W 14, 15 TIN24S (TIN24 input processing select bit) 01: Rising edge 10: Falling edge 11: Both edges TIN26, 27 Input Processing Control Register (TIN2627CR) <Address: H ’0080 0BE1> 9 1 01 11 21 31 4 b 1 5b8 TIN26STIN27S 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12, 13 TIN27S (TIN27 input processing select bit) 00: Disable input R W 14, 15 TIN26S (TIN26 input processing select bit) 01: Rising edge 10: Falling edge 11: Both edges TIN28, 29 Input Processing Control Register (TIN2829CR) <Address: H ’0080 0CE1> 9 1 01 11 21 31 4 b 1 5b8 TIN28STIN29S 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12, 13 TIN29S (TIN29 input processing select bit) 00: Disable input R W 14, 15 TIN28S (TIN28 input processing select bit) 01: Rising edge 10: Falling edge 11: Both edges

32180 Group User’s Manual (Rev.1.0)

10.2.5 Output Flip-flop Control Unit

The Output Flip-flop Control Unit controls the flip-flops (F/F) provided for each timer. Following flip-flop control registers are included:  F/F6–15 Source Select Register (FF615S)  F/F16–19 Source Select Register (FF1619S)  F/F0–15 Protect Register (FF015P)  F/F16–20 Protect Register (FF1620P)  F/F21–28 Protect Register (FF2128P)  F/F29–36 Protect Register (FF2936P)  F/F37–44 Protect Register (FF3744P)  F/F0–15 Data Register (FF015D)  F/F16–20 Data Register (FF1620D)  F/F21–28 Data Register (FF2128D)  F/F29–36 Data Register (FF2936D)  F/F37–44 Data Register (FF3744D) The timing at which signals are generated to the output flip-flop by each timer are shown in Table 10.2.5. (Note that this timing is different from one at which signals are output from the timer to the output event bus.)

32180 Group User’s Manual (Rev.1.0) Output event bus 0 Data bus F/F protect (FPn) WR Data bus Output control (ON/OFF) TOn Internal edge signal Port operation mode register (PnMOD) F/Fn output data (FDn) TOP/TIO/TOU udf F/F source selection (FSn) Output event bus 1 Output event bus 2 Output event bus 3 F/F F/F F/F Figure 10.2.2 Configuration of the F/F Output Circuit Table 10.2.5 Timing at Which Signals Are Generated to the Output Flip-Flop by Each Timer Timer Mode Timing at which signals are generated to the output flip-flop TOP Single-shot output mode When count is enabled or underflows Delayed single-shot output mode When counter underflows Continuous output mode When count is enabled or underflows TIO Measure clear input mode When counter underflows Measure free-run input mode When counter underflows Noise processing input mode When counter underflows PWM output mode When count is enabled or underflows Single-shot output mode When count is enabled or underflows Delayed single-shot output mode When counter underflows Continuous output mode When count is enabled or underflows TMS (16-bit measure input) No signals generated TML (32-bit measure input) No signals generated TID Fixed period count mode No signals generated Event count mode No signals generated Multiply-by-4 event count mode No signals generated Up/down event count mode No signals generated TOU PWM output mode When count is enabled or underflows Single-shot PWM output mode When counter underflows Delayed single-shot output mode When counter underflows Single-shot output mode When count is enabled or underflows Continuous output mode When count is enabled or underflows

32180 Group User’s Manual (Rev.1.0) F/F6–15 Source Select Register (FF615S) <Address: H ’0080 0220> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 0 0 0 0000000000000 <After reset: H’0000> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00

3 FS15 0: TIO4 output R W

F/F15 source select bit 1: Output event bus 0

4 FS14 0: TIO3 output R W

F/F14 source select bit 1: Output event bus 0

5 FS13 0: TIO2 output R W

F/F13 source select bit 1: Output event bus 3

6 FS12 0: TIO1 output R W

F/F12 source select bit 1: Output event bus 2

7 FS11 0: TIO0 output R W

F/F11 source select bit 1: Output event bus 1 8, 9 FS10 00: TOP10 output R W F/F10 source select bit 01: TOP10 output 10: Output event bus 0 11: Output event bus 1 10, 11 FS9 00: TOP9 output R W F/F9 source select bit 01: TOP9 output 10: Output event bus 0 11: Output event bus 1 12, 13 FS8 00: TOP8 output R W F/F8 source select bit 01: Output event bus 0 10: Output event bus 1 11: Output event bus 2

14 FS7 0: TOP7 output R W

F/F7 source select bit 1: Output event bus 0

15 FS6 0: TOP6 output R W

F/F6 source select bit 1: Output event bus 1 Note:  This register must always be accessed in halfwords.

32180 Group User’s Manual (Rev.1.0) F/F16–19 Source Select Register (FF1619S) <Address: H ’0080 0223> 9 1 01 11 21 31 4 b 1 5b8 FS16FS17FS19 FS18 00000000 <After reset: H’0000> b Bit Name Function R W 8, 9 FS19 00: TIO8 output R W F/F19 source select bit 01: TIO8 output 10: Output event bus 0 11: Output event bus 1 10, 11 FS18 00: TIO7 output R W F/F18 source select bit 01: TIO7 output 10: Output event bus 0 11: Output event bus 1 12, 13 FS17 00: TIO6 output R W F/F17 source select bit 01: TIO6 output 10: Output event bus 0 11: Output event bus 1 14, 15 FS16 00: TIO5 output R W F/F16 source select bit 01: Output event bus 0 10: Output event bus 1 11: Output event bus 3 These registers select the signal source for each output F/F (flip-flop). This signal source can be chosen to be a signal from the internal output bus or an underflow output from each timer.

32180 Group User’s Manual (Rev.1.0) F/F0–15 Protect Register (FF015P) <Address: H ’0080 0224> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 0000000000000000 <After reset: H’0000> b Bit Name Function R W

0 FP15 (F/F15 protect bit) 0: Enable write to F/F output bit R W

1 FP14 (F/F14 protect bit) 1: Disable write to F/F output bit

2 FP13 (F/F13 protect bit)

3 FP12 (F/F12 protect bit)

4 FP11 (F/F11 protect bit)

5 FP10 (F/F10 protect bit)

6 FP9 (F/F9 protect bit)

7 FP8 (F/F8 protect bit)

8 FP7 (F/F7 protect bit)

9 FP6 (F/F6 protect bit)

10 FP5 (F/F5 protect bit)

11 FP4 (F/F4 protect bit)

12 FP3 (F/F3 protect bit)

13 FP2 (F/F2 protect bit)

14 FP1 (F/F1 protect bit)

15 FP0 (F/F0 protect bit)

Note:  This register must always be accessed in halfwords. F/F16–20 Protect Register (FF1620P) <Address: H ’0080 0229> 9 1 01 11 21 31 4 b 1 5b8 FP16FP17FP20 FP19 FP18 000000 0 0 <After reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 FP20 (F/F20 protect bit) 0: Enable write to F/F output bit R W

12 FP19 (F/F19 protect bit) 1: Disable write to F/F output bit

13 FP18 (F/F18 protect bit)

14 FP17 (F/F17 protect bit)

15 FP16 (F/F16 protect bit)

32180 Group User’s Manual (Rev.1.0) F/F21–28 Protect Register (FF2128P) <Address: H ’0080 07D5> 9 1 01 11 21 31 4 b 1 5b8 FP28FP27FP24 FP25 FP26FP21 FP22 FP23 00000000 <After reset: H’00> b Bit Name Function R W

8 FP21 (F/F21 protect bit) 0: Enable write to F/F output bit R W

9 FP22 (F/F22 protect bit) 1: Disable write to F/F output bit

10 FP23 (F/F23 protect bit)

11 FP24 (F/F24 protect bit)

12 FP25 (F/F25 protect bit)

13 FP26 (F/F26 protect bit)

14 FP27 (F/F27 protect bit)

15 FP28 (F/F28 protect bit)

F/F29–36 Protect Register (FF2936P) <Address: H ’0080 0BD5> 9 1 01 11 21 31 4 b 1 5b8 FP36FP35FP32 FP33 FP34FP29 FP30 FP31 00000000 <After reset: H’00> b Bit Name Function R W

8 FP29 (F/F29 protect bit) 0: Enable write to F/F output bit R W

9 FP30 (F/F30 protect bit) 1: Disable write to F/F output bit

10 FP31 (F/F31 protect bit)

11 FP32 (F/F32 protect bit)

12 FP33 (F/F33 protect bit)

13 FP34 (F/F34 protect bit)

14 FP35 (F/F35 protect bit)

15 FP36 (F/F36 protect bit)

F/F37–44 Protect Register (FF3744P) <Address: H ’0080 0CD5> 9 1 01 11 21 31 4 b 1 5b8 FP44FP43FP40 FP41 FP42FP37 FP38 FP39 00000000 <After reset: H’00> b Bit Name Function R W

8 FP37 (F/F37 protect bit) 0: Enable write to F/F output bit R W

9 FP38 (F/F38 protect bit) 1: Disable write to F/F output bit

10 FP39 (F/F39 protect bit)

11 FP40 (F/F40 protect bit)

12 FP41 (F/F41 protect bit)

13 FP42 (F/F42 protect bit)

14 FP43 (F/F43 protect bit)

15 FP44 (F/F44 protect bit)

These registers control write to each output F/F (flip-flop) by enabling or disabling. If write to any output F/F is disabled, writing to the F/F data register has no effect.

32180 Group User’s Manual (Rev.1.0) F/F0–15 Data Register (FF015D) <Address: H ’0080 0226> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 FD15 FD14 FD13 FD12 FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 0000000000000000 <After reset: H’0000> b Bit Name Function R W

0 FD15 (F/F15 output data bit) 0: F/F output data = 0 R W

1 FD14 (F/F14 output data bit) 1: F/F output data = 1

2 FD13 (F/F13 output data bit)

3 FD12 (F/F12 output data bit)

4 FD11 (F/F11 output data bit)

5 FD10 (F/F10 output data bit)

6 FD9 (F/F9 output data bit)

7 FD8 (F/F8 output data bit)

8 FD7 (F/F7 output data bit)

9 FD6 (F/F6 output data bit)

10 FD5 (F/F5 output data bit)

11 FD4 (F/F4 output data bit)

12 FD3 (F/F3 output data bit)

13 FD2 (F/F2 output data bit)

14 FD1 (F/F1 output data bit)

15 FD0 (F/F0 output data bit)

Note:  This register must always be accessed in halfwords. F/F16–20 Data Register (FF1620D) <Address: H ’0080 022B> 9 1 01 11 21 31 4 b 1 5b8 FD16FD17FD20 FD19 FD18 000000 0 0 <After reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 FD20 (F/F20 output data bit) 0: F/F output data = 0 R W

12 FD19 (F/F19 output data bit) 1: F/F output data = 1

13 FD18 (F/F18 output data bit)

14 FD17 (F/F17 output data bit)

15 FD16 (F/F16 output data bit)

32180 Group User’s Manual (Rev.1.0) F/F21–28 Data Register (FF2128D) <Address: H ’0080 07D7> 9 1 01 11 21 31 4 b 1 5b8 FD28FD27FD24 FD25 FD26FD21 FD22 FD23 00000000 <After reset: H’00> b Bit Name Function R W

8 FD21 (F/F21 output data bit) 0: F/F output data = 0 R W

9 FD22 (F/F22 output data bit) 1: F/F output data = 1

10 FD23 (F/F23 output data bit)

11 FD24 (F/F24 output data bit)

12 FD25 (F/F25 output data bit)

13 FD26 (F/F26 output data bit)

14 FD27 (F/F27 output data bit)

15 FD28 (F/F28 output data bit)

F/F29–36 Data Register (FF2936D) <Address: H ’0080 0BD7> 9 1 01 11 21 31 4 b 1 5b8 FD36FD35FD32 FD33 FD34FD29 FD30 FD31 00000000 <After reset: H’00> b Bit Name Function R W

8 FD29 (F/F29 output data bit) 0: F/F output data = 0 R W

9 FD30 (F/F30 output data bit) 1: F/F output data = 1

10 FD31 (F/F31 output data bit)

11 FD32 (F/F32 output data bit)

12 FD33 (F/F33 output data bit)

13 FD34 (F/F34 output data bit)

14 FD35 (F/F35 output data bit)

15 FD36 (F/F36 output data bit)

32180 Group User’s Manual (Rev.1.0) F/F37–44 Data Register (FF3744D) <Address: H ’0080 0CD7> 9 1 01 11 21 31 4 b 1 5b8 FD44FD43FD40 FD41 FD42FD37 FD38 FD39 00000000 <After reset: H’00> b Bit Name Function R W

8 FD37 (F/F37 output data bit) 0: F/F output data = 0 R W

9 FD38 (F/F38 output data bit) 1: F/F output data = 1

10 FD39 (F/F39 output data bit)

11 FD40 (F/F40 output data bit)

12 FD41 (F/F41 output data bit)

13 FD42 (F/F42 output data bit)

14 FD43 (F/F43 output data bit)

15 FD44 (F/F44 output data bit)

These registers are used to set data in each output F/F (flip-flop). Although F/F output normally changes with timer output, setting data 0 or 1 in this register allows to produce desired output from any F/F. The F/F data register can only be operated on when the F/F protect register described earlier is enabled for write.

32180 Group User’s Manual (Rev.1.0)

10.2.6 Interrupt Control Unit

The Interrupt Control Unit controls the interrupt request signals output to the Interrupt Controller by each timer. Following timer interrupt control registers are provided for each timer:  TOP0–5 Interrupt Request Status Register (TOP05IST)  TOP0–5 Interrupt Request Mask Register (TOP05IMA)  TOP6,7 Interrupt Request Mask & Status Register (TOP67IMS)  TOP8,9 Interrupt Request Mask & Status Register (TOP89IMS)  TIO0–3 Interrupt Request Mask & Status Register (TIO03IMS)  TIO4–7 Interrupt Request Mask & Status Register (TIO47IMS)  TIO8,9 Interrupt Request Mask & Status Register (TIO89IMS)  TMS0,1 Interrupt Request Mask & Status Register (TMS01IMS)  TIN0–2 Interrupt Request Mask & Status Register (TIN02IMS)  TIN3–6 Interrupt Request Mask & Status Register (TIN36IMS)  TIN7–11 Interrupt Request Status Register (TIN711IST)  TIN7–11 Interrupt Request Mask Register (TIN711IMA)  TIN12–19 Interrupt Request Status Register (TIN1219IST)  TIN12–19 Interrupt Request Mask Register (TIN1219IMA)  TIN20–23 Interrupt Request Mask & Status Register (TIN2023IMS)  TIN24,25 Interrupt Request Mask Register (TIN2425IMA)  TIN24,25 Interrupt Request Status Register (TIN2425IST)  TIN26,27 Interrupt Request Mask Register (TIN2627IMA)  TIN26,27 Interrupt Request Status Register (TIN2627IST)  TIN28,29 Interrupt Request Mask Register (TIN2829IMA)  TIN28,29 Interrupt Request Status Register (TIN2829IST)  TIN30–33 Interrupt Request Mask & Status Register (TIN3033IMS)  TOU0 Interrupt Request Mask Register (TOU0IMA)  TOU0 Interrupt Request Status Register (TOU0IST)  TOU1 Interrupt Request Mask Register (TOU1IMA)  TOU1 Interrupt Request Status Register (TOU1IST)  TOU2 Interrupt Request Mask Register (TOU2IMA)  TOU2 Interrupt Request Status Register (TOU2IST) For interrupts which have only one interrupt request source in the interrupt vector table, no interrupt control registers are included in the timer, and the interrupt request status flags are automatically managed within the Interrupt Controller. For details, see Chapter 5, “Interrupt Controller.”  TOP10 TOP10 Output Interrupt Request (IRQ5)  TID0 TID0 Output Interrupt Request (IRQ14)  TID1 TID1 Output Interrupt Request (IRQ15)  TID2 TID2 Output Interrupt Request (IRQ17)

32180 Group User’s Manual (Rev.1.0) To the Interrupt Controller Timer or TIN input interrupt request Interrupt request status Data bus Set Group interrupt Interrupt request enabled clear F/F F/F Data = 0 Figure 10.2.3 Interrupt Request Status and Mask Registers For interrupts which have two or more interrupt sources in the interrupt vector table, interrupt control registers are included, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in the Interrupt Controller only serve as a bit to determine interrupt requests from interrupt-enabled sources and cannot be accessed for write. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt request mask bit, it can be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupts within the grouped interrupt request. Set this bit to "0" to enable interrupt requests or "1" to disable interrupt requests.

32180 Group User’s Manual (Rev.1.0) b4 5 b7 Interrupt request status Initial state Event occurs on bit 6 Interrupt request Event occurs on bit 4 Only bit 6 cleared Bit 4 data retained b4 5 b7 1 1 0 1 Write to the interrupt request status Example for clearing interrupt request status 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 Program example ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */  To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. b4 5 6 b7 Interrupt request status Event occurs on bit 6 Event occurs on bit 4 Only bit 6 cleared Bit 4 also cleared 0 0 1 0 1 0 1 0 0 0 0 0 Read 0 0 1 0 0 0 0 0 Clear bit 6 (ANDing with 1101) Write ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */ Figure 10.2.4 Example for Clearing Interrupt Request Status

32180 Group User’s Manual (Rev.1.0) The table below shows the relationship between the interrupt request signals generated by multijunction timers and the interrupt sources input to the Interrupt Controller (ICU). Table 10.2.6 Interrupt Request Signals Generated by MJT Signal Name Generated by Interrupt Request Source (Note 1) No. of ICU I nput Sources IRQ0 TIO0, TIO1, TIO2, TIO3 TIO0 –3 output interrupt 4 IRQ1 TOP6, TOP7 TOP6, 7 output interrupt 2 IRQ2 TOP0, TOP1, TOP2, TOP3, TOP4, TOP5 TOP0 –5 output interrupt 6 IRQ3 TIO8, TIO9 TIO8, 9 output interrupt 2 IRQ4 TIO4, TIO5, TIO6, TIO7 TIO4 –7 output interrupt 4 IRQ6 TOP8, TOP9 TOP8, 9 output interrupt 2 IRQ7 TMS0, TMS1 TMS0, 1 output interrupt 2 IRQ8 TIN7, TIN8, TIN9, TIN10, TIN11 TIN7 –11 input interrupt 5 IRQ9 TIN0, TIN1, TIN2 TIN0 –2 input interrupt 3 IRQ10 TIN12, TIN13, TIN14, TIN15, TIN16, TIN17, TIN12 –19 input interrupt 8 TIN18, TIN19 IRQ11 TIN20, TIN21, TIN22, TIN23, TIN24, TIN25 TIN20 –29 input interrupt 10 TIN26, TIN27, TIN28, TIN29 IRQ12 TIN3, TIN4, TIN5, TIN6 TIN3 –6 input interrupt 4 IRQ13 TOU0_0, TOU0_1, TOU0_2, TOU0_3 TOU0 output interrupt 8 TOU0_4, TOU0_5, TOU0_6, TOU0_7 IRQ16 TOU1_0, TOU1_1, TOU1_2, TOU1_3 TOU1 + TOU2 output interrupt 16 TOU1_4, TOU1_5, TOU1_6, TOU1_7 TOU2_0, TOU2_1, TOU2_2, TOU2_3 TOU2_4, TOU2_5, TOU2_6, TOU2_7 IRQ18 TIN30, TIN31, TIN32, TIN33 TIN30 –33 input interrupt 4 Note 1: See Chapter 5, “Interrupt Controller (ICU).” Note:  TOP10 and TID0–2 have only one interrupt source in each interrupt group, so that their status and mask registers are nonexistent in the MJT interrupt control registers. (They are controlled directly by the Interrupt Controller.)

32180 Group User’s Manual (Rev.1.0) TOP0 –5 Interrupt Request Status Register (TOP05IST) <Address: H ’0080 0230> 123456 b 7b0 TOPIS0TOPIS1TOPIS4TOPIS5 TOPIS3 TOPIS2 0000000 0 <After reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00

2 TOPIS5 (TOP5 interrupt request status bit) 0: Interrupt not requested R(Note 1)

3 TOPIS4 (TOP4 interrupt request status bit) 1: Interrupt requested

4 TOPIS3 (TOP3 interrupt request status bit)

5 TOPIS2 interrupt request status bit)

6 TOPIS1 interrupt request status bit)

7 TOPIS0 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TOP0 –5 Interrupt Request Mask Register (TOP05IMA) <Address: H ’0080 0231> 9 1 01 11 21 31 4 b 1 5b8 TOPIM0TOPIM1TOPIM4TOPIM5 TOPIM3 TOPIM2 0000000 0 <After reset: H’00> b Bit Name Function R W 8, 9 No function assigned. Fix to "0". 00

10 TOPIM5 (TOP5 interrupt request mask bit) 0: Enable interrupt request R W

11 TOPIM4 (TOP4 interrupt request mask bit) 1: Mask (disable) interrupt request

12 TOPIM3 (TOP3 interrupt request mask bit)

13 TOPIM2 (TOP2 interrupt request mask bit)

14 TOPIM1 (TOP1 interrupt request mask bit)

15 TOPIM0 (TOP0 interrupt request mask bit)

32180 Group User’s Manual (Rev.1.0) TOP0-5 output interrupt request IRQ2 Data bus TOPIS5 F/F TOPIM5 F/Fb10 TOPIS4 F/F TOPIM4 F/Fb11 b4 TOPIS3 F/F TOPIM3 F/Fb12 b5 TOPIS2 F/F TOPIM2 F/Fb13 b6 TOPIS1 F/F TOPIM1 F/Fb14 TOPIS0 F/F TOPIM0 F/Fb15 (Level) 6-source inputs TOP05IST <H'0080 0230> TOP05IMA <H'0080 0231> TOP5udf TOP4udf TOP3udf TOP2udf TOP1udf TOP0udf Figure 10.2.5 Block Diagram of TOP0–5 Output Interrupt Request

32180 Group User’s Manual (Rev.1.0) TOP6,7 Interrupt Request Mask & Status Register (TOP67IMS) <Address: H ’0080 0232> 123456 b 7b0 TOPIM6TOPIM7TO PIS6TO PIS7 00 000 0 0 0 <After reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00

2 TOPIS7 (TOP7 interrupt request status bit) 0: Interrupt not requested R(Note 1)

3 TOPIS6 (TOP6 interrupt request status bit) 1: Interrupt requested

4, 5 No function assigned. Fix to "0". 00

6 TOPIM7 (TOP7 interrupt request mask bit) 0: Enable interrupt request R W

7 TOPIM6 (TOP6 interrupt request mask bit) 1: Mask (disable) interrupt request

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TOP6,7 output interrupt request IRQ1 Data bus TOPIS7 F/F TOPIM7 F/Fb6 TOPIS6 F/F TOPIM6 F/Fb7 (Level) 2-source inputs TOP67IMS <H'0080 0232> TOP7udf TOP6udf Figure 10.2.6 Block Diagram of TOP6,7 Output Interrupt Request

32180 Group User’s Manual (Rev.1.0) TOP8,9 Interrupt Request Mask & Status Register (TOP89IMS) <Address: H ’0080 0233> 9 1 01 11 21 31 4 b 1 5b8 TOPIM8TOPIM9TO PIS8TO PIS9 00 000 0 0 0 <After reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00

2 TOPIS9 (TOP9 interrupt request status bit) 0: Interrupt not requested R(Note 1)

3 TOPIS8 (TOP8 interrupt request status bit) 1: Interrupt requested

4, 5 No function assigned. Fix to "0". 00

6 TOPIM9 (TOP9 interrupt request mask bit) 0: Enable interrupt request R W

7 TOPIM8 (TOP8 interrupt request mask bit) 1: Mask (disable) interrupt request

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Note:  TOP10 has only one interrupt source in the interrupt group, so that its status and mask registers are nonexistent in the MJT interrupt control registers. (They are controlled directly by the Interrupt Controller.) b10 TOPIS9 F/F TOPIM9 F/Fb14 b11 TOPIS8 F/F TOPIM8 F/Fb15 TOP8,9 output interrupt request IRQ6(Level) 2-source inputs TOP89IMS <H'0080 0233> Data bus TOP9udf TOP8udf Figure 10.2.7 Block Diagram of TOP8,9 Output Interrupt Request

32180 Group User’s Manual (Rev.1.0) TIO0–3 Interrupt Request Mask & Status Register (TIO03IMS) <Address: H ’0080 0234> 123456 b 7b0 TIOIM0TIOIM1TIOIS0TIOIS3 TIOIS2 TIOIS1 TIOIM3 TIOIM2 00000000 <After reset: H’00> b Bit Name Function R W

0 TIOIS3 (TIO3 interrupt request status bit) 0: Interrupt not requested R(Note 1)

1 TIOIS2 (TIO2 interrupt request status bit) 1: Interrupt requested

2 TIOIS1 (TIO1 interrupt request status bit)

3 TIOIS0 (TIO0 interrupt request status bit)

4 TIOIM3 (TIO3 interrupt request mask bit) 0: Enable interrupt request R W

5 TIOIM2 (TIO2 interrupt request mask bit) 1: Mask (disable) interrupt request

6 TIOIM1 (TIO1 interrupt request mask bit)

7 TIOIM0 (TIO0 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIO0–3 output interrupt request IRQ0 Data bus TIOIS3 F/F TIOIM3 F/Fb4 TIOIS2 F/F TIOIM2 F/Fb5 b2 TIOIS1 F/F TIOIM1 F/Fb6 b3 TIOIS0 F/F TIOIM0 F/Fb7 (Level) 2-source inputs TIO03IMS <H'0080 0234> TIO3udf TIO2udf TIO1udf TIO0udf Figure 10.2.8 Block Diagram of TIO0–3 Output Interrupt Request

32180 Group User’s Manual (Rev.1.0) TIO4–7 Interrupt Request Mask & Status Register (TIO47IMS) <Address: H ’0080 0235> 9 1 01 11 21 31 4 b 1 5b8 TIOIM4TIOIM5TIOIS4TIOIS7 TIOIS6 TIOIS5 TIOIM7 TIOIM6 00000000 <After reset: H’00> b Bit Name Function R W

8 TIOIS7 (TIO7 interrupt request status bit) 0: Interrupt not requested R(Note 1)

9 TIOIS6 (TIO6 interrupt request status bit) 1: Interrupt requested

10 TIOIS5 (TIO5 interrupt request status bit)

11 TIOIS4 (TIO4 interrupt request status bit)

12 TIOIM7 (TIO7 interrupt request mask bit) 0: Enable interrupt request R W

13 TIOIM6 (TIO6 interrupt request mask bit) 1: Mask (disable) interrupt request

14 TIOIM5 (TIO5 interrupt request mask bit)

15 TIOIM4 (TIO4 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIO4–7 output interrupt request IRQ4 Data bus TIOIS7 F/F TIOIM7 F/Fb12 b9 TIOIS6 F/F TIOIM6 F/Fb13 b10 TIOIS5 F/F TIOIM5 F/Fb14 b11 TIOIS4 F/F TIOIM4 F/Fb15 (Level) 4-source inputs TIO47IMS <H'0080 0235> TIO7udf TIO6udf TIO5udf TIO4udf Figure 10.2.9 Block Diagram of TIO4–7 Output Interrupt Request

32180 Group User’s Manual (Rev.1.0) TIO8,9 Interrupt Request Mask & Status Register (TIO89IMS) <Address: H ’0080 0236> 123456 b 7b0 TIOIM8TIOIM9TIO IS8TIO IS9 00 000 0 0 0 <After reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00

2 TIOIS9 (TIO9 interrupt request status bit) 0: Interrupt not requested R(Note 1)

3 TIOIS8 (TIO8 interrupt request status bit) 1: Interrupt requested

4, 5 No function assigned. Fix to "0". 00

6 TIOIM9 (TIO9 interrupt request mask bit) 0: Enable interrupt request R W

7 TIOIM8 (TIO8 interrupt request mask bit) 1: Mask (disable) interrupt request

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIO8, 9 output interrupt request IRQ3 Data bus TIOIS9 F/F TIOIM9 F/Fb6 TIOIS8 F/F TIOIM8 F/Fb7 (Level) 2-source inputs TIO89IMS <H'0080 0236> TIO9udf TIO8udf Figure 10.2.10 Block Diagram of TIO8,9 Output Interrupt Request

32180 Group User’s Manual (Rev.1.0) TMS0,1 Interrupt Request Mask & Status Register (TMS01IMS) <Address: H ’0080 0237> 9 1 01 11 21 31 4 b 1 5b8 TMSIM0TMSIM1TMSIS 0TMSIS 1 00 000 0 0 0 <After reset: H’00> b Bit Name Function R W 8, 9 No function assigned. Fix to "0". 00

10 TMSIS1 (TMS1 interrupt request status bit) 0: Interrupt not requested R(Note 1)

11 TMSIS0 (TMS0 interrupt request status bit) 1: Interrupt requested

12, 13 No function assigned. Fix to "0". 00

14 TMSIM1 (TMS1 interrupt request mask bit) 0: Enable interrupt request R W

15 TMSIM0 (TMS0 interrupt request mask bit) 1: Mask (disable) interrupt request

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TMS0, 1 output interrupt request IRQ7 Data bus b10 TMSIS1 F/F TMSIM1 F/Fb14 b11 TMSIS0 F/F TMSIM0 F/Fb15 (Level) 2-source inputs TMS01IMS <H'0080 0237> TMS1ovf TMS0ovf Figure 10.2.11 Block Diagram of TMS0,1 Output Interrupt Request

32180 Group User’s Manual (Rev.1.0) TIN0–2 Interrupt Request Mask & Status Register (TIN02IMS) <Address: H ’0080 0238> 123456 b 7b0 TINIM0TINIM1TINIM2TINIS0TINIS1TINIS2 000 0000 0 <After reset: H’00> b Bit Name Function R W 0 No function assigned. Fix to "0". 00

1 TINIS2 (TIN2 interrupt request status bit) 0: Interrupt not requested R(Note 1)

2 TINIS1 (TIN1 interrupt request status bit) 1: Interrupt requested

3 TINIS0 (TIN0 interrupt request status bit)

4 No function assigned. Fix to "0". 00

5 TINIM2 (TIN2 interrupt request mask bit) 0: Enable interrupt request R W

6 TINIM1 (TIN1 interrupt request mask bit) 1: Mask (disable) interrupt request

7 TINIM0 (TIN0 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Figure 10.2.12 Block Diagram of TIN0–2 Input Interrupt Request TIN0–2 input interrupt request IRQ9 Data bus TINIS2 F/F TINIM2 F/Fb5 TINIS1 F/F TINIM1 F/Fb6 b3 TINIS0 F/F TINIM0 F/Fb7 (Level) 3-source inputs TIN02IMS <H'0080 0238> TIN2edge TIN1edge TIN0edge

32180 Group User’s Manual (Rev.1.0) TIN3–6 Interrupt Request Mask & Status Register (TIN36IMS) <Address: H ’0080 0239> 9 1 01 11 21 31 4 b 1 5b8 TINIM3TINIM4TINIM5TINIM6TINIS3TINIS4TINIS5TINIS6 00000000 <After reset: H’00> b Bit Name Function R W

8 TINIS6 (TIN6 interrupt request status bit) 0: Interrupt not requested R(Note 1)

9 TINIS5 (TIN5 interrupt request status bit) 1: Interrupt requested

10 TINIS4 (TIN4 interrupt request status bit)

11 TINIS3 (TIN3 interrupt request status bit)

12 TINIM6 (TIN6 interrupt request mask bit) 0: Enable interrupt request R W

13 TINIM5 (TIN5 interrupt request mask bit) 1: Mask (disable) interrupt request

14 TINIM4 (TIN4 interrupt request mask bit)

15 TINIM3 (TIN3 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Figure 10.2.13 Block Diagram of TIN3–6 Input Interrupt Request TIN3–6 input interrupt request IRQ12 Data bus TINIS6 F/F TINIM6 F/Fb12 TINIS5 F/F TINIM5 F/Fb13 b10 TINIS4 F/F TINIM4 F/Fb14 (Level) 4-source inputs TIN36IMS <H'0080 0239> TIN6edge TIN5edge TIN4edge b11 TINIS3 F/F TINIM3 F/Fb15 TIN3edge

32180 Group User’s Manual (Rev.1.0) TIN7–11 Interrupt Request Status Register (TIN711IST) <Address: H ’0080 023A> 123456 b 7b0 TINIS7TINIS8TINIS9TINIS10TINIS11 000000 0 0 <After reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00

3 TINIS11 (TIN11 interrupt request status bit) 0: Interrupt not requested R(Note 1)

4 TINIS10 (TIN10 interrupt request status bit) 1: Interrupt requested

5 TINIS9 (TIN9 interrupt request status bit)

6 TINIS8 (TIN8 interrupt request status bit)

7 TINIS7 (TIN7 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIN7–11 Interrupt Request Mask Register (TIN711IMA) <Address: H ’0080 023B> 9 1 01 11 21 31 4 b 1 5b8 TINIM7TINIM8TINIM9TINIM10TINIM11 000000 0 0 <After reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 TINIM11 (TIN11 interrupt request mask bit) 0: Enable interrupt request R W

12 TINIM10 (TIN10 interrupt request mask bit) 1: Mask (disable) interrupt request

13 TINIM9 (TIN9 interrupt request mask bit)

14 TINIM8 (TIN8 interrupt request mask bit)

15 TINIM7 (TIN7 interrupt request mask bit)

32180 Group User’s Manual (Rev.1.0) TIN7–11 input interrupt request IRQ8 Data bus TINIS11 F/F TINIM11 F/Fb11 TINIS10 F/F TINIM4 F/Fb12 b5 TINIS9 F/F TINIM9 F/Fb13 b6 TINIS8 F/F TINIM8 F/Fb14 b7 TINIS7 F/F TINIM7 F/Fb15 (Level) 5-source inputs TIN711IST <H'0080 023A> TIN711IMA<H'0080 023B> TIN11edge TIN10edge TIN9edge TIN8edge TIN7edge Figure 10.2.14 Block Diagram of TIN7–11 Input Interrupt Request

32180 Group User’s Manual (Rev.1.0) TIN12–19 Interrupt Request Status Register (TIN1219IST) <Address: H ’0080 023C> 123456 b 7b0 TINIS12TINIS13TINIS14TINIS15TINIS16TINIS17TINIS18TINIS19 00000000 <After reset: H’00> b Bit Name Function R W

0 TINIS19 (TIN19 interrupt request status bit) 0: Interrupt not requested R(Note 1)

1 TINIS18 (TIN18 interrupt request status bit) 1: Interrupt requested

2 TINIS17 (TIN17 interrupt request status bit)

3 TINIS16 (TIN16 interrupt request status bit)

4 TINIS15 (TIN15 interrupt request status bit)

5 TINIS14 (TIN14 interrupt request status bit)

6 TINIS13 (TIN13 interrupt request status bit)

7 TINIS12 (TIN12 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIN12–19 Interrupt Request Mask Register (TIN1219IMA) <Address: H ’0080 023D> 9 1 01 11 21 31 4 b 1 5b8 TINIM12TINIM13TINIM14TINIM15TINIM16TINIM17TINIM18TINIM19 00000000 <After reset: H’00> b Bit Name Function R W

8 TINIM19 (TIN19 interrupt request mask bit) 0: Enable interrupt request R W

9 TINIM18 (TIN18 interrupt request mask bit) 1: Mask (disable) interrupt request

10 TINIM17 (TIN17 interrupt request mask bit)

11 TINIM16 (TIN16 interrupt request mask bit)

12 TINIM15 (TIN15 interrupt request mask bit)

13 TINIM14 (TIN14 interrupt request mask bit)

14 TINIM13 (TIN13 interrupt request mask bit)

15 TINIM12 (TIN12 interrupt request mask bit)

32180 Group User’s Manual (Rev.1.0) TIN12–19 input interrupt request IRQ10 Data bus TINIS19 F/F TINIM19 F/Fb8 TINIS18 F/F TINIM18 F/Fb9 b2 TINIS17 F/F TINIM17 F/Fb10 b3 TINIS16 F/F TINIM16 F/Fb11 b4 TINIS15 F/F TINIM15 F/Fb12 (Level) 8-source inputs TIN1219IST <H'0080 023C> TIN1219IMA <H'0080 023D> TIN19edge TIN18edge TIN17edge TIN16edge TIN15edge TINIS14 F/F TINIM14 F/Fb13 TINIS13 F/F TINIM13 F/Fb14 b7 TINIS12 F/F TINIM12 F/Fb15 TIN14edge TIN13edge TIN12edge Figure 10.2.15 Block Diagram of TIN12–19 Input Interrupt Request

32180 Group User’s Manual (Rev.1.0) TIN20–23 Interrupt Request Mask & Status Register (TIN2023IMS) <Address: H ’0080 023E> 123456 b 7b0 TINIM20TINIM21TINIM22TINIM23TINIS20TINIS21TINIS22TINIS23 00000000 <After reset: H’00> b Bit Name Function R W

0 TINIS23 (TIN23 interrupt request status bit) 0: Interrupt not requested R(Note 1)

1 TINIS22 (TIN22 interrupt request status bit) 1: Interrupt requested

2 TINIS21 (TIN21 interrupt request status bit)

3 TINIS20 (TIN20 interrupt request status bit)

4 TINIM23 (TIN23 interrupt request mask bit) 0: Enable interrupt request R W

5 TINIM22 (TIN22 interrupt request mask bit) 1: Mask (disable) interrupt request

6 TINIM21 (TIN21 interrupt request mask bit)

7 TINIM20 (TIN20 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIN24, 25 Interrupt Request Mask Register (TIN2425IMA) <Address: H ’0080 07E2> b 0123456b 7 TINIM24 TINIM25 0 0 0 0 0 0 00 <After reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00

6 TINIM24 (TIN24 interrupt request mask bit) 0: Enable interrupt request R W

7 TINIM25 (TIN25 interrupt request mask bit) 1: Mask (disable) interrupt request

TIN24, 25 Interrupt Request Status Register (TIN2425IST) <Address: H ’0080 023A> b8 9 10 11 12 13 14 b15 TINIS24 TINIS25 0 0 0 0 0 0 00 <After reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0". 00

14 TINIS24 (TIN24 interrupt request status bit) 0: Interrupt not requested R(Note 1)

15 TINIS25 (TIN25 interrupt request status bit) 1: Interrupt requested

32180 Group User’s Manual (Rev.1.0) TIN26, 27 Interrupt Request Mask Register (TIN2627IMA) <Address: H ’0080 0BE2> b 0123456b 7 TINIM26 TINIM27 0 0 0 0 0 0 00 <After reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00

6 TINIM26 (TIN26 interrupt request mask bit) 0: Enable interrupt request R W

7 TINIM27 (TIN27 interrupt request mask bit) 1: Mask (disable) interrupt request

TIN26, 27 Interrupt Request Status Register (TIN2627IST) <Address: H ’0080 0BE3> b8 9 10 11 12 13 14 b15 TINIS26 TINIS27 0 0 0 0 0 0 00 <After reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0". 00

14 TINIS26 (TIN26 interrupt request status bit) 0: Interrupt not requested R(Note 1)

15 TINIS27 (TIN27 interrupt request status bit) 1: Interrupt requested

TIN28, 29 Interrupt Request Mask Register (TIN2829IMA) <Address: H ’0080 0CE2> b 0123456b 7 TINIM28 TINIM29 0 0 0 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00

6 TINIM28 (TIN28 interrupt request mask bit) 0: Enable interrupt request R W

7 TINIM29 (TIN29 interrupt request mask bit) 1: Mask (disable) interrupt request

TIN28, 29 Interrupt Request Status Register (TIN2829IST) <Address: H ’0080 023A> b8 9 10 11 12 13 14 b15 TINIS28 TINIS29 0 0 0 0 0 0 00 <After reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0". 00

14 TINIS28 (TIN28 interrupt request status bit) 0: Interrupt not requested R(Note 1)

15 TINIS29 (TIN29 interrupt request status bit) 1: Interrupt requested

32180 Group User’s Manual (Rev.1.0) TIN20–29 input interrupt request IRQ11 Data bus b15 TINIS29 F/F TINIM29 F/Fb7 b14 TINIS28 F/F TINIM28 F/Fb6 b15 TINIS27 F/F TINIM27 F/Fb7 b15 TINIS26 F/F TINIM26 F/Fb6 b15 TINIS25 F/F TINIM25 F/Fb7 (Level) 10-source inputs TIN2425IST<H'0080 07E3> TIN2425IMA<H'0080 07E2> TIN2627IST<H'0080 0BE3> TIN2627IMA<H'0080 0BE2> TIN2829IST<H'0080 0CE3> TIN2829IMA<H'0080 0CE2> TIN29edge TIN28edge TIN27edge TIN26edge TIN25edge b14 TINIS24 F/F TINIM24 F/Fb6 TIN24edge ~To the remaining 4-input sources in the next page Figure 10.2.16 Block Diagram of TIN20–29 Input Interrupt Request (1/2)

32180 Group User’s Manual (Rev.1.0) To the preceding page Data bus TINIS23 F/F TINIM23 F/Fb4 TINIS22 F/F TINIM22 F/Fb5 b2 TINIS21 F/F TINIM21 F/Fb6 b3 TINIS20 F/F TINIM20 F/Fb7 4-source inputs TIN2023IMS <H'0080 023E> TIN23edge TIN22edge TIN21edge TIN20edge Figure 10.2.17 Block Diagram of TIN20–29 Input Interrupt Request (2/2)

32180 Group User’s Manual (Rev.1.0) TIN30–33 Interrupt Request Mask & Status Register (TIN3033IMS) <Address: H ’0080 023F> 9 1 01 11 21 31 4 b 1 5b8 TINIM30TINIM31TINIM32TINIM33TINIS30TINIS31TINIS32TINIS33 00000000 <After reset: H’00> b Bit Name Function R W

8 TINIS33 (TIN33 interrupt request status bit) 0: Interrupt not requested R(Note 1)

9 TINIS32 (TIN32 interrupt request status bit) 1: Interrupt requested

10 TINIS31 (TIN31 interrupt request status bit)

11 TINIS30 (TIN30 interrupt request status bit)

12 TINIM33 (TIN33 interrupt request mask bit) 0: Enable interrupt request R W

13 TINIM32 (TIN32 interrupt request mask bit) 1: Mask (disable) interrupt request

14 TINIM31 (TIN31 interrupt request mask bit)

15 TINIM30 (TIN30 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Note:  TIN24–TIN29 do not have interrupt functions, so that their status and mask registers are nonexistent. TIN30–33 input interrupt request IRQ18 Data bus TINIS33 F/F TINIM33 F/Fb12 TINIS32 F/F TINIM32 F/Fb13 b10 TINIS31 F/F TINIM31 F/Fb14 b11 TINIS30 F/F TINIM30 F/Fb15 (Level) 4-source inputs TIN3033IMS <H'0080 023F> TIN33edge TIN32edge TIN31edge TIN30edge Figure 10.2.18 Block Diagram of TIN30–33 Input Interrupt Request

32180 Group User’s Manual (Rev.1.0) TOU0 Interrupt Request Mask Register (TOU0IMA) <Address: H ’0080 07D2> 123456 b 7b0 TOU0IM7 TOU0IM6 TOU0IM5 TOU0IM4 TOU0IM3 TOU0IM2 TOU0IM1 TOU0IM0 00000000 <After reset: H’00> b Bit Name Function R W

0 TOU0IM7 (TOU0_7 interrupt request mask bit) 0: Enable interrupt request R W

1 TOU0IM6 (TOU0_6 interrupt request mask bit) 1: Mask (disable) interrupt request

2 TOU0IM5 (TOU0_5 interrupt request mask bit)

3 TOU0IM4 (TOU0_4 interrupt request mask bit)

4 TOU0IM3 (TOU0_3 interrupt request mask bit)

5 TOU0IM2 (TOU0_2 interrupt request mask bit)

6 TOU0IM1 (TOU0_1 interrupt request mask bit)

7 TOU0IM0 (TOU0_0 interrupt request mask bit)

TOU0 Interrupt Request Status Register (TOU0IST) <Address: H ’0080 07D3> 9 1 01 11 21 31 4 b 1 5b8 TOU0IS7 TOU0IS6 TOU0IS5 TOU0IS4 TOU0IS3 TOU0IS2 TOU0IS1 TOU0IS0 00000000 <After reset: H’00> b Bit Name Function R W

8 TOU0IS7 (TOU0_7 interrupt request status bit) 0: Interrupt not requested R(Note 1)

9 TOU0IS6 (TOU0_6 interrupt request status bit) 1: Interrupt requested

10 TOU0IS5 (TOU0_5 interrupt request status bit)

11 TOU0IS4 (TOU0_4 interrupt request status bit)

12 TOU0IS3 (TOU0_3 interrupt request status bit)

13 TOU0IS2 (TOU0_2 interrupt request status bit)

14 TOU0IS1 (TOU0_1 interrupt request status bit)

15 TOU0IS0 (TOU0_0 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

32180 Group User’s Manual (Rev.1.0) TOU0 output interrupt request 2 IRQ13 Data bus TOU0IS7 F/F TOU0IM7 F/Fb0 TOU0IS6 F/F TOU0IM6 F/Fb1 b10 TOU0IS5 F/F TOU0IM5 F/Fb2 b11 TOU0IS4 F/F TOU0IM4 F/Fb3 b12 TOU0IS3 F/F TOU0IM3 F/Fb4 (Level) 8-source inputs TOU0IMA <H'0080 07D2> TOU0IST <H'0080 07D3> TOU07udf TOU06udf TOU05udf TOU04udf TOU03udf b13 TOU0IS2 F/F TOU0IM2 F/Fb5 b14 TOU0IS1 F/F TOU0IM1 F/Fb6 b15 TOU0IS0 F/F TOU0IM0 F/Fb7 TOU02udf TOU01udf TOU00udf Figure 10.2.19 Block Diagram of TOU0 Output Interrupt Request

32180 Group User’s Manual (Rev.1.0) TOU1 Interrupt Request Mask Register (TOU1IMA) <Address: H ’0080 0BD2> 123456 b 7b0 TOU1IM7 TOU1IM6 TOU1IM5 TOU1IM4 TOU1IM3 TOU1IM2 TOU1IM1 TOU1IM0 00000000 <After reset: H’00> b Bit Name Function R W

0 TOU1IM7 (TOU1_7 interrupt request mask bit) 0: Enable interrupt request R W

1 TOU1IM6 (TOU1_6 interrupt request mask bit) 1: Mask (disable) interrupt request

2 TOU1IM5 (TOU1_5 interrupt request mask bit)

3 TOU1IM4 (TOU1_4 interrupt request mask bit)

4 TOU1IM3 (TOU1_3 interrupt request mask bit)

5 TOU1IM2 (TOU1_2 interrupt request mask bit)

6 TOU1IM1 (TOU1_1 interrupt request mask bit)

7 TOU1IM0 (TOU1_0 interrupt request mask bit)

TOU1 Interrupt Request Status Register (TOU1IST) <Address: H ’0080 0BD3> 9 1 01 11 21 31 4 b 1 5b8 TOU1IS7 TOU1IS6 TOU1IS5 TOU1IS4 TOU1IS3 TOU1IS2 TOU1IS1 TOU1IS0 00000000 <After reset: H’00> b Bit Name Function R W

8 TOU1IS7 (TOU1_7 interrupt request status bit) 0: Interrupt not requested R(Note 1)

9 TOU1IS6 (TOU1_6 interrupt request status bit) 1: Interrupt requested

10 TOU1IS5 (TOU1_5 interrupt request status bit)

11 TOU1IS4 (TOU1_4 interrupt request status bit)

12 TOU1IS3 (TOU1_3 interrupt request status bit)

13 TOU1IS2 (TOU1_2 interrupt request status bit)

14 TOU1IS1 (TOU1_1 interrupt request status bit)

15 TOU1IS0 (TOU1_0 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

32180 Group User’s Manual (Rev.1.0) TOU2 Interrupt Request Mask Register (TOU2IMA) <Address: H ’0080 0CD2> 123456 b 7b0 TOU2IM7 TOU2IM6 TOU2IM5 TOU2IM4 TOU2IM3 TOU2IM2 TOU2IM1 TOU2IM0 00000000 <After reset: H’00> b Bit Name Function R W

0 TOU2IM7 (TOU2_7 interrupt request mask bit) 0: Enable interrupt request R W

1 TOU2IM6 (TOU2_6 interrupt request mask bit) 1: Mask (disable) interrupt request

2 TOU2IM5 (TOU2_5 interrupt request mask bit)

3 TOU2IM4 (TOU2_4 interrupt request mask bit)

4 TOU2IM3 (TOU2_3 interrupt request mask bit)

5 TOU2IM2 (TOU2_2 interrupt request mask bit)

6 TOU2IM1 (TOU2_1 interrupt request mask bit)

7 TOU2IM0 (TOU2_0 interrupt request mask bit)

TOU2 Interrupt Request Status Register (TOU2IST) <Address: H ’0080 0CD3> 9 1 01 11 21 31 4 b 1 5b8 TOU2IS7 TOU2IS6 TOU2IS5 TOU2IS4 TOU2IS3 TOU2IS2 TOU2IS1 TOU2IS0 00000000 <After reset: H’00> b Bit Name Function R W

8 TOU2IS7 (TOU2_7 interrupt request status bit) 0: Interrupt not requested R(Note 1)

9 TOU2IS6 (TOU2_6 interrupt request status bit) 1: Interrupt requested

10 TOU2IS5 (TOU2_5 interrupt request status bit)

11 TOU2IS4 (TOU2_4 interrupt request status bit)

12 TOU2IS3 (TOU2_3 interrupt request status bit)

13 TOU2IS2 (TOU2_2 interrupt request status bit)

14 TOU2IS1 (TOU2_1 interrupt request status bit)

15 TOU2IS0 (TOU2_0 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.

32180 Group User’s Manual (Rev.1.0) TOU1+TOU2 output interrupt request IRQ16 Data bus TOU1IS7 F/F TOU1IM7 F/Fb0 TOU1IS6 F/F TOU1IM6 F/Fb1 b10 TOU1IS5 F/F TOU1IM5 F/Fb2 b11 TOU1IS4 F/F TOU1IM4 F/Fb3 b12 TOU1IS3 F/F TOU1IM3 F/Fb4 (Level) 16-source inputs TOU1IMA <H'0080 0BD2> TOU1IST <H'0080 0BD3> TOU17udf TOU16udf TOU15udf TOU14udf TOU13udf b13 TOU1IS2 F/F TOU1IM2 F/Fb5 b14 TOU1IS1 F/F TOU1IM1 F/Fb6 b15 TOU1IS0 F/F F/Fb7 TOU12udf TOU11udf TOU10udf TOU1IM0 To the remaining 8-input sources in the next page Figure 10.2.20 Block Diagram of TOU1 + TOU2 Output Interrupt Request (1/2)

32180 Group User’s Manual (Rev.1.0) Data bus TOU2IS7 F/F TOU2IM7 F/Fb0 TOU2IS6 F/F TOU2IM6 F/Fb1 b10 TOU2IS5 F/F TOU2IM5 F/Fb2 b11 TOU2IS4 F/F TOU2IM4 F/Fb3 b12 TOU2IS3 F/F TOU2IM3 F/Fb4 TOU2IMA <H'0080 0CD2> TOU2IST <H'0080 0CD3> TOU27udf TOU26udf TOU25udf TOU24udf TOU23udf b13 TOU2IS2 F/F TOU2IM2 F/Fb5 b14 TOU2IS1 F/F TOU2IM1 F/Fb6 b15 TOU2IS0 F/F F/Fb7 TOU22udf TOU21udf TOU20udf TOU2IM0 To the preceding page Figure 10.2.21 Block Diagram of TOU1 + TOU2 Output Interrupt Request (2/2)

32180 Group User’s Manual (Rev.1.0)

10.3.1 Outline of TOP

TOP (Timer OutPut) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software:  Single-shot output mode  Delayed single-shot output mode  Continuous output mode The table below shows specifications of TOP. The diagram in the next page shows a block diagram of TOP. Table 10.3.1 Specifications of TOP (Output-Related 16-Bit Timer) Item Specification Number of channels 11 channels Counter 16-bit down-counter Reload register 16-bit reload register Correction register 16-bit correction register Timer startup Started by writing to the enable bit in software or enabled by external input (rising or falling edge or both) Operation mode <With correction function>  Single-shot output mode  Delayed single-shot output mode <Without correction function>  Continuous output mode Interrupt request generation Can be generated by a counter underflow

32180 Group User’s Manual (Rev.1.0) Figure 10.3.1 Block Diagram of TOP (Output-Related 16-Bit Timer) IRQ2 clk en udf TOP 0 Clock bus Input event bus clk en udfTOP 1 clk en udfTOP 2 clk en udfTOP 3 Output event bus TCLK0S TO 0 (P110) IRQ9 3 2 1 0 clk en udfTOP 4 clk en udfTOP 5 TCLK0 (P124) TIN0 (P150) S STIN0S clk en udfTOP 6 clk en udfTOP 7 S S S IRQ9 TIN1 (P151) IRQ9 TIN2 (P152) S S clk en udfTOP 8 clk en udfTOP 9 clk en udfTOP 10 F/F0 F/F1 F/F2 F/F3 F/F4 F/F5 F/F6 F/F7 F/F8 F/F9 F/F10 S : SelectorF/F : Output flip-flop S S S S S IRQ2 IRQ2 IRQ2 IRQ2 IRQ2 TO 1 (P111) TO 2 (P112) TO 3 (P113) TO 4 (P114) TO 5 (P115) TO 6 (P116) TO 7 (P117) TO 8 (P100) TO 9 (P101) TO 10 (P102) IRQ1 IRQ1 IRQ6 IRQ6 IRQ5 3 2 1 0 0 1 2 3 TIN1S TIN2S Reload register Down-counter Correction register 3 2 1 0 3 2 1 0 0 1 2 3 (16-bit) DRQ7 DRQ8 DRQ9

32180 Group User’s Manual (Rev.1.0)

10.3.2 Outline of Each Mode of TOP

Each mode of TOP is outlined below. For each TOP channel, only one of the following modes can be selected. (1) Single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload register, the counter is loaded with the content of the reload register and starts counting synchronously with the count clock. The counter counts down and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of (reload register set value + 1) only once. An interrupt request can be generated when the counter underflows. (2) Delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) after a finite time equal to (counter set value + 1) only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. The first time the counter underflows, it is loaded with the reload register value and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload register set value + 1) after a finite time equal to (first set value of counter + 1) only once. An interrupt request can be generated when the counter underflows first time and next. (3) Continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload register set value + 1). When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be loaded with the content of the reload register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each time the counter underflows.

32180 Group User’s Manual (Rev.1.0) <Count clock-dependent delay>  Because the timer operates synchronously with the count clock, there is a count clock-dependent delay from when the timer is enabled till when it actually starts operating. In operation mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is inverted. BCLK Count clock Enable F/F operation (Note 1) Count clock period Count clock-dependent delay Write to the enable bit Note 1: This applies to the case where F/F output is inverted when the timer is enabled. Inverted Figure 10.3.2 Count Clock Dependent Delay

32180 Group User’s Manual (Rev.1.0)

10.3.3 TOP Related Register Map

Shown below is a TOP related register map. TOP Related Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0240 TOP0 Counter 10-75 (TOP0CT) H'0080 0242 TOP0 Reload Register 10-76 (TOP0RL) H'0080 0244 (Use inhibited area) H'0080 0246 TOP0 Correction Register 10-77 (TOP0CC) (Use inhibited area) H'0080 0250 TOP1 Counter 10-75 (TOP1CT) H'0080 0252 TOP1 Reload Register 10-76 (TOP1RL) H'0080 0254 (Use inhibited area) H'0080 0256 TOP1 Correction Register 10-77 (TOP1CC) (Use inhibited area) H'0080 0260 TOP2 Counter 10-75 (TOP2CT) H'0080 0262 TOP2 Reload Register 10-76 (TOP2RL) H'0080 0264 (Use inhibited area) H'0080 0266 TOP2 Correction Register 10-77 (TOP2CC) (Use inhibited area) H'0080 0270 TOP3 Counter 10-75 (TOP3CT) H'0080 0272 TOP3 Reload Register 10-76 (TOP3RL) H'0080 0274 (Use inhibited area) H'0080 0276 TOP3 Correction Register 10-77 (TOP3CC) (Use inhibited area) H'0080 0280 TOP4 Counter 10-75 (TOP4CT) H'0080 0282 TOP4 Reload Register 10-76 (TOP4RL) H'0080 0284 (Use inhibited area) H'0080 0286 TOP4 Correction Register 10-77 (TOP4CC) (Use inhibited area) H'0080 0290 TOP5 Counter 10-75 (TOP5CT) H'0080 0292 TOP5 Reload Register 10-76 (TOP5RL) H'0080 0294 (Use inhibited area) H'0080 0296 TOP5 Correction Register 10-77 (TOP5CC) H'0080 0298 (Use inhibited area)

32180 Group User’s Manual (Rev.1.0) TOP Related Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 029A TOP0 –5 Control Register 0 10-71 (TOP05CR0) H'0080 029C (Use inhibited area) TOP0 –5 Control Register 1 10-71 (TOP05CR1) (Use inhibited area) H'0080 02A0 TOP6 Counter 10-75 (TOP6CT) H'0080 02A2 TOP6 Reload Register 10-76 (TOP6RL) H'0080 02A4 (Use inhibited area) H'0080 02A6 TOP6 Correction Register 10-77 (TOP6CC) H'0080 02A8 (Use inhibited area) H'0080 02AA TOP6,7 Control Register 10-73 (TOP67CR) (Use inhibited area) H'0080 02B0 TOP7 Counter 10-75 (TOP7CT) H'0080 02B2 TOP7 Reload Register 10-76 (TOP7RL) H'0080 02B4 (Use inhibited area) H'0080 02B6 TOP7 Correction Register 10-77 (TOP7CC) (Use inhibited area) H'0080 02C0 TOP8 Counter 10-75 (TOP8CT) H'0080 02C2 TOP8 Reload Register 10-76 (TOP8RL) H'0080 02C4 (Use inhibited area) H'0080 02C6 TOP8 Correction Register 10-77 (TOP8CC) (Use inhibited area) H'0080 02D0 TOP9 Counter 10-75 (TOP9CT) H'0080 02D2 TOP9 Reload Register 10-76 (TOP9RL) H'0080 02D4 (Use inhibited area) H'0080 02D6 TOP9 Correction Register 10-77 (TOP9CC) (Use inhibited area) H'0080 02E0 TOP10 Counter 10-75 (TOP10CT) H'0080 02E2 TOP10 Reload Register 10-76 (TOP10RL) H'0080 02E4 (Use inhibited area) H'0080 02E6 TOP10 Correction Register 10-77 (TOP10CC) H'0080 02E8 (Use inhibited area) H'0080 02EA TOP8 –10 Control Register 10-74 (TOP810CR) (Use inhibited area) H'0080 02FA TOP External Enable Permit Register 10-78 (TOPEEN) H'0080 02FC TOP Enable Protect Register 10-78 (TOPPRO) H'0080 02FE TOP Count Enable Register 10-79 (TOPCEN)

32180 Group User’s Manual (Rev.1.0)

10.3.4 TOP Control Registers

The TOP control registers are used to select operation modes of TOP0–10 (single-shot output, delayed single- shot output or continuous output mode), as well as select the count enable and count clock sources. Following four TOP control registers are provided for each timer group.  TOP0–5 Control Register 0 (TOP05CR0)  TOP0–5 Control Register 1 (TOP05CR1)  TOP6,7 Control Register (TOP67CR)  TOP8–10 Control Register (TOP810CR)

32180 Group User’s Manual (Rev.1.0) TOP0 –5 Control Register 0 (TOP05CR0) <Address: H ’0080 029A> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP3M TOP2M TOP1M TOP0M TOP05ENS TOP05CKS 00000000 0 000 0 0 00 <After reset: H’0000> b Bit Name Function R W 0, 1 TOP3M (TOP3 operation mode select bit) 00: Single-shot output mode R W 2, 3 TOP2M (TOP2 operation mode select bit) 01: Delayed single-shot output mode 4, 5 TOP1M (TOP1 operation mode select bit) 10: Continuous output mode 6, 7 TOP0M (TOP0 operation mode select bit) 11: – ditto – 8 No function assigned. Fix to "0". 00 9–11 TOP05ENS 000: External TIN0 input R W TOP0 –5 enable source select bit 001: – ditto – 010: – ditto – 011: – ditto – 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12, 13 No function assigned. Fix to "0". 00 14, 15 TOP05CKS 00: Clock bus 0 R W TOP0 –5 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive. TOP0 –5 Control Register 1 (TOP05CR1) <Address: H ’0080 029D> 9 1 01 11 21 31 4 b 1 5b8 TOP5M TOP4M 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12, 13 TOP5M (TOP5 operation mode select bit) 00: Single-shot output mode R W 14, 15 TOP4M (TOP4 operation mode select bit) 01: Delayed single-shot output mode 10: Continuous output mode 11: – ditto – Note:  Operation mode can only be set or changed while the counter is inactive.

32180 Group User’s Manual (Rev.1.0) clk en TOP 0 Clock bus Input event bus clk en TOP 1 clk en TOP 2 clk en TOP 3 3 2 1 0 clk en TOP 4 clk en TOP 5 S S : Selector TIN0 (P150) S TIN0S 3 2 1 0 Note:  This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.3 Outline Diagram of TOP0–5 Clock and Enable Inputs

32180 Group User’s Manual (Rev.1.0) TOP6,7 Control Register (TOP67CR) <Address: H ’0080 02AA> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP7 ENS TOP7M TO P6M TOP67ENS TOP67CKS 0 00 0 0 0 0 0 0 000 0 0 00 <After reset: H’0000> b Bit Name Function R W 0 No function assigned. Fix to "0". 00

1 TOP7ENS 0: Result selected by TOP67ENS bit R W

TOP7 enable source select bit 1: TOP6 output 2, 3 TOP7M 00: Single-shot output mode R W TOP7 operation mode select bit 01: Delayed single-shot output mode 10: Continuous output mode 11: – ditto – 4, 5 No function assigned. Fix to "0". 00 6, 7 TOP6M 00: Single-shot output mode R W TOP6 operation mode select bit 01: Delayed single-shot output mode 10: Continuous output mode 11: – ditto – 8 No function assigned. Fix to "0". 00 9–11 TOP67ENS 000: External TIN1 input R W TOP6, TOP7 enable source select bit 001: – ditto – 010: – ditto – 011: – ditto – 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12, 13 No function assigned. Fix to "0". 00 14, 15 TOP67CKS 00: Clock bus 0 R W TOP6, TOP7 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive. Clock bus Input event bus 3 2 1 0 clk en udfTOP 6 clk en udfTOP 7 S S TIN1STIN1 (P151) S : Selector 3 2 1 0 S Note:  This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.4 Outline Diagram of TOP6, TOP7 Clock and Enable Inputs

32180 Group User’s Manual (Rev.1.0) Clock bus Input event bus 3 2 1 0 TIN2 (P152) TIN2S S S clk en TOP 8 clk en TOP 9 clk en TOP 10 S : Selector 3 2 1 0 Note:  This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.5 Outline Diagram of TOP8–10 Clock and Enable Inputs TOP8 –10 Control Register (TOP810CR) <Address: H ’0080 02EA> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP10M TOP9M TO P8M TO P810 ENS TOP810CKS 0 0 00000 0 0 0 0 0 0 0 00 <After reset: H’0000> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00 2, 3 TOP10M (TOP10 operation mode select bit) 00: Single-shot output mode R W 4, 5 TOP9M (TOP9 operation mode select bit) 01: Delayed single-shot output mode 6, 7 TOP8M (TOP8 operation mode select bit) 10: Continuous output mode 11: – ditto – 8–10 No function assigned. Fix to "0". 00

11 TOP810ENS 0: External TIN2 input R W

TOP8 –10 enable source select bit 1: Input event bus 3 12, 13 No function assigned. Fix to "0". 00 14, 15 TOP810CKS 00: Clock bus 0 R W TOP8 –10 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive.

32180 Group User’s Manual (Rev.1.0)

10.3.5 TOP Counters (TOP0CT–TOP10CT)

TOP0 Counter (TOP0CT) <Address: H ’0080 0240> TOP1 Counter (TOP1CT) <Address: H ’0080 0250> TOP2 Counter (TOP2CT) <Address: H ’0080 0260> TOP3 Counter (TOP3CT) <Address: H ’0080 0270> TOP4 Counter (TOP4CT) <Address: H ’0080 0280> TOP5 Counter (TOP5CT) <Address: H ’0080 0290> TOP6 Counter (TOP6CT) <Address: H ’0080 02A0> TOP7 Counter (TOP7CT) <Address: H ’0080 02B0> TOP8 Counter (TOP8CT) <Address: H ’0080 02C0> TOP9 Counter (TOP9CT) <Address: H ’0080 02D0> TOP10 Counter (TOP10CT) <Address: H ’0080 02E0> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP0CT –TOP10CT <After reset: Undefined> b Bit Name Function R W 0–15 TOP0CT –TOP10CT 16-bit counter value R W Note:  This register must always be accessed in halfwords. The TOP counters are a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by external input), the counter starts counting synchronously with the count clock.

32180 Group User’s Manual (Rev.1.0)

10.3.6 TOP Reload Registers (TOP0RL–TOP10RL)

TOP0 Reload Register (TOP0RL) <Address: H ’0080 0242> TOP1 Reload Register (TOP1RL) <Address: H ’0080 0252> TOP2 Reload Register (TOP2RL) <Address: H ’0080 0262> TOP3 Reload Register (TOP3RL) <Address: H ’0080 0272> TOP4 Reload Register (TOP4RL) <Address: H ’0080 0282> TOP5 Reload Register (TOP5RL) <Address: H ’0080 0292> TOP6 Reload Register (TOP6RL) <Address: H ’0080 02A2> TOP7 Reload Register (TOP7RL) <Address: H ’0080 02B2> TOP8 Reload Register (TOP8RL) <Address: H ’0080 02C2> TOP9 Reload Register (TOP9RL) <Address: H ’0080 02D2> TOP10 Reload Register (TOP10RL) <Address: H ’0080 02E2> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP0RL –TOP10RL <After reset: Undefined> b Bit Name Function R W 0–15 TOP0RL –TOP10RL 16-bit reload register value R W Note:  This register must always be accessed in halfwords. The TOP reload registers are used to load data into the TOP counter registers (TOP0CT–TOP10CT). The content of the reload register is loaded into the counter in the following cases:  When the counter is enabled in single-shot output mode  When the counter underflowed in delayed single-shot or continuous output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. Note that reloading of data after an underflow is performed synchronously with a clock pulse at which the counter underflowed.

32180 Group User’s Manual (Rev.1.0)

10.3.7 TOP Correction Registers (TOP0CC–TOP10CC)

TOP0 Correction Register (TOP0CC) <Address: H ’0080 0246> TOP1 Correction Register (TOP1CC) <Address: H ’0080 0256> TOP2 Correction Register (TOP2CC) <Address: H ’0080 0266> TOP3 Correction Register (TOP3CC) <Address: H ’0080 0276> TOP4 Correction Register (TOP4CC) <Address: H ’0080 0286> TOP5 Correction Register (TOP5CC) <Address: H ’0080 0296> TOP6 Correction Register (TOP6CC) <Address: H ’0080 02A6> TOP7 Correction Register (TOP7CC) <Address: H ’0080 02B6> TOP8 Correction Register (TOP8CC) <Address: H ’0080 02C6> TOP9 Correction Register (TOP9CC) <Address: H ’0080 02D6> TOP10 Correction Register (TOP10CC) <Address: H ’0080 02E6> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP0CC –TOP10CC (Acceptable range of values: +32,767 to –32,768) <After reset: Undefined> b Bit Name Function R W 0–15 TOP0CC –TOP10CC 16-bit correction register value R W Note:  This register must always be accessed in halfwords. The TOP correction registers are used to correct the TOP counter value by adding or subtracting in the middle of operation. To increase or reduce the counter value, write to this correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the correction register. The counter is corrected synchronously with a clock pulse next to one at which the correction value was written to the TOP correction register. If the counter is corrected this way, note that because one down count in that clock period is canceled, the counter value actually is corrected by (correction register value + 1). For example, if the initial counter value is 10 and the value 3 is written to the correction register when the counter has counted down to 5, then the counter counts a total of 15 before it underflows.

32180 Group User’s Manual (Rev.1.0)

10.3.8 TOP Enable Control Registers

TOP External Enable Permit Register (TOPEEN) <Address: H ’0080 02FA> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP10 EEN TOP9 EEN TOP8 EEN TOP7 EEN TOP6 EEN TOP5 EEN TOP4 EEN TOP3 EEN TOP2 EEN TOP1 EEN TOP0 EEN 0 0 0 0 0 00000000000 <After reset: H’0000> b Bit Name Function R W 0–4 No function assigned. Fix to "0". 00

5 TOP10EEN (TOP10 external enable permit bit) 0: Disable external enable R W

6 TOP9EEN (TOP9 external enable permit bit) 1: Enable external enable

7 TOP8EEN (TOP8 external enable permit bit)

8 TOP7EEN (TOP7 external enable permit bit)

9 TOP6EEN (TOP6 external enable permit bit)

10 TOP5EEN (TOP5 external enable permit bit)

11 TOP4EEN (TOP4 external enable permit bit)

12 TOP3EEN (TOP3 external enable permit bit)

13 TOP2EEN (TOP2 external enable permit bit)

14 TOP1EEN (TOP1 external enable permit bit)

15 TOP0EEN (TOP0 external enable permit bit)

Note:  This register must always be accessed in halfwords. The TOP External Enable Permit Register controls enable operation on TOP counters from external devices by enabling or disabling it. TOP Enable Protect Register (TOPPRO) <Address: H ’0080 02FC> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP10 PRO TOP9 PRO TOP8 PRO TOP7 PRO TOP6 PRO TOP5 PRO TOP4 PRO TOP3 PRO TOP2 PRO TOP1 PRO TOP0 PRO 0 0 0 0 0 00000000000 <After reset: H’0000> b Bit Name Function R W 0–4 No function assigned. Fix to "0". 00

5 TOP10PRO (TOP10 enable protect bit) 0: Enable for rewriting R W

6 TOP9PRO (TOP9 enable protect bit) 1: Protect against rewriting

7 TOP8PRO (TOP8 enable protect bit)

8 TOP7PRO (TOP7 enable protect bit)

9 TOP6PRO (TOP6 enable protect bit)

10 TOP5PRO (TOP5 enable protect bit)

11 TOP4PRO (TOP4 enable protect bit)

12 TOP3PRO (TOP3 enable protect bit)

13 TOP2PRO (TOP2 enable protect bit)

14 TOP1PRO (TOP1 enable protect bit)

15 TOP0PRO (TOP0 enable protect bit)

Note:  This register must always be accessed in halfwords. The TOP Enable Protect Register controls rewriting of the TOP count enable bit by enabling for or protecting it against rewriting.

32180 Group User’s Manual (Rev.1.0) TOP Count Enable Register (TOPCEN) <Address: H ’0080 02FE> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP10 CEN TOP9 CEN TOP8 CEN TOP7 CEN TOP6 CEN TOP5 CEN TOP4 CEN TOP3 CEN TOP2 CEN TOP1 CEN TOP0 CEN 0 0 0 0 0 00000000000 <After reset: H’0000> b Bit Name Function R W 0–4 No function assigned. Fix to "0". 00

5 TOP10CEN (TOP10 count enable bit) 0: Stop counting R W

6 TOP9CEN (TOP9 count enable bit) 1: Enable counting

7 TOP8CEN (TOP8 count enable bit)

8 TOP7CEN (TOP7 count enable bit)

9 TOP6CEN (TOP6 count enable bit)

10 TOP5CEN (TOP5 count enable bit)

11 TOP4CEN (TOP4 count enable bit)

12 TOP3CEN (TOP3 count enable bit)

13 TOP2CEN (TOP2 count enable bit)

14 TOP1CEN (TOP1 count enable bit)

15 TOP0CEN (TOP0 count enable bit)

Note:  This register must always be accessed in halfwords. The TOP Count Enable Register controls operation of TOP counters. To enable any TOP counter in software, enable its corresponding enable protect bit for write and set the count enable bit by writing "1". To stop any TOP counter, enable its corresponding enable protect bit for write and reset the count enable bit by writing "0". In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable bit is automatically reset to "0". Therefore, the TOP0-10 Count Enable Register when accessed for read serves as a status register indicating whether the counter is operating or idle. WR Dn TOPm enable protect (TOPmPRO) WR EN-ON TOPm external enable (TOPmEEN) TINnS TOPm count enable (TOPmCEN) TOP enable control Input processing selection F/F F/F F/F Event bus TINn Figure 10.3.6 Configuration of the TOP Enable Circuit

32180 Group User’s Manual (Rev.1.0)

10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function)

(1) Outline of TOP single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload register, the counter is loaded with the content of the reload register and starts counting synchronously with the count clock. The counter counts down and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload regis- ter set value + 1) only once. An interrupt request can be generated when the counter underflows. The count value is (reload register set value + 1). For example, if the initial reload register value is 7, then the count value is 8. Figure 10.3.7 Example of Counting in TOP Single-shot Output Mode Enable Reload register (7) 6 5 4 3 1234567 8 H'FFFF Counter Interrupt request Underflow Count value = 8 (Note 1) Note 1: What actually is seen in the cycle immediately after reload is the previous counter value, and not 7. Note:  This diagram does not show detailed timing information. 2 1 F/F output Count clock * A count clock dependent delay is included before F/F output changes state after the timer is enabled.

32180 Group User’s Manual (Rev.1.0) In the example below, the reload register is initially set to H’A000. (The initial counter value can be undefined, and does not have to be specific.) When the timer starts, the reload register value is loaded into the counter, letting it start counting. Thereafter, it continues counting down until it underflows after reaching the minimum count. Count clock Correction register H'FFFF H'0000 Enabled (by writing to the enable bit or by external input) F/F output Disabled (by underflow) (Unused) TOP interrupt request due to underflow Enable bit Starts counting down from the reload register set value Note:  This diagram does not show detailed timing information. Reload register H'A000 Data inverted by enable Counter H'A000 Data inverted by underflow H'FFFF H'(A000-1) Indeterminate value Figure 10.3.8 Typical Operation in TOP Single-shot Output Mode

32180 Group User’s Manual (Rev.1.0) When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. (2) Correction function of TOP single-shot output mode To change the counter value while in progress, write to the TOP correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the correction register. The counter is corrected synchronously with a count clock pulse next to one at which the correction value was written to the TOP correction register. If the counter is corrected this way, note that because one down count in that clock period is canceled, the counter value actually is corrected by (correction register value + 1). For example, if the initial counter value is 7 and the value 3 is written to the correction register when the counter has counted down to 3, then the counter counts a total of 12 before it underflows. Figure 10.3.9 Example of Counting in TOP Single-shot Output Mode When Count is Corrected (7) 6 5 4 3 2 1 0 123456789 1 0 1 1 12 6 5 4 3 Correction register Underflow Count value = (7 + 1) + (3 + 1) = 12 Count clock dependent delay H'FFFFEnable Reload register Counter Interrupt request Count clock (Note 1) Note 1: What actually is seen in the cycle immediately after reload is the previous counter value, and not 7. Note:  This diagram does not show detailed timing information.

32180 Group User’s Manual (Rev.1.0) Figure 10.3.10 Typical Operation in TOP Single-shot Output Mode When Count is Corrected Data inverted by enable Data inverted by underflow H'(8000-1) H'FFFF H'0000 H'8000 H'5000 H'5000+H'4000 H'8000 H'FFFF Undefined H'4000 Count clock Correction register Enabled (by writing to the enable bit or by external input) F/F output TOP interrupt request due to underflow Enable bit Note:  This diagram does not show detailed timing information. Reload register Write to the correction register Undefined value Disabled (by underflow) Counter In the example below, the reload register is initially set to H’8000. When the timer starts, the reload register value is loaded into the counter, letting it start counting down. In the diagram below, the value H’4000 is written to the correction register when the counter has counted down to H’5000. As a result of this correction, the count has been increased to H’9000, so that the counter counts a total of (H’8000 + 1 + H’4000 + 1) before it stops.

32180 Group User’s Manual (Rev.1.0) (3) Precautions on using TOP single-shot output mode The following describes precautions to be observed when using TOP single-shot output mode.  If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.  If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  Because the timer operates synchronously with the count clock, a count clock-dependent delay is included before F/F output is inverted after the timer is enabled.  When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. Therefore, if the counter underflows in the subsequent down-count after an overflow, a false interrupt re- quest is generated for an underflow that includes the overflowed count.

32180 Group User’s Manual (Rev.1.0) H'FFFF H'0000 H'FFF8 H'(FFF0+0014) H'0004 H'FFF0 H'0014 H'FFF8 H'FFFF Data inverted by enable Data inverted by underflow H'(FFF8-1) Counter Count clock Correction register F/F output TOP interrupt request due to underflow Enable bit Note:  This diagram does not show detailed timing information. Reload register Write to the correction register Enabled (by writing to the enable bit or by external input) Disabled (by underflow) Undefined value Actual count after overflow Overflow occurs Undefined Figure 10.3.11 Example of an Operation in TOP Single-shot Output Mode Where Count Overflows Due to Correction In the example below, the reload register is initially set to H’FFF8. When the timer starts, the reload register value is loaded into the counter, letting it start counting down. In the diagram below, the value H’0014 is written to the correction register when the counter has counted down to H’FFF0. As a result of this correction, the count overflows to H’0004 and the counter fails to count correctly. Also, an interrupt request is generated for an erroneous overflowed count.

32180 Group User’s Manual (Rev.1.0)

10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function)

(1) Outline of TOP delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) after a finite time equal to (counter set value + 1) only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. The first time the counter underflows, it is loaded with the reload register value and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from low to high or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload register set value + 1) after a finite time equal to (first set value of counter + 1) only once. An interrupt request can be generated when the counter underflows first time and next. The (counter set value + 1) and (reload register set value + 1) are effective as count values. For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates as shown below. Figure 10.3.12 Example of Counting in TOP Delayed Single-shot Output Mode 4 3 2 1 123 45 67 8 F/F output 9 10 11 3 2 1 0 4(5) (Note 1) H'FFFF Count clock dependent delay Enable Reload register Counter Interrupt request Count clock Note 1: What actually is seen in the cycle immediately after reload is the previous counter value, and not 7. Note:  This diagram does not show detailed timing information. Underflow Underflow Count value = (4 + 1) + (5 + 1) = 11

32180 Group User’s Manual (Rev.1.0) In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respectively. When the timer is enabled, the counter starts counting down and when it underflows after reaching the minimum count, the counter is loaded with the content of the reload register and continues counting down. The counter stops when it underflows second time. Figure 10.3.13 Typical Operation in TOP Delayed Single-shot Output Mode H'FFFF H'0000 Underflow (first time) Count down from the counter's set valueH'A000 Underflow (second time) H'F000 Count down from the reload register's set value H'(F000-1) (Unused) H'FFFF H'F000 Data inverted by underflow Data inverted by underflow Count clock Correction register Enabled (by writing to the enable bit or by external input) F/F output TOP interrupt request due to underflow Enable bit Note:  This diagram does not show detailed timing information. Reload register Counter

32180 Group User’s Manual (Rev.1.0) (2) Correction function of TOP delayed single-shot output mode To change the counter value while in progress, write to the TOP correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the correction register. The counter is corrected synchronously with a count clock pulse next to one at which the correction value was written to the TOP correction register. If the counter is corrected this way, note that because one down count in that clock period is canceled, the counter value actually is corrected by (correction register value + 1). For example, if the reload register value is 7 and the value 3 is written to the correction register when the counter has counted down to 3 after being reloaded, then the counter counts a total of 12 after being reloaded before it underflows. Enable = "H" (7) 6 5 4 3 2 1 0 123456789 1 0 1 1 12 6 5 4 3 (Note 1) H'FFFF Underflow Correction register Reload register Counter Interrupt request Count clock Note 1: What actually is seen in the cycle immediately after reload is the previous counter value, and not 7. Note:  This diagram does not show detailed timing information. Count value after being reloaded = (7 + 1) + (3 + 1) = 12 Figure 10.3.14 Example of Counting in TOP Delayed Single-shot Output Mode When Count is Corrected When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow.

32180 Group User’s Manual (Rev.1.0) Figure 10.3.15 Typical Operation in TOP Delayed Single-shot Output Mode when Count is Corrected H'FFFF H'0000 H'9000+H'0008 H'F000 H'A000 H'F000 H'(F000+0008+1) H'0008 Write to the correction register H'9000 Data inverted by underflow Data inverted by underflow Correction register F/F output TOP interrupt request due to underflow Enable bit Note:  This diagram does not show detailed timing information. Reload register Counter Count clock Underflow (first time) Underflow (second time) Enabled (by writing to the enable bit or by external input) Undefined In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respectively. When the timer is enabled, the counter starts counting down and when it underflows after reaching the minimum count, the counter is loaded with the content of the reload register and continues counting down. In the diagram below, the value H’0008 is written to the correction register when the counter has counted down to H’9000. As a result of this correction, the counter has its count value increased to H’9008 and counts (H’F000 + 1 + H’0008 + 1) after the first underflow before it stops.

32180 Group User’s Manual (Rev.1.0) (3) Precautions on using TOP delayed single-shot output mode The following describes precautions to be observed when using TOP delayed single-shot output mode.  If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.  If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. Therefore, if the counter underflows in the subsequent down-count after an overflow, a false interrupt request is generated for an underflow that includes the overflowed count.  If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge. Figure 10.3.16 Counter Value Immediately after Underflow Count clock Enable bit "H" H'0001 H'0000 H'FFFF H'AAA9 H'AAA8Counter value H'AAAAReload register Reload due to underflow H'(AAAA-1) H'(AAAA-2) What is seen during reload cycle is always H'FFFF , and not the reload register value (in this case, H'AAAA). Count down from the reload register value Reload cycle

32180 Group User’s Manual (Rev.1.0)

10.3.11 Operation in TOP Continuous Output Mode (without Correction Function)

(1) Outline of TOP continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload register set value + 1). When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be loaded with the content of the reload register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output level changes from low to high or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each time the counter underflows. The (counter set value + 1) and (reload register set value + 1) are effective as count values. For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates as shown below. Figure 10.3.17 Example of Counting in TOP Continuous Output Mode (4) 3 2 1 1234 5 (Note 1) F/F output 3 2 1 0 4(5) (Note 2) 3 2 1 0 (5) (5)4 12345612345 6 Count clock dependent delay Enable Reload register Counter Interrupt request Count clock Underflow Note 1: What actually is seen in the cycle immediately after enable is the previous counter value, and not 4. Note 2: What actually is seen in the cycle immediately after reload is H'FFFF (underflow value), and not 5. Note:  This diagram does not show detailed timing information. Underflow Underflow (Note 2) (Note 2) Count value = 5 Count value = 6 Count value = 6

32180 Group User’s Manual (Rev.1.0) In the example below, the counter and the reload register are initially set to H’A000 and H’E000, respectively. When the timer is enabled, the counter starts counting down and when it underflows after reaching the minimum count, the counter is loaded with the content of the reload register and continues counting down. H'FFFF H'0000 H'E000 H'A000 H'FFFF H'FFFF Data inverted by underflow Data inverted by underflow Data inverted by enable Count clock Correction register F/F output TOP interrupt request due to underflow Enable bit Note:  This diagram does not show detailed timing information. Reload register Counter Underflow (first time) Underflow (second time) Enabled (by writing to the enable bit or by external input) Count down from the counter's set value Count down from the reload register's set value Count down from the reload register's set value (Unused) Figure 10.3.18 Typical Operation in TOP Continuous Output Mode

32180 Group User’s Manual (Rev.1.0) (2) Precautions on using TOP continuous output mode The following describes precautions to be observed when using TOP continuous output mode.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.  Because the timer operates synchronously with the count clock, a count clock-dependent delay is included before F/F output is inverted after the timer is enabled.

32180 Group User’s Manual (Rev.1.0)

10.4.1 Outline of TIO

TIO (Timer Input/Output) is an input/output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time: <Input modes>  Measure clear input mode  Measure free-run input mode  Noise processing input mode <Output modes without correction function>  PWM output mode  Single-shot output mode  Delayed single-shot output mode  Continuous output mode The table below shows specifications of TIO. The diagram in the next page shows a block diagram of TIO. Table 10.4.1 Specifications of TIO (Input/Output-Related 16-Bit Timer) Item Specification Number of channels 10 channels Counter 16-bit down-counter Reload register 16-bit reload register Measure register 16-bit capture register Timer startup Started by writing to the enable bit in software or enabled by external input (rising or falling or both edges or high or low level) Operation mode <Input modes>  Measure clear input mode  Measure free-run input mode  Noise processing input mode <Output modes without correction function>  PWM output mode  Single-shot output mode  Delayed single-shot output mode  Continuous output mode Interrupt request generation Can be generated by a counter underflow

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0) IRQ12 IRQ12 IRQ12 Clock bus Input event bus Output event bus 3 2 1 0 BCLK/2 IRQ8 TIN7 (P157) TCLK1 (P125) clk en/cap udf TIO 0 clk en/cap udfTIO 1 clk en/cap udfTIO 2 clk en/cap udfTIO 3 clk en/cap udfTIO 4 S STIN3STIN3 (P153) S S TIN4STIN4 (P154) TIN5STIN5 (P155) S SIRQ12 TIN6STIN6 (P156) PRS1 PRS0 clk en/cap udfTIO 5STCLK1S STIN7S IRQ8 TIN8 (P140) TCLK2 (P126) clk en/cap udfTIO 6STCLK2S STIN8S IRQ8 TIN9 (P141) clk en/cap udfTIO 7S STIN9S IRQ8 TIN10 (P142) S STIN10S clk en/cap udfTIO 8 clk en/cap udfTIO 9 IRQ8 TIN11 (P143) S STIN11S F/F11 F/F12 F/F13 F/F14 F/F15 S F/F16 F/F17 F/F18 F/F19 S : SelectorF/F : Flip-flopPRS0 –2 : Prescaler S S S S S S S S S TO 11 (P103) TO 12 (P104) TO 13 (P105) TO 14 (P106) TO 15 (P107) IRQ0 IRQ0 IRQ0 IRQ0 IRQ4 TO 16 (P93) TO 17 (P94) TO 18 (P95) TO 19 (P96) TO 20 (P97) IRQ4 IRQ4 IRQ4 DMA0 IRQ3 3 2 1 0 0 1 2 3 0 1 2 33 2 1 0 3 2 1 0 PRS2 Reload 0/measure register Down-counter Reload 1 register (Note 1) (16-bit) IRQ3 Note 1: The reload 1 register is used in only PWM output mode. F/F20 DMA10 DMA11 Figure 10.4.1 Block Diagram of TIO (Input/Output-Related 16-Bit Timer)

32180 Group User’s Manual (Rev.1.0)

10.4.2 Outline of Each Mode of TIO

Each mode of TIO is outlined below. For each TIO channel, only one of the following modes can be selected. (1) Measure clear/free-run input modes In measure clear/free-run input modes, the timer is used to measure a duration of time from when the counter starts counting till when an external capture signal is entered. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchro- nously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written into a register called the “measure register.” In measure clear input mode, the counter value is initialized to H’FFFF upon capture, from which the counter starts counting down again. In measure free-run input mode, the counter continues counting down even after capture and upon underflow, recycles to H’FFFF, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. An interrupt request can be gener- ated by a counter underflow or execution of a measure operation. (2) Noise processing input mode In noise processing input mode, the timer is used to detect that the input signal remained in the same state for over a predetermined time. In noise processing input mode, a high or low level on external input activates the counter and if the input signal remains in the same state for over a predetermined time before the counter underflows, the counter generates an interrupt request before stopping. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and when a valid-level signal is en- tered again, the counter is reloaded with the initial count and restarts counting. The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. An interrupt request can be generated by a counter underflow. (3) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts counting down synchronously with the count clock. The first time the counter underflows, it is loaded with the reload 1 register value and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The F/F output waveform in PWM output mode is inverted when the counter starts counting and each time it underflows. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). An interrupt request can be generated when the counter underflows every other time (second time, fourth time and so on) after being enabled.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0) (4) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload 0 register, the counter is loaded with the reload 0 register value and starts counting synchronously with the count clock. The counter counts down and when the minimum count is reached, stops upon underflow. The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. An interrupt request can be generated when the counter underflows. (5) Delayed single-shot output mode (without correction function) In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) after a finite time equal to (counter set value + 1) only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock. The first time the counter underflows, it is loaded with the reload 0 register value and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) after a finite time equal to (first set value of counter + 1) only once. An interrupt request can be generated when the counter underflows first time and next. (6) Continuous output mode (without correction function) In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses in width of (reload 0 register set value + 1). When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be loaded with the content of the reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each time the counter underflows.

32180 Group User’s Manual (Rev.1.0) <Count clock-dependent delay>  Because the timer operates synchronously with the count clock, there is a count clock-dependent delay from when the timer is enabled till when it actually starts operating. In operation mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is inverted. BCLK Count clock Enable F/F operation (Note 1) Count clock period Count clock-dependent delay Write to the enable bit Note 1: This applies to the case where F/F output is inverted when the timer is enabled. Inverted Figure 10.4.2 Count Clock Dependent Delay

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0)

10.4.3 TIO Related Register Map

Shown below is a TIO related register map. TIO Related Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0300 TIO0 Counter 10-109 (TIO0CT) H'0080 0302 (Use inhibited area) H'0080 0304 TIO0 Reload 1 Register 10-111 (TIO0RL1) H'0080 0306 TIO0 Reload 0/Measure Register 10-110 (TIO0RL0) (Use inhibited area) H'0080 0310 TIO1 Counter 10-109 (TIO1CT) H'0080 0312 (Use inhibited area) H'0080 0314 TIO1 Reload 1 Register 10-111 (TIO1RL1) H'0080 0316 TIO1 Reload 0/Measure Register 10-110 (TIO1RL0) H'0080 0318 (Use inhibited area) H'0080 031A TIO0 –3 Control Register 0 10-102 (TIO03CR0) H'0080 031C (Use inhibited area) TIO0 –3 Control Register 1 10-103 (TIO03CR1) (Use inhibited area) H'0080 0320 TIO2 Counter 10-109 (TIO2CT) H'0080 0322 (Use inhibited area) H'0080 0324 TIO2 Reload 1 Register 10-111 (TIO2RL1) H'0080 0326 TIO2 Reload 0/Measure Register 10-110 (TIO2RL0) (Use inhibited area) H'0080 0330 TIO3 Counter 10-109 (TIO3CT) H'0080 0332 (Use inhibited area) H'0080 0334 TIO3 Reload 1 Register 10-111 (TIO3RL1) H'0080 0336 TIO3 Reload 0/Measure Register 10-110 (TIO3RL0) (Use inhibited area) H'0080 0340 TIO4 Counter 10-109 (TIO4CT) H'0080 0342 (Use inhibited area) H'0080 0344 TIO4 Reload 1 Register 10-111 (TIO4RL1) H'0080 0346 TIO4 Reload 0/Measure Register 10-110 (TIO4RL0) H'0080 0348 (Use inhibited area) H'0080 034A TIO4 Control Register TIO5 Control Register 10-104 (TIO4CR) (TIO5CR) 10-106 (Use inhibited area)

32180 Group User’s Manual (Rev.1.0) TIO Related Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0350 TIO5 Counter 10-109 (TIO5CT) H'0080 0352 (Use inhibited area) H'0080 0354 TIO5 Reload 1 Register 10-111 (TIO5RL1) H'0080 0356 TIO5 Reload 0/Measure Register 10-110 (TIO5RL0) (Use inhibited area) H'0080 0360 TIO6 Counter 10-109 (TIO6CT) H'0080 0362 (Use inhibited area) H'0080 0364 TIO6 Reload 1 Register 10-111 (TIO6RL1) H'0080 0366 TIO6 Reload 0/Measure Register 10-110 (TIO6RL0) H'0080 0368 (Use inhibited area) H'0080 036A TIO6 Control Register TIO7 Control Register 10-107 (TIO6CR) (TIO7CR) 10-108 (Use inhibited area) H'0080 0370 TIO7 Counter 10-109 (TIO7CT) H'0080 0372 (Use inhibited area) H'0080 0374 TIO7 Reload 1 Register 10-111 (TIO7RL1) H'0080 0376 TIO7 Reload 0/Measure Register 10-110 (TIO7RL0) (Use inhibited area) H'0080 0380 TIO8 Counter 10-109 (TIO8CT) H'0080 0382 (Use inhibited area) H'0080 0384 TIO8 Reload 1 Register 10-111 (TIO8RL1) H'0080 0386 TIO8 Reload 0/Measure Register 10-110 (TIO8RL0) H'0080 0388 (Use inhibited area) H'0080 038A TIO8 Control Register TIO9 Control Register 10-108 (TIO8CR) (TIO9CR) 10-109 (Use inhibited area) H'0080 0390 TIO9 Counter 10-109 (TIO9CT) H'0080 0392 (Use inhibited area) H'0080 0394 TIO9 Reload 1 Register 10-111 (TIO9RL1) H'0080 0396 TIO9 Reload 0/Measure Register 10-110 (TIO9RL0) (Use inhibited area) H'0080 03BC TIO Enable Protect Register 10-112 (TIOPRO) H'0080 03BE TIO Count Enable Register 10-113 (TIOCEN)

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0)

10.4.4 TIO Control Registers

The TIO control registers are used to select operation modes of TIO0–9 (measure input, noise processing input, PWM output, single-shot output, delayed single-shot output or continuous output mode), as well as select the count enable and count clock sources. Following TIO control registers are provided for each timer group.  TIO0–3 Control Register 0 (TIO03CR0)  TIO0–3 Control Register 1 (TIO03CR1)  TIO4 Control Register (TIO4CR)  TIO5 Control Register (TIO5CR)  TIO6 Control Register (TIO6CR)  TIO7 Control Register (TIO7CR)  TIO8 Control Register (TIO8CR)  TIO9 Control Register (TIO9CR)

32180 Group User’s Manual (Rev.1.0) TIO0–3 Control Register 0 (TIO03CR0) <Address: H ’0080 031A> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO3EEN TIO2ENS TIO3M TIO2M TIO1M TIO0M TIO1ENS TIO0ENS 0000000000000000 <After reset: H’0000> b Bit Name Function R W

0 TIO3EEN (Note 1) 0: Disable external input R W

TIO3 external input enable bit 1: Enable external input 1–3 TIO3M 000: Single-shot output mode R W TIO3 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: – ditto –

4 TIO2ENS 0: No selection R W

TIO2 enable/measure input source select bit 1: External input TIN5 5–7 TIO2M 000: Single-shot output mode R W TIO2 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: – ditto –

8 TIO1ENS 0: No selection R W

TIO1 enable/measure input source select bit 1: External input TIN4 9–11 TIO1M 000: Single-shot output mode R W TIO1 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: – ditto –

12 TIO0ENS 0: No selection R W

TIO0 enable/measure input source select bit 1: External input TIN3 13–15 TIO0M 000: Single-shot output mode R W TIO0 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: – ditto – Note 1: During measure free-run/clear input mode, even if this bit is set to "0" (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written into the measure register. In measure clear input mode, however, if this bit = "0" (external input disabled), the counter value is not initialized (H’FFFF) upon capture and, therefore, this bit should be set to "1" (external input enabled) when using measure clear input mode. Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive.  To select TIO3 enable/measure input sources, use the TIO4 Control Register TIO34ENS (TIO3, TIO4 enable/measure input source select) bits.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0) TIO0–3 Control Register 1 (TIO03CR1) <Address: H ’0080 031D> 9 1 01 11 21 31 4 b 1 5b8 TIO03CKS 000 0 0 0 0 0 <After reset: H’0000> b Bit Name Function R W 8–13 No function assigned. Fix to "0". 00 14, 15 TIO03CKS 00: Clock bus 0 R W TIO0–3 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Figure 10.4.3 Outline Diagram of TIO0–4 Clock and Enable Inputs Clock bus Input event bus 3 2 1 0 clk en/cap TIO 0 clk en/cap TIO 1 clk en/cap TIO 2 clk en/cap TIO 3 clk en/cap TIO 4 S STIN3STIN3 (P153) S S TIN4STIN4 (P154) TIN5STIN5 (P155) S S TIN6STIN6 (P156) S : Selector 3 2 1 0 3 2 1 0 3 2 1 0 Note:  This diagram only illustrates TIO control registers and is partly omitted.

32180 Group User’s Manual (Rev.1.0) TIO4 Control Register (TIO4CR) <Address: H ’0080 034A> 123456 b 7b0 TIO4MTIO4EENTIO4CKS TIO34ENS 00000000 <After reset: H’0000> b Bit Name Function R W 0, 1 TIO4CKS 00: Clock bus 3 R W TIO4 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3

2 TIO4EEN (Note 1) 0: Disable external input R W

TIO4 external input enable bit 1: Enable external input 3, 4 TIO34ENS 00: External input TIN6 R W TIO3,4 enable/measure input source select bit 01: – ditto – 10: Input event bus 2 11: Input event bus 3 5–7 TIO4M 000: Single-shot output mode R W TIO4 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: – ditto – Note 1: During measure free-run/clear input mode, even if this bit is set to "0" (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written into the measure register. In measure clear input mode, however, if this bit = "0" (external input disabled), the counter value is not initialized (H’FFFF) upon capture and, therefore, this bit should be set to "1" (external input enabled) when using measure clear input mode. Note:  Operation mode can only be set or changed while the counter is inactive.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0) clk en/capS TCLK2S STIN8S Clock bus Input event bus 3 2 1 0 TIN7 (P157) TCLK1 (P125) clk en/cap TIO 5S TCLK1S STIN7S TIN8 (P140) TCLK2 (P126) TIO 6 TIN9 (P141) clk en/cap TIO 7S STIN9S TIN10 (P142) S S TIN10S clk en/cap TIO 8 clk en/cap TIO 9 TIN11 (P143) S STIN11S S : Selector 3 2 1 0 3 2 1 0 3 2 1 0 Note:  This diagram only illustrates TIO control registers and is partly omitted. Figure 10.4.4 Outline Diagram of TIO5–9 Clock and Enable Inputs

32180 Group User’s Manual (Rev.1.0) TIO5 Control Register (TIO5CR) <Address: H ’0080 034B> 9 1 01 11 21 31 4 b 1 5b8 TIO5MTIO5CKS TIO5ENS 00000000 <After reset: H’00> b Bit Name Function R W 8–10 TIO5CKS 000: External input TCLK1 R W TIO5 clock source select bit 001: – ditto – 010: – ditto – 011: – ditto – 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 11, 12 TIO5ENS 00: No selection R W TIO5 enable/measure input source select bit 01: – ditto – 10: External input TIN7 11: Input event bus 3 13–15 TIO5M 000: Single-shot output mode R W TIO5 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: – ditto – Note:  Operation mode can only be set or changed while the counter is inactive.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0) TIO6 Control Register (TIO6CR) <Address: H ’0080 036A>

123456 D 7D0

<After reset: H’00> b Bit Name Function R W 0–2 TIO6CKS 000: External input TCLK2 R W TIO6 clock source select bit 001: – ditto – 010: – ditto – 011: – ditto – 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 3, 4 TIO6ENS 00: No selection R W TIO6 enable/measure input source select bit 01: External input TIN8 10: Input event bus 2 11: Input event bus 3 5–7 TIO6M 000: Single-shot output mode R W TIO6 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: – ditto – Note:  Operation mode can only be set or changed while the counter is inactive.

32180 Group User’s Manual (Rev.1.0) TIO7 Control Register (TIO7CR) <Address: H ’0080 036B> 9 1 01 11 21 31 4 b 1 5b8 TIO7MTIO7CKS TIO7ENS 00000000 <After reset: H’00> b Bit Name Function R W 8 No function assigned. Fix to "0". 00 9, 10 TIO7CKS 00: Clock bus 0 R W TIO7 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11, 12 TIO7ENS 00: No selection R W TIO7 enable/measure input source select bit 01: External input TIN9 10: Input event bus 0 11: Input event bus 3 13–15 TIO7M 000: Single-shot output mode R W TIO7 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: – ditto – Note:  Operation mode can only be set or changed while the counter is inactive. TIO8 Control Register (TIO8CR) <Address: H ’0080 038A> 123456 b 7b0 TIO8MTIO8CKS TIO8ENS 00000000 <After reset: H’00> b Bit Name Function R W 0, 1 TIO8CKS 100: Clock bus 0 R W TIO8 clock source select bit 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 2–4 TIO8ENS 000: No selection R W TIO8 enable/measure input source select bit 001: – ditto – 010: – ditto – 011: – ditto – 100: External input TIN10 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 5–7 TIO8M 000: Single-shot output mode R W TIO8 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: – ditto – Note:  Operation mode can only be set or changed while the counter is inactive.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0)

10.4.5 TIO Counters (TIO0CT–TIO9CT)

TIO0 Counter (TIO0CT) <Address: H ’0080 0300> TIO1 Counter (TIO1CT) <Address: H ’0080 0310> TIO2 Counter (TIO2CT) <Address: H ’0080 0320> TIO3 Counter (TIO3CT) <Address: H ’0080 0330> TIO4 Counter (TIO4CT) <Address: H ’0080 0340> TIO5 Counter (TIO5CT) <Address: H ’0080 0350> TIO6 Counter (TIO6CT) <Address: H ’0080 0360> TIO7 Counter (TIO7CT) <Address: H ’0080 0370> TIO8 Counter (TIO8CT) <Address: H ’0080 0380> TIO9 Counter (TIO9CT) <Address: H ’0080 0390> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO0CT –TIO9CT <After reset: Undefined> b Bit Name Function R W 0–15 TIO0CT –TIO9CT 16-bit reload counter value R(Note 1) Note 1: Protected against write during PWM output mode. Note:  This register must always be accessed in halfwords. The TIO counters are a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by external input), the counter starts counting synchronously with the count clock. These counters are protected against write during PWM output mode. TIO9 Control Register (TIO9CR) <Address: H ’0080 038B> 9 1 01 11 21 31 4 b 1 5b8 TIO9MTIO9CKS TIO9ENS 00000000 <After reset: H’00> b Bit Name Function R W 8 No function assigned. Fix to "0". 00 9, 10 TIO9CKS 00: Clock bus 0 R W TIO9 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11, 12 TIO9ENS 00: No selection R W TIO9 enable/measure input source select bit 01: External input TIN11 10: Input event bus 1 11: Input event bus 3 13–15 TIO9M 000: Single-shot output mode R W TIO9 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: – ditto – Note:  Operation mode can only be set or changed while the counter is inactive.

32180 Group User’s Manual (Rev.1.0)

10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0)

TIO0 Reload 0/ Measure Register (TIO0RL0) <Address: H ’0080 0306> TIO1 Reload 0/ Measure Register (TIO1RL0) <Address: H ’0080 0316> TIO2 Reload 0/ Measure Register (TIO2RL0) <Address: H ’0080 0326> TIO3 Reload 0/ Measure Register (TIO3RL0) <Address: H ’0080 0336> TIO4 Reload 0/ Measure Register (TIO4RL0) <Address: H ’0080 0346> TIO5 Reload 0/ Measure Register (TIO5RL0) <Address: H ’0080 0356> TIO6 Reload 0/ Measure Register (TIO6RL0) <Address: H ’0080 0366> TIO7 Reload 0/ Measure Register (TIO7RL0) <Address: H ’0080 0376> TIO8 Reload 0/ Measure Register (TIO8RL0) <Address: H ’0080 0386> TIO9 Reload 0/ Measure Register (TIO9RL0) <Address: H ’0080 0396> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO0RL0 –TIO9RL0 <After reset: Undefined> b Bit Name Function R W 0–15 TIO0RL0 –TIO9RL0 16-bit reload register value R(Note 1) Note 1: This register is protected against write during measure input mode. Note:  This register must always be accessed in halfwords. The TIO Reload 0/ Measure Registers serve dual purposes as a register for reloading data into the TIO Count Registers (TIO0CT–TIO9CT) and as a measure register during measure input mode. These registers are pro- tected against write during measure input mode. The content of the reload 0 register is loaded into the counter in the following cases:  When after the counter started counting in noise processing input mode, the input signal is inverted and a valid-level signal is entered again before the counter underflows  When the counter is enabled in single-shot output mode  When the counter underflowed in delayed single-shot output or continuous output mode  When the counter is enabled in PWM output mode and when the counter value set by the reload 1 register underflowed Simply because data is written to the reload 0 register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. If this register is used as a measure register, the counter value is latched into that measure register by event input.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0)

10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1)

TIO0 Reload 1 Register (TIO0RL1) <Address: H ’0080 0304> TIO1 Reload 1 Register (TIO1RL1) <Address: H ’0080 0314> TIO2 Reload 1 Register (TIO2RL1) <Address: H ’0080 0324> TIO3 Reload 1 Register (TIO3RL1) <Address: H ’0080 0334> TIO4 Reload 1 Register (TIO4RL1) <Address: H ’0080 0344> TIO5 Reload 1 Register (TIO5RL1) <Address: H ’0080 0354> TIO6 Reload 1 Register (TIO6RL1) <Address: H ’0080 0364> TIO7 Reload 1 Register (TIO7RL1) <Address: H ’0080 0374> TIO8 Reload 1 Register (TIO8RL1) <Address: H ’0080 0384> TIO9 Reload 1 Register (TIO9RL1) <Address: H ’0080 0394> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO0RL1 –TIO9RL1 <After reset: Undefined> b Bit Name Function R W 0–15 TIO0RL1 –TIO9RL1 16-bit reload register value R W Note:  This register must always be accessed in halfwords. The TIO Reload 1 Registers are used to reload data into the TIO Count Registers (TIO0CT–TIO9CT). The content of the reload 1 register is loaded into the counter in the following cases:  When the count value set by the reload 0 register underflowed in PWM output mode Simply because data is written to the reload 1 register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases.

32180 Group User’s Manual (Rev.1.0)

10.4.8 TIO Enable Control Registers

TIO Enable Protect Register (TIOPRO) <Address: H ’0080 03BC> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO9PRO TIO8PRO TIO7PRO TIO6PRO TIO5PRO TIO4PRO TIO3PRO TIO2PRO TIO1PRO TIO0PRO 0 0 0 0 0 0 0000000000 <After reset: H’0000> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00

6 TIO9PRO (TIO9 enable protect bit) 0: Enable rewrite R W

7 TIO8PRO (TIO8 enable protect bit) 1: Disable rewrite

8 TIO7PRO (TIO7 enable protect bit)

9 TIO6PRO (TIO6 enable protect bit)

10 TIO5PRO (TIO5 enable protect bit)

11 TIO4PRO (TIO4 enable protect bit)

12 TIO3PRO (TIO3 enable protect bit)

13 TIO2PRO (TIO2 enable protect bit)

14 TIO1PRO (TIO1 enable protect bit)

15 TIO0PRO (TIO0 enable protect bit)

Note:  This register must always be accessed in halfwords. The TIO Enable Protect Register controls rewriting of the TIO count enable bit described in the next page by enabling or disabling it.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0) WR Dn TIOm enable protect (TIOmPRO) WR EN-ON TIOm external enable (TIOmEEN or TIOmENS) TINnS TIOm count enable (TIOmCEN) TIO enable control Input processing selection F/F F/F F/F Event bus TINn Figure 10.4.5 Configuration of the TIO Enable Circuit TIO Count Enable Register (TIOCEN) <Address: H ’0080 03BE> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO9CEN TIO8CEN TIO7CEN TIO6CEN TIO5CEN TIO4CEN TIO3CEN TIO2CEN TIO1CEN TIO0CEN 0 0 0 0 0 0 0000000000 <After reset: H’0000> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00

6 TIO9CEN (TIO9 count enable bit) 0: Stop count R W

7 TIO8CEN (TIO8 count enable bit) 1: Enable count

8 TIO7CEN (TIO7 count enable bit)

9 TIO6CEN (TIO6 count enable bit)

10 TIO5CEN (TIO5 count enable bit)

11 TIO4CEN (TIO4 count enable bit)

12 TIO3CEN (TIO3 count enable bit)

13 TIO2CEN (TIO2 count enable bit)

14 TIO1CEN (TIO1 count enable bit)

15 TIO0CEN (TIO0 count enable bit)

Note:  This register must always be accessed in halfwords The TIO Count Enable Register controls operation of the TIO counters. To enable any TIO counter in software, enable its corresponding enable protect bit for write and set the count enable bit by writing "1". To stop any TIO counter, enable its corresponding enable protect bit for write and reset the count enable bit by writing "0". In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable bit is automatically reset to "0". Therefore, the TIO Count Enable Register when accessed for read serves as a status register indicating whether the counter is operating or idle.

32180 Group User’s Manual (Rev.1.0)

10.4.9 Operation in TIO Measure Free-Run/ Clear Input Modes

(1) Outline of TIO measure free-run/ clear input modes In measure free-run/ clear input modes, the timer is used to measure a duration of time from when the counter starts counting till when an external capture signal is entered. An interrupt request can be generated by a counter underflow or execution of a measure operation. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchro- nously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written into a register called the “measure register.” In measure clear input mode, the counter value is initialized to H’FFFF upon capture, from which the counter starts counting down again. When the counter underflows, it starts counting down from H'FFFF. In measure free-run input mode, the counter continues counting down even after capture and upon under- flow, recycles to H’FFFF, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. Figure 10.4.6 Typical Operation in Measure Free-Run Input Mode Count clock Counter H'FFFF H'0000 Enabled (by writing to the enable bit) TIO interrupt request Measure event (capture) occurs Enable bit Note:  This diagram does not show detailed timing information. Measure register TIN interrupt request due to external event input TIO interrupt request due to underflow H'7000 H'9000 Measure event (capture) TIN interrupt request due to external event input TIN interrupt request Undefined value H'7000Undefined H'9000

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0) (2) Precautions on using TIO measure free-run/ clear input modes The following describes precautions to be observed when using TIO measure free-run/ clear input modes.  If measure event input and write to the counter occur in the same clock period, the write value is set in the counter while at the same time latched into the measure register. Figure 10.4.7 Typical Operation in Measure Clear Input Mode H'FFFF H'0000 H'7000 H'0008 Enabled (by writing to the enable bit) Measure event (capture) occurs Count clock Counter TIO interrupt request Enable bit Note:  This diagram does not show detailed timing information. Measure register TIN interrupt request Undefined value TIN interrupt request due to external event input TIO interrupt request due to underflow Undefined

32180 Group User’s Manual (Rev.1.0)

10.4.10 Operation in TIO Noise Processing Input Mode

In noise processing input mode, the timer is used to detect that the input signal remained in the same state for over a predetermined time. In noise processing input mode, a high or low level on external input activates the counter and if the input signal remains in the same state for over a predetermined time before the counter underflows, the counter generates an interrupt request before stopping. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and when a valid-level signal is entered again, the counter is reloaded with the initial count and restarts counting. The effective count width is (reload 0 register set value + 1). The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. An interrupt request can be generated by a counter underflow. Figure 10.4.8 Typical Operation in Noise Processing Input Mode H'FFFF H'0000 Reload 0 register External input (noise processing) H'A000 Effective signal width Invalid Disabled by underflow H'A000 Count clock Counter Enabled (by writing to the enable bit) TIO interrupt request Enable bit Note:  This diagram does not show detailed timing information. Invalid TIO interrupt request due to underflow

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0) Count clock Counter H'FFFF H'0000 Enabled (by writing to the enable bit or by external input) F/F output Underflow (first time) TIO interrupt request due to underflow Enable bit Note:  This diagram does not show detailed timing information. Reload 0 register H'A000 Underflow (second time) Count down from the reload 1 register set value H'(C000-1) H'(A000-1) Reload 1 register H'C000 Count down from the reload 1 register set value H'A000 PWM output period H'C000 H'A000 Undefined value Count down from the reload 0 register set value Data inverted by underflow Data inverted by enable Data inverted by underflow H'(A000-1) Figure 10.4.9 Typical Operation in PWM Output Mode

10.4.11 Operation in TIO PWM Output Mode

(1) Outline of TIO PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts counting down synchronously with the count clock. The first time the counter underflows, it is loaded with the reload 1 register value and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The (reload 0 register set value + 1) and (reload 1 register set value + 1) respectively are effective as count values. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output level changes from low to high or vice versa) when the counter starts counting and each time it underflows. An interrupt request can be generated when the counter underflows every other time (second time, fourth time and so on) after being enabled. Note that TIO’s PWM output mode does not have the count correction function.

32180 Group User’s Manual (Rev.1.0) To rewrite the reload 0 and reload 1 registers while the timer is operating, rewrite the reload 1 register first and then the reload 0 register. That way, the reload 0 and reload 1 registers both are updated synchronously with PWM period, from which the timer starts operating. This operation can normally be performed collec- tively by accessing 32-bit addresses beginning with the reload 1 register address wordwise. (Data are auto- matically written to the reload 1 and then the reload 0 registers in succession.) If the reload 0 and reload 1 registers are updated in the reverse order beginning with reload 0, only the reload 0 register is updated. Note also that if the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have been written to the respective registers, and not the reload values being actually used. When altering PWM period by rewriting the reload registers, if the PWM period terminates before the CPU finishes writing to reload 0, the PWM period is not altered in the current session and the data written to the register is reflected in the next period. (3) Precautions on using TIO PWM output mode The following describes precautions to be observed when using TIO PWM output mode.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.  Because the timer operates synchronously with the count clock, a count clock-dependent delay is in- cluded before F/F output is inverted after the timer is enabled. (2) Reload register updates in TIO PWM output mode In PWM output mode, when the timer remains idle, the reload 0 and reload 1 registers are updated at the same time data are written to the respective registers. But when the timer is operating, the reload 1 register is updated by updating the reload 0 register. However, if the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have been written to the respective registers. Internal bus TIOnRL1 Reload 1 Reload 1 WR Reload 0 WR Buffer 16-bit counterPrescaler output F/F TO TIOnRL0 Reload 0 PWM mode control Figure 10.4.10 PWM Circuit Diagram

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0) Figure 10.4.11 Reload 0 and Reload 1 Register Updates in PWM Output Mode (a) When reload register updates take effect in the current period (reflected in the next period) Count clock Reload 0 register Reload 1 register H'0001 H'FFFF H'1000 H'7FFF H'2000 H'8000 H'9000 Counter Interrupt due to underflow Timing at which reload 0 and reload 1 registers are updated Operation by new reload value written Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (Reload 1 data latched) H'1000 H'2000 H'8000 H'9000 Enlarged view Old PWM output period F/F output H'7FFEH'0000 PWM period latched Reload 1 buffer H'2000 H'9000 New PWM output period New PWM output period Note:  This diagram does not show detailed timing information. H'0001 H'FFFF H'1000 H'0FFF H'2000 H'8000 H'9000 (b) When reload register updates take effect in the next period (reflected one period later) Operation by old reload value H'1000 H'2000 H'8000 H'9000 H'0FFEH'0000 H'2000 H'9000 Write to reload 1 Write to reload 0 (Reload 1 data latched) Old PWM output period Old PWM output period Old PWM output period Timing at which reload 0 and reload 1 registers are updated PWM period latched Count clock Reload 0 register Reload 1 register Counter Interrupt due to underflow Reload 0 register Reload 1 register F/F output Enlarged view F/F output Reload 1 buffer

32180 Group User’s Manual (Rev.1.0)

10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function)

(1) Outline of TIO single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload 0 register, the counter is loaded with the content of the reload 0 register and starts counting synchronously with the count clock. The counter counts down and when the minimum count is reached, stops upon under- flow. The F/F output waveform in single-shot output mode is inverted (F/F output level changes from low to high or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. An interrupt request can be generated when the counter underflows. The count value is (reload 0 register set value + 1). (For counting operation, see also Section 10.3.9, “Opera- tion of TOP Single-shot Output Mode.”) (2) Precautions on using TIO single-shot output mode The following describes precautions to be observed when using TIO single-shot output mode.  If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.  If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  Because the timer operates synchronously with the count clock, a count clock-dependent delay is in- cluded before F/F output is inverted after the timer is enabled.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0) Count clock H'FFFF H'0000 Enabled (by writing to the enable bit or by external input) F/F output Disabled (by underflow) (Unused) TIO interrupt request due to underflow Enable bit Count down from the reload 0 register set value Note:  This diagram does not show detailed timing information. Reload 0 registerH'A000 H'A000 Counter Reload 1 register Undefined value H'(A000-1) Data inverted by enable Data inverted by underflow Figure 10.4.12 Typical Operation in TIO Single-shot Output Mode (without Correction Function)

32180 Group User’s Manual (Rev.1.0)

10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function)

(1) Outline of TIO delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) after a finite time equal to (counter set value + 1) only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock. The first time the counter underflows, it is loaded with the reload 0 register value and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from low to high or vice versa) when the counter underflows first time and next, generating a single-shot pulse wave- form in width of (reload 0 register set value + 1) after a finite time equal to (first set value of counter + 1) only once. An interrupt request can be generated when the counter underflows first time and next. The (counter set value + 1) and (reload 0 register set value + 1) are effective as count values. (For counting operation, see also Section 10.3.10, “Operation of TOP Delayed Single-shot Output Mode.”) (2) Precautions on using TIO delayed single-shot output mode The following describes precautions to be observed when using TIO delayed single-shot output mode.  If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.  If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0) H'FFFF H'0000 Underflow (first time) Count down from the counter set valueH'A000 Underflow (second time) H'F000 Count down from the reload 0 register set value H'EFFF H'F000 Data inverted by underflow Data inverted by underflow Count clock F/F output (Unused) TIO interrupt request due to underflow Enable bit Note:  This diagram does not show detailed timing information. Reload 0 register Counter Reload 1 register Enabled (by writing to the enable bit or by external input) Figure 10.4.13 Typical Operation in TIO Delayed Single-shot Output Mode (without Correction Function)

32180 Group User’s Manual (Rev.1.0)

10.4.14 Operation in TIO Continuous Output Mode (without Correction Function)

(1) Outline of TIO continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload 0 register set value + 1). When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be loaded with the content of the reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output level changes from low to high or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each time the counter underflows. The (counter set value + 1) and (reload 0 register set value + 1) are effective as count values. (For counting operation, see also Section 10.3.11, “Operation of TOP Continuous Output Mode.”) (2) Precautions on using TIO continuous output mode The following describes precautions to be observed when using TIO continuous output mode.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.  Because the timer operates synchronously with the count clock, a count clock-dependent delay is in- cluded before F/F output is inverted after the timer is enabled.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 32180 Group User’s Manual (Rev.1.0) H'FFFF H'0000 H'E000 H'A000 H'E000 H'DFFF H'DFFF (Unused) Data inverted by enable Data inverted by underflow Data inverted by underflow Count clock F/F output TIO interrupt request due to underflow Enable bit Note:  This diagram does not show detailed timing information. Reload 0 register Counter Reload 1 register Underflow (first time) Count down from thecounter set value Underflow (second time) Count down from the reload 0 register set value Enabled (by writing to the enable bit or by external input) Count down from the reload 0 register set value Figure 10.4.14 Typical Operation in TIO Continuous Output Mode (without Correction Function)

32180 Group User’s Manual (Rev.1.0)

10.5.1 Outline of TMS

TMS (Timer Measure Small) is an input-related 16-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table below shows specifications of TMS. The diagram in the next page shows a block diagram of TMS. Table 10.5.1 Specifications of TMS (Input-Related 16-Bit Timer) Item Specification Number of channels 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) Counter 16-bit up-counter × 2 Measure register 16-bit measure register × 8 Timer startup Started by writing to the enable bit in software Interrupt request generation Can be generated by a counter overflow

10.5.2 Outline of TMS Operation

In TMS, when the timer is enabled (by writing to the enable bit in software), the counter starts operating. The counter is a 16-bit up-counter, where when a measure signal is entered from an external device, the counter value is latched into each measure register. The counter stops counting at the same time count is disabled by writing to the enable bit in software. TIN and TMS interrupt requests can be generated by external measure signal input and counter overflow, respectively.

32180 Group User’s Manual (Rev.1.0) Clock bus Input event bus 3 2 1 0 3 2 1 0 clk TMS 0 S ovf cap3 cap2 cap1 cap0 S S S S TCLK3 (P127) TCLK3S TIN12S DMA3 TIN13S IRQ10 TIN12 (P144) TIN13 (P145) TIN14STIN14 (P146) TIN15STIN15 (P147) S S S S S TIN16S DMA5 TIN17S TIN16 (P130) TIN17 (P131) TIN18STIN18 (P132) TIN19STIN19 (P133) DMA6 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 Output event bus 0 1 2 3 IRQ7 S : Selector 3 2 1 0 3 2 1 0 0 1 2 3 Measure register 3Counter (16-bit) clk TMS 1 ovf cap3 cap2 cap1 cap0 IRQ7 Counter (16-bit) Measure register 2 Measure register 1 Measure register 0 Measure register 3 Measure register 2 Measure register 1 Measure register 0 Figure 10.5.1 Block Diagram of TMS (Input-Related 16-Bit Timer)

32180 Group User’s Manual (Rev.1.0)

10.5.3 TMS Related Register Map

Shown below is a TMS related register map. TMS Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 03C0 TMS0 Counter 10-130 (TMS0CT) H'0080 03C2 TMS0 Measure 3 Register 10-130 (TMS0MR3) H'0080 03C4 TMS0 Measure 2 Register 10-130 (TMS0MR2) H'0080 03C6 TMS0 Measure 1 Register 10-130 (TMS0MR1) H'0080 03C8 TMS0 Measure 0 Register 10-130 (TMS0MR0) H'0080 03CA TMS0 Control Register TMS1 Control Register 10-129 (TMS0CR) (TMS1CR) (Use inhibited area) H'0080 03D0 TMS1 Counter 10-130 (TMS1CT) H'0080 03D2 TMS1 Measure 3 Register 10-130 (TMS1MR3) H'0080 03D4 TMS1 Measure 2 Register 10-130 (TMS1MR2) H'0080 03D6 TMS1 Measure 1 Register 10-130 (TMS1MR1) H'0080 03D8 TMS1 Measure 0 Register 10-130 (TMS1MR0) <Count clock-dependent delay>  Because the timer operates synchronously with the count clock, there is a count clock-dependent delay from when the timer is enabled till when it actually starts operating. Figure 10.5.2 Count Clock-Dependent Delay BCLK Count clock Enable Count clock period Count clock-dependent delay Write to the enable bit

32180 Group User’s Manual (Rev.1.0)

10.5.4 TMS Control Registers

The TMS control registers are used to select TMS0/1 input events and count clock sources, as well as control count enable. Following two TMS control registers are included:  TMS0 Control Register (TMS0CR)  TMS1 Control Register (TMS1CR) TMS0 Control Register (TMS0CR) <Address: H ’0080 03CA> 123456 b 7b0 TMS0SS0 TMS0SS1 TMS0SS2 TMS0SS3 TMS0CKS TMS0CEN 000000 0 0 <After reset: H’00> b Bit Name Function R W

0 TMS0SS0 0: External input TIN15 R W

TMS0 measure 0 source select bit 1: Input event bus 0

1 TMS0SS1 0: External input TIN14 R W

TMS0 measure 1 source select bit 1: Input event bus 1

2 TMS0SS2 0: External input TIN13 R W

TMS0 measure 2 source select bit 1: Input event bus 2

3 TMS0SS3 0: External input TIN12 R W

TMS0 measure 3 source select bit 1: Input event bus 3 4, 5 TMS0CKS 00: External input TCLK3 R W TMS0 clock source select bit 01: Clock bus 0 10: Clock bus 1 11: Clock bus 3 6 No function assigned. Fix to "0". 00

7 TMS0CEN 0: Stop count R W

TMS0 count enable bit 1: Start count TMS1 Control Register (TMS1CR) <Address: H ’0080 03CB> 9 1 01 11 21 31 4 b 1 5b8 TMS1SS0 TMS1SS1 TMS1SS2 TMS1SS3 TMS1CKS TMS1CEN 0000 0 0 00 <After reset: H’00> b Bit Name Function R W

8 TMS1SS0 0: External input TIN19 R W

TMS1 measure 0 source select bit 1: Input event bus 0

9 TMS1SS1 0: External input TIN18 R W

TMS1 measure 1 source select bit 1: Input event bus 1

10 TMS1SS2 0: External input TIN17 R W

TMS1 measure 2 source select bit 1: Input event bus 2

11 TMS1SS3 0: External input TIN16 R W

TMS1 measure 3 source select bit 1: Input event bus 3 12 No function assigned. Fix to "0". 00

13 TMS1CKS 0: Clock bus 0 R W

TMS1 clock source select bit 1: Clock bus 3 14 No function assigned. Fix to "0". 00

15 TMS1CEN 0: Stop count R W

TMS1 count enable bit 1: Start count

32180 Group User’s Manual (Rev.1.0)

10.5.5 TMS Counters (TMS0CT, TMS1CT)

TMS0 Counter (TMS0CT) <Address: H ’0080 03C0> TMS1 Counter (TMS1CT) <Address: H ’0080 03D0> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TMS0CT,TMS1CT <After reset: Undefined> b Bit Name Function R W 0–15 TMS0CT, TMS1CT 16-bit counter value R W Note:  This register must always be accessed in halfwords. The TMS counters are a 16-bit up-counter, which starts counting when the timer is enabled (by writing to the enable bit in software). The counters can be read on-the-fly.

10.5.6 TMS Measure Registers (TMS0MR3–0, TMS1MR3–0)

TMS0 Measure 3 Register (TMS0MR3) <Address: H ’0080 03C2> TMS0 Measure 2 Register (TMS0MR2) <Address: H ’0080 03C4> TMS0 Measure 1 Register (TMS0MR1) <Address: H ’0080 03C6> TMS0 Measure 0 Register (TMS0MR0) <Address: H ’0080 03C8> TMS1 Measure 3 Register (TMS1MR3) <Address: H ’0080 03D2> TMS1 Measure 2 Register (TMS1MR2) <Address: H ’0080 03D4> TMS1 Measure 1 Register (TMS1MR1) <Address: H ’0080 03D6> TMS1 Measure 0 Register (TMS1MR0) <Address: H ’0080 03D8> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TMS0MR3 –0,TMS1MR3 –0 <After reset: Undefined> b Bit Name Function R W 0–15 TMS0MR3-TMS0MR0 16-bit measured value R – TMS1MR3-TMS1MR0 Notes:  This register is a read-only register.  This register can be accessed in either byte or halfword. The TMS measure registers are used to latch counter contents upon event input. The TMS measure registers are a read-only register.

32180 Group User’s Manual (Rev.1.0)

10.5.7 Operation of TMS Measure Input

(1) Outline of TMS measure input In TMS measure input, when the timer is enabled (by writing to the enable bit in software), it starts counting up synchronously with the count clock. Then when event input to TMS is detected while the timer is operat- ing, the counter value is latched into measure registers 0–3. The timer stops counting at the same time count is disabled by writing to the enable bit. A TIN interrupt request can be generated by measure signal input from an external device. A TMS interrupt request can be generated when the counter overflows. Count clock Counter H'FFFF H'0000 Enabled (by writing to the enable bit) Measure event 1 occurs Undefined Enable bit Note:  This diagram does not show detailed timing information. Measure 0 register H'8000 Overflow occurs TIN15 interrupt request H'C000 Measure 1 register TIN14 interrupt request Measure event 0 occurs TMS interrupt request due to overflow H'6000 H'D000 H'6000H'8000 Undefined value Undefined H'D000H'C000 Measure event 1 occurs Measure event 0 occurs Figure 10.5.3 Typical Operation of TMS Measure Input (2) Precautions on using TMS measure input The following describes precautions to be observed when using TMS measure input.  If measure event input and write to the counter occur in the same clock period, the write value is set in the counter while at the same time latched into the measure register.

32180 Group User’s Manual (Rev.1.0) Figure 10.6.1 Block Diagram of TML (Input-Related 32-Bit Timer) Clock bus Input event bus 3 2 1 03 2 1 0 S S S S TIN20S TIN21S TIN20 (P134) TIN21 (P135) TIN22STIN22 (P136) TIN23STIN23 (P137) IRQ11 IRQ11 IRQ11 IRQ11 BCLK/2 Output event bus 0 1 2 3 S : Selector 3 2 1 0 3 2 1 0 0 1 2 3 clk TML0 cap3 cap2 cap1 cap0 Measure register 3Counter (32-bit) S S S S S TIN30S TIN31S TIN30 (P194) TIN31 (P195) TIN32STIN32 (P196) TIN33STIN33 (P197) IRQ18 IRQ18 IRQ18 IRQ18 clk TML1 cap3 cap2 cap1 cap0 S Measure register 2 Measure register 1 Measure register 0 Measure register 3 Measure register 2 Measure register 1 Measure register 0 Counter (32-bit)

10.6.1 Outline of TML

TML (Timer Measure Large) is an input-related 32-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table below shows specifications of TML. The diagram in the next page shows a block diagram of TML. Table 10.6.1 Specifications of TML (Input-Related 32-Bit Timer) Item Specification Number of channels 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) Input clock BCLK/2 (10.0 MHz when f(BCLK) = 20 MHz) or clock bus 1 input Counter 32-bit up-counter × 2 Measure register 32-bit measure register × 8 Timer startup Start counting immediately after reset

32180 Group User’s Manual (Rev.1.0)

10.6.2 Outline of TML Operation

In TML, the timer starts counting upon deassertion of the reset input signal. The counter included in the timer is a 32-bit up-counter, where when a measure event signal is entered from an external device, the counter value at that point in time is stored in each 32-bit measure register. When the reset input signal is deasserted, the counter starts operating with a BCLK/2 clock, and cannot be stopped once it has started. The counter is idle only when the microcomputer remains reset. A TIN interrupt request can be generated by external measure signal input. However, no TML counter overflow interrupts are available.

10.6.3 TML Related Register Map

Shown below is a TML related register map. TML Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 03E0 TML0 Counter (Upper) 10-135 (TML0CT) H'0080 03E2 (Lower) H'0080 03EA (Use inhibited area) TML0 Control Register 10-134 (TML0CR) (Use inhibited area) H'0080 03F0 TML0 Measure 3 Register (Upper) 10-135 (TML0MR3) H'0080 03F2 (Lower) H'0080 03F4 TML0 Measure 2 Register (Upper) 10-135 (TML0MR2) H'0080 03F6 (Lower) H'0080 03F8 TML0 Measure 1 Register (Upper) 10-135 (TML0MR1) H'0080 03FA (Lower) H'0080 03FC TML0 Measure 0 Register (Upper) 10-135 (TML0MR0) H'0080 03FE (Lower) H'0080 0FE0 TML1 Counter (Upper) 10-135 (TML1CT) H'0080 0FE2 (Lower) (Use inhibited area) H'0080 0FEA (Use inhibited area) TML1 Control Register 10-134 (TML1CR) (Use inhibited area) H'0080 0FF0 TML1 Measure 3 Register (Upper) 10-135 (TML1MR3) H'0080 0FF2 (Lower) H'0080 0FF4 TML1 Measure 2 Register (Upper) 10-135 (TML1MR2) H'0080 0FF6 (Lower) H'0080 0FF8 TML1 Measure 1 Register (Upper) 10-135 (TML1MR1) H'0080 0FFA (Lower) H'0080 0FFC TML1 Measure 0 Register (Upper) 10-135 (TML1MR0) H'0080 0FFE (Lower)

32180 Group User’s Manual (Rev.1.0)

10.6.4 TML Control Registers

TML0 Control Register (TML0CR) <Address: H ’0080 03EB> 9 1 01 11 21 31 4 b 1 5b8 TML0SS0 TML0SS1 TML0SS2 TML0SS3 TML0CKS 0000 0 0 0 0 <After reset: H’00> b Bit Name Function R W

8 TML0SS0 0: External input TIN23 R W

TML0 measure 0 source select bit 1: Input event bus 0

9 TML0SS1 0: External input TIN22 R W

TML0 measure 1 source select bit 1: Input event bus 1

10 TML0SS2 0: External input TIN21 R W

TML0 measure 2 source select bit 1: Input event bus 2

11 TML0SS3 0: External input TIN20 R W

TML0 measure 3 source select bit 1: Input event bus 3 12–14 No function assigned. Fix to "0". 00

15 TML0CKS (Note 1) 0: BCLK/2 R W

TML0 clock source select bit 1: Clock bus 1 Note 1: The counter can only be written normally when BCLK/2 is used as the clock source for the counter. If the selected clock source is not BCLK/2, do not write to the counter because it cannot be written normally. TML1 Control Register (TML1CR) <Address: H ’0080 0FEB> 9 1 01 11 21 31 4 b 1 5b8 TML1SS0 TML1SS1 TML1SS2 TML1SS3 TML1CKS 0000 0 0 0 0 <After reset: H’00> b Bit Name Function R W

8 TML1SS0 0: External input TIN33 R W

TML1 measure 0 source select bit 1: Input event bus 0

9 TML1SS1 0: External input TIN32 R W

TML1 measure 1 source select bit 1: Input event bus 1

10 TML1SS2 0: External input TIN31 R W

TML1 measure 2 source select bit 1: Input event bus 2

11 TML1SS3 0: External input TIN30 R W

TML1 measure 3 source select bit 1: Input event bus 3 12–14 No function assigned. Fix to "0". 00

15 TML1CKS (Note 1) 0: BCLK/2 R W

TML1 clock source select bit 1: Clock bus 1 Note 1: The counter can only be written normally when BCLK/2 is used as the clock source for the counter. If the selected clock source is not BCLK/2, do not write to the counter because it cannot be written normally. The TML control register is used to select TML input event and count clock.

32180 Group User’s Manual (Rev.1.0)

10.6.5 TML Counters

TML0 Counter (TML0CT) <Address: H ’0080 03E0> TML1 Counter (TML1CT) <Address: H ’0080 0FE0> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TML0CT, TML1CT(16 high-order bits) b16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b31 (16 low-order bits) <After reset: Undefined> b Bit Name Function R W 0–31 TML0CT 32-bit counter value R(Note 1) Note 1: If the clock source selected for the counter is not BCLK/2, do not write to this register. Note:  This register must always be accessed wordwise (in 32 bits) beginning with the word boundary. The TML counters are a 32-bit up-counter, which starts counting upon deassertion of the reset input signal. The counters can be read on-the-fly.

10.6.6 TML Measure Registers

TML0 Measure 3 Register (TML0MR3) <Address: H ’0080 03F0> TML0 Measure 2 Register (TML0MR2) <Address: H ’0080 03F4> TML0 Measure 1 Register (TML0MR1) <Address: H ’0080 03F8> TML0 Measure 0 Register (TML0MR0) <Address: H ’0080 03FC> TML1 Measure 3 Register (TML1MR3) <Address: H ’0080 0FF0> TML1 Measure 2 Register (TML1MR2) <Address: H ’0080 0FF4> TML1 Measure 1 Register (TML1MR1) <Address: H ’0080 0FF8> TML1 Measure 0 Register (TML1MR0) <Address: H ’0080 0FFC> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TML0MR3 –TML0MR0, TML1MR3 –TML1MR0 (16 high-order bits) b16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (16 low-order bits) <After reset: Undefined> b Bit Name Function R W 0–31 TML0MR3 –TML0MR0, TML1MR3 –TML1MR0 32-bit measure register value R – Notes:  These registers are a read-only register.  These registers must always be accessed wordwise (in 32 bits) beginning with the word boundary. The TML measure registers are a 32-bit register, which is used to latch the counter content upon event input. The TML measure registers can only be read, and cannot be written to.

32180 Group User’s Manual (Rev.1.0)

10.6.7 Operation of TML Measure Input

(1) Outline of TML measure input In TML measure input, when the reset input signal is deasserted, the counter starts counting up synchro- nously with the count clock. Upon event input to measure registers 0–3, the counter value is latched into each measure register. A TIN interrupt request can be generated by measure signal input from an external device. However, no TML counter overflow interrupts are available. Figure 10.6.2 Typical Operation of TML Measure Input Count clock Counter (32-bit) H'FFFF FFFF H'0000 0000 Enabled (by deassertion of reset) Undefined Reset Note:  This diagram does not show detailed timing information. Measure 0 register Overflow occurs TIN23 interrupt request Measure 1 register TIN22 interrupt request Measure event 0 occurs H'8000 0000 H'C000 0000 H'8000 0000 H'6000 0000 H'6000 0000 H'D000 0000 Undefined value Undefined H'C000 0000 H'D000 0000 Measure event 0 occurs Measure event 0 occurs Measure event 0 occurs

32180 Group User’s Manual (Rev.1.0) (2) Precautions on using TML measure input The following describes precautions to be observed when using TML measure input.  If measure event input and write to the counter occur in the same clock period, the write value is set in the counter, whereas the up-count value (before being rewritten) is latched into the measure register.  If clock bus 1 is selected and any clock other than BCLK/2 is used for the timer, the counter cannot be written normally. Therefore, when using any clock other than BCLK/2, do not write to the counter.  If clock bus 1 is selected and any clock other than BCLK/2 is used for the timer, the value captured into the measure register is one count larger the counter value. During the count clock to BCLK/2 period interval, however, the captured value is exactly the counter value. The diagram below shows the relationship between counter operation and the valid data that can be cap- tured. Counter BAC D E F AB CD E  When BCLK/2 is selected BCLK/2 Captured Counter BA C  When clock bus 1 is selected BCLK/2 Count clock Captured BC D F Figure 10.6.3 Mistimed Counter Value and the Captured Value

32180 Group User’s Manual (Rev.1.0)

10.7.1 Outline of TID

TID (Timer Input Derivation) is an input-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time:  Fixed period count mode  Event count mode  Multiply-by-4 event count mode  Up/down event count mode The table below shows specifications of TID. The diagram in the next page shows a block diagram of TID. Table 10.7.1 Specifications of TID (Input-Related 16-Bit Timer) Item Specification Number of channels 3 channels Counter 16-bit up/down-counter Reload register 16-bit reload register Timer startup Started by writing to the enable bit in software Operation mode <Input modes>  Fixed period count mode  Event count mode  Multiply-by-4 event count mode  Up/down event count mode Interrupt request generation Can be generated by counter underflow and overflow

32180 Group User’s Manual (Rev.1.0) IRQ14 IRQ11 IRQ11 DMA0 TOU0_0 –7en TOU1_0 –7en TOU2_0 –7enTOU2_7udf TOU1_7udf TOU0_7udf Output event bus 0 IRQ17 DMA2 IRQ15, AD1TRG(To A-D1 converter) DMA1 BCLK/2 TIN24(P172) TIN25(P173) IRQ11 IRQ11 BCLK/2 TIN26(P190) TIN27(P191) IRQ11 IRQ11 BCLK/2 TIN28(P192) TIN29(P193) TID 0 clk CLK1 CLK2 ovf udf TIN25S PRS3 TIN27S TIN29S S S S TIN24S TIN26S TIN28S Clock control Reload register Up/down-counter TID 1 clk CLK1 CLK2 ovf udf Clock control Reload register TID 2 clk CLK1 CLK2 ovf udf Clock control Reload register PRS4 PRS5 Up/down-counter Up/down-counter Figure 10.7.1 Block Diagram of TID (Input-Related 16-Bit Timer) <Count clock-dependent delay>  Because the timer operates synchronously with the count clock, there is a count clock-dependent delay from when the timer is enabled till when it actually starts operating. BCLK Count clock Enable Count clock period Count clock-dependent delay Write to the enable bit Figure 10.7.2 Count Clock Dependent Delay

32180 Group User’s Manual (Rev.1.0)

10.7.2 TID Related Register Map

Shown below is a TID related register map. TID Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 078C TID0 Counter 10-144 (TID0CT) H'0080 078E TID0 Reload Register 10-144 (TID0RL) H'0080 07D0 Prescaler Register 3 TID0 Control & Prescaler 3 Enable Register 10-12 (PRS3) (TID0PRS3EN) 10-141 H'0080 0B8C TID1 Counter 10-144 (TID1CT) H'0080 0B8E TID1 Reload Register 10-144 (TID1RL) H'0080 0BD0 Prescaler Register 4 TID1 Control & Prescaler 4 Enable Register 10-12 (PRS4) (TID1PRS4EN) 10-142 H'0080 0C8C TID2 Counter 10-144 (TID2CT) H'0080 0C8E TID2 Reload Register 10-144 (TID2RL) H'0080 0CD0 Prescaler Register 5 TID2 Control & Prescaler 5 Enable Register 10-12 (PRS5) (TID2PRS5EN) 10-143

32180 Group User’s Manual (Rev.1.0)

10.7.3 TID Control & Prescaler Enable Registers

TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) <Address: H ’0080 07D1> 9 1 01 11 21 31 4 b 1 5b8 TID0M TID0CEN TOU0ENS PRS3EN 00000000 <After reset: H’00> b Bit Name Function R W 8–10 TID0M 000: Fixed period count mode R W TID0 operation mode select bit 001: – ditto– 010: Multiply-by-4 event count mode 011: Event count mode 100: Fixed period count mode 101: – ditto – 110: Multiply-by-4 event count mode 111: Up/down event count mode

11 TID0CEN 0: Stop TID0 count R W

TID0 count enable bit 1: Start TID0 count 12–14 TOU0ENS 000: Disable event enable R W TOU0 enable source select bit 001: – ditto – 010: TID0 underflow/overflow 011: TOU0_7 underflow 100: Disable event enable 101: – ditto – 110: Output event bus 0 111: External input TIN25 signal

15 PRS3EN 0: Stop count R W

Prescaler 3 enable bit 1: Start count Note:  Operation mode can only be set or changed while the counter is inactive. The TID0 Control & Prescaler 3 Enable Register is used to select TID0 operation mode (Fixed period count, Event count, Multiply-by-4 event count or Up/down event count mode), as well as select TOU0_0–7 timer enable sources and control prescaler 3 startup.

32180 Group User’s Manual (Rev.1.0) TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) <Address: H ’0080 0BD1> 9 1 01 11 21 31 4 b 1 5b8 TID1M TID1CEN TOU1ENO PRS4EN 00000000 <After reset: H’00> b Bit Name Function R W 8–10 TID1M 000: Fixed period count mode R W TID1 operation mode select bit 001: – ditto– 010: Multiply-by-4 event count mode 011: Event count mode 100: Fixed period count mode 101: – ditto – 110: Multiply-by-4 event count mode 111: Up/down event count mode

11 TID1CEN 0: Stop TID1 count R W

TID1 count enable bit 1: Start TID1 count 12–14 TOU1ENS 000: Disable event enable R W TOU1 enable source select bit 001: – ditto – 010: TID1 underflow/overflow 011: TOU1_7 underflow 100: Disable event enable 101: – ditto – 110: TOU0 startup source (Note 1) (The enable source selected by TOU0ENS) 111: External input TIN27 signal

15 PRS4EN 0: Stop prescaler 4 count R W

Prescaler 4 enable bit 1: Start prescaler 4 count Note 1: Any event must be selected using the TOU0 enable source select bit. Note:  Operation mode can only be set or changed while the counter is inactive. The TID1 Control & Prescaler 4 Enable Register is used to select TID1 operation mode (Fixed period count, Event count, Multiply-by-4 event count or Up/down event count mode), as well as select TOU1_0–7 timer enable sources and control prescaler 4 startup.

32180 Group User’s Manual (Rev.1.0) TID2 Control & Prescaler 5 Enable Register (TID2PRS5EN) <Address: H ’0080 0CD1> 9 1 01 11 21 31 4 b 1 5b8 TID2M TID2CEN TOU2ENO PRS5EN 00000000 <After reset: H’00> b Bit Name Function R W 8–10 TID2M 000: Fixed period count mode R W TID2 operation mode select bit 001: – ditto– 010: Multiply-by-4 event count mode 011: Event count mode 100: Fixed period count mode 101: – ditto – 110: Multiply-by-4 event count mode 111: Up/down event count mode

11 TID2CEN 0: Stop TID2 count R W

TID2 count enable bit 1: Start TID2 count 12–14 TOU2ENS 000: Disable event enable R W TOU2 enable source select bit 001: – ditto – 010: TID2 underflow/overflow 011: TOU2_7 underflow 100: Disable event enable 101: – ditto – 110: TOU0 startup source (Note 1) (The enable source selected by TOU0ENS) 111: External input TIN29 signal

15 PRS5EN 0: Stop prescaler 5 count R W

Prescaler 5 enable bit 1: Start prescaler 5 count Note 1: Any event must be selected using the TOU0 enable source select bit. Note:  Operation mode can only be set or changed while the counter is inactive. The TID2 Control & Prescaler 5 Enable Register is used to select TID2 operation mode (Fixed period count, Event count, Multiply-by-4 event count or Up/down event count mode), as well as select TOU2_0–7 timer enable sources and control prescaler 5 startup.

32180 Group User’s Manual (Rev.1.0)

10.7.4 TID Counters (TID0CT, TID1CT and TID2CT)

TID0 Counter (TID0CT) <Address: H ’0080 078C> TID1 Counter (TID1CT) <Address: H ’0080 0B8C> TID2 Counter (TID2CT) <Address: H ’0080 0C8C> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TID0CT, TID1CT, TID2CT <After reset: Undefined> b Bit Name Function R W 0–15 TID0CT, TID1CT, TID2CT 16-bit counter value R W Note:  This register must always be accessed in halfwords. The TID counters are a 16-bit up/down-counter. After the timer is enabled (by writing to the enable bit in soft- ware), the counter starts counting synchronously with the count clock.

10.7.5 TID Reload Registers (TID0RL, TID1RL and TID2RL)

TID0 Reload Register (TID0RL) <Address: H ’0080 078E> TID1 Reload Register (TID1RL) <Address: H ’0080 0B8E> TID2 Reload Register (TID2RL) <Address: H ’0080 0C8E> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TID0RL, TID1RL, TID2RL <After reset: Undefined> b Bit Name Function R W 0–15 TID0RL,TID1RL,TID2RL 16-bit reload register value R W Note:  This register must always be accessed in halfwords. The TID reload registers are used to reload data into the TID counter registers (TID0CT, TID1CT and TID2CT). The content of the reload register is loaded into the counter in the following cases:  When the counter is enabled in fixed period count mode  When the counter has underflowed in fixed period count mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases.

32180 Group User’s Manual (Rev.1.0)

10.7.6 Outline of Each Mode of TID

Each mode of TID is outlined below. TID modes can be selected from the following, only one at a time. (1) Fixed period count mode In fixed period count mode, the timer uses a reload register to generate an interrupt request at intervals of (reload register set value + 1). When the timer is enabled (by writing to the enable bit in software) after setting the reload register (initial value being undefined), the counter is loaded with the content of the reload register and starts counting synchronously with the count clock. The counter counts down and when it underflows after reaching the minimum count, the counter is loaded with the content of the reload register and continues counting. To stop the counter, disable count by writing to the enable bit in software. An interrupt request can be generated each time the counter underflows. The (reload register set value + 1) is effective as count value. Count clock Counter H'FFFF H'0000 Enabled (by writing to the enable bit) Underflow (first time) TID0 interrupt request due to underflow Enable bit Count down from the reload register set value Note:  This diagram does not show detailed timing information. Reload register H'E000 Underflow (second time) Count down from the reload register set value Count down from the reload register set valueUndefined value Figure 10.7.3 Typical Operation in TID Fixed Period Count Mode

32180 Group User’s Manual (Rev.1.0) (2) Event count mode In event count mode, the timer uses an external input signal (TIN24, TIN26 or TIN28) as the clock source for the counter. Note:  TIN25, TIN27 and TIN29 cannot be used as the clock source for the counter. By detecting the rising and falling edges of the external input signal (TIN24, TIN26 or TIN28), the timer generates clock pulses synchronized to the microcomputer’s internal clock. When after setting the counter the timer is enabled (by writing to the enable bit in software), the counter starts counting up from the set count value synchronously with the generated clock. An interrupt request can be generated by a counter overflow. To stop the counter, disable count by writing to the enable bit in software or fix the external input signal either "high" or "low". TIN24 (TIN26, TIN28) Counter value 7FFF 8000 8001 8002 8003 8004 Figure 10.7.4 Typical Operation in TID Event Count Mode (Basic Operation) Figure 10.7.5 Typical Operation in TID Event Count Mode (when Overflow Occurs) TIN24 (TIN26, TIN28) Counter value FFFE FFFF 0000 0001 0002 0003 TID interrupt request due to overflow FFFD

32180 Group User’s Manual (Rev.1.0) (3) Multiply-by-4 event count mode In multiply-by-4 event count mode, the timer uses two external input signals in pairs (TIN24 and TIN25, TIN26 and TIN27, or TIN28 and TIN29) as the clock sources for the counter. The count direction is switched between up-count and down-count depending on the status of the two input signals. By detecting the rising and falling edges on both of the two external input signals, the timer generates clock pulses synchronized to the microcomputer’s internal clock. When after setting the counter the timer is en- abled (by writing to the enable bit in software), the counter starts counting synchronously with the generated clock. To know whether the counter counts up or counts down, see Table 10.7.2 below. An interrupt request can be generated when the counter underflows or overflows. To stop the counter, disable count by writing to the enable bit in software or fix the external input signals either "high" or "low". Table 10.7.2 Count Direction during Multiply-by-4 Event Count Mode TIN24 (TIN26, TIN28) TIN25 (TIN27, TIN29) Input H H L L H L L H Up-count Down-count Count Direction

32180 Group User’s Manual (Rev.1.0) Figure 10.7.6 Multiply-by-4 Count Operation (Switchover Timing) TIN24 (TIN26, TIN28) TIN25 (TIN27, TIN29) Up-count Down-count 8000 8001 8002 8001 8000 8003 7FFE 8003Counter value Counter 80027FFF7FFE 7FFF 7FFE Switched over Figure 10.7.7 Multiply-by-4 Count Operation (Count Enabled/Disabled) 8000 TIN24 (TIN26, TIN28) TIN25 (TIN27, TIN29) 8001 8000 8001 7FFE 7FFF7FFE Timer enable Count disabled Count enabled 7FFF enabled Up-count Down-count Counter value Counter Switched over Count disabled Count disabled Count enabled TID output interrupt request TIN24 (TIN26, TIN28) TIN25 (TIN27, TIN29) FFFF 0000 0001 0000 FFFF FFFF 0000 00020001FFFEFFFD FFFE FFFD Up-count Down-count Switched over Counter value Counter Figure 10.7.8 Multiply-by-4 Count Operation (Interrupt Request Timing)

32180 Group User’s Manual (Rev.1.0) (4) Up/down event count mode In up/down event count mode, the timer uses one of two-channel external input signals (TIN24, TIN26 or TIN28) as the clock source for the counter and the other (TIN25, TIN27 or TIN29) as an up/down select signal. The counter is switched between up-count and down-count depending on the status of the up/down select input signal. By detecting the rising and falling edges of the external input signal selected as the clock source, the timer generates clock pulses synchronized to the microcomputer’s internal clock. When after setting the counter the timer is enabled, the counter starts counting up or down synchronously with the generated clock. The count direction is determined by the level of the up/down select input signal (see Table 10.7.3). An interrupt request can be generated when the counter underflows or overflows. To stop the counter, disable count by writing to the enable bit in software or fix the external input signal selected as the clock source either "high" or "low". Note that TIN25, TIN27 and TIN29 cannot be used as the clock source. Table 10.7.3 Count Direction during Up/Down Event Count Mode TIN24 (TIN26, TIN28) TIN25 (TIN27, TIN29) Input Up-count Down-count Count Direction Low level High level Figure 10.7.9 Up/Down Count Operation Figure 10.7.10 Up/Down Count Operation (Interrupt Request Timing) TIN25 (TIN27, TIN29) Counter value 7FFF 7FFF8000 8001 8002 8001 8000 Up-count Down-count TIN24 (TIN26, TIN28) FFFD FFFE FFFF 0000 0001 0002 0003 0002 0001 0000 FFFF FFFE FFFD TIN24 (TIN26, TIN28) TIN25 (TIN27, TIN29) Counter value TID output interrupt request due to overflow or underflow

32180 Group User’s Manual (Rev.1.0)

10.8.1 Outline of TOU

TOU (Timer Output Unification) is an output-related 24-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time. <Output modes without correction function>  PWM output mode  Single-shot PWM output mode  Delayed single-shot output mode  Single-shot output mode  Continuous output mode The table below shows specifications of TOU. The diagram in the next page shows a block diagram of TOU. Table 10.8.1 Specifications of TOU (Output-Related 24-Bit Timer) Item Specification Number of channels 24 channels (8 channels × 3 circuit blocks) Counter 24-bit down-counter (or 16-bit down counter when in PWM output or single-shot PWM output mode) Reload register 24-bit reload register (or 16-bit reload register when in PWM output or single-shot PWM output mode) Timer startup TOU0:  Writing to the enable bit in software  TID0 underflow/overflow signal  TOU0_7 underflow signal  Output event bus 0 signal  External input TIN25 signal TOU1:  Writing to the enable bit in software  TID1 underflow/overflow signal  TOU1_7 underflow signal  TOU0 cause of start signal (Event enable must be selected by TOU0)  External input TIN27 signal TOU2:  Writing to the enable bit in software  TID2 underflow/overflow signal  TOU2_7 underflow signal  TOU0 cause of start signal (Event enable must be selected by TOU0)  External input TIN29 signal Mode switching <Output modes without correction function>  PWM output mode  Single-shot PWM output mode  Delayed single-shot output mode  Single-shot output mode  Continuous output mode Interrupt request generation Can be generated by a counter underflow

32180 Group User’s Manual (Rev.1.0) TIN16/PWMOFF0 (P130) BCLK/2 TIN24 (P172) TIN25 (P173) TIN17/PWMOFF1 (P131) BCLK/2 TIN26 (P190) TIN27 (P191) TIN33/PWMOFF2 (P197) BCLK/2 TIN28 (P192) TIN29 (P193) TO21 (P160) TO22 (P161) TO23 (P162) TO24 (P163) TO25 (P164) TO26 (P165) TO27 (P166) TO28 (P167) TO29 (P180) TO30 (P181) TO31 (P182) TO32 (P183) TO33 (P184) TO34 (P185) TO35 (P186) TO36 (P187) TO37 (P210) TO38 (P211) TO39 (P212) TO40 (P213) TO41 (P214) TO42 (P215) TO43 (P216) TO44 (P217) IRQ11 IRQ11 IRQ11 IRQ11 IRQ11 IRQ11 DMA5 DMA6 DMA7 DMA8 DMA9 DMA0 DMA4 DMA1 DMA5 DMA2 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ14 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ15, AD1TRG (To A-D1 converter) IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ17 TOU0_0 (24-bit)clk en udf TOU0_1 (24-bit)clk en udf TOU0_2 (24-bit)clk en udf TOU0_3 (24-bit)clk en udf TOU0_4 (24-bit)clk en udf TOU0_5 (24-bit)clk en udf TOU0_6 (24-bit)clk en udf TOU0_7 (24-bit)clk en udf TID 0clkCLK1 CLK2 ovf udf TOU1_0 (24-bit)clk en udf TOU1_1 (24-bit)clk en udf TOU1_2 (24-bit)clk en udf TOU1_3 (24-bit)clk en udf TOU1_4 (24-bit)clk en udf TOU1_5 (24-bit)clk en udf TOU1_6 (24-bit)clk en udf TOU1_7 (24-bit)clk en udf TID 1clkCLK1 CLK2 ovf udf TOU2_0 (24-bit)clk en udf TOU2_1 (24-bit)clk en udf TOU2_2 (24-bit)clk en udf TOU2_3 (24-bit)clk en udf TOU2_4 (24-bit)clk en udf TOU2_5 (24-bit)clk en udf TOU2_6 (24-bit)clk en udf TOU2_7 (24-bit)clk en udf TID 2clkCLK1 CLK2 ovf udf F/F37 F/F38 F/F39 F/F40 F/F41 F/F42 F/F43 F/F44 TIN25S PWMOFF1S PWMOFF2S PWMOFF0S PO1DIS PO2DIS PO0DIS TIN24S PRS3 F/F29 F/F30 F/F31 F/F32 F/F33 F/F34 F/F35 F/F36 F/F21 F/F22 F/F23 F/F24 F/F25 F/F26 F/F27 F/F28S TIN27S TIN26S PRS4 S TIN29S TIN28S PRS5 S S S S Output event bus Figure 10.8.1 Block Diagram of TOU (Output-Related 24-Bit Timer)

32180 Group User’s Manual (Rev.1.0)

10.8.2 Outline of Each Mode of TOU

Each mode of TOU is outlined below. Modes on each TOU channel can be selected from the following, only one at a time. (1) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. During PWM output mode, the timer operates as a 16-bit timer. When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts counting down synchronously with the count clock. The first time the counter underflows, it is loaded with the reload 1 register value and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The F/F output waveform in PWM output mode is inverted when the counter starts counting and each time it underflows. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). An interrupt request and DMA transfer request can be generated when the counter underflows every other time (second time, fourth time and so on) after being enabled. (2) Single-shot PWM output mode (without correction function) In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle only once. During PWM output mode, the timer operates as a 16-bit timer. When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts counting down synchronously with the count clock. The first time the counter underflows, it is loaded with the reload 1 register value and continues counting. The counter stops when it underflows next time. The (reload 0 register set value + 1) and (reload 1 register set value + 1) respectively are effective as count values. The timer can be stopped in software, in which case it stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in single-shot PWM output mode is inverted (F/F output level changes from low to high or vice versa) each time the counter underflows. (Unlike in PWM output mode, the F/F output is not inverted when the counter is enabled.) An interrupt request and DMA transfer request can be generated when the counter underflows second time after being enabled. (3) Delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) after a finite time equal to (counter set value + 1) only once and then stops. When the timer is enabled after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. The first time the counter underflows, it is loaded with the reload register value and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload register set value + 1) after a finite time equal to (first set value of counter + 1) only once. An interrupt request and DMA transfer request can be generated when the counter underflows first time and next.

32180 Group User’s Manual (Rev.1.0) BCLK Count clock Enable F/F operation (Note 1) Count clock period Count clock-dependent delay Write to the enable bit Note 1: This applies to the case where F/F output is inverted when the timer is enabled. Inverted Figure 10.8.2 Count Clock Dependent Delay (4) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once and then stops. When the timer is enabled after setting the reload register, the counter is loaded with the content of the reload register and starts counting synchronously with the count clock. The counter counts down and when the minimum count is reached, stops upon underflow. The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of (reload register set value + 1) only once. An interrupt request and DMA transfer request can be generated when the counter underflows. (5) Continuous output mode (without correction function) In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses in width of (reload register set value + 1). When the timer is enabled after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be loaded with the content of the reload register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request and DMA transfer re- quest can be generated each time the counter underflows. <Count clock-dependent delay>  Because the timer operates synchronously with the count clock, there is a count clock-dependent delay from when the timer is enabled till when it actually starts operating. In operation mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is inverted.

32180 Group User’s Manual (Rev.1.0)

10.8.3 TOU Related Register Map

Shown below is a TOU related register map. TOU Related Register Map (1/4) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0780 PWM Output 0 Disable Control Register PWM Output 0 Disable Level Control Register 10-174 (PO0DISCR) (PO0LVCR) 10-177 H'0080 0782 PWM Output 1 Disable Control Register PWM Output 1 Disable Level Control Register 10-174 (PO1DISCR) (PO1LVCR) 10-177 H'0080 0784 PWM Output 2 Disable Control Register PWM Output 2 Disable Level Control Register 10-175 (PO2DISCR) (PO2LVCR) 10-177 H'0080 0790 TOU0_0 Counter (Upper) 10-161 (TOU00CTW) (TOU00CTH) H'0080 0792 (Lower) 10-163 (TOU00CT) H'0080 0794 TOU0_0 Reload Register TOU0_0 Reload 1 Register 10-164 (TOU00RLW) (TOU00RL1) 10-167 H'0080 0796 TOU0_0 Reload 0 Register 10-166 (TOU00RL0) H'0080 0798 TOU0_1 Counter (Upper) 10-161 (TOU01CTW) (TOU01CTH) H'0080 079A (Lower) 10-163 (TOU01CT) H'0080 079C TOU0_1 Reload Register TOU0_1 Reload 1 Register 10-164 (TOU01RLW) (TOU01RL1) 10-167 H'0080 079E TOU0_1 Reload 0 Register 10-166 (TOU01RL0) H'0080 07A0 TOU0_2 Counter (Upper) 10-161 (TOU02CTW) (TOU02CTH) H'0080 07A2 (Lower) 10-163 (TOU02CT) H'0080 07A4 TOU0_2 Reload Register TOU0_2 Reload 1 Register 10-164 (TOU02RLW) (TOU02RL1) 10-167 H'0080 07A6 TOU0_2 Reload 0 Register 10-166 (TOU02RL0) H'0080 07A8 TOU0_3 Counter (Upper) 10-161 (TOU03CTW) (TOU03CTH) H'0080 07AA (Lower) 10-163 (TOU03CT) H'0080 07AC TOU0_3 Reload Register TOU0_3 Reload 1 Register 10-164 (TOU03RLW) (TOU03RL1) 10-167 H'0080 07AE TOU0_3 Reload 0 Register 10-166 (TOU03RL0) H'0080 07B0 TOU0_4 Counter (Upper) 10-161 (TOU04CTW) (TOU04CTH) H'0080 07B2 (Lower) 10-163 (TOU04CT) H'0080 07B4 TOU0_4 Reload Register TOU0_4 Reload 1 Register 10-164 (TOU04RLW) (TOU04RL1) 10-167 H'0080 07B6 TOU0_4 Reload 0 Register 10-166 (TOU04RL0) H'0080 07B8 TOU0_5 Counter (Upper) 10-161 (TOU05CTW) (TOU05CTH) H'0080 07BA (Lower) 10-163 (TOU05CT) H'0080 07BC TOU0_5 Reload Register TOU0_5 Reload 1 Register 10-164 (TOU05RLW) (TOU05RL1) 10-167 H'0080 07BE TOU0_5 Reload 0 Register 10-166 (TOU05RL0) H'0080 07C0 TOU0_6 Counter (Upper) 10-161 (TOU06CTW) (TOU06CTH) H'0080 07C2 (Lower) 10-163 (TOU06CT) H'0080 07C4 TOU0_6 Reload Register TOU0_6 Reload 1 Register 10-164 (TOU06RLW) (TOU06RL1) 10-167 H'0080 07C6 TOU0_6 Reload 0 Register 10-166 (TOU06RL0)

32180 Group User’s Manual (Rev.1.0) TOU Related Register Map (2/4) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 07C8 TOU0_7 Counter (Upper) 10-161 (TOU07CTW) (TOU07CTH) H'0080 07CA (Lower) 10-163 (TOU07CT) H'0080 07CC TOU0_7 Reload Register TOU0_7 Reload 1 Register 10-164 (TOU07RLW) (TOU07RL1) 10-167 H'0080 07CE TOU0_7 Reload 0 Register 10-166 (TOU07RL0) H'0080 07D2 TOU0 Interrupt Request Mask Register TOU0 Interrupt Request Status Register 10-58 (TOU0IMA) (TOU0IST) H'0080 07D8 TOU0 Control Register 1 10-158 (TOU0CR1) H'0080 07DA TOU0 Control Register 0 10-158 (TOU0CR0) H'0080 07DC (Use inhibited area) TOU0 Enable Protect Register 10-168 (TOU0PRO) H'0080 07DE (Use inhibited area) TOU0 Count Enable Register 10-169 (TOU0CEN) H'0080 07E0 PWMOFF0 Input Processing Control Register 10-171 (PWMOFF0CR) H'0080 0B90 TOU1_0 Counter (Upper) 10-161 (TOU10CTW) (TOU10CTH) H'0080 0B92 (Lower) 10-163 (TOU10CT) H'0080 0B94 TOU1_0 Reload Register TOU1_0 Reload 1 Register 10-164 (TOU10RLW) (TOU10RL1) 10-167 H'0080 0B96 TOU1_0 Reload 0 Register 10-166 (TOU10RL0) H'0080 0B98 TOU1_1 Counter (Upper) 10-161 (TOU11CTW) (TOU11CTH) H'0080 0B9A (Lower) 10-163 (TOU11CT) H'0080 0B9C TOU1_1 Reload Register TOU1_1 Reload 1 Register 10-164 (TOU11RLW) (TOU11RL1) 10-167 H'0080 0B9E TOU1_1 Reload 0 Register 10-166 (TOU11RL0) H'0080 0BA0 TOU1_2 Counter (Upper) 10-161 (TOU12CTW) (TOU12CTH) H'0080 0BA2 (Lower) 10-163 (TOU12CT) H'0080 0BA4 TOU1_2 Reload Register TOU1_2 Reload 1 Register 10-164 (TOU12RLW) (TOU12RL1) 10-167 H'0080 0BA6 TOU1_2 Reload 0 Register 10-166 (TOU12RL0) H'0080 0BA8 TOU1_3 Counter (Upper) 10-161 (TOU13CTW) (TOU13CTH) H'0080 0BAA (Lower) 10-163 (TOU13CT) H'0080 0BAC TOU1_3 Reload Register TOU1_3 Reload 1 Register 10-164 (TOU13RLW) (TOU13RL1) 10-167 H'0080 0BAE TOU1_3 Reload 0 Register 10-166 (TOU13RL0) H'0080 0BB0 TOU1_4 Counter (Upper) 10-161 (TOU14CTW) (TOU14CTH) H'0080 0BB2 (Lower) 10-163 (TOU14CT) H'0080 0BB4 TOU1_4 Reload Register TOU1_4 Reload 1 Register 10-164 (TOU14RLW) (TOU14RL1) 10-167 H'0080 0BB6 TOU1_4 Reload 0 Register 10-166 (TOU14RL0)

32180 Group User’s Manual (Rev.1.0) TOU Related Register Map (3/4) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0BB8 TOU1_5 Counter (Upper) 10-161 (TOU15CTW) (TOU15CTH) H'0080 0BBA (Lower) 10-163 (TOU15CT) H'0080 0BBC TOU1_5 Reload Register TOU1_5 Reload 1 Register 10-164 (TOU15RLW) (TOU15RL1) 10-167 H'0080 0BBE TOU1_5 Reload 0 Register 10-166 (TOU15RL0) H'0080 0BC0 TOU1_6 Counter (Upper) 10-161 (TOU16CTW) (TOU16CTH) H'0080 0BC2 (Lower) 10-163 (TOU16CT) H'0080 0BC4 TOU1_6 Reload Register TOU1_6 Reload 1 Register 10-164 (TOU16RLW) (TOU16RL1) 10-167 H'0080 0BC6 TOU1_6 Reload 0 Register 10-166 (TOU16RL0) H'0080 0BC8 TOU1_7 Counter (Upper) 10-161 (TOU17CTW) (TOU17CTH) H'0080 0BCA (Lower) 10-163 (TOU17CT) H'0080 0BCC TOU1_7 Reload Register TOU1_7 Reload 1 Register 10-164 (TOU17RLW) (TOU17RL1) 10-167 H'0080 0BCE TOU1_7 Reload 0 Register 10-166 (TOU17RL0) H'0080 0BD2 TOU1 Interrupt Request Mask Register TOU1 Interrupt Request Status Register 10-60 (TOU1IMA) (TOU1IST) H'0080 0BD8 TOU1 Control Register 1 10-159 (TOU1CR1) H'0080 0BDA TOU1 Control Register 0 10-159 (TOU1CR0) H'0080 0BDC (Use inhibited area) TOU1 Enable Protect Register 10-168 (TOU1PRO) H'0080 0BDE (Use inhibited area) TOU1 Count Enable Register 10-169 (TOU1CEN) H'0080 0BE0 PWMOFF1 Input Processing Control Register 10-171 (PWMOFF1CR) H'0080 0C90 TOU2_0 Counter (Upper) 10-161 (TOU20CTW) (TOU20CTH) H'0080 0C92 (Lower) 10-163 (TOU20CT) H'0080 0C94 TOU2_0 Reload Register TOU2_0 Reload 1 Register 10-164 (TOU20RLW) (TOU20RL1) 10-167 H'0080 0C96 TOU2_0 Reload 0 Register 10-166 (TOU20RL0) H'0080 0C98 TOU2_1 Counter (Upper) 10-161 (TOU21CTW) (TOU21CTH) H'0080 0C9A (Lower) 10-163 (TOU21CT) H'0080 0C9C TOU2_1 Reload Register TOU2_1 Reload 1 Register 10-164 (TOU21RLW) (TOU21RL1) 10-167 H'0080 0C9E TOU2_1 Reload 0 Register 10-166 (TOU21RL0) H'0080 0CA0 TOU2_2 Counter (Upper) 10-161 (TOU22CTW) (TOU22CTH) H'0080 0CA2 (Lower) 10-163 (TOU22CT) H'0080 0CA4 TOU2_2 Reload Register TOU2_2 Reload 1 Register 10-164 (TOU22RLW) (TOU22RL1) 10-167 H'0080 0CA6 TOU2_2 Reload 0 Register 10-166 (TOU22RL0)

32180 Group User’s Manual (Rev.1.0) TOU Related Register Map (4/4) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0CA8 TOU2_3 Counter (Upper) 10-161 (TOU23CTW) (TOU23CTH) H'0080 0CAA (Lower) 10-163 (TOU23CT) H'0080 0CAC TOU2_3 Reload Register TOU2_3 Reload 1 Register 10-164 (TOU23RLW) (TOU23RL1) 10-167 H'0080 0CAE TOU2_3 Reload 0 Register 10-166 (TOU23RL0) H'0080 0CB0 TOU2_4 Counter (Upper) 10-161 (TOU24CTW) (TOU24CTH) H'0080 0CB2 (Lower) 10-163 (TOU24CT) H'0080 0CB4 TOU2_4 Reload Register TOU2_4 Reload 1 Register 10-164 (TOU24RLW) (TOU24RL1) 10-167 H'0080 0CB6 TOU2_4 Reload 0 Register 10-166 (TOU24RL0) H'0080 0CB8 TOU2_5 Counter (Upper) 10-161 (TOU25CTW) (TOU25CTH) H'0080 0CBA (Lower) 10-163 (TOU25CT) H'0080 0CBC TOU2_5 Reload Register TOU2_5 Reload 1 Register 10-164 (TOU25RLW) (TOU25RL1) 10-167 H'0080 0CBE TOU2_5 Reload 0 Register 10-166 (TOU25RL0) H'0080 0CC0 TOU2_6 Counter (Upper) 10-161 (TOU26CTW) (TOU26CTH) H'0080 0CC2 (Lower) 10-163 (TOU26CT) H'0080 0CC4 TOU2_6 Reload Register TOU2_6 Reload 1 Register 10-164 (TOU26RLW) (TOU26RL1) 10-167 H'0080 0CC6 TOU2_6 Reload 0 Register 10-166 (TOU26RL0) H'0080 0CC8 TOU2_7 Counter (Upper) 10-161 (TOU27CTW) (TOU27CTH) H'0080 0CCA (Lower) 10-163 (TOU27CT) H'0080 0CCC TOU2_7 Reload Register TOU2_7 Reload 1 Register 10-164 (TOU27RLW) (TOU27RL1) 10-167 H'0080 0CCE TOU2_7 Reload 0 Register 10-166 (TOU27RL0) H'0080 0CD2 TOU2 Interrupt Request Mask Register TOU2 Interrupt Request Status Register 10-61 (TOU2IMA) (TOU2IST) H'0080 0CD8 TOU2 Control Register 1 10-160 (TOU2CR1) H'0080 0CDA TOU2 Control Register 0 10-160 (TOU2CR0) H'0080 0CDC (Use inhibited area) TOU2 Enable Protect Register 10-168 (TOU2PRO) H'0080 0CDE (Use inhibited area) TOU2 Count Enable Register 10-169 (TOU2CEN) H'0080 0CE0 PWMOFF2 Input Processing Control Register 10-172 (PWMOFF2CR)

32180 Group User’s Manual (Rev.1.0)

10.8.4 TOU Control Registers

TOU0 Control Register 0 (TOU0CR0) <Address: H ’0080 07DA> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU00M0 TOU01M0 TOU02M0 TOU03M0 TOU04M0 TOU05M0 TOU06M0 TOU07M0 0000000000000000 <After reset: H’0000> b Bit Name Function R W 0, 1 TOU00M0 (TOU0_0 operation mode select 0 bit) 00: Single-shot output mode R W 2, 3 TOU01M0 (TOU0_1 operation mode select 0 bit) 01: Single-shot PWM output mode 4, 5 TOU02M0 (TOU0_2 operation mode select 0 bit) or delayed single-shot output mode (Note 1) 6, 7 TOU03M0 (TOU0_3 operation mode select 0 bit) 10: Continuous output mode 8, 9 TOU04M0 (TOU0_4 operation mode select 0 bit) 11: PWM output mode 10, 11 TOU05M0 (TOU0_5 operation mode select 0 bit) 12, 13 TOU06M0 (TOU0_6 operation mode select 0 bit) 14, 15 TOU07M0 (TOU0_7 operation mode select 0 bit) Note 1: Use TOU0 Control Register 1 to select between these two modes. Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive. TOU0 Control Register 1 (TOU0CR1) <Address: H ’0080 07D8> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU0CKS TOU00M1 TOU01M1 TOU02M1 TOU03M1 TOU05M1 TOU06M1 TOU07M1TOU04M1 0 0 0 0 0 0 0 0 00000000 <After reset: H’0000> b Bit Name Function R W

0 TOU0CKS 0: Use prescaler 3 R W

TOU0 clock source select bit 1: Use external clock (TIN24) 1–7 No function assigned. Fix to "0". 00

8 TOU00M1 (TOU0_0 operation mode select 1 bit) 0: Single-shot PWM output mode R W

9 TOU01M1 (TOU0_1 operation mode select 1 bit) 1: Delayed single-shot output mode

10 TOU02M1 (TOU0_2 operation mode select 1 bit)

11 TOU03M1 (TOU0_3 operation mode select 1 bit)

12 TOU04M1 (TOU0_4 operation mode select 1 bit)

13 TOU05M1 (TOU0_5 operation mode select 1 bit)

14 TOU06M1 (TOU0_6 operation mode select 1 bit)

15 TOU07M1 (TOU0_7 operation mode select 1 bit)

Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive. TOU0 Control Registers 0 and 1 are used to select operation modes of TOU0_0–7. To select prescaler 3 as the clock source for TOU0, make sure the TID0 Control & Prescaler 3 Enable Register’s prescaler 3 enable bit is set to "1". For details, see Section 10.7.3, “TID Control & Prescaler Enable Registers.”

32180 Group User’s Manual (Rev.1.0) TOU1 Control Register 0 (TOU1CR0) <Address: H ’0080 0BDA> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU10M0 TOU11M0 TOU12M0 TOU13M0 TOU14M0 TOU15M0 TOU16M0 TOU17M0 0000000000000000 <After reset: H’0000> b Bit Name Function R W 0, 1 TOU10M0 (TOU1_0 operation mode select 0 bit) 00: Single-shot output mode R W 2, 3 TOU11M0 (TOU1_1 operation mode select 0 bit) 01: Single-shot PWM output mode 4, 5 TOU12M0 (TOU1_2 operation mode select 0 bit) or delayed single-shot output mode (Note 1) 6, 7 TOU13M0 (TOU1_3 operation mode select 0 bit) 10: Continuous output mode 8, 9 TOU14M0 (TOU1_4 operation mode select 0 bit) 11: PWM output mode 10, 11 TOU15M0 (TOU1_5 operation mode select 0 bit) 12, 13 TOU16M0 (TOU1_6 operation mode select 0 bit) 14, 15 TOU17M0 (TOU1_7 operation mode select 0 bit) Note 1: Use TOU1 Control Register 1 to select between these two modes. Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive. TOU1 Control Register 1 (TOU1CR1) <Address: H ’0080 0BD8> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU1CKS TOU10M1 TOU11M1 TOU12M1 TOU13M1 TOU15M1 TOU16M1 TOU17M1TOU14M1 0 0 0 0 0 0 0 0 00000000 <After reset: H’0000> b Bit Name Function R W

0 TOU1CKS 0: Use prescaler 4 R W

TOU1 clock source select bit 1: Use external clock (TIN26) 1–7 No function assigned. Fix to "0". 00

8 TOU10M1 (TOU1_0 operation mode select 1 bit) 0: Single-shot PWM output mode R W

9 TOU11M1 (TOU1_1 operation mode select 1 bit) 1: Delayed single-shot output mode

10 TOU12M1 (TOU1_2 operation mode select 1 bit)

11 TOU13M1 (TOU1_3 operation mode select 1 bit)

12 TOU14M1 (TOU1_4 operation mode select 1 bit)

13 TOU15M1 (TOU1_5 operation mode select 1 bit)

14 TOU16M1 (TOU1_6 operation mode select 1 bit)

15 TOU17M1 (TOU1_7 operation mode select 1 bit)

Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive. TOU1 Control Registers 0 and 1 are used to select operation modes of TOU1_0–7. To select prescaler 4 as the clock source for TOU1, make sure the TID1 Control & Prescaler 4 Enable Register’s prescaler 4 enable bit is set to "1". For details, see Section 10.7.3, “TID Control & Prescaler Enable Registers.”

32180 Group User’s Manual (Rev.1.0) TOU2 Control Register 0 (TOU2CR0) <Address: H ’0080 0CDA> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU20M0 TOU21M0 TOU22M0 TOU23M0 TOU24M0 TOU25M0 TOU26M0 TOU27M0 0000000000000000 <After reset: H’0000> b Bit Name Function R W 0, 1 TOU20M0 (TOU2_0 operation mode select 0 bit) 00: Single-shot output mode R W 2, 3 TOU21M0 (TOU2_1 operation mode select 0 bit) 01: Single-shot PWM output mode 4, 5 TOU22M0 (TOU2_2 operation mode select 0 bit) or delayed single-shot output mode (Note 1) 6, 7 TOU23M0 (TOU2_3 operation mode select 0 bit) 10: Continuous output mode 8, 9 TOU24M0 (TOU2_4 operation mode select 0 bit) 11: PWM output mode 10, 11 TOU25M0 (TOU2_5 operation mode select 0 bit) 12, 13 TOU26M0 (TOU2_6 operation mode select 0 bit) 14, 15 TOU27M0 (TOU2_7 operation mode select 0 bit) Note 1: Use TOU2 Control Register 1 to select between these two modes. Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive. TOU2 Control Register 1 (TOU2CR1) <Address: H ’0080 0CD8> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU2CKS TOU20M1 TOU21M1 TOU22M1 TOU23M1 TOU25M1 TOU26M1 TOU27M1TOU24M1 0 0 0 0 0 0 0 0 00000000 <After reset: H’0000> b Bit Name Function R W

0 TOU2CKS 0: Use prescaler 5 R W

TOU2 clock source select bit 1: Use external clock (TIN28) 1–7 No function assigned. Fix to "0". 00

8 TOU20M1 (TOU2_0 operation mode select 1 bit) 0: Single-shot PWM output mode R W

9 TOU21M1 (TOU2_1 operation mode select 1 bit) 1: Delayed single-shot output mode

10 TOU22M1 (TOU2_2 operation mode select 1 bit)

11 TOU23M1 (TOU2_3 operation mode select 1 bit)

12 TOU24M1 (TOU2_4 operation mode select 1 bit)

13 TOU25M1 (TOU2_5 operation mode select 1 bit)

14 TOU26M1 (TOU2_6 operation mode select 1 bit)

15 TOU27M1 (TOU2_7 operation mode select 1 bit)

Notes:  This register must always be accessed in halfwords.  Operation mode can only be set or changed while the counter is inactive. TOU2 Control Registers 0 and 1 are used to select operation modes of TOU2_0–7. To select prescaler 5 as the clock source for TOU2, make sure the TID2 Control & Prescaler 5 Enable Register’s prescaler 5 enable bit is set to "1". For details, see Section 10.7.3, “TID Control & Prescaler Enable Registers.”

32180 Group User’s Manual (Rev.1.0)

10.8.5 TOU Counters

The TOU counters are functionally different depending on the timer’s operation mode. (1) TOU counters during single-shot output, delayed single-shot output and continuous output modes TOU0_0 Counter (TOU00CTW) <Address: H ’0080 0790> TOU0_1 Counter (TOU01CTW) <Address: H ’0080 0798> TOU0_2 Counter (TOU02CTW) <Address: H ’0080 07A0> TOU0_3 Counter (TOU03CTW) <Address: H ’0080 07A8> TOU0_4 Counter (TOU04CTW) <Address: H ’0080 07B0> TOU0_5 Counter (TOU05CTW) <Address: H ’0080 07B8> TOU0_6 Counter (TOU06CTW) <Address: H ’0080 07C0> TOU0_7 Counter (TOU07CTW) <Address: H ’0080 07C8> TOU1_0 Counter (TOU10CTW) <Address: H ’0080 0B90> TOU1_1 Counter (TOU11CTW) <Address: H ’0080 0B98> TOU1_2 Counter (TOU12CTW) <Address: H ’0080 0BA0> TOU1_3 Counter (TOU13CTW) <Address: H ’0080 0BA8> TOU1_4 Counter (TOU14CTW) <Address: H ’0080 0BB0> TOU1_5 Counter (TOU15CTW) <Address: H ’0080 0BB8> TOU1_6 Counter (TOU16CTW) <Address: H ’0080 0BC0> TOU1_7 Counter (TOU17CTW) <Address: H ’0080 0BC8> TOU2_0 Counter (TOU20CTW) <Address: H ’0080 0C90> TOU2_1 Counter (TOU21CTW) <Address: H ’0080 0C98> TOU2_2 Counter (TOU22CTW) <Address: H ’0080 0CA0> TOU2_3 Counter (TOU23CTW) <Address: H ’0080 0CA8> TOU2_4 Counter (TOU24CTW) <Address: H ’0080 0CB0> TOU2_5 Counter (TOU25CTW) <Address: H ’0080 0CB8> TOU2_6 Counter (TOU26CTW) <Address: H ’0080 0CC0> TOU2_7 Counter (TOU27CTW) <Address: H ’0080 0CC8> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU00C TW –TOU07CTW , TOU10CT W ––TOU17CTW, TOU20CTW –TOU27CTW b16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b31 <After reset: Undefined> b Bit Name Function R W 0–7 No function assigned. Fix to "0" 00 8–31 TOU00CTW-TOU07CTW, 24-bit counter value R W TOU10CTW-TOU17CTW, TOU20CTW-TOU27CTW Note:  The 16 low-order bits must always be accessed in halfwords or more.

32180 Group User’s Manual (Rev.1.0) The TOU counters operate as a 24-bit down-counter when in single-shot output, delayed single-shot output or continuous output mode. After the timer is enabled (by writing to the enable bit in software or upon occurrence of the event selected by the TOU enable source select bit), the counter starts counting synchronously with the count clock. Bits 8–15 and bits 16–31 are the 8 high-order and the 16 low-order bits of the counter, respectively. Bits 0–7 are ignored. When writing to the counter separately in high and low-order bits, rewrite the 8 high-order bits first and then the 16 low-order bits. The 8 high-order bits become effective when the 16 low-order bits are rewritten. If the counter is rewritten in the reverse order beginning with the 16 low-order bits, the value of the 8 high-order bits is not reflected until the next time the 16 low-order bits are rewritten. If the 8 high-order bits are read before the CPU has finished rewriting the 16 low-order bits after rewriting the 8 high-order bits. The read value shows the previous data (when not counting) or the current count of the previous data (when count is in progress), and not the new rewritten data. If the counter is written to in 32-bit units, it is rewritten successively in order of the 8 high- order bits and then the 16 low-order bits automatically. During PWM output or single-shot PWM output mode, the TOU counters operate as a 16-bit down-counter where only the 16 low-order bits are effective. For details, see Section 10.8.5, Paragraph (2), “TOU counters during PWM output and single-shot PWM output modes.” To read the counter on-the-fly, make sure the read timing does not coincide with an underflow of the 16 low- order bits (8 high-order bits decremented). When reading the counter on-the-fly, take the appropriate measure to ensure that the read value is correct by, for example, reading the counter twice in succession. Figure 10.8.3 Example of How to Read the Counter Value Count clock Counter value Lower counter read Upper counter read Read value (first time) FF 0000 FE FFFF FE FFFE FF FFFF Read value is incorrect Smaller of the two (Note 1) FE FFFFRead value (second time) Correct value Note 1: If the counter underflows, the 8 high-order bits become 'FF' and the read value cannot be guaranteed to be correct. Check the count enable bit to see if count is in progress as necessary. Notes:  In cases where the count clock is significantly fast compared with the read interval, read also the lower counter twice as necessary.  If interrupt processing, etc. occurs while reading the counter, the read value cannot be guaranteed to be correct. Therefore, disable interrupts during read.

32180 Group User’s Manual (Rev.1.0) (2) TOU counters during PWM output and single-shot PWM output modes TOU0_0 Counter (TOU00CT) <Address: H ’0080 0792> TOU0_1 Counter (TOU01CT) <Address: H ’0080 079A> TOU0_2 Counter (TOU02CT) <Address: H ’0080 07A2> TOU0_3 Counter (TOU03CT) <Address: H ’0080 07AA> TOU0_4 Counter (TOU04CT) <Address: H ’0080 07B2> TOU0_5 Counter (TOU05CT) <Address: H ’0080 07BA> TOU0_6 Counter (TOU06CT) <Address: H ’0080 07C2> TOU0_7 Counter (TOU07CT) <Address: H ’0080 07CA> TOU1_0 Counter (TOU10CT) <Address: H ’0080 0B92> TOU1_1 Counter (TOU11CT) <Address: H ’0080 0B9A> TOU1_2 Counter (TOU12CT) <Address: H ’0080 0BA2> TOU1_3 Counter (TOU13CT) <Address: H ’0080 0BAA> TOU1_4 Counter (TOU14CT) <Address: H ’0080 0BB2> TOU1_5 Counter (TOU15CT) <Address: H ’0080 0BBA> TOU1_6 Counter (TOU16CT) <Address: H ’0080 0BC2> TOU1_7 Counter (TOU17CT) <Address: H ’0080 0BCA> TOU2_0 Counter (TOU20CT) <Address: H ’0080 0C92> TOU2_1 Counter (TOU21CT) <Address: H ’0080 0C9A> TOU2_2 Counter (TOU22CT) <Address: H ’0080 0CA2> TOU2_3 Counter (TOU23CT) <Address: H ’0080 0CAA> TOU2_4 Counter (TOU24CT) <Address: H ’0080 0CB2> TOU2_5 Counter (TOU25CT) <Address: H ’0080 0CBA> TOU2_6 Counter (TOU26CT) <Address: H ’0080 0CC2> TOU2_7 Counter (TOU27CT) <Address: H ’0080 0CCA> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU00CT-TOU07CT, TOU10CT-TOU17CT, TOU20CT-TOU27CT <After reset: Undefined> b Bit Name Function R W 0–15 TOU00CT –TOU07CT, 16-bit counter value R W TOU10CT –TOU17CT, TOU20CT –TOU27CT Note:  This register must always be accessed in halfwords. The TOU counters operate as a 16-bit down-counter when in PWM output or single-shot PWM output mode. After the timer is enabled (by writing to the enable bit in software or upon occurrence of the event selected by the TOU enable source select bit), the counter starts counting synchronously with the count clock. During single-shot output, delayed single-shot output and continuous output modes, the TOU counters operate as a 24-bit down-counter, with the 8 high-order bits added. For details, see Section 10.8.5, Paragraph (1), “TOU counters during single-shot output, delayed single-shot output and continuous output modes.”

32180 Group User’s Manual (Rev.1.0)

10.8.6 TOU Reload Registers

The TOU reload registers are used to load data into the TOU counters. These registers are functionally different depending on the timer’s operation mode. (1) TOU reload registers during single-shot output, delayed single-shot output and continuous output modes TOU0_0 Reload Register (TOU00RLW) <Address: H'0080 0794> TOU0_1 Reload Register (TOU01RLW) <Address: H'0080 079C> TOU0_2 Reload Register (TOU02RLW) <Address: H'0080 07A4> TOU0_3 Reload Register (TOU03RLW) <Address: H'0080 07AC> TOU0_4 Reload Register (TOU04RLW) <Address: H'0080 07B4> TOU0_5 Reload Register (TOU05RLW) <Address: H'0080 07BC> TOU0_6 Reload Register (TOU06RLW) <Address: H'0080 07C4> TOU0_7 Reload Register (TOU07RLW) <Address: H'0080 07CC> TOU1_0 Reload Register (TOU10RLW) <Address: H'0080 0B94> TOU1_1 Reload Register (TOU11RLW) <Address: H'0080 0B9C> TOU1_2 Reload Register (TOU12RLW) <Address: H'0080 0BA4> TOU1_3 Reload Register (TOU13RLW) <Address: H'0080 0BAC> TOU1_4 Reload Register (TOU14RLW) <Address: H'0080 0BB4> TOU1_5 Reload Register (TOU15RLW) <Address: H'0080 0BBC> TOU1_6 Reload Register (TOU16RLW) <Address: H'0080 0BC4> TOU1_7 Reload Register (TOU17RLW) <Address: H'0080 0BCC> TOU2_0 Reload Register (TOU20RLW) <Address: H'0080 0C94> TOU2_1 Reload Register (TOU21RLW) <Address: H'0080 0C9C> TOU2_2 Reload Register (TOU22RLW) <Address: H'0080 0CA4> TOU2_3 Reload Register (TOU23RLW) <Address: H'0080 0CAC> TOU2_4 Reload Register (TOU24RLW) <Address: H'0080 0CB4> TOU2_5 Reload Register (TOU25RLW) <Address: H'0080 0CBC> TOU2_6 Reload Register (TOU26RLW) <Address: H'0080 0CC4> TOU2_7 Reload Register (TOU27RLW) <Address: H'0080 0CCC> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU00 RLW – ––TOU17RLW, TOU20RLW –TOU27RLW b16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b31 <After reset: Undefined> b Bit Name Function R W 0–7 No function assigned. Fix to "0". 00 8–31 TOU00RLW –TOU07RLW, 24-bit reload register value R W TOU10RLW –TOU17RLW, TOU20RLW –TOU27RLW Note:  The 16 low-order bits must always be accessed in halfwords or more.

32180 Group User’s Manual (Rev.1.0) During single-shot output, delayed single-shot output and continuous output modes, TOU operates as a 24-bit timer. The value set in the 24 low-order bits of the reload register is loaded into the counter. Bits 8–15 and bits 16–31 are the 8 high-order and the 16 low-order bits of the counter, respectively. Bits 0–7 are ignored. The content of the reload register is loaded into the counter in the following cases:  When the counter is enabled in single-shot output mode  When the counter has underflowed in delayed single-shot output or continuous output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. During PWM output and single-shot PWM output modes, the TOU reload register operates as 16-bit reload 0 and reload 1 registers. For details, see Section 10.8.6, Paragraph (2), “TOU reload registers during PWM output and single-shot PWM output modes.”

32180 Group User’s Manual (Rev.1.0) (2) TOU reload registers during PWM output and single-shot PWM output modes TOU0_0 Reload 0 Register (TOU00RL0) <Address: H'0080 0796> TOU0_1 Reload 0 Register (TOU01RL0) <Address: H'0080 079E> TOU0_2 Reload 0 Register (TOU02RL0) <Address: H'0080 07A6> TOU0_3 Reload 0 Register (TOU03RL0) <Address: H'0080 07AE> TOU0_4 Reload 0 Register (TOU04RL0) <Address: H'0080 07B6> TOU0_5 Reload 0 Register (TOU05RL0) <Address: H'0080 07BE> TOU0_6 Reload 0 Register (TOU06RL0) <Address: H'0080 07C6> TOU0_7 Reload 0 Register (TOU07RL0) <Address: H'0080 07CE> TOU1_0 Reload 0 Register (TOU10RL0) <Address: H'0080 0B96> TOU1_1 Reload 0 Register (TOU11RL0) <Address: H'0080 0B9E> TOU1_2 Reload 0 Register (TOU12RL0) <Address: H'0080 0BA6> TOU1_3 Reload 0 Register (TOU13RL0) <Address: H'0080 0BAE> TOU1_4 Reload 0 Register (TOU14RL0) <Address: H'0080 0BB6> TOU1_5 Reload 0 Register (TOU15RL0) <Address: H'0080 0BBE> TOU1_6 Reload 0 Register (TOU16RL0) <Address: H'0080 0BC6> TOU1_7 Reload 0 Register (TOU17RL0) <Address: H'0080 0BCE> TOU2_0 Reload 0 Register (TOU20RL0) <Address: H'0080 0C96> TOU2_1 Reload 0 Register (TOU21RL0) <Address: H'0080 0C9E> TOU2_2 Reload 0 Register (TOU22RL0) <Address: H'0080 0CA6> TOU2_3 Reload 0 Register (TOU23RL0) <Address: H'0080 0CAE> TOU2_4 Reload 0 Register (TOU24RL0) <Address: H'0080 0CB6> TOU2_5 Reload 0 Register (TOU25RL0) <Address: H'0080 0CBE> TOU2_6 Reload 0 Register (TOU26RL0) <Address: H'0080 0CC6> TOU2_7 Reload 0 Register (TOU27RL0) <Address: H'0080 0CCE> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU00RL0 –TOU07RL0, TOU10RL0 –TOU17RRL0, TOU20RL0 –TOU27RL0 <After reset: Undefined> b Bit Name Function R W 0–15 TOU00RL0 –TOU07RL0, 16-bit reload register value R W TOU10RL0 –TOU17RL0, TOU20RL0 –TOU27RL0 Note:  This register must always be accessed in halfwords. During PWM output and single-shot PWM output modes, TOU operates as a 16-bit timer. Use the reload 0 register to set the 16-bit value to be loaded into the counter when it is enabled. The content of the reload 0 register is loaded into the counter in the following cases:  When the counter is enabled  When the count value set in the reload 1 register has underflowed in PWM output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. If the value ‘FFFF ’ is set in the reload register, F/F output will not be inverted, making it possible to produce a 0% or 100% duty-cycle PWM output. For details, see Section 10.8.17, “0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.” During single-shot output, delayed single-shot output and continuous output modes, the reload 0 and reload 1 registers are combined for use as a 24-bit reload register. For details, see Section 10.8.6, Paragraph (1), “TOU reload registers during single-shot output, delayed single-shot output and continuous output modes.”

32180 Group User’s Manual (Rev.1.0) TOU0_0 Reload 1 Register (TOU00RL1) <Address: H'0080 0794> TOU0_1 Reload 1 Register (TOU01RL1) <Address: H'0080 079C> TOU0_2 Reload 1 Register (TOU02RL1) <Address: H'0080 07A4> TOU0_3 Reload 1 Register (TOU03RL1) <Address: H'0080 07AC> TOU0_4 Reload 1 Register (TOU04RL1) <Address: H'0080 07B4> TOU0_5 Reload 1 Register (TOU05RL1) <Address: H'0080 07BC> TOU0_6 Reload 1 Register (TOU06RL1) <Address: H'0080 07C4> TOU0_7 Reload 1 Register (TOU07RL1) <Address: H'0080 07CC> TOU1_0 Reload 1 Register (TOU10RL1) <Address: H'0080 0B94> TOU1_1 Reload 1 Register (TOU11RL1) <Address: H'0080 0B9C> TOU1_2 Reload 1 Register (TOU12RL1) <Address: H'0080 0BA4> TOU1_3 Reload 1 Register (TOU13RL1) <Address: H'0080 0BAC> TOU1_4 Reload 1 Register (TOU14RL1) <Address: H'0080 0BB4> TOU1_5 Reload 1 Register (TOU15RL1) <Address: H'0080 0BBC> TOU1_6 Reload 1 Register (TOU16RL1) <Address: H'0080 0BC4> TOU1_7 Reload 1 Register (TOU17RL1) <Address: H'0080 0BCC> TOU2_0 Reload 1 Register (TOU20RL1) <Address: H'0080 0C94> TOU2_1 Reload 1 Register (TOU21RL1) <Address: H'0080 0C9C> TOU2_2 Reload 1 Register (TOU22RL1) <Address: H'0080 0CA4> TOU2_3 Reload 1 Register (TOU23RL1) <Address: H'0080 0CAC> TOU2_4 Reload 1 Register (TOU24RL1) <Address: H'0080 0CB4> TOU2_5 Reload 1 Register (TOU25RL1) <Address: H'0080 0CBC> TOU2_6 Reload 1 Register (TOU26RL1) <Address: H'0080 0CC4> TOU2_7 Reload 1 Register (TOU27RL1) <Address: H'0080 0CCC> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOU00RL1 –TOU07RL1, TOU10RL1 –TOU17RL1, TOU20RL1 –TOU27RL1 <After reset: Undefined> b Bit Name Function R W 0–15 TOU00RL1 –TOU07RL1, 16-bit reload register value R W TOU10RL1 –TOU17RL1, TOU20RL1 –TOU27RL1 Note:  This register must always be accessed in halfwords. During PWM output and single-shot PWM output modes, TOU operates as a 16-bit timer. Use the reload 1 register to set the 16-bit value to be loaded into the counter when the count value set in the reload 1 register has underflowed. The content of the reload 1 register is loaded into the counter in the following cases:  When the count value set in the reload 0 register has underflowed in PWM output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. If the value ‘FFFF ’ is set in the reload register, F/F output will not be inverted, making it possible to produce a 0% or 100% duty-cycle PWM output. For details, see Section 10.8.17, “0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.” During single-shot output, delayed single-shot output and continuous output modes, the reload 0 and reload 1 registers are combined for use as a 24-bit reload register. For details, see Section 10.8.6, Paragraph (1), “TOU reload registers during single-shot output, delayed single-shot output and continuous output modes.”

32180 Group User’s Manual (Rev.1.0)

10.8.7 TOU Enable Protect Registers

TOU0 Enable Protect Register (TOU0PRO) <Address: H'0080 07DD> TOU1 Enable Protect Register (TOU1PRO) <Address: H'0080 0BDD> TOU2 Enable Protect Register (TOU2PRO) <Address: H'0080 0CDD> 9 1 01 11 21 31 4 b 1 5b8 TOUn 0PRO TOUn 1PRO TOUn 2PRO TOUn 3PRO TOUn 4PRO TOUn 5PRO TOUn 6PRO TOUn 7PRO 00000000 <After reset: H’00> b Bit Name Function R W

8 TOUn0PRO 0: Enable rewrite R W

TOUn_0 enable protect bit 1: Disable rewrite

9 TOUn1PRO

TOUn_1 enable protect bit

10 TOUn2PRO

TOUn_2 enable protect bit

11 TOUn3PRO

TOUn_3 enable protect bit

12 TOUn4PRO

TOUn_4 enable protect bit

13 TOUn5PRO

TOUn_5 enable protect bit

14 TOUn6PRO

TOUn_6 enable protect bit

15 TOUn7PRO

TOUn_7 enable protect bit The TOU enable protect registers control rewriting of the TOU count enable bit described in Section 10.8.8, “TOU Count Enable Registers,” by enabling or disabling rewrite.

32180 Group User’s Manual (Rev.1.0)

10.8.8 TOU Count Enable Registers

TOU0 Count Enable Register (TOU0CEN) <Address: H ’0080 07DF> TOU1 Count Enable Register (TOU1CEN) <Address: H'0080 0BDF> TOU2 Count Enable Register (TOU2CEN) <Address: H'0080 0CDF> 9 1 01 11 21 31 4 b 1 5b8 TOUn 0CEN TOUn 1CEN TOUn 2CEN TOUn 3CEN TOUn 4CEN TOUn 5CEN TOUn 6CEN TOUn 7CEN 00000000 <After reset: H’00> b Bit Name Function R W

8 TOUn0CEN 0: Stop count R W

TOUn_0 count enable bit 1: Enable count

9 TOUn1CEN

TOUn_1 count enable bit

10 TOUn2CEN

TOUn_2 count enable bit

11 TOUn3CEN

TOUn_3 count enable bit

12 TOUn4CEN

TOUn_4 count enable bit

13 TOUn5CEN

TOUn_5 count enable bit

14 TOUn6CEN

TOUn_6 count enable bit

15 TOUn7CEN

TOUn_7 count enable bit The TOU count enable registers control operation of the TOU counters. To enable any TOU counter in software, enable its corresponding enable protect bit for rewrite and set the count enable bit by writing "1". To stop any TOU counter, enable its corresponding enable protect bit for rewrite and reset the count enable bit by writing "0". In single-shot output, single-shot PWM output or delayed single-shot output mode, when the counter stops due to occurrence of an underflow, the count enable bit is automatically reset to "0". Therefore, the TOU count enable register when accessed for read serves as a status register indicating whether the counter is operating or idle.

32180 Group User’s Manual (Rev.1.0) Figure 10.8.6 Configuration of the TOU2 Enable Circuit Figure 10.8.4 Configuration of the TOU0 Enable Circuit WR bn TOU0m enable protect (TOU0mPRO) WR TOU0m enable TOU0 enable source selection (TOU0ENS) (TOU0mCEN) TOU0m enable control F/F F/F Event enable disable TID0_udf/ovf TOU0_7udf Output event bus 0 TIN25S EN-ON WR bn (TOU1mPRO) WR EN-ON (TOU1mCEN) F/F F/F TID1_udf/ovf TOU1_7udf TIN27STID0_udf/ovf TOU0_7udf TIN25S TOU1m enable protect TOU0 enable source selection (TOU0ENS) Event enable disable Output event bus 0 Event enable disable TOU1 enable source selection (TOU1ENS) TOU1m enable TOU1m enable control Figure 10.8.5 Configuration of the TOU1 Enable Circuit WR bn (TOU2mPRO) WR EN-ON (TOU2mCEN) F/F F/F TID2_udf/ovf TOU2_7udf TIN29STID0_udf/ovf TOU0_7udf TIN25S TOU2m enable protect TOU0 enable source selection (TOU0ENS) Event enable disable Output event bus 0 Event enable disable TOU2 enable source selection (TOU2ENS) TOU2m enable TOU2m enable control

32180 Group User’s Manual (Rev.1.0)

10.8.9 PWMOFF Input Processing Control Registers

PWMOFF0 Input Processing Control Register (PWMOFF0CR) <Address: H'0080 07E0> 123456 b 7b0 PWMOFF0SPWM OFF0SP 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00

4 PWMOFF0SP 0W

PWMOFF0S write control bit 5–7 PWMOFF0S 000: Input has no effect R W PWMOFF0 input processing control bit 001: Rising edge 010: Falling edge 011: Both edges 10X: Low level 11X: High level PWMOFF1 Input Processing Control Register (PWMOFF1CR) <Address: H'0080 0BE0> 123456 b 7b0 PWMOFF1SPWM OFF1SP 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00

4 PWMOFF1SP 0W

PWMOFF1S write control bit 5–7 PWMOFF1S 000: Input has no effect R W PWMOFF1 input processing control bit 001: Rising edge 010: Falling edge 011: Both edges 10X: Low level 11X: High level

32180 Group User’s Manual (Rev.1.0) PWMOFF2 Input Processing Control Register (PWMOFF2CR) <Address: H'0080 0CE0> 123456 b 7b0 PWMOFF2SPWM OFF2SP 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00

4 PWMOFF2SP 0W

PWMOFF2S write control bit 5–7 PWMOFF2S 000: Input has no effect R W PWMOFF2 input processing control bit 001: Rising edge 010: Falling edge 011: Both edges 10X: Low level 11X: High level The PWMOFF input processing control registers are used to set the active edge or level entered for PWM output disable control from an external pin. For details about the PWM output disable function, see Section 10.8.18, “PWM Output Disable Function.” To set the PWMOFF input processing control bits, follow the procedure described below. 1. Write data ‘1’ to the PWMOFFnS write control bit (PWMOFFnSP). 2. After 1 above, write data ‘0’ to the PWMOFFnS write control bit (PWMOFFnSP) and the set value to the PWMOFF input processing control bits (PWMOFFnS). Note:  If a write cycle to any other area occurs between 1 and 2, what has successively been set above has no effect and the written value is not reflected. Therefore, disable interrupts and DMA transfers before setting the PWMOFF control bits. Be aware that a pair of two consecutive writes comprise a write operation.

32180 Group User’s Manual (Rev.1.0) If a write cycle to any other area occurs during this interval, the value that was set in the PWMOFFnS bits is not reflected. PWMOFFnSP "1" PWMOFFnSP "0" PWMOFFnS Set value  Example of correct settings  Cases where settings have no effect Because a write cycle to other area exists, the set value is not reflected. PWMOFFnSP "1" Write to other area PWMOFFnSP "0" PWMOFFnS Set value (1) (2) PWMOFFnSP "1" PWMOFFnSP "1" PWMOFFnS "0" PWMOFFnS Set value Because these two consecutive writes comprise a pair, the next set value is not reflected. Figure 10.8.7 PWMOFFnS Setting Procedure

32180 Group User’s Manual (Rev.1.0)

10.8.10 PWM Output Control Registers

PWM Output 0 Disable Control Register (PO0DISCR) <Address: H ’0080 0780> 123456 b 7b0 PO0DISPO0DISP 000 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00

6 PO0DISP – 0W

7 PO0DIS 0: Enable output R W

P160/TO21 –P165/TO26 output disable select bit 1: Disable output PWM Output 1 Disable Control Register (PO1DISCR) <Address: H'0080 0782> 123456 b 7b0 PO1DISPO1DISP 000 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00

6 PO1DISP – 0W

7 PO1DIS 0: Enable output R W

P180/TO29 –P185/TO34 output disable select bit 1: Disable output

32180 Group User’s Manual (Rev.1.0) PWM Output 2 Disable Control Register (PO2DISCR) <Address: H'0080 0784> 123456 b 7b0 PO2DISPO2DISP 000 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00

6 PO2DISP – 0W

7 PO2DIS 0: Enable output R W

P210/TO37 –P215/TO42 output disable select bit 1: Disable output These registers control output from the respective corresponding pins by enabling or disabling it. These pins can be used to control three-phase PWM output using the TOU timer. Three-phase PWM output can be forcibly disabled (placed in the high-impedance state) by controlling this reg- ister. For details, see Section 10.8.18, “PWM Output Disable Function.” Also, if this register is accessed for read, it serves as a status register indicating whether PWM output is disabled. To set this register, follow the procedure described below. 1. Write data ‘1’ to the POnDIS write control bit (POnDISP). 2. After 1 above, write data ‘0’ to the POnDIS write control bit (POnDISP) and data ‘0’ or ‘1’ to the output disable select bit (POnDIS). Note:  If a write cycle to any other area occurs between 1 and 2, what has successively been set above has no effect and the written value is not reflected. Therefore, disable interrupts and DMA transfers before setting the POnDIS bits. Be aware that a pair of two consecutive writes comprise a write operation.

32180 Group User’s Manual (Rev.1.0) Figure 10.8.8 POnDIS Setting Procedure If a write cycle to any other area occurs during this interval, the value that was set in the POnDIS bit is not reflected. POnDISP "1" POnDISP "0" POnDIS Set value  Example of correct settings  Cases where settings have no effect Because a write cycle to other area exists, the set value is not reflected. POnDISP "1" Write to other area POnDISP "0" POnDIS Set value (1) (2) POnDISP "1" POnDISP "1" POnDISP "0" POnDIS Set value Because these two consecutive writes comprise a pair, the next set value is not reflected.

32180 Group User’s Manual (Rev.1.0)

10.8.11 PWM Output Disable Level Control Registers

PWM Output 0 Disable Level Control Register (PO0LVCR) <Address: H'0080 0781> 9 1 01 11 21 31 4 b 1 5b8 PO0LVENPO0LVSEL 000 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0". 00

14 PO0LVSEL 0: Select low output disable level R W

P160/TO21 –P165/TO26 output disable level select bit 1: Select high output disable level

15 PO0LVEN 0: Disable selected output disable level R W

Output disable level enable/disable select bit 1: Enable selected output disable level PWM Output 1 Disable Level Control Register (PO1LVCR) <Address: H'0080 0783> 9 1 01 11 21 31 4 b 1 5b8 PO1LVENPO1LVSEL 000 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0". 00

14 PO1LVSEL 0: Select low output disable level R W

P180/TO29 –P185/TO34 output disable level select bit 1: Select high output disable level

15 PO1LVEN 0: Disable selected output disable level R W

Output disable level enable/disable select bit 1: Enable selected output disable level PWM Output 2 Disable Level Control Register (PO2LVCR) <Address: H'0080 0785> 9 1 01 11 21 31 4 b 1 5b8 PO2LVENPO2LVSEL 000 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0". 00

14 PO2LVSEL 0: Select low output disable level R W

P210/TO37 –P215/TO42 output disable level select bit 1: Select high output disable level

15 PO2LVEN 0: Disable selected output disable level R W

Output disable level enable/disable select bit 1: Enable selected output disable level The output disable level select function allows output from a port to be forcibly disabled (placed in the high- impedance state) depending on the output state of that port. This function may be used to determine whether three-phase PWM output signals are simultaneously on. Furthermore, this function may be used for double- verification of ports because it works depending on the output state of ports.

32180 Group User’s Manual (Rev.1.0) (1) POnLVSEL (Output Disable Level Select) bit (Bit 14) This bit specifies the level (high or low) at which port output is to be disabled. Set this bit to "0" to disable port output when its level is low, or "1" to disable port output when its level is high. The following shows the conditions under which port output is turned off depending on the port’s output state. 1) PO0LVSEL = 0 If any one of the following conditions hold true, P160/TO21–P165/TO26 outputs (TOU0_0–TOU0_5 output pins) are disabled.  P160/TO21 (TOU0_0 output pin) output and P161/TO22 (TOU0_1 output pin) output both are at the low level  P162/TO23 (TOU0_2 output pin) output and P163/TO24 (TOU0_3 output pin) output both are at the low level  P164/TO25 (TOU0_4 output pin) output and P165/TO26 (TOU0_5 output pin) output both are at the low level 2) PO0LVSEL = 1 If any one of the following conditions hold true, P160/TO21–P165/TO26 outputs (TOU0_0–TOU0_5 output pins) are disabled.  P160/TO21 (TOU0_0 output pin) output and P161/TO22 (TOU0_1 output pin) output both are at the high level  P162/TO23 (TOU0_2 output pin) output and P163/TO24 (TOU0_3 output pin) output both are at the high level  P164/TO25 (TOU0_4 output pin) output and P165/TO26 (TOU0_5 output pin) output both are at the high level 3) PO1LVSEL = 0 If any one of the following conditions hold true, P180/TO29–P185/TO34 outputs (TOU1_0–TOU1_5 output pins) are disabled.  P180/TO29 (TOU1_0 output pin) output and P181/TO30 (TOU1_1 output pin) output both are at the low level  P182/TO31 (TOU1_2 output pin) output and P183/TO32 (TOU1_3 output pin) output both are at the low level  P184/TO33 (TOU1_4 output pin) output and P185/TO34 (TOU1_5 output pin) output both are at the low level 4) PO1LVSEL = 1 If any one of the following conditions hold true, P180/TO29–P185/TO34 outputs (TOU1_0–TOU1_5 output pins) are disabled.  P180/TO29 (TOU1_0 output pin) output and P181/TO30 (TOU1_1 output pin) output both are at the high level  P182/TO31 (TOU1_2 output pin) output and P183/TO32 (TOU1_3 output pin) output both are at the high level  P184/TO33 (TOU1_4 output pin) output and P185/TO34 (TOU1_5 output pin) output both are at the high level 5) PO2LVSEL = 0 If any one of the following conditions hold true, P210/TO37–P215/TO42 outputs (TOU2_0–TOU2_5 output pins) are disabled.  P210/TO37 (TOU2_0 output pin) output and P211/TO38 (TOU2_1 output pin) output both are at the low level  P212/TO39 (TOU2_2 output pin) output and P213/TO40 (TOU2_3 output pin) output both are at the low level  P214/TO41 (TOU2_4 output pin) output and P215/TO42 (TOU2_5 output pin) output both are at the low level 6) PO2LVSEL = 1 If any one of the following conditions hold true, P210/TO37–P215/TO42 outputs (TOU2_0–TOU2_5 output pins) are disabled.  P210/TO37 (TOU2_0 output pin) output and P211/TO38 (TOU2_1 output pin) output both are at the high level  P212/TO39 (TOU2_2 output pin) output and P213/TO40 (TOU2_3 output pin) output both are at the high level  P214/TO41 (TOU2_4 output pin) output and P215/TO42 (TOU2_5 output pin) output both are at the high level (2) POnLVEN (Output Disable Level Enable/Disable Select) bit (Bit 15) This bit enables or disables the output disable level that was selected with the POnLVSEL bit. Setting this bit to "1" enables the output disable level selected with the POnLVSEL bit; setting this bit to "0" disables the output disable level selected with the POnLVSEL bit.

32180 Group User’s Manual (Rev.1.0)

10.8.12 Operation in TOU PWM Output Mode

(1) Outline of TOU PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts counting down synchronously with the count clock. The first time the counter underflows, it is loaded with the reload 1 register value and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The (reload 0 register set value + 1) and (reload 1 register set value + 1) respectively are effective as count values. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output level changes from "low" to "high" or vice versa) when the counter starts counting and each time it underflows. An interrupt request can be gener- ated when the counter underflows every other time (second time, fourth time and so on) after being enabled. If the value ‘FFFF ’ is set in the reload register, F/F output will not be inverted although an interrupt request is generated upon underflow, making it possible to produce a 0% or 100% duty-cycle PWM output. Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. However, startup requests to other timers are not delayed. For details, see Section 10.8.17, “0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.” Note that TOU’s PWM output mode does not have the count correction function.

32180 Group User’s Manual (Rev.1.0) Figure 10.8.9 Typical Operation in PWM Output Mode Count clock Counter H'FFFF H'0000 Enabled (by writing to the enable bit or by external input) F/F output Underflow (first time) Interrupt request due to underflow Enable bit Note:  This diagram does not show detailed timing information. Reload 0 register H'A000 Underflow (second time) H'(C000-1) Data inverted by underflow Data inverted by enable H'(A000-1) Data inverted by underflow Reload 1 register H'C000 H'A000 PWM output period H'C000 H'A000 Count down from the reload 0 register set value One count clock equivalent delay Undefined value H'(A000-1) One count clock equivalent delay One count clock equivalent delay Count down from the reload 1 register set value Count down from the reload 0 register set value

32180 Group User’s Manual (Rev.1.0) (2) Reload register updates in TOU PWM output mode In PWM output mode, when the timer remains idle, the reload 0 and reload 1 registers are updated at the same time data are written to the respective registers. But when the timer is operating, the reload 1 register is updated by updating the reload 0 register. However, if the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have been written to the respective registers. Internal bus TOUnRL1 Reload 1 Reload 1 WR Reload 0 WR Buffer 16-bit counterPrescaler output F/F TO TOUnRL0 Reload 0 PWM mode control Figure 10.8.10 PWM Circuit Diagram To rewrite the reload 0 and reload 1 registers while the timer is operating, rewrite the reload 1 register first and then the reload 0 register. That way, the reload 0 and reload 1 registers both are updated synchronously with PWM period, from which the timer starts operating. This operation can normally be performed collec- tively by accessing 32-bit addresses beginning with the reload 1 register address wordwise. (Data are auto- matically written to the reload 1 and then the reload 0 registers in succession.) If the reload 0 and reload 1 registers are updated in the reverse order beginning with reload 0, only the reload 0 register is updated. Note also that if the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have been written to the respective registers, and not the reload values being actually used. When altering PWM period by rewriting the reload registers, if the PWM period terminates before the CPU finishes writing to reload 0, the PWM period is not altered in the current session and the data written to the register is reflected in the next period. (3) Precautions on using TOU PWM output mode The following describes precautions to be observed when using TOU PWM output mode.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.  Because the timer operates synchronously with the count clock, a count clock-dependent delay is in- cluded before F/F output is inverted after the timer is enabled. Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. How- ever, startup requests to other timers are not delayed. For details, see Section 10.8.17, “0% or 100% Duty- Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.”

32180 Group User’s Manual (Rev.1.0) Figure 10.8.11 Reload 0 and Reload 1 Register Updates in PWM Output Mode (a) When reload register updates take effect in the current period (reflected in the next period) Count clock Reload 0 register Reload 1 register H'0001 H'FFFF H'1000 H'7FFF H'2000 H'8000 H'9000 Counter Interrupt due to underflow Timing at which reload 0 and reload 1 registers are updated New PWM output period Operation by new reload value written Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (Reload 1 data latched) H'1000 H'2000 H'8000 H'9000 Enlarged view New PWM output periodOld PWM output period F/F output H'7FFEH'0000 PWM period latched Reload 1 buffer H'2000 H'9000 H'0001 H'FFFF H'1000 H'0FFF H'2000 H'8000 H'9000 (b) When reload register updates take effect in the next period (reflected one period later) Old PWM output period Operation by old reload value H'1000 H'2000 H'8000 H'9000 Old PWM output period H'0FFEH'0000 H'2000 H'9000 Note:  This diagram does not show detailed timing information. Count clock Reload 0 register Reload 1 register Counter Interrupt due to underflow Timing at which reload 0 and reload 1 registers are updated Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (Reload 1 data latched) Enlarged view Old PWM output period F/F output PWM period latched Reload 1 buffer

32180 Group User’s Manual (Rev.1.0) Figure 10.8.12 Reload 0 and Reload 1 Register Updates in PWM Output Mode (For 0% or 100% Duty-Cycle Wave Output) H'0001 H'FFFF H'1000 FFFF H'2000 FFFF H'9000 H'1000 H'2000 FFFF H'9000 8FFFH'0000 H'2000 H'9000 H'0001 H'FFFF H'1000 H'0FFF H'2000 FFFF H'9000 H'1000 H'2000 FFFF H'9000 H'0FFEH'0000 H'2000 H'9000 (a) When reload register updates take effect in the current period (reflected in the next period) Count clock Reload 0 register Reload 1 register Counter Interrupt due to underflow Timing at which reload 0 and reload 1 registers are updated New PWM output period Operation by new reload value written Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (Reload 1 data latched) Enlarged view New PWM output periodOld PWM output period F/F output PWM period latched Reload 1 buffer (b) When reload register updates take effect in the next period (reflected one period later) Old PWM output period Operation by old reload value Old PWM output period Note:  This diagram does not show detailed timing information. Count clock Reload 0 register Reload 1 register Counter Interrupt due to underflow Timing at which reload 0 and reload 1 registers are updated Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (Reload 1 data latched) Enlarged view Old PWM output period F/F output PWM period latched Reload 1 buffer

32180 Group User’s Manual (Rev.1.0)

10.8.13 Operation in TOU Single-shot PWM Output Mode (without Correction Function)

(1) Outline of TOU single-shot PWM output mode In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle only once. When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts counting down synchronously with the count clock. The first time the counter underflows, it is loaded with the reload 1 register value and continues counting. The counter stops when it underflows next time. The (reload 0 register set value + 1) and (reload 1 register set value + 1) respectively are effective as count values. The timer can be stopped in software, in which case it stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in single-shot PWM output mode is inverted (F/F output level changes from low to high or vice versa) each time the counter underflows. (Unlike in PWM output mode, the F/F output is not inverted when the counter is enabled.) An interrupt request and DMA transfer request can be generated when the counter underflows second time after being enabled. If the value ‘FFFF ’ is set in the reload register, F/F output will not be inverted although an interrupt request is generated upon underflow, making it possible to produce a 0% or 100% duty-cycle PWM output. Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. However, startup requests to other timers are not delayed. For details, see Section 10.8.17, “0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.” Note that TOU’s single-shot PWM output mode does not have the count correction function. (2) Precautions on using TOU single-shot PWM output mode The following describes precautions to be observed when using TOU single-shot PWM output mode.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge. Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. How- ever, startup requests to other timers are not delayed. For details, see Section 10.8.17, “0% or 100% Duty- Cycle Wave Output during PWM Output and Single-shot PWM Output Modes.”

32180 Group User’s Manual (Rev.1.0) Figure 10.8.13 Typical Operation in TOU Single-shot PWM Output Mode (without Correction Function) Count clock H'FFFF H'0000 Enabled (by writing to the enable bit or by external input) F/F output Underflow (first time) Interrupt request due to underflow Enable bit Note:  This diagram does not show detailed timing information. Reload 0 register H'A000 H'A000 Underflow (second time) H'F000 H'EFFF Data inverted by underflow Counter Reload 1 register H'F000 Count down from the reload 0 register set value PWM output period One count clock equivalent delay One count clock equivalent delay Undefined value H'(A000-1) Count down from the reload 1 register set value Data inverted by underflow

32180 Group User’s Manual (Rev.1.0)

10.8.14 Operation in TOU Delayed Single-shot Output Mode (without Correction Function)

(1) Outline of TOU delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) after a finite time equal to (counter set value + 1) only once and then stops. When the timer is enabled after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. The first time the counter underflows, it is loaded with the reload register value and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from low to high or vice versa) when the counter underflows first time and next, generating a single-shot pulse wave- form in width of (reload register set value + 1) after a finite time equal to (first set value of counter + 1) only once. An interrupt request can be generated when the counter underflows first time and next. The (counter set value + 1) and (reload register set value + 1) respectively are effective as count values. (For counting operation, see also Section 10.3.10, “Operation of TOP Delayed Single-shot Output Mode.”) (2) Precautions on using TOU delayed single-shot output mode The following describes precautions to be observed when using TOU delayed single-shot output mode.  If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.  If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  To read the counter on-the-fly, make sure the read timing does not coincide with an underflow of the 16 low-order bits (8 high-order bits decremented). When reading the counter on-the-fly, take the appropriate measure to ensure that the read value is correct by, for example, reading the counter twice in succession.  If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter value temporarily reads as H’FF FFFF but immediately changes to (reload value – 1) at the next clock edge.  Because the timer operates synchronously with the count clock, a count clock-dependent delay is in- cluded before F/F output is inverted after the timer is enabled.

32180 Group User’s Manual (Rev.1.0) Figure 10.8.14 Typical Operation in TOU Delayed Single-shot Output Mode (without Correction Function) H'FF FFFF H'00 0000 H'10 F000 H'08 A000 H'10 F000 H'10 EFFF Data inverted by underflow Data inverted by underflow H'(08 A000-1) Count clock Enabled (by writing to the enable bit or by external input) F/F output Underflow (first time) Interrupt request due to underflow Enable bit Note:  This diagram does not show detailed timing information. Underflow (second time) Counter Reload 1 register Count down from the reload register set value Undefined value Count down from the counter set value

32180 Group User’s Manual (Rev.1.0)

10.8.15 Operation in TOU Single-shot Output Mode (without Correction Function)

(1) Outline of TOU single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once and then stops. When the timer is enabled after setting the reload register, the counter is loaded with the content of the reload register and starts counting synchronously with the count clock. The counter counts down and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload regis- ter set value + 1) only once. An interrupt request can be generated when the counter underflows. The count value is (reload register set value + 1). (For counting operation, see also Section 10.3.9, “Opera- tion of TOP Single-shot Output Mode.”) (2) Precautions on using TOU single-shot output mode The following describes precautions to be observed when using TOU single-shot output mode.  If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.  If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  To read the counter on-the-fly, make sure the read timing does not coincide with an underflow of the 16 low-order bits (8 high-order bits decremented). When reading the counter on-the-fly, take the appropriate measure to ensure that the read value is correct by, for example, reading the counter twice in succession.  Because the timer operates synchronously with the count clock, a count clock-dependent delay is in- cluded before F/F output is inverted after the timer is enabled.

32180 Group User’s Manual (Rev.1.0) Figure 10.8.15 Typical Operation in TOU Single-shot Output Mode (without Correction Function) Count clock H'FF FFFF H'00 0000 Enabled (by writing to the enable bit or by external input) F/F output Disable (due to underflow) Interrupt request due to underflow Enable bit Count down from the reload 0 register set value Note:  This diagram does not show detailed timing information. Reload registerH'55 AA00 H'55 AA00 Counter Data inverted by enable Data inverted by underflow H'(55 AA00-1) Undefined value

32180 Group User’s Manual (Rev.1.0)

10.8.16 Operation in TOU Continuous Output Mode (without Correction Function)

(1) Outline of TOU continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload register set value + 1). When the timer is enabled after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be loaded with the content of the reload register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output level changes from low to high or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each time the counter underflows. The (counter set value + 1) and (reload register set value + 1) are effective as count values. (For counting operation, see also Section 10.3.11, “Operation of TOP Continuous Output Mode.”) (2) Precautions on using TOU continuous output mode The following describes precautions to be observed when using TOU continuous output mode.  If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.  To read the counter on-the-fly, make sure the read timing does not coincide with an underflow of the 16 low-order bits (8 high-order bits decremented). When reading the counter on-the-fly, take the appropriate measure to ensure that the read value is correct by, for example, reading the counter twice in succession.  If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter value temporarily reads as H’FF FFFF but immediately changes to (reload value – 1) at the next clock edge.  Because the timer operates synchronously with the count clock, a count clock-dependent delay is in- cluded before F/F output is inverted after the timer is enabled.

32180 Group User’s Manual (Rev.1.0) Figure 10.8.16 Typical Operation in TOU Continuous Output Mode (without Correction Function) H'FF FFFF H'FF 0000 Underflow (first time) Count down from the counter set value H'0E 0000 H'0A 0000 Underflow (second time) H'0E 0000 Count down from the reload 0 register set value H'00 FFFF Count down from the reload 0 register set value H'0D FFFF Data inverted by enable Data inverted by underflow Data inverted by underflow H'(0A 0000-1) Count clock Enabled (by writing to the enable bit or by external input) F/F output Interrupt request due to underflow Enable bit Note:  This diagram does not show detailed timing information. Reload register Counter Undefined value

32180 Group User’s Manual (Rev.1.0) 10.8.17 0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes During PWM output or single-shot PWM output mode, if the value ‘FFFF ’ is written to the reload 0 or reload 1 register, F/F output will not be inverted, making it possible to produce a 0% or 100% duty-cycle PWM output. Because determination is made to see if the reload value is ‘FFFF ’ during PWM output or single-shot PWM output mode, following precautions must be observed. (1) Because the counter counts one even when detecting 0% or 100% duty-cycle, one of the two reload registers must have set in it one less than the intended value in order for a constant-cycle waveform to be produced. Example: If the desired output cycle is 10 counts Cycle ratio 50% : 50% 80% : 20% 90% : 10% 100% : 0% Count ratio 5 : 5 8 : 2 9 : 1 10 : 0 ƒRegister set values 0004 : 0004 0007 : 0001 0008 : 0000 0009 : FFFF Because the counter counts n + 1, the values actually set in the respective registers must be one less than the intended value. (2) Because setting the value ‘FFFF ’ in the reload register produces a 0% or 100% duty-cycle, it is impossible to count the exact ‘FFFF.’ (3) Setting the value ‘FFFF ’ in both reload 0 and reload 1 registers is inhibited. (4) Writing the value ‘FFFF ’ to the counter while in operation is inhibited. (5) Even for a 0% or 100% duty-cycle, interrupt requests and startup registers to other timers are generated. (6) Because a 0% or 100% duty-cycle needs to be determined when reloading the counter, there is a one count clock equivalent delay before F/F is inverted and an interrupt or DMA transfer request is generated. However, startup requests to other timers are not delayed. 0008: FFFF The counter counts one without invert- ing F/F output after detecting ‘FFFF.’ For this reason, the value to be set in the register must be ‘0008’, and not ‘0009’.

32180 Group User’s Manual (Rev.1.0) Figure 10.8.17 Typical Operation in PWM Output Mode (Reload 0 Register: H’FFFF) Note 1: DMA transfer request also is generated with the same timing. Note:  This diagram does not show detailed timing information.  This diagram is shown with respect to the one-count-clock delayed output. Enabled (by writing to the enable bit or by external input) Count down from the reload 1 register set value Count down from the reload 1 register set value UnderflowSuperficial underflow H'FFFF H'0000 H'FFFF H'E000 H'(E000-1) H'(FFFF-1)H'(FFFF-1) H'(E000-1) H'E000 Data not invertedData not inverted Data not inverted Counter Because the reload 0 register = H'FFFF , a superficial underflow is generated, causing the counter to be loaded with the content of the reload 1 register Undefined value Enable bit Reload 0 register Reload 1 register F/F output Interrupt request due to underflow (Note 1) Timing at which startup requests to other timers are generated Count clock

32180 Group User’s Manual (Rev.1.0) Figure 10.8.18 Typical Operation in PWM Output Mode (Reload 1 Register: H’FFFF) Enabled (by writing to the enable bit or by external input) H'FFFF H'0000 H'E000 H'E000 H'(E000-1) H'(FFFF-1) H'(FFFF-1) H'(E000-1) H'FFFF Data inverted by enable Note 1: DMA transfer request also is generated with the same timing. Note:  This diagram does not show detailed timing information. Data not inverted Counter Undefined value Enable bit Reload 0 register Reload 1 register F/F output Interrupt request due to underflow (Note 1) Timing at which startup requests to other timers are generated Count clock Data not inverted Count down from the reload 0 register set value Underflow Superficial underflow Because the reload 1 register = H'FFFF , a superficial underflow is generated, causing the counter to be loaded with the content of the reload 0 register Count down from the reload 0 register set value

32180 Group User’s Manual (Rev.1.0) Figure 10.8.19 Typical Operation in Single-shot PWM Output Mode (Reload 0 Register: H’FFFF) H'FFFF H'0000 H'FFFF H'E000 H'E000 Enabled (by writing to the enable bit or by external input) Note 1: DMA transfer request also is generated with the same timing. Note:  This diagram does not show detailed timing information. Counter Undefined value Enable bit Reload 0 register Reload 1 register F/F output Interrupt request due to underflow (Note 1) Count clock Underflow Superficial underflow Data inverted by enable Timing at which startup requests to other timers are generated Because the reload 0 register = H'FFFF , a superficial underflow is generated, causing the counter to be loaded with the content of the reload 1 register Count down from the reload 1 register set value Data inverted by underflow

32180 Group User’s Manual (Rev.1.0) Figure 10.8.20 Typical Operation in Single-shot PWM Output Mode (Reload 1 Register: H’FFFF) H'FFFF H'0000 H'E000 H'E000 H'(FFFF-1) H'FFFF Because the reload 1 register = H'FFFF , a superficial underflow is generated Enabled (by writing to the enable bit or by external input) Note 1: DMA transfer request also is generated with the same timing. Note:  This diagram does not show detailed timing information. Counter Undefined value Enable bit Reload 0 register Reload 1 register F/F output Interrupt request due to underflow (Note 1) Timing at which startup requests to other timers are generated Count clock Count down from the reload 0 register set value Underflow Superficial underflow Data not inverted

32180 Group User’s Manual (Rev.1.0)

10.8.18 PWM Output Disable Function

The microcomputer has the function to forcibly disable outputs from the P160/TO21–P165/TO26, P180/TO29– P185/TO34 and P210/TO37 –P215/TO42 that respectively are the output pins for the TOU0_0–TOU0_5, TOU1_0 –TOU1_5 and TOU2_0 –TOU2_5 timers. This function may be used as a protective function when a fault condition such as short-circuiting is detected during three-phase PWM control. This function can be used PWM output disable function. F/F F/F F/F F/FF/F TIN16S PWMOFF0S RD P160/TO21 P161/TO22 P162/TO23 P163/TO24 P164/TO25 P165/TO26 P166/TO27 P167/TO28 P160 (internal) P160 (internal) P161 (internal) P162 (internal) P163 (internal) P164 (internal) P165 (internal) P166 (internal) P167 (internal) P161 (internal) P162 (internal) P163 (internal) P164 (internal) P165 (internal) IRQ10 TMS1(Cap3) SET WR Address PO0DISCR (WR) PO0LVSEL PO0LVEN F/F F/F F/F F/FF/F TIN17S PWMOFF1S RD P180/TO29 P181/TO30 P182/TO31 P183/TO32 P184/TO33 P185/TO34 P186/TO35 P187/TO36 P180 (internal) P180 (internal) P181 (internal) P182 (internal) P183 (internal) P184 (internal) P185 (internal) P186 (internal) P187 (internal) P181 (internal) P182 (internal) P183 (internal) P184 (internal) P185 (internal) IRQ10 TMS1 (Cap2) SET WR Address PO1DISCR(WR) PO1LVSEL PO1LVEN PO1DIS PO0DIS P130/TIN16/PWMOFF0 P131/TIN17/PWMOFF1 Figure 10.8.21 Circuit Configurations of the PWM Output Disable Function (1)

32180 Group User’s Manual (Rev.1.0) F/F F/F F/F F/FF/F TIN33S PWMOFF2S RD P210/TO37 P211/TO38 P212/TO39 P213/TO40 P214/TO41 P215/TO42 P216/TO43 P217/TO44 P210 (internal) P210 (internal) P211 (internal) P212 (internal) P213 (internal) P214 (internal) P215 (internal) P216 (internal) P217 (internal) P211 (internal) P212 (internal) P213 (internal) P214 (internal) P215 (internal) IRQ18 TML1 (Cap0) SET WR Address PO2DISCR (WR) PO2LVSEL PO2LVSEL PO2DIS P197/TIN33/PWMOFF2 Figure 10.8.22 Circuit Configurations of the PWM Output Disable Function (2) There are following three methods to disable PWM outputs. (1) Using the signal entered from an external pin (TIN16/PWMOFF0, TIN17/PWMOFF1 or TIN33/PWMOFF2) to disable PWM outputs The input signal on the external pin (TIN16/PWMOFF0) may be used to disable outputs from the ports P160/ TO21 –P165/TO26 that are provided for the PWM outputs of the TOU0_0–TOU0_5 timers. Similarly, the input signal on the external pin (TIN17/PWMOFF1) may be used to disable outputs from the ports P180/ TO29 –P185/TO34 that are provided for the PWM outputs of the TOU1_0–TOU1_5 timers. Also, the input signal on the external pin (TIN33/PWMOFF2) may be used to disable outputs from the ports P210/TO37– P215/TO42 that are provided for the PWM outputs of the TOU2_0–TOU2_5 timers. To disable PWM outputs using the input signal on the external pin (TIN16/PWMOFF0, TIN17/PWMOFF1 or TIN33/PWMOFF2), set up the PWMOFF Input Processing Control Register (PWMOFFnCR) as described below. [Setting up the PWMOFF Input Processing Control Register] When using TIN16/PWMOFF0 to disable PWM outputs 1. Write data ‘1’ to the PWMOFF0CR register PWMOFF0SP bit. 2. After 1 above, write data ‘0’ to the PWMOFF0SP bit and then data ‘000,’ ‘001,’ ‘010,’ ‘011,’ ‘10X’ or ‘11X’ to the PWMOFF0S bit in succession. Note:  If a write cycle to any other area occurs between 1 and 2, the value written to the PWMOFF0S bit has no effect.

32180 Group User’s Manual (Rev.1.0) When using TIN17/PWMOFF1 to disable PWM outputs 1. Write data ‘1’ to the PWMOFF1CR register PWMOFF1SP bit. 2. After 1 above, write data ‘0’ to the PWMOFF1SP bit and then data ‘000,’ ‘001,’ ‘010,’ ‘011,’ ‘10X’ or ‘11X’ to the PWMOFF1S bit in succession. Note:  If a write cycle to any other area occurs between 1 and 2, the value written to the PWMOFF1S bit has no effect. When using TIN33/PWMOFF2 to disable PWM outputs 1. Write data ‘1’ to the PWMOFF2CR register PWMOFF2SP bit. 2. After 1 above, write data ‘0’ to the PWMOFF2SP bit and then data ‘000,’ ‘001,’ ‘010,’ ‘011,’ ‘10X’ or ‘11X’ to the PWMOFF2S bit in succession. Note:  If a write cycle to any other area occurs between 1 and 2, the value written to the PWMOFF2S bit has no effect. (2) Using the PWM control registers to disable PWM outputs The PWM Output 0 Control Register (PO0DISCR) may be used to disable outputs from the ports P160/ TO21 –P165/TO26 that are provided for the PWM outputs of the TOU0_0–TOU0_5 timers. Similarly, the PWM Output 1 Control Register (PO1DISCR) may be used to disable outputs from the ports P180/TO29– P185/TO34 that are provided for the PWM outputs of the TOU1_0–TOU1_5 timers. Also, the PWM Output 2 Control Register (PO2DISCR) may be used to disable outputs from the ports P210/TO37–P215/TO42 that are provided for the PWM outputs of the TOU2_0–TOU2_5 timers. Set up the PWM Output Control Register (POnDISCR) as described below. When using the PWM Output 0 Control Register (PO0DISCR) to disable PWM outputs 1. Set the PO0DISCR register PO0DISP bit to "1". 2. After 1 above, set the PO0DISP bit to "0" and then the PO0DIS bit to "1" (output disabled). Note:  If a write cycle to any other area occurs between 1 and 2, the setting of the PO0DIS bit has no effect. When using the PWM Output 1 Control Register (PO1DISCR) to disable PWM outputs 1. Set the PO1DISCR register PO1DISP bit to "1". 2. After 1 above, set the PO1DISP bit to "0" and then the PO1DIS bit to "1" (output disabled). Note:  If a write cycle to any other area occurs between 1 and 2, the setting of the PO1DIS bit has no effect. When using the PWM Output 2 Control Register (PO2DISCR) to disable PWM outputs 1. Set the PO2DISCR register PO2DISP bit to "1". 2. After 1 above, set the PO2DISP bit to "0" and then the PO2DIS bit to "1" (output disabled). Note:  If a write cycle to any other area occurs between 1 and 2, the setting of the PO2DIS bit has no effect.

32180 Group User’s Manual (Rev.1.0) (3) Using the pin level on ports P160/TO21–P165/TO26, P180/TO29–P185/TO34 or P210/TO37–P215/TO42 to disable PWM outputs The pin level (high or low level) on ports P160/TO21–P165/TO26 may be used to disable outputs from the ports P160/TO21–P165/TO26 that are provided for the PWM outputs of the TOU0_0–TOU0_5 timers. Simi- larly, the pin level (high or low level) on ports P180/TO29–P185/TO34 may be used to disable outputs from the ports P180/TO29–P185/TO34 that are provided for the PWM outputs of the TOU1_0–TOU1_5 timers. Also, the pin level (high or low level) on ports P210/TO37–P215/TO42 may be used to disable outputs from the ports P210/TO37–P215/TO42 that are provided for the PWM outputs of the TOU2_0–TOU2_5 timers. To disable PWM outputs using the pin level of ports, set up the PWM Output Disable Control Register (POnLVCR) as described below. When using the P160/TO21–P165/TO26 port level to disable PWM outputs 1. Using the PO0LVCR register PO0LVSEL bit, select the high or low level at which PWM output is to be disabled. 2. Set the PO0LVEN bit to "1" (the selected output disable level effective). When using the P180/TO29–P185/TO34 port level to disable PWM outputs 1. Using the PO1LVCR register PO1LVSEL bit, select the high or low level at which PWM output is to be disabled. 2. Set the PO1LVEN bit to "1" (the selected output disable level effective). When using the P210/TO37–P215/TO42 port level to disable PWM outputs 1. Using the PO2LVCR register PO2LVSEL bit, select the high or low level at which PWM output is to be disabled. 2. Set the PO2LVEN bit to "1" (the selected output disable level effective).

32180 Group User’s Manual (Rev.1.0)

10.8.19 Example Application for Using the 32180 in Motor Control

The three-channel TOU timers incorporated in the 32180 help to reduce software burdens during motor control. The following shows an example application for using these 32180 timers in motor control. The three-phase motor control waveform is produced by starting TOU in accordance with the fixed 20 kHz TOU startup timing generated by TID. The single-shot PWM function included in TOU enables any desired output waveform to be configured easily by storing waveform data only when the data needs to be rewritten. Note that the transistor shorting prevention time can be provided by changing the set time of TOU in software. 32180 Power-MOS MotorU V W TOU TOU TOU TOU TOU TOU Circuit board Figure 10.8.23 System Configuration Diagram clk TOUn_0 clk TOUn_1 clk TOUn_2 clk TOUn_3 clk TOUn_4 clk TOUn_5 F/F F/F F/F F/F F/F F/F TO(U) PRS EN EN EN EN EN EN clk udfTIDn Single-shot PWM Single-shot PWM Single-shot PWM Single-shot PWM Single-shot PWM Single-shot PWM Fixed period udf udf udf udf udf udf TO(/U) TO(V) TO(/V) TO(W) TO(/W) 20 kHz generated Startup Figure 10.8.24 Timer Connections When Used for Three-Phase Motor Control U V W 20KHzTOU start TO(U) TO(/U) TO(V) TO(/V) TO(W) TO(/W) Delay Single shot Delay Single shot : Shorting prevention time Figure 10.8.25 Conceptual Diagram of Motor Control

32180 Group User’s Manual (Rev.1.0) This page is blank for reasons of layout.

11.1 Outline of A-D Converters

11.2 A-D Converter Related Registers

11.3 Functional Description of A-D Converters

11.4 Inflow Current Bypass Circuit

11.5 Precautions on Using A-D Converters

32180 Group User's Manual (Rev.1.0) The 32180 contains two 10-bit A-D Converters of the successive approximation type (A-D0 and A-D1 Converters). Each A-D Converter has 16 input channels. In addition to performing conversion individually on each channel, the A-D Converter can perform conversion successively on all of N channels (N = 1–16) as a single group. The conversion result can be read out in either 10 or 8 bits. There are following conversion and operation modes for the A-D conversion: (1) Conversion Modes  A-D conversion mode : Ordinary mode in which analog input voltages are converted into digital quantities.  Comparator mode (Note 1) : A mode in which analog input voltage is compared with a preset comparison voltage to find only the relative magnitude of two quantities. (Useful in only single operation mode) (2) Operation Modes  Single mode : Analog input voltage on one channel is A-D converted once or comparated (Note 1) with a given quantity.  Scan mode : Analog input voltages on two or more selected channels (in N channel units, N = 1–16) are sequentially A-D converted. Single-shot scan mode : Scan operation is performed for one machine cycle. Continuous scan mode : Scan operation is repeatedly until stopped. (3) Special Operation Modes  Forcible single mode execution during scan mode : Conversion is forcibly executed in single mode (comparator mode) during scan operation.  Scan mode start after single mode execution : Scan operation is started subsequently after executing conversion in single mode.  Conversion restart : A-D conversion being executed in single or scan mode is restarted. (4) Sample-and-Hold Function The analog input voltage is sampled when starting A-D conversion, and A-D conversion is performed on the sampled voltage. This function can be enabled or disabled as necessary. (5) A-D Disconnection Detection Assist Function To suppress influences of the analog input voltage wrapping around from any preceding channel during scan mode operation, a function is incorporated that helps to fix the electric charge on the chopper amp capacitor to the given state (AVCC or AVSS) before starting A-D conversion. This function provides a sure and reliable means of detecting a disconnection in the wiring patterns connecting to the analog input pins. (6) Inflow Current Bypass Circuit If an overvoltage or negative voltage is applied to any analog input channel which is currently inactive, a current flows into or out of the analog input channel currently being A-D converted via the internal circuit, causing the conversion accuracy to degrade. To solve this problem, the A-D Converter incorporates a circuit that bypasses such inflow current. This circuit is always enabled. (7) Conversion Speed The A-D conversion and comparate speed can be selected from a total of four speeds available: slow mode (normal or double speed) and fast mode (normal or double speed). The normal speed and double speed in slow mode are compatible with the 32170 group of Mitsubishi microcomputers.

32180 Group User's Manual (Rev.1.0) (8) Interrupt and DMA Transfer Request Generation Function An A-D conversion interrupt or DMA transfer request can be generated each time A-D conversion or comparate operation in single mode is completed, as well as when a single-shot scan operation or one cycle of continuous scan operation is completed. Note 1: To discriminate between the comparison performed internally by the successive approximation- type A-D Converter and that performed in comparator mode using the same A-D Converter as a comparator, the comparison in comparator mode is referred to in this manual as “comparate.” Table 11.1.1 Outline of the A-D Converters Item Description Analog input 16 channels ×2 A-D0 Converter: 16-channel analog input-only pins A-D1 Converter: 16-channel analog input-only pins A-D conversion method Successive approximation method Resolution 10 bits (Conversion result can be read out in either 8 or 10 bits) Absolute accuracy (Note 1) During slow mode: ±2 SLB at normal speed, ±2 SLB at double speed Conditions: Ta = 25°C,During fast mode: ±3 SLB at normal speed, ±3 SLB at double speed AVCC0, 1 = 5.12 V, Note:  The accuracy when sample-and-hold is enabled is T.B.D. VREF0, 1 = 5.12 V Conversion mode A-D conversion mode and comparator mode Operation mode Single mode, single-shot scan mode and continuous scan mode Conversion start trigger Software start Started by setting the A-D conversion start bit to "1" Hardware start A-D0 Converter MJT (input event bus 2), MJT (input event bus 3), MJT (output event bus 3) and MJT (TIN23S) A-D1 Converter MJT (input event bus 2), MJT (input event bus 3), TID1_udf/ovf and MJT (TIN23S) Conversion speed During single mode Slow mode Normal speed 299BCLK 14.95µs (Note 2) BCLK: ( When sample-and-hold disabled Double speed173BCLK 8.65µs Internal peripheral clock  When normal sample-and-hold enabled) Fast mode Normal speed 131BCLK 6.55µs Double speed 89BCLK 4.45µs During single mode Slow mode Normal speed 191BCLK 9.55µs (When fast sample-and-hold enabled) Double speed101BCLK 5.05µs Fast mode Normal speed 95BCLK 4.75µs Double speed 53BCLK 2.65µs During comparator mode Slow mode Normal speed 47BCLK 2.35µs Double speed 29BCLK 1.45µs Fast mode Normal speed 23BCLK 1.15µs Double speed 17BCLK 0.85µs Sample-and-hold functionSample-and-hold function can be enabled or disabled as necessary. A-D disconnection Influences of the analog input voltage wrapping around from any preceding channel during scan detection assist functionmode operation are suppressed. Interrupt request Generated when A-D conversion or comparate operation is completed generation function Generated when a single-shot scan operation or one cycle of continuous scan operation is completed DMA transfer request Generated when A-D conversion or comparate operation is completed generation function Generated when a single-shot scan operation or one cycle of continuous scan operation is completed Note 1: The conversion accuracy stipulated here refers to that of the microcomputer alone, with influences of the power supply wiring and noise on the board not taken into account. Note 2: This indicates the conversion time when f(BCLK) = 20 MHz (1 BCLK = 50 ns).

32180 Group User's Manual (Rev.1.0) Figure 11.1.1 Block Diagram of the A-D0 Converter AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 Selector Interrupt requestAVSS0 VREF0 10-bit A-D Successive Approximation Register (AD0SAR) 10-bit A-D0 Data Register 0 10-bit A-D0 Data Register 1 A-D0 Single Mode Register A-D Comparate Data Register A-D Control Circuit  Mode selection  Channel selection  Conversion time selection  Flag control  Interrupt control 10-bit D-A Converter Comparator AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 AD0CMP AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0DT12 AD0DT13 AD0DT14 AD0DT15 DMA transfer request Successive Approximation-type A-D Converter Unit Internal data bus A-D0 Scan Mode RegisterAD0SCM0, 1 AD0SIM0, 1 AVCC0 10-bit readout 8-bit readout Shifter 10-bit A-D0 Data Register 2 10-bit A-D0 Data Register 3 10-bit A-D0 Data Register 4 10-bit A-D0 Data Register 5 10-bit A-D0 Data Register 6 10-bit A-D0 Data Register 7 10-bit A-D0 Data Register 8 10-bit A-D0 Data Register 9 10-bit A-D0 Data Register 10 10-bit A-D0 Data Register 11 10-bit A-D0 Data Register 12 10-bit A-D0 Data Register 13 10-bit A-D0 Data Register 14 10-bit A-D0 Data Register 15 Input event bus 3 Input event bus 2 Output event bus 3 TIN23S S S AD0CTRG1 AD0STRG1 DMA0 DMA common Sample-and-Hold Control Circuit

32180 Group User's Manual (Rev.1.0) Figure 11.1.2 Block Diagram of the A-D1 Converter AD1IN0 AD1IN1 AD1IN2 AD1IN3 AD1IN4 AD1IN5 AD1IN6 AD1IN7 AVSS1 VREF1 AD1IN8 AD1IN9 AD1IN10 AD1IN11 AD1IN12 AD1IN13 AD1IN14 AD1IN15 AD1CMP AD1DT0 AD1DT1 AD1DT2 AD1DT3 AD1DT4 AD1DT5 AD1DT6 AD1DT7 AD1DT8 AD1DT9 AD1DT10 AD1DT11 AD1DT12 AD1DT13 AD1DT14 AD1DT15 AD1SCM0, 1 AD1SIM0, 1 AVCC1 10-bit readout 8-bit readout Shifter TIN23S S S AD1CTRG1 AD1STRG1 Internal data bus 10-bit A-D1 Data Register 0 10-bit A-D1 Data Register 1 A-D Comparate Data Register 10-bit A-D1 Data Register 2 10-bit A-D1 Data Register 3 10-bit A-D1 Data Register 4 10-bit A-D1 Data Register 5 10-bit A-D1 Data Register 6 10-bit A-D1 Data Register 7 10-bit A-D1 Data Register 8 10-bit A-D1 Data Register 9 10-bit A-D1 Data Register 10 10-bit A-D1 Data Register 11 10-bit A-D1 Data Register 12 10-bit A-D1 Data Register 13 10-bit A-D1 Data Register 14 10-bit A-D1 Data Register 15 A-D1 Single Mode Register A-D1 Scan Mode Register Input event bus 3 Input event bus 2 TID1_unf/ovf Interrupt request A-D Control Circuit  Mode selection  Channel selection  Conversion time selection  Flag control  Interrupt controlDMA transfer request DMA3 DMA9 Comparator Sample-and-Hold Control Circuit Selector Successive Approximation-type A-D Converter Unit 10-bit D-A Converter 10-bit A-D Successive Approximation Register (AD0SAR)

32180 Group User's Manual (Rev.1.0) Figure 11.1.3 Operation in Single Mode (A-D Conversion) A-D conversion interrupt or DMA transfer request Note 1: A-D0 conversion start: Software trigger → Started by setting the A-D0 conversion start bit to "1" Hardware trigger → Started by input event bus 3, input event bus 2, output event bus 3 or TIN23S signal input A-D1 conversion start: Software trigger → Started by setting the A-D1 conversion start bit to "1" Hardware trigger → Started by input event bus 3, input event bus 2, TID1_udf/ovf or TIN23S signal input ANiINn Completed ADiDTn 10-bit A-Di Data Register Conversion starts (Note 1) i=0, 1 n=0–15

11.1.1 Conversion Modes

The A-D Converters have two conversion mode: “A-D Conversion mode” and “Comparator mode.” (1) A-D Conversion Mode In A-D conversion mode, the analog input voltage on a specified channel is A-D converted. There are two operation modes for A-D conversion mode as will be described later. In single mode, A-D conversion is performed on a channel selected by the A-D Single Mode Register 1 analog input pin select bit. In scan mode, A-D conversion is performed on channels selected by A-D Scan Mode Register 1 according to settings of A-D Scan Mode Register 0. The conversion result is stored in each channel’s corresponding 10-bit A-D Data Register. There is also an 8- bit A-D Data Register for each channel, from which 8-bit A-D conversion results can be read out. An A-D conversion interrupt or DMA transfer request can be generated when A-D conversion in single mode is completed, as well as when one cycle of scan loop in scan mode is completed. (2) Comparator Mode In comparator mode, the analog input voltage on a specified channel is “comparated” (compared) with the succes- sive approximation register value, and the result (relative magnitude of two values) is returned to a flag. The channel to be comparated is selected using the A-D Single Mode Register 1 analog input pin select bit. The result of comparate operation is flagged ("0" or "1") by setting or resetting the A-D Comparate Data Register bit that corresponds to the selected channel. An A-D conversion interrupt or DMA transfer request can be generated when comparate operation is completed.

11.1.2 Operation Modes

There are two operation modes for the A-D Converter: “Single mode” and “Scan mode.” When comparator mode is selected as A-D conversion mode, only single mode can be used. (1) Single Mode In single mode, the analog input voltage on one selected channel is A-D converted or comparated once. An A-D conver- sion interrupt or DMA transfer request can be generated when A-D conversion or comparate operation is completed.

32180 Group User's Manual (Rev.1.0) A-D conversion interrupt or DMA transfer request ADiIN0 Completed here when operating in single-shot scan mode ADiDT010-bit A-Di Data Register Conversion starts (Note 1) ADiIN1 ADiINn-1 ADiINn ADiDT1 ADiDTn-1 ADiDTn During continuous scan mode <n-channel scan> i=0, 1 n=0–15 Note 1: A-D0 conversion start: Software trigger → Started by setting the A-D0 conversion start bit to "1" Hardware trigger → Started by input event bus 3, input event bus 2, output event bus 3 or TIN23S signal input A-D1 conversion start: Software trigger → Started by setting the A-D1 conversion start bit to "1" Hardware trigger → Started by input event bus 3, input event bus 2, TID1_udf/ovf or TIN23S signal input Figure 11.1.5 Operation of A-D Conversion in Scan Mode Figure 11.1.4 Operation in Single Mode (Comparate) (2) Scan Mode In scan mode, the analog input voltages on two or more selected channels from channel 0 (ADiIN0, i = 0 or 1) to the channel (channels 0–15) selected by the A-D Scan Mode Register 1 scan loop select bit are sequen- tially A-D converted. There are two types of scan mode: “Single-shot scan mode” in which A-D conversion is completed after performing one cycle of scan operation, and “Continuous scan mode” in which scan operation is continued until halted by setting the A-D scan mode register 0’s A-D conversion stop bit to "1". These types of scan mode are selected using A-D Scan Mode Register 0. The channels to be scanned are selected using A-D Scan Mode Register 1. The selected channels are scanned sequentially beginning with channel 0. An A-D conversion interrupt or DMA transfer request can be generated when one cycle of scan operation is completed. A-D conversion interrupt or DMA transfer request Note 1: Comparate operation is started by writing a comparison value to the Successive Approximation Register (ADiSAR) ADiINn Completed ADiCMP A-Di Comparate Data Register Conversion starts (Note 1) ADiSAR A-D Successive Approximation Register Comparate result ADiCMP=0 (ANn > ADiSAR) ADiCMP=1 (ANn < ADiSAR) i=0,1 n=0–15

32180 Group User's Manual (Rev.1.0) Table 11.1.2 Registers in Which Scan Mode A-D Conversion Results Are Stored Scan Mode Register 1 Selected channels Selected channels A-D conversion result channel selection for single-shot scan for continuous scan storage register B'0000:0 ADiIN0 ADiIN0 10-bit A-Di Data Register 0 (ADiIN0) Completed ADiIN0 10-bit A-Di Data Register 0 (Repeated until forcibly terminated) B'0001:1 ADiIN0 ADiIN0 10-bit A-Di Data Register 0 (ADiIN1) ADiIN1 ADiIN1 10-bit A-Di Data Register 1 Completed ADiIN0 10-bit A-Di Data Register 0 (Repeated until forcibly terminated) B'0010:2 ADiIN0 ADiIN0 10-bit A-Di Data Register 0 (ADiIN2) ADiIN1 ADiIN1 10-bit A-Di Data Register 1 ADiIN2 ADiIN2 10-bit A-Di Data Register 2 Completed ADiIN0 10-bit A-Di Data Register 0 (Repeated until forcibly terminated) B'0011:3 ADiIN0 ADiIN0 10-bit A-Di Data Register 0 (ADiIN3) ADiIN1 ADiIN1 10-bit A-Di Data Register 1 ADiIN2 ADiIN2 10-bit A-Di Data Register 2 ADiIN3 ADiIN3 10-bit A-Di Data Register 3 Completed ADiIN0 10-bit A-Di Data Register 0 (Repeated until forcibly terminated) B'XXXX:n ADiIN0 ADiIN0 10-bit A-Di Data Register 0 (ADiINn) ADiIN1 ADiIN1 10-bit A-Di Data Register 1 ADiIN2 ADiIN2 10-bit A-Di Data Register 2 n≤15 ADiINn ADiINn 10-bit A-Di Data Register n Completed ADiIN0 10-bit A-Di Data Register 0 (Repeated until forcibly terminated) (i=0, 1)

32180 Group User's Manual (Rev.1.0)

11.1.3 Special Operation Modes

(1) Forcible single mode execution during scan mode In this special operation mode, single mode conversion (A-D conversion or comparate) is forcibly executed on a specified channel during scan mode operation. For A-D conversion mode, the conversion result is stored in the 10-bit A-D Data Register corresponding to the specified channel, whereas for comparate mode, the conversion result is stored in the 10-bit A-D Comparate Data Register. When the A-D conversion or comparate operation on a specified channel finishes, scan mode A-D conversion is restarted from where it was canceled during scan operation. To start single mode conversion during scan mode operation in software, choose a software trigger using the A-D Single Mode Register 0 A-D conversion start trigger select bit. Then, for A-D conversion, set the said register’s A-D conversion start bit to "1". For comparate mode, write a comparison value to the A-D Succes- sive Approximation Register (AD0SAR or AD1SAR) during scan mode operation. To start single mode conversion during scan mode operation in hardware, choose a hardware trigger using the A-D Single Mode Register 0 A-D conversion start trigger select bit. Then enter the hardware trigger selected with the said register. An A-D conversion interrupt or DMA transfer request can be generated when conversion on a specified channel or one cycle of scan operation is completed. Figure 11.1.6 Forcible Single Mode Execution during Scan Mode A-D conversion interrupt or DMA transfer request ADiIN0 ADiDT010-bit A-Di Data Register Scan mode conversion starts ADiIN1 ADiDT1 ADiDT5 Note 1: The canceled convert operation on channel 2 is reexecuted from the beginning. <To perform single mode conversion on channel ADiIN5 during ADiIN2 conversion in n-channel single-shot scan mode> CompletedADiIN2 ADiINn ADiDT2 ADiDTn ADiIN5 Forcible single mode execution starts (Note 1)ADiIN2 i=0, 1 n=0–15

32180 Group User's Manual (Rev.1.0) Figure 11.1.7 Scan Mode Start after Single Mode Execution A-D conversion interrupt or DMA transfer request ADiIN0 ADiDT010-bit A-Di Data Register Instructed to start scan mode conversion ADiIN1 ADiDT1ADiDT5 <To start n-channel single-shot scan mode subsequently after single mode conversion on channel ADiIN5> CompletedADiINn-1 ADiINn ADiDTn-1 ADiDTn ADiIN5 Single mode conversion starts i=0, 1 n=0–15 (2) Scan mode start after single mode execution In this special operation mode, scan operation is started subsequently after executing single mode conver- sion (A-D conversion or comparate). To start this mode in software, choose a software trigger using the A-D Scan Mode Register 0 A-D conver- sion start trigger select bit. Then set the said register’s A-D conversion start bit to "1" during single mode conversion operation. To start this mode in hardware, choose a hardware trigger using the A-D Scan Mode Register 0 A-D conver- sion start trigger select bit. Then enter the hardware trigger selected with the said register during single mode conversion operation. If a hardware trigger is selected using the A-D conversion start trigger select bit in both A-D Single Mode Register 0 and A-D Scan Mode Register 0 and the selected hardware triggers are entered, the A-D Converter first performs single mode conversion and then scan mode conversion in succession. An A-D conversion interrupt or DMA transfer request can be generated when single mode conversion on a specified channel or one cycle of scan operation is completed.

32180 Group User's Manual (Rev.1.0) (3) Conversion restart In this special operation mode, operation being executed in single or scan mode is stopped in the middle and reexecuted from the beginning. When in single mode, set the A-D Single Mode Register 0 A-D conversion start bit to "1" again or enter a hardware trigger during A-D conversion or comparate operation, and the operation that was stopped during execution is executed over again. When in scan mode, set the A-D Scan Mode Register 0 A-D conversion start bit to "1" again or enter a hardware trigger signal during scan operation, and the channel being converted is canceled and A-D conver- sion is performed from channel 0 over again. Figure 11.1.8 Conversion Restart during Single Mode Operation A-D conversion interrupt or DMA transfer request Single mode ADiIN5 conversion starts ADiDT5 <To restart single mode ADiIN5 conversion> Completed Single mode ADiIN5 restarts ADiIN5 ADiIN5 10-bit A-Di Data Register i=0, 1 Figure 11.1.9 Conversion Restart during Scan Operation A-D conversion interrupt or DMA transfer request ADiIN0 ADiDT010-bit A-Di Data Register Scan mode conversion starts ADiIN1 ADiDT1 <To restart during ADiIN2 conversion in n-channel single-shot scan mode> CompletedADiINn-1 ADiINn ADiDTn-1 ADiDTn Scan mode restarts ADiIN2 ADiIN0 ADiDT0 ADiIN1 ADiDT1 i=0, 1 n=0–15

32180 Group User's Manual (Rev.1.0)

11.1.4 A-D Converter Interrupt and DMA Transfer Requests

The A-D Converter can generate an A-D conversion interrupt or DMA transfer request each time A-D conver- sion, comparate operation, single-shot scan or one cycle of continuous scan mode is completed. The A-D Single Mode Register 0 and A-D Scan Mode Register 0 are used to select between A-D conversion interrupt and DMA transfer requests. Figure 11.1.10 Selecting between Interrupt and DMA Transfer Requests

11.1.5 Sample-and-Hold Function

The analog input voltage that was sampled immediately after A-D conversion started is held on, and A-D conver- sion is performed on that seized voltage. The A-D conversion time in “normal” sample-and-hold mode is the same as in conventional A-D conversion mode of the 32170, etc. The A-D conversion time in “fast” sample-and-hold mode is significantly short, allowing to obtain conversion results more quickly than ever. Scan mode (when one cycle of scan is completed) Single mode (when A-D conversion or comparate operation is completed) A-Di conversion interrupt request (To the Interrupt Controller) DMA transfer request (To the DMAC Controller) A-Di Scan Mode Register 0 interrupt/DMA transfer request select bit A-Di Single Mode Register 0 interrupt/DMA transfer request select bit i=0, 1

32180 Group User's Manual (Rev.1.0) Shown below is an A-D converter related register map. A-D Converter Related Register Map (1/3) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0080 A-D0 Single Mode Register 0 A-D0 Single Mode Register 1 11-16 (AD0SIM0) (AD0SIM1) 11-18 H'0080 0082 (Use inhibited area) H'0080 0084 A-D0 Scan Mode Register 0 A-D0 Scan Mode Register 1 11-20 (AD0SCM0) (AD0SCM1) 11-22 H'0080 0086 A-D0 Disconnection Detection Assist Function Control RegisterA-D0 Conversion Speed Control Register 11-25 (AD0DDACR) (AD0CVSCR) 11-24 H'0080 0088 A-D0 Successive Approximation Register 11-29 (AD0SAR) H'0080 008A A-D0 Disconnection Detection Assist Method Select Register 11-26 (AD0DDASEL) H'0080 008C A-D0 Comparate Data Register 11-30 (AD0CMP) H'0080 008E (Use inhibited area) H'0080 0090 10-bit A-D0 Data Register 0 11-31 (AD0DT0) H'0080 0092 10-bit A-D0 Data Register 1 11-31 (AD0DT1) H'0080 0094 10-bit A-D0 Data Register 2 11-31 (AD0DT2) H'0080 0096 10-bit A-D0 Data Register 3 11-31 (AD0DT3) H'0080 0098 10-bit A-D0 Data Register 4 11-31 (AD0DT4) H'0080 009A 10-bit A-D0 Data Register 5 11-31 (AD0DT5) H'0080 009C 10-bit A-D0 Data Register 6 11-31 (AD0DT6) H'0080 009E 10-bit A-D0 Data Register 7 11-31 (AD0DT7) H'0080 00A0 10-bit A-D0 Data Register 8 11-31 (AD0DT8) H'0080 00A2 10-bit A-D0 Data Register 9 11-31 (AD0DT9) H'0080 00A4 10-bit A-D0 Data Register 10 11-31 (AD0DT10) H'0080 00A6 10-bit A-D0 Data Register 11 11-31 (AD0DT11) H'0080 00A8 10-bit A-D0 Data Register 12 11-31 (AD0DT12) H'0080 00AA 10-bit A-D0 Data Register 13 11-31 (AD0DT13) H'0080 00AC 10-bit A-D0 Data Register 14 11-31 (AD0DT14) H'0080 00AE 10-bit A-D0 Data Register 15 11-31 (AD0DT15) | (Use inhibited area) H'0080 00D0 (Use inhibited area) 8-bit A-D0 Data Register 0 11-32 (AD08DT0) H'0080 00D2 (Use inhibited area) 8-bit A-D0 Data Register 1 11-32 (AD08DT1) H'0080 00D4 (Use inhibited area) 8-bit A-D0 Data Register 2 11-32 (AD08DT2) H'0080 00D6 (Use inhibited area) 8-bit A-D0 Data Register 3 11-32 (AD08DT3) H'0080 00D8 (Use inhibited area) 8-bit A-D0 Data Register 4 11-32 (AD08DT4) H'0080 00DA (Use inhibited area) 8-bit A-D0 Data Register 5 11-32 (AD08DT5) H'0080 00DC (Use inhibited area) 8-bit A-D0 Data Register 6 11-32 (AD08DT6)

32180 Group User's Manual (Rev.1.0) A-D Converter Related Register Map (2/3) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 00DE (Use inhibited area) 8-bit A-D0 Data Register 7 11-32 (AD08DT7) H'0080 00E0 (Use inhibited area) 8-bit A-D0 Data Register 8 11-32 (AD08DT8) H'0080 00E2 (Use inhibited area) 8-bit A-D0 Data Register 9 11-32 (AD08DT9) H'0080 00E4 (Use inhibited area) 8-bit A-D0 Data Register 10 11-32 (AD08DT10) H'0080 00E6 (Use inhibited area) 8-bit A-D0 Data Register 11 11-32 (AD08DT11) H'0080 00E8 (Use inhibited area) 8-bit A-D0 Data Register 12 11-32 (AD08DT12) H'0080 00EA (Use inhibited area) 8-bit A-D0 Data Register 13 11-32 (AD08DT13) H'0080 00EC (Use inhibited area) 8-bit A-D0 Data Register 14 11-32 (AD08DT14) H'0080 00EE (Use inhibited area) 8-bit A-D0 Data Register 15 11-32 (AD08DT15) H'0080 0A80 A-D1 Single Mode Register 0 A-D1 Single Mode Register 1 11-16 (AD1SIM0) (AD1SIM1) 11-18 H'0080 0A82 (Use inhibited area) H'0080 0A84 A-D1 Scan Mode Register 0 A-D1 Scan Mode Register 1 11-20 (AD1SCM0) (AD1SCM1) 11-22 H'0080 0A86 A-D1 Disconnection Detection Assist Function Control RegisterA-D1 Conversion Speed Control Register 11-25 (AD1DDACR) (AD1CVSCR) 11-24 H'0080 0A88 A-D1 Successive Approximation Register 11-29 (AD1SAR) H'0080 0A8A A-D1 Disconnection Detection Assist Method Select Register 11-26 (AD1DDASEL) H'0080 0A8C A-D1 Comparate Data Register 11-30 (AD1CMP) H'0080 0A8E (Use inhibited area) H'0080 0A90 10-bit A-D1 Data Register 0 11-31 (AD1DT0) H'0080 0A92 10-bit A-D1 Data Register 1 11-31 (AD1DT1) H'0080 0A94 10-bit A-D1 Data Register 2 11-31 (AD1DT2) H'0080 0A96 10-bit A-D1 Data Register 3 11-31 (AD1DT3) H'0080 0A98 10-bit A-D1 Data Register 4 11-31 (AD1DT4) H'0080 0A9A 10-bit A-D1 Data Register 5 11-31 (AD1DT5) H'0080 0A9C 10-bit A-D1 Data Register 6 11-31 (AD1DT6) H'0080 0A9E 10-bit A-D1 Data Register 7 11-31 (AD1DT7) H'0080 0AA0 10-bit A-D1 Data Register 8 11-31 (AD1DT8) H'0080 0AA2 10-bit A-D1 Data Register 9 11-31 (AD1DT9) H'0080 0AA4 10-bit A-D1 Data Register 10 11-31 (AD1DT10) H'0080 0AA6 10-bit A-D1 Data Register 11 11-31 (AD1DT11) H'0080 0AA8 10-bit A-D1 Data Register 12 11-31 (AD1DT12) H'0080 0AAA 10-bit A-D1 Data Register 13 11-31 (AD1DT13) H'0080 0AAC 10-bit A-D1 Data Register 14 11-31 (AD1DT14) H'0080 0AAE 10-bit A-D1 Data Register 15 11-31 (AD1DT15) | (Use inhibited area)

32180 Group User's Manual (Rev.1.0) A-D Converter Related Register Map (3/3) Adrdress +0 address +1 address See b0 b7 b8 b15 pages H'0080 0AD0 (Use inhibited area) 8-bit A-D1 Data Register 0 11-32 (AD18DT0) H'0080 0AD2 (Use inhibited area) 8-bit A-D1 Data Register 1 11-32 (AD18DT1) H'0080 0AD4 (Use inhibited area) 8-bit A-D1 Data Register 2 11-32 (AD18DT2) H'0080 0AD6 (Use inhibited area) 8-bit A-D1 Data Register 3 11-32 (AD18DT3) H'0080 0AD8 (Use inhibited area) 8-bit A-D1 Data Register 4 11-32 (AD18DT4) H'0080 0ADA (Use inhibited area) 8-bit A-D1 Data Register 5 11-32 (AD18DT5) H'0080 0ADC (Use inhibited area) 8-bit A-D1 Data Register 6 11-32 (AD18DT6) H'0080 0ADE (Use inhibited area) 8-bit A-D1 Data Register 7 11-32 (AD18DT7) H'0080 0AE0 (Use inhibited area) 8-bit A-D1 Data Register 8 11-32 (AD18DT8) H'0080 0AE2 (Use inhibited area) 8-bit A-D1 Data Register 9 11-32 (AD18DT9) H'0080 0AE4 (Use inhibited area) 8-bit A-D1 Data Register 10 11-32 (AD18DT10) H'0080 0AE6 (Use inhibited area) 8-bit A-D1 Data Register 11 11-32 (AD18DT11) H'0080 0AE8 (Use inhibited area) 8-bit A-D1 Data Register 12 11-32 (AD18DT12) H'0080 0AEA (Use inhibited area) 8-bit A-D1 Data Register 13 11-32 (AD18DT13) H'0080 0AEC (Use inhibited area) 8-bit A-D1 Data Register 14 11-32 (AD18DT14) H'0080 0AEE (Use inhibited area) 8-bit A-D1 Data Register 15 11-32 (AD18DT15)

32180 Group User's Manual (Rev.1.0)

11.2.1 A-D Single Mode Registers 0

A-D0 Single Mode Register 0 (AD0SIM0) <Address: H ’0080 0080> A-D1 Single Mode Register 0 (AD1SIM0) <Address: H'0080 0A80> 123456 b 7b0 ADSTRG0ADSTRG1 ADSSEL ADSREQ ADSSTT ADSSTPADSCMP 0 0001000 <After reset: H’04> b Bit Name Function R W 0 ADSTRG1 (Note 1) Bits 0 and 2 are used to select an A-D hardware trigger. R W A-D hardware trigger select 1 bit b0 b2 A-D0 Converter A-D1 Converter 0 0 : Input event bus 2 Input event bus 2 0 1 : Input event bus 3 Input event bus 3 1 0 : Output event bus 3 TID1_udf/ovf 1 1 : TIN23S signal TIN23S signal 1 No function assigned. Fix to "0". 00 2 ADSTRG0 (Note 1) Bits 0 and 2 are used to select an A-D hardware trigger. R W A-D hardware trigger select 0 bit (See the column for bit 0.)

3 ADSSEL 0: Software trigger R W

A-D conversion start trigger select bit 1: Hardware trigger (Note 2)

4 ADSREQ 0: A-D conversion interrupt request R W

Interrupt/DMA transfer request select bit 1: DMA transfer request

5 ADSCMP 0: A-D conversion/comparate in progress R –

A-D conversion/comparate completed bit 1: A-D conversion/comparate completed

6 ADSSTP 0: No operation 0 W

A-D conversion stop bit 1: Stop A-D conversion

7 ADSSTT 0: No operation 0 W

A-D conversion start bit 1:Start A-D conversion Note 1: Two bits— A-D hardware trigger select 1 (bit 0) and A-D hardware trigger select 0 (bit 2)— are used to select an A-D hardware trigger. Note 2: During comparator mode, hardware triggers, if any selected, are ignored and operation is started by a software trigger. A-D Single Mode Registers 0 are used to control operation of the A-D Converters during single mode (including “Forcible single mode execution during scan mode”). (1) ADSTRG (A-D Hardware Trigger Select) bits (Bits 0 and 2) These bits select a hardware trigger when A-D conversion by the A-D Converter is to be started in hardware. Select one from the following hardware trigger sources: A-D0 Converter: Input event bus 2 A-D1 Converter: Input event bus 2 Input event bus 3 Input event bus 3 Output event bus 3 TID1 underflow/overflow TIN23 edge select output TIN23 edge select output The contents of these bits are ignored if a software trigger is selected by ADSSEL (A-D conversion start trigger select bit).

32180 Group User's Manual (Rev.1.0) (2) ADSSEL (A-D Conversion Start Trigger Select) bit (Bit 3) This bit selects whether to use a software or hardware trigger to start A-D conversion during single mode. If a software trigger is selected, A-D conversion is started by setting the ADSSTT (A-D conversion start) bit to "1". If a hardware trigger is selected, A-D conversion is started by the trigger source selected with the ADSTRG (hardware trigger select) bits. (3) ADSREQ (A-D Interrupt/DMA Transfer Request Select) bit (Bit 4) This bit selects whether to request an A-D conversion interrupt or a DMA transfer when single mode opera- tion (A-D conversion or comparate) is completed. If neither an interrupt nor a DMA transfer are used, choose to request an A-D conversion interrupt and use the A-D Converter Interrupt Control Register of the Interrupt Controller (ICU) to mask the interrupt request, or choose to request a DMA transfer and use the DMA Chan- nel Control Register to disable DMA transfers to be performed upon completion of A-D conversion. (4) ADSCMP (A-D Conversion/Comparate Completed) bit (Bit 5) This is a read-only bit, whose value after reset is "1". This bit is "0" when the A-D Converter is performing single mode operation (A-D conversion or comparate) and is set to "1" when the operation finishes. This bit is also set to "1" when A-D conversion or comparate operation is forcibly terminated by setting the ADSSTP (A-D conversion stop) bit to "1" during A-D conversion or comparate operation. (5) ADSSTP (A-D Conversion Stop) bit (Bit 6) Setting this bit to "1" while the A-D Converter is performing single mode operation (A-D conversion or comparate) causes the operation being performed to stop. Manipulation of this bit is ignored while single mode operation is idle or scan mode operation is under way. Operation stops immediately after writing to this bit. If the A-D Successive Approximation Register is read after being stopped, the content read from the register is the value in the middle of conversion (not trans- ferred to the A-D Data Register). If the A-D conversion start bit and A-D conversion stop bit are set to "1" at the same time, the A-D conversion stop bit has priority. If this bit is set to "1" when performing single mode operation in special mode “Forcible single mode execution during scan mode,” only single mode conversion stops and scan mode operation restarts. (6) ADSSTT (A-D Conversion Start) bit (Bit 7) If this bit is set to "1" when a software trigger has been selected with the ADSSEL (A-D conversion start trigger select) bit, the A-D Converter starts A-D conversion. If the A-D conversion start bit and A-D conversion stop bit are set to "1" at the same time, the A-D conversion stop bit has priority. If this bit is set to "1" again while performing single mode conversion, special operation mode “Conversion restart” is turned on, so that single mode conversion restarts. If this bit is set to "1" again while performing A-D conversion in scan mode, special operation mode “Forcible single mode execution during scan mode” is turned on, so that the channel being converted in scan mode is canceled and single mode conversion is performed. When the single mode conversion finishes, scan mode A-D conversion restarts beginning with the canceled channel.

32180 Group User's Manual (Rev.1.0)

11.2.2 A-D Single Mode Registers 1

A-D0 Single Mode Register 1 (AD0SIM1) <Address: H ’0080 0081> A-D1 Single Mode Register 1 (AD1SIM1) <Address: H ’0080 0A81> 9 1 01 11 21 31 4 b 1 5b8 ADSMSL ADSSPD ADSSHSL ANSEL 00000000 ADSSHSPD <After reset: H’00> b Bit Name Function R W

8 ADSMSL 0: A-D conversion mode R W

A-D conversion mode select bit 1: Comparator mode

9 ADSSPD (Note 1) 0: Normal speed R W

A-D conversion speed select bit 1: Double speed

10 ADSSHSL 0: Disable sample-and-hold R W

A-D conversion method select bit 1: Enable sample-and-hold

11 ADSSHSPD (Note 2) 0: Normal sample-and-hold R W

A-D sample-and-hold conversion speed select bit 1: Fast sample-and-hold 12–15 ANSEL 0000 : Select ADiIN0 (i = 0, 1) R W A-D analog input pin select bit 0001 : Select ADiIN1 0010 : Select ADiIN2 0011 : Select ADiIN3 0100 : Select ADiIN4 0101 : Select ADiIN5 0110 : Select ADiIN6 0111 : Select ADiIN7 1000 : Select ADiIN8 1001 : Select ADiIN9 1010 : Select ADiIN10 1011 : Select ADiIN11 1100 : Select ADiIN12 1101 : Select ADiIN13 1110 : Select ADiIN14 1111 : Select ADiIN15 Note 1: The A-D conversion speed is determined by a combination of ADSSPD, ADSSHSL and ADSSHSPD bits and the A-D Conversion Speed Control Register ADCVSD bit. Note 2: Setting of this bit is effective when the sample-and-hold function is enabled by ADSSHSL bit. A-D Single Mode Registers 1 are used to select operation mode, conversion speed and analog input pins when the A-D Converter is operating in single mode.

32180 Group User's Manual (Rev.1.0) (1) ADSMSL (A-D Conversion Mode Select) bit (Bit 8) This bit selects A-D conversion mode when the A-D Converter is operating in single mode. Setting this bit to "0" selects A-D conversion mode, and setting this bit to "1" selects comparator mode. (2) ADSSPD (A-D Conversion Speed Select) bit (Bit 9) This bit selects the A-D conversion speed when the A-D Converter is operating in single mode. Setting this bit to "0" selects normal speed, and setting this bit to "1" selects double speed. (3) ADSSHSL (A-D Conversion Method Select) bit (Bit 10) This bit enables or disables the sample-and-hold function when the A-D Converter is operating in single mode. Setting this bit to "0" disables the sample-and-hold function, and setting this bit to "1" enables the sample-and-hold function. Setting of this bit has no effect if comparator mode is selected with the ADSMSL (A-D conversion mode select) bit. (4) ADSSHSPD (A-D Sample-and-Hold Speed Select) bit (Bit 11) When the A-D Converter’s sample-and-hold function is enabled, this bit selects a conversion speed. When this bit is "0", the conversion speed is the same as normal A-D conversion speed. When this bit is "1", conversion is performed at a speed faster than normal A-D conversion speed. Setting of this bit has no effect if the sample-and-hold function is disabled by setting the ADSSHSL (A-D conversion method select) bit to "0". For details about the conversion time, see Section 11.3.4, “Calculating the A-D Conversion Time.” (5) ANSEL (A-D Analog Input Pin Select) bits (Bits 12–15) These bits select the analog input pins when the A-D Converter is operating in single mode. A-D conversion or comparate operation is performed on the channels selected with these bits. If these bits are accessed for read, the value written to them is read out.

32180 Group User's Manual (Rev.1.0)

11.2.3 A-D Scan Mode Registers 0

A-D0 Scan Mode Register 0 (AD0SCM0) <Address: H ’0080 0084> A-D1 Scan Mode Register 0 (AD1SCM0) <Address: H ’0080 0A84> 123456 b 7b0 ADCTRG0ADCMSLADCTRG1 ADSHIDE ADCREQ ADCSTT ADCSTPADCCMP 00000100 <After reset: H’04> b Bit Name Function R W 0 ADCTRG1 (Note 1) Bits 0 and 2 are used to select an A-D hardware trigger. R W A-D hardware trigger select 1 bit b0 b2 A-D0 Converter A-D1 Converter 0 0 : Input event bus 2 Input event bus 2 0 1 : Input event bus 3 Input event bus 3 1 0 : Output event bus 3 TID1_udf/ovf 1 1 : TIN23S signal TIN23S signal

1 ADCMSL 0: Single-shot mode R W

A-D scan mode select bit 1: Continuous mode 2 ADCTRG0 (Note 1) Bits 0 and 2 are used to select an A-D hardware trigger. R W A-D hardware trigger select 0 bit (See the column for bit 0.)

3 ADCSEL 0: Software trigger R W

A-D conversion start trigger select bit 1: Hardware trigger

4 ADCREQ 0: A-D conversion interrupt request R W

Interrupt/DMA transfer request select bit 1: DMA transfer request

5 ADCCMP 0: A-D conversion in progress R –

A-D conversion completed bit 1: A-D conversion completed

6 ADCSTP 0: No operation 0 W

A-D conversion stop bit 1: Stop A-D conversion

7 ADCSTT 0: No operation 0 W

A-D conversion start bit 1: Start A-D conversion Note 1: Two bits— A-D hardware trigger select 1 (bit 0) and A-D hardware trigger select 0 (bit 2)— are used to select an A-D hardware trigger. A-D Scan Mode Registers 0 are used to control operation of the A-D Converters during scan mode. (1) ADCTRG (A-D Hardware Trigger Select) bits (Bits 0 and 2) These bits select a hardware trigger when A-D conversion by the A-D Converter is to be started in hardware. Select one from the following hardware trigger sources: A-D0 Converter: Input event bus 2 A-D1 Converter: Input event bus 2 Input event bus 3 Input event bus 3 Output event bus 3 TID1 underflow/overflow TIN23 edge select output TIN23 edge select output The contents of these bits are ignored if a software trigger is selected by ADCSEL (A-D conversion start trigger select bit).

32180 Group User's Manual (Rev.1.0) (2) ADCMSL (A-D Scan Mode Select) bit (Bit 1) This bit selects scan mode of the A-D Converter between single-shot scan and continuous scan. Setting this bit to "0" selects single-shot scan mode, where the channels selected with the ANSCAN (scan loop select) bits are sequentially A-D converted and when A-D conversion on all selected channels is com- pleted, the conversion operation stops. Setting this bit to "1" selects continuous scan mode, where after operation in single-shot scan mode finishes, A-D conversion is reexecuted beginning with the first channel and continued until stopped by setting the ADCSTP (A-D conversion stop) bit to "1". (3) ADCSEL (A-D Conversion Start Trigger Select) bit (Bit 3) This bit selects whether to use a software or hardware trigger to start A-D conversion during scan mode. If a software trigger is selected, A-D conversion is started by setting the ADCSTT (A-D conversion start) bit to "1". If a hardware trigger is selected, A-D conversion is started by the trigger source selected with the ADnCTRG (hardware trigger select) bits. (4) ADCREQ (A-D Interrupt/DMA Transfer Request Select) bit (Bit 4) This bit selects whether to request an A-D conversion interrupt or a DMA transfer when one cycle of scan mode operation is completed. If neither an interrupt nor a DMA transfer are used, choose to request an A-D conversion interrupt and use the A-D Converter Interrupt Control Register of the Interrupt Controller (ICU) to mask the interrupt request, or choose to request a DMA transfer and use the DMA Channel Control Register to disable DMA transfers to be performed upon completion of A-D conversion. (5) ADCCMP (A-D Conversion Completed) bit (Bit 5) This is a read-only bit, whose value after reset is 1. This bit is 0 when the A-D Converter is performing scan mode A-D conversion and is set to "1" when single-shot scan mode finishes or continuous scan mode is stopped by setting the ADCSTP (A-D conversion stop) bit to "1". (6) ADCSTP (A-D Conversion Stop) bit (Bit 6) Setting this bit to "1" while the A-D Converter is performing scan mode A-D conversion causes the operation being performed to stop. This bit is effective only for scan mode operation, and does not affect single mode operation even when single and scan modes both are active during special operation mode. Operation stops immediately after writing to this bit, and the A-D conversion being performed on any channel is aborted in the middle, without transferring the result to the A-D data register. If the A-D conversion start bit and A-D conversion stop bit are set to "1" at the same time, the A-D conversion stop bit has priority. (7) ADCSTT (A-D Conversion Start) bit (Bit 7) This bit is used to start scan mode operation of the A-D Converter in software. Only when a software trigger has been selected with the ADCSEL (A-D conversion start trigger select) bit, setting this bit to "1" causes A- D conversion to start. If the A-D conversion start bit and A-D conversion stop bit are set to "1" at the same time, the A-D conversion stop bit has priority. If this bit is set to "1" again while performing scan mode conversion, special operation mode “Conversion restart” is turned on, so that scan mode operation is restarted using the contents set by A-D Scan Mode Registers 0 and 1. If this bit is set to "1" again while performing A-D conversion in scan mode, special operation mode “Scan mode start after single mode execution” is turned on, so that scan mode operation starts subsequently after single mode has finished.

32180 Group User's Manual (Rev.1.0)

11.2.4 A-D Scan Mode Registers 1

A-D0 Scan Mode Register 1 (AD0SCM1) <Address: H ’0080 0085> A-D1 Scan Mode Register 1 (AD1SCM1) <Address: H ’0080 0A85> 9 1 01 11 21 31 4 b 1 5b8 ADCSPD ADCSHSL ADSCAN 0000000 ADCSHSPD <After reset: H’00> b Bit Name Function R W 8 No function assigned. Fix to "0". 00

9 ADCSPD (Note 1) 0: Normal speed R W

A-D conversion speed select bit 1: Double speed

10 ADCSHSL 0: Disable sample-and-hold R W

A-D conversion method select bit 1: Enable sample-and-hold

11 ADCSHSPD (Note 2) 0: Normal sample-and-hold R W

A-D sample-and-hold conversion speed select bit 1: Fast sample-and-hold 12–15 ADSCAN <For write> R W A-D scan loop select bit ‘B0000 –1111 (channels 0–15) <For read during conversion> (i = 0, 1) 0000: Converting ADiIN0 0001: Converting ADiIN1 0010: Converting ADiIN2 0011: Converting ADiIN3 0100: Converting ADiIN4 0101: Converting ADiIN5 0110: Converting ADiIN6 0111: Converting ADiIN7 1000: Converting ADiIN8 1001: Converting ADiIN9 1010: Converting ADiIN10 1011: Converting ADiIN11 1100: Converting ADiIN12 1101: Converting ADiIN13 1110: Converting ADiIN14 1111: Converting ADiIN15 Note 1: The A-D conversion speed is determined by a combination of ADCSPD, ADCSHSL and ADCSHSPD bits and the A-D Conversion Speed Control Register ADCVSD bit. Note 2: Setting of this bit is effective when the sample-and-hold function is enabled by ADCSHSL bit. A-D Scan Mode Registers 1 are used to select operation mode, conversion speed and scan loop when the A-D Converter is operating in scan mode. The channels selected with the scan loop select bit are scanned sequen- tially beginning with channel 0 (n-channel scan).

32180 Group User's Manual (Rev.1.0) (1) ADCSPD (A-D Conversion Speed Select) bit (Bit 9) This bit selects an A-D conversion speed when the A-D Converter is operating in scan mode. Setting this bit to selects normal speed, and setting this bit to "1" selects double speed. (2) ADCSHSL (A-D Conversion Method Select) bit (Bit 10) This bit enables or disables the sample-and-hold function when the A-D Converter is operating in scan mode. Setting this bit to "0" disables the sample-and-hold function, and setting this bit to "1" enables the sample- and-hold function. (3) ADSSHSPD (A-D Sample-and-Hold Speed Select) bit (Bit 11) When the A-D Converter’s sample-and-hold function is enabled, this bit selects a conversion speed. When this bit is "0", the conversion speed is the same as normal A-D conversion speed. When this bit is "1", conversion is performed at a speed faster than normal A-D conversion speed. Setting of this bit has no effect if the sample-and-hold function is disabled by setting the ADCSHSL (A-D conversion method select) bit to "0". For details about the conversion time, see Section 11.3.4, “Calculating the A-D Conversion Time.” (4) ANSCAN (A-D Scan Loop Select) bits (Bits 12–15) The ANSCAN (A-D scan loop select) bits set the channels to be scanned during scan mode of the A-D Converter. The ANSCAN (A-D scan loop select) bits when accessed for read during scan operation serve as a status register indicating the channel being scanned. The value read from these bits during single mode is always B’0000. If A-D conversion is stopped by setting A-D Scan Mode Register 0 ADCSTP (A-D conversion stop) bit to "1" while executing scan mode, the value read from these bits indicates the channel whose A-D conversion has been canceled. Also, if read during single mode conversion of special operation mode “Forcible single mode execution dur- ing scan mode,” the value of these bits indicates the channel whose A-D conversion has been canceled in the middle of scan.

32180 Group User's Manual (Rev.1.0)

11.2.5 A-D Conversion Speed Control Registers

A-D0 Conversion Speed Control Register (AD0CVSCR) <Address: H ’0080 0087> A-D1 Conversion Speed Control Register (AD1CVSCR) <Address: H ’0080 0A87> 9 1 01 11 21 31 4 b 1 5b8 ADCVSD 00 0 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 8–14 No function assigned. Fix to "0". 00

15 ADCVSD (Note 1) 0: Slow mode R W

A-D conversion speed control bit 1: Fast mode Note 1: The A-D conversion speed is determined by a combination of ADCVSD bit and A-D Single Mode Register 1’s relevant bit during single mode, or a combination of ADCVSD bit and A-D Scan Mode Register 1’s relevant bit during scan mode. The A-D Conversion Speed Control Registers control the A-D conversion speed during single and scan modes of the A-D Converter.

32180 Group User's Manual (Rev.1.0)

11.2.6 A-D Disconnection Detection Assist Function Control Registers

A-D0 Disconnection Detection Assist Function Control Register (AD0DDACR) <Address: H’0080 0086> A-D1 Disconnection Detection Assist Function Control Register (AD1DDACR) <Address: H’0080 0A86> 123456 b 7b0 ADDDAEN 00 0 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 0–6 No function assigned. Fix to "0". 00

7 ADDDAEN (Note 1) 0: Disable A-D disconnection detection assist function R W

A-D disconnection detection assist function enable bit 1: Enable A-D disconnection detection assist function Note 1: For the A-D disconnection detection assist function to be enabled, the conversion start state (discharge or precharge) must be set using the A-D disconnection detection assist method select register after setting the ADDDAEN bit to "1". The A-D Disconnection Detection Assist Function Control Registers are used to enable or disable the content of the A-D Disconnection Detection Assist Method Select Register. Note:  If any analog input wiring is disconnected, the conversion result varies depending on the circuits fitted external to the chip. This function must be fully evaluated in the actual application system before it can be used.

32180 Group User's Manual (Rev.1.0)

11.2.7 A-D Disconnection Detection Assist Method Select Registers

A-D0 Disconnection Detection Assist Method Select Register (AD0DDASEL) <Address: H’0080 008A> A-D1 Disconnection Detection Assist Method Select Register (AD1DDASEL) <Address: H’0080 0A8A> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 ADDDA SEL0 ADDDA SEL1 ADDDA SEL2 ADDDA SEL3 ADDDA SEL4 ADDDA SEL6 ADDDA SEL7 ADDDA SEL8 ADDDA SEL9 ADDDA SEL10 ADDDA SEL11 ADDDA SEL12 ADDDA SEL13 ADDDA SEL14 ADDDA SEL15 ADDDA SEL5 <After reset: Undefined> b Bit Name Function R W

0 ADDDASEL0 0: Discharge before conversion R W

Channel 0 disconnection detection assist method select bit 1: Precharge before conversion

1 ADDDASEL1

Channel 1 disconnection detection assist method select bit

2 ADDDASEL2

Channel 2 disconnection detection assist method select bit

3 ADDDASEL3

Channel 3 disconnection detection assist method select bit

4 ADDDASEL4

Channel 4 disconnection detection assist method select bit

5 ADDDASEL5

Channel 5 disconnection detection assist method select bit

6 ADDDASEL6

Channel 6 disconnection detection assist method select bit

7 ADDDASEL7

Channel 7 disconnection detection assist method select bit

8 ADDDASEL8

Channel 8 disconnection detection assist method select bit

9 ADDDASEL9

Channel 9 disconnection detection assist method select bit

10 ADDDASEL10

Channel 10 disconnection detection assist method select bit

11 ADDDASEL11

Channel 11 disconnection detection assist method select bit

12 ADDDASEL12

Channel 12 disconnection detection assist method select bit

13 ADDDASEL13

Channel 13 disconnection detection assist method select bit

14 ADDDASEL14

Channel 14 disconnection detection assist method select bit

15 ADDDASEL15

Channel 15 disconnection detection assist method select bit Notes:  This register must always be accessed in halfwords.  For these bits to be enabled, the ADDDAEN bit (A-D Disconnection Detection Assist Function Control Register bit 7) must be set to "1" before setting these bits. In order to prevent the A-D conversion result from being affected by the analog input voltage wrapping around from any preceding channel, the A-D Disconnection Detection Assist Method Select Registers are used to control the conversion start state by selecting whether to discharge or precharge the chopper amp capacitor before starting regular conversion operation.

32180 Group User's Manual (Rev.1.0) Figure 11.2.1 shows an example of A-D disconnection detection assist method in which the conversion start of A-D disconnection detection assist method in which the conversion start state is set to the AVSS side (i.e., discharge before conversion is selected). Figure 11.2.1 Example of A-D Disconnection Detection on AVCC Side (Precharge Before Conversion Selected) Figure 11.2.2 Example of A-D Disconnection Detection on AVSS Side (Discharge Before Conversion Selected) Analog input ADiINn Precharge Broken wire R C Precharge control signal Chopper amp capacitor Discharge control signal Typical external circuit (Note 1) On Off Note 1: In case of broken wire, the conversion result varies with external circuits. Therefore, careful evaluation is required before this function can be used. ADDDAEN Analog input ADiINn Discharge Broken wire R C Precharge control signal Chopper amp capacitor Discharge control signal Typical external circuit (Note 1) Off On Note 1: In case of broken wire, the conversion result varies with external circuits. Therefore, careful evaluation is required before this function can be used. ADDDAEN

32180 Group User's Manual (Rev.1.0) Disconnection detection voltage (without sample-and-hold) 200 400 600 800 1000 1200 1400 1600 1800 2000 0 20 40 60 80 100 120 A-D conversion cycle [kHz] Voltage on disconnected port [mV] Scan mode: Disconnection detection enabled Scan mode: Disconnection detection disabled 2900 3100 3300 3500 3700 3900 4100 4300 4500 4700 4900 5100 0 20 40 60 80 100 120 A-D conversion cycle [kHz] Voltage on disconnected port [mV] Scan mode: Disconnection detection enabled Scan mode: Disconnection detection disabled Disconnection detection voltage (without sample-and-hold) Figure 11.2.3 A-D Disconnection Detection Assist Data (when Discharge Before Conversion Selected) Figure 11.2.4 A-D Disconnection Detection Assist Data (when Precharge Before Conversion Selected)

32180 Group User's Manual (Rev.1.0)

11.2.8 A-D Successive Approximation Registers

A-D0 Successive Approximation Register(AD0SAR) <Address: H ’0080 0088> A-D1 Successive Approximation Register(AD1SAR) <Address: H ’0080 0A88> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 ADSAR <After reset: Undefined> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00 6–15 ADSAR 0: A-D successive approximation value (A-D conversion mode)RW A-D successive approximation value/comparison value1: Comparison value (comparator mode) Note:  This register must always be accessed in halfwords. The A-D Successive Approximation Registers (ADSAR) are used to read the conversion result of the A-D Converters when operating in A-D conversion mode or write a comparison value when operating in comparator mode. In A-D conversion mode, the successive approximation method is used to perform A-D conversion. With this method, the reference voltage VREF and analog input voltages are sequentially compared bitwise beginning with the high-order bit, and the comparison result is set in the A-D Successive Approximation Register (ADSAR) bits 6–15. When the A-D conversion has finished, the value of this register is transferred to the 10-bit A-D Data Register (ADDTn) corresponding to each converted channel. When this register is accessed for read in the middle of A-D conversion, the value read from the register indicates the intermediate result of conversion. In comparator mode, this register is used to write a comparison value (the voltage with which to “comparate”). Simultaneously with a write to this register, the A-D Converter starts comparing the voltage on the analog input pin selected with A-D Single Mode Register 1 and the value written in this register. After comparate operation, the result is stored in the A-D Comparate Data Register (ADCMP). Use the calculation formula shown below to find the comparison value to be written to the A-D Successive Approximation Register (ADSAR) during comparator mode. Comparison value = H’3FF x Comparate comparison voltage [V] VREF input voltage [V]

32180 Group User's Manual (Rev.1.0)

11.2.9 A-D Comparate Data Registers

A-D0 Comparate Data Register (AD0CMP) <Address: H ’0080 008C> A-D1 Comparate Data Register (AD1CMP) <Address: H ’0080 0A8C> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 ADCMP0 ADCMP1 ADCMP2 ADCMP3 ADCMP4 ADCMP6 ADCMP7 ADCMP8 ADCMP9 ADCMP10 ADCMP11 ADCMP12 ADCMP13 ADCMP14 ADCMP15ADCMP5 <After reset: Undefined> b Bit Name Function R W 0–15 ADCMP0 –ADCMP15 (Note 1) 0: Analog input voltage > comparison voltage R – A-D comparate result flag 1: Analog input voltage < comparison voltage Note 1: During comparator mode, the bits in this register correspond one for one to channels 0–15. Note:  This register must always be accessed in halfwords. When comparator mode is selected using the A-D Single Mode Register 1 ADSMSL (A-D conversion mode select) bit, the selected analog input voltage is compared with the value written to the A-D Successive Approxi- mation Register and the result is stored in the corresponding bit of this comparate data register. The bit or flag in this register is "0" when analog input voltage > comparison voltage, or "1" when analog input voltage < comparison voltage.

32180 Group User's Manual (Rev.1.0) 11.2.10 10-bit A-D Data Registers 10-bit A-D0 Data Register 0(AD0DT0) <Address: H ’0080 0090> 10-bit A-D0 Data Register 1(AD0DT1) <Address: H ’0080 0092> 10-bit A-D0 Data Register 2(AD0DT2) <Address: H ’0080 0094> 10-bit A-D0 Data Register 3(AD0DT3) <Address: H ’0080 0096> 10-bit A-D0 Data Register 4(AD0DT4) <Address: H ’0080 0098> 10-bit A-D0 Data Register 5(AD0DT5) <Address: H ’0080 009A> 10-bit A-D0 Data Register 6(AD0DT6) <Address: H ’0080 009C> 10-bit A-D0 Data Register 7(AD0DT7) <Address: H ’0080 009E> 10-bit A-D0 Data Register 8(AD0DT8) <Address: H ’0080 00A0> 10-bit A-D0 Data Register 9(AD0DT9) <Address: H ’0080 00A2> 10-bit A-D0 Data Register 10(AD0DT10) <Address: H ’0080 00A4> 10-bit A-D0 Data Register 11(AD0DT11) <Address: H ’0080 00A6> 10-bit A-D0 Data Register 12(AD0DT12) <Address: H ’0080 00A8> 10-bit A-D0 Data Register 13(AD0DT13) <Address: H ’0080 00AA> 10-bit A-D0 Data Register 14(AD0DT14) <Address: H ’0080 00AC> 10-bit A-D0 Data Register 15(AD0DT15) <Address: H ’0080 00AE> 10-bit A-D1 Data Register 0(AD1DT0) <Address: H ’0080 0A90> 10-bit A-D1 Data Register 1(AD1DT1) <Address: H ’0080 0A92> 10-bit A-D1 Data Register 2(AD1DT2) <Address: H ’0080 0A94> 10-bit A-D1 Data Register 3(AD1DT3) <Address: H ’0080 0A96> 10-bit A-D1 Data Register 4(AD1DT4) <Address: H ’0080 0A98> 10-bit A-D1 Data Register 5(AD1DT5) <Address: H ’0080 0A9A> 10-bit A-D1 Data Register 6(AD1DT6) <Address: H ’0080 0A9C> 10-bit A-D1 Data Register 7(AD1DT7) <Address: H ’0080 0A9E> 10-bit A-D1 Data Register 8(AD1DT8) <Address: H ’0080 0AA0> 10-bit A-D1 Data Register 9(AD1DT9) <Address: H ’0080 0AA2> 10-bit A-D1 Data Register 10(AD1DT10) <Address: H ’0080 0AA4> 10-bit A-D1 Data Register 11(AD1DT11) <Address: H ’0080 0AA6> 10-bit A-D1 Data Register 12(AD1DT12) <Address: H ’0080 0AA8> 10-bit A-D1 Data Register 13(AD1DT13) <Address: H ’0080 0AAA> 10-bit A-D1 Data Register 14(AD1DT14) <Address: H ’0080 0AAC> 10-bit A-D1 Data Register 15(AD1DT15) <Address: H ’0080 0AAE> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 AD0DT0-AD0DT15, AD1DT0-AD1DT15 <After reset: Undefined> b Bit Name Function R W 0–5 No function assigned. 0 – 6–15 AD0DT0-AD0DT15, AD1DT0-AD1DT15 10-bit A-D conversion result R – 10-bit A-D data Note:  This register must always be accessed in halfwords. During single mode, the 10-bit A-D Data Registers are used to store the result of A-D conversion performed on each corresponding channel. During single-shot or continuous scan mode, the content of the A-D Successive Approximation Register is transferred to the 10-bit A-D Data Register for the corresponding channel when A-D conversion on each channel has finished. Each 10-bit A-D Data Register retains the last conversion result until they receive the next conver- sion result transferred, allowing the content to be read out at any time.

32180 Group User's Manual (Rev.1.0) 11.2.11 8-bit A-D Data Registers 8-bit A-D0 Data Register 0(AD08DT0) <Address: H ’0080 00D1> 8-bit A-D0 Data Register 1(AD08DT1) <Address: H ’0080 00D3> 8-bit A-D0 Data Register 2(AD08DT2) <Address: H ’0080 00D5> 8-bit A-D0 Data Register 3(AD08DT3) <Address: H ’0080 00D7> 8-bit A-D0 Data Register 4(AD08DT4) <Address: H ’0080 00D9> 8-bit A-D0 Data Register 5(AD08DT5) <Address: H ’0080 00DB> 8-bit A-D0 Data Register 6(AD08DT6) <Address: H ’0080 00DD> 8-bit A-D0 Data Register 7(AD08DT7) <Address: H ’0080 00DF> 8-bit A-D0 Data Register 8(AD08DT8) <Address: H ’0080 00E1> 8-bit A-D0 Data Register 9(AD08DT9) <Address: H ’0080 00E3> 8-bit A-D0 Data Register 10(AD08DT10) <Address: H ’0080 00E5> 8-bit A-D0 Data Register 11(AD08DT11) <Address: H ’0080 00E7> 8-bit A-D0 Data Register 12(AD08DT12) <Address: H ’0080 00E9> 8-bit A-D0 Data Register 13(AD08DT13) <Address: H ’0080 00EB> 8-bit A-D0 Data Register 14(AD08DT14) <Address: H ’0080 00ED> 8-bit A-D0 Data Register 15(AD08DT15) <Address: H ’0080 00EF> 8-bit A-D1 Data Register 0(AD18DT0) <Address: H ’0080 0AD1> 8-bit A-D1 Data Register 1(AD18DT1) <Address: H ’0080 0AD3> 8-bit A-D1 Data Register 2(AD18DT2) <Address: H ’0080 0AD5> 8-bit A-D1 Data Register 3(AD18DT3) <Address: H ’0080 0AD7> 8-bit A-D1 Data Register 4(AD18DT4) <Address: H ’0080 0AD9> 8-bit A-D1 Data Register 5(AD18DT5) <Address: H ’0080 0ADB> 8-bit A-D1 Data Register 6(AD18DT6) <Address: H ’0080 0ADD> 8-bit A-D1 Data Register 7(AD18DT7) <Address: H ’0080 0ADF> 8-bit A-D1 Data Register 8(AD18DT8) <Address: H ’0080 0AE1> 8-bit A-D1 Data Register 9(AD18DT9) <Address: H ’0080 0AE3> 8-bit A-D1 Data Register 10(AD18DT10) <Address: H ’0080 0AE5> 8-bit A-D1 Data Register 11(AD18DT11) <Address: H ’0080 0AE7> 8-bit A-D1 Data Register 12(AD18DT12) <Address: H ’0080 0AE9> 8-bit A-D1 Data Register 13(AD18DT13) <Address: H ’0080 0AEB> 8-bit A-D1 Data Register 14(AD18DT14) <Address: H ’0080 0AED> 8-bit A-D1 Data Register 15(AD18DT15) <Address: H ’0080 0AEF> 9 1 01 11 21 31 4 b 1 5b8 AD08DT0-AD08DT15, AD18DT0-AD18DT15 <After reset: Undefined> b Bit Name Function R W 8–15 AD08DT0-AD08DT15, AD18DT0-AD18DT15 8-bit A-D conversion result R – 8-bit A-D data During single mode, the 8-bit A-D Data Registers are used to store the result of A-D conversion performed on each corresponding channel. During single-shot or continuous scan mode, the content of the A-D Successive Approximation Register is transferred to the 8-bit A-D Data Register for the corresponding channel when A-D conversion on each channel has finished. Each 8-bit A-D Data Register retains the last conversion result until they receive the next conver- sion result transferred, allowing the content to be read out at any time.

32180 Group User's Manual (Rev.1.0)

11.3.1 How to Find Analog Input Voltages

The A-D Converters perform A-D conversion using a 10-bit successive approximation method as will be de- scribed later. The equation shown below is used to calculate the actual analog input voltage from the digital value obtained by executing A-D conversion. Analog input voltage [v] = A-D conversion result x VREF input voltage [V] 1,024 The A-D Converters are a 10-bit converter, providing a resolution of 1,024 discrete voltage levels. Because the reference voltage for the A-D Converters is the voltage applied to the VREF pin, make sure that an exact and stable constant-voltage power supply is connected to VREF. Also make sure the analog circuit power supply and ground (AVCC, AVSS) are separated from those of the digital circuit, with sufficient noise prevention mea- sures incorporated. For details about the conversion accuracy, see Section 11.3.5, “Accuracy of A-D Conversion.” Figure 11.3.1 Outline Block Diagram of the Successive Approximation-type A-D Converter Unit ADiIN0 ADiIN1 ADiIN2 ADiIN3 ADiIN4 ADiIN5 ADiIN6 ADiIN7 ADiIN8 ADiIN9 ADiIN10 ADiIN11 ADiIN12 ADiIN13 ADiIN14 Selector AVSSi VREFi 10-bit A-Di Successive Approximation Register (ADiSAR) 10-bit A-Di Data Register A-Di Comparate Data Register A-D Control Circuit 10-bit D-A Converter Comparator ADiCMP ADiDT0 –15 Successive Approximation-type A-D Converter Unit AVCCi Vref VIN i = 0, 1 Sample-and-Hold Control Circuit ADiIN15

32180 Group User's Manual (Rev.1.0)

11.3.2 A-D Conversion by Successive Approximation Method

The A-D Converters use an A-D conversion start trigger (software or hardware) as they start A-D conversion. Once A-D conversion begins, the following operation is automatically performed. 1. During single mode, A-D Single Mode Register 0’s A-D conversion/comparate completion bit is cleared to "0". During scan mode, A-D Scan Mode Register 0’s A-D conversion completion bit is cleared to "0". 2. The content of the A-D Successive Approximation Register is cleared to H’0000. 3. The A-D Successive Approximation Register’s most significant bit (bit 6) is set to "1". 4. The comparison voltage, Vref (Note 1), is fed from the D-A Converter into the comparator. 5. The comparison voltage, Vref, and the analog input voltage, VIN, are compared, with the comparison result stored in bit 6. If Vref < VIN, then bit 6 = "1" If Vref > VIN, then bit 6 = "0" 6. Operations in 3 through 5 above are executed for all other bits from bit 7 to bit 15. 7. The value stored in the A-D Successive Approximation Register by the time comparison for bit 15 has finished is held in it as the A-D conversion result. b 6 7 8 9 1 01 11 21 31 4 b 1 5 100000000 0 n 9 10000000 0 n 9 n 8 1000000 0 n9 n8 n7 n6 n5 n4 n3 n2 n1 1 2nd comparison 3rd comparison 10th comparison Conversion com pleted n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 Result of 1st comparison Result of 2nd comparison If Vref > VIN, then nX = 0 If Vref < VIN, then nX = 1 A-D Successive Approximation Register (ADiSAR) i = 0, 1 Figure 11.3.2 Changes of the A-D Successive Approximation Register during A-D Convert Operation Note 1: The comparison voltage, Vref (the voltage fed from the D-A Converter into the comparator), is determined according to changes of the A-D Successive Approximation Register content. Shown below are the equations used to calculate the comparison voltage, Vref.  If the A-D Successive Approximation Register content = 0 Vref [V] = 0  If the A-D Successive Approximation Register content = 1 to 1,023 Vref [V] = (reference voltage VREF / 1,024) × (A-D Successive Approximation Register content – 0.5)

32180 Group User's Manual (Rev.1.0) The conversion result is stored in the 10-bit A-D Data Register (AD0DTn, AD1DTn) corresponding to each converted channel. There is also an 8-bit A-D Data Register (AD08DTn, AD18DTn) for each channel, from which the 8 high-order bits of the 10-bit conversion result can be read out. The following shows the procedure for A-D conversion by a successive approximation method in each operation mode. (1) Single mode The convert operation stops when comparison for the A-D Successive Approximation Register bit 15 is completed. The content (A-D conversion result) of the A-D Successive Approximation Register is transferred to the 10-bit A-D Data Registers 0–15 for the converted channel. (2) Single-shot scan mode When comparison for the A-D Successive Approximation Register bit 15 on a specified channel is completed, the content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Regis- ters 0–15, and the convert operations in steps 2 to 7 above are reexecuted for the next channel to be converted. In single-shot scan mode, the convert operation stops when A-D conversion in one specified scan loop is completed. (3) Continuous scan mode When comparison for the A-D Successive Approximation Register bit 15 on a specified channel is completed, the content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Regis- ters 0–15, and the convert operations in steps 2 to 7 above are reexecuted for the next channel to be converted. In continuous scan mode, the convert operation is executed continuously until scan operation is forcibly termi- nated by setting the A-D conversion stop bit (Scan Mode Register 0 bit 6) to "1".

11.3.3 Comparator Operation

When comparator mode (single mode only) is selected, the A-D Converter functions as a comparator which compares analog input voltages with the comparison voltage that is set by software. When a comparison value is written to the successive approximation register, the A-D Converter starts “comparating” the analog input voltage selected by the Single Mode Register 1 analog input select bit with the value written into the successive approximation register. Once comparate begins, the following operation is automatically executed. 1. The A-D Single Mode Register 0 or A-D Scan Mode Register 0 A-D conversion/comparate completion bit is cleared to "0". 2. The comparison voltage, Vref (Note 1), is fed from the D-A Converter into the comparator. 3. The comparison voltage, Vref, and the analog input voltage, VIN, are compared, with the comparison result stored in the comparate result flag for the corresponding channel. If Vref < VIN, then the comparate result flag = 0 If Vref > VIN, then the comparate result flag = 1 4. The comparate operation is stopped after storing the comparison result. The comparison result is stored in the A-D Comparate Data Register (AD0CMP, AD1CMP)’s corresponding bit. Note 1: The comparison voltage, Vref (the voltage fed from the D-A Converter into the comparator), is determined according to changes of the A-D Successive Approximation Register content. Shown below are the equations used to calculate the comparison voltage, Vref.  If the A-D Successive Approximation Register content = 0 Vref [V] = 0  If the A-D Successive Approximation Register content = 1 to 1,023 Vref [V] = (reference voltage VREF / 1,024) x (A-D Successive Approximation Register content – 0.5)

32180 Group User's Manual (Rev.1.0)

11.3.4 Calculating the A-D Conversion Time

The A-D conversion time is expressed by the sum of dummy cycle time and actual execution cycle time. The following shows each time factor necessary to calculate the conversion time. 1. Start dummy time A time from when the CPU executed the A-D conversion start instruction to when the A-D Converter starts A-D conversion 2. A-D conversion execution cycle time If sample-and-hold is enabled, the sampling time is included in this execution cycle time. 3. Comparate execution cycle time 4. End dummy time A time from when the A-D Converter has finished A-D conversion to when the CPU can stably read out the conversion result from the A-D data register. 5. Scan to scan dummy time A time during single-shot or continuous scan mode from when the A-D Converter has finished A-D conversion on a channel to when it starts A-D conversion on the next channel. The equation to calculate the A-D conversion time is as follows: A-D conversion time = Start dummy time + Execution cycle time (+ Scan to scan dummy time + Execution cycle time + Scan to scan dummy time + Execution cycle time + Scan to scan dummy time .... + Execution cycle time) + End dummy time Note:  Enclosed in ( ) are the conversion time required for the second and subsequent channels to be converted in scan mode. (1) Calculating the conversion time during A-D conversion mode The following schematically shows the method for calculating the conversion time during A-D conversion mode. Start dummy Execution cycle A-D conversion start trigger Convert operation starts Transferred to the A-D data register <Scan mode> End dummy Start dummy Execution cycle Execution cycle <Single mode> Completed Execution cycle End dummy Scan to scan dummy Scan to scan dummy (Channel 0) (Channel 1) (Last channel)Figure 11.3.3 Conceptual Diagram of A-D Conversion Time

32180 Group User's Manual (Rev.1.0) Table 11.3.1 Conversion Clock Periods in A-D Conversion Mode Unit: BCLK Conversion speed Start dummy (N ote 1)Execution cycle End dummy Scan to scan dummy (Note 2) Slow mode Normal speed 4 294 1 4 Double speed 4 168 1 4 Fast mode Normal speed 4 126 1 4 Double speed 4 84 1 4 Note 1: The same applies to both software and hardware triggers. Note 2: Only during scan operation, execution time per channel is added. (2) Calculating the conversion time when sample-and-hold is enabled The following schematically shows the method for calculating the conversion time when the sample-and-hold function is enabled. Start dummy Execution cycle A-D conversion start trigger Convert operation starts End dummy Completed Sampling time Figure 11.3.4 Conceptual Diagram of A-D Conversion Time when Sample-and-Hold is Enabled Table 11.3.2 Conversion Clock Periods during Normal Sample-and-Hold Mode Unit: BCLK Conversion speed Start dummy (N ote 1)Execution cycle End dummy Scan to scan dummy (Note 2) Slow mode Normal speed 4 294 1 4 Double speed 4 168 1 4 Fast mode Normal speed 4 126 1 4 Double speed 4 84 1 4 Note 1: The same applies to both software and hardware triggers. Note 2: Only during scan operation, execution time per channel is added. Table 11.3.3 Conversion Clock Periods during Fast Sample-and-Hold Mode Unit: BCLK Conversion speed Start dummy (N ote 1)Execution cycle End dummy Scan to scan dummy (Note 2) Slow mode Normal speed 4 186 1 4 Double speed 4 96 1 4 Fast mode Normal speed 4 90 1 4 Double speed 4 48 1 4 Note 1: The same applies to both software and hardware triggers. Note 2: Only during scan operation, execution time per channel is added.

32180 Group User's Manual (Rev.1.0) Start dummy Execution cycle A-D conversion start trigger Convert operation starts Transferred to the comparate data register End dummy Completed Figure 11.3.5 Conceptual Diagram of A-D Conversion Time during Comparator Mode Table 11.3.4 Conversion Clock Periods during Comparator Mode Unit: BCLK Conversion speed Start dummy Execution cycle End dummy Slow mode Normal speed 4 42 1 Double speed 4 24 1 Fast mode Normal speed 4 18 1 Double speed 4 12 1 (4) A-D conversion time A total A-D conversion time in various modes are shown in the table below. Table 11.3.5 A-D Conversion Time (Total Time) Unit: BCLK Conversion start method Conversion speed Conversion mode (Note 1) Conversion time When fast sample- and-hold enabled Software and Normal speed Single mode 299 191 hardware triggers n-channel single-shot scan/ (298 × n)+1 (190 × n)+1 (Note 2) continuous scan mode Slow Comparator mode 47 47 Mode Double speed Single mode 173 101 n-channel single-shot scan/ (172 × n)+1 (100 × n)+1 continuous scan mode Comparator mode 29 29 Normal speed Single mode 131 95 n-channel single-shot scan/ (130 × n)+1 (94 × n)+1 continuous scan mode Fast Comparator mode 23 23 Mode Double speed Single mode 89 53 n-channel single-shot scan/ (88 × n)+1 (52 × n)+1 continuous scan mode Comparator mode 17 17 Note 1: For single mode and comparator mode, this indicates an A-D conversion or comparate time per channel. For single- shot and continuous scan modes, this indicates an A-D conversion time per scan loop. Note 2: This indicates a time from when a register write cycle has finished to when an A-D conversion completion interrupt request is generated, or a time from when an event bus or other MJT event has occurred to when an A-D conversion completion interrupt request is generated. (3) Calculating the conversion time during comparator mode The following schematically shows the method for calculating the conversion time during comparator mode.

32180 Group User's Manual (Rev.1.0)

11.3.5 Accuracy of A-D Conversion

The accuracy of the A-D Converters is indicated by an absolute accuracy. The absolute accuracy refers to a difference expressed by LSB between the output code obtained by A-D converting the analog input voltages and the output code expected for an A-D converter with ideal characteristics. The analog input voltages used during accuracy measurement are the midpoint values of the voltage width in which an A-D converter with ideal char- acteristics produces the same output code. If VREF = 5.12 V, for example, the width of 1 LSB for a 10-bit A-D converter is 5 mV, so that 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, 25 mV and so on are selected as midpoints of the analog input voltage. If an A-D converter is said to have the absolute accuracy of ±2 LSB, it means that if the input voltage is 25 mV, for example, the output code expected for an A-D converter with ideal characteristics is H’005, and the actual A- D conversion result is in the range of H’003 to H’007. Note that the absolute accuracy includes zero and full- scale errors. When actually using the A-D Converters, the analog input voltages are in the range of AVSS to VREF. Note, however, that low VREF voltages result in a poor resolution. Note also that output codes for the analog input voltages from VREF to AVCC are always H’3FF. H'000 H'001 H'002 H'003 H'3FE H'3FF A-D conv ersion res ult (hexade cimal) → Analog input voltage [V] VREF 1024 × 1 Ideal A-D conversion characteristics A-D conversion characteristics with infinite resolution

0 VREF

1024 × 2 VREF 1024 × 3 VREF 1024 × 1022 VREF 1024 × 1023 VREF 1024 × 1024 Figure 11.3.6 Ideal A-D Conversion Characteristics Relative to the 10-bit A-D Converter’s Analog Input Voltages

32180 Group User's Manual (Rev.1.0) H'000 H'001 H'002 H'003 H'004 H'005 H'006 Output code (he xadecimal) → Analog input voltage [mV] Ideal A-D conversion characteristics A-D conversion characteristics with infinite resolution 5 1 01 52 02 53 03 54 04 55 05 5 H'007 H'008 H'009 H'00A H'00B +2 LSB -2 LSB Figure 11.3.7 Absolute Accuracy of A-D Converters

32180 Group User's Manual (Rev.1.0) If when the A-D Converter is A-D converting a selected analog input an overvoltage exceeding the converter’s absolute maximum rating is applied to any unselected analog input, the selector for the unselected analog input is inadvertently turned on by that overvoltage. This causes current to wrap around to the selected analog input, and the accuracy of the A-D conversion result is thereby deteriorated. The Inflow Current Bypass Circuit fixes the internal signals of unselected analog inputs to the GND level, so that when an overvoltage is applied, this circuit lets the current flow into the GND and prevents it from wrapping around to the selected analog input. That way, the accuracy of the A-D conversion result is prevented from being deterio- rated by extreme voltages. This circuit is always active while the A-D Converter is operating, and does not need to be controlled in software. Unselected channel Selected channel To the internal logic of the A-D Converter OFF ON OFF ON ON OFF Fixed to GND level External input latched into Assist circuit Figure 11.4.1 Configuration of the Inflow Current Bypass Circuit Figure 11.4.2 Example of an Inflow Current Bypass Circuit where VCCE + 0.7 V or More is Applied Unselected channel Selected channel To the internal logic of the A-D Converter OFF ON OFF ON ON OFF Assist circuit VCCE + 0.7 V or more Leakage current generated Sensor input Leakage current generated Unaffected by leakage

32180 Group User's Manual (Rev.1.0) Figure 11.4.3 Example of an Inflow Current Bypass Circuit where GND – 0.7 V or Less is Applied Table 11.4.1 Accuracy Errors (Actual Performance Values) when Current is Injected into AD0IN0 Note 1: The conversion accuracy is not affected unless the injection current is greater than 1 mA. Unselected channel Selected channel To the internal logic of the A-D Converter OFF ON OFF ON ON OFF Assist circuit GND - 0.7V or less Leakage current generated Sensor input Unaffected by leakage Leakage current generated AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 1 0 m A 000000000000000 9 m A 000000000000000 8 m A 000000000000000 7 m A 000000000000000 6 m A 000000000000000 5 m A 000000000000000 4 m A 000000000000000 3 m A 000000000000000 2 m A 000000000000000 1 m A 000000000000000 0 m A 000000000000000 - 1 m A 000000000000000 - 2 m A - 100000000000000 - 3 m A - 100000000000000 - 4 m A - 100000000000000 - 5 m A - 2 - 10000000000000 - 6 m A - 3 - 10000000000000 - 7 m A - 3 - 10000000000000 - 8 m A - 3 - 10000000000000 - 9 m A - 4 - 10000000000000 - 1 0 m A - 5 - 10000000000000 Accuracy error on overcurrent injected ports (Unit: LSB) Analog input pin Injection current (Note 1) /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 /i0 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32180 Group User's Manual (Rev.1.0) Figure 11.5.1 Internal Equivalent Circuit of the Analog Input Part  Forcible termination during scan operation If A-D conversion is forcibly terminated by setting the A-D conversion stop bit (AD0CSTP or AD1CSTP) to "1" during scan mode operation and the A-D data register for the channel that was in the middle of conversion is accessed for read, the read value shows the last conversion result that had been transferred to the data register before the conversion was forcibly terminated.  Modification of the A-D converter related registers If the content of any register— A-D Conversion Interrupt Control Register, Single or Scan Mode Registers or A-D Successive Approximation Register, except the A-D conversion stop bit— is modified in the middle of A-D conver- sion, the conversion result cannot be guaranteed. Therefore, do not modify the contents of these registers while A- D conversion is in progress, or be sure to restart A-D conversion if register contents have been modified.  Handling of analog input signals When using the A-D Converter with its sample-and-hold function disabled, make sure the analog input level is fixed during A-D conversion.  A-D conversion completed bit read timing To read the A-D conversion completed bit (Single Mode Register 0 bit 5 or Scan Mode Register 0 bit 5) immediately after A-D conversion has started, be sure to adjust the timing 2 BCLK periods by, for example, inserting a NOP instruction before read.  Regarding the analog input pins Figure 11.5.1 shows the internal equivalent circuit of the A-D Converter’s analog input part. To obtain accurate A-D conversion results, make sure the internal capacitor C2 of the A-D conversion circuit is charged up within a predetermined time (sampling time). To meet this sampling time requirement, it is recommended that a stabiliz- ing capacitor C1 be connected external to the chip. The method for determining the necessary value of this external stabilizing capacitor with respect to the output impedance of an analog output device is described below. Also, an explanation is made of the case where the output impedance of an analog output device is low and the external stabilizing capacitor C1 is unnecessary.  Rated value of the absolute accuracy The rated value of the absolute accuracy is the actual performance value of the microcomputer alone, with influences of the power supply wiring and noise on the board not taken into account. When designing the application system, use caution for the board layout by, for example, separating the analog circuit power supply and ground (AVCC, AVSS and VREF) from those of the digital circuit and incorporating measures to prevent the analog input pins from being affected by noise, etc. from other digital signals. Approximation Register (ADiSAR) 10-bit D-A ConverterVREF V2 Cin : input pin capacitance (approx. 10 pF) R2 : parasitic resistance of the selector (1-2 KΩ) C2 : comparator capacitance (approx. 2.9 pF) Selector R2i i1i2→ ADIN n C1E C1 : parasitic capacitance of the board + stabilizing capacitance R1 : resistance of analog output device Analog output device Cin E : voltage of analog output device V2 : voltage across C2 VREF : analog reference voltage

32180 Group User's Manual (Rev.1.0) Thus, for 10-bit resolution A-D converters where C2 = 2.9 pF, C1 is 0.06 µF or more. Use this value for reference when setting up C1. (b) Maximum value of the output impedance R1 when C1 is not added If the external capacitor C1 in Figure 11.5.1 is not used, examination must be made to see if the analog input device can fully charge C2 within a predetermined time. First, the equation to find i2 when C1 in Figure 11.5.1 does not exist is shown below. Cin×R1+C2(R1+R2) Cin×R1+C2(R1+R2) (a) Example for calculating the external stabilizing capacitor C1 (addition of this capacitor is recommended) Assuming the R1 in Figure 11.5.1 is infinitely large and that the current necessary to charge the internal capacitor C2 is supplied from C1, if the potential fluctuation, Vp, caused by capacitance division of C1 and C2 is to be within 0.1 LSB, then what amount of capacitance C1 should have. For 10-bit A-D converters where VREF is 5.12 V, 1 LSB determination voltage = 5.12 V / 1,024 = 5 mV. The potential fluctuation of 0.1 LSB means a 0.5 mV fluctuation. Vp is also obtained by the equation below: The relationship between the capacitance division of C1 and C2 and the potential fluctuation, Vp, is obtained by the equation below: C1 + C2Vp = × (E - V2) Eq. A-1 2Vp = Vp1 × < Eq. A-2i VREF 10 × 2× x - 1 i = 0 where Vp1 = potential fluctuation in the first A-D conversion performed and x = 10 for a 10-bit resolution A-D converter When Eq. A-1 and Eq. A-2 are solved, the following results: E - V2 Vp1C1 = C2 { - 1 } Eq. A-3 x - 1 i = 0 ADINi Conversion time for the first bit Sampling time Comparison time Repeated (10 times) for 10 bits Second bit Sampling time When sample-and-hold is disabled * When sample-and-hold is enabled, the analog input is sampled for only the first bit. Figure 11.5.2 A-D Conversion Timing Diagram Figure 11.5.2 shows an A-D conversion timing diagram. C2 must be charged up within the sampling time shown in this diagram. When the sample-and-hold function is disabled, the sampling time for the second and subsequent bits is about half that of the first bit. The sampling times at the respective conversion speeds are listed in the table 11.5.1. Note that when the sample-and-hold function is enabled, the analog input is sampled for only the first bit.

32180 Group User's Manual (Rev.1.0) Table 11.5.1 Sampling Time (in Which C2 Needs to Be Charged) Conversion start method Conversion speed Sampling time for the first bit Sampling time for the second and subsequent bits Single mode Slow mode Normal speed 27. 5BCLK 13.5BCLK (when sample-and Double speed 15.5BCLK 7.5BCLK -hold disabled) Fast mode Normal speed 11. 5BCLK 5.5BCLK Double speed 7.5BCLK 3.5BCLK Single mode Slow mode Normal speed 27. 5BCLK – (when sample-and Double speed 15.5BCLK – -hold enabled) Fast mode Normal speed 11. 5BCLK – Double speed 7.5BCLK – Comparator mode Slow mode Normal speed 27. 5BCLK – Double speed 15.5BCLK – Fast mode Normal speed 11.5BCLK – Double speed 7.5BCLK – Therefore, the time in which C2 needs to be charged is found from Eq. B-1, as follows: Sampling time (in which C2 needs to be charged) > Cin × R1 + C2(R1 + R2) --- Eq. B2 Thus, the maximum value of R1 can be obtained as a criterion from the equation below. Note, however, that for single mode (when sample-and-hold is disabled), the sampling time for the second and subsequent bits (C2 charging time) must be applied. C2 charging time - C2 × R2 R1 < Cin + C2

32180 Group User's Manual (Rev.1.0) This page is blank for reasons of layout.

12.1 Outline of Serial I/O

12.2 Serial I/O Related Registers

12.3 Transmit Operation in CSIO Mode

12.4 Receive Operation in CSIO Mode

12.5 Precautions on Using CSIO Mode

12.6 Transmit Operation in UART Mode

12.7 Receive Operation in UART Mode

12.8 Fixed Period Clock Output Function

12.9 Precautions on Using UART Mode

32180 Group User's Manual (Rev.1.0) The 32180 contains a total of six serial I/O channels, SIO0–SIO5. Channels SIO0, SIO1, SIO4 and SIO5 can be selected between CSIO mode (clock-synchronous serial I/O) and UART mode (clock-asynchronous serial I/O). Channels SIO2 and SIO3 are UART mode only.

• CSIO mode (clock-synchronous serial I/O) Communication is performed synchronously with a transfer clock, using the same clock on both transmit and receive sides. The transfer data is 8 bits long (fixed).  UART mode (clock-asynchronous serial I/O) Communication is performed at any transfer rate in any transfer data format. The transfer data length can be selected from 7, 8 and 9 bits. Channels SIO0–SIO3 each have a transmit DMA transfer and a receive DMA transfer request. These serial I/Os, when combined with the internal DMA Controller (DMAC), allow serial communication to be performed at high speed, as well as reduce the data communication load of the CPU. Serial I/O is outlined below. Table 12.1.1 Outline of Serial I/O Item Description Number of channels CSIO mode/UART mode : 4 channels (SIO0, SIO1, SIO4, SIO5) UART only : 2 channels (SIO2, SIO3) Clock During CSIO mode : Internal clock or external clock as selected (Note 1) During UART mode : Internal clock only Transfer mode Transmit half-duplex, receive half-duplex, transmit/receive full-duplex BRG count source f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BLCK)/256 (Note 2) (when internal clock selected) f(BCLK): Peripheral clock operating frequency Data format CSIO mode : Data length = 8 bits (fixed) Order of transfer = LSB first (fixed) UART mode : Start bit = 1 bit Character length = 7, 8 or 9 bits Parity bit = Added (odd, even) or not added Stop bit = 1 or 2 bits Order of transfer = LSB first (fixed) Baud rate CSIO mode : 152 bits/sec to 2 Mbits/sec (when f(BCLK) = 20 MHz) UART mode : 19 bits/sec to 156 Kbits/sec (when f(BCLK) = 20 MHz) Error detection CSIO mode : Overrun error only UART mode : Overrun, parity and framing errors (Occurrence of any of these errors is indicated by an error sum bit) Fixed period clock output function When using SIO0, SIO1, SIO4 and SIO5 as UART, this function outputs a divided-by-2 BRG clock from the SCLK pin. Note 1: The maximum input frequency of an external clock during CSIO mode is f(BCLK)/16. Note 2: If f(BCLK) is selected as the count source, the BRG set value is subject to limitations.

32180 Group User's Manual (Rev.1.0) Table 12.1.2 Interrupt Generation Functions of Serial I/O Serial I/O Interrupt Request Source ICU Interrupt Sources SIO0 transmit buffer empty or transmission finished SIO0 transmit interrupt SIO0 reception finished or receive error SIO0 receive interrupt SIO1 transmit buffer empty or transmission finished SIO1 transmit interrupt SIO1 reception finished or receive error SIO1 receive interrupt SIO2 transmit buffer empty or transmission finished SIO2,3 transmit/receive interrupt (group interrupt) SIO2 reception finished or receive error SIO2,3 transmit/receive interrupt (group interrupt) SIO3 transmit buffer empty or transmission finished SIO2,3 transmit/receive interrupt (group interrupt) SIO3 reception finished or receive error SIO2,3 transmit/receive interrupt (group interrupt) SIO4 transmit buffer empty or transmission finished SIO4,5 transmit/receive interrupt (group interrupt) SIO4 reception finished or receive error SIO4,5 transmit/receive interrupt (group interrupt) SIO5 transmit buffer empty or transmission finished SIO4,5 transmit/receive interrupt (group interrupt) SIO5 reception finished or receive error SIO4,5 transmit/receive interrupt (group interrupt) Note:  The transmission-finished interrupt is effective when the internal clock is selected in UART or CSIO mode. Table 12.1.3 DMA Transfer Request Generation Functions of Serial I/O Serial I/O DMA Transfer Request DMAC Input Channels SIO0 transmit buffer empty DMA3, DMA4 SIO0 reception finished DMA4 SIO1 transmit buffer empty DMA6 SIO1 reception finished DMA6, DMA3 SIO2 transmit buffer empty DMA7 SIO2 reception finished DMA5 SIO3 transmit buffer empty DMA7, DMA9 SIO3 reception finished DMA8

32180 Group User's Manual (Rev.1.0) SCLKI0/SCLKO0 BCLK, BCLK/8, BCLK/32, BCLK/256 Baud Rate Generator (BRG) BCLK (set value + 1) Interna l data busCSIO mode When internal clock selected CSIO mode UART mode When internal clock selected Clock Divider RXD0 TXD0 Receive interrupt request Transmit/ Receive Control Circuit SIO0 Transmit Buffer Register SIO0 Transmit Shift Register Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request To DMA3, DMA4SIO0 Receive Shift Register SIO0 Receive Buffer Register When external clock selected When UART mode selected Notes:  When BCLK is selected, the BRG set value is subject to limitations.  SIO2 and SIO3 do not have the SCLKI/SCLKO function. SCLKI1/SCLKO1 To DMA6 To the Interrupt Controller (ICU) SIO0 SIO1 SIO2 SIO3 RXD1 TXD1 Transmit/ Receive Control Circuit SIO1 Transmit Shift Register SIO1 Receive Shift Register To DMA7RXD2 TXD2 Transmit/ Receive Control Circuit SIO2 Transmit Shift Register SIO2 Receive Shift Register To DMA7, DMA9 RXD3 TXD3 Transmit/ Receive Control Circuit SIO3 Transmit Shift Register SIO3 Receive Shift Register Receive interrupt request Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request Receive interrupt request Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request Receive interrupt request Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request To the Interrupt Controller (ICU) To DMA8 To DMA5 To DMA3, DMA6 To DMA4 SIO4 RXD4 TXD4 Transmit/ Receive Control Circuit SIO4 Transmit Shift Register SIO4 Receive Shift Register Receive interrupt request Transmit interrupt request SIO5 RXD5 TXD5 Transmit/ Receive Control Circuit SIO5 Transmit Shift Register SIO5 Receive Shift Register Receive interrupt request Transmit interrupt request SCLKI4/SCLKO4 SCLKI5/SCLKO5 To the Interrupt Controller (ICU) To the Interrupt Controller (ICU) Figure 12.1.1 Block Diagram of SIO0–SIO5

32180 Group User's Manual (Rev.1.0) Shown below is a serial I/O related register map. Serial I/O Related Register Map Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0100 SIO23 Interrupt Request Status Register SIO03 Interrupt Request Enable Register 12-9 (SI23STAT) (SI03EN) 12-10 H'0080 0102 SIO03 Interrupt Source Select Register (Use inhibited area) 12-11 (SI03SEL) | (Use inhibited area) H'0080 0110 SIO0 Transmit Control Register SIO0 Transmit/Receive Mode Register 12-14 (S0TCNT) (S0MOD) 12-15 H'0080 0112 SIO0 Transmit Buffer Register 12-18 (S0TXB) H'0080 0114 SIO0 Receive Buffer Register 12-19 (S0RXB) H'0080 0116 SIO0 Receive Control Register SIO0 Baud Rate Register 12-20 (S0RCNT) (S0BAUR) 12-23 | (Use inhibited area) H'0080 0120 SIO1 Transmit Control Register SIO1 Transmit/Receive Mode Register 12-14 (S1TCNT) (S1MOD) 12-15 H'0080 0122 SIO1 Transmit Buffer Register 12-18 (S1TXB) H'0080 0124 SIO1 Receive Buffer Register 12-19 (S1RXB) H'0080 0126 SIO1 Receive Control Register SIO1 Baud Rate Register 12-20 (S1RCNT) (S1BAUR) 12-23 | (Use inhibited area) H'0080 0130 SIO2Transmit Control Register SIO2 Transmit/Receive Mode Register 12-14 (S2TCNT) (S2MOD) 12-15 H'0080 0132 SIO2 Transmit Buffer Register 12-18 (S2TXB) H'0080 0134 SIO2 Receive Buffer Register 12-19 (S2RXB) H'0080 0136 SIO2 Receive Control Register SIO2 Baud Rate Register 12-20 (S2RCNT) (S2BAUR) 12-23 | (Use inhibited area) H'0080 0140 SIO3 Transmit Control Register SIO3 Transmit/Receive Mode Register 12-14 (S3TCNT) (S3MOD) 12-15 H'0080 0142 SIO3 Transmit Buffer Register 12-18 (S3TXB) H'0080 0144 SIO3 Receive Buffer Register 12-19 (S3RXB) H'0080 0146 SIO3 Receive Control Register SIO3 Baud Rate Register 12-20 (S3RCNT) (S3BAUR) 12-23 H'0080 0A00 SIO45 Interrupt Request Status Register SIO45 Interrupt Request Enable Register 12-9 (SI45STAT) (SI45EN) 12-10 H'0080 0A02 SIO45 Interrupt Source Select Register (Use inhibited area) 12-11 (SI45SEL) | (Use inhibited area) H'0080 0A10 SIO4 Transmit Control Register SIO4 Transmit/Receive Mode Register 12-14 (S4TCNT) (S4MOD) 12-15 H'0080 0A12 SIO4 Transmit Buffer Register 12-18 (S4TXB) H'0080 0A14 SIO4 Receive Buffer Register 12-19 (S4RXB) H'0080 0A16 SIO4 Receive Control Register SIO4 Baud Rate Register 12-20 (S4RCNT) (S4BAUR) 12-23 | (Use inhibited area) H'0080 0A20 SIO5 Transmit Control Register SIO5 Transmit/Receive Mode Register 12-14 (S5TCNT) (S5MOD) 12-15 H'0080 0A22 SIO5 Transmit Buffer Register 12-18 (S5TXB) H'0080 0A24 SIO5 Receive Buffer Register 12-19 (S5RXB) H'0080 0A26 SIO5 Receive Control Register SIO5 Baud Rate Register 12-20 (S5RCNT) (S5BAUR) 12-23

32180 Group User's Manual (Rev.1.0)

12.2.1 SIO Interrupt Related Registers

The SIO interrupt related registers are used to control the interrupt request signals output from SIO to the Interrupt Controller (ICU), as well as select the source of each interrupt request. (1) Interrupt request status bit This status bit is used to determine whether an interrupt is requested. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this bit is unaffected by the interrupt request enable bit, it can also be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request enable bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "1" to enable interrupt requests or "0" to disable interrupt requests. Figure 12.2.1 Interrupt Request Status and Enable Registers To the Interrupt Controller Interrupt request from each peripheral function Interrupt request status Data bus Set  Group interrupt Interrupt request enable clear F/F F/F Data=0

32180 Group User's Manual (Rev.1.0) Figure 12.2.2 Example for Clearing Interrupt Request Status b4 5 b7 Interrupt request status Initial state Bit 6 event occurs Interrupt request Bit 4 event occurs Only bit 6 cleared Bit 4 data retained b4 5 b7 1 1 0 1 Write to the interrupt request status Example for clearing interrupt request status 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 Program example ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */  To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1: ISTAT1 (0x02 bit) To clear an interrupt request status, always be sure to write 1 to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. b4 5 6 b7 Interrupt request status Bit 6 event occurs Bit 4 event occurs Only bit 6 cleared Bit 4 also cleared 0 0 1 0 1 0 1 0 0 0 0 0 Read 0 0 1 0 0 0 0 0 Clear bit 6 (ANDing with 1101) Write ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */

32180 Group User's Manual (Rev.1.0) Receive DMA transfer request RFIN (Reception Finished bit) Note:  No reception-finished DMA transfer requests are generated if a receive error occurs. Figure 12.2.4 Reception-finished DMA Transfer Request (3) Selecting the source of an interrupt request The interrupt request signals sent from each SIO to the Interrupt Controller (ICU) are broadly classified into transmit interrupts and receive interrupts. Transmit interrupt requests can be generated when the transmit buffer is empty or transmission is finished, and the receive interrupt requests can be generated when recep- tion is finished or an receive error is detected, as selected by the Interrupt Source Select Registers (SI03SEL, SI45SEL). Notes:  No interrupt request signals are generated unless interrupts are generated by the SIO Interrupt Request Enable Register after enabling the TEN (Transmit Enable) bit or REN (Receive Enable) bit for the corresponding SIO.  SIO2 and SIO3 together comprise one interrupt group, so do SIO4 and SIO5.  The transmission-finished interrupt is effective when the internal clock is selected in UART or CSIO mode. (4) Notes on using transmit interrupts While the SIO Interrupt Request Enable Register is set to enable interrupts, a transmit interrupt request is generated upon enabling the corresponding TEN (Transmit Enable) bit. (5) About DMA transfer requests from SIO Each SIO can generate a transmit DMA transfer and a reception-finished DMA transfer request. These DMA transfer requests can be generated by enabling each SIO’s corresponding TEN (Transmit Enable) bit or REN (Receive Enable) bit. When using DMA transfers to communicate with external devices, be sure to set the DMA Controller (DMAC) before enabling the TEN or REN bit. No reception-finished DMA transfer requests are generated if a receive error occurs.  Transmit DMA transfer request Generated when the transmit buffer is empty and the TEN bit is enabled. TEN (Transmit Enable bit) TBE (Transmit Buffer Empty bit) Transmit DMA transfer request Figure 12.2.3 Transmit DMA Transfer Request  Reception-finished DMA transfer request A DMA transfer request is generated when the receive buffer is filled.

32180 Group User's Manual (Rev.1.0) SIO23 Interrupt Request Status Register (SI23STAT) <Address: H ’0080 0100> 123456 b 7b0 IRQT2 IRQR3 IRQT3IRQR2 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00

4 IRQT2 0: Interrupt not requested R (Note 1)

SIO2 transmit interrupt request status bit 1: Interrupt requested

5 IRQR2 0: Interrupt not requested R (Note 1)

SIO2 receive interrupt request status bit 1: Interrupt requested

6 IRQT3 0: Interrupt not requested R (Note 1)

SIO3 transmit interrupt request status bit 1: Interrupt requested

7 IRQR3 0: Interrupt not requested R (Note 1)

SIO3 receive interrupt request status bit 1: Interrupt requested Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. SIO45 Interrupt Request Status Register (SI45STAT) <Address: H ’0080 0A00> 123456 b 7b0 IRQT4 IRQR5 IRQT5IRQR4 0000 0 0 0 0 <After reset: H’00> b Bit Name Function R W

0 IRQT4 0: Interrupt not requested R (Note 1)

SIO4 transmit interrupt request status bit 1: Interrupt requested

1 IRQR4 0: Interrupt not requested R (Note 1)

SIO4 receive interrupt request status bit 1: Interrupt requested

2 IRQT5 0: Interrupt not requested R (Note 1)

SIO5 transmit interrupt request status bit 1: Interrupt requested

3 IRQR5 0: Interrupt not requested R (Note 1)

SIO5 receive interrupt request status bit 1: Interrupt requested 4–7 No function assigned. Fix to "0". 00 Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. These registers indicate the transmit/receive interrupt requests from each SIO. [Setting the interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the interrupt request status bit] This bit is cleared by writing "0" in software. Note:  If the status bit is set in hardware at the same time it is cleared in software, the former has priority and the status bit is set. When writing to the SIO Interrupt Request Status Register, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write.

32180 Group User's Manual (Rev.1.0) SIO03 Interrupt Request Enable Register (SI03EN) <Address: H ’0080 0101> 9 1 01 11 21 31 4 b 1 5b8 T0EN R0EN T1EN R1EN T2EN R2EN T3EN R3EN 00000000 <After reset: H’00> b Bit Name Function R W

8 T0EN 0: Mask (disable) interrupt request R W

SIO0 transmit interrupt request enable bit 1: Enable interrupt request

9 R0EN 0: Mask (disable) interrupt request R W

SIO0 receive interrupt request enable bit 1: Enable interrupt request

10 T1EN 0: Mask (disable) interrupt request R W

SIO1 transmit interrupt request enable bit 1: Enable interrupt request

11 R1EN 0: Mask (disable) interrupt request R W

SIO1 receive interrupt request enable bit 1: Enable interrupt request

12 T2EN 0: Mask (disable) interrupt request R W

SIO2 transmit interrupt request enable bit 1: Enable interrupt request

13 R2EN 0: Mask (disable) interrupt request R W

SIO2 receive interrupt request enable bit 1: Enable interrupt request

14 T3EN 0: Mask (disable) interrupt request R W

SIO3 transmit interrupt request enable bit 1: Enable interrupt request

15 R3EN 0: Mask (disable) interrupt request R W

SIO3 receive interrupt request enable bit 1: Enable interrupt request SIO45 Interrupt Request Enable Register (SI45EN) <Address: H ’0080 0A01> 9 1 01 11 21 31 4 b 1 5b8 T4EN R5EN T5ENR4EN 0000 0 0 0 0 <After reset: H’00> b Bit Name Function R W

8 T4EN 0: Mask (disable) interrupt request R W

SIO4 transmit interrupt request enable bit 1: Enable interrupt request

9 R4EN 0: Mask (disable) interrupt request R W

SIO4 receive interrupt request enable bit 1: Enable interrupt request

10 T5EN 0: Mask (disable) interrupt request R W

SIO5 transmit interrupt request enable bit 1: Enable interrupt request

11 R5EN 0: Mask (disable) interrupt request R W

SIO5 receive interrupt request enable bit 1: Enable interrupt request 12–15 No function assigned. Fix to "0". 00 These registers enable or disable the interrupt requests generated by each SIO. Interrupt requests from any SIO are enabled by setting its corresponding interrupt request enable bit to "1".

32180 Group User's Manual (Rev.1.0) SIO03 Interrupt Source Select Register (SI03EN) <Address: H ’0080 0102> 123456 b 7b0 ISR0IST0 IST1 IST2 IST3 ISR3 ISR2ISR1 00000000 <After reset: H’00> b Bit Name Function R W

0 IST0 0: Transmit buffer empty interrupt R W

SIO0 transmit interrupt request source select bit 1: Transmission finished interrupt

1 IST1 0: Transmit buffer empty interrupt R W

SIO1 transmit interrupt request source select bit 1: Transmission finished interrupt

2 IST2 0: Transmit buffer empty interrupt R W

SIO2 transmit interrupt request source select bit 1: Transmission finished interrupt

3 IST3 0: Transmit buffer empty interrupt R W

SIO3 transmit interrupt request source select bit 1: Transmission finished interrupt

4 ISR0 0: Reception finished interrupt R W

SIO0 receive interrupt request source select bit 1: Receive error interrupt

5 ISR1 0: Reception finished interrupt R W

SIO1 receive interrupt request source select bit 1: Receive error interrupt

6 ISR2 0: Reception finished interrupt R W

SIO2 receive interrupt request source select bit 1: Receive error interrupt

7 ISR3 0: Reception finished interrupt R W

SIO3 receive interrupt request source select bit 1: Receive error interrupt SIO45 Interrupt Source Select Register (SI45SEL) <Address: H ’0080 0A02> 123456 b 7b0 ISR4IST4 IST5 ISR 5 00 00 0 0 0 0 <After reset: H’00> b Bit Name Function R W

0 IST4 0: Transmit buffer empty interrupt R W

SIO4 transmit interrupt request source select bit 1: Transmission finished interrupt

1 IST5 0: Transmit buffer empty interrupt R W

SIO5 transmit interrupt request source select bit 1: Transmission finished interrupt 2, 3 No function assigned. Fix to "0". 00

4 ISR4 0: Reception finished interrupt R W

SIO4 receive interrupt request source select bit 1: Receive error interrupt

5 ISR5 0: Reception finished interrupt R W

SIO5 receive interrupt request source select bit 1: Receive error interrupt 6, 7 No function assigned. Fix to "0". 00 These registers select the source of interrupt requests generated by each SIO when transmit or receive opera- tion is completed.

32180 Group User's Manual (Rev.1.0) (1) SIOn transmit interrupt request source select bit [When set to "0"] The transmit buffer empty interrupt is selected. A transmit buffer empty interrupt request is generated when data is transferred from the transmit buffer register to the transmit shift register. Also, a transmit buffer empty interrupt request is generated when the TEN (Transmit Enable) bit is set to "1" (interrupt enabled). [When set to "1"] The transmission finished (transmit shift buffer empty) interrupt is selected. A transmission finished interrupt request is generated when all of the data in the transmit shift register has been transferred. Note:  Do not select the transmission finished interrupt when an external clock is selected in CSIO mode. (2) SIOn receive interrupt request source select bit [When set to "0"] The reception finished (receive buffer full) interrupt is selected. A reception finished interrupt request is also generated when a receive error (except overrun error) occurs. [When set to "1"] The receive error interrupt is selected. Following types of errors constitute a receive error:  CSIO mode: Overrun error  UART mode: Overrun, parity and framing errors

32180 Group User's Manual (Rev.1.0) Figure 12.2.5 Block Diagram of SIO2,3 Transmit Interrupt Requests Figure 12.2.6 Block Diagram of SIO4,5 Transmit Interrupt Requests F/F F/F R3EN IRQR3 F/F F/F T3EN IRQT3 F/F F/F R2EN IRQR2 F/F F/F T2EN IRQT2 b15 b14 b13 b12 Data bus SIO2, 3 transmit/receive interrupt requests(Level) 4-source inputs <SI23STAT : H'0080 0100> <SI03EN : H'0080 0101> F/F SIO2 reception finished SIO2 receive error ISR2 F/F SIO2 transmit buffer empty SIO2 transmission finished IST2 F/F SIO3 transmit buffer empty SIO3 transmission finished IST3 F/F SIO3 reception finished SIO3 receive error ISR3 <SI03SEL : H'0080 0102> F/F F/F R5EN IRQR5 F/F F/F T5EN IRQT5 F/F F/F R4EN IRQR4 F/F F/F T4EN IRQT4 b11 b10 Data bus SIO4, 5 transmit/receive interrupt requests(Level) 4-source inputs F/F SIO4 reception finished SIO4 receive error ISR4 F/F SIO4 transmit buffer empty SIO4 transmission finished IST4 F/F SIO5 transmit buffer empty SIO5 transmission finished IST5 F/F SIO5 reception finished SIO5 receive error ISR5 <SI45STAT : H'0080 0A00> <SI45EN : H'0080 0A01> <SI45SEL : H'0080 0A02>

32180 Group User's Manual (Rev.1.0)

12.2.2 SIO Transmit Control Registers

SIO0 Transmit Control Register (S0TCNT) <Address: H'0080 0110> SIO1 Transmit Control Register (S1TCNT) <Address: H'0080 0120> SIO2 Transmit Control Register (S2TCNT) <Address: H'0080 0130> SIO3 Transmit Control Register (S3TCNT) <Address: H'0080 0140> SIO4 Transmit Control Register (S4TCNT) <Address: H'0080 0A10> SIO5 Transmit Control Register (S5TCNT) <Address: H'0080 0A20> 123456 b 7b0 TSTAT TBE TENCDIV 0 10 1 00 0 0 <After reset: H’12> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00 2, 3 CDIV b2 b3 R W BRG count source select bit 0 0: Select f(BCLK) 0 1: Select f(BCLK) divided by 8 1 0: Select f(BCLK) divided by 32 1 1: Select f(BCLK) divided by 256 4 No function assigned. Fix to "0". 00

5 TSTAT 0: Transmission stopped and no data in transmit buffer register R–

Transmit status bit 1: Transmitting now or data present in transmit buffer register

6 TBE 0:Data present in transmit buffer register R –

Transmit buffer empty bit 1: No data in transmit buffer register

7 TEN 0: Disable transmission R W

Transmit enable bit 1: Enable transmission (1) CDIV (baud rate generator count source select) bits (Bits 2–3) These bits select the count source for the Baud Rate Generator (BRG). Note:  If f(BCLK) is selected as the count source for the BRG, care must be taken when setting the BRG so that the baud rate will not exceed the maximum transfer speed. For details, see the section in which the BRG register is explained. (2) TSTAT (Transmit Status) bit (Bit 5) [Set condition] This bit is set to "1" by a write to the transmit buffer register while transmission is enabled. [Clear condition] This bit is cleared to "0" when transmission is idle (no data in the transmit shift register) and no data exists in the transmit buffer register. This bit is also cleared by clearing the transmit enable bit. (3) TBE (Transmit Buffer Empty) bit (Bit 6) [Set condition] This bit is set to "1" when data is transferred from the transmit buffer register to the transmit shift register and the transmit buffer register is thereby emptied. This bit is also set by clearing the transmit enable bit. [Clear condition] This bit is cleared to "0" by writing data to the lower byte of the transmit buffer register while transmission is enabled (TEN = "1"). (4) TEN (Transmit Enable) bit (Bit 7) Transmission is enabled by setting this bit to "1" and disabled by clearing this bit to "0". If this bit is cleared to "0" while transmitting data, the transmit operation stops.

32180 Group User's Manual (Rev.1.0)

12.2.3 SIO Transmit/Receive Mode Registers

SIO0 Transmit/Receive Mode Register (S0MOD) <Address: H'0080 0111> SIO1 Transmit/Receive Mode Register (S1MOD) <Address: H'0080 0121> SIO2 Transmit/Receive Mode Register (S2MOD) <Address: H'0080 0131> SIO3 Transmit/Receive Mode Register (S3MOD) <Address: H'0080 0141> SIO4 Transmit/Receive Mode Register (S4MOD) <Address: H'0080 0A11> SIO5 Transmit/Receive Mode Register (S5MOD) <Address: H'0080 0A21> 9 1 01 11 21 31 4 b 1 5b8 SMOD PEN SEN PSELSTBCKS 00000000 <After reset: H’00> b Bit Name Function R W 8–10 SMOD b8 b9 b10 R W Serial I/O mode select bit 0 0 0 : 7-bit UART (Note 1) 0 0 1 : 8-bit UART 0 1 X : 9-bit UART

1 X X : 8-bit clock-synchronous serial I/O

11 CKS 0: Internal clock R W

Internal/external clock select bit 1: External clock (Note 2)

12 STB 0: One stop bit R W

Stop bit length select bit, UART mode only 1: Two stop bits (Note 3)

13 PSEL 0: Odd parity R W

Odd/even parity select bit, UART mode only 1: Even parity (Note 3)

14 PEN 0: Disable parity R W

Parity enable bit, UART mode only 1: Enable parity (Note 3)

15 SEN 0: Disable sleep function R W

Sleep select bit, UART mode only 1: Enable sleep function (Note 3) Note 1: For SIO2 and 3, bit 8 is fixed to "0" in hardware. This bit cannot be set to "1" in software (to select clock-synchronous serial I/O). Note 2: Has no effect when UART mode selected. Note 3: Bits 12–15 have no effect during clock-synchronous mode. The SIO Mode Registers consist of bits to set the serial I/O operation mode, data format and the functions used during communication. The SIO Transmit/Receive Mode Registers must always be set before the serial I/O starts operating. To change register settings before the serial I/O starts sending or receiving data, first confirm that transmit and receive operations have finished and then disable transmit/receive operations (by clearing the SIO Transmit Control Register transmit enable bit and SIO Receive Control Register receive enable bit to "0") before making changes. (1) SMOD (Serial I/O Mode Select) bits (Bits 8–10) These bits select the operation mode of serial I/O. (2) CKS (Internal/External Clock Select) bit (Bit 11) This bit is effective when CSIO mode is selected. Setting this bit has no effect when UART mode is selected, in which case the serial I/O is clocked by the internal clock. (3) STB (Stop Bit Length Select) bit (Bit 12) This bit is effective during UART mode. Use this bit to select the stop bit length that indicates the end of data to transmit. Setting this bit to "0" selects one stop bit, and setting this bit to "1" selects two stop bits. During clock-synchronous mode, the content of this bit has no effect.

32180 Group User's Manual (Rev.1.0) (4) PSEL (Odd/Even Parity Select) bit (Bit 13) This bit is effective during UART mode. When parity is enabled (bit 14 = "1"), use this bit to select the parity attribute (whether odd or even). Setting this bit to "0" selects an odd parity, and setting this bit to "1" selects an even parity. When parity is disabled (bit 14 = "0") and during clock-synchronous mode, the content of this bit has no effect. (5) PEN (Parity Enable) bit (Bit 14) This bit is effective during UART mode. When this bit is set to "1", a parity bit is added immediately after the data bits of the transmit data, and the received data is checked for parity. The parity bit added to the transmit data is automatically determined to be "0" or "1" so that the attribute (odd/ even) derived by adding the number of 1’s in data bits and the content of the parity bit agrees with one that was selected with the odd/even parity select bit (bit 13). Figure 12.2.7 shows an example of a data format when parity is enabled. (6) SEN (Sleep Select) bit (Bit 15) This bit is effective during UART mode. If the sleep function is enabled by setting this bit to "1", data is latched into the UART Receive Buffer Register only when the most significant bit (MSB) of the received data is "1".

32180 Group User's Manual (Rev.1.0)  When transmitting If the attribute (odd/even) represented by the number of 1's in data bits agrees with the selected parity attribute, a parity bit "0" is added. If the attribute (odd/even) represented by the number of 1's in data bits does not agree with the selected parity attribute, a parity bit "1" is added. b7 b6 b5 b4 b3 b2 b1 b0 PAR SPST Attribute derived from b7 + b6 + ... + b0 If it agrees with the selected parity attribute, PAR = "0" is added. If it does not agree with the selected parity attribute, PAR = "1" is added. LSB MSB  When receiving The received data is checked to see if the number of 1's included in its data and parity bits agrees with the parity attribute (known as parity check). b7 b6 b5 b4 b3 b2 b1 b0 PAR SPST LSB MSB If the result of b7 + b6 + ... + b0 + PAR does not agree with the selected parity attribute, a parity error is assumed Notes :  Shown above is an example of a data format in 8-bit UART mode.  The data bit numbers (bn) above indicate bit numbers in a data list, and not the register bit numbers (bn). b8 b7 b6 b5 b4 b3 b2 b1 PAR SPST b0 9-bit UART mode b7 b6 b5 b4 b3 b2 b1 b0 PAR SPST 8-bit UART mode b6 b5 b4 b3 b2 b1 b0 PAR SPST (Note 1)  7-bit UART mode b7 b6 b5 b4 b3 b2 b1 Clock-synchronous mode b0 Note 1: Whether or not to add a parity bit is selectable. Note 2: The stop bit can be chosen to be one bit or two bits long. Direction of transfer ST : Start bit PAR : Parity bit : One frame equivalent b : Data bits SP : Stop bit (Note 2) (Note 1) (Note 1) (Note 2) (Note 2) Figure 12.2.7 Data Format When Parity is Enabled

32180 Group User's Manual (Rev.1.0)

12.2.4 SIO Transmit Buffer Registers

SIO0 Transmit Buffer Register (S0TXB) <Address: H'0080 0112> SIO1 Transmit Buffer Register (S1TXB) <Address: H'0080 0122> SIO2 Transmit Buffer Register (S2TXB) <Address: H'0080 0132> SIO3 Transmit Buffer Register (S3TXB) <Address: H'0080 0142> SIO4 Transmit Buffer Register (S4TXB) <Address: H'0080 0A12> SIO5 Transmit Buffer Register (S5TXB) <Address: H'0080 0A22> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TDATA <After reset: Undefined> b Bit Name Function R W 0–6 No function assigned. Fix to "0". ?0 7–15 TDATA Transmit data is set in these bits. ? W Transmit data The SIO Transmit Buffer Registers are used to set transmit data. These registers are a write-only register, and the contents of these registers cannot be read out. Data must be LSB-aligned when set in these registers. Therefore, write transmit data to bits 9–15 for the 7-bit data format (UART mode only), bits 8–15 for the 8-bit data format, or bits 7–15 for the 9-bit data format (UART mode only). Before setting transmit data in these registers, enable the Transmit Control Register TEN (Transmit Enable) bit by setting it to "1". Writing data to these registers while the TEN bit is disabled (cleared to "0") has no effect. When data is written to the SIO Transmit Buffer Register while transmission is enabled, the data is transferred from that register to the SIO Transmit Shift Register, upon which the serial I/O starts sending data. Note: For the 7-bit and 8-bit data formats, the register can be accessed bytewise.

32180 Group User's Manual (Rev.1.0)

12.2.5 SIO Receive Buffer Registers

SIO0 Receive Buffer Register (S0RXB) <Address: H'0080 0114> SIO1 Receive Buffer Register (S1RXB) <Address: H'0080 0124> SIO2 Receive Buffer Register (S2RXB) <Address: H'0080 0134> SIO3 Receive Buffer Register (S3RXB) <Address: H'0080 0144> SIO4 Receive Buffer Register (S4RXB) <Address: H'0080 0A14> SIO5 Receive Buffer Register (S5RXB) <Address: H'0080 0A24> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 RDATA <After reset: Undefined> b Bit Name Function R W 0–6 No function assigned. 0 – 8–15 RDATA Received data is stored in these bits. R – Received data The SIO Receive Buffer Registers are used to store the received data. When the serial I/O has finished receiving data, the content of the SIO Receive Shift Register is transferred to the SIO Receive Buffer Register. These registers are a read-only register. For the 7-bit data format (UART mode only), data is set in bits 9–15, with bits 8 and 7 always set to "0". For the 8-bit data format, data is set in bits 8–15, with bit 7 always set to "0". When reading the content of the SIO Receive Buffer Register after reception is completed, if the serial I/O finishes receiving the next data before the previous data is not read out, an overrun error occurs and the subse- quent received data are not transferred to the Receive Buffer Register. To restart normal receive operation, clear the Receive Control Register REN (Receive Enable) bit to "0". Note: For the 7-bit and 8-bit data formats, the register can be accessed bytewise.

32180 Group User's Manual (Rev.1.0)

12.2.6 SIO Receive Control Registers

SIO0 Receive Control Register (S0RCNT) <Address: H'0080 0116> SIO1 Receive Control Register (S1RCNT) <Address: H'0080 0126> SIO2 Receive Control Register (S2RCNT) <Address: H'0080 0136> SIO3 Receive Control Register (S3RCNT) <Address: H'0080 0146> SIO4 Receive Control Register (S4RCNT) <Address: H'0080 0A16> SIO5 Receive Control Register (S5RCNT) <Address: H'0080 0A26> 123456 b 7b0 PTY FLM ERSRSTAT RFIN REN OVR 00000000 <After reset: H’00> b Bit Name Function R W 0 No function assigned. Fix to "0". 00

1 RSTAT 0: Reception stopped R –

Receive status bit 1: Reception in progress

2 RFIN 0: No data in receive buffer register R –

Reception finished bit 1: Data present in receive buffer register

3 REN 0: Disable reception R W

Receive enable bit 1: Enable reception

4 OVR 0: No overrun error R –

Overrun error bit 1: Overrun error occurred

5 PTY 0: No parity error R –

Parity error bit, UART mode only 1: Parity error occurred

6 FLM 0: No framing error R –

Framing error bit, UART mode only 1: Framing error occurred

7 ERS 0: No error R –

Error sum bit 1: Error occurred

32180 Group User's Manual (Rev.1.0) (1) RSTAT (Receive Status) bit (Bit 1) [Set condition] This bit is set to "1" by a start of receive operation. When this bit = "1", the serial I/O is receiving data. [Clear condition] This bit is cleared to "0" upon completion of receive operation or by clearing the REN (Receive Enable) bit. (2) RFIN (Reception Finished) bit (Bit 2) [Set condition] This bit is set to "1" when all data bits have been received in the Receive Shift Register and whose content is transferred to the Receive Buffer Register. [Clear condition] This bit is cleared to "0" by reading out the lower byte of the Receive Buffer Register or by clearing the REN (Receive Enable) bit. However, if an overrun error occurs, this bit cannot be cleared by reading out the lower byte of the Receive Buffer Register. In this case, clear REN (Receive Enable) bit. (3) REN (Receive Enable) bit (Bit 3) Reception is enabled by setting this bit to "1", and is disabled by clearing this bit to "0", in which case the receiver unit is initialized. Accordingly, the receive status and reception finished flags, as well as the overrun error, framing error, parity error and error sum flags all are cleared. The receive operation stops if the Receive Enable bit is cleared to "0" while receiving data. (4) OVR (Overrun Error) bit (Bit 4) [Set condition] This bit is set to "1" when all bits of the next received data have been set in the Receive Shift Register while the Receive Buffer Register still contains the previous received data. In this case, the received data is not stored in the Receive Buffer Register. Although receive operation continues even when the overrun error flag = "1", the received data is not stored in the Receive Buffer Register. This error bit must be cleared before normal reception can be restarted. [Clear condition] This bit is cleared to "0" by only clearing the REN (Receive Enable) bit. (5) PTY (Parity Error) bit (Bit 5) This bit is effective in only UART mode. It is fixed to "0" during CSIO mode. [Set condition] The PTY (Parity Error) bit is set to "1" when the SIO Transmit/Receive Mode Register PEN (Parity Enable/Disable) bit is enabled and the parity (even or odd) of the received data does not agree with one that was set by the said register’s PSEL (Parity Select) bit. [Clear condition] The PTY bit is cleared to "0" by reading out the lower byte of the SIO Receive Buffer Register or by clearing the SIO Receive Control Register REN (Receive Enable) bit. However, if an overrun error occurs, this bit cannot be cleared by reading out the lower byte of the Receive Buffer Register. In this case, clear the REN (Receive Enable) bit.

32180 Group User's Manual (Rev.1.0) (6) FLM (Framing Error) bit (Bit 6) This bit is effective in only UART mode. It is fixed to "0" during CSIO mode. [Set condition] The FLM (Framing Error) bit is set to "1" when the number of received bits does not agree with one that was set by the SIO Transmit/Receive Mode Register. [Clear condition] The FLM bit is cleared to "0" by reading out the lower byte of the SIO Receive Buffer Register or by clearing the SIO Receive Control Register REN (Receive Enable) bit. However, if an overrun error occurs, this bit cannot be cleared by reading out the lower byte of the Receive Buffer Register. In this case, clear the REN (Receive Enable) bit. (7) ERS (Error Sum) bit (Bit 7) [Set condition] This flag is set to "1" when any one of overrun, framing or parity errors is detected at completion of reception. [Clear condition] If the detected error was an overrun error, this flag is cleared by clearing the REN (Receive Enable) bit to "0". Otherwise, this flag is cleared by reading out the lower byte of the SIO Receive Buffer Register or by clearing the SIO Receive Control Register REN (Receive Enable) bit.

32180 Group User's Manual (Rev.1.0)

12.2.7 SIO Baud Rate Registers

SIO0 Baud Rate Register (S0BAUR) <Address: H'0080 0117> SIO1 Baud Rate Register (S1BAUR) <Address: H'0080 0127> SIO2 Baud Rate Register (S2BAUR) <Address: H'0080 0137> SIO3 Baud Rate Register (S3BAUR) <Address: H'0080 0147> SIO4 Baud Rate Register (S4BAUR) <Address: H'0080 0A17> SIO5 Baud Rate Register (S5BAUR) <Address: H'0080 0A27> 9 1 01 11 21 31 4 b 1 5b8 BRG <After reset: Undefined> b Bit Name Function R W 8–15 BRG The baud rate count source selected by SIO Mode Register R W Baud rate divide value is divided by (n + 1) where n = BRG set value. (1) BRG (baud rate divide value) (Bits 8–15) The SIO Baud Rate Registers are used to set a baud rate divide value, so that the baud rate count source selected by SIO Mode Register is divided by (n + 1) where n = BRG set value. Because the BRG value initially is undefined, be sure to set the divide value before the serial I/O starts operating. The value written to the BRG during transmit/receive operation takes effect in the next cycle after the BRG counter has finished counting. When using the internal clock (to output the SCLKO signal) in CSIO mode, the serial I/O divides the internal BCLK using a clock divider and then divides the resulting clock by (n + 1) where n = BRG set value and further by 2, thereby generating a transmit/receive shift clock. When using an external clock in CSIO mode, the serial I/O does not use the BRG. (Transmit/receive opera- tions are synchronized to the externally supplied clock.) During UART mode, the serial I/O divides the internal BCLK using a clock divider and then divides the resulting clock by (n + 1) where n = BRG set value and further by 16, thereby generating a transmit/receive shift clock. When using SIO0, SIO1, SIO4 or SIO5 in UART mode, set the relevant port (P84, P87, P65 or P66) to function as an SCLKO pin, so that a BRG output clock divided by 2 can be output from that SCLKO pin. When using the internal clock (internally clocked CSIO mode or UART mode), if f(BCLK) is selected as the BRG count source, make sure the transfer rate does not exceed 2 Mbits/second during CSIO mode, and that BRG is equal to or greater than 7 during UART mode.

32180 Group User's Manual (Rev.1.0)

12.3.1 Setting the CSIO Baud Rate

The baud rate (data transfer rate) in CSIO mode is determined by a transmit/receive shift clock. The clock source from which a transmit/receive shift clock derives is selected from the internal clock f(BCLK) or external clock. The CKS (Internal/External Clock Select) bit (SIO Transmit/Receive Mode Register bit 11) is used to select the clock source. The equation used to calculate the transmit/receive baud rate differs depending on whether an internal or exter- nal clock is selected. (1) When internal clock is selected in CSIO mode When the internal clock is selected, f(BCLK) is divided by a clock divider before being supplied to the Baud Rate Generator (BRG). The clock divider’s divide-by value is selected from 1, 8, 32 or 256 by using the CDIV (baud rate generator count source select) bits (Transmit Control Register bits 2–3). The Baud Rate Generator divides the clock divider output by (baud rate register set value + 1) and further by 2, thus generating a transmit/receive shift clock. When the internal clock is selected in CSIO mode, the baud rate is calculated using the equation below. Baud rate = f(BCLK) [bps] Clock divider’s divide-by value x (baud rate register set value + 1) x 2 Baud rate register set value = H’00 to H’FF (Note 1) Clock divider’s divide-by value = 1, 8, 32 or 256 Note 1: If divide-by-1 (i.e., f(BCLK) itself) is selected as the baud rate generator count source, use caution when setting the baud rate register so that the transfer rate will not exceed 2 Mbps. (2) When external clock is selected in CSIO mode In this case, the Baud Rate Generator is not used, and the input clock from the SCLKI pin serves directly as a transmit/receive shift clock for CSIO. The maximum frequency of the SCLKI pin input clock is f(BCLK)/16. Baud rate = SCLKI pin input clock [bps]

32180 Group User's Manual (Rev.1.0)

12.3.2 Initializing CSIO Transmission

To transmit data in CSIO mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register  Set the register to CSIO mode.  Select the internal or an external clock. (2) Setting SIO Transmit Control Register  Select the clock divider’s divide-by ratio (when internal clock selected). (3) Setting SIO Baud Rate Register When the internal clock is selected, set a baud rate generator value. (See Section 12.3.1, “Setting the CSIO Baud Rate.”) (4) Setting the SIO interrupt related registers  Select the source of transmit interrupt request (transmit buffer empty or transmission finished) (SIO Interrupt Request Source Select Register).  Enable or disable transmit interrupt requests (SIO Interrupt Request Enable Register). Note:  Transmission finished interrupt requests are effective only when the internal clock is selected. (5) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) To use transmit interrupts, set their priority levels. (6) Setting the DMAC To issue DMA transfer requests to the internal DMAC when the transmit buffer is empty, set up the DMAC. (See Chapter 9, “DMAC. ”) (7) Selecting pin functions Because the serial I/O related pins serve dual purposes, set the pin functions for use as SIO pins or input/ output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”)

32180 Group User's Manual (Rev.1.0) Figure 12.3.1 Procedure for Initializing CSIO Transmission Set SIO Transmit/Receive Mode Register Initialize CSIO transmission Note 1: Necessary when the internal clock is selected. Note 2: If the internal clock and a divide-by ratio = 1 are selected, caution must be used when setting the baud rate register so that the transfer rate will not exceed 2 Mbps. Note 3: Transmission finished interrupts are effective only when the internal clock is selected.  Set the register to CSIO mode  Select the internal or external clock (When using the DMAC)Set DMAC (When using interrupts)Set Interrupt Controller Set SIO interrupt related registers  Divide-by ratio = H'00 to H'FF (Note 2)Set SIO Baud Rate Register  Select the clock divider divide-by ratio (Note 1)Set SIO Transmit Control Register Set Input/Output Port Operation Mode Register Serial I/O related registers End of CSIO transmit initialization  Enable or disable transmit interrupt requests  Select the source of transmit interrupt request (Note 3)

32180 Group User's Manual (Rev.1.0)

12.3.3 Starting CSIO Transmission

The serial I/O starts a transmit operation when all of the following conditions are met after being initialized. (1) Transmit conditions when CSIO mode internal clock is selected  The SIO Transmit Control Register transmit enable bit is set to "1".  Transmit data (8 bits) is written to the lower byte of the SIO Transmit Buffer Register (transmit buffer empty bit = "0") (2) Transmit conditions when CSIO mode external clock is selected  The SIO Transmit Control Register transmit enable bit is set to "1".  Transmit data is written to the lower byte of the SIO Transmit Buffer Register (transmit buffer empty bit = "0")  A falling edge of transmit clock on the SCLKI pin is detected.  While the transmit enable bit is cleared to "0", writes to the transmit buffer register are ignored. Always set the transmit enable bit to "1" before writing to the transmit buffer register.  When the internal clock is selected, a write to the lower byte of the transmit buffer register in above triggers transmission to start.  The transmit status bit is set to "1" at the time data is set in the lower byte of the SIO Transmit Buffer Register. When transmission starts, the serial I/O sends data following the procedure described below.  Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register.  Set the transmit buffer empty bit to "1" (Note 1).  Start sending data synchronously with the shift clock beginning with the LSB. Note 1: A transmit interrupt request can be generated for reasons that the transmit buffer is empty or transmission has finished. Also, a DMA transfer request can be generated when the transmit buffer is empty. No DMA transfer requests can be generated for reasons that transmission has finished.

12.3.4 Successive CSIO Transmission

Once data has been transferred from the transmit buffer register to the transmit shift register, the next data can be written to the transmit buffer register even when the serial I/O has not finished sending the previous data. If the next data is written to the transmit buffer register before transmission has finished, the previous and the next data are transmitted successively. Check the SIO Transmit Control Register’s Status Register’s transmit buffer empty flag to see if data has been transferred from the transmit buffer register to the transmit shift register.

32180 Group User's Manual (Rev.1.0)

12.3.5 Processing at End of CSIO Transmission

When data transmission finishes, the following operation is automatically performed in hardware. (1) When not transmitting successively  The transmit status bit is cleared to "0". (2) When transmitting successively  When transmission of the last data in a consecutive data train finishes, the transmit status bit is cleared to "0".

12.3.6 Transmit Interrupts

(1) Transmit buffer empty interrupt If the transmit buffer empty interrupt was selected using the SIO Interrupt Request Source Select Register, a transmit buffer empty interrupt request is generated when data has been transferred from the transmit buffer register to the transmit shift register. A transmit buffer empty interrupt request is also generated when the TEN (Transmit Enable) bit is set to "1" (disabled → enabled) while the transmit buffer empty interrupt has been enabled. (2) Transmission finished interrupt If the transmission finished interrupt was selected using the SIO Interrupt Request Source Select Register, a transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse at which the last bit of data in the transmit shift register has been transmitted or when the transmit enable bit is cleared. The SIO Interrupt Request Enable Register and the Interrupt Controller (ICU) must be set before these transmit interrupts can be used.

12.3.7 Transmit DMA Transfer Request

When data has been transferred from the transmit buffer register to the transmit shift register, a transmit DMA transfer request for the corresponding SIO channel is output to the DMAC. A transmit DMA transfer request is also output when the TEN (Transmit Enable) bit is set to "1" (disabled → enabled). The DMAC must be set before DMA transfers can be used during data transmission.

32180 Group User's Manual (Rev.1.0) Figure 12.3.2 Transmit Operation during CSIO Mode (Hardware Processing) The following processing is automatically performed in hardware.  Transfer the content of the transmit buffer to the transmit shift register  Set the transmit buffer empty bit to "1" Transmit data Y (Successive transmission) Transmit conditions met? Transmit conditions met? Y N N Clear the transmit status bit to "0" Transmit DMA transfer request Transmit interrupt request (Note 1) CSIO transmit operation starts End of CSIO transmit operation Note 1: This applies when the transmit interrupt request was enabled using the SIO Interrupt Request Enable Register after selecting the transmit buffer empty interrupt with the SIO Interrupt Request Source Select Register.

32180 Group User's Manual (Rev.1.0)

12.3.8 Example of CSIO Transmit Operation

The following shows a typical transmit operation in CSIO mode. Figure 12.3.3 Example of CSIO Transmission (Transmitted Only Once) Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time) Note 3: When transmission finished interrupt is enable Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt request bit cleared Note 5: A transmit interrupt request is generated when transmission is enabled. Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. Note 7: A transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse at which transmission of the transmit shift register data has finished or when the transmit enable bit is cleared. Note 8: It is inhibited to select the transmission finished interrupt when an external clock is selected. Internal clock selected External clock selected Set Transmit enable bit Transmit buffer empty bit Transmit status bit TXD (When transmit buffer empty interrupt is selected) Transmit interrupt request (Note 2) (Note 5) Transmit interrupt request (Note 2) (Note 6) Interrupt request accepted (Note 4) Set by a write to the transmit buffer Write to the transmit buffer register Transmit clock (SCLKO) <CSIO on transmit side> Cleared Cleared by completion of transmission b7 b6 b5 b4 b3 b2 b1 b0 Content of the transmit buffer register is transferred to the transmit shift register : Interrupt request generated : Processing by software <CSIO on transmit side> <CSIO on receive side> SCLKO TXD SCLKI RXD Transmit interrupt request (Note 3) (Note 7) Interrupt request accepted (When transmission finished interrupt is selected)(Note 8) (Internal transfer clock) SIO transmit interrupt request (Note 1)

32180 Group User's Manual (Rev.1.0) Figure 12.3.4 Example of CSIO Transmission (Transmitted Successively) Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time) Note 3: When transmission finished interrupt is enable Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt request bit cleared Note 5: A transmit interrupt request is generated when transmission is enabled. Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. Note 7: A transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse at which transmission of the transmit shift register data has finished or when the transmit enable bit is cleared. Note 8: It is inhibited to select the transmission finished interrupt when an external clock is selected. : Interrupt request generated : Processing by software Transmit enable bit Transmit buffer empty bit Transmit status bit TXD SIO transmit interrupt request (Note 1) Transmit clock (SCLKO) <CSIO on transmit side> <CSIO on transmit side> <CSIO on receive side> SCLKO TXD SCLKI RXD b7 b6 b5 b0 b7 b6 b5 b0 (Note 2) (Note 5) (Note 2) (Note 2)(Note 6) Next data is written at a transmit buffer empty interrupt First data Next data Write to the transmit buffer register (First data) (Next data) Write to the transmit buffer register Cleared Internal clock selected External clock selected Set (Internal transfer clock) (When transmit buffer empty interrupt is selected) (When transmission finished interrupt is selected) (Note 8) (Note 3) Transmit interrupt request (Note 3)(Note 7)Interrupt request accepted (Note 4) Interrupt request accepted (Note 4)

32180 Group User's Manual (Rev.1.0)

12.4.1 Initialization for CSIO Reception

To receive data in CSIO mode, initialize the serial I/O following the procedure described below. Note, however, that because the receive shift clock is derived by an operation of the transmit circuit, transmit operation must always be executed even when the serial I/O is used for only receiving data. (1) Setting SIO Transmit/Receive Mode Register  Set the register to CSIO mode.  Select the internal or an external clock. (2) Setting SIO Transmit Control Register  Select the clock divider’s divide-by ratio (when internal clock selected). (3) Setting SIO Baud Rate Register When the internal clock is selected, set a baud rate generator value. (See Section 12.3.1, “Setting the CSIO Baud Rate.”) (4) Setting SIO interrupt related registers  Select the source of receive interrupt request (reception finished or error) (SIO Interrupt Request Source Select Register).  Enable or disable receive interrupts (SIO Interrupt Request Enable Register). (5) Setting SIO Receive Control Register  Set the receive enable bit. (6) Setting Interrupt Controller (SIO Transmit Interrupt Control Register) To use receive interrupts, set their priority levels. (7) Setting DMAC Set up the DMAC when the DMA transfer is requested to the internal DMAC on completion of the transmission. (See Chapter 9, “DMAC. ”)

32180 Group User's Manual (Rev.1.0) Figure 12.4.1 Procedure for Initializing CSIO Reception Initialize CSIO reception Note 1: Necessary when the internal clock is selected. Note 2: If the internal clock and a divide-by ratio = 1 are selected, caution must be used when setting the baud rate register so that the transfer rate will not exceed 2 Mbps.  Set the register to CSIO mode  Select the internal or external clock Set SIO Transmit/Receive Mode Register (When using the DMAC)Set DMAC (When using interrupts)Set Interrupt Controller  Select the source of receive interrupt requestSet SIO interrupt related registers  Divide-by ratio = H'00 to H'FF (Note 2) Set SIO Baud Rate Register  Select the clock divider divide-by ratio (Note 1) Set SIO Transmit Control Register Set Input/Output Port Operation Mode Register Serial I/O related registers Set SIO Receive Control Register  Set the receive enable bit End of CSIO receive initialization  Enable or disable receive interrupt requests (8) Selecting pin functions Because the serial I/O related pins serve dual purposes, set the pin functions for use as SIO pins or input/ output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”)

32180 Group User's Manual (Rev.1.0)

12.4.2 Starting CSIO Reception

The serial I/O starts receive operation when all of the following conditions are met after being initialized. (1) Receive conditions when CSIO mode internal clock is selected  The SIO Receive Control Register receive enable bit is set to "1".  Transmit conditions are met. (See Section 12.3.3, “Starting CSIO Transmission.”) (2) Receive conditions when CSIO mode external clock is selected  The SIO Receive Control Register receive enable bit is set to "1".  Transmit conditions are met. (See Section 12.3.3, “Starting CSIO Transmission.”) Note:  The receive status bit is set to "1" at the time dummy data is set in the lower byte of the SIO Transmit Buffer Register. When the above conditions are met, the serial I/O starts receiving 8-bit serial data (LSB first) synchronously with the receive shift clock.

12.4.3 Processing at End of CSIO Reception

When data reception finishes, the following operation is automatically performed in hardware. (1) When reception is completed normally The reception finished (receive buffer full) bit is set to "1". Notes:  An interrupt request is generated if the reception finished (receive buffer full) interrupt has been enabled.  A DMA transfer request is generated. (2) When an error occurred during reception If an error (only overrun error in CSIO mode) occurred during reception, the overrun error bit and receive error sum bit are set to "1". Notes:  If the reception finished interrupt has been selected (by SIO Receive Interrupt Request Source Select Register), neither a reception finished interrupt request nor a DMA transfer request is generated.  If the receive error interrupt has been selected (by SIO Receive Interrupt Request Source Select Register), a receive error interrupt request is generated when interrupt requests are enabled. No DMA transfer requests are generated.

32180 Group User's Manual (Rev.1.0) Figure 12.4.2 Receive Operation during CSIO Mode (Hardware Processing) Receive data Set the SIO Receive Control Register reception finished bit to "1" Store the received data in the receive buffer register Set the SIO Receive Control Register overrun error and receive error sum bits to "1" Receive conditions met? Overrun error ? Y Y N N End of CSIO receive operation CSIO receive operation starts

12.4.4 About Successive Reception

If the following conditions are met when data reception has finished, data may be received successively.  The receive enable bit is set to "1".  Transmit conditions are met.  No overrun error has occurred.

32180 Group User's Manual (Rev.1.0)

12.4.5 Flags Showing the Status of CSIO Receive Operation

There are following flags that indicate the status of receive operation during CSIO mode:  SIO Receive Control Register receive status bit  SIO Receive Control Register reception finished bit  SIO Receive Control Register receive error sum bit  SIO Receive Control Register overrun error bit When reading the content of the SIO Receive Buffer Register after reception is completed, if the serial I/O finishes receiving the next data before the previous data is not read out, an overrun error occurs and the subse- quent received data are not transferred to the receive buffer register. Before receive operation can be restarted, the receive enable bit must temporarily be cleared to "0" to initialize the receiver control unit. The above reception finished bit, if no receive errors occurred (Note 1), may be cleared by reading out the lower byte of the SIO Receive Buffer Register or clearing the REN (Receive Enable) bit. However, if any receive error occurred, the reception finished bit can only be cleared by clearing the REN (Receive Enable) bit, and cannot be cleared by reading out the lower byte of the SIO Receive Buffer Register. Note 1: Overrun errors are the only error that can be detected during reception in CSIO mode.

32180 Group User's Manual (Rev.1.0) Figure 12.4.3 Example of CSIO Reception (When Received Normally) Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit Note 2: When reception finished interrupt is enabled (DMA transfer can also be requested at the same time) Note 3: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register interrupt request bit cleared <CSIO on receive side> <CSIO on transmit side><CSIO on receive side> SCLKO TXD SCLKI RXD Internal clock selected External clock selected Receive clock (SCLKO) Set Receive enable bit RXD Receive status bit Reception finished bit SIO receive interrupt request (Note 1) (When reception finished interrupt is selected) (When receive error interrupt is selected) No interrupt request Interrupt request accepted (Note 3) Reception finished interrupt request (Note 2) Read from the receive buffer : Interrupt request generated : Processing by software Automatically cleared for each receive operation performed Clock stops Cleared Set by a write to the transmit buffer b7 b6 b5 b4 b3 b2 b1 b0

12.4.6 Example of CSIO Receive Operation

The following shows a typical receive operation in CSIO mode.

32180 Group User's Manual (Rev.1.0) Figure 12.4.4 Example of CSIO Reception (When Overrun Error Occurred) <CSIO on receive side> External clock selectedInternal clock selected <CSIO on receive side> <CSIO on transmit side> SCLKO RXD SCLKI TXD : Processing by software : Interrupt request generated Receive clock (SCLKI) Set Receive enable bit b7 b6 b0RXD b7 b6b0 Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit Note 2: When reception finished interrupt is enabled Note 3: When receive error interrupt is enabled Note 4: The receive enable bit is cleared Note 5: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register interrupt request bit cleared First data reception completed Next data reception completed Reception finished bit SIO receive interrupt request (Note 1) (When reception finished interrupt is selected) Receive buffer not read out during this interval Set Overrun error bit cleared (Note 4) Reception finished interrupt request (Note 2) Interrupt request accepted (Note 5) Cleared Receive error interrupt request (Note 3) Interrupt request accepted (Note 5) (When receive error interrupt is selected) Overrun error bit

32180 Group User's Manual (Rev.1.0)

12.5 Precautions on Using CSIO Mod

 Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register’s BRG count source select bit must always be set before the serial I/O starts operating. If these settings need to be changed after a transmit or receive operation has started, first check to see that transmit and receive operations have finished and then clear the transmit and receive enable bits before making changes.  Settings of BRG (Baud Rate Register) If f(BCLK) is selected with the BRG clock source select bit, use caution when setting the BRG register so that the transfer rate will not exceed 2 Mbps.  About successive transmission To transmit data successively, make sure the next transmit data is set in the SIO Transmit Buffer Register before the current data transmission finishes.  About reception Because the receive shift clock in CSIO mode is derived by an operation of the transmit circuit, transmit operation must always be executed (by sending dummy data) even when the serial I/O is used for only receiving data. In this case, be aware that if the port function is set for the TXD pin (by setting the operation mode register to "1"), dummy data may actually be output from the pin.  About successive reception To receive data successively, make sure that data (dummy data) is set in the SIO Transmit Buffer Register before a transmit operation on the transmitter side starts.  Transmission/reception using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before serial communication starts.  About reception finished bit If a receive error (overrun error) occurs, the reception finished bit can only be cleared by clearing the receive enable bit, and cannot be cleared by reading out the receive buffer register.  About overrun error If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored in the receive buffer register, with the previous received data retained in it. Although a receive operation continues thereafter, the subsequent received data is not stored in the receive buffer register (receive status bit = "1"). Before normal receive operation can be restarted, the receive enable bit must be temporarily cleared to "0". And this is the only way that the overrun error flag can be cleared.  About DMA transfer request generation during SIO transmission If the transmit buffer register becomes empty (transmit buffer empty flag = "1") while the transmit enable bit remains set to "1" (transmission enabled), an SIO transmit buffer empty DMA transfer request is generated.  About DMA transfer request generation during SIO reception If the reception finished bit is set to "1" (receive buffer register full), a reception finished DMA transfer request is generated. Be aware, however, that if an overrun error occurred during reception, this DMA transfer re- quest is not generated.

32180 Group User's Manual (Rev.1.0) Figure 12.6.1 Example of a Transfer Data Format during UART Mode ST b7 b6 b5 b4 b3 b2 b1 b0 PAR SP SP LSB MSB ST Parity bit Stop bit Start bit Data bits (8 bits) Transmit data Next data

12.6.1 Setting the UART Baud Rate

The baud rate (data transfer rate) in UART mode is determined by a transmit/receive shift clock. During UART mode, the source for this transmit/receive shift clock is always the internal clock no matter how the internal/ external clock select bit (SIO Transmit/Receive Mode Register bit 11) is set. (1) Calculating the UART mode baud rate After being divided by a clock divider, f(BCLK) is supplied to the Baud Rate Generator (BRG), after which it is further divided by 16 to produce a transmit/receive shift clock. The clock divider’s divide-by value is selected from 1, 8, 32 or 256 by using the SIO Transmit Control Regis- ter CDIV (baud rate generator count source select) bits (bits 2–3).(Note 1) The Baud Rate Generator divides the clock divider output by (baud rate register set value + 1) and further by 16, thus generating a transmit/receive shift clock. When the internal clock is selected in UART mode, the baud rate is calculated using the equation below. Baud rate = f(BCLK) [bps] Clock divider’s divide-by value x (baud rate register set value + 1) x 16 Baud rate register set value = H’00 to H’FF (Note 1) Clock divider’s divide-by value = 1, 8, 32 or 256 Note 1: If divide-by-1 (i.e., f(BCLK) itself) is selected as the baud rate generator count source, make sure the value set in the baud rate register is equal to or greater than 7.

12.6.2 UART Transmit/Receive Data Formats

The transmit/receive data format during UART mode is determined by setting the SIO Transmit/Receive Mode Register. Shown below is the transmit/receive data format that can be used in UART mode.

32180 Group User's Manual (Rev.1.0) Table 12.6.1 Transfer Data in UART Mode Bit Name Content ST (start bit) Indicates the beginning of data transmission. This is a low-level signal of a one bit period, which is added immediately preceding the transmit data. Bits 0–8 (character bits) Transmit/receive data transferred via serial I/O. In UART mode, 7, 8 or 9 bits of data can be transmitted/received. PAR (parity bit) Added to the transmit/receive character. When parity is enabled, parity is automatically set in such a way that the number of 1’s in the character including the parity bit itself is always even or odd as selected by the even/odd parity select bit. SP (stop bit) Indicates the end of data transmission, which is added immediately following the character (or if parity is enabled, immediately following the parity bit). The stop bit can be chosen to be one bit or two bits long. Figure 12.6.2 Selectable Data Formats during UART Mode ST b7 b6 b5 b4 b3 b2 b1 b0 PAR SP SP ST b7 b6 b5 b4 b3 b2 b1 b0 PAR SP ST b7 b6 b5 b4 b3 b2 b1 b0 SP SP ST b7 b6 b5 b4 b3 b2 b1 b0 SP LSB MSB 8-bit character ST b7 b6 b5 b4 b3 b2 b1 SP SPPAR ST b7 b6 b5 b4 b3 b2 b1 SP PAR ST b7 b6 b5 b4 b3 b2 b1 SP SP ST b7 b6 b5 b4 b3 b2 b1 SP LSB MSB 7-bit character 9-bit character ST b7 b6 b5 b4 b3 b2 b1 b0 PAR SP SP ST b7 b6 b5 b4 b3 b2 b1 b0 PAR SP ST b7 b6 b5 b4 b3 b2 b1 b0 SP SP ST b7 b6 b5 b4 b3 b2 b1 b0 SP LSB MSB Bits 0-7: Character (data) bits SP: Stop bit ST: Start bit PAR: Parity bitb0 b7 b8 b15 7-bit character 8-bit character 9-bit character SIO Transmit Buffer Register SIO Receive Buffer Register Notes:  The high-order bits of the selected character length in the SIO Receive Buffer Register are fixed to "0".  The data bit numbers (bn) above indicate bit numbers in a data list, and not the register bit numbers (bn).

32180 Group User's Manual (Rev.1.0)

12.6.3 Initializing UART Transmission

To transmit data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register  Set the register to UART mode.  Set parity (when enabled, select odd/even).  Set the stop bit length.  Set the character length (Note 1). Note 1: During UART mode, settings of the internal/external clock select bit have no effect (only the internal clock is useful). (2) Setting SIO Transmit Control Register  Select the clock divider’s divide-by ratio. (3) Setting SIO Baud Rate Register Set a baud rate generator value. (See Section 12.6.1, “Setting the UART Baud Rate.”) (4) Setting SIO interrupt related registers  Select the source of transmit interrupt request (transmit buffer empty or transmission finished) (SIO Interrupt Request Source Select Register).  Enable or disable SIO transmit interrupt requests (SIO Interrupt Request Enable Register). (5) Setting Interrupt Controller (SIO Transmit Interrupt Control Register) To use transmit interrupts, set their priority levels. (6) Setting DMAC To issue DMA transfer requests to the internal DMAC when the transmit buffer is empty, set up the DMAC. (See Chapter 9, “DMAC. ”) (7) Selecting pin functions Because the serial I/O related pins serve dual purposes, set the pin functions for use as SIO pins or input/ output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”)

32180 Group User's Manual (Rev.1.0) Figure 12.6.3 Procedure for Initializing UART Transmission Initialize UART transmission  Set the register to UART mode  Set parity (when enabled, select odd/even)  Set the stop bit length  Set the character length Set SIO Transmit/Receive Mode Register (When using the DMAC)Set DMAC related registers Set Interrupt Controller Set SIO interrupt related registers  Divide-by ratio = H'00 to H'FF (Note 1)Set SIO Baud Rate Register  Select the clock divider divide-by ratioSet SIO Transmit Control Register Set Input/Output Port Operation Mode Register Serial I/O related registers End of UART transmit initialization (When using interrupts) Note 1: If f(BCLK) is selected for BRG count source (CDVI), it is necessary that the value set in the baud rate register be equal to or greater than 7.  Select the source of transmit interrupt request  Enable or disable transmit interrupt requests

32180 Group User's Manual (Rev.1.0)

12.6.4 Starting UART Transmission

The serial I/O starts a transmit operation when all of the following conditions are met after being initialized.  SIO Transmit Control Register TEN (Transmit Enable) bit is set to "1" (Note 1).  Transmit data is written to the SIO Transmit Buffer Register (transmit buffer empty bit = "0"). Note 1: While the transmit enable bit is cleared to "0", writes to the transmit buffer are ignored. Always be sure to set the transmit enable bit to "1" before writing to the transmit buffer register. When transmission starts, the serial I/O sends data following the procedure described below.  Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register.  Set the transmit buffer empty bit to "1" (Note 2).  Start sending data synchronously with the shift clock beginning with the LSB. Note 2: A transmit interrupt request can be generated for reasons that the transmit buffer is empty or transmission has finished. Also, a DMA transfer request can be generated when the transmit buffer is empty. No DMA transfer requests can be generated for reasons that transmission has finished.

12.6.5 Successive UART Transmission

Once data has been transferred from the transmit buffer register to the transmit shift register, the next data can be written to the transmit buffer register even when the serial I/O has not finished sending the previous data. If the next data is written to the transmit buffer before transmission has finished, the previous and the next data are transmitted successively. Check the SIO Transmit Control Register’s transmit buffer empty flag to see if data has been transferred from the transmit buffer register to the transmit shift register.

12.6.6 Processing at End of UART Transmission

When data transmission finishes, the following operation is automatically performed in hardware. (1) When not transmitting successively  The transmit status bit is cleared to "0". (2) When transmitting successively  When transmission of the last data in a consecutive data train finishes, the transmit status bit is cleared to "0".

12.6.7 Transmit Interrupts

(1) Transmit buffer empty interrupt If the transmit buffer empty interrupt was selected using the SIO Interrupt Request Source Select Register, a transmit buffer empty interrupt request is generated when data has been transferred from the transmit buffer register to the transmit shift register. A transmit buffer empty interrupt request is also generated when the TEN (Transmit Enable) bit is set to "1" (reenabled after being disabled) while the transmit buffer empty interrupt has been enabled.

32180 Group User's Manual (Rev.1.0) Figure 12.6.4 Transmit Operation during UART Mode (Hardware Processing) The following processing is automatically performed in hardware.  Transfer the content of the transmit buffer to the transmit shift register  Set the transmit buffer empty bit to "1" Transmit DMA transfer request Transmit interrupt request Transmit data Y (Successive transmission) Transmit conditions met ? Transmit conditions met ? Clear the transmit status bit to "0" Y N N (Note 1) Note 1: This applies when the transmit interrupt was enabled using the SIO Interrupt Request Enable Register after selecting the transmit buffer empty interrupt with the SIO Interrupt Request Source Select Register. End of UART transmit operation UART transmit operation starts (2) Transmission finished interrupt If the transmission finished interrupt was selected using the SIO Interrupt Request Source Select Register, a transmission finished interrupt request is generated when data in the transmit shift register has all been transmitted. The SIO Interrupt Request Enable Register and the Interrupt Controller (ICU) must be set before these transmit interrupts can be used.

12.6.8 Transmit DMA Transfer Request

When data has been transferred from the transmit buffer register to the transmit shift register, a transmit DMA transfer request for the corresponding SIO channel is output to the DMAC. A transmit DMA transfer request is also output when the TEN (Transmit Enable) bit is set to "1" (disabled → enabled). The DMAC must be set before DMA transfers can be used during data transmission.

32180 Group User's Manual (Rev.1.0)

12.6.9 Example of UART Transmit Operation

The following shows a typical transmit operation in UART mode. <UART on transmit side> <UART on transmit side> <UART on receive side> TXD RXD Transmit enable bit Transmit buffer empty bit b0b6b7ST SP SPPAR Write to the transmit buffer register Transmit status bit TXD SIO transmit interrupt request (Note 1) Set Cleared : Processing by software : Interrupt request generated Cleared Transferred from the transmit buffer to the transmit shift register (transmission starts) Set Interrupt request accepted (Note 4) (Note 2)(Note 6) (Note 3)(Note 7) (Note 2) (Note 5) Transmit interrupt requestTransmit interrupt request Transmit interrupt request Interrupt request accepted (Note 4) (When transmit buffer empty interrupt is selected) (When transmission finished interrupt is selected) Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time) Note 3: When transmission finished interrupt is enable Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt request bit cleared Note 5: A transmit interrupt request is generated when transmission is enabled. Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. Note 7: A transmission finished interrupt request is generated when data in the transmit shift register has all been transmitted. Figure 12.6.5 Example of UART Transmission (Transmitted Only Once)

32180 Group User's Manual (Rev.1.0) Figure 12.6.6 Example of UART Transmission (Transmitted Successively) : Processing by software : Interrupt request generated Set Transmit buffer empty bit Transmit enable bit Cleared Transmit status bit Transferred from the transmit buffer to the transmit shift register (transmission starts) TXD SIO transmit interrupt request (Note 1) (First data) (Next data) Write to the transmit buffer register First data Next data is written upon transmit interrupt (Note 5) (Note 2) (Note 2) <UART on transmit side> <UART on transmit side> <UART on receive side> TXD RXD ST b7 b0 STSP b7 b0 SP Cleared when transfer of the last data is completed Interrupt request accepted (Note 4) Next data (Note 2)(Note 6) (Note 3) (Note 3)(Note 7) Interrupt request accepted (Note 4) (When transmit buffer empty interrupt is selected) (When transmission finished interrupt is selected) Write to the transmit buffer register Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time) Note 3: When transmission finished interrupt is enable Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt request bit cleared Note 5: A transmit interrupt request is generated when transmission is enabled. Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. Note 7: A transmission finished interrupt request is generated when data in the transmit shift register has all been transmitted.

32180 Group User's Manual (Rev.1.0)

12.7.1 Initialization for UART Reception

To receive data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register  Set the register to UART mode.  Set parity (when enabled, select odd/even).  Set the stop bit length.  Set the character length. Note:  During UART mode, settings of the internal/external clock select bit have no effect (only the internal clock is useful). (2) Setting SIO Transmit Control Register  Set the clock divider’s divide-by ratio. (3) Setting SIO Baud Rate Register Set a baud rate generator value. (See Section 12.6.1, “Setting the UART Baud Rate.”) (4) Setting SIO interrupt related registers  Select the source of receive interrupt request (reception finished or receive error) (Interrupt Request Source Select Register).  Enable or disable receive interrupts (Interrupt Request Enable Register). (5) Setting Interrupt Controller To use interrupts during reception, set their priority levels. (6) Setting DMAC To issue DMA transfer requests to the internal DMAC when reception has finished, set up the DMAC. (See Chapter 9, “DMAC. ”) (7) Selecting pin functions Because the serial I/O related pins serve dual purposes, set the pin functions for use as SIO pins or input/ output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”)

32180 Group User's Manual (Rev.1.0) Figure 12.7.1 Procedure for Initializing UART Reception Initialize UART reception  Set the register to UART mode  Set parity (when enabled, select odd/even)  Set the stop bit length  Set the character length Set SIO Transmit/Receive Mode Register (When using the DMAC)Set DMAC related registers Set Interrupt Controller's SIO Receive Interrupt Control Register Set SIO interrupt related registers  Select the source of receive interrupt request Enable or disable receive interrupt requests Set SIO Baud Rate Register  Select the clock divider divide-by ratioSet SIO Transmit Control Register Serial I/O related registers End of UART receive initialization (When using interrupts)  Divide-by ratio = H'00 to H'FF (Note 1) Note 1: If clock divider divide-by ratio = 1 is selected, it is necessary that the value set in the baud rate register be equal to or greater than 7. Set Input/Output Port Operation Mode Register

32180 Group User's Manual (Rev.1.0)

12.7.2 Starting UART Reception

The serial I/O starts receive operation when all of the following conditions are met after being initialized.  SIO Receive Control Register receive enable bit is set to "1"  Start bit (falling edge signal) is applied to the RXD pin When the above conditions are met, the serial I/O enters UART receive operation. However, the start bit is checked again at the first rise of the internal receive shift clock and if it is detected high for reasons of noise, etc., the serial I/O stops receive operation and waits for the start bit again.

12.7.3 Processing at End of UART Reception

When data reception finishes, the following operation is automatically performed in hardware. (1) When reception is completed normally The reception finished (receive buffer full) bit is set to "1". Notes:  An interrupt request is generated if the reception finished (receive buffer full) interrupt has been enabled.  A DMA transfer request is generated. (2) When a receive error occurred If an error occurred, the corresponding error bit (OE, FE or PE) and the receive error sum bit are set to "1". Notes:  If the reception finished interrupt has been selected (by SIO Receive Interrupt Request Source Select Register), a reception finished interrupt request is generated when interrupt requests are enabled. However, this does not apply when the detected error is an overrun error, in which case no reception finished interrupt requests are generated.  If the receive error interrupt has been selected (by SIO Receive Interrupt Request Source Select Register), a receive error interrupt request is generated when interrupt requests are enabled.  No DMA transfer requests are generated.

32180 Group User's Manual (Rev.1.0) Figure 12.7.2 Receive Operation during UART Mode (Hardware Processing) The following processing is automatically performed in hardware. Receive data Y Y N Transfer data from the SIO Receive Shift Register to the SIO Receive Buffer Register Set the SIO Receive Control Register reception finished bit to "1" Set the receive status bit to "1" Overrun error ? Parity error or framing error ? Receive conditions met ? Start bit detected normally ? N Set the SIO Receive Control Register overrun error bit and error sum bit to "1" Set the SIO Receive Control Register'scorresponding error bit and receive error sum bit to "1" N UART receive operation starts End of UART reception Y N Y

32180 Group User's Manual (Rev.1.0)

12.7.4 Example of UART Receive Operation

The following shows a typical receive operation in UART mode. Figure 12.7.3 Example of UART Reception (When Received Normally) <UART on receive side> <UART on receive side> <UART on transmit side> TXD RXD Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit Note 2: When reception finished interrupt is enabled (DMA transfer can also be requested at the same time) Note 3: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register interrupt re quest bit cleared Receive enable bit (SIO Receive Control Register) b0b6b7ST SP SP PAR Reception finished bit RXD Set Cleared : Processing by software : Interrupt request generated Internal clock selected Read from the receive buffer Reception finished interrupt request (Note 2) Interrupt request accepted (Note 3) Receive status bit Automatically cleared for each receive operation performed SIO receive interrupt request (Note 1) (When reception finished interrupt is selected) (When receive error interrupt is selected) No interrupt request

32180 Group User's Manual (Rev.1.0) Figure 12.7.4 Example of UART Reception (When Overrun Error Occurred) <UART on receive side> <UART on receive side> <UART on transmit side> TXD RXD Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit Note 2: When reception finished interrupt is enabled Note 3: When receive error interrupt is enabled Note 4: This is done by clearing the receive enable bit to "0". Note 5: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register interrupt request bit cleared Receive enable bit SIO Receive Control Register) b7ST SP SP Reception finished bit RXD Set : Processing by software : Interrupt request generated ST b7 Receive buffer not read during this interval First data reception completed Next data reception completed (Note 5) Overrun error bit cleared (Note 4) Overrun error bit Set SIO receive interrupt request (Note 1) (When reception finished interrupt is selected) Reception finished interrupt request Interrupt request accepted (Note 5) Receive error interrupt request (Note 3) Interrupt request accepted (Note 5) (When receive error interrupt is selected) (Note 2)

32180 Group User's Manual (Rev.1.0) Figure 12.7.7 Delay in Receive Timing

12.7.5 Start Bit Detection during UART Reception

The start bit is sampled synchronously with the internal BRG output. If the received signal remains low for 8 BRG output cycles after the falling edge of the start bit, the CPU recognizes that part of the received signal as the start bit and starts latching the received data another 8 cycles after that, beginning with the LSB (first bit). If some sampled part of the received signal is high before being determined to be the start bit, the CPU starts hunting the falling edge of the received signal again. Because the start bit is sampled synchronously with the internal BRG output, there is a delay equivalent to one BRG output cycle at maximum. The subsequent received data is latched into the internal circuit with that delayed timing. Figure 12.7.5 Start Bit Detection Figure 12.7.6 Example of an Invalid Start Bit (Not Received) Internal BRG output RXD LSB data 16 cycles 8 cycles 8 cycles Note:  This diagram does not show detailed timing information. Internal BRG output RXD 8 cycles Note:  This diagram does not show detailed timing information. Internal RXD Internal BRG output RXD Delay equivalent to one BRG output cycle at maximum

32180 Group User's Manual (Rev.1.0) When using SIO0, SIO1, SIO4 or SIO5 in UART mode, the relevant port (P84, P87, P65 or P66) can be switched for use as an SCLKO0, SCLKO1, SCLKO4 or SCLKO5 pin, respectively. That way, a BRG output clock divided by 2 can be output from the SCLKO pin. Note:  This clock is output not just during data transfer. Figure 12.8.1 Example of Fixed Period Clock Output SCLKO TXD RXD Clock output to peripheral circuits UART transmission/reception ST SP Data ST SP Data 50% 50% BRG period Internal BRG output SCLKO output 1. Configuration when using BRG/2 clock 2. Operation timing

32180 Group User's Manual (Rev.1.0)  Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register’s BRG count source select bit must always be set before the serial I/O starts operating. If these settings need to be changed after a transmit or receive operation has started, first check to see that transmit and receive operations have finished and then clear the transmit and receive enable bits before making changes.  Settings of BRG (Baud Rate Register) If f(BCLK) is selected with the BRG clock source select bit, make sure the value set in the BRG register is equal to or greater than 7. Writes to the SIO Baud Rate Register take effect in the next cycle after the BRG counter has finished counting. However, if the register is accessed for write while transmission and reception are disabled, the written value takes effect at the same time it is written.  Transmission/reception using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before serial communication starts.  About overrun error If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored in the receive buffer register, with the previous received data retained in it. Once an overrun error occurs, although a receive operation continues, the subsequent received data is not stored in the receive buffer register. Before normal receive operation can be restarted, the receive enable bit must be temporarily cleared. And this is the only way that the overrun error flag can be cleared.  Flags showing the status of UART receive operation There are following flags that indicate the status of receive operation during UART mode:  SIO Receive Control Register receive status bit  SIO Receive Control Register reception finished bit  SIO Receive Control Register receive error sum bit  SIO Receive Control Register overrun error bit  SIO Receive Control Register parity error bit  SIO Receive Control Register framing error bit The manner in which the reception finished bit and various error flags are cleared differs depending on whether an overrun error occurred, as described below. [When an overrun error did not occur] Cleared by reading out the lower byte of the receive buffer register or by clearing the receive enable bit. [When an overrun error occurred] Cleared by only clearing the receive enable bit.

13.1 Outline of the CAN Module

13.2 CAN Module Related Registers

13.3 CAN Protocol

13.4 Initializing the CAN Module

13.5 Transmitting Data Frames

13.6 Receiving Data Frames

13.7 Transmitting Remote Frames

13.8 Receiving Remote Frames

13.9 Precautions about CAN Module

13-2 32180 Group User’s Manual (Rev.1.0) CAN MODULE The 32180 contains two-channel Full CAN modules compliant with CAN (Controller Area Network) Specification V2.0 B Active. These CAN modules each have 16 message slots and three mask registers, effective use of which helps to reduce the data processing load of the CPU. The CAN modules are outlined below. Table 13.1.1 Outline of the CAN Module Item Description Protocol CAN Specification V2.0 B Active Number of message slots Total 16 slots (14 global slots, two local slots) Polarity 0: Dominant 1: Recessive Acceptance filter Global mask: 1 (Function to receive only a rangeLocal mask: 2 of IDs specified by receive ID filter) Baud rate 1 time quantum (Tq) = (BRP + 1) / (CPU clock/2) (BRP: Baud Rate Prescaler set value) Tq period × number of Tq’s for one bit BRP: 1–55 (0: inhibited) Number of Tq’s for one bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 Propagation Segment: 1–8Tq Phase Segment 1: 1–8Tq Phase Segment 2: 1–8Tq (IPT = "1") Remote frame automatic The slot that received a remote frame responds by automatically sending a data frame. response function Timestamp function This function is implemented using a 16-bit counter. The count period is derived from the CAN bus bit period by dividing it by 1, 2, 3 or 4. BasicCAN mode BasicCAN function is materialized using two local slots. Transmit abort function Transmit requests can be canceled. Loopback function The CAN module receives the data transmitted by itself. Return bus off function Error active mode is forcibly entered into after clearing the error counter. Single shot function Transmission is not retried even when it failed due to arbitration-lost or a transmit error. DMA transfer function DMA transfer request is generated when transmission failed or transmit/receive operation finished (CAN0 only). Self-diagnostic function Communication module is diagnosed by communicating internally in the CAN module. Note 1: The maximum allowable error of oscillation depends on the system configuration (e.g., bus length, clock error, CAN bus transceiver, sampling position and bit configuration). Table 13.1.2 DMA Transfer Requests Generated by CAN DMA Transfer Request by CAN DMAC Input Channel CAN0: Slot 0 transmission failed or slot 15 transmit/receive operation finishedDMA0 CAN1: Slot 1 transmission failed or slot 14 transmit/receive operation finishedDMA2

32180 Group User’s Manual (Rev.1.0) CAN MODULE Table 13.1.3 Interrupt Requests Generated by CAN Modules CAN Module Interrupt Request Source ICU Input Interrupt Source CAN0 transmission completed CAN0 transmit/receive & error interrupt CAN1 transmission completed CAN1 transmit/receive & error interrupt CAN0 reception completed CAN0 transmit/receive & error interrupt CAN1 reception completed CAN1 transmit/receive & error interrupt CAN0 bus error CAN0 transmit/receive & error interrupt CAN1 bus error CAN1 transmit/receive & error interrupt CAN0 error passive CAN0 transmit/receive & error interrupt CAN1 error passive CAN1 transmit/receive & error interrupt CAN0 bus off CAN0 transmit/receive & error interrupt CAN1 bus off CAN1 transmit/receive & error interrupt CAN0 single shot CAN0 transmit/receive & error interrupt CAN1 single shot CAN1 transmit/receive & error interrupt Acceptance Filter Self- diagnosis Control Baud Rate Prescaler CPUCLK Message Slot × 16 Transmit/receive completed, error or single shot DMA0, 2 CAN0 Internal data bus Interrupt CTX0 CRX0 DAM Request CAN Protocol Controller Acceptance Filter Self- diagnosis Control Baud Rate Prescaler CPUCLK Message Slot × 16 Transmit/receive completed, error or single shot CAN1 Interrupt CTX1 CRX1 CAN Protocol Controller Figure 13.1.1 Block Diagram of the CAN Modules

13-4 32180 Group User’s Manual (Rev.1.0) CAN MODULE Shown below is a CAN module related register map. CAN Module Related Register Map (1/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1000 CAN0 Control Register 13-15 (CAN0CNT) H'0080 1002 CAN0 Status Register 13-18 (CAN0STAT) H'0080 1004 CAN0 Frame Format Select Register 13-21 (CAN0FFS) H'0080 1006 CAN0 Configuration Register 13-22 (CAN0CONF) H'0080 1008 CAN0 Timestamp Count Register 13-24 (CAN0TSTMP) H'0080 100A CAN0 Receive Error Count Register CAN0 Transmit Error Count Register 13-25 (CAN0REC) (CAN0TEC) H'0080 100C CAN0 Slot Interrupt Request Status Register 13-29 (CAN0SLIST) H'0080 100E (Use inhibited area) H'0080 1010 CAN0 Slot Interrupt Request Enable Register 13-30 (CAN0SLIEN) H'0080 1012 (Use inhibited area) H'0080 1014 CAN0 Error Interrupt Request Status Register CAN0 Error Interrupt Request Enable Register 13-31 (CAN0ERIST) (CAN0ERIEN) 13-32 H'0080 1016 CAN0 Baud Rate Prescaler CAN0 Cause of Error Register 13-26 (CAN0BRP) (CAN0EF) 13-45 H'0080 1018 CAN0 Mode Register CAN0 DMA Transfer Request Select Register 13-46 (CAN0MOD) (CAN0DMARQ) 13-47 (Use inhibited area) H'0080 1028 CAN0 Global Mask Register Standard ID0 CAN0 Global Mask Register Standard ID1 13-48 (C0GMSKS0) (C0GMSKS1) H'0080 102A CAN0 Global Mask Register Extended ID0 CAN0 Global Mask Register Extended ID1 13-49 (C0GMSKE0) (C0GMSKE1) H'0080 102C CAN0 Global Mask Register Extended ID2 (Use inhibited area) 13-50 (C0GMSKE2) H'0080 102E (Use inhibited area) H'0080 1030 CAN0 Local Mask Register A Standard ID0 CAN0 Local Mask Register A Standard ID1 13-48 (C0LMSKAS0) (C0LMSKAS1) H'0080 1032 CAN0 Local Mask Register A Extended ID0 CAN0 Local Mask Register A Extended ID1 13-49 (C0LMSKAE0) (C0LMSKAE1) H'0080 1034 CAN0 Local Mask Register A Extended ID2 (Use inhibited area) 13-50 (C0LMSKAE2) H'0080 1036 (Use inhibited area) H'0080 1038 CAN0 Local Mask Register B Standard ID0 CAN0 Local Mask Register B Standard ID1 13-48 (C0LMSKBS0) (C0LMSKBS1) H'0080 103A CAN0 Local Mask Register B Extended ID0 CAN0 Local Mask Register B Extended ID1 13-49 (C0LMSKBE0) (C0LMSKBE1) H'0080 103C CAN0 Local Mask Register B Extended ID2 (Use inhibited area) 13-50 (C0LMSKBE2) H'0080 103E (Use inhibited area) H'0080 1040 CAN0 Single-Shot Mode Control Register 13-52 (CAN0SSMODE) H'0080 1042 (Use inhibited area) H'0080 1044 CAN0 Single-Shot Interrupt Request Status Register 13-33 (CAN0SSIST) H'0080 1046 (Use inhibited area) H'0080 1048 CAN0 Single-Shot Interrupt Request Enable Register 13-34 (CAN0SSIEN)

32180 Group User’s Manual (Rev.1.0) CAN Module Related Register Map (2/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1050 CAN0 Message Slot 0 Control Register CAN0 Message Slot 1 Control Register 13-53 (C0MSL0CNT) (C0MSL1CNT) H'0080 1052 CAN0 Message Slot 2 Control Register CAN0 Message Slot 3 Control Register 13-53 (C0MSL2CNT) (C0MSL3CNT) H'0080 1054 CAN0 Message Slot 4 Control Register CAN0 Message Slot 5 Control Register 13-53 (C0MSL4CNT) (C0MSL5CNT) H'0080 1056 CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register 13-53 (C0MSL6CNT) (C0MSL7CNT) H'0080 1058 CAN0 Message Slot 8 Control Register CAN0 Message Slot 9 Control Register 13-53 (C0MSL8CNT) (C0MSL9CNT) H'0080 105A CAN0 Message Slot 10 Control Register CAN0 Message Slot 11 Control Register 13-53 (C0MSL10CNT) (C0MSL11CNT) H'0080 105C CAN0 Message Slot 12 Control Register CAN0 Message Slot 13 Control Register 13-53 (C0MSL12CNT) (C0MSL13CNT) H'0080 105E CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register 13-53 (C0MSL14CNT) (C0MSL15CNT) (Use inhibited area) H'0080 1100 CAN0 Message Slot 0 Standard ID0 CAN0 Message Slot 0 Standard ID1 13-57 (C0MSL0SID0) (C0MSL0SID1) 13-58 H'0080 1102 CAN0 Message Slot 0 Extended ID0 CAN0 Message Slot 0 Extended ID1 13-59 (C0MSL0EID0) (C0MSL0EID1) 13-60 H'0080 1104 CAN0 Message Slot 0 Extended ID2 CAN0 Message Slot 0 Data Length Register 13-61 (C0MSL0EID2) (C0MSL0DLC) 13-62 H'0080 1106 CAN0 Message Slot 0 Data 0 CAN0 Message Slot 0 Data 1 13-63 (C0MSL0DT0) (C0MSL0DT1) 13-64 H'0080 1108 CAN0 Message Slot 0 Data 2 CAN0 Message Slot 0 Data 3 13-65 (C0MSL0DT2) (C0MSL0DT3) 13-66 H'0080 110A CAN0 Message Slot 0 Data 4 CAN0 Message Slot 0 Data 5 13-67 (C0MSL0DT4) (C0MSL0DT5) 13-68 H'0080 110C CAN0 Message Slot 0 Data 6 CAN0 Message Slot 0 Data 7 13-69 (C0MSL0DT6) (C0MSL0DT7) 13-70 H'0080 110E CAN0 Message Slot 0 Timestamp 13-71 (C0MSL0TSP) H'0080 1110 CAN0 Message Slot 1 Standard ID0 CAN0 Message Slot 1 Standard ID1 13-57 (C0MSL1SID0) (C0MSL1SID1) 13-58 H'0080 1112 CAN0 Message Slot 1 Extended ID0 CAN0 Message Slot 1 Extended ID1 13-59 (C0MSL1EID0) (C0MSL1EID1) 13-60 H'0080 1114 CAN0 Message Slot 1 Extended ID2 CAN0 Message Slot 1 Data Length Register 13-61 (C0MSL1EID2) (C0MSL1DLC) 13-62 H'0080 1116 CAN0 Message Slot 1 Data 0 CAN0 Message Slot 1 Data 1 13-63 (C0MSL1DT0) (C0MSL1DT1) 13-64 H'0080 1118 CAN0 Message Slot 1 Data 2 CAN0 Message Slot 1 Data 3 13-65 (C0MSL1DT2) (C0MSL1DT3) 13-66 H'0080 111A CAN0 Message Slot 1 Data 4 CAN0 Message Slot 1 Data 5 13-67 (C0MSL1DT4) (C0MSL1DT5) 13-68 H'0080 111C CAN0 Message Slot 1 Data 6 CAN0 Message Slot 1 Data 7 13-69 (C0MSL1DT6) (C0MSL1DT7) 13-70 H'0080 111E CAN0 Message Slot 1 Timestamp 13-71 (C0MSL1TSP) H'0080 1120 CAN0 Message Slot 2 Standard ID0 CAN0 Message Slot 2 Standard ID1 13-57 (C0MSL2SID0) (C0MSL2SID1) 13-58 H'0080 1122 CAN0 Message Slot 2 Extended ID0 CAN0 Message Slot 2 Extended ID1 13-59 (C0MSL2EID0) (C0MSL2EID1) 13-60 H'0080 1124 CAN0 Message Slot 2 Extended ID2 CAN0 Message Slot 2 Data Length Register 13-61 (C0MSL2EID2) (C0MSL2DLC) 13-62 H'0080 1126 CAN0 Message Slot 2 Data 0 CAN0 Message Slot 2 Data 1 13-63 (C0MSL2DT0) (C0MSL2DT1) 13-64 H'0080 1128 CAN0 Message Slot 2 Data 2 CAN0 Message Slot 2 Data 3 13-65 (C0MSL2DT2) (C0MSL2DT3) 13-66 H'0080 112A CAN0 Message Slot 2 Data 4 CAN0 Message Slot 2 Data 5 13-67 (C0MSL2DT4) (C0MSL2DT5) 13-68 H'0080 112C CAN0 Message Slot 2 Data 6 CAN0 Message Slot 2 Data 7 13-69 (C0MSL2DT6) (C0MSL2DT7) 13-70 H'0080 112E CAN0 Message Slot 2 Timestamp 13-71 (C0MSL2TSP)

13-6 32180 Group User’s Manual (Rev.1.0) CAN MODULE CAN Module Related Register Map (3/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1130 CAN0 Message Slot 3 Standard ID0 CAN0 Message Slot 3 Standard ID1 13-57 (C0MSL3SID0) (C0MSL3SID1) 13-58 H'0080 1132 CAN0 Message Slot 3 Extended ID0 CAN0 Message Slot 3 Extended ID1 13-59 (C0MSL3EID0) (C0MSL3EID1) 13-60 H'0080 1134 CAN0 Message Slot 3 Extended ID2 CAN0 Message Slot 3 Data Length Register 13-61 (C0MSL3EID2) (C0MSL3DLC) 13-62 H'0080 1136 CAN0 Message Slot 3 Data 0 CAN0 Message Slot 3 Data 1 13-63 (C0MSL3DT0) (C0MSL3DT1) 13-64 H'0080 1138 CAN0 Message Slot 3 Data 2 CAN0 Message Slot 3 Data 3 13-65 (C0MSL3DT2) (C0MSL3DT3) 13-66 H'0080 113A CAN0 Message Slot 3 Data 4 CAN0 Message Slot 3 Data 5 13-67 (C0MSL3DT4) (C0MSL3DT5) 13-68 H'0080 113C CAN0 Message Slot 3 Data 6 CAN0 Message Slot 3 Data 7 13-69 (C0MSL3DT6) (C0MSL3DT7) 13-70 H'0080 113E CAN0 Message Slot 3 Timestamp 13-71 (C0MSL3TSP) H'0080 1140 CAN0 Message Slot 4 Standard ID0 CAN0 Message Slot 4 Standard ID1 13-57 (C0MSL4SID0) (C0MSL4SID1) 13-58 H'0080 1142 CAN0 Message Slot 4 Extended ID0 CAN0 Message Slot 4 Extended ID1 13-59 (C0MSL4EID0) (C0MSL4EID1) 13-60 H'0080 1144 CAN0 Message Slot 4 Extended ID2 CAN0 Message Slot 4 Data Length Register 13-61 (C0MSL4EID2) (C0MSL4DLC) 13-62 H'0080 1146 CAN0 Message Slot 4 Data 0 CAN0 Message Slot 4 Data 1 13-63 (C0MSL4DT0) (C0MSL4DT1) 13-64 H'0080 1148 CAN0 Message Slot 4 Data 2 CAN0 Message Slot 4 Data 3 13-65 (C0MSL4DT2) (C0MSL4DT3) 13-66 H'0080 114A CAN0 Message Slot 4 Data 4 CAN0 Message Slot 4 Data 5 13-67 (C0MSL4DT4) (C0MSL4DT5) 13-68 H'0080 114C CAN0 Message Slot 4 Data 6 CAN0 Message Slot 4 Data 7 13-69 (C0MSL4DT6) (C0MSL4DT7) 13-70 H'0080 114E CAN0 Message Slot 4 Timestamp 13-71 (C0MSL4TSP) H'0080 1150 CAN0 Message Slot 5 Standard ID0 CAN0 Message Slot 5 Standard ID1 13-57 (C0MSL5SID0) (C0MSL5SID1) 13-58 H'0080 1152 CAN0 Message Slot 5 Extended ID0 CAN0 Message Slot 5 Extended ID1 13-59 (C0MSL5EID0) (C0MSL5EID1) 13-60 H'0080 1154 CAN0 Message Slot 5 Extended ID2 CAN0 Message Slot 5 Data Length Register 13-61 (C0MSL5EID2) (C0MSL5DLC) 13-62 H'0080 1156 CAN0 Message Slot 5 Data 0 CAN0 Message Slot 5 Data 1 13-63 (C0MSL5DT0) (C0MSL5DT1) 13-64 H'0080 1158 CAN0 Message Slot 5 Data 2 CAN0 Message Slot 5 Data 3 13-65 (C0MSL5DT2) (C0MSL5DT3) 13-66 H'0080 115A CAN0 Message Slot 5 Data 4 CAN0 Message Slot 5 Data 5 13-67 (C0MSL5DT4) (C0MSL5DT5) 13-68 H'0080 115C CAN0 Message Slot 5 Data 6 CAN0 Message Slot 5 Data 7 13-69 (C0MSL5DT6) (C0MSL5DT7) 13-70 H'0080 115E CAN0 Message Slot 5 Timestamp 13-71 (C0MSL5TSP) H'0080 1160 CAN0 Message Slot 6 Standard ID0 CAN0 Message Slot 6 Standard ID1 13-57 (C0MSL6SID0) (C0MSL6SID1) 13-58 H'0080 1162 CAN0 Message Slot 6 Extended ID0 CAN0 Message Slot 6 Extended ID1 13-59 (C0MSL6EID0) (C0MSL6EID1) 13-60 H'0080 1164 CAN0 Message Slot 6 Extended ID2 CAN0 Message Slot 6 Data Length Register 13-61 (C0MSL6EID2) (C0MSL6DLC) 13-62 H'0080 1166 CAN0 Message Slot 6 Data 0 CAN0 Message Slot 6 Data 1 13-63 (C0MSL6DT0) (C0MSL6DT1) 13-64 H'0080 1168 CAN0 Message Slot 6 Data 2 CAN0 Message Slot 6 Data 3 13-65 (C0MSL6DT2) (C0MSL6DT3) 13-66 H'0080 116A CAN0 Message Slot 6 Data 4 CAN0 Message Slot 6 Data 5 13-67 (C0MSL6DT4) (C0MSL6DT5) 13-68 H'0080 116C CAN0 Message Slot 6 Data 6 CAN0 Message Slot 6 Data 7 13-69 (C0MSL6DT6) (C0MSL6DT7) 13-70 H'0080 116E CAN0 Message Slot 6 Timestamp 13-71 (C0MSL6TSP)

32180 Group User’s Manual (Rev.1.0) CAN Module Related Register Map (4/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1170 CAN0 Message Slot 7 Standard ID0 CAN0 Message Slot 7 Standard ID1 13-57 (C0MSL7SID0) (C0MSL7SID1) 13-58 H'0080 1172 CAN0 Message Slot 7 Extended ID0 CAN0 Message Slot 7 Extended ID1 13-59 (C0MSL7EID0) (C0MSL7EID1) 13-60 H'0080 1174 CAN0 Message Slot 7 Extended ID2 CAN0 Message Slot 6 Data Length Register 13-61 (C0MSL7EID2) (C0MSL7DLC) 13-62 H'0080 1176 CAN0 Message Slot 7 Data 0 CAN0 Message Slot 7 Data 1 13-63 (C0MSL7DT0) (C0MSL7DT1) 13-64 H'0080 1178 CAN0 Message Slot 7 Data 2 CAN0 Message Slot 7 Data 3 13-65 (C0MSL7DT2) (C0MSL7DT3) 13-66 H'0080 117A CAN0 Message Slot 7 Data 4 CAN0 Message Slot 7 Data 5 13-67 (C0MSL7DT4) (C0MSL7DT5) 13-68 H'0080 117C CAN0 Message Slot 7 Data 6 CAN0 Message Slot 7 Data 7 13-69 (C0MSL7DT6) (C0MSL7DT7) 13-70 H'0080 117E CAN0 Message Slot 7 Timestamp 13-71 (C0MSL7TSP) H'0080 1180 CAN0 Message Slot 8 Standard ID0 CAN0 Message Slot 8 Standard ID1 13-57 (C0MSL8SID0) (C0MSL8SID1) 13-58 H'0080 1182 CAN0 Message Slot 8 Extended ID0 CAN0 Message Slot 8 Extended ID1 13-59 (C0MSL8EID0) (C0MSL8EID1) 13-60 H'0080 1184 CAN0 Message Slot 8 Extended ID2 CAN0 Message Slot 8 Data Length Register 13-61 (C0MSL8EID2) (C0MSL8DLC) 13-62 H'0080 1186 CAN0 Message Slot 8 Data 0 CAN0 Message Slot 8 Data 1 13-63 (C0MSL8DT0) (C0MSL8DT1) 13-64 H'0080 1188 CAN0 Message Slot 8 Data 2 CAN0 Message Slot 8 Data 3 13-65 (C0MSL8DT2) (C0MSL8DT3) 13-66 H'0080 118A CAN0 Message Slot 8 Data 4 CAN0 Message Slot 8 Data 5 13-67 (C0MSL8DT4) (C0MSL8DT5) 13-68 H'0080 118C CAN0 Message Slot 8 Data 6 CAN0 Message Slot 8 Data 7 13-69 (C0MSL8DT6) (C0MSL8DT7) 13-70 H'0080 118E CAN0 Message Slot 8 Timestamp 13-71 (C0MSL8TSP) H'0080 1190 CAN0 Message Slot 9 Standard ID0 CAN0 Message Slot 9 Standard ID1 13-57 (C0MSL9SID0) (C0MSL9SID1) 13-58 H'0080 1192 CAN0 Message Slot 9 Extended ID0 CAN0 Message Slot 9 Extended ID1 13-59 (C0MSL9EID0) (C0MSL9EID1) 13-60 H'0080 1194 CAN0 Message Slot 9 Extended ID2 CAN0 Message Slot 9 Data Length Register 13-61 (C0MSL9EID2) (C0MSL9DLC) 13-62 H'0080 1196 CAN0 Message Slot 9 Data 0 CAN0 Message Slot 9 Data 1 13-63 (C0MSL9DT0) (C0MSL9DT1) 13-64 H'0080 1198 CAN0 Message Slot 9 Data 2 CAN0 Message Slot 9 Data 3 13-65 (C0MSL9DT2) (C0MSL9DT3) 13-66 H'0080 119A CAN0 Message Slot 9 Data 4 CAN0 Message Slot 9 Data 5 13-67 (C0MSL9DT4) (C0MSL9DT5) 13-68 H'0080 119C CAN0 Message Slot 9 Data 6 CAN0 Message Slot 9 Data 7 13-69 (C0MSL9DT6) (C0MSL9DT7) 13-70 H'0080 119E CAN0 Message Slot 9 Timestamp 13-71 (C0MSL9TSP) H'0080 11A0 CAN0 Message Slot 10 Standard ID0 CAN0 Message Slot 10 Standard ID1 13-57 (C0MSL10SID0) (C0MSL10SID1) 13-58 H'0080 11A2 CAN0 Message Slot 10 Extended ID0 CAN0 Message Slot 10 Extended ID1 13-59 (C0MSL10EID0) (C0MSL10EID1) 13-60 H'0080 11A4 CAN0 Message Slot 10 Extended ID2 CAN0 Message Slot 10 Data Length Register 13-61 (C0MSL10EID2) (C0MSL10DLC) 13-62 H'0080 11A6 CAN0 Message Slot 10 Data 0 CAN0 Message Slot 10 Data 1 13-63 (C0MSL10DT0) (C0MSL10DT1) 13-64 H'0080 11A8 CAN0 Message Slot 10 Data 2 CAN0 Message Slot 10 Data 3 13-65 (C0MSL10DT2) (C0MSL10DT3) 13-66 H'0080 11AA CAN0 Message Slot 10 Data 4 CAN0 Message Slot 10 Data 5 13-67 (C0MSL10DT4) (C0MSL10DT5) 13-68 H'0080 11AC CAN0 Message Slot 10 Data 6 CAN0 Message Slot 10 Data 7 13-69 (C0MSL10DT6) (C0MSL10DT7) 13-70 H'0080 11AE CAN0 Message Slot 10 Timestamp 13-71 (C0MSL10TSP)

13-8 32180 Group User’s Manual (Rev.1.0) CAN MODULE CAN Module Related Register Map (5/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 11B0 CAN0 Message Slot 11 Standard ID0 CAN0 Message Slot 11 Standard ID1 13-57 (C0MSL11SID0) (C0MSL11SID1) 13-58 H'0080 11B2 CAN0 Message Slot 11 Extended ID0 CAN0 Message Slot 11 Extended ID1 13-59 (C0MSL11EID0) (C0MSL11EID1) 13-60 H'0080 11B4 CAN0 Message Slot 11 Extended ID2 CAN0 Message Slot 11 Data Length Register 13-61 (C0MSL11EID2) (C0MSL11DLC) 13-62 H'0080 11B6 CAN0 Message Slot 11 Data 0 CAN0 Message Slot 11 Data 1 13-63 (C0MSL11DT0) (C0MSL11DT1) 13-64 H'0080 11B8 CAN0 Message Slot 11 Data 2 CAN0 Message Slot 11 Data 3 13-65 (C0MSL11DT2) (C0MSL11DT3) 13-66 H'0080 11BA CAN0 Message Slot 11 Data 4 CAN0 Message Slot 11 Data 5 13-67 (C0MSL11DT4) (C0MSL11DT5) 13-68 H'0080 11BC CAN0 Message Slot 11 Data 6 CAN0 Message Slot 11 Data 7 13-69 (C0MSL11DT6) (C0MSL11DT7) 13-70 H'0080 11BE CAN0 Message Slot 11 Timestamp 13-71 (C0MSL11TSP) H'0080 11C0 CAN0 Message Slot 12 Standard ID0 CAN0 Message Slot 12 Standard ID1 13-57 (C0MSL12SID0) (C0MSL12SID1) 13-58 H'0080 11C2 CAN0 Message Slot 12 Extended ID0 CAN0 Message Slot 12 Extended ID1 13-59 (C0MSL12EID0) (C0MSL12EID1) 13-60 H'0080 11C4 CAN0 Message Slot 12 Extended ID2 CAN0 Message Slot 12 Data Length Register 13-61 (C0MSL12EID2) (C0MSL12DLC) 13-62 H'0080 11C6 CAN0 Message Slot 12 Data 0 CAN0 Message Slot 12 Data 1 13-63 (C0MSL12DT0) (C0MSL12DT1) 13-64 H'0080 11C8 CAN0 Message Slot 12 Data 2 CAN0 Message Slot 12 Data 3 13-65 (C0MSL12DT2) (C0MSL12DT3) 13-66 H'0080 11CA CAN0 Message Slot 12 Data 4 CAN0 Message Slot 12 Data 5 13-67 (C0MSL12DT4) (C0MSL12DT5) 13-68 H'0080 11CC CAN0 Message Slot 12 Data 6 CAN0 Message Slot 12 Data 7 13-69 (C0MSL12DT6) (C0MSL12DT7) 13-70 H'0080 11CE CAN0 Message Slot 12 Timestamp 13-71 (C0MSL12TSP) H'0080 11D0 CAN0 Message Slot 13 Standard ID0 CAN0 Message Slot 13 Standard ID1 13-57 (C0MSL13SID0) (C0MSL13SID1) 13-58 H'0080 11D2 CAN0 Message Slot 13 Extended ID0 CAN0 Message Slot 13 Extended ID1 13-59 (C0MSL13EID0) (C0MSL13EID1) 13-60 H'0080 11D4 CAN0 Message Slot 13 Extended ID2 CAN0 Message Slot 13 Data Length Register 13-61 (C0MSL13EID2) (C0MSL13DLC) 13-62 H'0080 11D6 CAN0 Message Slot 13 Data 0 CAN0 Message Slot 13 Data 1 13-63 (C0MSL13DT0) (C0MSL13DT1) 13-64 H'0080 11D8 CAN0 Message Slot 13 Data 2 CAN0 Message Slot 13 Data 3 13-65 (C0MSL13DT2) (C0MSL13DT3) 13-66 H'0080 11DA CAN0 Message Slot 13 Data 4 CAN0 Message Slot 13 Data 5 13-67 (C0MSL13DT4) (C0MSL13DT5) 13-68 H'0080 11DC CAN0 Message Slot 13 Data 6 CAN0 Message Slot 13 Data 7 13-69 (C0MSL13DT6) (C0MSL13DT7) 13-70 H'0080 11DE CAN0 Message Slot 13 Timestamp 13-71 (C0MSL13TSP) H'0080 11E0 CAN0 Message Slot 14 Standard ID0 CAN0 Message Slot 14 Standard ID1 13-57 (C0MSL14SID0) (C0MSL14SID1) 13-58 H'0080 11E2 CAN0 Message Slot 14 Extended ID0 CAN0 Message Slot 14 Extended ID1 13-59 (C0MSL14EID0) (C0MSL14EID1) 13-60 H'0080 11E4 CAN0 Message Slot 14 Extended ID2 CAN0 Message Slot 14 Data Length Register 13-61 (C0MSL14EID2) (C0MSL14DLC) 13-62 H'0080 11E6 CAN0 Message Slot 14 Data 0 CAN0 Message Slot 14 Data 1 13-63 (C0MSL14DT0) (C0MSL14DT1) 13-64 H'0080 11E8 CAN0 Message Slot 14 Data 2 CAN0 Message Slot 14 Data 3 13-65 (C0MSL14DT2) (C0MSL14DT3) 13-66 H'0080 11EA CAN0 Message Slot 14 Data 4 CAN0 Message Slot 14 Data 5 13-67 (C0MSL14DT4) (C0MSL14DT5) 13-68 H'0080 11EC CAN0 Message Slot 14 Data 6 CAN0 Message Slot 14 Data 7 13-69 (C0MSL14DT6) (C0MSL14DT7) 13-70 H'0080 11EE CAN0 Message Slot 14 Timestamp 13-71 (C0MSL14TSP)

32180 Group User’s Manual (Rev.1.0) CAN Module Related Register Map (6/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 11F0 CAN0 Message Slot 15 Standard ID0 CAN0 Message Slot 15 Standard ID1 13-57 (C0MSL15SID0) (C0MSL15SID1) 13-58 H'0080 11F2 CAN0 Message Slot 15 Extended ID0 CAN0 Message Slot 15 Extended ID1 13-59 (C0MSL15EID0) (C0MSL15EID1) 13-60 H'0080 11F4 CAN0 Message Slot 15 Extended ID2 CAN0 Message Slot 15 Data Length Register 13-61 (C0MSL15EID2) (C0MSL15DLC) 13-62 H'0080 11F6 CAN0 Message Slot 15 Data 0 CAN0 Message Slot 15 Data 1 13-63 (C0MSL15DT0) (C0MSL15DT1) 13-64 H'0080 11F8 CAN0 Message Slot 15 Data 2 CAN0 Message Slot 15 Data 3 13-65 (C0MSL15DT2) (C0MSL15DT3) 13-66 H'0080 11FA CAN0 Message Slot 15 Data 4 CAN0 Message Slot 15 Data 5 13-67 (C0MSL15DT4) (C0MSL15DT5) 13-68 H'0080 11FC CAN0 Message Slot 15 Data 6 CAN0 Message Slot 15 Data 7 13-69 (C0MSL15DT6) (C0MSL15DT7) 13-70 H'0080 11FE CAN0 Message Slot 15 Timestamp 13-71 (C0MSL15TSP) (Use inhibited area) H'0080 1400 CAN1 Control Register 13-15 (CAN1CNT) H'0080 1402 CAN1 Status Register 13-18 (CAN1STAT) H'0080 1404 CAN1 Frame Format Select Register 13-21 (CAN1FFS) H'0080 1406 CAN1 Configuration Register 13-22 (CAN1CONF) H'0080 1408 CAN1 Timestamp Count Register 13-24 (CAN1TSTMP) H'0080 140A CAN1 Receive Error Count Register CAN1 Transmit Error Count Register 13-25 (CAN1REC) (CAN1TEC) H'0080 140C CAN1 Slot Interrupt Request Status Register 13-29 (CAN1SLIST) H'0080 140E (Use inhibited area) H'0080 1410 CAN1 Slot Interrupt Request Enable Register 13-30 (CAN1SLIEN) H'0080 1412 (Use inhibited area) H'0080 1414 CAN1 Error Interrupt Request Status Register CAN1 Error Interrupt Request Enable Register 13-31 (CAN1ERIST) (CAN1ERIEN) 13-32 H'0080 1416 CAN1 Baud Rate Prescaler CAN1 Cause of Error Register 13-26 (CAN1BRP) (CAN1EF) 13-45 H'0080 1418 CAN1 Mode Register (Use inhibited area) 13-46 (CAN1MOD) (Use inhibited area) H'0080 1428 CAN1 Global Mask Register Standard ID0 CAN1 Global Mask Register Standard ID1 13-48 (C1GMSKS0) (C1GMSKS1) H'0080 142A CAN1 Global Mask Register Extended ID0 CAN1 Global Mask Register Extended ID1 13-49 (C1GMSKE0) (C1GMSKE1) H'0080 142C CAN1 Global Mask Register Extended ID2 (Use inhibited area) 13-50 (C1GMSKE2) H'0080 142E (Use inhibited area) H'0080 1430 CAN1 Local Mask Register A Standard ID0 CAN1 Local Mask Register A Standard ID1 13-48 (C1LMSKAS0) (C1LMSKAS1) H'0080 1432 CAN1 Local Mask Register A Extended ID0 CAN1 Local Mask Register A Extended ID1 13-49 (C1LMSKAE0) (C1LMSKAE1) H'0080 1434 CAN1 Local Mask Register A Extended ID2 (Use inhibited area) 13-50 (C1LMSKAE2) H'0080 1436 (Use inhibited area) H'0080 1438 CAN1 Local Mask Register B Standard ID0 CAN1 Local Mask Register B Standard ID1 13-48 (C1LMSKBS0) (C1LMSKBS1) H'0080 143A CAN1 Local Mask Register B Extended ID0 CAN1 Local Mask Register B Extended ID1 13-49 (C1LMSKBE0) (C1LMSKBE1) H'0080 143C CAN1 Local Mask Register B Extended ID2 (Use inhibited area) 13-50 (C1LMSKBE2) H'0080 143E (Use inhibited area)

13-10 32180 Group User’s Manual (Rev.1.0) CAN MODULE CAN Module Related Register Map (7/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1440 CAN1 Single-Shot Mode Control Register 13-52 (CAN1SSMODE) H'0080 1442 (Use inhibited area) H'0080 1444 CAN1 Single-Shot Interrupt Request Status Register 13-33 (CAN1SSIST) H'0080 1446 (Use inhibited area) H'0080 1448 CAN1 Single-Shot Interrupt Request Enable Register 13-34 (CAN1SSIEN) (Use inhibited area) H'0080 1450 CAN1 Message Slot 0 Control Register CAN1 Message Slot 1 Control Register 13-53 (C1MSL0CNT) (C1MSL1CNT) H'0080 1452 CAN1 Message Slot 2 Control Register CAN1 Message Slot 3 Control Register 13-53 (C1MSL2CNT) (C1MSL3CNT) H'0080 1454 CAN1 Message Slot 4 Control Register CAN1 Message Slot 5 Control Register 13-53 (C1MSL4CNT) (C1MSL5CNT) H'0080 1456 CAN1 Message Slot 6 Control Register CAN1 Message Slot 7 Control Register 13-53 (C1MSL6CNT) (C1MSL7CNT) H'0080 1458 CAN1 Message Slot 8 Control Register CAN1 Message Slot 9 Control Register 13-53 (C1MSL8CNT) (C1MSL9CNT) H'0080 145A CAN1 Message Slot 10 Control Register CAN1 Message Slot 11 Control Register 13-53 (C1MSL10CNT) (C1MSL11CNT) H'0080 145C CAN1 Message Slot 12 Control Register CAN1 Message Slot 13 Control Register 13-53 (C1MSL12CNT) (C1MSL13CNT) H'0080 145E CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register 13-53 (C1MSL14CNT) (C1MSL15CNT) (Use inhibited area) H'0080 1500 CAN1 Message Slot 0 Standard ID0 CAN1 Message Slot 0 Standard ID1 13-57 (C1MSL0SID0) (C1MSL0SID1) 13-58 H'0080 1502 CAN1 Message Slot 0 Extended ID0 CAN1 Message Slot 0 Extended ID1 13-59 (C1MSL0EID0) (C1MSL0EID1) 13-60 H'0080 1504 CAN1 Message Slot 0 Extended ID2 CAN1 Message Slot 0 Data Length Register 13-61 (C1MSL0EID2) (C1MSL0DLC) 13-62 H'0080 1506 CAN1 Message Slot 0 Data 0 CAN1 Message Slot 0 Data 1 13-63 (C1MSL0DT0) (C1MSL0DT1) 13-64 H'0080 1508 CAN1 Message Slot 0 Data 2 CAN1 Message Slot 0 Data 3 13-65 (C1MSL0DT2) (C1MSL0DT3) 13-66 H'0080 150A CAN1 Message Slot 0 Data 4 CAN1 Message Slot 0 Data 5 13-67 (C1MSL0DT4) (C1MSL0DT5) 13-68 H'0080 150C CAN1 Message Slot 0 Data 6 CAN1 Message Slot 0 Data 7 13-69 (C1MSL0DT6) (C1MSL0DT7) 13-70 H'0080 150E CAN1 Message Slot 0 Timestamp 13-71 (C1MSL0TSP) H'0080 1510 CAN1 Message Slot 1 Standard ID0 CAN1 Message Slot 1 Standard ID1 13-57 (C1MSL1SID0) (C1MSL1SID1) 13-58 H'0080 1512 CAN1 Message Slot 1 Extended ID0 CAN1 Message Slot 1 Extended ID1 13-59 (C1MSL1EID0) (C1MSL1EID1) 13-60 H'0080 1514 CAN1 Message Slot 1 Extended ID2 CAN1 Message Slot 1 Data Length Register 13-61 (C1MSL1EID2) (C1MSL1DLC) 13-62 H'0080 1516 CAN1 Message Slot 1 Data 0 CAN1 Message Slot 1 Data 1 13-63 (C1MSL1DT0) (C1MSL1DT1) 13-64 H'0080 1518 CAN1 Message Slot 1 Data 2 CAN1 Message Slot 1 Data 3 13-65 (C1MSL1DT2) (C1MSL1DT3) 13-66 H'0080 151A CAN1 Message Slot 1 Data 4 CAN1 Message Slot 1 Data 5 13-67 (C1MSL1DT4) (C1MSL1DT5) 13-68 H'0080 151C CAN1 Message Slot 1 Data 6 CAN1 Message Slot 1 Data 7 13-69 (C1MSL1DT6) (C1MSL1DT7) 13-70 H'0080 151E CAN1 Message Slot 1 Timestamp 13-71 (C1MSL1TSP)

32180 Group User’s Manual (Rev.1.0) CAN Module Related Register Map (8/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1520 CAN1 Message Slot 2 Standard ID0 CAN1 Message Slot 2 Standard ID1 13-57 (C1MSL2SID0) (C1MSL2SID1) 13-58 H'0080 1522 CAN1 Message Slot 2 Extended ID0 CAN1 Message Slot 2 Extended ID1 13-59 (C1MSL2EID0) (C1MSL2EID1) 13-60 H'0080 1524 CAN1 Message Slot 2 Extended ID2 CAN1 Message Slot 2 Data Length Register 13-61 (C1MSL2EID2) (C1MSL2DLC) 13-62 H'0080 1526 CAN1 Message Slot 2 Data 0 CAN1 Message Slot 2 Data 1 13-63 (C1MSL2DT0) (C1MSL2DT1) 13-64 H'0080 1528 CAN1 Message Slot 2 Data 2 CAN1 Message Slot 2 Data 3 13-65 (C1MSL2DT2) (C1MSL2DT3) 13-66 H'0080 152A CAN1 Message Slot 2 Data 4 CAN1 Message Slot 2 Data 5 13-67 (C1MSL2DT4) (C1MSL2DT5) 13-68 H'0080 152C CAN1 Message Slot 2 Data 6 CAN1 Message Slot 2 Data 7 13-69 (C1MSL2DT6) (C1MSL2DT7) 13-70 H'0080 152E CAN1 Message Slot 2 Timestamp 13-71 (C1MSL2TSP) H'0080 1530 CAN1 Message Slot 3 Standard ID0 CAN1 Message Slot 3 Standard ID1 13-57 (C1MSL3SID0) (C1MSL3SID1) 13-58 H'0080 1532 CAN1 Message Slot 3 Extended ID0 CAN1 Message Slot 3 Extended ID1 13-59 (C1MSL3EID0) (C1MSL3EID1) 13-60 H'0080 1534 CAN1 Message Slot 3 Extended ID2 CAN1 Message Slot 3 Data Length Register 13-61 (C1MSL3EID2) (C1MSL3DLC) 13-62 H'0080 1536 CAN1 Message Slot 3 Data 0 CAN1 Message Slot 3 Data 1 13-63 (C1MSL3DT0) (C1MSL3DT1) 13-64 H'0080 1538 CAN1 Message Slot 3 Data 2 CAN1 Message Slot 3 Data 3 13-65 (C1MSL3DT2) (C1MSL3DT3) 13-66 H'0080 153A CAN1 Message Slot 3 Data 4 CAN1 Message Slot 3 Data 5 13-67 (C1MSL3DT4) (C1MSL3DT5) 13-68 H'0080 153C CAN1 Message Slot 3 Data 6 CAN1 Message Slot 3 Data 7 13-69 (C1MSL3DT6) (C1MSL3DT7) 13-70 H'0080 153E CAN1 Message Slot 3 Timestamp 13-71 (C1MSL3TSP) H'0080 1540 CAN1 Message Slot 4 Standard ID0 CAN1 Message Slot 4 Standard ID1 13-57 (C1MSL4SID0) (C1MSL4SID1) 13-58 H'0080 1542 CAN1 Message Slot 4 Extended ID0 CAN1 Message Slot 4 Extended ID1 13-59 (C1MSL4EID0) (C1MSL4EID1) 13-60 H'0080 1544 CAN1 Message Slot 4 Extended ID2 CAN1 Message Slot 4 Data Length Register 13-61 (C1MSL4EID2) (C1MSL4DLC) 13-62 H'0080 1546 CAN1 Message Slot 4 Data 0 CAN1 Message Slot 4 Data 1 13-63 (C1MSL4DT0) (C1MSL4DT1) 13-64 H'0080 1548 CAN1 Message Slot 4 Data 2 CAN1 Message Slot 4 Data 3 13-65 (C1MSL4DT2) (C1MSL4DT3) 13-66 H'0080 154A CAN1 Message Slot 4 Data 4 CAN1 Message Slot 4 Data 5 13-67 (C1MSL4DT4) (C1MSL4DT5) 13-68 H'0080 154C CAN1 Message Slot 4 Data 6 CAN1 Message Slot 4 Data 7 13-69 (C1MSL4DT6) (C1MSL4DT7) 13-70 H'0080 154E CAN1 Message Slot 4 Timestamp 13-71 (C1MSL4TSP) H'0080 1550 CAN1 Message Slot 5 Standard ID0 CAN1 Message Slot 5 Standard ID1 13-57 (C1MSL5SID0) (C1MSL5SID1) 13-58 H'0080 1552 CAN1 Message Slot 5 Extended ID0 CAN1 Message Slot 5 Extended ID1 13-59 (C1MSL5EID0) (C1MSL5EID1) 13-60 H'0080 1554 CAN1 Message Slot 5 Extended ID2 CAN1 Message Slot 5 Data Length Register 13-61 (C1MSL5EID2) (C1MSL5DLC) 13-62 H'0080 1556 CAN1 Message Slot 5 Data 0 CAN1 Message Slot 5 Data 1 13-63 (C1MSL5DT0) (C1MSL5DT1) 13-64 H'0080 1558 CAN1 Message Slot 5 Data 2 CAN1 Message Slot 5 Data 3 13-65 (C1MSL5DT2) (C1MSL5DT3) 13-66 H'0080 155A CAN1 Message Slot 5 Data 4 CAN1 Message Slot 5 Data 5 13-67 (C1MSL5DT4) (C1MSL5DT5) 13-68 H'0080 155C CAN1 Message Slot 5 Data 6 CAN1 Message Slot 5 Data 7 13-69 (C1MSL5DT6) (C1MSL5DT7) 13-70 H'0080 155E CAN1 Message Slot 5 Timestamp 13-71 (C1MSL5TSP)

13-12 32180 Group User’s Manual (Rev.1.0) CAN MODULE CAN Module Related Register Map (9/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1560 CAN1 Message Slot 6 Standard ID0 CAN1 Message Slot 6 Standard ID1 13-57 (C1MSL6SID0) (C1MSL6SID1) 13-58 H'0080 1562 CAN1 Message Slot 6 Extended ID0 CAN1 Message Slot 6 Extended ID1 13-59 (C1MSL6EID0) (C1MSL6EID1) 13-60 H'0080 1564 CAN1 Message Slot 6 Extended ID2 CAN1 Message Slot 6 Data Length Register 13-61 (C1MSL6EID2) (C1MSL6DLC) 13-62 H'0080 1566 CAN1 Message Slot 6 Data 0 CAN1 Message Slot 6 Data 1 13-63 (C1MSL6DT0) (C1MSL6DT1) 13-64 H'0080 1568 CAN1 Message Slot 6 Data 2 CAN1 Message Slot 6 Data 3 13-65 (C1MSL6DT2) (C1MSL6DT3) 13-66 H'0080 156A CAN1 Message Slot 6 Data 4 CAN1 Message Slot 6 Data 5 13-67 (C1MSL6DT4) (C1MSL6DT5) 13-68 H'0080 156C CAN1 Message Slot 6 Data 6 CAN1 Message Slot 6 Data 7 13-69 (C1MSL6DT6) (C1MSL6DT7) 13-70 H'0080 156E CAN1 Message Slot 6 Timestamp 13-71 (C1MSL6TSP) H'0080 1570 CAN1 Message Slot 7 Standard ID0 CAN1 Message Slot 7 Standard ID1 13-57 (C1MSL7SID0) (C1MSL7SID1) 13-58 H'0080 1572 CAN1 Message Slot 7 Extended ID0 CAN1 Message Slot 7 Extended ID1 13-59 (C1MSL7EID0) (C1MSL7EID1) 13-60 H'0080 1574 CAN1 Message Slot 7 Extended ID2 CAN1 Message Slot 7 Data Length Register 13-61 (C1MSL7EID2) (C1MSL7DLC) 13-62 H'0080 1576 CAN1 Message Slot 7 Data 0 CAN1 Message Slot 7 Data 1 13-63 (C1MSL7DT0) (C1MSL7DT1) 13-64 H'0080 1578 CAN1 Message Slot 7 Data 2 CAN1 Message Slot 7 Data 3 13-65 (C1MSL7DT2) (C1MSL7DT3) 13-66 H'0080 157A CAN1 Message Slot 7 Data 4 CAN1 Message Slot 7 Data 5 13-67 (C1MSL7DT4) (C1MSL7DT5) 13-68 H'0080 157C CAN1 Message Slot 7 Data 6 CAN1 Message Slot 7 Data 7 13-69 (C1MSL7DT6) (C1MSL7DT7) 13-70 H'0080 157E CAN1 Message Slot 7 Timestamp 13-71 (C1MSL7TSP) H'0080 1580 CAN1 Message Slot 8 Standard ID0 CAN1 Message Slot 8 Standard ID1 13-57 (C1MSL8SID0) (C1MSL8SID1) 13-58 H'0080 1582 CAN1 Message Slot 8 Extended ID0 CAN1 Message Slot 8 Extended ID1 13-59 (C1MSL8EID0) (C1MSL8EID1) 13-60 H'0080 1584 CAN1 Message Slot 8 Extended ID2 CAN1 Message Slot 8 Data Length Register 13-61 (C1MSL8EID2) (C1MSL8DLC) 13-62 H'0080 1586 CAN1 Message Slot 8 Data 0 CAN1 Message Slot 8 Data 1 13-63 (C1MSL8DT0) (C1MSL8DT1) 13-64 H'0080 1588 CAN1 Message Slot 8 Data 2 CAN1 Message Slot 8 Data 3 13-65 (C1MSL8DT2) (C1MSL8DT3) 13-66 H'0080 158A CAN1 Message Slot 8 Data 4 CAN1 Message Slot 8 Data 5 13-67 (C1MSL8DT4) (C1MSL8DT5) 13-68 H'0080 158C CAN1 Message Slot 8 Data 6 CAN1 Message Slot 8 Data 7 13-69 (C1MSL8DT6) (C1MSL8DT7) 13-70 H'0080 158E CAN1 Message Slot 8 Timestamp 13-71 (C1MSL8TSP) H'0080 1590 CAN1 Message Slot 9 Standard ID0 CAN1 Message Slot 9 Standard ID1 13-57 (C1MSL9SID0) (C1MSL9SID1) 13-58 H'0080 1592 CAN1 Message Slot 9 Extended ID0 CAN1 Message Slot 9 Extended ID1 13-59 (C1MSL9EID0) (C1MSL9EID1) 13-60 H'0080 1594 CAN1 Message Slot 9 Extended ID2 CAN1 Message Slot 9 Data Length Register 13-61 (C1MSL9EID2) (C1MSL9DLC) 13-62 H'0080 1596 CAN1 Message Slot 9 Data 0 CAN1 Message Slot 9 Data 1 13-63 (C1MSL9DT0) (C1MSL9DT1) 13-64 H'0080 1598 CAN1 Message Slot 9 Data 2 CAN1 Message Slot 9 Data 3 13-65 (C1MSL9DT2) (C1MSL9DT3) 13-66 H'0080 159A CAN1 Message Slot 9 Data 4 CAN1 Message Slot 9 Data 5 13-67 (C1MSL9DT4) (C1MSL9DT5) 13-68 H'0080 159C CAN1 Message Slot 9 Data 6 CAN1 Message Slot 9 Data 7 13-69 (C1MSL9DT6) (C1MSL9DT7) 13-70 H'0080 159E CAN1 Message Slot 9 Timestamp 13-71 (C1MSL9TSP)

32180 Group User’s Manual (Rev.1.0) CAN Module Related Register Map (10/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 15A0 CAN1 Message Slot 10 Standard ID0 CAN1 Message Slot 10 Standard ID1 13-57 (C1MSL10SID0) (C1MSL10SID1) 13-58 H'0080 15A2 CAN1 Message Slot 10 Extended ID0 CAN1 Message Slot 10 Extended ID1 13-59 (C1MSL10EID0) (C1MSL10EID1) 13-60 H'0080 15A4 CAN1 Message Slot 10 Extended ID2 CAN1 Message Slot 10 Data Length Register 13-61 (C1MSL10EID2) (C1MSL10DLC) 13-62 H'0080 15A6 CAN1 Message Slot 10 Data 0 CAN1 Message Slot 10 Data 1 13-63 (C1MSL10DT0) (C1MSL10DT1) 13-64 H'0080 15A8 CAN1 Message Slot 10 Data 2 CAN1 Message Slot 10 Data 3 13-65 (C1MSL10DT2) (C1MSL10DT3) 13-66 H'0080 15AA CAN1 Message Slot 10 Data 4 CAN1 Message Slot 10 Data 5 13-67 (C1MSL10DT4) (C1MSL10DT5) 13-68 H'0080 15AC CAN1 Message Slot 10 Data 6 CAN1 Message Slot 10 Data 7 13-69 (C1MSL10DT6) (C1MSL10DT7) 13-70 H'0080 15AE CAN1 Message Slot 10 Timestamp 13-71 (C1MSL10TSP) H'0080 15B0 CAN1 Message Slot 11 Standard ID0 CAN1 Message Slot 11 Standard ID1 13-57 (C1MSL11SID0) (C1MSL11SID1) 13-58 H'0080 15B2 CAN1 Message Slot 11 Extended ID0 CAN1 Message Slot 11 Extended ID1 13-59 (C1MSL11EID0) (C1MSL11EID1) 13-60 H'0080 15B4 CAN1 Message Slot 11 Extended ID2 CAN1 Message Slot 11 Data Length Register 13-61 (C1MSL11EID2) (C1MSL11DLC) 13-62 H'0080 15B6 CAN1 Message Slot 11 Data 0 CAN1 Message Slot 11 Data 1 13-63 (C1MSL11DT0) (C1MSL11DT1) 13-64 H'0080 15B8 CAN1 Message Slot 11 Data 2 CAN1 Message Slot 11 Data 3 13-65 (C1MSL11DT2) (C1MSL11DT3) 13-66 H'0080 15BA CAN1 Message Slot 11 Data 4 CAN1 Message Slot 11 Data 5 13-67 (C1MSL11DT4) (C1MSL11DT5) 13-68 H'0080 15BC CAN1 Message Slot 11 Data 6 CAN1 Message Slot 11 Data 7 13-69 (C1MSL11DT6) (C1MSL11DT7) 13-70 H'0080 15BE CAN1 Message Slot 11 Timestamp 13-71 (C1MSL11TSP) H'0080 15C0 CAN1 Message Slot 12 Standard ID0 CAN1 Message Slot 12 Standard ID1 13-57 (C1MSL12SID0) (C1MSL12SID1) 13-58 H'0080 15C2 CAN1 Message Slot 12 Extended ID0 CAN1 Message Slot 12 Extended ID1 13-59 (C1MSL12EID0) (C1MSL12EID1) 13-60 H'0080 15C4 CAN1 Message Slot 12 Extended ID2 CAN1 Message Slot 12 Data Length Register 13-61 (C1MSL12EID2) (C1MSL12DLC) 13-62 H'0080 15C6 CAN1 Message Slot 12 Data 0 CAN1 Message Slot 12 Data 1 13-63 (C1MSL12DT0) (C1MSL12DT1) 13-64 H'0080 15C8 CAN1 Message Slot 12 Data 2 CAN1 Message Slot 12 Data 3 13-65 (C1MSL12DT2) (C1MSL12DT3) 13-66 H'0080 15CA CAN1 Message Slot 12 Data 4 CAN1 Message Slot 12 Data 5 13-67 (C1MSL12DT4) (C1MSL12DT5) 13-68 H'0080 15CC CAN1 Message Slot 12 Data 6 CAN1 Message Slot 12 Data 7 13-69 (C1MSL12DT6) (C1MSL12DT7) 13-70 H'0080 15CE CAN1 Message Slot 12 Timestamp 13-71 (C1MSL12TSP) H'0080 15D0 CAN1 Message Slot 13 Standard ID0 CAN1 Message Slot 13 Standard ID1 13-57 (C1MSL13SID0) (C1MSL13SID1) 13-58 H'0080 15D2 CAN1 Message Slot 13 Extended ID0 CAN1 Message Slot 13 Extended ID1 13-59 (C1MSL13EID0) (C1MSL13EID1) 13-60 H'0080 15D4 CAN1 Message Slot 13 Extended ID2 CAN1 Message Slot 13 Data Length Register 13-61 (C1MSL13EID2) (C1MSL13DLC) 13-62 H'0080 15D6 CAN1 Message Slot 13 Data 0 CAN1 Message Slot 13 Data 1 13-63 (C1MSL13DT0) (C1MSL13DT1) 13-64 H'0080 15D8 CAN1 Message Slot 13 Data 2 CAN1 Message Slot 13 Data 3 13-65 (C1MSL13DT2) (C1MSL13DT3) 13-66 H'0080 15DA CAN1 Message Slot 13 Data 4 CAN1 Message Slot 13 Data 5 13-67 (C1MSL13DT4) (C1MSL13DT5) 13-68 H'0080 15DC CAN1 Message Slot 13 Data 6 CAN1 Message Slot 13 Data 7 13-69 (C1MSL13DT6) (C1MSL13DT7) 13-70 H'0080 15DE CAN1 Message Slot 13 Timestamp 13-71 (C1MSL13TSP)

13-14 32180 Group User’s Manual (Rev.1.0) CAN MODULE CAN Module Related Register Map (11/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 15E0 CAN1 Message Slot 14 Standard ID0 CAN1 Message Slot 14 Standard ID1 13-57 (C1MSL14SID0) (C1MSL14SID1) 13-58 H'0080 15E2 CAN1 Message Slot 14 Extended ID0 CAN1 Message Slot 14 Extended ID1 13-59 (C1MSL14EID0) (C1MSL14EID1) 13-60 H'0080 15E4 CAN1 Message Slot 14 Extended ID2 CAN1 Message Slot 14 Data Length Register 13-61 (C1MSL14EID2) (C1MSL14DLC) 13-62 H'0080 15E6 CAN1 Message Slot 14 Data 0 CAN1 Message Slot 14 Data 1 13-63 (C1MSL14DT0) (C1MSL14DT1) 13-64 H'0080 15E8 CAN1 Message Slot 14 Data 2 CAN1 Message Slot 14 Data 3 13-65 (C1MSL14DT2) (C1MSL14DT3) 13-66 H'0080 15EA CAN1 Message Slot 14 Data 4 CAN1 Message Slot 14 Data 5 13-67 (C1MSL14DT4) (C1MSL14DT5) 13-68 H'0080 15EC CAN1 Message Slot 14 Data 6 CAN1 Message Slot 14 Data 7 13-69 (C1MSL14DT6) (C1MSL14DT7) 13-70 H'0080 15EE CAN1 Message Slot 14 Timestamp 13-71 (C1MSL14TSP) H'0080 15F0 CAN1 Message Slot 15 Standard ID0 CAN1 Message Slot 15 Standard ID1 13-57 (C1MSL15SID0) (C1MSL15SID1) 13-58 H'0080 15F2 CAN1 Message Slot 15 Extended ID0 CAN1 Message Slot 15 Extended ID1 13-59 (C1MSL15EID0) (C1MSL15EID1) 13-60 H'0080 15F4 CAN1 Message Slot 15 Extended ID2 CAN1 Message Slot 15 Data Length Register 13-61 (C1MSL15EID2) (C1MSL15DLC) 13-62 H'0080 15F6 CAN1 Message Slot 15 Data 0 CAN1 Message Slot 15 Data 1 13-63 (C1MSL15DT0) (C1MSL15DT1) 13-64 H'0080 15F8 CAN1 Message Slot 15 Data 2 CAN1 Message Slot 15 Data 3 13-65 (C1MSL15DT2) (C1MSL15DT3) 13-66 H'0080 15FA CAN1 Message Slot 15 Data 4 CAN1 Message Slot 15 Data 5 13-67 (C1MSL15DT4) (C1MSL15DT5) 13-68 H'0080 15FC CAN1 Message Slot 15 Data 6 CAN1 Message Slot 15 Data 7 13-69 (C1MSL15DT6) (C1MSL15DT7) 13-70 H'0080 15FE CAN1 Message Slot 15 Timestamp 13-71 (C1MSL15TSP)

32180 Group User’s Manual (Rev.1.0)

13.2.1 CAN Control Registers

CAN0 Control Register (CAN0CNT) <Address: H ’0080 1000> CAN1 Control Register (CAN1CNT) <Address: H ’0080 1400> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 FRS TTS PTSRRB O BCM LBM RST 0 0 0 0 0 00 0 0 0 0 1 0 0 01 <After reset: H’0011> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00

4 RBO 0: Enable normal operation R(Note 1)

Return bus off bit 1: Request clearing of error counter

5 TSR 0: Enable count operation R(Note 1)

Timestamp counter reset bit 1: Initialize count (to H ’0000) 6–7 TSP 00: Select CAN bus bit clock R W Timestamp prescaler bit 01: Select CAN bus bit clock divided by 2 10: Select CAN bus bit clock divided by 3 11: Select CAN bus bit clock divided by 4 8–9 No function assigned. Fix to "0". 00 10 No function assigned. Fix to "0". 00

11 FRST 0: Negate reset R W

Forcible reset bit 1: Forcibly reset

12 BCM 0: Disable BasicCAN mode R W

BasicCAN mode bit 1: BasicCAN mode 13 No function assigned. Fix to "0". 00

14 LBM 0: Disable loopback function R W

Loopback mode bit 1: Enable loopback function

15 RST 0: Negate reset R W

CAN reset bit 1: Request reset Note 1: Only writing "1" is effective. Automatically cleared to "0" in hardware.

13-16 32180 Group User’s Manual (Rev.1.0) CAN MODULE (1) RBO (Return Bus Off) bit (Bit 4) Setting this bit to "1" clears the CAN Receive Error Count Register (CANnREC) and CAN Transmit Error Count Register (CANnTEC) to H'00 and forcibly places the CAN module into an error active state. This bit is cleared when the CAN module goes to an error active state. Note:  Communication becomes possible when 11 consecutive recessive bits are detected on the CAN bus after clearing the error counters. (2) TSR (Timestamp Counter Reset) bit (Bit 5) Setting this bit to "1" clears the value of the CAN Timestamp Count Register (CANnTSTMP) to H’0000. This bit is cleared after the value of the CAN Timestamp Count Register (CANnTSTMP) is cleared to H’0000. (3) TSP (Timestamp Prescaler) bits (Bits 6–7) These bits select the count clock source for the timestamp counter. Note:  Do not change settings of the TSP bits while CAN is operating (CAN Status Register CRS bit = "0"). (4) FRST (Forcible Reset) bit (Bit 11) When the FRST bit is set to "1", the CAN module is separated from the CAN bus and the protocol control unit is reset regardless of whether the CAN module currently is communicating. Up to 5 BCLK periods are re- quired before the protocol control unit is reset after setting the FRST bit. Notes:  In order for CAN communication to start, the FRST and RST bits must be cleared to "0".  If the FRST bit is set to "1" during communication, the CTX pin output goes high immediately after that. Therefore, setting the FRST bit to "1" while sending CAN frame may cause a CAN error.  The CAN Message Slot Control Register’s transmit/receive requests are not cleared for rea- sons that the FRST or RST bits are set.  When the protocol control unit is reset by setting the FRST bit to "1", the CAN Timestamp Count and CAN Transmit/Receive Error Count Registers are initialized to "0". (5) BCM (BasicCAN Mode) bit (Bit 12) By setting this bit to "1", the CAN module can be operated in BasicCAN mode.  Operation during BasicCAN mode During BasicCAN mode, two local slots— slots 14 and 15— are used as dual buffers, and the received frames with matching ID are stored alternately in slots 14 and 15 by acceptance filtering. Used for this acceptance filtering when slot 14 is active (next received frame to be stored in slot 14) are the ID set in slot 14 and local mask A, and those when slot 15 is active are the ID set in slot 15 and local mask B. Two types of frames— data frame and remote frame— can be received in this mode. By setting the same ID and the same mask register value for the two slots, the possibility of loosing messages when, for example, receiving frames which have many IDs may be reduced.

32180 Group User’s Manual (Rev.1.0)  Procedure for entering BasicCAN mode Follow the procedure below during initialization: 1) Set the ID for slots 14 and 15 and the local mask registers A and B. (We recommend setting the same value.) 2) Set the frame types to be handled by slots 14 and 15 (standard or extended) in the CAN Extended ID Register. (We recommend setting the same type.) 3) Set the Message Slot Control Registers for slots 14 and 15 for data frame reception. 4) Set the BCM bit to "1". Notes:  Do not change settings of the BCM bit while CAN is operating (CAN Status Register CRS bit = "0").  The first slot that is active after clearing the RST bit is slot 14.  Even during BasicCAN mode, slots 0 to 13 can be used the same way as in normal operation. (6) LBM (Loopback Mode) bit (Bit 14) When the LBM bit is set to "1", if a receive slot exists whose ID matches that of the frame sent by the CAN module itself, then the frame can be received. Notes:  ACK is not returned for the transmit frame.  Do not change settings of the LBM bit while CAN is operating (CAN Status Register CRS bit = "0"). (7) RST (CAN Reset) bit (Bit 15) When the RST bit is cleared to "0", the CAN module is connected to the CAN bus and becomes ready to communicate after detecting 11 consecutive recessive bits. Also, the CAN Timestamp Count Register thereby starts counting. When the RST bit is set to "1", the CAN module is reset so that when a bus idle state is entered after sending frames from the slots which have had transmit requests set by that time, the protocol control unit is reset and the CAN module is disconnected from the CAN bus. Frames received during this time are processed normally. Notes:  It is inhibited to set a new transmit request until the CAN Status Register CRS bit is set to "1" and the protocol control unit is reset after setting the RST bit to "1".  When the protocol control unit is reset by setting the RST bit to "1", the CAN Timestamp Count and CAN Transmit/Receive Error Count Registers are initialized to "0".  In order for CAN communication to start, the FRST and RST bits must be cleared to "0".

13-18 32180 Group User’s Manual (Rev.1.0) CAN MODULE

13.2.2 CAN Status Registers

CAN0 Status Register (CAN0STAT) <Address: H ’0080 1002> CAN1 Status Register (CAN1STAT) <Address: H ’0080 1402> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TSCRSCTSBRSBCRSLBSBCSCBSEPSBOS MSN 0 0000 0 0100000000 <After reset: H’0100> b Bit Name Function R W 0 No function assigned. Fix to "0". 00

1 BOS 0: Not bus off R –

Bus off status bit 1: Bus off state

2 EPS 0: Not error passive R –

Error passive status bit 1: Error passive state

3 CBS 0: No error occurred R –

CAN bus error bit 1: Error occurred

4 BCS 0: Normal mode R –

BasicCAN mode status bit 1: BasicCAN mode 5 No function assigned. Fix to "0". 00

6 LBS 0: Normal mode R –

Loopback status bit 1: Loopback mode

7 CRS 0: Operating R –

CAN reset status bit 1: Reset

8 RSB 0: Not receiving R –

Receive status bit 1: Receiving

9 TSB 0: Not sending R –

Transmit status bit 1: Sending

10 RSC 0: Reception not completed R –

Reception completed status bit 1: Reception completed

11 TSC 0: Transmission not completed R –

Transmission completed status bit 1: Transmission completed 12–15 MSN Number of the message slot which has finished R – Message slot number bit sending or receiving 0000: Slot 0 0001: Slot 1 0010: Slot 2 0011: Slot 3 0100: Slot 4 0101: Slot 5 0110: Slot 6 0111: Slot 7 1000: Slot 8 1001: Slot 9 1010: Slot 10 1011: Slot 11 1100: Slot 12 1101: Slot 13 1110: Slot 14 1111: Slot 15

32180 Group User’s Manual (Rev.1.0) (1) BOS (Bus Off Status) bit (Bit 1) When BOS bit = "1", it means that the CAN module is in a buss off state. [Set condition] This bit is set to "1" when the transmit error count register value exceeded 255 and a bus off state is entered. [Clear condition] This bit is cleared when restored from the bus off state. (2) EPS (Error Passive Status) bit (Bit 2) When EPS bit = "1", it means that the CAN module is in an error passive state. [Set condition] This bit is set to "1" when the transmit or receive error count register value exceeded 127 and an error passive state is entered. [Clear condition] This bit is cleared when restored from the error passive state. (3) CBS (CAN Bus Error) bit (Bit 3) [Set condition] This bit is set to "1" when an error is detected on the CAN bus. [Clear condition] This bit is cleared when the CAN module finished sending or receiving normally. (4) BCS (BasicCAN Status) bit (Bit 4) When BCS bit = "1", it means that the CAN module is operating in BasicCAN mode. [Set condition] This bit is set to "1" when the CAN module is operating in BasicCAN mode. BasicCAN mode is useful when the following conditions are met:  CAN Control Register BCM bit = "1"  Slots 14 and 15 both are set for data frame reception [Clear condition] This bit is cleared by clearing the BCM bit to "0". (5) LBS (Loopback Status) bit (Bit 6) When LBS bit = "1", it means that the CAN module is operating in loopback mode. [Set condition] This bit is set to "1" by setting the CAN Control Register LBM (loopback mode) bit to "1". [Clear condition] This bit is cleared by clearing the LBM bit to "0".

13-20 32180 Group User’s Manual (Rev.1.0) CAN MODULE (6) CRS (CAN Reset Status) bit (Bit 7) When CRS bit = "1", it means that the protocol control unit is in a reset state. [Set condition] This bit is set to "1" when the CAN protocol control unit is in a reset state. [Clear condition] This bit is cleared by clearing the CAN Control Register RST (CAN reset) and FRST bits to "0". (7) RSB (Receive Status) bit (Bit 8) [Set condition] This bit is set to "1" when the CAN module is operating as a receive node. [Clear condition] This bit is cleared when the CAN module starts operating as a transmit node or enters a bus idle state. (8) TSB (Transmit Status) bit (Bit 9) [Set condition] This bit is set to "1" when the CAN module is operating as a transmit node. [Clear condition] This bit is cleared when the CAN module starts operating as a receive node or enters a bus idle state. (9) RSC (Reception Completed Status) bit (Bit 10) [Set condition] This bit is set to "1" when the CAN module has finished receiving normally (regardless of whether there is any slot that meets receive conditions). [Clear condition] This bit is cleared when the CAN module has finished sending normally. (10) TSC (Transmission Completed Status) bit (Bit 11) [Set condition] This bit is set to "1" when the CAN module has finished sending normally. [Clear condition] This bit is cleared when the CAN module has finished receiving normally. (11) MSN (Message Slot Number) bits (Bits 12–15) These bits indicate the relevant slot number when the CAN module has finished sending or finished storing the received data. These bits cannot be cleared to "0" in software. Note:  When during loopback mode a frame is received that the CAN module itself transmitted, the MSN bits indicate the transmit slot number.

32180 Group User’s Manual (Rev.1.0)

13.2.3 CAN Frame Format Select Registers

CAN0 Frame Format Select Register (CAN0FFS) <Address: H ’0080 1004> CAN1 Frame Format Select Register (CAN1FFS) <Address: H ’0080 1404> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 FFE0 FFE1 FFE2 FFE3 FFE4 FFE6 FFE7 FFE8 FFE9 FFE10 FFE11 FFE12 FFE13 FFE14 FFE15FFE5 0000000000000000 <After reset: H’0000> b Bit Name Function R W

0 FFE0 (slot 0 extended format bit) 0: Standard ID format R W

1 FFE1 (slot 1 extended format bit) 1: Extended ID format

2 FFE2 (slot 2 extended format bit)

3 FFE3 (slot 3 extended format bit)

4 FFE4 (slot 4 extended format bit)

5 FFE5 (slot 5 extended format bit)

6 FFE6 (slot 6 extended format bit)

7 FFE7 (slot 7 extended format bit)

8 FFE8 (slot 8 extended format bit)

9 FFE9 (slot 9 extended format bit)

10 FFE10 (slot 10 extended format bit)

11 FFE11 (slot 11 extended format bit)

12 FFE12 (slot 12 extended format bit)

13 FFE13 (slot 13 extended format bit)

14 FFE14 (slot 14 extended format bit)

15 FFE15 (slot 15 extended format bit)

This register selects the format of frames handled by message slots corresponding to the respective bits in the register. Setting any bit in this register to "0" selects the standard ID format, and setting any bit in this register to "1" selects the extended ID format. Note:  Settings of any bit in this register can only be changed when the corresponding slot does not have transmit or receive requests set.

13-22 32180 Group User’s Manual (Rev.1.0) CAN MODULE

13.2.4 CAN Configuration Registers

CAN0 Configuration Register (CAN0CONF) <Address: H'0080 1006> CAN1 Configuration Register (CAN1CONF) <Address: H'0080 1406> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 SAMPRBPH1PH2SJW 000000000000 0 0 0 0 <After reset: H’0000> b Bit Name Function R W 0–1 SJW 00: SJW = 1Tq R W reSynchronization Jump Width setting bit 01: SJW = 2Tq 10: SJW = 3Tq 11: SJW = 4Tq 2–4 PH2 000: Phase Segment2 = 1Tq R W Phase Segment2 setting bit 001: Phase Segment2 = 2Tq 010: Phase Segment2 = 3Tq 011: Phase Segment2 = 4Tq 100: Phase Segment2 = 5Tq 101: Phase Segment2 = 6Tq 110: Phase Segment2 = 7Tq 111: Phase Segment2 = 8Tq 5–7 PH1 000: Phase Segment1 = 1Tq R W Phase Segment1 setting bit 001: Phase Segment1 = 2Tq 010: Phase Segment1 = 3Tq 011: Phase Segment1 = 4Tq 100: Phase Segment1 = 5Tq 101: Phase Segment1 = 6Tq 110: Phase Segment1 = 7Tq 111: Phase Segment1 = 8Tq 8–10 PRB 000: Propagation Segment = 1Tq R W Propagation Segment setting bit 001: Propagation Segment = 2Tq 010: Propagation Segment = 3Tq 011: Propagation Segment = 4Tq 100: Propagation Segment = 5Tq 101: Propagation Segment = 6Tq 110: Propagation Segment = 7Tq 111: Propagation Segment = 8Tq

11 SAM 0: Sampled one time R W

Sampling count select bit 1: Sampled three times 12–15 No function assigned. Fix to "0". 00 Notes:  Do not change settings of the CAN Configuration Register (CAN0CONF or CAN1CONF) during CAN operation (CAN Status Register CRS bit = "0").  When setting the bits in this register, make sure the conditions given below are met:  Number of Tq’s for one bit: 8–25 Tq’s  SJW ≤ min (Phase Segment1, Phase Segment2)  Phase Segment2 = max (Phase Segment1, IPT) where IPT = 1 for the internal CAN modules of the 32180 min() is the function that returns the smaller of two values; max() is the function that returns the maximum value.

32180 Group User’s Manual (Rev.1.0) (1) SJW bits (Bits 0–1) These bits set the reSynchronization Jump Width. (2) PH2 bits (Bits 2–4) These bits set the width of Phase Segment2. (3) PH1 bits (Bits 5–7) These bits set the width of Phase Segment1. (4) PRB bits (Bits 8–10) These bits set the width of Propagation Segment. (5) SAM bit (Bit 11) This bit sets the number of times each bit is sampled. When SAM = "0", the value sampled at the end of Phase Segment1 is assumed to be the value of the bit. When SAM = "1", the value of the bit is determined by a majority circuit from three sampled values, each sampled 2 Tq’s before, 1 Tq before, and at the end of Phase Segment1. Table 13.2.1 Typical Settings of Bit Timing when CPU Clock = 80 MHz Baud Rate BRP Set Value Tq Period (ns) No. of Tq ’s in 1 Bit PROP + PH1 PH2 Sampling Point 1M bps 1 50 20 13 6 70% 3 100 10 7 2 80% 3 100 10 6 3 70% 3 100 10 5 4 60% 4 125 8 5 2 75% 4 125 8 4 3 63% 500K bps 4 125 16 13 2 88% 4 125 16 12 3 81% 4 125 16 11 4 75% 7 200 10 7 2 80% 7 200 10 6 3 70% 7 200 10 5 4 60% 9 250 8 5 2 75% 9 250 8 4 3 63% Table 13.2.2 Typical Settings of Bit Timing when CPU Clock = 64 MHz Baud Rate BRP Set Value Tq Period (ns) No. of Tq ’s in 1 Bit PROP + PH1 PH2 Sampling Point 1M bps 1 62.5 16 10 5 69% 3 125 8 5 2 75% 3 125 8 4 3 63% 500K bps 3 125 16 13 2 88% 3 125 16 11 4 75% 7 250 8 5 2 75% 7 250 8 4 3 63%

13-24 32180 Group User’s Manual (Rev.1.0) CAN MODULE

13.2.5 CAN Timestamp Count Registers

CAN0 Timestamp Count Register (CAN0TSTMP) <Address: H ’0080 1008> CAN1 Timestamp Count Register (CAN1TSTMP) <Address: H ’0080 1408> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 CANTSTMP 0000000000000000 <After reset: H’0000> b Bit Name Function R W 0–15 CANTSTMP 16-bit timestamp count value R – The CAN module contains a 16-bit up-count register. The count period can be selected from the CAN bus bit period divided by 1, 2, 3 or 4 by setting the CAN Control Register (CANnCNT) TSP (Timestamp Prescaler) bits. When the CAN module finishes sending or receiving, it captures the count register value and stores the value in a message slot. The counter is made to start counting by clearing the CAN Control Register (CANnCNT) RST bit to "0". Notes:  The CAN protocol control unit can be reset and the counter initialized to H’0000 by setting the CAN Control Register (CANnCNT) RST (CAN Reset) bit to "1". Or the counter can be initialized to H’0000 while the CAN module remains operating by setting the TSR (Timestamp Counter Reset) bit to "1".  If any slot with the matching ID exists during loopback mode, the CAN module stores the timestamp value in that slot when it finished receiving. (No timestamp values are stored this way when the CAN module finished sending.)  The count period of the CAN Timestamp Count Register varies with the CAN resynchronization function.

32180 Group User’s Manual (Rev.1.0)

13.2.6 CAN Error Count Registers

CAN0 Receive Error Count Register (CAN0REC) <Address: H ’0080 100A> CAN1 Receive Error Count Register (CAN1REC) <Address: H ’0080 140A> 123456 b 7b0 REC 00000000 <After reset: H’00> b Bit Name Function R W 0–7 REC Receive error count value R – During an error active/error passive state, a receive error count value is stored in this register. The count is decremented when frames are received normally or incremented when an error occurred. If the CAN module finished receiving normally when REC ≥ 128 (error passive), REC is set to 127. During a bus off state, an undefined value is stored in this register. The count is reset to H’00 upon returning to an error active state. CAN0 Transmit Error Count Register (CAN0TEC) <Address: H ’0080 100B> CAN1 Transmit Error Count Register (CAN1TEC) <Address: H ’0080 140B> 9 10 11 12 13 14 b15b8 TEC 00000000 <After reset: H’00> b Bit Name Function R W 8–15 TEC Transmit error count value R – During an error active/error passive state, a transmit error count value is stored in this register. The count is decremented when frames are transmitted normally or incremented when an error occurred. Dur- ing a bus off state, an undefined value is stored in this register. The count is reset to H’00 upon returning to an error active state.

13-26 32180 Group User’s Manual (Rev.1.0) CAN MODULE

13.2.7 CAN Baud Rate Prescalers

CAN0 Baud Rate Prescaler (CAN0BRP) <Address: H ’0080 1016> CAN1 Baud Rate Prescaler (CAN1BRP) <Address: H ’0080 1416> 123456 b 7b0 BRP 00000001 <After reset: H’00> b Bit Name Function R W 0–7 BRP Baud rate prescaler value R W This register sets the Tq period of CAN. The CAN baud rate is determined by (Tq period × number of Tq’s in one bit). Tq period = (BRP + 1) / (CPU clock/2) CAN transfer baud rate = 1 Tq period × number of Tq’s in one bit Number of Tq’s in one bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 Notes:  Setting H’00 (divide by 1) is inhibited.  Do not change settings of the CAN Baud Rate Prescaler (CANnBRP) during CAN operation (CAN Status Register CRS bit = "0").

32180 Group User’s Manual (Rev.1.0)

13.2.8 CAN Interrupt Related Registers

The CAN interrupt related registers are used to control the interrupt request signals output to the Interrupt Control- ler by CAN. (1) Interrupt request status bit This status bit is used to determine whether an interrupt is requested. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this bit is unaffected by the interrupt request enable bit, it can also be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request enable bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "1" to enable interrupt requests or "0" to disable interrupt requests. Figure 13.2.1 Interrupt Request Status and Enable Registers To the Interrupt Controller Interrupt request from each peripheral function Interrupt request status Data bus Set  Group interrupt Interrupt request enable clear F/F F/F Data = 0

13-28 32180 Group User’s Manual (Rev.1.0) CAN MODULE Figure 13.2.1 Interrupt Request Status and Enable Registers b4 5 b7 Interrupt request status Initial state Event occurs on bit 6 Interrupt request Event occurs on bit 4 Only bit 6 cleared Bit 4 data retained b4 5 b7 1 1 0 1 Write to the interrupt request status Example for clearing interrupt request status 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 Program example ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */  To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) To clear an interrupt request status, always be sure to write 1 to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. b4 5 6 b7 Interrupt request status Event occurs on bit 6 Event occurs on bit 4 Only bit 6 cleared Bit 4 also cleared 0 0 1 0 1 0 1 0 0 0 0 0 Read 0 0 1 0 0 0 0 0 Clear bit 6 (AND'ing with 1101) Write ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */

32180 Group User’s Manual (Rev.1.0) CAN0 Slot Interrupt Request Status Register (CAN0SLIST) <Address: H ’0080 100C> CAN1 Slot Interrupt Request Status Register (CAN1SLIST) <Address: H ’0080 140C> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 SSB0 SSB1 SSB2 SSB3 SSB4 SSB6 SSB7 SSB8 SSB9 SSB10 SSB11 SSB12 SSB13 SSB14 SSB15SSB5 0000000000000000 <After reset: H’0000> b Bit Name Function R W

0 SSB0 (slot 0 interrupt request status bit) 0: Interrupt not requested R(Note 1)

1 SSB1 (slot 1 interrupt request status bit) 1: Interrupt requested

2 SSB2 (slot 2 interrupt request status bit)

3 SSB3 (slot 3 interrupt request status bit)

4 SSB4 (slot 4 interrupt request status bit)

5 SSB5 (slot 5 interrupt request status bit)

6 SSB6 (slot 6 interrupt request status bit)

7 SSB7 (slot 7 interrupt request status bit)

8 SSB8 (slot 8 interrupt request status bit)

9 SSB9 (slot 9 interrupt request status bit)

10 SSB10 (slot 10 interrupt request status bit)

11 SSB11 (slot 11 interrupt request status bit)

12 SSB12 (slot 12 interrupt request status bit)

13 SSB13 (slot 13 interrupt request status bit)

14 SSB14 (slot 14 interrupt request status bit)

15 SSB15 (slot 15 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write. When using CAN interrupts, this register helps to know which slot requested an interrupt.  Slots set for transmission The corresponding bit is set to "1" when the CAN module finished sending. This bit is cleared by writing "0" in software.  Slots set for reception The corresponding bit is set to "1" when the CAN module finished receiving and finished storing the received message in the message slot. This bit is cleared by writing "0" in software. When writing to the CAN slot interrupt request status, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write. Notes:  If the automatic response function is enabled for remote frame receive slots, the request status is set after the CAN module finished receiving a remote frame and after it finished sending a data frame.  For remote frame transmit slots, the request status is set after the CAN module finished sending a remote frame and after it finished receiving a data frame.  If the request status is set by an interrupt request at the same time it is cleared in software, the former has priority so that the request status is set.

13-30 32180 Group User’s Manual (Rev.1.0) CAN MODULE CAN0 Slot Interrupt Request Enable Register (CAN0SLIEN) <Address: H ’0080 1010> CAN1 Slot Interrupt Request Enable Register (CAN1SLIEN) <Address: H ’0080 1410> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 IRB0 IRB1 IRB2 IRB3 IRB4 IRB6 IRB7 IRB8 IRB9 IRB10 IRB11 IRB12 IRB13 IRB14 IRB15IRB5 0000000000000000 <After reset: H’0000> b Bit Name Function R W

0 IRB0 (slot 0 interrupt request enable bit) 0: Mask (disable) interrupt request R W

1 IRB1 (slot 1 interrupt request enable bit) 1: Enable interrupt request

2 IRB2 (slot 2 interrupt request enable bit)

3 IRB3 (slot 3 interrupt request enable bit)

4 IRB4 (slot 4 interrupt request enable bit)

5 IRB5 (slot 5 interrupt request enable bit)

6 IRB6 (slot 6 interrupt request enable bit)

7 IRB7 (slot 7 interrupt request enable bit)

8 IRB8 (slot 8 interrupt request enable bit)

9 IRB9 (slot 9 interrupt request enable bit)

10 IRB10 (slot 10 interrupt request enable bit)

11 IRB11 (slot 11 interrupt request enable bit)

12 IRB12 (slot 12 interrupt request enable bit)

13 IRB13 (slot 13 interrupt request enable bit)

14 IRB14 (slot 14 interrupt request enable bit)

15 IRB15 (slot 15 interrupt request enable bit)

This register is used to enable or disable the interrupt requests that will be generated when data transmission or reception in each corresponding slot is completed. Setting IRBn (n = 0–15) to "1" enables the interrupt request to be generated when data transmission or reception in the corresponding slot is completed. The CAN Slot Interrupt Request Status Register (CANnSLIST) helps to know which slot requested the interrupt.

32180 Group User’s Manual (Rev.1.0) CAN0 Error Interrupt Request Status Register (CAN0ERIST) <Address: H ’0080 1014> CAN1 Error Interrupt Request Status Register (CAN1ERIST) <Address: H ’0080 1414> 123456 b 7b0 BEIS EPIS EOIS 0000 0 0 0 0 <After reset: H’00> b Bit Name Function R W 0–4 No function assigned. Fix to "0". 00

5 BEIS 0: Interrupt not requested R(Note 1)

CAN bus error interrupt request status bit 1: Interrupt requested

6 EPIS

Error passive interrupt request status bit

7 EOIS

Bus off interrupt request status bit Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write. When using CAN interrupts, if the interrupt request sources are associated with errors, this register helps to know which source generated the interrupt. (1) BEIS (CAN Bus Error Interrupt Request Status) bit (Bit 5) The BEIS bit is set to "1" when a communication error is detected. This bit is cleared by writing "0" in soft- ware. (2) EPIS (Error Passive Interrupt Request Status) bit (Bit 6) The EPIS bit is set to "1" when the CAN module goes to an error passive state. This bit is cleared by writing "0" in software. (3) EOIS (Bus Off Interrupt Request Status) bit (Bit 7) The EOIS bit is set to "1" when the CAN module goes to a bus off passive state. This bit is cleared by writing "0" in software. When writing to the CAN error interrupt request status, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write.

13-32 32180 Group User’s Manual (Rev.1.0) CAN MODULE CAN0 Error Interrupt Request Enable Register (CAN0ERIEN) <Address: H ’0080 1015> CAN1 Error Interrupt Request Enable Register (CAN1ERIEN) <Address: H ’0080 1415> 9 10 11 12 13 14 b15b8 BEIEN EPIEN EOIEN 0000 0 0 0 0 <After reset: H’00> b Bit Name Function R W 8–12 No function assigned. Fix to "0". 00

13 BEIEN 0: Mask (disable) interrupt request R W

CAN bus error interrupt request enable bit 1: Enable interrupt request

14 EPIEN

Error passive interrupt request enable bit

15 EOIEN

Bus off interrupt request enable bit (1) BEIEN (CAN Bus Error Interrupt Request Enable) bit (Bit 5) The BEIEN bit enables or disables the interrupt requests to be generated when CAN bus errors occurred. CAN bus error interrupt requests are enabled by setting this bit to "1". (2) EPIEN (Error Passive Interrupt Request Enable) bit (Bit 6) The EPIEN bit enables or disables the interrupt requests to be generated when the CAN module entered an error passive state. Error passive interrupt requests are enabled by setting this bit to "1". (3) EOIEN (Bus Off Interrupt Request Enable) bit (Bit 7) The EOIEN bit enables or disables the interrupt requests to be generated when the CAN module entered a bus off state. Bus off interrupt requests are enabled by setting this bit to "1".

32180 Group User’s Manual (Rev.1.0) CAN0 Single-Shot Interrupt Request Status Register (CAN0SSIST) <address: H ’0080 1044> CAN1 Single-Shot Interrupt Request Status Register (CAN1SSIST) <Address: H ’0080 1444> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 SSIST0 SSIST1 SSIST2 SSIST3 SSIST4 SSIST5 SSIST6 SSIST7 SSIST8 SSIST9 SSIST10 SSIST11 SSIST12 SSIST13 SSIST14 SSIST15 0000000000000000 <After reset: H’0000> b Bit Name Function R W

0 SSIST0 0: No arbitration-lost or transmit error R(Note 1)

Slot 0 single-shot interrupt request status 1: Arbitration-lost or transmit error occurred

1 SSIST1

Slot 1 single-shot interrupt request status

2 SSIST2

Slot 2 single-shot interrupt request status

3 SSIST3

Slot 3 single-shot interrupt request status

4 SSIST4

Slot 4 single-shot interrupt request status

5 SSIST5

Slot 5 single-shot interrupt request status

6 SSIST6

Slot 6 single-shot interrupt request status

7 SSIST7

Slot 7 single-shot interrupt request status

8 SSIST8

Slot 8 single-shot interrupt request status

9 SSIST9

Slot 9 single-shot interrupt request status

10 SSIST10

Slot 10 single-shot interrupt request status

11 SSIST11

Slot 11 single-shot interrupt request status

12 SSIST12

Slot 12 single-shot interrupt request status

13 SSIST13

Slot 13 single-shot interrupt request status

14 SSIST14

Slot 14 single-shot interrupt request status

15 SSIST15

Slot 15 single-shot interrupt request status Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write. If transmission in any slot failed for reasons of arbitration-lost or a transmit error, the corresponding bit in this register is set to "1". The bit is cleared by writing "0" in software. Furthermore, if the corresponding bit in the CAN single-shot interrupt request enable register has been set to "1", an interrupt request can be generated when transmission failed. When writing to the CAN single-shot interrupt request status, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write.

13-34 32180 Group User’s Manual (Rev.1.0) CAN MODULE CAN0 Single-Shot Interrupt Request Enable Register (CAN0SSIEN) <Address: H ’0080 1048> CAN1 Single-Shot Interrupt Request Enable Register (CAN1SSIEN) <Address: H ’0080 1448> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 SSIEN0 SSIEN1 SSIEN2 SSIEN3 SSIEN4 SSIEN5 SSIEN6 SSIEN7 SSIEN8 SSIEN9 SSIEN10 SSIEN11 SSIEN12 SSIEN13 SSIEN14 SSIEN15 0000000000000000 <After reset: H’0000> b Bit Name Function R W

0 SSIEN0 0: Disable interrupt request R W

Slot 0 single-shot interrupt request enable bit 1: Enable interrupt request

1 SSIEN1

Slot 1 single-shot interrupt request enable bit

2 SSIEN2

Slot 2 single-shot interrupt request enable bit

3 SSIEN3

Slot 3 single-shot interrupt request enable bit

4 SSIEN4

Slot 4 single-shot interrupt request enable bit

5 SSIEN5

Slot 5 single-shot interrupt request enable bit

6 SSIEN6

Slot 6 single-shot interrupt request enable bit

7 SSIEN7

Slot 7 single-shot interrupt request enable bit

8 SSIEN8

Slot 8 single-shot interrupt request enable bit

9 SSIEN9

Slot 9 single-shot interrupt request enable bit

10 SSIEN10

Slot 10 single-shot interrupt request enable bit

11 SSIEN11

Slot 11 single-shot interrupt request enable bit

12 SSIEN12

Slot 12 single-shot interrupt request enable bit

13 SSIEN13

Slot 13 single-shot interrupt request enable bit

14 SSIEN14

Slot 14 single-shot interrupt request enable bit

15 SSIEN15

Slot 15 single-shot interrupt request enable bit This register is used to enable or disable the interrupt requests that will be generated when transmission in each corresponding slot has failed. Setting any bit in this register to "1" enables the interrupt request to be generated when transmission in the corresponding slot (in single-shot mode only) has failed. The CAN Single-Shot Inter- rupt Request Status Register helps to know which slot requested the interrupt.

32180 Group User’s Manual (Rev.1.0) Slot 0 transmission/reception completed Slot 1 transmission/reception completed Slot 2 transmission/reception completed Slot 3 transmission/reception completed Slot 4 transmission/reception completed Slot 5 transmission/reception completed Slot 6 transmission/reception completed Slot 7 transmission/reception completed To the remaining 27-source inputs in the next page CAN0 transmit/receive & error interrupt request(Level) 35-source inputs CAN0SLIST (H'0080 100C) CAN0SLIEN (H'0080 1010) Figure 13.2.3 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (1/5)

13-36 32180 Group User’s Manual (Rev.1.0) CAN MODULE Slot 8 transmission/reception completed Slot 9 transmission/reception completed Slot 10 transmission/reception completed Slot 11 transmission/reception completed Slot 12 transmission/reception completed Slot 13 transmission/reception completed Slot 14 transmission/reception completed Slot 15 transmission/reception completed To the preceding page(Level) 27-source inputs CAN0SLIST (H'0080 100C) CAN0SLIEN (H'0080 1010) To the remaining 19-source inputs in the next page Figure 13.2.4 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (2/5)

32180 Group User’s Manual (Rev.1.0) Figure 13.2.5 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (3/5) F/F F/F EOIEN EOIS F/F F/F EPIEN EPIS F/F F/F BEIEN BEIS b15 b14 b13 Data bus CAN bus error occurs Go to error passive state Go to bus off state To the preceding page(Level) 19-source inputs CAN0ERIST (H'0080 1014) CAN0ERIEN (H'0080 1015) To the remaining 16-source inputs in the next page

13-38 32180 Group User’s Manual (Rev.1.0) CAN MODULE Slot 0 arbitration-lost/transmit error occurs Slot 1 arbitration-lost/transmit error occurs Slot 2 arbitration-lost/transmit error occurs Slot 3 arbitration-lost/transmit error occurs Slot 4 arbitration-lost/transmit error occurs Slot 5 arbitration-lost/transmit error occurs Slot 6 arbitration-lost/transmit error occurs Slot 7 arbitration-lost/transmit error occurs To the preceding page(Level) 16-source inputs CAN0SSIST (H'0080 1044) CAN0SSIEN (H'0080 1048) To the remaining 8-source inputs in the next page Figure 13.2.6 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (4/5)

32180 Group User’s Manual (Rev.1.0) Figure 13.2.7 Block Diagram of the CAN0 Transmit/Receive & Error Interrupt Requests (5/5) F/F F/F F/F F/F F/F F/F F/F F/F SSIEN15 SSIST15 SSIEN14 SSIST14 SSIEN13 SSIST13 SSIEN12 SSIST12 F/F F/F SSIEN11 SSIST11 F/F F/F SSIEN10 SSIST10 F/F F/F SSIEN9 SSIST9 F/F F/F SSIEN8 SSIST8 b15 b15 b14 b14 b13 b13 b12 b12 b11 b11 b10 b10 Data bus Slot 8 arbitration-lost/transmit error occurs Slot 9 arbitration-lost/transmit error occurs Slot 10 arbitration-lost/transmit error occurs Slot 11 arbitration-lost/transmit error occurs Slot 12 arbitration-lost/transmit error occurs Slot 13 arbitration-lost/transmit error occurs Slot 14 arbitration-lost/transmit error occurs Slot 15 arbitration-lost/transmit error occurs To the preceding page(Level) 8-source inputs CAN0SSIST (H'0080 1044) CAN0SSIEN (H'0080 1048)

13-40 32180 Group User’s Manual (Rev.1.0) CAN MODULE Figure 13.2.8 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (1/5) F/F F/F F/F F/F F/F F/F F/F F/F IRB7 SSB7 IRB6 SSB6 IRB5 SSB5 IRB4 SSB4 F/F F/F IRB3 SSB3 F/F F/F IRB2 SSB2 F/F F/F IRB1 SSB1 F/F F/F IRB0 SSB0 Data bus Slot 0 transmission/reception completed Slot 1 transmission/reception completed Slot 2 transmission/reception completed Slot 3 transmission/reception completed Slot 4 transmission/reception completed Slot 5 transmission/reception completed Slot 6 transmission/reception completed Slot 7 transmission/reception completed To the remaining 27-source inputs in the next page CAN1 transmit/receive & error interrupt request(Level) 35-source inputs CAN1SLIST (H'0080 140C) CAN1SLIEN (H'0080 1410)

32180 Group User’s Manual (Rev.1.0) Slot 8 transmission/reception completed Slot 9 transmission/reception completed Slot 10 transmission/reception completed Slot 11 transmission/reception completed Slot 12 transmission/reception completed Slot 13 transmission/reception completed Slot 14 transmission/reception completed Slot 15 transmission/reception completed To the preceding page(Level) 27-source inputs CAN1SLIST (H'0080 140C) CAN1SLIEN (H'0080 1410) To the remaining 19-source inputs in the next page Figure 13.2.9 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (2/5)

13-42 32180 Group User’s Manual (Rev.1.0) CAN MODULE Figure 13.2.10 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (3/5) F/F F/F EOIEN EOIS F/F F/F EPIEN EPIS F/F F/F BEIEN BEIS b15 b14 b13 Data bus CAN bus error occurs Go to error passive state Go to bus off state To the preceding page(Level) 19-source inputs CAN1ERIST (H'0080 1414) CAN1ERIEN (H'0080 1415) To the remaining 16-source inputs in the next page

32180 Group User’s Manual (Rev.1.0) Figure 13.2.11 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (4/5) F/F F/F F/F F/F F/F F/F F/F F/F SSIEN7 SSIST7 SSIEN6 SSIST6 SSIEN5 SSIST5 SSIEN4 SSIST4 F/F F/F SSIEN3 SSIST3 F/F F/F SSIEN2 SSIST2 F/F F/F SSIEN1 SSIST1 F/F F/F SSIEN0 SSIST0 Data bus Slot 0 arbitration-lost/transmit error occurs Slot 1 arbitration-lost/transmit error occurs Slot 2 arbitration-lost/transmit error occurs Slot 3 arbitration-lost/transmit error occurs Slot 4 arbitration-lost/transmit error occurs Slot 5 arbitration-lost/transmit error occurs Slot 6 arbitration-lost/transmit error occurs Slot 7 arbitration-lost/transmit error occurs To the remaining 8-source inputs in the next page To the preceding page (Level) 16-source inputs CAN1SSIST (H'0080 1444) CAN1SSIEN (H'0080 1488)

13-44 32180 Group User’s Manual (Rev.1.0) CAN MODULE Figure 13.2.12 Block Diagram of the CAN1 Transmit/Receive & Error Interrupt Requests (5/5) F/F F/F F/F F/F F/F F/F F/F F/F SSIEN15 SSIST15 SSIEN14 SSIST14 SSIEN13 SSIST13 SSIEN12 SSIST12 F/F F/F SSIEN11 SSIST11 F/F F/F SSIEN10 SSIST10 F/F F/F SSIEN9 SSIST9 F/F F/F SSIEN8 SSIST8 b15 b15 b14 b14 b13 b13 b12 b12 b11 b11 b10 b10 Data bus Slot 8 arbitration-lost/transmit error occurs Slot 9 arbitration-lost/transmit error occurs Slot 10 arbitration-lost/transmit error occurs Slot 11 arbitration-lost/transmit error occurs Slot 12 arbitration-lost/transmit error occurs Slot 13 arbitration-lost/transmit error occurs Slot 14 arbitration-lost/transmit error occurs Slot 15 arbitration-lost/transmit error occurs To the preceding page(Level) 8-source inputs CAN1SSIST (H'0080 1444) CAN1SSIEN (H'0080 1488)

32180 Group User’s Manual (Rev.1.0)

13.2.9 CAN Cause of Error Registers

CAN0 Cause of Error Register (CAN0EF) <Address: H ’0080 1017> CAN1 Cause of Error Register (CAN1EF) <Address: H ’0080 1417> 123456 b 7b0 BITEETR STFE FORME CRCE ACKE 0000000 0 <After reset: H’00> b Bit Name Function R W 0–1 No function assigned. Fix to "0". 00

2 ETR 0: Error detected when sending R –

Transmit/receive error judgment bit 1: Error detected when receiving

3 BITE 0: Bit error not detected R –

Bit error detection bit 1: Bit error detected

4 STFE 0: Stuff error not detected R –

Stuff error detection bit 1: Stuff error detected

5 FORME 0: Form error not detected R –

Form error detection bit 1: Form error detected

6 CRCE 0: CRC error not detected R –

CRC error detection bit 1: CRC error detected

7 ACKE 0: ACK error not detected R –

ACK error detection bit 1: ACK error detected This register indicates error information when a communication error occurred. (1) ETR (Transmit/Receive Error Judgement) bit (Bit 2) This bit is set to "1" if the CAN module was operating as a reception node when a communication error occurred. The bit is cleared to "0" by a read of this register. (2) BITE (Bit Error Detection) bit (Bit 3) This bit is set to "1" when a bit error was detected. The bit is cleared to "0" by a read of this register. (3) STFE (Stuff Error Detection) bit (Bit 4) This bit is set to "1" when a stuff error was detected. The bit is cleared to "0" by a read of this register. (4) FORME (Form Error Detection) bit (Bit 5) This bit is set to "1" when a form error was detected. The bit is cleared to "0" by a read of this register. (5) CRCE (CRC Error Detection) bit (Bit 6) This bit is set to "1" when a CRC error was detected. The bit is cleared to "0" by a read of this register. (6) ACKE (ACK Error Detection) bit (Bit 7) This bit is set to "1" when an ACK error was detected. The bit is cleared to "0" by a read of this register. Note:  Depending on the error status, two or more bits may be set at the same time.

13-46 32180 Group User’s Manual (Rev.1.0) CAN MODULE

13.2.10 CAN Mode Registers

CAN0 Mode Register (CAN0MOD) <Address: H ’0080 1018> CAN1 Mode Register (CAN1MOD) <Address: H ’0080 1418> 123456 b 7b0 CMOD 000 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00 6–7 CMOD 00: Normal mode R W CAN operation mode select bit 01: Bus monitor mode 10: Self-diagnostic mode 11: Settings inhibited (1) CMOD (CAN Operation Mode Select) bits (Bit 6, Bit 7) These bits select the CAN operation mode.  Normal operation mode Normal transmit/receive operations can be performed.  Bus monitor mode Only receive operation is performed. During bus monitor mode, the CTX output is fixed high and neither ACK nor an error frame can be returned. Note:  During bus monitor mode, issuing transmit requests is inhibited. The ACK bit is handled as “Don ’t care” during bus monitor mode. Therefore, if all bits of data including the CRC delim- iter are received normally, it is assumed that data has been received normally no matter whether the ACK bit is high.  Self-diagnostic mode CTX and CRX are connected together internally in the CAN module. When combined with loopback mode, this mode allows communication to be performed within the CAN module alone. During self- diagnostic mode, the CTX pin output is fixed high even when transmitting. Figure 13.2.13 Conceptual Diagram of Self-Diagnostic Mode

32180 Group User’s Manual (Rev.1.0)

13.2.11 CAN DMA Transfer Request Select Registers

CAN0 DMA Transfer Request Select Register (CAN0DMARQ) <Address: H ’0080 1019> 123456 b 7b0 CDMSEL1 CDMSEL0 000 0 0 0 0 0 <After reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00

6 CDMSEL1 0: Slot 1 transmission failed R W

CAN DMA1 transfer request source select bit 1: Slot 14 transmission/reception completed

7 CDMSEL0 0: Slot 0 transmission failed R W

CAN DMA0 transfer request source select bit 1: Slot 15 transmission/reception completed CAN0 can generate DMA transfer requests. This register is used to select the cause or source of that request. (1) CDMSEL1 (CAN DMA1 Transfer Request Source Select) bit (Bit 6) This bit selects one of the following two as the cause or source of a transfer request to DMA2.  Slot 1 transmission failed If the CDMSEL1 bit is set to "0", a transfer request is generated when transmission in slot 1 has failed for reasons of arbitration-lost or transmit error.  Slot 14 transmission/reception completed If the CDMSEL1 bit is set to "1", a transfer request is generated when transmission/reception in slot 14 is completed. Notes:  If slot 14 has been set for remote frame transmission, a DMA transfer request is generated when remote frame transmission is completed as well as when data frame reception is completed.  If slot 14 has been set for remote frame reception (automatic response), a DMA transfer request is generated when remote frame reception is completed as well as when data frame transmission is completed. Note:  CAN1 does not have the DMA transfer request function. (2) CDMSEL0 (CAN DMA0 Transfer Request Source Select) bit (Bit 7) This bit selects one of the following two as the cause or source of a transfer request to DMA0.  Slot 0 transmission failed If the CDMSEL0 bit is set to "0", a transfer request is generated when transmission in slot 0 has failed for reasons of arbitration-lost or transmit error.  Slot 15 transmission/reception completed If the CDMSEL0 bit is set to "1", a transfer request is generated when transmission/reception in slot 15 is completed. Notes:  If slot 15 has been set for remote frame transmission, a DMA transfer request is generated when remote frame transmission is completed as well as when data frame reception is completed.  If slot 15 has been set for remote frame reception (automatic response), a DMA transfer request is generated when remote frame reception is completed as well as when data frame transmission is completed.

13-48 32180 Group User’s Manual (Rev.1.0) CAN MODULE

13.2.12 CAN Mask Registers

CAN0 Global Mask Register Standard ID0 (C0GMSKS0) <Address: H ’0080 1028> CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0) <Address: H ’0080 1030> CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0) <Address: H ’0080 1038> CAN1 Global Mask Register Standard ID0 (C1GMSKS0) <Address: H ’0080 1428> CAN1 Local Mask Register A Standard ID0 (C1LMSKAS0) <Address: H ’0080 1430> CAN1 Local Mask Register B Standard ID0 (C1LMSKBS0) <Address: H ’0080 1438> 123456 b 7b0 SID0M SID1M SID2M SID3M SID4M 000000 0 0 <After reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00 3–7 SID0M –SID4M 0: ID not checked R W (Standard mask ID0–standard mask ID4) 1: ID checked CAN0 Global Mask Register Standard ID1 (C0GMSKS1) <Address: H ’0080 1029> CAN0 Local Mask Register A Standard ID1 (C0LMSKAS1) <Address: H ’0080 1031> CAN0 Local Mask Register B Standard ID1 (C0LMSKBS1) <Address: H ’0080 1039> CAN1 Global Mask Register Standard ID1 (C1GMSKS1) <Address: H ’0080 1429> CAN1 Local Mask Register A Standard ID1 (C1LMSKAS1) <Address: H ’0080 1431> CAN1 Local Mask Register B Standard ID1 (C1LMSKBS1) <Address: H ’0080 1439> 9 10 11 12 13 14 b15b8 SID6MSID5M SID7M SID8M SID9M SID10M 0000000 0 <After reset: H’00> b Bit Name Function R W 8–9 No function assigned. Fix to "0". 00 10–15 SID5M –SID10M 0: ID not checked R W (Standard mask ID5–standard mask ID10) 1: ID checked Three mask registers are used in acceptance filtering: global mask register, local mask register A and local mask register B. The global mask register is used for message slots 0-13, while local mask registers A and B are used for message slots 14 and 15, respectively.  If any bit in this register is set to "0", the corresponding ID bit is masked (assumed to have matched) during acceptance filtering.  If any bit in this register is set to "1", the corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set in the message slot, the received data is stored in it. Notes:  SID0M corresponds to the MSB of the standard ID.  The global mask register can only be modified when none of slots 0-13 have receive requests set.  The local mask register A can only be modified when slot 14 does not have a receive request set.  The local mask register B can only be modified when slot 15 does not have a receive request set.

32180 Group User’s Manual (Rev.1.0) CAN0 Global Mask Register Extended ID0 (C0GMSKE0) <Address: H ’0080 102A> CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0) <Address: H ’0080 1032> CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) <Address: H ’0080 103A> CAN1 Global Mask Register Extended ID0 (C1GMSKE0) <Address: H ’0080 142A> CAN1 Local Mask Register A Extended ID0 (C1LMSKAE0) <Address: H ’0080 1432> CAN1 Local Mask Register B Extended ID0 (C1LMSKBE0) <Address: H ’0080 143A> 123456 b 7b0 EID1MEID0M EID2M EID3M 00000 0 0 0 <After reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00 4–7 EID0M –EID3M 0: ID not checked R W (Extended mask ID0–extended mask ID3) 1: ID checked CAN0 Global Mask Register Extended ID1 (C0GMSKE1) <Address: H ’0080 102B> CAN0 Local Mask Register A Extended ID1 (C0LMSKAE1) <Address: H ’0080 1033> CAN0 Local Mask Register B Extended ID1 (C0LMSKBE1) <Address: H ’0080 103B> CAN1 Global Mask Register Extended ID1 (C1GMSKE1) <Address: H ’0080 142B> CAN1 Local Mask Register A Extended ID1 (C1LMSKAE1) <Address: H ’0080 1433> CAN1 Local Mask Register B Extended ID1 (C1LMSKBE1) <Address: H ’0080 143B> 9 1 01 11 21 31 4 b 1 5b8 EID6MEID5MEID4M EID7M EID8M EID9M EID10M EID11M 00000000 <After reset: H’00> b Bit Name Function R W 8–15 EID4M –EID11M 0: ID not checked R W (Extended mask ID4–extended mask ID11) 1: ID checked

13-50 32180 Group User’s Manual (Rev.1.0) CAN MODULE CAN0 Global Mask Register Extended ID2 (C0GMSKE2) <Address: H ’0080 102C> CAN0 Local Mask Register A Extended ID2 (C0LMSKAE2) <Address: H ’0080 1034> CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2) <Address: H ’0080 103C> CAN1 Global Mask Register Extended ID2 (C1GMSKE2) <Address: H ’0080 142C> CAN1 Local Mask Register A Extended ID2 (C1LMSKAE2) <Address: H ’0080 1434> CAN1 Local Mask Register B Extended ID2 (C1LMSKBE2) <Address: H ’0080 143C>

123456 B 7b0

EID12M EID13M EID14M EID15M EID16M EID17M 0000000 0 <After reset: H’00> b Bit Name Function R W 0,1 No function assigned. Fix to "0". 00 2–7 EID12M –EID17M 0: ID not checked R W (Extended mask ID12–extended mask ID17) 1: ID checked Three mask registers are used in acceptance filtering: global mask register, local mask register A and local mask register B. The global mask register is used for message slots 0-13, while local mask registers A and B are used for message slots 14 and 15, respectively.  If any bit in this register is set to "0", the corresponding ID bit is masked (assumed to have matched) during acceptance filtering.  If any bit in this register is set to "1", the corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set in the message slot, the received data is stored in it. Notes:  EID0M corresponds to the MSB of the extended ID.  The global mask register can only be modified when none of slots 0-13 have receive requests set.  The local mask register A can only be modified when slot 14 does not have a receive request set.  The local mask register B can only be modified when slot 15 does not have a receive request set.

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