32176

Renesas Technology Corp

32-BIT RISC SINGLE-CHIP MICROCOMPUTER

Manufacturer: Renesas Technology Corp

Document: 742 Pages / 4Mb

Request Quote Download Datasheet Read online HTML view

More from Renesas Technology Corp Browse 0-9 parts

Online Datasheet

Read 32176 online.

32176 RENESAS | Alldatasheet

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 742

Technical content

RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES

32176 Group32

Rev. 1.10 Revision date: Jun 20, 2006 Hardware Manual www.renesas.com Before using this material, please visit our website to confirm that this is the most current document available. REJ09B0067-0110

Keep safety first in your circuit designs! Notes regarding these materials 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, pro- grams, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers con- tact Renesas Technology Corp. or an authorized Renesas Technology Corp. product dis- tributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by vari- ous means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liabil- ity or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or repro- duce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be im- ported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products.

1.01 Oct 31, 2003 – First edition issued

1.10 Jun 20, 2006 Add “Before Use The optional Specification for the product of 32176 Group”

Common Incorrect) A-D Converter Correct) A/D Converter in all Incorrect) A-D Conversion Correct) A/D Conversion chapters Incorrect) D-A Converter Correct) D/A Converter Incorrect) D-A Conversion Correct) D/A Conversion Incorrect) Serial I/O Correct) Serial Interface 1-2,4 Remove the Table from 1.1.2 to replace 1.1.1 and add Note 1 1-17 Correct Pin No. 135 and 136 lines in the table 1.4.1 2-4 Add Note 1 to IE bit in the PWS register 3-19 Add H’0080 0600 to H’0080 0603 Dummy access area (note 1) 3-31 Add Note 1 3-35 Add descriptions for Dummy access areas 5-6 Correct notes for IMASK register 5-7 Add a note to SBICR register 5-12,14 Combine Table 5.4.1 with Table 5.5.1 5-15 Add a note to [6] Enabling multiple interrupts 5-17 Correct Note 2 and Note 5 in the Figure 5.5.2 5-18 Add a sentence to 5.6.1 6-7 Add a description to FAENS bit in FMOD register 6-9 Correct descriptions in (1) FENTRY bit 6-13 Add Note 1 to Flash Control Register 4 6-17 Add precautions to be observed after boot mode start 6-19,21 Add Note 1 to Figure 6.5.2 and Figure 6.5.4 6-26 Add “Procedure for switching to nomal mode” to Figure 6.5.7 6-28 Add Note 2 to Figure 6.5.9 6-30 Add Note 2 to Figure 6.5.10 6-31 Add Note 2 to FIgure 6.5.11 6-48 Correct Table 6.7.1: Incorrect) pull low Correct) pull low (0 –100kΩ ) 6-49 Add SBI# pin and Note 1 to Figure 6.7.1 6-50,51 Add pages 6.8 Connecting to a Serial Programmer (UART Mode)

REVISION HISTORY

Rev. Date Description Page Summary (REVISION HISTORY-1 )

32176 Group Hardware Manual

6-52 Add descriptions to (2) Protection by FP pin 6-53 Add 6.10 Notes on the Internal RAM 8-9 Add Note 2 to P70MOD bit in the P7MOD register 8-15 Add precaution to 3) Method for using XSTAT to detect XIN oscillation stoppage 8-16 Add Note to Figure 8.3.1 8-18,19 Replace Figure 8.4.1 Correct PG67LEV register Incorrect) VT26EL0 Correct) VT6SEL0 Incorrect) VT26EL1 Correct) VT6SEL1 8-20 to Add Note 2 to Port Peripheral Circuit Diagrams 8-23 8-20 Add P130 – P137 (TIN16 – TIN23) to FIgure 8.5.1 8-25 Add “About the peripheral function input when it is set to the general purpose port” 9-11 Correct descriptions of (2) TREQFn bit and (4) TENLn bit 9-31 Add “DMA interrupt related registers” to Table 9.4.1 Chap. 10 Replace diagrams of Timing Describe reload timing of reload registers 10-6 Replace Figure 10.1.3 10-96 Change the descriptions of Reload register updates in TIO PWM output mode Replace Figure 10.4.10 10-96,97 Add Figure 10.4.11 Update timing of PWM period and descriptions 12-8 Change the description of (4) Notes on using transmit interrupts 12-22 Add Table 12.2.1 and Table 12.2.2 12-40 Add the precaution of switching from general-purpose to serial interface pin 12-55 Replace Figure 12.7.5 12-56 Replace Figure 12.8.1 12-57 Add the precaution of switching from general-purpose to serial interface pin Rev. Date Description Page Summary (REVISION HISTORY-2 )

32176 Hardware Manual

1.10 Jun 20, 2006

13-17 Add descriptions to notes of LBM bit Add descriptions to RST bit 13-20 Add descriptions to CRS bit 13-75 Add Note 1 to Figure 13.3.4 90,95 13-85 Correct the note of clearing TRFIN bit 15-3 Correct descriptions of (9) Hold control 15-4 Add Note 2 to P70MOD bit in P7Mod register 15-5 Add Note 1 to BUSMOD bit in BUSMODC register 17-2 Add Figure 17.1.1 RAM Backup Area 18.2 Replace Figure 18.1.1 18-3 Change the descriptions of 18.1.2 and replace Figure 18.1.2 18-4 Add a centence to 3) of XSTAT bit Add Note to Figure 18.1.3 18-6 Add Note 1 to Figure 18.1.4 20-2 Add Note 1 to Figure 20.1.1 20-3 to Correct Notes in Figure 20.2.1 to Figure 20.3.3 20-7 20-8 Add Note 1 to Figure 20.3.4 and Figure 20.3.5 21-20 to Change the configuration of A.C. Characteristics 21-53 21-20 Add tc(XIN)[119], tw(RESET)[124], tw(XINH)[120], tw(XINL)[121], tr(XINL)[122], and tr(XINL)[123] Add Figure 21.8.1 Clock and Reset Timing 21-27 Correct tw(BLWL) tw(BHWL)[51] Add td(CSL-RDL)[93] 21-30 td(CSL-RDL)[93], td(BLEL-RDL) td(BHEL-RDL)[136], and tv(RDH-BLEL) tv(RDH-BHEL)[137] 21-31 Add Figure 21.8.12 Read Timing (Byte Enable Mode) 21-32 Add td(CSL-WRL)[96] Rev. Date Description Page Summary (REVISION HISTORY-3 )

21-37 Add tc(XIN)[119], tw(RESET)[124], tw(XINH)[120], tw(XINL)[122], and tr(XINL)[123] Add Figure 21.9.1 Clock and Reset Timing 21-44 Correct tw(BLWL) tw(BHWL)[51] Add td(CSL-RDL)[93] 21-47 td(CSL-RDL)[93], td(BLEL-RDL) td(BHEL-RDL)[136], and tv(RDH-BLEL) tv(RDH-BHEL)[137] 21-48 Add Figure 21.9.12 Read Timing (Byte Enable Mode) 21-49 Add td(CSL-WRL)[96] App.1-2 Replace Dimensional Outline Drawing App.4-3 Add descriptions for dummy access areas Add Notes on the Internal RAM App.4-4 Add “About the peripheral function input when it is set to the general purpose port” App.4-5 Add “DMA interrupt related registers” to Appendix Table 4.8.1 App.4-7 Replace Appendix Figure 4.9.1 App.4-8 Replace Appendix Figure 4.9.2 App.4-16 Add the precaution of switching from general-purpose to serial interface pin Rev. Date Description Page Summary (REVISION HISTORY-4 )

Guide to Understanding the Register Table (1) Bit number: Indicates a register’s bit number. (2) Register border: The registers enclosed with thick border lines must be accessed in halfwords or words. (3) Status after reset: The initial state of each register after reset is indicated in hexadecimal or binary. (4) Status after reset: The initial state of each register after reset is indicated bitwise. 0: This bit is “0” after reset. 1: This bit is “1” after reset. ?: This bit is undefined after reset. (5) The shaded bits mean that they have no functions assigned. (6) Read conditions: R: This bit can be accessed for read. ?: The value read from this bit is undefined. (Reading this bit has no effect.) 0: The value read from this bit is always “0”. 1: The value read from this bit is always “1”. (7) Write conditions: W: This bit can be accessed for write. N: This bit is write protected. 0: To write to this bit, always write “0”. 1: To write to this bit, always write “1”. –: Writing to this bit has no effect. (It does not matter whether this bit is set to “0” or “1” by writing in software.) Note: Care must be taken when writing to this bit. See Note in each register table. XXXRegister(XXX) <Address: H’XXXX XXXX> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 AAA BBB CCC 000 0 0 0 0 0 0 0 0 0 0 0 0 0 <After reset: H’0000> b Bit name Function R W 3–15 No function assigned. Fix to “0”. 0 0 Note 1: Only writing “0” is effective. Writing “1” has no effect, in which case the bit retains the value it had before the write. Notation of “L” (signals) The symbol “#” suffixed to the pin (or signal) names means that the pins (or signals) are “L” . Before Use (2) (4) (6) (7) (3) (1) (5)

The optional specification for the product of 32176Group [Contents] The optional specification for the product of M32176F4VFP,M32176F3VFP,M32176F2VFP is shown below. (1) Flash 10000(10k) times rewritable product (4Kbyte block x 2 only) (2) 40MHz operation product (3) Lead-Free product However it is not able to select both (1) and (2) at same time. Note. There is no (1) optional specification for M32176F4TFP, M32176F3TFP, M32176F2TFP. The product cord is allocated for each optional specification. The list of product cord and the figure of marking are shown below. [The list of products specification] Model name Product cord Contents of specification M32176F4VFP B 0 32MHz/125°C, Flash is rewritable for 100 times M32176F3VFP or 1 32MHz/125°C, Flash is rewritable for 10000(10k) times (4Kbyte block x 2 only) M32176F2VFP U 2 40MHz/125°C, Flash is rewritable for 100 times M32176F4TFP B M32176F3TFP or 0 40MHz/85°C, Flash is rewritable for 100 times M32176F2TFP U *B:Non-Lead-Free product, U:Lead-Free product [The figure of marking] Please contact Renesas Technology Corp. for further details on these optional specifications or price. When samples are requred, specify products cord (B0~B2,U0~U2). If not, the standard specification (B0) is requred. Before Use M32R/ECU : Show the family name. M32176F4VFP : Show the product name M32176F4VFP. XXXXXXX : Show the administration number of the date cord (7 figure) in manufacturing. B0 : Show the product cord.

This page is blank for reasons of layout.

Contents-132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20. 06 Table of contents CHAPTER 1 OVERVIEW CHAPTER 2 CPU CHAPTER 3 ADDRESS SPACE CHAPTER 4 EIT

Contents-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20. 06 CHAPTER 5 INTERRUPT CONTROLLER (ICU) CHAPTER 6 INTERNAL MEMORY

Contents-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20. 06 CHAPTER 7 RESET CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS CHAPTER 9 DMAC

Contents-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20. 06 CHAPTER 10 MULTIJUNCTION TIMERS

Contents-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20. 06 CHAPTER 11 A/D CONVERTER CHAPTER 12 SERIAL INTERFACE

Contents-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20. 06 CHAPTER 13 CAN MODULE

Contents-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20. 06 CHAPTER 14 REAL TIME DEBUGGER (RTD)

Contents-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20. 06 CHAPTER 15 EXTERNAL BUS INTERFACE CHAPTER 16 WAIT CONTROLLER CHAPTER 17 RAM BACKUP MODE CHAPTER 18 OSCILLATOR CIRCUIT CHAPTER 19 JTAG

Contents-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20. 06 CHAPTER 20 POWER SUPPLY CIRCUIT CHAPTER 21 ELECTRICAL CHARACTERISTICS 21.4.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) ----- 21-11 APPENDIX 1 MECHANICAL SPECIFICAITONS APPENDIX 2 INSTRUCTION PROCESSING TIME

Contents-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20. 06 APPENDIX 3 PROCESSING OF UNUSED PINS APPENDIX 4 SUMMARY OF PRECAUTIONS

1.1 Outline of the 32176 Group

1.2 Block Diagram

1.3 Pin Functions

1.4 Pin Assignments

1-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 1.1.1 Product List Type Name ROM RAM Frequency Power supply voltage Temperature Range capacity capacity (Note 1) M32176F4VFP 512 Kbytes 24 Kbytes 32 MHz (Note 2) 5 V or 3.3 V –40°C to +125°C M32176F4TFP 512 Kbytes 24 Kbytes 40 MHz 5 V or 3.3 V –40°C to +85°C M32176F3VFP 384 Kbytes 24 Kbytes 32 MHz (Note 2) 5 V or 3.3 V –40°C to +125°C M32176F3TFP 384 Kbytes 24 Kbytes 40 MHz 5 V or 3.3 V –40°C to +85°C M32176F2VFP 256 Kbytes 24 Kbytes 32 MHz (Note 2) 5 V or 3.3 V –40°C to +125°C M32176F2TFP 256 Kbytes 24 Kbytes 40 MHz 5 V or 3.3 V –40°C to +85°C Note 1: This does not guarantee continuous operation and there is a limitation on the length of use (temperature profile). Note 2: There is a 40 MHz operation product optional specification for the product of M32176F4VFP, M32176F3VFP, and M32176F2VFP. Please contact Renesas Technology Corp. for further details on those optional specifications or price.

1.1.1 M32R Family CPU Core

(1) Based on a RISC architecture The 32176 is a 32-bit RISC single-chip microcomputer which is built around the M32R family CPU core (hereinafter referred to as the M32R) and incorporates flash memory, RAM and various other peripheral functions-all integrated into a single chip. The M32R is based on a RISC architecture. Memory is accessed using load/store instructions, and various arithmetic operations are executed using register-to-register operation instructions. The M32R internally contains sixteen 32-bit general-purpose registers and has 83 instructions. The M32R supports compound instructions such as Load & Address Update and Store & Address Update, in addition to ordinary load and store instructions. These instructions help to speed up data transfers. (2) Five-stage pipelined processing The M32R supports five-stage pipelined instruction processing consisting of Instruction Fetch, De- code, Execute, Memory Access and Write Back. Not just load/store instructions and register-to- register operation instructions, compound instructions such as Load & Address Update and Store & Address Update are executed in one CPUCLK period (which is equivalent to 25 ns when f(CPUCLK) = 40 MHz). Although instructions are supplied to the execution stage in the order in which they were fetched, it is possible that if the load/store instruction supplied first is extended by wait cycles inserted in memory access, the subsequent register-to-register operation instruction will be executed before that instruction. Using such a facility, which is known as the “out-of-order-completion” mechanism, the M32R is able to control instruction execution without wasting clock cycles. (3) Compact instruction code The M32R supports two instruction formats: one 16 bits long, and one 32 bits long. Use of the 16-bit instruction format especially helps to suppress the code size of a program. Moreover, the availability of 32-bit instructions makes programming easier and provides higher per- formance at the same clock speed than in architectures where the address space is segmented. For example, some 32-bit instructions allow control to jump to an address 32 Mbytes forward or back- ward from the currently executed address in one instruction, making programming easy.

1-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

1.1.2 Built-in Multiplier/Accumulator

(1) Built-in high-speed multiplier The M32R contains a 32 bits × 16 bits high-speed multiplier which enables the M32R to execute a 32 bits × 32 bits integral multiplication instruction in three CPUCLK periods. (2) DSP-comparable multiply-accumulate instructions The M32R supports the following four types of multiply-accumulate instructions (or multiplication instruc- tions) which each can be executed in one CPUCLK period using a 56-bit accumulator. (1) 16 high-order bits of register × 16 high-order bits of register (2) 16 low-order bits of register × 16 low-order bits of register (3) Whole 32 bits of register × 16 high-order bits of register (4) Whole 32 bits of register × 16 low-order bits of register The M32R has some special instructions to round the value stored in the accumulator to 16 or 32 bits or shift the accumulator value before storing in a register to have its digits adjusted. Because these instructions are also executed in one CPUCLK period, when used in combination with high- speed data transfer instructions such as Load & Address Update or Store & Address Update, they enable the M32R to exhibit data processing capability comparable to that of a DSP.

1.1.3 Built-in Flash Memory and RAM

The 32176 contains a RAM that can be accessed with zero wait state, allowing to design a high- speed embedded system. The internal flash memory can be written to while mounted on a printed circuit board (on-board writing). Use of flash memory facilitates development work, because the chip used at the develop- ment stage can be used directly in mass-production, allowing for a smooth transition from prototype to mass-production without the need to change the printed circuit board. The internal flash memory has a virtual flash emulation function, allowing the internal RAM to be virtually mapped into part of the internal flash memory. When combined with the internal Real-Time Debugger (RTD), this function makes the ROM table data tuning easy. The internal RAM can be accessed for reading or rewriting data from an external device indepen- dently of the M32R by using the Real-Time Debugger. The external device is communicated using the Real-Time Debugger’s exclusive clock-synchronized serial interface.

1-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

1.1.4 Built-in Clock Frequency Multiplier

The 32176 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1 below. XIN pin (8MHz-10MHz) BCLK (peripheral clock) (16MHz-20MHz) CPUCLK (CPU clock) (32MHz-40MHz) PLL Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier Table 1.1.2 Clock Functional Block Features CPUCLK CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for the M32R core, internal flash memory and internal RAM. BCLK Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency for the internal peripheral I/O and external data bus. Clock output (BCLK pin output) A clock with the same frequency as f(BCLK) is output from this pin.

1.1.5 Powerful Built-in Peripheral Functions

(1) 8-level interrupt controller (ICU) (2) 10-channel DMAC (3) 37-channel Multijunction timer (MJT) (4) 16-channel A/D converter (ADC) (5) 4-channel high-speed serial interface (SIO) (6) 2-channel Full-CAN (7) Real-time debugger (RTD) (8) Wait controller (9) M32R family’s common debug function (Scalable Debug Interface or SDI)

1-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 1.2.1 Block Diagram of the 32176 PLL Clock Generator Internal Bus Interface AddressData Internal RAM (24 Kbytes) Internal Flash Memory (M32176F4: 512 Kbytes) (M32176F3: 384 Kbytes) (M32176F2: 256 Kbytes) M32R Core (Max. 40MHz) Multiplier/Accumulator (32 bits x 16 bits + 56 bits) DMAC (10 channels) Multijunction Timer (37 channels) Serial Interface (4 channels) A/D Converter (10-bit converter, 16 channels) Wait Controller Interrupt Controller (23 sources, 8 levels) Real-Time Debugger (RTD) External Bus Interface Internal 32-bit bus

96 Input/output Ports

(2 channels) Internal 16-bit bus Internal Power Supply Generator (VDC)

1-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 1.2.1 Features of the 32176 (1/2) Functional Block Features M32R CPU core Implementation: Five-stage pipelined instruction processing Internal 32-bit structure of the core Register configuration General-purpose registers: 32 bits × 16 registers Control registers: 32 bits × 5 registers Instruction set 16 and 32-bit instruction formats 83 instructions and six addressing modes Internal multiplier/accumulator (32 bits × 16 bits + 56 bits) RAM Capacity: 24 Kbytes Zero-wait access The internal RAM can be accessed for reading or rewriting data from the outside independently of the M32R by using the Real-Time Debugger, without ever causing the CPU performance to decrease. The internal RAM can be backed up by using RAM back up mode when turn off the power supply. Flash memory Capacity: M32176F2: 256 Kbytes, M32176F3: 384 Kbytes, M32176F4: 512 Kbytes Zero-wait access Durability: Standard product : 100 times 10000 (10k) times rewritable : 4-Kbyte block (Note 2) : 10000 (10k) times -product (Note 1) : Other blocks : 1000 (1k) times Bus specification Fundamental bus cycle : 25 ns (when f(CPUCLK = 40 MHz) Logical address space : 4 Gbytes linear Internal bus specification : Internal 32-bit data bus (for CPU <-> internal flash memory and RAM access) : Internal 16-bit data bus (for internal peripheral I/O access) External area: Maximum 2 Mbytes (during processor mode) External extension area: Maximum 2 Mbytes External data address bus: 19-bit address External data bus: 16-bit data bus Shortest external bus access: 2 BCLK periods during read, 2 BCLK periods during write DMAC Number of channels: 10 Transfers between internal peripheral I/O’s or internal RAM’s or between internal peripheral I/O and internal RAM are supported. Capable of advanced DMA transfers when used in combination with internal peripheral I/O Transfer request: Software or internal peripheral I/O (A/D converter, MJT, serial interface or CAN) DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a transfer on another channel.) Interrupt request: DMA transfer counter register underflow Multijunction timer (MJT) 37-channel multi-functional timer 16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels, 16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels Flexible timer configuration is possible by interconnecting these timer channels. Interrupt request: Counter underflow or overflow and rising, falling or both edges or “H” or “L”level from the TIN pin (These can be used as external interrupt inputs irrespective of timer operation.) DMA transfer request: Counter underflow or overflow and rising, falling or both edges or “H” or “L” level from the TIN pin (These can be used as external DMA transfer request inputs irrespective of timer operation.)

1-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 1.2.1 Features of the 32176 (2/2) A/D converter (ADC) 16 channels: 10-bit resolution A/D converter Conversion modes: Ordinary conversion modes plus comparator mode are built-in Operation modes: Single conversion mode and n-channel scan mode (n = 1–16) Sample-and-hold function: Sample-and-hold function can be enabled or disabled as necessary. A/D disconnection detection assist function: Influences of the analog input voltage leakage from any preceding channel during scan mode operation are suppressed. An inflow current bypass circuit is built-in. Can generate an interrupt or start DMA transfer upon completion of A/D conversion. Either 8 or 10-bit conversion results can be read out. Interrupt request: Completion of A/D conversion DMA transfer request: Completion of A/D conversion Serial Interface (SIO) 4-channel serial interface Can be chosen to be clock-synchronized serial interface or clock-asynchronous serial interface. Data can be transferred at high speed (2 Mbits per second during clock-synchronized mode or 156 Kbits per second during UART mode when f(BCLK) = 20 MHz). Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed DMA transfer request: Reception completed or transmit buffer empty CAN 16 message slots × 2 blocks Compliant with CAN specification 2.0B active. Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off or single shot DMA transfer request: Transmission failed, transmission completed or reception completed Real-Time Debugger Internal RAM can be rewritten or monitored independently of the CPU by entering a command (RTD) from the outside. Comes with exclusive clock-synchronized serial ports. Interrupt request: RTD interrupt command input Interrupt Controller (ICU) Controls interrupt requests from the internal peripheral I/O. Supports 8-level interrupt priority including an interrupt disabled state. External interrupt: 11 sources (SBI#, TIN0,TIN3, TIN16-TIN23) TIN pin input sensing: Rising, falling or both edges or “H” or “L” level Wait Controller Controls wait states for access to the external extension area. Insertion of 1-4 wait states by setting up in software + wait state extension by entering WAIT# signal PLL A multiply-by-4 clock generating circuit Clock Maximum external input clock frequency (XIN) is 10.0 MHz. (Note 3) CPUCLK: Operating clock for the M32R-CPU core, internal flash memory and internal RAM The maximum CPU clock is 40 MHz (when f(XIN) = 10 MHz). BCLK: Operating clock for the internal peripheral I/O and external data bus The maximum peripheral clock is 20 MHz (peripheral module access when f(XIN) = 10 MHz). Clock output (BCLK pin output): A clock with the same frequency as BCLK is output from this pin. JTAG Boundary scan function VDC Internal power supply generating circuit: Generates the internal power supply (2.5 V) from an external single power supply (5 or 3.3 V). Ports Input/output pins: 96 pins The port input threshold can be set in a program to one of three levels individually for each port group (with or without Schmitt circuit, selectable). Note 1: The 10000 (10k) times rewritable product is offered as an optional item. For details about it, please contact your nearest office of Renesas or its distributor. Note 2: Block 1: H’0000 2000 to H’0000 2FFFF Block 2: H’0000 3000 to H’0000 3FFFF Note 3: Maximum external input clock frequency (XIN) for the M32176F2VFP, M32176F3VFP and M32176F4VFP is 8.0 MHz.

1-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 1.3.1 Pin Function Diagram RESET#

32176 Group

P46/A13, P47/A14 P225/A12 Address bus P00/DB0-P07/DB7 P10/DB8-P17/DB15 Data bus P72/HREQ# P73/HACK# Bus control P71/WAIT# P43/RD# P44/CS0# P45/CS1# P41/BLW#/BLE# P42/BHW#/BHE# Port 2 Port 3 Port 4 Port 22 Port 0 Port 1 Port 7 Port 4 XOUT EXCOSC-VCC OSC-VSS MOD0 MOD2 (Note 1) MOD1 P150/TIN0, P153/TIN3 P130/TIN16-P137/TIN23 Port 15 Port 13 P124/TCLK0-P127/TCLK3 4 Multi- junction timer P93/TO16-P97/TO20 P100/TO8-P107/TO15 P110/TO0-P117/TO7 Port 12 Port 11 Port 10 Port 9 P74/RTDTXD/TXD3 P75/RTDRXD/RXD3 P76/RTDACK/CTX1 P77/RTDCLK/CRX1 Real time debuggerPort 7 P70/BCLK/WR#Port 7 P82/TXD0 P83/RXD0 P84/SCLKI 0/SCLKO 0 P85/TXD1 P86/RXD1 P87/SCLKI 1/SCLKO 1 Serial Interface CAN1 Serial Interface Port 8 AVCC0 P61-P63Port 6 VREF0 VDDE N.C. (Note 2) FP EXCVCC VCCE P174/TXD2 P175/RXD2 Port 17 AD0IN0-AD0IN15 P220/CTX0 P221/CRX0CAN0 JTMS JTCK JTRST JTDO JTAG JTDI Port 22 SBI# AVSS0 Clock Reset Mode A/D converter Interrupt controller Note 1: MOD2 must be connected to the ground. Note 2: N.C. indicates non-connected pin. Connect the pin to the power supply, ground, or the like that has no voltage change. Note: • The symbol "#" suffixed to the pin (or signal) name means that the pins (or signals) are "L."

1-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 1.3.1 Description of Pin Functions (1/4) Type Pin Name Signal Name Input/Output Description EXCVCC Internal power supply – This pin connects an external capacitor. VDDE RAM power supply – Backup power supply for the internal RAM (5.0 V ± 0.5 V or 3.3 V ± 0.3 V). EXCVDD Internal power – This pin connects an external capacitor for the internal power supply of RAM supply of the internal RAM. VSS Ground – Connect all VSS pins to ground (GND). Clock XIN, Clock input Input These are clock input/output pins. A PLL-based ×4 frequency XOUT Clock output Output multiplier is included, which accepts as input a clock whose frequency is 1/4 of the internal CPU clock frequency. (XIN input is 10 MHz when f(CPUCLK) = 40 MHz.) BCLK System clock Output This pin outputs a clock whose frequency is twice that of the external input clock (XIN). (BCLK output is 20 MHz when f(CPUCLK) = 40 MHz.) Use this clock to synchronize the operation of external devices. EXCOSC Clock power supply – This pin connects an external capacitor for the oscillator circuit. -VCC OSC-VSS Clock ground – Connect OSC-VSS to ground. Reset RESET# Reset Input Reset input pin for the internal circuit. Mode MOD0– Mode Input Set the microcomputer’s operation mode. MOD2 MOD0 MOD1 MOD2 Mode L L L Single-chip mode L H L External extension mode H L L Processor mode (boot mode) (Note1) H H L (Settings inhibited) X X H (Settings inhibited) X: Don’t care Flash FP Flash protect Input This special pin protects the flash memory against rewrites in hardware. Address bus A12–A30 Address bus Output To allow two areas of up to 1 Mbyte memory space to be connected external to the chip, the device has 19 address lines (A12–A30). A31 is not output. Note 1: Boot mode requires that the FP pin should be at “H” level. For details about boot mode, see Chapter 6, “Internal Memory.”

1-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 1.3.1 Description of Pin Functions (2/4) Type Pin Name Signal Name Input/Output Description Data bus DB0–DB15 Data bus Input/output This 16-bit data bus is used to connect external devices. When writing in byte units during a write cycle, the output data at the invalid byte position is undefined. During a read cycle, data on the entire 16-bit data bus is always read in. However, only the data at the valid byte position is transferred into the internal circuit. Bus control CS0#,CS1# Chip select Output These are chip select signals for external devices. RD# Read Output This signal is output when reading an external device. WR# Write Output This signal is output when writing to an external device. BHW#,BLW# Byte high write/ Output When writing to an external device, this signal indicates the Byte low write valid byte position to which data is transferred. BHW# and BLW# correspond to the upper address side (bits 0–7 are valid) and the lower address side (bits 8–15 are valid), respectively. BHE# Byte high enable Output During an external device access, this signal indicates that the high-order data (bits 0–7) is valid. BLE# Byte low enable Output During an external device access, this signal indicates that the low-order data (bits 8–15) is valid. WAIT# Wait Input When accessing an external device, a “L” signal input on WAIT# pin extends the wait cycle. HREQ# Hold request Input This input is used by an external device to request control of the external bus. A “L” level input on HREQ# pin places the CPU in a hold state. HACK# Hold acknowledge Output This signal notifies that the CPU has entered a hold state and relinquished control of the external bus. Multijunction TIN0, TIN3, Timer input Input Input pins for the multijunction timer. timer TIN16–TIN23 TO0–TO20 Timer output Output Output pins for the multijunction timer. TCLK0 Timer clock Input Clock input pins for the multijunction timer. –TCLK3 A/D converter AVCC0 Analog power supply – AVCC0 is the power supply for the A/D0 converter. Connect AVCC0 to the power supply rail. AVSS0 Analog ground – AVSS0 is the analog ground for the A/D0 converter. Connect AVSS0 to ground. AD0IN0 Analog input Input 16-channel analog input pins for the A/D0 converter. –AD0IN15 VREF0 Reference voltage Input VREF0 is the reference voltage input pin for the A/D0 input converter. Interrupt SBI# System break Input This is the system break interrupt (SBI) input pin for the controller interrupt interrupt controller.

1-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 1.3.1 Description of Pin Functions (3/4) Type Pin Name Signal Name Input/Output Description Serial Interface SCLKI0/UART transmit/receiveInput/outputWhen channel 0 is in UART mode: SCLKO0 clock output or CSIO This pin outputs a clock derived from BRG output by transmit/receive clock dividing it by 2. input/output When channel 0 is in CSIO mode: This pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected. SCLKI1/ UART transmit/receiveInput/output When channel 1 is in UART mode: SCLKO1 clock output or CSIO This pin outputs a clock derived from BRG output by transmit/receive clock dividing it by 2. input/output When channel 1 is in CSIO mode: This pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected. TXD0–TXD3 Transmit data Output Transmit data output pin for serial interface. RXD0–RXD3 Received data Input Received data input pin for serial interface. Real-time RTDTXD Transmit data Output Serial data output pin for the real-time debugger. debugger RTDRXD Received data Input Serial data input pin for the real-time debugger. (RTD) RTDCLK Clock input Input Serial data transmit/receive clock input pin for the real-time debugger. RTDACK Acknowledge Output A ”L” pulse is output from this pin synchronously with the start clock for the real-time debugger’s serial data output word. The “L” pulse width indicates the type of command/data received by the real-time debugger. CAN CTX0, CTX1 Data output Output This pin outputs data from the CAN module. CRX0, CRX1 Data input Input This pin inputs the data to the CAN module. JTAG JTMS Test mode Input Test mode select input to control the state transition of the test circuit. JTCK Clock Input Clock input for the debug module and test circuit. JTRST Test reset Input Test reset input to initialize the test circuit asynchronously with device operation. JTDI Serial input Input This pin inputs the test instruction code or test data that is serially received. JTDO Serial output Output This pin outputs the test instruction code or test data serially.

1-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 1.3.1 Description of Pin Functions (4/4) Type Pin Name Signal Name Input/Output Description Input/output P00–P07 Input/output port 0 Input/output Programmable input/output port. ports P10–P17 Input/output port 1 Input/output (Note 1) P20–P27 Input/output port 2 Input/output P30–P37 Input/output port 3 Input/output P41–P47 Input/output port 4 Input/output P61–P63 Input/output port 6 Input/output P70–P77 Input/output port 7 Input/output P82–P87 Input/output port 8 Input/output P93–P97 Input/output port 9 Input/output P100–P107 Input/output port 10 Input/output P110–P117 Input/output port 11 Input/output P124–P127 Input/output port 12 Input/output P130–P137 Input/output port 13 Input/output P150, P153 Input/output port 15 Input/output P174, P175 Input/output port 17 Input/output P220, P221(Note 2), P225, Input/output port 22 Input/output Note 1: Input/output port 5 is reserved for future use. Also, input/output ports 14, 16 and 18-21 are nonexistent. Note 2: P221 is input-only port.

1-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 1.4.1 Pin Assignment Diagram (Top View) 899099 98 97 96 9594 93 929110310210110810 105104 737484 75767778798081828385868788100 2 43 5 6 7 8 9 3522 23 24 25 26 2728 29 30 31 32 33 3411 12 13 14 15 16 1718 19 2021101 36 P43/RD# VSS EXCVCC P41/BLW#/BLE# P153/TIN3 P150/TIN0 VCCE P107/TO15 P106/TO14 P104/TO12 P103/TO11 MOD2 (Note1) P125/TCLK1 P124/TCLK0 N.C. (Note 2) EXCOSC-VCC XOUT XI N OS C-VS S 7/A2 6/A2 3/A1 1/A1 0/A1 5/A2 A19 2/A1 P27/A3 P25/ A28 6/A29 P24/A2 P11/ DB9 P07/ DB7 5/DB5 P02/DB 1/DB P00/ DB0 3/A26 2/A2 0/A2 P10/DB P06/DB6P0 4/DB4 P03/ DB3 P21/ P44/CS0# P45/CS1# P47/A14 P46/A13 P221/CRX0 P14/DB12 P15/DB13 P16/DB14 P17/DB15 P82/TXD0 P83/RXD0 P174/TXD2 P175/RXD2 VSS EXCVCC VREF0 AVCC0 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AVSS0 P85/TXD1 P86/RXD1 RE SE P87/SCLKI1/SCLKO1 VSS FP P9 4/TO17 P74/RTDTXD/ TXD3 P75/RTDRXD/ RXD3 P76/RTDACK/C TX1 P77/RTDCLK/C RX1 P61P6 14/ TO4 P115/ TO5 16/ TO6 17/TO7 VCCEMOD 12/ TO2 /TO 0/BCLK / W R # P71/ WAIT# P72/ HRE SBI#MOD P93/ TO16 3/ HAC VDDE EXCVDDVS S P127/TCLK3 P100/ TO8 01/TO9 02/ TO10 P137/TIN23 P136/TIN22 P135/TIN21 P134/TIN20 P105/TO13 /TO0 11/ TO1 P97/ TO20 P96/TO 5/TO18 P133/TIN19 P132/TIN18 P131/TIN17 P130/TIN16 P126/TCLK2 JTDI JTDO JTRST JTCK JTMS 2/DB P84/SCLKI0/SCLKO0 VCCE VCCE 112 119 116 115 113 111 110 109 120 117 114 124 132 130 129 127 121 137 144 143 142 141 140 139 138 133 136 135 134 123 122 131 128 125 126 118 P220/CTX0 /A1 P13/DB11 VSS P42/BHW#/BHE# Note 1: MOD2 must be connected to the ground. Note 2: N.C. indicates non-connected pin. Connect the pin to the power supply, ground, or the like that has no voltage change. Note: The symbol "#" suffixed to the pin (or signal) name means that the pins (or signals) are "L."

1-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The pins directed for input go to a high-impedance state (Hi-Z) when reset. The term “when reset” refers to the period when input on RESET# pin is held “L” (the device remains reset), as well as when the RESET# pin is released back “H” (the device comes out of reset). Table 1.4.1 Pin Assignments of the 32176 (1/4) Pin State When Reset Port Other than port Other than port Function Type State during reset State upon exiting reset

1 P221/CRX0 P221 CRX0 - Input P221 Input Hi-Z Hi-Z

During single-chip mode P225 Input Hi-Z Hi-Z During external extension and processor modes A12 Output Hi-Z Undefined

3 OSC-VSS - OSC-VSS -- OSC-VSS ---

4X I N - XIN - Input XIN Input -- 5X O U T - XOUT - Output XOUT Output XOUT XOUT 6E X C O S C - V C C - EXCOSC- V CC -- EXCOSC-V CC --- During single-chip mode P30 Input Hi-Z Hi-Z During external extension and processor modes A15 Output Hi-Z Undefined During single-chip mode P31 Input Hi-Z Hi-Z During external extension and processor modes A16 Output Hi-Z Undefined During single-chip mode P32 Input Hi-Z Hi-Z During external extension and processor modes A17 Output Hi-Z Undefined During single-chip mode P33 Input Hi-Z Hi-Z During external extension and processor modes A18 Output Hi-Z Undefined During single-chip mode P34 Input Hi-Z Hi-Z During external extension and processor modes A19 Output Hi-Z Undefined During single-chip mode P35 Input Hi-Z Hi-Z During external extension and processor modes A20 Output Hi-Z Undefined During single-chip mode P36 Input Hi-Z Hi-Z During external extension and processor modes A21 Output Hi-Z Undefined During single-chip mode P37 Input Hi-Z Hi-Z During external extension and processor modes A22 Output Hi-Z Undefined During single-chip mode P20 Input Hi-Z Hi-Z During external extension and processor modes A23 Output Hi-Z Undefined During single-chip mode P21 Input Hi-Z Hi-Z During external extension and processor modes A24 Output Hi-Z Undefined During single-chip mode P22 Input Hi-Z Hi-Z During external extension and processor modes A25 Output Hi-Z Undefined During single-chip mode P23 Input Hi-Z Hi-Z During external extension and processor modes A26 Output Hi-Z Undefined

20 VCCE - VCCE -- VCCE ---

21 VSS - VSS -- VSS ---

During single-chip mode P24 Input Hi-Z Hi-Z During external extension and processor modes A27 Output Hi-Z Undefined During single-chip mode P25 Input Hi-Z Hi-Z During external extension and processor modes A28 Output Hi-Z Undefined During single-chip mode P26 Input Hi-Z Hi-Z During external extension and processor modes A29 Output Hi-Z Undefined During single-chip mode P27 Input Hi-Z Hi-Z During external extension and processor modes A30 Output Hi-Z Undefined During single-chip mode P00 Input Hi-Z Hi-Z During external extension and processor modes DB0 Input/output Hi-Z Hi-Z - Input/output

25 P27/A30

26 P00/DB0 P00 DB0

Input/output - Input/output - Input/output

24 P26/A29 P26 A29

23 P25/A28 P25 A28

Input/output

19 P23/A26

22 P24/A27 P24 A27

Input/output - Input/output - Input/output

18 P22/A25 P22 A25

17 P21/A24 P21 A24

Input/output

15 P37/A22

16 P20/A23 P20 A23

Input/output - Input/output - Input/output

14 P36/A21 P36 A21

13 P35/A20 P35 A20

Input/output

11 P33/A18

12 P34/A19 P34 A19

Input/output - Input/output - Input/output

10 P32/A17 P32 A17

9 P31/A16 P31 A16

8 P30/A15

Input/output - Input/output Condition Function Pin No. Symbol Type

1-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 1.4.1 Pin Assignments of the 32176 (2/4) Pin State When Reset Port Other than port Other than port Function Type State during reset State upon exiting reset During single-chip mode P01 Input Hi-Z Hi-Z During external extension and processor modes DB1 Input/output Hi-Z Hi-Z During single-chip mode P02 Input Hi-Z Hi-Z During external extension and processor modes DB2 Input/output Hi-Z Hi-Z During single-chip mode P03 Input Hi-Z Hi-Z During external extension and processor modes DB3 Input/output Hi-Z Hi-Z During single-chip mode P04 Input Hi-Z Hi-Z During external extension and processor modes DB4 Input/output Hi-Z Hi-Z During single-chip mode P05 Input Hi-Z Hi-Z During external extension and processor modes DB5 Input/output Hi-Z Hi-Z During single-chip mode P06 Input Hi-Z Hi-Z During external extension and processor modes DB6 Input/output Hi-Z Hi-Z During single-chip mode P07 Input Hi-Z Hi-Z During external extension and processor modes DB7 Input/output Hi-Z Hi-Z During single-chip mode P10 Input Hi-Z Hi-Z During external extension and processor modes DB8 Input/output Hi-Z Hi-Z During single-chip mode P11 Input Hi-Z Hi-Z During external extension and processor modes DB9 Input/output Hi-Z Hi-Z During single-chip mode P12 Input Hi-Z Hi-Z During external extension and processor modes DB10 Input/output Hi-Z Hi-Z During single-chip mode P13 Input Hi-Z Hi-Z During external extension and processor modes DB11 Input/output Hi-Z Hi-Z During single-chip mode P14 Input Hi-Z Hi-Z During external extension and processor modes DB12 Input/output Hi-Z Hi-Z During single-chip mode P15 Input Hi-Z Hi-Z During external extension and processor modes DB13 Input/output Hi-Z Hi-Z During single-chip mode P16 Input Hi-Z Hi-Z During external extension and processor modes DB14 Input/output Hi-Z Hi-Z During single-chip mode P17 Input Hi-Z Hi-Z During external extension and processor modes DB15 Input/output Hi-Z Hi-Z

42 VREF0 - VREF0 -- VREF0 ---

43 AVCC0 - AVCC0 -- AVCC0 ---

44 AD0IN0 - AD0IN0 - Input AD0IN0 Input Hi-Z Hi-Z

45 AD0IN1 - AD0IN1 - Input AD0IN1 Input Hi-Z Hi-Z

46 AD0IN2 - AD0IN2 - Input AD0IN2 Input Hi-Z Hi-Z

47 AD0IN3 - AD0IN3 - Input AD0IN3 Input Hi-Z Hi-Z

48 AD0IN4 - AD0IN4 - Input AD0IN4 Input Hi-Z Hi-Z

49 AD0IN5 - AD0IN5 - Input AD0IN5 Input Hi-Z Hi-Z

50 AD0IN6 - AD0IN6 - Input AD0IN6 Input Hi-Z Hi-Z

51 AD0IN7 - AD0IN7 - Input AD0IN7 Input Hi-Z Hi-Z

52 AD0IN8 - AD0IN8 - Input AD0IN8 Input Hi-Z Hi-Z

53 AD0IN9 - AD0IN9 - Input AD0IN9 Input Hi-Z Hi-Z

54 AD0IN10 - AD0IN10 - Input AD0IN10 Input Hi-Z Hi-Z

55 AD0IN11 - AD0IN11 - Input AD0IN11 Input Hi-Z Hi-Z

56 AD0IN12 - AD0IN12 - Input AD0IN12 Input Hi-Z Hi-Z

57 AD0IN13 - AD0IN13 - Input AD0IN13 Input Hi-Z Hi-Z

58 AD0IN14 - AD0IN14 - Input AD0IN14 Input Hi-Z Hi-Z

59 AD0IN15 - AD0IN15 - Input AD0IN15 Input Hi-Z Hi-Z

Input/output Function - Input/output - Input/output - Input/output

30 P04/DB4 P04 DB4

29 P03/DB3 P03 DB3

27 P01/DB1 P01 DB1

28 P02/DB2

No. -DB13 -DB11 -DB9 Input/output41 P17/DB15 P17 DB15 Input/output

40 P16/DB14 P16 DB14 - Input/output

39 P15/DB13 P15

38 P14/DB12 P14 DB12 - Input/output

37 P13/DB11 P13

36 P12/DB10 P12 DB10 - Input/output

35 P11/DB9 P11

Input/output

33 P07/DB7

34 P10/DB8 P10 DB8

Input/output - Input/output - Input/output

32 P06/DB6 P06 DB6

31 P05/DB5 P05 DB5

1-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 1.4.1 Pin Assignments of the 32176 (3/4) Note 1: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin. When a “L” level is applied to the JTRST pin, the JTCK, JTDI, JTDO and JTMS pins are in the high impedance state. Pin State When Reset Port Other than port Other than port Function Type State during reset State upon exiting reset

60 AVSS0 - AVSS0 -- AVSS0 ---

61 EXCVCC - EXCVCC -- EX CVCC ---

62 VSS - VSS -- VSS ---

63 P174/TXD2 P174 TXD2 - Input/output P174 Input Hi-Z Hi-Z

64 P175/RXD2 P175 RXD2 - Input/output P175 Input Hi-Z Hi-Z

65 VCCE - VCCE - Input/output VCCE ---

66 P82/TXD0 P82 TXD0 - Input/output P82 Input Hi-Z Hi-Z

67 P83/RXD0 P83 RXD0 - Input/output P83 Input Hi-Z Hi-Z

68 P84/SCLKI0/SCLKO0 P84 SCLKI0 SCLKO0 Input/output P84 Input Hi-Z Hi-Z

69 P85/TXD1 P85 TXD1 - Input/output P85 Input Hi-Z Hi-Z

70 P86/RXD1 P86 RXD1 - Input/output P86 Input Hi-Z Hi-Z

71 P87/SCLKI1/SCLKO1 P87 SCLKI1 SCLKO1 Input/output P87 Input Hi-Z Hi-Z

72 VSS - VSS -- VSS ---

73 EXCVDD - EXCVDD -- EX CVDD ---

74 P61 P61 -- Input/output P61 Input Hi-Z Hi-Z

75 P62 P62 -- Input/output P62 Input Hi-Z Hi-Z

76 P63 P63 -- Input/output P63 Input Hi-Z Hi-Z

77 SBI# SBI# - Input SBI# Input Hi-Z Hi-Z

78 P70/BCLK/WR# P70 BCLK WR# Input/output P70 Input Hi-Z Hi-Z

79 P71/WAIT# P71 WAIT# - Input/output P71 Input Hi-Z Hi-Z

80 P72/HREQ# P72 HREQ# - Input/output P72 Input Hi-Z Hi-Z

81 P73/HACK# P73 HACK# - Input/output P73 Input Hi-Z Hi-Z

82 P74/RTDTXD/TXD3 P74 RTDTXD TXD3 Input/output P74 Input Hi-Z Hi-Z

83 P75/RTDRXD/RXD3 P75 RTDRXD RXD3 Input/output P75 Input Hi-Z Hi-Z

84 P76/RTDACK/CTX1 P76 RTDACK CTX1 Input/output P76 Input Hi-Z Hi-Z

85 P77/RTDCLK/CRX1 P77 RTDCLK CRX1 Input/output P77 Input Hi-Z Hi-Z

86 P93/TO16 P93 TO16 - Input/output P93 Input Hi-Z Hi-Z

87 P94/TO17 P94 TO17 - Input/output P94 Input Hi-Z Hi-Z

88 P95/TO18 P95 TO18 - Input/output P95 Input Hi-Z Hi-Z

89 P96/TO19 P96 TO19 - Input/output P96 Input Hi-Z Hi-Z

90 P97/TO20 P97 TO20 - Input/output P97 Input Hi-Z Hi-Z

91 RESET# - RESET# - Input RESET# Input Hi-Z Hi-Z

92 MOD0 - MOD0 - Input MOD0 Input Hi-Z Hi-Z

93 MOD1 - MOD1 - Input MOD1 Input Hi-Z Hi-Z

94 FP - FP - Input FP Input Hi-Z Hi-Z

95 VCCE - VCCE -- VCCE ---

96 VSS - VSS -- VSS ---

97 P110/TO0 P110 TO0 - Input/output P110 Input Hi-Z Hi-Z

98 P111/TO1 P111 TO1 - Input/output P111 Input Hi-Z Hi-Z

99 P112/TO2 P112 TO2 - Input/output P112 Input Hi-Z Hi-Z

100 P113/TO3 P113 TO3 - Input/output P113 Input Hi-Z Hi-Z

101 P114/TO4 P114 TO4 - Input/output P114 Input Hi-Z Hi-Z

102 P115/TO5 P115 TO5 - Input/output P115 Input Hi-Z Hi-Z

103 P116/TO6 P116 TO6 - Input/output P116 Input Hi-Z Hi-Z

104 P117/TO7 P117 TO7 - Input/output P117 Input Hi-Z Hi-Z

105 P100/TO8 P100 TO8 - Input/output P100 Input Hi-Z Hi-Z

106 P101/TO9 P101 TO9 - Input/output P101 Input Hi-Z Hi-Z

107 P102/TO10 P102 TO10 - Input/output P102 Input Hi-Z Hi-Z

108 VDDE - VDDE -- VDDE ---

109 JTMS (Note 1) - JTMS - Input JTMS Input Hi-Z Hi-Z

110 JTCK (Note 1) - JTCK - Input JTCK Input Hi-Z Hi-Z

111 JTRST (Note 1) - JTRST - Input JTRST Input Hi-Z Hi-Z

112 JTDO (Note 1) - JTDO - Output JTDO Output Hi-Z Hi-Z

113 JTDI (Note 1) - JTDI - Input JTDI Input Hi-Z Hi-Z

114 P103/TO11 P103 TO11 - Input/output P103 Input Hi-Z Hi-Z

115 P104/TO12 P104 TO12 - Input/output P104 Input Hi-Z Hi-Z

116 P105/TO13 P105 TO13 - Input/output P105 Input Hi-Z Hi-Z

117 P106/TO14 P106 TO14 - Input/output P106 Input Hi-Z Hi-Z

No. Symbol Type Condition Function

1-1732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 1.4.1 Pin Assignments of the 32176 (4/4) Pin State When Reset Port Other than port Other than port Function Type State during reset State upon exiting reset

118 P107/TO15 P107 TO15 - Input/output P107 Input Hi-Z Hi-Z

119 P124/TCLK0 P124 TCLK0 - Input/output P124 Input Hi-Z Hi-Z

120 P125/TCLK1 P125 TCLK1 - Input/output P125 Input Hi-Z Hi-Z

121 P126/TCLK2 P126 TCLK2 - Input/output P126 Input Hi-Z Hi-Z

122 P127/TCLK3 P127 TCLK3 - Input/output P127 Input Hi-Z Hi-Z

123 MOD2 - MOD2 - - MOD2 - - -

124 P130/TIN16 P130 TIN16 - Input/output P130 Input Hi-Z Hi-Z

125 P131/TIN17 P131 TIN17 - Input/output P131 Input Hi-Z Hi-Z

126 P132/TIN18 P132 TIN18 - Input/output P132 Input Hi-Z Hi-Z

127 P133/TIN19 P133 TIN19 - Input/output P133 Input Hi-Z Hi-Z

128 P134/TIN20 P134 TIN20 - Input/output P134 Input Hi-Z Hi-Z

129 P135/TIN21 P135 TIN21 - Input/output P135 Input Hi-Z Hi-Z

130 P136/TIN22 P136 TIN22 - Input/output P136 Input Hi-Z Hi-Z

131 P137/TIN23 P137 TIN23 - Input/output P137 Input Hi-Z Hi-Z

132 VCCE - VCCE - - VCCE - - -

133 P150/TIN0 P150 TIN0 -

Input/output P150 Input Hi-Z Hi-Z

134 P153/TIN3 P153 TIN3 - Input/output P153 Input Hi-Z Hi-Z

During single-chip mode P41 Input Hi-Z Hi-Z During external extension and processor modes BLW# Output Hi-Z "H" lev el During single-chip mode P42 Input Hi-Z Hi-Z During external extension and processor modes BHW# Output Hi-Z "H" lev el

137 EX CVCC - EX CVCC - - EX CVCC - - -

138 VSS - VSS - - VSS - - -

During single-chip mode P43 Input Hi-Z Hi-Z During external extension and processor modes RD# Output Hi-Z "H" level During single-chip mode P44 Input Hi-Z Hi-Z During external extension and processor modes CS0# Output Hi-Z "H" level During single-chip mode P45 Input Hi-Z Hi-Z During external extension and processor modes CS1# Output Hi-Z "H" level During single-chip mode P46 Input Hi-Z Hi-Z During external extension and processor modes A13 Output Hi-Z Undefined During single-chip mode P47 Input Hi-Z Hi-Z During external extension and processor modes A14 Output Hi-Z Undefined

144 P220/CTX0 P220 CTX0 - Input/output P220 Input Hi-Z Hi-Z

BLE# BHE# Input/output Input/output P41 P42 BLW# BHW# 135 136 P41/BLW#/BLE# P42/BHW#/BHE# Pin No. - Input/output - Input/output

141 P45/CS1# P45 CS1# -

Input/output

142 P46/A13 P46 A13

143 P47/A14 P47 A14

140 P44/CS0# P44 CS0#

139 P43/RD# P43 RD# - Input/output

1-1832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 This page is blank for reasons of layout.

2.1 CPU Registers

2.2 General-purpose Registers

2.3 Control Registers

2.4 Accumulator

2.5 Program Counter

2.6 Data Formats

2.7 Supplementary Explanation for LOCK and

UNLOCK Instruction Execution

2-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The M32R contains 16 general-purpose registers, five control registers, an accumulator and a program counter. The accumulator is configured with 56 bits, and all other registers are 32 bits wide. The 16 general-purpose registers (R0–R15) are of 32-bit width and are used to retain data, base address, etc. R14 is used as the link register and R15 as the stack pointer. The link register is used to store the return address when executing a subroutine call instruction. The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) are alternately represented by R15 depending on the value of the Stack Mode (SM) bit in the Processor Status Word Register (PSW). Upon exiting the reset state, the value of the general-purpose registers is undefined. Figure 2.2.1 General-purpose Registers b0b0 b31 R10 R11 R12 R13 R14 (Link register) R15 (Stack pointer) (Note 1) Note 1: The stack pointer functions as either the SPI or the SPU depending on the value of the SM bit in the PSW. b31

2-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 There are 5 control registers which are the Processor Status Word Register (PSW), the Condition Bit Register (CBR), the Interrupt Stack Pointer (SPI), the User Stack Pointer (SPU) and the Backup PC (BPC). The dedicated MVTC and MVFC instructions are used for writing and reading these control registers. Figure 2.3.1 Control Registers Backup PC BPCCR6 b31 PSW CBR SPI SPU CR0 CR1 CR2 CR3 Processor Status Word Register Condition Bit Register Interrupt Stack Pointer User Stack Pointer CRn Notes: CRn (n = 0-3 and 6) denotes the control register number. The dedicated MVTC and MVFC instructions are used for writing and reading these control registers.

2-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

2.3.1 Processor Status Word Register: PSW (CR0)

The Processor Status Word Register (PSW) indicates the M32R status. It consists of the PSW field which is regularly used, and the BPSW field where a copy of the PSW field is saved when an EIT occurs. The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and the Condition (C) bit. The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt Enable (BIE) bit and the Backup Condition (BC) bit. Upon exiting the reset state, BSM, BIE and BC are undefined. All other bits are "0". 0000 000 0000000 7654321 8 9 1 01 11 21 31 4 b 1 5b0 ?? 00000?00000000 BC SM IE C 23 24 25 26 27 28 29 30 b3117 18 19 20 21 22b16 BIEBSM BPSW field 0 0 PSW field <Upon exiting reset: B’0000 0000 0000 0000 ??00 000? 0000 0000> b Bit Name Function R W 0–15 No function assigned. Fix to "0". 00

16 BSM Saves value of SM bit when EIT occurs R W

17 BIE Saves value of IE bit when EIT occurs R W

18–22 No function assigned. Fix to "0". 00

23 BC Saves value of C bit when EIT occurs R W

24 SM 0: Uses R15 as the interrupt stack pointer R W

Stack Mode Bit 1: Uses R15 as the user stack pointer

25 IE 0: Does not accept interrupt R W

Interrupt Enable Bit (Note 1) 1: Accepts interrupt 26–30 No function assigned. Fix to "0". 00

31 C Indicates carry, borrow or overflow resulting R W

Condition Bit from operations (instruction dependent) Note 1: Interruput which is controllable is External Interrupt (EI). Reserved Instruction Exception (RIE), Address Except (AE), Reset Interrupt (RI), System Break Interrupt (SBI) and Trap are not controlled.

2-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

2.3.2 Condition Bit Register: CBR (CR1)

The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value written to the PSW register’s C bit is reflected in this register. The register can only be read. (Writing to the register with the MVTC instruction is ignored.) Upon exiting the reset state, the value of CBR is H’0000 0000. b0 b31

0000000000000000000000000000000 CCBR

2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3)

The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) retain the address of the current stack pointer. These registers can be accessed as the general-purpose register R15. R15 switches between repre- senting the SPI and SPU depending on the value of the Stack Mode (SM) bit in the PSW. Upon exiting the reset state, the values of the SPI and SPU are undefined. b0 b31 SPI SPI b0 b31 SPU SPU

2.3.4 Backup PC: BPC (CR6)

The Backup PC (BPC) is used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31 is fixed to "0". When an EIT occurs, the register sets either the PC value immediately before the EIT occurred or the PC value for the next instruction. The BPC value is loaded to the PC when the RTE instruction is executed. However, the values of the lower 2 bits of the PC are always "00" when returned. (PC always returns to the word-aligned address.) Upon exiting the reset state, the value of the BPC is undefined. b0 b31 0BPCBPC

2-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The Accumulator (ACC) is a 56-bit register used for DSP function instructions. The accumulator is handled as a 64-bit register when accessed for read or write. When reading data from the accumulator, the value of bit 8 is sign-extended. When writing data to the accumulator, bits 0 to 7 are ignored. The accumulator is also used for the multiply instruction “MUL,” in which case the accumulator value is destroyed by instruction execution. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the high-order 32 bits (bits 0–31) and the low-order 32 bits (bits 32–63), respectively. Use the MVFACHI, MVFACLO and MVFACMI instructions for reading data from the accumulator. The MVFACHI, MVFACLO and MVFACMI instructions read data from the high-order 32 bits (bits 0–31), the low-order 32 bits (bits 32–63) and the middle 32 bits (bits 16–47), respectively. Upon exiting the reset state, the value of accumulator is undefined. 15b0 16 7 8 31 32 47 48 b63 ACC (Note 1) Read range of MVFACMI instruction Write and read ranges of MVTACLO and MVFACLO instructions Write and read ranges of MVTACHI and MVFACHI instructions Note 1: When read, bits 0 to 7 always show the sign-extended value of the value of bit 8. Writing to this bit field is ignored. The Program Counter (PC) is a 32-bit counter that retains the address of the instruction being executed. Since the M32R instruction starts with even-numbered addresses, the LSB (bit 31) is always "0". Upon exiting the reset state, the value of PC is H’0000 0000. b0 b31 0PCPC

2-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

2.6.1 Data Types

The data types that can be handled by the M32R instruction set are signed or unsigned 8, 16 and 32-bit integers. The signed integers are represented by 2’s complements. Figure 2.6.1 Data Types Signed byte (8-bit) integer Unsigned byte (8-bit) integer Signed halfword (16-bit) integer Unsigned halfword (16-bit) integer Signed word (32-bit) integer Unsigned word (32-bit) integer b15 b15 b31 b31 S S S S: Sign bit

2-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

2.6.2 Data Formats

(1) Data formats in registers The data sizes in the M32R registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) to a word (32-bit) quantity before being loaded in the register. When storing data from a register into a memory, the 32-bit data, the 16-bit data on the LSB side and the 8-bit data on the LSB side of the register are stored into memory by the ST, STH and STB instructions, respectively. Figure 2.6.2 Data Formats in Registers Rn b0 b31 <Load> Byte Rn b0 b31 Halfword Rn b0 b31 Word Sign-extended (LDB instruction) or zero-extended (LDUB instruction) From memory (LDB, LDUB instructions) <Store> Rn b0 b31 Byte Rn b0 b31 Halfword Rn b0 b31 Word To memory (STB instruction) To memory (STH instruction) To memory (ST instruction) From memory (LDH, LDUH instructions) From memory (LD instruction) Sign-extended (LDH instruction) or zero-extended (LDUH instruction)

2-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) Data formats in memory The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). Although byte data can be located at any address, halfword and word data must be located at the addresses aligned with a halfword boundary (least significant address bit = "0") or a word boundary (two low-order address bits = "00"), respectively. If an attempt is made to access memory data that overlaps the halfword or word boundary, an address exception occurs. Figure 2.6.3 Data Formats in Memory Address Byte Halfword Word +0 address +1 address +2 address +3 address b0 b31 Byte Byte Byte Byte Halfword Halfword Word 7 8 15 16 23 24 b0 15 b0 b31 b31

2-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (3) Endian The diagrams below show a general endian system and the endian adopted for the M32R family micro- computers. Bit endian (H'01) Byte endian (H'01234567) Big endian Little endian Note: Even when bits are arranged in big endian, H'01 is not B'10000000. HH HL LH LL H'01 H'23 H'45 H'67 LL LH HL HH H'67 H'45 H'23 H'01 B'0000001 b0 b7 B'0000001 b7 b0 Figure 2.6.4 General Endian System Little/little LL LH HL HH Big/big HH HL LH LL Little/big HH HL LH LL Endian (bit/byte) Data arrangement Renesas microcomputer family name 7700 and M16C families M32R family 31–247–0 23–1615–8 0–7 24–31 8–15 16–23Bit number Example: 0x01234567 .byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67 Note: The M32R family uses the big endian for both bits and bytes. 7–031–24 15–823–16 Figure 2.6.5 Endian Adopted for the M32R Family

2-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Constant transfer LD24 Rdest, #imm24 LDI Rdest, #imm16 LDI Rdest, #imm8 SETH Rdest, #imm16 b23b0 Rdest imm24 b31b0 LD24 Rdest, #imm24 b15b0 Rdest imm16 b31b0 SETH Rdest, #imm16 00 00 Register to register transfer MV Rdest, Rsrc Control register transfer MVFC Rdest, CRsrc MVTC Rsrc, CRdest Rsrc b31b0 Rdest b31b0 Rsrc b31b0 CRdest b31b0 MVTC Rsrc, CRdest MV Rdest, Rsrc Note: The condition bit C changes state when data is written to CR0 (PSW) using the MVTC instruction. Figure 2.6.6 Transfer Instructions (4) Transfer instructions

2-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (5) Transfer from memory (signed) to registers Signed 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc Signed 16 bits LD24 Rsrc, #label LDH Rdest, @Rsrc Signed 8 bits LD24 Rsrc, #label LDB Rdest, @Rsrc label Rdest b31b0+0 +1 +2 +3 Rdestlabel 00 00 FF FF Determined by MSB b31b0 +0 +1 +2 +3 Rdestlabel 00 00 00 FF FF FF b31b0 +0 +1 +2 +3 Determined by MSB Memory Register 0: Positive number 1: Negative number 0: Positive number 1: Negative number Unsigned 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc Unsigned 16 bits LD24 Rsrc, #label LDUB Rdest, @Rsrc Unsigned 8 bits LD24 Rsrc, #label LDUH Rdest, @Rsrc Rdest 00 00 b31b0 label +0 +1 +2 +3 label +0 +1 +2 +3 Rdest b31b0 label +0 +1 +2 +3 Rdest 00 00 00 b31b0 Memory Register Figure 2.6.7 Transfer from Memory (Signed) to Registers (6) Transfer from memory (unsigned) to registers Figure 2.6.8 Transfer from Memory (Unsigned) to Registers

2-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (7) Notes on data transfer When transferring data, be aware that data arrangements in registers and memory are different. Word data (32 bits) +0 +1 +2 +3 b0 b31 HH HL LH LL b0 b31 HH HL LH LL Halfword data (16 bits) +0 +1 +2 +3 b0 b31 H L b0 b15 H L Byte data (8 bits) +0 +1 +2 +3 b0 b31 b0 b7 (R0–R15) (R0–R15) (R0–R15) +0 +1 +2 +3 b0 b31 b8 b15 (R0–R15) +0 +1 +2 +3 b0 b31 b16 b23 (R0–R15) +0 +1 +2 +3 b0 b31 b24 b31 (R0–R15) +0 +1 +2 +3 b0 b31 H L b16 b31 H L (R0–R15) Data in registers Data in memory Figure 2.6.9 Difference in Data Arrangements

2-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

2.7 Supplementary Explanation for LOCK and UNLOCK Instruction Execution

The LOCK instruction sets the LOCK bit, as well as performs an ordinary load operation. The UNLOCK instruc- tion is used to clear the LOCK bit. The LOCK bit is located inside the CPU, and cannot directly be accessed for read or write by users. This bit controls granting of bus control requested by devices other than the CPU. When LOCK bit = "0" Control of the bus requested by devices other than the CPU is granted When LOCK bit = "1" Control of the bus requested by devices other than the CPU is denied Control of the bus may be requested by devices other than the CPU in the following two cases: When DMA transfer is requested by the internal DMAC When HREQ# input is pulled low to request that the CPU be placed in a hold state

2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution

3.1 Outline of the Address Space

3.2 Operation Modes

3.3 Internal ROM and External Extension Areas

3.4 Internal RAM and SFR Areas

3.5 EIT Vector Entry

3.6 ICU Vector Table

3.7 Notes on Address Space

3-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The logical addresses of the M32R are always handled in 32 bits, providing a linear address space of up to 4 Gbytes. The address space of the M32R consists of the following: (1) User space

Internal ROM area External extension area Internal RAM area SFR (Special Function Register) area The 2 Gbytes from the address H’0000 0000 to the address H’7FFF FFFF comprise the user space. Located in this space are the internal ROM area, an external extension area, the internal RAM area and the SFR (Special Function Register) area (in which a set of internal peripheral I/O registers exist). Of these, the internal ROM and external extension areas are located differently depending on mode settings as will be described later. (2) System space The 2 Gbytes from the address H’8000 0000 to the address H’FFFF FFFF comprise the system space. This space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and cannot be used by the user.

3-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The microcomputer is placed in one of the following modes depending on how CPU operation mode is set by MOD0 and MOD1 pins. The operation mode used for rewriting the internal flash memory is described separately in Section 6.5, “Programming the Internal Flash Memory.” Table 3.2.1 Operation Mode Settings MOD0 MOD1 MOD2 (Note 1) Operation mode (Note 2) VSS VSS VSS Single-chip mode VSS VCCE VSS External extension mode VCCE VSS VSS Processor mode (FP = VSS) VCCE VCCE VSS Reserved (use inhibited) -- VCCE Reserved (use inhibited) Note 1: Connect VCCE and VSS to the VCCE input power supply and ground, respectively. Note 2: For the operation mode used to rewrite the internal flash memory (FP = VCCE) which is not shown in the above table, see Section 6.5, “Programming the Internal Flash Memory.” The internal ROM and external extension areas are located differently depending on how operation mode is set. (All other areas in the address space are located the same way.) The diagram below shows how the internal ROM and external extension areas are mapped into the address space in each operation mode. (For flash rewrite mode, see Section 6.5, “Programming the Internal Flash Memory.”)

3-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Logical address Single chip mode External extension mode Processor mode Logical address (16 Mbytes) (16 Mbytes) (16M bytes) Ghost area in 16-Mbyte units User space System space

2 Gbytes

H'0000 0000 H'7FFF FFFF H'0000 0000 H'FFFF FFFF H'8000 0000 H'000F FFFF H'0010 0000 H'0008 0000 H'0020 0000 H'002F FFFF H'00FF FFFF H'0084 0000 H'0083 FFFF H'0080 A000 H'008F 9FFF H'0080 0000 H'007F FFFF H'0050 0000 H'004F FFFF H'0040 0000 H'003F FFFF H'0030 0000 H'0007 FFFF H'001F FFFF Internal ROM area (512 Kbytes) Notes: . CS0-CS2 areas: External extension areas of up to 2 Mbytes SFR area (16 Kbytes) Internal RAM area (24 Kbytes) Internal RAM area (24 Kbytes) Internal RAM area (24 Kbytes) H'0070 0000 H'006F FFFF H'0080 4000 H'0080 3FFF H'0082 0000 H'0081 FFFF H'00FE 0000 H'00FD FFFF Reserved area (512 Kbytes) Reserved area (512 Kbytes) Reserved area (88 Kbytes) Reserved area (88 Kbytes) Reserved area (88 Kbytes) . : Indicates Ghost area. This area must not be used during programming intentionally. Internal ROM area (512 Kbytes) SFR area (16 Kbytes) CS0 area (1 Mbytes) CS1 area (1 Mbytes) SFR area (16 Kbytes) CS0 area (1 Mbytes) CS1 area (1 Mbytes) Figure 3.2.1 Address Space of the M32176F4

3-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Logical address Single chip mode External extension mode Processor mode Logical address (16 Mbytes) (16 Mbytes) (16M bytes) Ghost area in 16-Mbyte units User space System space H'0000 0000 H'7FFF FFFF H'0000 0000 H'FFFF FFFF H'8000 0000 H'000F FFFF H'0010 0000 H'0006 0000 H'0020 0000 H'002F FFFF H'00FF FFFF H'0084 0000 H'0083 FFFF H'0080 A000 H'008F 9FFF H'0080 0000 H'007F FFFF H'0050 0000 H'004F FFFF H'0040 0000 H'003F FFFF H'0030 0000 H'0005 FFFF H'001F FFFF Internal ROM area (384 Kbytes) Notes: . CS0-CS2 areas: External extension areas of up to 2 Mbytes SFR area (16 Kbytes) Internal RAM area (24 Kbytes) Internal RAM area (24 Kbytes) Internal RAM area (24 Kbytes) H'0070 0000 H'006F FFFF H'0080 4000 H'0080 3FFF H'0082 0000 H'0081 FFFF H'00FE 0000 H'00FD FFFF Reserved area (640 Kbytes) Reserved area (640 Kbytes) Reserved area (88 Kbytes) Reserved area (88 Kbytes) Reserved area (88 Kbytes) . : Indicates Ghost area. This area must not be used during programming intentionally. Internal ROM area (384 Kbytes) SFR area (16 Kbytes) CS0 area (1 Mbytes) CS1 area (1 Mbytes) SFR area (16 Kbytes) CS0 area (1 Mbytes) CS1 area (1 Mbytes) Figure 3.2.2 Address Space of the M32176F3

3-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 3.2.3 Address Space of the M32176F2 Logical address Single chip mode External extension mode Processor mode Logical address (16 Mbytes) (16 Mbytes) (16M bytes) Ghost area in 16-Mbyte units User space System space H'0000 0000 H'7FFF FFFF H'0000 0000 H'FFFF FFFF H'8000 0000 H'000F FFFF H'0010 0000 H'0004 0000 H'0020 0000 H'002F FFFF H'00FF FFFF H'0084 0000 H'0083 FFFF H'0080 A000 H'008F 9FFF H'0080 0000 H'007F FFFF H'0050 0000 H'004F FFFF H'0040 0000 H'003F FFFF H'0030 0000 H'0003 FFFF H'001F FFFF Internal ROM area (256 Kbytes) Notes: . CS0-CS2 areas: External extension areas of up to 2 Mbytes SFR area (16 Kbytes) Internal RAM area (24 Kbytes) Internal RAM area (24 Kbytes) Internal RAM area (24 Kbytes) H'0070 0000 H'006F FFFF H'0080 4000 H'0080 3FFF H'0082 0000 H'0081 FFFF H'00FE 0000 H'00FD FFFF Reserved area (768 Kbytes) Reserved area (768 Kbytes) Reserved area (88 Kbytes) Reserved area (88 Kbytes) Reserved area (88 Kbytes) . : Indicates Ghost area. This area must not be used during programming intentionally. Internal ROM area (256 Kbytes) SFR area (16 Kbytes) CS0 area (1 Mbytes) CS1 area (1 Mbytes) SFR area (16 Kbytes) CS0 area (1 Mbytes) CS1 area (1 Mbytes)

3-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The 8-Mbyte area in the user space from the address H’0000 0000 to the address H’007F FFFF comprise the internal ROM and external extension areas. For the address mapping of these areas that differs with each operation mode, see Section 3.2, “Operation Modes.”

3.3.1 Internal ROM Area

The internal ROM is allocated to the addresses shown below. Located at the beginning of this area is the EIT vector entry (and the ICU vector table). Table 3.3.1 Internal ROM Allocation Address Type Name Size Allocation Address M32176F4 512 Kbytes H’0000 0000 to H’0007 FFFF M32176F3 384 kbytes H’0000 0000 to H’0005 FFFF M32176F2 256 Kbytes H’0000 0000 to H’0003 FFFF

3.3.2 External Extension Area

The external extension area is only available when external extension or processor mode is selected by opera- tion mode settings. When accessing the external extension area, the control signals necessary to access external devices are output. The CS0# and CS1# signals are output corresponding to the address mapping of the external extension area. The CS0# and CS1# signals are output for the CS0 and CS1 areas, respectively. Table 3.3.2 Address Mapping of the External Extension Area in Each Operation Mode Operation Mode Address Mapping of External Extension Area Single-chip mode None External extension mode H’0010 0000 to H’001F FFFF (CS0 area: 1 Mbyte) H’0020 0000 to H’002F FFFF (CS1 area: 1 Mbyte) (Note 1) Processor mode H’0000 0000 to H’000F FFFF (CS0 area: 1 Mbyte) (Note 2) H’0020 0000 to H’002F FFFF (CS1 area: 1 Mbyte) (Note 2) Note 1: During external extension mode, a ghost (1 Mbyte) of the CS1 area appears in an area of H'0030 0000 through H'003F FFFF. Note 2: During processor mode, a ghost (1 Mbyte) of the CS0 area appears in an area of H'0010 0000 through H'001F FFFF and a ghost (1 Mbyte) of the CS1 area appears in an area of H'0030 0000 through H'003F FFFF.

3-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The 8-Mbyte area from the address H’0080 0000 to the address H’00FF FFFF comprise the internal RAM and SFR (Special Function Register) areas. Of these, the space that the user can actually use is a 128-Kbyte area from the address H’0080 0000 to the address H’0081 FFFF. The other areas here are ghosts in 128-Kbyte units. (Do not use the ghost area intentionally during programming.)

3.4.1 Internal RAM Area

The internal RAM area is allocated to the addresses shown below. Table 3.4.1 Internal RAM Allocation Address Type Name Size Allocation Address M32176F4 24 Kbytes H’0080 4000 to H’0080 9FFF M32176F3 24 Kbytes H’0080 4000 to H’0080 9FFF M32176F2 24 Kbytes H’0080 4000 to H’0080 9FFF

3.4.2 SFR (Special Function Register) Area

The addresses H’0080 0000 to H’0080 3FFFF comprise the SFR (Special Function Register) area. Located in this area are the internal peripheral I/O registers. Figure 3.4.1 Internal RAM and SFR (Special Function Register) Areas SFR area (16 Kbytes) H'0080 0000 H'0080 3FFF H'0080 4000 H'0080 9FFF Internal RAM (24 Kbytes) Virtual flash emulation areas separated in 8- or 4-Kbyte units can be allocated here. For details, see Section 6.6.

3-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 3.4.2 Outline Mapping of the SFR Area H'0080 0000 H'0080 007E H'0080 0180 H'0080 0080 H'0080 00EE H'0080 0100 H'0080 0146 MJT(TOP) MJT(TIO) MJT(TMS) H'0080 0200 H'0080 0240 H'0080 0300 H'0080 03C0 H'0080 03E0 H'0080 03FE 0 7 8 150 7 8 15 Flash control H'0080 07E0 H'0080 07F2 H'0080 023E H'0080 02FE MJT(TML1) H'0080 0FE0 H'0080 0FFE H'0080 0400 DMAC H'0080 0478 CAN1 CAN0 H'0080 1000 H'0080 11FE H'0080 0700 H'0080 077F H'0080 03BE H'0080 03D8 MJT(TML0) H'0080 1400 H'0080 15FE H'0080 3FFE +1 address+0 address Interrupt Controller (ICU) A/D Converter Serial Interface Wait Controller MJT (common part) Multijunction timer (MJT) Input/output port Note: • The Real-time Debugger (RTD) is an independent module that is operated from the outside, and is transparent to the CPU. Multijunction timer (MJT) +1 address+0 address

3-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (1/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0000 Interrupt Vector Register 5-5 (IVECT) H'0080 0002 (Use inhibited area) H'0080 0004 Interrupt Request Mask Register (Use inhibited area) 5-6 (IMASK) H'0080 0006 SBI Control Register (Use inhibited area) 5-7 (SBICR) (Use inhibited area) H'0080 0060 CAN0 Transmit/Receive & Error Interrupt Control Register (Use inhibited area) 5-8 (ICAN0CR) H'0080 0062 (Use inhibited area) H'0080 0064 (Use inhibited area) H'0080 0066 (Use inhibited area) RTD Interrupt Control Register 5-8 (IRTDCR) H'0080 0068 SIO2, 3 Transmit/Receive Interrupt Control Register DMA5–9 Interrupt Control Register 5-8 (ISIO23CR) (IDMA59CR) H'0080 006A (Use inhibited area) H'0080 006C A/D0 Conversion Interrupt Control Register SIO0 Transmit Interrupt Control Register 5-8 (IAD0CCR) (ISIO0TXCR) H'0080 006E SIO0 Receive Interrupt Control Register SIO1 Transmit Interrupt Control Register 5-8 (ISIO0RXCR) (ISIO1TXCR) H'0080 0070 SIO1 Receive Interrupt Control Register DMA0–4 Interrupt Control Register 5-8 (ISIO1RXCR) (IDMA04CR) H'0080 0072 MJT Output Interrupt Control Register 0 MJT Output Interrupt Control Register 1 5-8 (IMJTOCR0) (IMJTOCR1) H'0080 0074 MJT Output Interrupt Control Register 2 MJT Output Interrupt Control Register 3 5-8 (IMJTOCR2) (IMJTOCR3) H'0080 0076 MJT Output Interrupt Control Register 4 MJT Output Interrupt Control Register 5 5-8 (IMJTOCR4) (IMJTOCR5) H'0080 0078 MJT Output Interrupt Control Register 6 MJT Output Interrupt Control Register 7 5-8 (IMJTOCR6) (IMJTOCR7) H'0080 007A (Use inhibited area) MJT Input Interrupt Control Register 1 5-8 (IMJTICR1) H'0080 007C MJT Input Interrupt Control Register 2 MJT Input Interrupt Control Register 3 5-8 (iIMJTICR2) (IMJTICR3) H'0080 007E MJT Input Interrupt Control Register 4 CAN1 Transmit/Receive & Error Interrupt Control Register 5-8 (IMJTICR4) (ICAN1CR) H'0080 0080 A/D0 Single Mode Register 0 A/D0 Single Mode Register 1 11-14 (AD0SIM0) (AD0SIM1) 11-16 H'0080 0082 (Use inhibited area) H'0080 0084 A/D0 Scan Mode Register 0 A/D0 Scan Mode Register 1 11-18 (AD0SCM0) (AD0SCM1) 11-20 H'0080 0086 A/D0 Disconnection Detection Assist Function Control RegisterA/D0 Conversion Speed Control Register 11-23 (AD0DDACR) (AD0CVSCR) 11-22 H'0080 0088 A/D0 Successive Approximation Register 11-27 (AD0SAR) H'0080 008A A/D0 Disconnection Detection Assist Method Select Register 11-24 (AD0DDASEL) H'0080 008C A/D0 Comparate Data Register 11-28 (AD0CMP) H'0080 008E (Use inhibited area) H'0080 0090 10-bit A/D0 Data Register 0 11-29 (AD0DT0) H'0080 0092 10-bit A/D0 Data Register 1 11-29 (AD0DT1) H'0080 0094 10-bit A/D0 Data Register 2 11-29 (AD0DT2) H'0080 0096 10-bit A/D0 Data Register 3 11-29 (AD0DT3) H'0080 0098 10-bit A/D0 Data Register 4 11-29 (AD0DT4) H'0080 009A 10-bit A/D0 Data Register 5 11-29 (AD0DT5)

3-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 009C 10-bit A/D0 Data Register 6 11-29 (AD0DT6) H'0080 009E 10-bit A/D0 Data Register 7 11-29 (AD0DT7) H'0080 00A0 10-bit A/D0 Data Register 8 11-29 (AD0DT8) H'0080 00A2 10-bit A/D0 Data Register 9 11-29 (AD0DT9) H'0080 00A4 10-bit A/D0 Data Register 10 11-29 (AD0DT10) H'0080 00A6 10-bit A/D0 Data Register 11 11-29 (AD0DT11) H'0080 00A8 10-bit A/D0 Data Register 12 11-29 (AD0DT12) H'0080 00AA 10-bit A/D0 Data Register 13 11-29 (AD0DT13) H'0080 00AC 10-bit A/D0 Data Register 14 11-29 (AD0DT14) H'0080 00AE 10-bit A/D0 Data Register 15 11-29 (AD0DT15) H'0080 00D0 (Use inhibited area) 8-bit A/D0 Data Register 0 11-30 (AD08DT0) H'0080 00D2 (Use inhibited area) 8-bit A/D0 Data Register 1 11-30 (AD08DT1) H'0080 00D4 (Use inhibited area) 8-bit A/D0 Data Register 2 11-30 (AD08DT2) H'0080 00D6 (Use inhibited area) 8-bit A/D0 Data Register 3 11-30 (AD08DT3) H'0080 00D8 (Use inhibited area) 8-bit A/D0 Data Register 4 11-30 (AD08DT4) H'0080 00DA (Use inhibited area) 8-bit A/D0 Data Register 5 11-30 (AD08DT5) H'0080 00DC (Use inhibited area) 8-bit A/D0 Data Register 6 11-30 (AD08DT6) H'0080 00DE (Use inhibited area) 8-bit A/D0 Data Register 7 11-30 (AD08DT7) H'0080 00E0 (Use inhibited area) 8-bit A/D0 Data Register 8 11-30 (AD08DT8) H'0080 00E2 (Use inhibited area) 8-bit A/D0 Data Register 9 11-30 (AD08DT9) H'0080 00E4 (Use inhibited area) 8-bit A/D0 Data Register 10 11-30 (AD08DT10) H'0080 00E6 (Use inhibited area) 8-bit A/D0 Data Register 11 11-30 (AD08DT11) H'0080 00E8 (Use inhibited area) 8-bit A/D0 Data Register 12 11-30 (AD08DT12) H'0080 00EA (Use inhibited area) 8-bit A/D0 Data Register 13 11-30 (AD08DT13) H'0080 00EC (Use inhibited area) 8-bit A/D0 Data Register 14 11-30 (AD08DT14) H'0080 00EE (Use inhibited area) 8-bit A/D0 Data Register 15 11-30 (AD08DT15) (Use inhibited area) H'0080 0100 SIO23 Interrupt Request Status Register SIO03 Interrupt Request Mask Register 12-9 (SI23STAT) (SI03MASK) 12-10 H'0080 0102 SIO03 Interrupt Request Source Select Register (Use inhibited area) 12-11 (SI03SEL) (Use inhibited area) H'0080 0110 SIO0 Transmit Control Register SIO0 Transmit/Receive Mode Register 12-13 (S0TCNT) (S0MOD) 12-14 H'0080 0112 SIO0 Transmit Buffer Register 12-17 (S0TXB) H'0080 0114 SIO0 Receive Buffer Register 12-18 (S0RXB) H'0080 0116 SIO0 Receive Control Register SIO0 Baud Rate Register 12-19 (S0RCNT) (S0BAUR) 12-21 SFR Area Register Map (2/22)

3-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0118 SIO0 Special Mode Register (Use inhibited area) 12-23 (S0SMOD) (Use inhibited area) H'0080 0120 SIO1 Transmit Control Register SIO1 Transmit/Receive Mode Register 12-13 (S1TCNT) (S1MOD) 12-14 H'0080 0122 SIO1 Transmit Buffer Register 12-17 (S1TXB) H'0080 0124 SIO1 Receive Buffer Register 12-18 (S1RXB) H'0080 0126 SIO1 Receive Control Register SIO1 Baud Rate Register 12-19 (S1RCNT) (S1BAUR) 12-21 H'0080 0128 SIO1 Special Mode Register (Use inhibited area) 12-23 (S1SMOD) (Use inhibited area) H'0080 0130 SIO2 Transmit Control Register SIO2 Transmit/Receive Mode Register 12-13 (S2TCNT) (S2MOD) 12-14 H'0080 0132 SIO2 Transmit Buffer Register 12-17 (S2TXB) H'0080 0134 SIO2 Receive Buffer Register 12-18 (S2RXB) H'0080 0136 SIO2 Receive Control Register SIO2 Baud Rate Register 12-19 (S2RCNT) (S2BAUR) 12-21 (Use inhibited area) H'0080 0140 SIO3 Transmit Control Register SIO3 Transmit/Receive Mode Register 12-13 (S3TCNT) (S3MOD) 12-14 H'0080 0142 SIO3 Transmit Buffer Register 12-17 (S3TXB) H'0080 0144 SIO3 Receive Buffer Register 12-18 (S3RXB) H'0080 0146 SIO3 Receive Control Register SIO3 Baud Rate Register 12-19 (S3RCNT) (S3BAUR) 12-21 (Use inhibited area) H'0080 0180 Wait Cycles Control Register (Use inhibited area) 16-4 (WTCCR) (Use inhibited area) H'0080 0200 (Use inhibited area) Clock Bus & Input Event Bus Control Register 10-13 (CKIEBCR) H'0080 0202 Prescaler Register 0 Prescaler Register 1 10-9 (PRS0) (PRS1) H'0080 0204 Prescaler Register 2 Output Event Bus Control Register 10-9 (PRS2) (OEBCR) 10-14 (Use inhibited area) H'0080 0210 TCLK Input Processing Control Register 10-17 (TCLKCR) H'0080 0212 TIN Input Processing Control Register 0 10-18 (TINCR0) H'0080 0214 (Use inhibited area) H'0080 0216 (Use inhibited area) H'0080 0218 TIN Input Processing Control Register 3 10-19 (TINCR3) H'0080 021A TIN Input Processing Control Register 4 10-19 (TINCR4) H'0080 021C (Use inhibited area) H'0080 021E (Use inhibited area) H'0080 0220 F/F Source Select Register 0 10-21 (FFS0) H'0080 0222 (Use inhibited area) F/F Source Select Register 1 10-22 (FFS1) H'0080 0224 F/F Protect Register 0 10-23 (FFP0) SFR Area Register Map (3/22)

3-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0226 F/F Data Register 0 10-24 (FFD0) H'0080 0228 (Use inhibited area) F/F Protect Register 1 10-23 (FFP1) H'0080 022A (Use inhibited area) F/F Data Register 1 10-24 (FFD1) (Use inhibited area) H'0080 0230 TOP Interrupt Control Register 0 TOP Interrupt Control Register 1 10-29 (TOPIR0) (TOPIR1) H'0080 0232 TOP Interrupt Control Register 2 TOP Interrupt Control Register 3 10-31 (TOPIR2) (TOPIR3) 10-32 H'0080 0234 TIO Interrupt Control Register 0 TIO Interrupt Control Register 1 10-33 (TIOIR0) (TIOIR1) 10-34 H'0080 0236 TIO Interrupt Control Register 2 TMS Interrupt Control Register 10-35 (TIOIR2) (TMSIR) 10-36 H'0080 0238 TIN Interrupt Control Register 0 TIN Interrupt Control Register 1 10-37 (TINIR0) (TINIR1) 10-38 H'0080 023A (Use inhibited area) H'0080 023C TIN Interrupt Control Register 4 TIN Interrupt Control Register 5 10-39 (TINIR4) (TINIR5) H'0080 023E TIN Interrupt Control Register 6 (Use inhibited area) 10-41 (TINIR6) H'0080 0240 TOP0 Counter 10-53 (TOP0CT) H'0080 0242 TOP0 Reload Register 10-54 (TOP0RL) H'0080 0244 (Use inhibited area) H'0080 0246 TOP0 Correction Register 10-55 (TOP0CC) (Use inhibited area) H'0080 0250 TOP1 Counter 10-53 (TOP1CT) H'0080 0252 TOP1 Reload Register 10-54 (TOP1RL) H'0080 0254 (Use inhibited area) H'0080 0256 TOP1 Correction Register 10-55 (TOP1CC) (Use inhibited area) H'0080 0260 TOP2 Counter 10-53 (TOP2CT) H'0080 0262 TOP2 Reload Register 10-54 (TOP2RL) H'0080 0264 (Use inhibited area) H'0080 0266 TOP2 Correction Register 10-55 (TOP2CC) (Use inhibited area) H'0080 0270 TOP3 Counter 10-53 (TOP3CT) H'0080 0272 TOP3 Reload Register 10-54 (TOP3RL) H'0080 0274 (Use inhibited area) H'0080 0276 TOP3 Correction Register 10-55 (TOP3CC) (Use inhibited area) H'0080 0280 TOP4 Counter 10-53 (TOP4CT) H'0080 0282 TOP4 Reload Register 10-54 (TOP4RL) H'0080 0284 (Use inhibited area) SFR Area Register Map (4/22)

3-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0286 TOP4 Correction Register 10-55 (TOP4CC) (Use inhibited area) H'0080 0290 TOP5 Counter 10-53 (TOP5CT) H'0080 0292 TOP5 Reload Register 10-54 (TOP5RL) H'0080 0294 (Use inhibited area) H'0080 0296 TOP5 Correction Register 10-55 (TOP5CC) H'0080 0298 (Use inhibited area) H'0080 029A TOP0–5 Control Register 0 10-49 (TOP05CR0) H'0080 029C (Use inhibited area) TOP0–5 Control Register 1 10-49 (TOP05CR1) H'0080 029E (Use inhibited area) H'0080 02A0 TOP6 Counter 10-53 (TOP6CT) H'0080 02A2 TOP6 Reload Register 10-54 (TOP6RL) H'0080 02A4 (Use inhibited area) H'0080 02A6 TOP6 Correction Register 10-55 (TOP6CC) H'0080 02A8 (Use inhibited area) H'0080 02AA TOP6, 7 Control Register 10-51 (TOP67CR) (Use inhibited area) H'0080 02B0 TOP7 Counter 10-53 (TOP7CT) H'0080 02B2 TOP7 Reload Register 10-54 (TOP7RL) H'0080 02B4 (Use inhibited area) H'0080 02B6 TOP7 Correction Register 10-55 (TOP7CC) (Use inhibited area) H'0080 02C0 TOP8 Counter 10-53 (TOP8CT) H'0080 02C2 TOP8 Reload Register 10-54 (TOP8RL) H'0080 02C4 (Use inhibited area) H'0080 02C6 TOP8 Correction Register 10-55 (TOP8CC) (Use inhibited area) H'0080 02D0 TOP9 Counter 10-53 (TOP9CT) H'0080 02D2 TOP9 Reload Register 10-54 (TOP9RL) H'0080 02D4 (Use inhibited area) H'0080 02D6 TOP9 Correction Register 10-55 (TOP9CC) (Use inhibited area) H'0080 02E0 TOP10 Counter 10-53 (TOP10CT) H'0080 02E2 TOP10 Reload Register 10-54 (TOP10RL) H'0080 02E4 (Use inhibited area) SFR Area Register Map (5/22)

3-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Address +0 address +1address See b0 b7 b8 b15 pages H'0080 02E6 TOP10 Correction Register 10-55 (TOP10CC) H'0080 02E8 (Use inhibited area) H'0080 02EA TOP8–10 Control Register 10-52 (TOP810CR) (Use inhibited area) H'0080 02FA TOP0-10 External Enable Permit Register 10-56 (TOPEEN) H'0080 02FC TOP0-10 Enable Protect Register 10-56 (TOPPRO) H'0080 02FE TOP0-10 Count Enable Register 10-57 (TOPCEN) H'0080 0300 TIO0 Counter 10-87 (TIO0CT) H'0080 0302 (Use inhibited area) H'0080 0304 TIO0 Reload 1 Register 10-89 (TIO0RL1) H'0080 0306 TIO0 Reload 0/ Measure Register 10-88 (TIO0RL0) (Use inhibited area) H'0080 0310 TIO1 Counter 10-87 (TIO1CT) H'0080 0312 (Use inhibited area) H'0080 0314 TIO1 Reload 1 Register 10-89 (TIO1RL1) H'0080 0316 TIO1 Reload 0/ Measure Register 10-88 (TIO1RL0) H'0080 0318 (Use inhibited area) H'0080 031A TIO0–3 Control Register 0 10-80 (TIO03CR0) H'0080 031C (Use inhibited area) TIO0–3 Control Register 1 10-81 (TIO03CR1) H'0080 031E (Use inhibited area) H'0080 0320 TIO2 Counter 10-87 (TIO2CT) H'0080 0322 (Use inhibited area) H'0080 0324 TIO2 Reload 1 Register 10-89 (TIO2RL1) H'0080 0326 TIO2 Reload 0/ Measure Register 10-88 (TIO2RL0) (Use inhibited area) H'0080 0330 TIO3 Counter 10-87 (TIO3CT) H'0080 0332 (Use inhibited area) H'0080 0334 TIO3 Reload 1 Register 10-89 (TIO3RL1) H'0080 0336 TIO3 Reload 0/ Measure Register 10-88 (TIO3RL0) (Use inhibited area) H'0080 0340 TIO4 Counter 10-87 (TIO4CT) H'0080 0342 (Use inhibited area) H'0080 0344 TIO4 Reload 1 Register 10-89 (TIO4RL1) H'0080 0346 TIO4 Reload 0/ Measure Register 10-88 (TIO4RL0) H'0080 0348 (Use inhibited area) SFR Area Register Map (6/22)

3-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 034A TIO4 Control Register TIO5 Control Register 10-82 (TIO4CR) (TIO5CR) 10-84 (Use inhibited area) H'0080 0350 TIO5 Counter 10-87 (TIO5CT) H'0080 0352 (Use inhibited area) H'0080 0354 TIO5 Reload 1 Register 10-89 (TIO5RL1) H'0080 0356 TIO5 Reload 0/ Measure Register 10-88 (TIO5RL0) (Use inhibited area) H'0080 0360 TIO6 Counter 10-87 (TIO6CT) H'0080 0362 (Use inhibited area) H'0080 0364 TIO6 Reload 1 Register 10-89 (TIO6RL1) H'0080 0366 TIO6 Reload 0/ Measure Register 10-88 (TIO6RL0) H'0080 0368 (Use inhibited area) H'0080 036A TIO6 Control Register TIO7 Control Register 10-85 (TIO6CR) (TIO7CR) 10-86 (Use inhibited area) H'0080 0370 TIO7 Counter 10-87 (TIO7CT) H'0080 0372 (Use inhibited area) H'0080 0374 TIO7 Reload 1 Register 10-89 (TIO7RL1) H'0080 0376 TIO7 Reload 0/ Measure Register 10-88 (TIO7RL0) (Use inhibited area) H'0080 0380 TIO8 Counter 10-87 (TIO8CT) H'0080 0382 (Use inhibited area) H'0080 0384 TIO8 Reload 1 Register 10-89 (TIO8RL1) H'0080 0386 TIO8 Reload 0/ Measure Register 10-88 (TIO8RL0) H'0080 0388 (Use inhibited area) H'0080 038A TIO8 Control Register TIO9 Control Register 10-86 (TIO8CR) (TIO9CR) 10-87 (Use inhibited area) H'0080 0390 TIO9 Counter 10-87 (TIO9CT) H'0080 0392 (Use inhibited area) H'0080 0394 TIO9 Reload 1 Register 10-89 (TIO9RL1) H'0080 0396 TIO9 Reload 0/ Measure Register 10-88 (TIO9RL0) (Use inhibited area) H'0080 03BC TIO0-9 Enable Protect Register 10-90 (TIOPRO) H'0080 03BE TIO0-9 Count Enable Register 10-91 (TIOCEN) H'0080 03C0 TMS0 Counter 10-109 (TMS0CT) H'0080 03C2 TMS0 Measure 3 Register 10-109 (TMS0MR3) SFR Area Register Map (7/22)

3-1732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (8/22) Address +0 address +1address See b0 b7 b8 b15 pages H'0080 03C4 TMS0 Measure 2 Register 10-109 (TMS0MR2) H'0080 03C6 TMS0 Measure 1 Register 10-109 (TMS0MR1) H'0080 03C8 TMS0 Measure 0 Register 10-109 (TMS0MR0) H'0080 03CA TMS0 Control Register TMS1 Control Register 10-108 (TMS0CR) (TMS1CR) (Use inhibited area) H'0080 03D0 TMS1 Counter 10-109 (TMS1CT) H'0080 03D2 TMS1 Measure 3 Register 10-109 (TMS1MR3) H'0080 03D4 TMS1 Measure 2 Register 10-109 (TMS1MR2) H'0080 03D6 TMS1 Measure 1 Register 10-109 (TMS1MR1) H'0080 03D8 TMS1 Measure 0 Register 10-109 (TMS1MR0) (Use inhibited area) H'0080 03E0 TML0 Counter (Upper) 10-114 (TML0CTH) H'0080 03E2 TML0 Counter (Lower) 10-114 (TML0CTL) (Use inhibited area) H'0080 03EA (Use inhibited area) TML0 Control Register 10-113 (TML0CR) (Use inhibited area) H'0080 03F0 TML0 Measure 3 Register (Upper) 10-115 (TML0MR3H) H'0080 03F2 TML0 Measure 3 Register (Lower) 10-115 (TML0MR3L) H'0080 03F4 TML0 Measure 2 Register (Upper) 10-115 (TML0MR2H) H'0080 03F6 TML0 Measure 2 Register (Lower) 10-115 (TML0MR2L) H'0080 03F8 TML0 Measure 1 Register (Upper) 10-115 (TML0MR1H) H'0080 03FA TML0 Measure 1 Register (Lower) 10-115 (TML0MR1L) H'0080 03FC TML0 Measure 0 Register (Upper) 10-115 (TML0MR0H) H'0080 03FE TML0 Measure 0 Register (Lower) 10-115 (TML0MR0L) H'0080 0400 DMA0–4 Interrupt Request Status Register DMA0–4 Interrupt Request Mask Register 9-18 (DM04ITST) (DM04ITMK) 9-19 (Use inhibited area) H'0080 0408 DMA5–9 Interrupt Request Status Register DMA5–9 Interrupt Request Mask Register 9-18 (DM59ITST) (DM59ITMK) 9-19 (Use inhibited area) H'0080 0410 DMA0 Channel Control Register DMA0 Transfer Count Register 9-6 (DM0CNT) (DM0TCT) 9-15 H'0080 0412 DMA0 Source Address Register 9-13 (DM0SA) H'0080 0414 DMA0 Destination Address Register 9-14 (DM0DA) H'0080 0416 (Use inhibited area) H'0080 0418 DMA5 Channel Control Register DMA5 Transfer Count Register 9-8 (DM5CNT) (DM5TCT) 9-15 H'0080 041A DMA5 Source Address Register 9-13 (DM5SA) H'0080 041C DMA5 Destination Address Register 9-14 (DM5DA)

3-1832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (9/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 041E (Use inhibited area) H'0080 0420 DMA1 Channel Control Register DMA1 Transfer Count Register 9-6 (DM1CNT) (DM1TCT) 9-15 H'0080 0422 DMA1 Source Address Register 9-13 (DM1SA) H'0080 0424 DMA1 Destination Address Register 9-14 (DM1DA) H'0080 0426 (Use inhibited area) H'0080 0428 DMA6 Channel Control Register DMA6 Transfer Count Register 9-9 (DM6CNT) (DM6TCT) 9-15 H'0080 042A DMA6 Source Address Register 9-13 (DM6SA) H'0080 042C DMA6 Destination Address Register 9-14 (DM6DA) H'0080 042E (Use inhibited area) H'0080 0430 DMA2 Channel Control Register DMA2 Transfer Count Register 9-7 (DM2CNT) (DM2TCT) 9-15 H'0080 0432 DMA2 Source Address Register 9-13 (DM2SA) H'0080 0434 DMA2 Destination Address Register 9-14 (DM2DA) H'0080 0436 (Use inhibited area) H'0080 0438 DMA7 Channel Control Register DMA7 Transfer Count Register 9-9 (DM7CNT) (DM7TCT) 9-15 H'0080 043A DMA7 Source Address Register 9-13 (DM7SA) H'0080 043C DMA7 Destination Address Register 9-14 (DM7DA) H'0080 043E (Use inhibited area) H'0080 0440 DMA3 Channel Control Register DMA3 Transfer Count Register 9-7 (DM3CNT) (DM3TCT) 9-15 H'0080 0442 DMA3 Source Address Register 9-13 (DM3SA) H'0080 0444 DMA3 Destination Address Register 9-14 (DM3DA) H'0080 0446 (Use inhibited area) H'0080 0448 DMA8 Channel Control Register DMA8 Transfer Count Register 9-10 (DM8CNT) (DM8TCT) 9-15 H'0080 044A DMA8 Source Address Register 9-13 (DM8SA) H'0080 044C DMA8 Destination Address Register 9-14 (DM8DA) H'0080 044E (Use inhibited area) H'0080 0450 DMA4 Channel Control Register DMA4 Transfer Count Register 9-8 (DM4CNT) (DM4TCT) 9-15 H'0080 0452 DMA4 Source Address Register 9-13 (DM4SA) H'0080 0454 DMA4 Destination Address Register 9-14 (DM4DA) H'0080 0456 (Use inhibited area) H'0080 0458 DMA9 Channel Control Register DMA9 Transfer Count Register 9-10 (DM9CNT) (DM9TCT) 9-15 H'0080 045A DMA9 Source Address Register 9-13 (DM9SA) H'0080 045C DMA9 Destination Address Register 9-14 (DM9DA) H'0080 045E (Use inhibited area) H'0080 0460 DMA0 Software Request Generation Register 9-12 (DM0SRI) H'0080 0462 DMA1 Software Request Generation Register 9-12 (DM1SRI)

3-1932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (10/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0464 DMA2 Software Request Generation Register 9-12 (DM2SRI) H'0080 0466 DMA3 Software Request Generation Register 9-12 (DM3SRI) H'0080 0468 DMA4 Software Request Generation Register 9-12 (DM4SRI) (Use inhibited area) H'0080 0470 DMA5 Software Request Generation Register 9-12 (DM5SRI) H'0080 0472 DMA6 Software Request Generation Register 9-12 (DM6SRI) H'0080 0474 DMA7 Software Request Generation Register 9-12 (DM7SRI) H'0080 0476 DMA8 Software Request Generation Register 9-12 (DM8SRI) H'0080 0478 DMA9 Software Request Generation Register 9-12 (DM9SRI) (Use inhibited area) H'0080 0600 Dummy access area (Note 1) Dummy access area (Note 1) 3-31 H'0080 0602 Dummy access area (Note 1) Dummy access area (Note 1) 3-31 (Use inhibited area) H'0080 0700 P0 Data Register P1 Data Register 8-7 (P0DATA) (P1DATA) H'0080 0702 P2 Data Register P3 Data Register 8-7 (P2DATA) (P3DATA) H'0080 0704 P4 Data Register (Use inhibited area) 8-7 (P4DATA) H'0080 0706 P6 Data Register P7 Data Register 8-7 (P6DATA) (P7DATA) H'0080 0708 P8 Data Register P9 Data Register 8-7 (P8DATA) (P9DATA) H'0080 070A P10 Data Register P11 Data Register 8-7 (P10DATA) (P11DATA) H'0080 070C P12 Data Register P13 Data Register 8-7 (P12DATA) (P13DATA) H'0080 070E (Use inhibited area) P15 Data Register 8-7 (P15DATA) H'0080 0710 (Use inhibited area) P17 Data Register 8-7 (P17DATA) H'0080 0712 (Use inhibited area) (Use inhibited area) H'0080 0714 (Use inhibited area) (Use inhibited area) H'0080 0716 P22 Data Register (Use inhibited area) 8-7 (P22DATA) (Use inhibited area) H'0080 0720 P0 Direction Register P1 Direction Register 8-8 (P0DIR) (P1DIR) H'0080 0722 P2 Direction Register P3 Direction Register 8-8 (P2DIR) (P3DIR) H'0080 0724 P4 Direction Register (Use inhibited area) 8-8 (P4DIR) H'0080 0726 P6 Direction Register P7 Direction Register 8-8 (P6DIR) (P7DIR) H'0080 0728 P8 Direction Register P9 Direction Register 8-8 (P8DIR) (P9DIR) H'0080 072A P10 Direction Register P11 Direction Register 8-8 (P10DIR) (P11DIR) H'0080 072C P12 Direction Register P13 Direction Register 8-8 (P12DIR) (P13DIR) H'0080 072E (Use inhibited area) P15 Direction Register 8-8 (P15DIR)

3-2032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0730 (Use inhibited area) P17 Direction Register 8-8 (P17DIR) H'0080 0732 (Use inhibited area) (Use inhibited area) H'0080 0734 (Use inhibited area) (Use inhibited area) H'0080 0736 P22 Direction Register (Use inhibited area) 8-8 (P22DIR) (Use inhibited area) H'0080 0744 (Use inhibited area) Port Input Special Function Control Register 8-15 (PICNT) 18-3 H'0080 0746 (Use inhibited area) P7 Operation Mode Register 8-9, 15-4 (P7MOD) 18-7 H'0080 0748 P8 Operation Mode Register P9 Operation Mode Register 8-9 (P8MOD) (P9MOD) 8-10 H'0080 074A P10 Operation Mode Register P11 Operation Mode Register 8-10 (P10MOD) (P11MOD) 8-11 H'0080 074C P12 Operation Mode Register P13 Operation Mode Register 8-11 (P12MOD) (P13MOD) 8-12 H'0080 074E (Use inhibited area) P15 Operation Mode Register 8-12 (P15MOD) H'0080 0750 (Use inhibited area) P17 Operation Mode Register 8-13 (P17MOD) H'0080 0752 (Use inhibited area) (Use inhibited area) H'0080 0754 (Use inhibited area) (Use inhibited area) H'0080 0756 P22 Operation Mode Register (Use inhibited area) 8-13 (P22MOD) (Use inhibited area) H'0080 0760 Port Group 0, 1 Input Level Setting Register Port Group 3 Input Level Setting Register 8-19 (PG01LEV) (PG3LEV) H'0080 0762 Port Group 4, 5 Input Level Setting Register Port Group 6, 7 Input Level Setting Register 8-19 (PG45LEV) (PG67LEV) H'0080 0764 Port Group 8 Input Level Setting Register (Use inhibited area) 8-19 (PG8LEV) H'0080 0766 (Use inhibited area) P7 Peripheral Function Select Register 8-14 (P7SMOD) (Use inhibited area) H'0080 077A (Use inhibited area) RTD Write Function Disable Register 14-3 (WRRDIS) (Use inhibited area) H'0080 077E (Use inhibited area) Bus Mode Control Register 15-5 (BUSMODC) (Use inhibited area) H'0080 0786 Clock Control Register (Use inhibited area) 18-5 (CLKCR) (Use inhibited area) H'0080 07E0 Flash Mode Register Flash Status Register 6-7 (FMOD) (FSTAT) 6-8 H'0080 07E2 Flash Control Register 1 Flash Control Register 2 6-9 (FCNT1) (FCNT2) 6-10 H'0080 07E4 Flash Control Register 3 Flash Control Register 4 6-11 (FCNT3) (FCNT4) 6-13 H'0080 07E6 (Use inhibited area) H'0080 07E8 Virtual Flash L Bank Register 0 6-15 (FELBANK0) H'0080 07EA Virtual Flash L Bank Register 1 6-15 (FELBANK1) (Use inhibited area) H'0080 07F0 Virtual Flash S Bank Register 0 6-16 (FESBANK0) SFR Area Register Map (11/22)

3-2132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (12/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 07F2 Virtual Flash S Bank Register 1 6-16 (FESBANK1) (Use inhibited area) H'0080 0FE0 TML1 Counter (Upper) 10-114 (TML1CTH) H'0080 0FE2 TML1 Counter (Lower) 10-114 (TML1CTL) (Use inhibited area) H'0080 0FEA (Use inhibited area) TML1 Control Register 10-113 (TML1CR) (Use inhibited area) H'0080 0FF0 TML1 Measure 3 Register (Upper) 10-116 (TML1MR3H) H'0080 0FF2 TML1 Measure 3 Register (Lower) 10-116 (TML1MR3L) H'0080 0FF4 TML1 Measure 2 Register (Upper) 10-116 (TML1MR2H) H'0080 0FF6 TML1 Measure 2 Register (Lower) 10-116 (TML1MR2L) H'0080 0FF8 TML1 Measure 1 Register (Upper) 10-116 (TML1MR1H) H'0080 0FFA TML1 Measure 1 Register (Lower) 10-116 (TML1MR1L) H'0080 0FFC TML1 Measure 0 Register (Upper) 10-116 (TML1MR0H) H'0080 0FFE TML1 Measure 0 Register (Lower) 10-116 (TML1MR0L) (Use inhibited area) H'0080 1000 CAN0 Control Register 13-15 (CAN0CNT) H'0080 1002 CAN0 Status Register 13-18 (CAN0STAT) H'0080 1004 CAN0 Extended ID Register 13-21 (CAN0EXTID) H'0080 1006 CAN0 Configuration Register 13-22 (CAN0CONF) H'0080 1008 CAN0 Timestamp Count Register 13-24 (CAN0TSTMP) H'0080 100A CAN0 Receive Error Count Register CAN0 Transmit Error Count Register 13-25 (CAN0REC) (CAN0TEC) H'0080 100C CAN0 Slot Interrupt Request Status Register 13-29 (CAN0SLIST) H'0080 100E (Use inhibited area) H'0080 1010 CAN0 Slot Interrupt Request Mask Register 13-30 (CAN0SLIMK) H'0080 1012 (Use inhibited area) H'0080 1014 CAN0 Error Interrupt Request Status Register CAN0 Error Interrupt Request Mask Register 13-31 (CAN0ERIST) (CAN0ERIMK) 13-32 H'0080 1016 CAN0 Baud Rate Prescaler CAN0 Cause of Error Register 13-26 (CAN0BRP) (CAN0EF) 13-45 H'0080 1018 CAN0 Mode Register CAN0 DMA Transfer Request Select Register 13-47 (CAN0MOD) (CAN0DMARQ) 13-48 (Use inhibited area) H'0080 1028 CAN0 Global Mask Register Standard ID 0 CAN0 Global Mask Register Standard ID 1 13-49 (C0GMSKS0) (C0GMSKS1) H'0080 102A CAN0 Global Mask Register Extended ID 0 CAN0 Global Mask Register Extended ID 1 13-50 (C0GMSKE0) (C0GMSKE1) H'0080 102C CAN0 Global Mask Register Extended ID 2 (Use inhibited area) 13-51 (C0GMSKE2) H'0080 102E (Use inhibited area) H'0080 1030 CAN0 Local Mask Register A Standard ID 0 CAN0 Local Mask Register A Standard ID 1 13-49 (C0LMSKAS0) (C0LMSKAS1)

3-2232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (13/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 1032 CAN0 Local Mask Register A Extended ID 0 CAN0 Local Mask Register A Extended ID 1 13-50 (C0LMSKAE0) (C0LMSKAE1) H'0080 1034 CAN0 Local Mask Register A Extended ID 2 (Use inhibited area) 13-51 (C0LMSKAE2) H'0080 1036 (Use inhibited area) H'0080 1038 CAN0 Local Mask Register B Standard ID 0 CAN0 Local Mask Register B Standard ID 1 13-49 (C0LMSKBS0) (C0LMSKBS1) H'0080 103A CAN0 Local Mask Register B Extended ID 0 CAN0 Local Mask Register B Extended ID 1 13-50 (C0LMSKBE0) (C0LMSKBE1) H'0080 103C CAN0 Local Mask Register B Extended ID 2 (Use inhibited area) 13-51 (C0LMSKBE2) H'0080 103E (Use inhibited area) H'0080 1040 CAN0 Single Shot Mode Control Register 13-53 (CAN0SSMODE) H'0080 1042 (Use inhibited area) H'0080 1044 CAN0 Single-Shot Interrupt Request Status Register 13-33 (CAN0SSIST) H'0080 1046 (Use inhibited area) H'0080 1048 CAN0 Single-Shot Interrupt Request Mask Register 13-34 (CAN0SSIMK) (Use inhibited area) H'0080 1050 CAN0 Message Slot 0 Control Register CAN0 Message Slot 1 Control Register 13-54 (C0MSL0CNT) (C0MSL1CNT) H'0080 1052 CAN0 Message Slot 2 Control Register CAN0 Message Slot 3 Control Register 13-54 (C0MSL2CNT) (C0MSL3CNT) H'0080 1054 CAN0 Message Slot 4 Control Register CAN0 Message Slot 5 Control Register 13-54 (C0MSL4CNT) (C0MSL5CNT) H'0080 1056 CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register 13-54 (C0MSL6CNT) (C0MSL7CNT) H'0080 1058 CAN0 Message Slot 8 Control Register CAN0 Message Slot 9 Control Register 13-54 (C0MSL8CNT) (C0MSL9CNT) H'0080 105A CAN0 Message Slot 10 Control Register CAN0 Message Slot 11 Control Register 13-54 (C0MSL10CNT) (C0MSL11CNT) H'0080 105C CAN0 Message Slot 12 Control Register CAN0 Message Slot 13 Control Register 13-54 (C0MSL12CNT) (C0MSL13CNT) H'0080 105E CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register 13-54 (C0MSL14CNT) (C0MSL15CNT) (Use inhibited area) H'0080 1100 CAN0 Message Slot 0 Standard ID 0 CAN0 Message Slot 0 Standard ID 1 13-58 (C0MSL0SID0) (C0MSL0SID1) 13-59 H'0080 1102 CAN0 Message Slot 0 Extended ID 0 CAN0 Message Slot 0 Extended ID 1 13-60 (C0MSL0EID0) (C0MSL0EID1) 13-61 H'0080 1104 CAN0 Message Slot 0 Extended ID 2 CAN0 Message Slot 0 Data Length Register 13-62 (C0MSL0EID2) (C0MSL0DLC) 13-63 H'0080 1106 CAN0 Message Slot 0 Data 0 CAN0 Message Slot 0 Data 1 13-64 (C0MSL0DT0) (C0MSL0DT1) 13-65 H'0080 1108 CAN0 Message Slot 0 Data 2 CAN0 Message Slot 0 Data 3 13-66 (C0MSL0DT2) (C0MSL0DT3) 13-67 H'0080 110A CAN0 Message Slot 0 Data 4 CAN0 Message Slot 0 Data 5 13-68 (C0MSL0DT4) (C0MSL0DT5) 13-69 H'0080 110C CAN0 Message Slot 0 Data 6 CAN0 Message Slot 0 Data 7 13-70 (C0MSL0DT6) (C0MSL0DT7) 13-71 H'0080 110E CAN0 Message Slot 0 Timestamp 13-72 (C0MSL0TSP) H'0080 1110 CAN0 Message Slot 1 Standard ID 0 CAN0 Message Slot 1 Standard ID 1 13-58 (C0MSL1SID0) (C0MSL1SID1) 13-59 H'0080 1112 CAN0 Message Slot 1 Extended ID 0 CAN0 Message Slot 1 Extended ID 1 13-60 (C0MSL1EID0) (C0MSL1EID1) 13-61 H'0080 1114 CAN0 Message Slot 1 Extended ID 2 CAN0 Message Slot 1 Data Length Register 13-62 (C0MSL1EID2) (C0MSL1DLC) 13-63 H'0080 1116 CAN0 Message Slot 1 Data 0 CAN0 Message Slot 1 Data 1 13-64 (C0MSL1DT0) (C0MSL1DT1) 13-65 H'0080 1118 CAN0 Message Slot 1 Data 2 CAN0 Message Slot 1 Data 3 13-66 (C0MSL1DT2) (C0MSL1DT3) 13-67

3-2332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (14/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 111A CAN0 Message Slot 1 Data 4 CAN0 Message Slot 1 Data 5 13-68 (C0MSL1DT4) (C0MSL1DT5) 13-69 H'0080 111C CAN0 Message Slot 1 Data 6 CAN0 Message Slot 1 Data 7 13-70 (C0MSL1DT6) (C0MSL1DT7) 13-71 H'0080 111E CAN0 Message Slot 1 Timestamp 13-72 (C0MSL1TSP) H'0080 1120 CAN0 Message Slot 2 Standard ID 0 CAN0 Message Slot 2 Standard ID 1 13-58 (C0MSL2SID0) (C0MSL2SID1) 13-59 H'0080 1122 CAN0 Message Slot 2 Extended ID 0 CAN0 Message Slot 2 Extended ID 1 13-60 (C0MSL2EID0) (C0MSL2EID1) 13-61 H'0080 1124 CAN0 Message Slot 2 Extended ID 2 CAN0 Message Slot 2 Data Length Register 13-62 (C0MSL2EID2) (C0MSL2DLC) 13-63 H'0080 1126 CAN0 Message Slot 2 Data 0 CAN0 Message Slot 2 Data 1 13-64 (C0MSL2DT0) (C0MSL2DT1) 13-65 H'0080 1128 CAN0 Message Slot 2 Data 2 CAN0 Message Slot 2 Data 3 13-66 (C0MSL2DT2) (C0MSL2DT3) 13-67 H'0080 112A CAN0 Message Slot 2 Data 4 CAN0 Message Slot 2 Data 5 13-68 (C0MSL2DT4) (C0MSL2DT5) 13-69 H'0080 112C CAN0 Message Slot 2 Data 6 CAN0 Message Slot 2 Data 7 13-70 (C0MSL2DT6) (C0MSL2DT7) 13-71 H'0080 112E CAN0 Message Slot 2 Timestamp 13-72 (C0MSL2TSP) H'0080 1130 CAN0 Message Slot 3 Standard ID 0 CAN0 Message Slot 3 Standard ID 1 13-58 (C0MSL3SID0) (C0MSL3SID1) 13-59 H'0080 1132 CAN0 Message Slot 3 Extended ID 0 CAN0 Message Slot 3 Extended ID 1 13-60 (C0MSL3EID0) (C0MSL3EID1) 13-61 H'0080 1134 CAN0 Message Slot 3 Extended ID 2 CAN0 Message Slot 3 Data Length Register 13-62 (C0MSL3EID2) (C0MSL3DLC) 13-63 H'0080 1136 CAN0 Message Slot 3 Data 0 CAN0 Message Slot 3 Data 1 13-64 (C0MSL3DT0) (C0MSL3DT1) 13-65 H'0080 1138 CAN0 Message Slot 3 Data 2 CAN0 Message Slot 3 Data 3 13-66 (C0MSL3DT2) (C0MSL3DT3) 13-67 H'0080 113A CAN0 Message Slot 3 Data 4 CAN0 Message Slot 3 Data 5 13-68 (C0MSL3DT4) (C0MSL3DT5) 13-69 H'0080 113C CAN0 Message Slot 3 Data 6 CAN0 Message Slot 3 Data 7 13-70 (C0MSL3DT6) (C0MSL3DT7) 13-71 H'0080 113E CAN0 Message Slot 3 Timestamp 13-72 (C0MSL3TSP) H'0080 1140 CAN0 Message Slot 4 Standard ID 0 CAN0 Message Slot 4 Standard ID 1 13-58 (C0MSL4SID0) (C0MSL4SID1) 13-59 H'0080 1142 CAN0 Message Slot 4 Extended ID 0 CAN0 Message Slot 4 Extended ID 1 13-60 (C0MSL4EID0) (C0MSL4EID1) 13-61 H'0080 1144 CAN0 Message Slot 4 Extended ID 2 CAN0 Message Slot 4 Data Length Register 13-62 (C0MSL4EID2) (C0MSL4DLC) 13-63 H'0080 1146 CAN0 Message Slot 4 Data 0 CAN0 Message Slot 4 Data 1 13-64 (C0MSL4DT0) (C0MSL4DT1) 13-65 H'0080 1148 CAN0 Message Slot 4 Data 2 CAN0 Message Slot 4 Data 3 13-66 (C0MSL4DT2) (C0MSL4DT3) 13-67 H'0080 114A CAN0 Message Slot 4 Data 4 CAN0 Message Slot 4 Data 5 13-68 (C0MSL4DT4) (C0MSL4DT5) 13-69 H'0080 114C CAN0 Message Slot 4 Data 6 CAN0 Message Slot 4 Data 7 13-70 (C0MSL4DT6) (C0MSL4DT7) 13-71 H'0080 114E CAN0 Message Slot 4 Timestamp 13-72 (C0MSL4TSP) H'0080 1150 CAN0 Message Slot 5 Standard ID 0 CAN0 Message Slot 5 Standard ID 1 13-58 (C0MSL5SID0) (C0MSL5SID1) 13-59 H'0080 1152 CAN0 Message Slot 5 Extended ID 0 CAN0 Message Slot 5 Extended ID 1 13-60 (C0MSL5EID0) (C0MSL5EID1) 13-61 H'0080 1154 CAN0 Message Slot 5 Extended ID 2 CAN0 Message Slot 5 Data Length Register 13-62 (C0MSL5EID2) (C0MSL5DLC) 13-63 H'0080 1156 CAN0 Message Slot 5 Data 0 CAN0 Message Slot 5 Data 1 13-64 (C0MSL5DT0) (C0MSL5DT1) 13-65 H'0080 1158 CAN0 Message Slot 5 Data 2 CAN0 Message Slot 5 Data 3 13-66 (C0MSL5DT2) (C0MSL5DT3) 13-67 H'0080 115A CAN0 Message Slot 5 Data 4 CAN0 Message Slot 5 Data 5 13-68 (C0MSL5DT4) (C0MSL5DT5) 13-69 H'0080 115C CAN0 Message Slot 5 Data 6 CAN0 Message Slot 5 Data 7 13-70 (C0MSL5DT6) (C0MSL5DT7) 13-71 H'0080 115E CAN0 Message Slot 5 Timestamp 13-72 (C0MSL5TSP)

3-2432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (15/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 1160 CAN0 Message Slot 6 Standard ID 0 CAN0 Message Slot 6 Standard ID 1 13-58 (C0MSL6SID0) (C0MSL6SID1) 13-59 H'0080 1162 CAN0 Message Slot 6 Extended ID 0 CAN0 Message Slot 6 Extended ID 1 13-60 (C0MSL6EID0) (C0MSL6EID1) 13-61 H'0080 1164 CAN0 Message Slot 6 Extended ID 2 CAN0 Message Slot 6 Data Length Register 13-62 (C0MSL6EID2) (C0MSL6DLC) 13-63 H'0080 1166 CAN0 Message Slot 6 Data 0 CAN0 Message Slot 6 Data 1 13-64 (C0MSL6DT0) (C0MSL6DT1) 13-65 H'0080 1168 CAN0 Message Slot 6 Data 2 CAN0 Message Slot 6 Data 3 13-66 (C0MSL6DT2) (C0MSL6DT3) 13-67 H'0080 116A CAN0 Message Slot 6 Data 4 CAN0 Message Slot 6 Data 5 13-68 (C0MSL6DT4) (C0MSL6DT5) 13-69 H'0080 116C CAN0 Message Slot 6 Data 6 CAN0 Message Slot 6 Data 7 13-70 (C0MSL6DT6) (C0MSL6DT7) 13-71 H'0080 116E CAN0 Message Slot 6 Timestamp 13-72 (C0MSL6TSP) H'0080 1170 CAN0 Message Slot 7 Standard ID 0 CAN0 Message Slot 7 Standard ID 1 13-58 (C0MSL7SID0) (C0MSL7SID1) 13-59 H'0080 1172 CAN0 Message Slot 7 Extended ID 0 CAN0 Message Slot 7 Extended ID 1 13-60 (C0MSL7EID0) (C0MSL7EID1) 13-61 H'0080 1174 CAN0 Message Slot 7 Extended ID 2 CAN0 Message Slot 7 Data Length Register 13-62 (C0MSL7EID2) (C0MSL7DLC) 13-63 H'0080 1176 CAN0 Message Slot 7 Data 0 CAN0 Message Slot 7 Data 1 13-64 (C0MSL7DT0) (C0MSL7DT1) 13-65 H'0080 1178 CAN0 Message Slot 7 Data 2 CAN0 Message Slot 7 Data 3 13-66 (C0MSL7DT2) (C0MSL7DT3) 13-67 H'0080 117A CAN0 Message Slot 7 Data 4 CAN0 Message Slot 7 Data 5 13-68 (C0MSL7DT4) (C0MSL7DT5) 13-69 H'0080 117C CAN0 Message Slot 7 Data 6 CAN0 Message Slot 7 Data 7 13-70 (C0MSL7DT6) (C0MSL7DT7) 13-71 H'0080 117E CAN0 Message Slot 7 Timestamp 13-72 (C0MSL7TSP) H'0080 1180 CAN0 Message Slot 8 Standard ID 0 CAN0 Message Slot 8 Standard ID 1 13-58 (C0MSL8SID0) (C0MSL8SID1) 13-59 H'0080 1182 CAN0 Message Slot 8 Extended ID 0 CAN0 Message Slot 8 Extended ID 1 13-60 (C0MSL8EID0) (C0MSL8EID1) 13-61 H'0080 1184 CAN0 Message Slot 8 Extended ID 2 CAN0 Message Slot 8 Data Length Register 13-62 (C0MSL8EID2) (C0MSL8DLC) 13-63 H'0080 1186 CAN0 Message Slot 8 Data 0 CAN0 Message Slot 8 Data 1 13-64 (C0MSL8DT0) (C0MSL8DT1) 13-65 H'0080 1188 CAN0 Message Slot 8 Data 2 CAN0 Message Slot 8 Data 3 13-66 (C0MSL8DT2) (C0MSL8DT3) 13-67 H'0080 118A CAN0 Message Slot 8 Data 4 CAN0 Message Slot 8 Data 5 13-68 (C0MSL8DT4) (C0MSL8DT5) 13-69 H'0080 118C CAN0 Message Slot 8 Data 6 CAN0 Message Slot 8 Data 7 13-70 (C0MSL8DT6) (C0MSL8DT7) 13-71 H'0080 118E CAN0 Message Slot 8 Timestamp 13-72 (C0MSL8TSP) H'0080 1190 CAN0 Message Slot 9 Standard ID 0 CAN0 Message Slot 9 Standard ID 1 13-58 (C0MSL9SID0) (C0MSL9SID1) 13-59 H'0080 1192 CAN0 Message Slot 9 Extended ID 0 CAN0 Message Slot 9 Extended ID 1 13-60 (C0MSL9EID0) (C0MSL9EID1) 13-61 H'0080 1194 CAN0 Message Slot 9 Extended ID 2 CAN0 Message Slot 9 Data Length Register 13-62 (C0MSL9EID2) (C0MSL9DLC) 13-63 H'0080 1196 CAN0 Message Slot 9 Data 0 CAN0 Message Slot 9 Data 1 13-64 (C0MSL9DT0) (C0MSL9DT1) 13-65 H'0080 1198 CAN0 Message Slot 9 Data 2 CAN0 Message Slot 9 Data 3 13-66 (C0MSL9DT2) (C0MSL9DT3) 13-67 H'0080 119A CAN0 Message Slot 9 Data 4 CAN0 Message Slot 9 Data 5 13-68 (C0MSL9DT4) (C0MSL9DT5) 13-69 H'0080 119C CAN0 Message Slot 9 Data 6 CAN0 Message Slot 9 Data 7 13-70 (C0MSL9DT6) (C0MSL9DT7) 13-71 H'0080 119E CAN0 Message Slot 9 Timestamp 13-72 (C0MSL9TSP)

3-2532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (16/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 11A0 CAN0 Message Slot 10 Standard ID 0 CAN0 Message Slot 10 Standard ID 1 13-58 (C0MSL10SID0) (C0MSL10SID1) 13-59 H'0080 11A2 CAN0 Message Slot 10 Extended ID 0 CAN0 Message Slot 10 Extended ID 1 13-60 (C0MSL10EID0) (C0MSL10EID1) 13-61 H'0080 11A4 CAN0 Message Slot 10 Extended ID 2 CAN0 Message Slot 10 Data Length Register 13-62 (C0MSL10EID2) (C0MSL10DLC) 13-63 H'0080 11A6 CAN0 Message Slot 10 Data 0 CAN0 Message Slot 10 Data 1 13-64 (C0MSL10DT0) (C0MSL10DT1) 13-65 H'0080 11A8 CAN0 Message Slot 10 Data 2 CAN0 Message Slot 10 Data 3 13-66 (C0MSL10DT2) (C0MSL10DT3) 13-67 H'0080 11AA CAN0 Message Slot 10 Data 4 CAN0 Message Slot 10 Data 5 13-68 (C0MSL10DT4) (C0MSL10DT5) 13-69 H'0080 11AC CAN0 Message Slot 10 Data 6 CAN0 Message Slot 10 Data 7 13-70 (C0MSL10DT6) (C0MSL10DT7) 13-71 H'0080 11AE CAN0 Message Slot 10 Timestamp 13-72 (C0MSL10TSP) H'0080 11B0 CAN0 Message Slot 11 Standard ID 0 CAN0 Message Slot 11 Standard ID 1 13-58 (C0MSL11SID0) (C0MSL11SID1) 13-59 H'0080 11B2 CAN0 Message Slot 11 Extended ID 0 CAN0 Message Slot 11 Extended ID 1 13-60 (C0MSL11EID0) (C0MSL11EID1) 13-61 H'0080 11B4 CAN0 Message Slot 11 Extended ID 2 CAN0 Message Slot 11 Data Length Register 13-62 (C0MSL11EID2) (C0MSL11DLC) 13-63 H'0080 11B6 CAN0 Message Slot 11 Data 0 CAN0 Message Slot 11 Data 1 13-64 (C0MSL11DT0) (C0MSL11DT1) 13-65 H'0080 11B8 CAN0 Message Slot 11 Data 2 CAN0 Message Slot 11 Data 3 13-66 (C0MSL11DT2) (C0MSL11DT3) 13-67 H'0080 11BA CAN0 Message Slot 11 Data 4 CAN0 Message Slot 11 Data 5 13-68 (C0MSL11DT4) (C0MSL11DT5) 13-69 H'0080 11BC CAN0 Message Slot 11 Data 6 CAN0 Message Slot 11 Data 7 13-70 (C0MSL11DT6) (C0MSL11DT7) 13-71 H'0080 11BE CAN0 Message Slot 11 Timestamp 13-72 (C0MSL11TSP) H'0080 11C0 CAN0 Message Slot 12 Standard ID 0 CAN0 Message Slot 12 Standard ID 1 13-58 (C0MSL12SID0) (C0MSL12SID1) 13-59 H'0080 11C2 CAN0 Message Slot 12 Extended ID 0 CAN0 Message Slot 12 Extended ID 1 13-60 (C0MSL12EID0) (C0MSL12EID1) 13-61 H'0080 11C4 CAN0 Message Slot 12 Extended ID 2 CAN0 Message Slot 12 Data Length Register 13-62 (C0MSL12EID2) (C0MSL12DLC) 13-63 H'0080 11C6 CAN0 Message Slot 12 Data 0 CAN0 Message Slot 12 Data 1 13-64 (C0MSL12DT0) (C0MSL12DT1) 13-65 H'0080 11C8 CAN0 Message Slot 12 Data 2 CAN0 Message Slot 12 Data 3 13-66 (C0MSL12DT2) (C0MSL12DT3) 13-67 H'0080 11CA CAN0 Message Slot 12 Data 4 CAN0 Message Slot 12 Data 5 13-68 (C0MSL12DT4) (C0MSL12DT5) 13-69 H'0080 11CC CAN0 Message Slot 12 Data 6 CAN0 Message Slot 12 Data 7 13-70 (C0MSL12DT6) (C0MSL12DT7) 13-71 H'0080 11CE CAN0 Message Slot 12 Timestamp 13-72 (C0MSL12TSP) H'0080 11D0 CAN0 Message Slot 13 Standard ID 0 CAN0 Message Slot 13 Standard ID 1 13-58 (C0MSL13SID0) (C0MSL13SID1) 13-59 H'0080 11D2 CAN0 Message Slot 13 Extended ID 0 CAN0 Message Slot 13 Extended ID 1 13-60 (C0MSL13EID0) (C0MSL13EID1) 13-61 H'0080 11D4 CAN0 Message Slot 13 Extended ID 2 CAN0 Message Slot 13 Data Length Register 13-62 (C0MSL13EID2) (C0MSL13DLC) 13-63 H'0080 11D6 CAN0 Message Slot 13 Data 0 CAN0 Message Slot 13 Data 1 13-64 (C0MSL13DT0) (C0MSL13DT1) 13-65 H'0080 11D8 CAN0 Message Slot 13 Data 2 CAN0 Message Slot 13 Data 3 13-66 (C0MSL13DT2) (C0MSL13DT3) 13-67 H'0080 11DA CAN0 Message Slot 13 Data 4 CAN0 Message Slot 13 Data 5 13-68 (C0MSL13DT4) (C0MSL13DT5) 13-69 H'0080 11DC CAN0 Message Slot 13 Data 6 CAN0 Message Slot 13 Data 7 13-70 (C0MSL13DT6) (C0MSL13DT7) 13-71 H'0080 11DE CAN0 Message Slot 13 Timestamp 13-72 (C0MSL13TSP)

3-2632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (17/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 11E0 CAN0 Message Slot 14 Standard ID 0 CAN0 Message Slot 14 Standard ID 1 13-58 (C0MSL14SID0) (C0MSL14SID1) 13-59 H'0080 11E2 CAN0 Message Slot 14 Extended ID 0 CAN0 Message Slot 14 Extended ID 1 13-60 (C0MSL14EID0) (C0MSL14EID1) 13-61 H'0080 11E4 CAN0 Message Slot 14 Extended ID 2 CAN0 Message Slot 14 Data Length Register 13-62 (C0MSL14EID2) (C0MSL14DLC) 13-63 H'0080 11E6 CAN0 Message Slot 14 Data 0 CAN0 Message Slot 14 Data 1 13-64 (C0MSL14DT0) (C0MSL14DT1) 13-65 H'0080 11E8 CAN0 Message Slot 14 Data 2 CAN0 Message Slot 14 Data 3 13-66 (C0MSL14DT2) (C0MSL14DT3) 13-67 H'0080 11EA CAN0 Message Slot 14 Data 4 CAN0 Message Slot 14 Data 5 13-68 (C0MSL14DT4) (C0MSL14DT5) 13-69 H'0080 11EC CAN0 Message Slot 14 Data 6 CAN0 Message Slot 14 Data 7 13-70 (C0MSL14DT6) (C0MSL14DT7) 13-71 H'0080 11EE CAN0 Message Slot 14 Timestamp 13-72 (C0MSL14TSP) H'0080 11F0 CAN0 Message Slot 15 Standard ID 0 CAN0 Message Slot 15 Standard ID 1 13-58 (C0MSL15SID0) (C0MSL15SID1) 13-59 H'0080 11F2 CAN0 Message Slot 15 Extended ID 0 CAN0 Message Slot 15 Extended ID 1 13-60 (C0MSL15EID0) (C0MSL15EID1) 13-61 H'0080 11F4 CAN0 Message Slot 15 Extended ID 2 CAN0 Message Slot 15 Data Length Register 13-62 (C0MSL15EID2) (C0MSL15DLC) 13-63 H'0080 11F6 CAN0 Message Slot 15 Data 0 CAN0 Message Slot 15 Data 1 13-64 (C0MSL15DT0) (C0MSL15DT1) 13-65 H'0080 11F8 CAN0 Message Slot 15 Data 2 CAN0 Message Slot 15 Data 3 13-66 (C0MSL15DT2) (C0MSL15DT3) 13-67 H'0080 11FA CAN0 Message Slot 15 Data 4 CAN0 Message Slot 15 Data 5 13-68 (C0MSL15DT4) (C0MSL15DT5) 13-69 H'0080 11FC CAN0 Message Slot 15 Data 6 CAN0 Message Slot 15 Data 7 13-70 (C0MSL15DT6) (C0MSL15DT7) 13-71 H'0080 11FE CAN0 Message Slot 15 Timestamp 13-72 (C0MSL15TSP) (Use inhibited area) H'0080 1400 CAN1 Control Register 13-15 (CAN1CNT) H'0080 1402 CAN1 Status Register 13-18 (CAN1STAT) H'0080 1404 CAN1 Extended ID Register 13-21 (CAN1EXTID) H'0080 1406 CAN1 Configuration Register 13-22 (CAN1CONF) H'0080 1408 CAN1 Timestamp Count Register 13-24 (CAN1TSTMP) H'0080 140A CAN1 Receive Error Count Register CAN1 Transmit Error Count Register 13-25 (CAN1REC) (CAN1TEC) H'0080 140C CAN1 Slot Interrupt Request Status Register 13-29 (CAN1SLIST) H'0080 140E (Use inhibited area) H'0080 1410 CAN1 Slot Interrupt Request Mask Register 13-30 (CAN1SLIMK) H'0080 1412 (Use inhibited area) H'0080 1414 CAN1 Error Interrupt Request Status Register CAN1 Error Interrupt Request Mask Register 13-31 (CAN1ERIST) (CAN1ERIMK) 13-32 H'0080 1416 CAN1 Baud Rate Prescaler CAN1 Cause of Error Register 13-26 (CAN1BRP) (CAN1EF) 13-45 H'0080 1418 CAN1 Mode Register CAN1 DMA Transfer Request Select Register 13-47 (CAN1MOD) (CAN1DMARQ) 13-48 (Use inhibited area) H'0080 1428 CAN1 Global Mask Register Standard ID 0 CAN1 Global Mask Register Standard ID 1 13-49 (C1GMSKS0) (C1GMSKS1) H'0080 142A CAN1 Global Mask Register Extended ID 0 CAN1 Global Mask Register Extended ID 1 13-50 (C1GMSKE0) (C1GMSKE1) H'0080 142C CAN1 Global Mask Register Extended ID 2 (Use inhibited area) 13-51 (C1GMSKE2) H'0080 142E (Use inhibited area)

3-2732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (18/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 1430 CAN1 Local Mask Register A Standard ID 0 CAN1 Local Mask Register A Standard ID 1 13-49 (C1LMSKAS0) (C1LMSKAS1) H'0080 1432 CAN1 Local Mask Register A Extended ID 0 CAN1 Local Mask Register A Extended ID 1 13-50 (C1LMSKAE0) (C1LMSKAE1) H'0080 1434 CAN1 Local Mask Register A Extended ID 2 (Use inhibited area) 13-51 (C1LMSKAE2) H'0080 1436 (Use inhibited area) H'0080 1438 CAN1 Local Mask Register B Standard ID 0 CAN1 Local Mask Register B Standard ID 1 13-49 (C1LMSKBS0) (C1LMSKBS1) H'0080 143A CAN1 Local Mask Register B Extended ID 0 CAN1 Local Mask Register B Extended ID 1 13-50 (C1LMSKBE0) (C1LMSKBE1) H'0080 143C CAN1 Local Mask Register B Extended ID 2 (Use inhibited area) 13-51 (C1LMSKBE2) H'0080 143E (Use inhibited area) H'0080 1440 CAN1 Single-Shot Mode Control Register 13-53 (CAN1SSMODE) H'0080 1442 (Use inhibited area) H'0080 1444 CAN1 Single-Shot Interrupt Request Status Register 13-33 (CAN1SSIST) H'0080 1446 (Use inhibited area) H'0080 1448 CAN1 Single-Shot Interrupt Request Mask Register 13-34 (CAN1SSIMK) (Use inhibited area) H'0080 1450 CAN1 Message Slot 0 Control Register CAN1 Message Slot 1 Control Register 13-54 (C1MSL0CNT) (C1MSL1CNT) H'0080 1452 CAN1 Message Slot 2 Control Register CAN1 Message Slot 3 Control Register 13-54 (C1MSL2CNT) (C1MSL3CNT) H'0080 1454 CAN1 Message Slot 4 Control Register CAN1 Message Slot 5 Control Register 13-54 (C1MSL4CNT) (C1MSL5CNT) H'0080 1456 CAN1 Message Slot 6 Control Register CAN1 Message Slot 7 Control Register 13-54 (C1MSL6CNT) (C1MSL7CNT) H'0080 1458 CAN1 Message Slot 8 Control Register CAN1 Message Slot 9 Control Register 13-54 (C1MSL8CNT) (C1MSL9CNT) H'0080 145A CAN1 Message Slot 10 Control Register CAN1 Message Slot 11 Control Register 13-54 (C1MSL10CNT) (C1MSL11CNT) H'0080 145C CAN1 Message Slot 12 Control Register CAN1 Message Slot 13 Control Register 13-54 (C1MSL12CNT) (C1MSL13CNT) H'0080 145E CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register 13-54 (C1MSL14CNT) (C1MSL15CNT) (Use inhibited area) H'0080 1500 CAN1 Message Slot 0 Standard ID 0 CAN1 Message Slot 0 Standard ID 1 13-58 (C1MSL0SID0) (C1MSL0SID1) 13-59 H'0080 1502 CAN1 Message Slot 0 Extended ID 0 CAN1 Message Slot 0 Extended ID 1 13-60 (C1MSL0EID0) (C1MSL0EID1) 13-61 H'0080 1504 CAN1 Message Slot 0 Extended ID 2 CAN1 Message Slot 0 Data Length Register 13-62 (C1MSL0EID2) (C1MSL0DLC) 13-63 H'0080 1506 CAN1 Message Slot 0 Data 0 CAN1 Message Slot 0 Data 1 13-64 (C1MSL0DT0) (C1MSL0DT1) 13-65 H'0080 1508 CAN1 Message Slot 0 Data 2 CAN1 Message Slot 0 Data 3 13-66 (C1MSL0DT2) (C1MSL0DT3) 13-67 H'0080 150A CAN1 Message Slot 0 Data 4 CAN1 Message Slot 0 Data 5 13-68 (C1MSL0DT4) (C1MSL0DT5) 13-69 H'0080 150C CAN1 Message Slot 0 Data 6 CAN1 Message Slot 0 Data 7 13-70 (C1MSL0DT6) (C1MSL0DT7) 13-71 H'0080 150E CAN1 Message Slot 0 Timestamp 13-72 (C1MSL0TSP)

3-2832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (19/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 1510 CAN1 Message Slot 1 Standard ID 0 CAN1 Message Slot 1 Standard ID 1 13-58 (C1MSL1SID0) (C1MSL1SID1) 13-59 H'0080 1512 CAN1 Message Slot 1 Extended ID 0 CAN1 Message Slot 1 Extended ID 1 13-60 (C1MSL1EID0) (C1MSL1EID1) 13-61 H'0080 1514 CAN1 Message Slot 1 Extended ID 2 CAN1 Message Slot 1 Data Length Register 13-62 (C1MSL1EID2) (C1MSL1DLC) 13-63 H'0080 1516 CAN1 Message Slot 1 Data 0 CAN1 Message Slot 1 Data 1 13-64 (C1MSL1DT0) (C1MSL1DT1) 13-65 H'0080 1518 CAN1 Message Slot 1 Data 2 CAN1 Message Slot 1 Data 3 13-66 (C1MSL1DT2) (C1MSL1DT3) 13-67 H'0080 151A CAN1 Message Slot 1 Data 4 CAN1 Message Slot 1 Data 5 13-68 (C1MSL1DT4) (C1MSL1DT5) 13-69 H'0080 151C CAN1 Message Slot 1 Data 6 CAN1 Message Slot 1 Data 7 13-70 (C1MSL1DT6) (C1MSL1DT7) 13-71 H'0080 151E CAN1 Message Slot 1 Timestamp 13-72 (C1MSL1TSP) H'0080 1520 CAN1 Message Slot 2 Standard ID 0 CAN1 Message Slot 2 Standard ID 1 13-58 (C1MSL2SID0) (C1MSL2SID1) 13-59 H'0080 1522 CAN1 Message Slot 2 Extended ID 0 CAN1 Message Slot 2 Extended ID 1 13-60 (C1MSL2EID0) (C1MSL2EID1) 13-61 H'0080 1524 CAN1 Message Slot 2 Extended ID 2 CAN1 Message Slot 2 Data Length Register 13-62 (C1MSL2EID2) (C1MSL2DLC) 13-63 H'0080 1526 CAN1 Message Slot 2 Data 0 CAN1 Message Slot 2 Data 1 13-64 (C1MSL2DT0) (C1MSL2DT1) 13-65 H'0080 1528 CAN1 Message Slot 2 Data 2 CAN1 Message Slot 2 Data 3 13-66 (C1MSL2DT2) (C1MSL2DT3) 13-67 H'0080 152A CAN1 Message Slot 2 Data 4 CAN1 Message Slot 2 Data 5 13-68 (C1MSL2DT4) (C1MSL2DT5) 13-69 H'0080 152C CAN1 Message Slot 2 Data 6 CAN1 Message Slot 2 Data 7 13-70 (C1MSL2DT6) (C1MSL2DT7) 13-71 H'0080 152E CAN1 Message Slot 2 Timestamp 13-72 (C1MSL2TSP) H'0080 1530 CAN1 Message Slot 3 Standard ID 0 CAN1 Message Slot 3 Standard ID 1 13-58 (C1MSL3SID0) (C1MSL3SID1) 13-59 H'0080 1532 CAN1 Message Slot 3 Extended ID 0 CAN1 Message Slot 3 Extended ID 1 13-60 (C1MSL3EID0) (C1MSL3EID1) 13-61 H'0080 1534 CAN1 Message Slot 3 Extended ID 2 CAN1 Message Slot 3 Data Length Register 13-62 (C1MSL3EID2) (C1MSL3DLC) 13-63 H'0080 1536 CAN1 Message Slot 3 Standard ID 0 CAN1 Message Slot 3 Standard ID 1 13-64 (C1MSL3DT0) (C1MSL3DT1) 13-65 H'0080 1538 CAN1 Message Slot 3 Data 2 CAN1 Message Slot 3 Data 3 13-66 (C1MSL3DT2) (C1MSL3DT3) 13-67 H'0080 153A CAN1 Message Slot 3 Data 4 CAN1 Message Slot 3 Data 5 13-68 (C1MSL3DT4) (C1MSL3DT5) 13-69 H'0080 153C CAN1 Message Slot 3 Data 6 CAN1 Message Slot 3 Data 7 13-70 (C1MSL3DT6) (C1MSL3DT7) 13-71 H'0080 153E CAN1 Message Slot 3 Timestamp 13-72 (C1MSL3TSP) H'0080 1540 CAN1 Message Slot 4 Standard ID 0 CAN1 Message Slot 4 Standard ID 1 13-58 (C1MSL4SID0) (C1MSL4SID1) 13-59 H'0080 1542 CAN1 Message Slot 4 Extended ID 0 CAN1 Message Slot 4 Extended ID 1 13-60 (C1MSL4EID0) (C1MSL4EID1) 13-61 H'0080 1544 CAN1 Message Slot 4 Extended ID 2 CAN1 Message Slot 4 Data Length Register 13-62 (C1MSL4EID2) (C1MSL4DLC) 13-63 H'0080 1546 CAN1 Message Slot 4 Data 0 CAN1 Message Slot 4 Data 1 13-64 (C1MSL4DT0) (C1MSL4DT1) 13-65 H'0080 1548 CAN1 Message Slot 4 Data 2 CAN1 Message Slot 4 Data 3 13-66 (C1MSL4DT2) (C1MSL4DT3) 13-67 H'0080 154A CAN1 Message Slot 4 Data 4 CAN1 Message Slot 4 Data 5 13-68 (C1MSL4DT4) (C1MSL4DT5) 13-69 H'0080 154C CAN1 Message Slot 4 Data 6 CAN1 Message Slot 4 Data 7 13-70 (C1MSL4DT6) (C1MSL4DT7) 13-71 H'0080 154E CAN1 Message Slot 4 Timestamp 13-72 (C1MSL4TSP)

3-2932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (20/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 1550 CAN1 Message Slot 5 Standard ID 0 CAN1 Message Slot 5 Standard ID 1 13-58 (C1MSL5SID0) (C1MSL5SID1) 13-59 H'0080 1552 CAN1 Message Slot 5 Extended ID 0 CAN1 Message Slot 5 Extended ID 1 13-60 (C1MSL5EID0) (C1MSL5EID1) 13-61 H'0080 1554 CAN1 Message Slot 5 Extended ID 2 CAN1 Message Slot 5 Data Length Register 13-62 (C1MSL5EID2) (C1MSL5DLC) 13-63 H'0080 1556 CAN1 Message Slot 5 Data 0 CAN1 Message Slot 5 Data 1 13-64 (C1MSL5DT0) (C1MSL5DT1) 13-65 H'0080 1558 CAN1 Message Slot 5 Data 2 CAN1 Message Slot 5 Data 3 13-66 (C1MSL5DT2) (C1MSL5DT3) 13-67 H'0080 155A CAN1 Message Slot 5 Data 4 CAN1 Message Slot 5 Data 5 13-68 (C1MSL5DT4) (C1MSL5DT5) 13-69 H'0080 155C CAN1 Message Slot 5 Data 6 CAN1 Message Slot 5 Data 7 13-70 (C1MSL5DT6) (C1MSL5DT7) 13-71 H'0080 155E CAN1 Message Slot 5 Timestamp 13-72 (C1MSL5TSP) H'0080 1560 CAN1 Message Slot 6 Standard ID 0 CAN1 Message Slot 6 Standard ID 1 13-58 (C1MSL6SID0) (C1MSL6SID1) 13-59 H'0080 1562 CAN1 Message Slot 6 Extended ID 0 CAN1 Message Slot 6 Extended ID 1 13-60 (C1MSL6EID0) (C1MSL6EID1) 13-61 H'0080 1564 CAN1 Message Slot 6 Extended ID 2 CAN1 Message Slot 6 Data Length Register 13-62 (C1MSL6EID2) (C1MSL6DLC) 13-63 H'0080 1566 CAN1 Message Slot 6 Data 0 CAN1 Message Slot 6 Data 1 13-64 (C1MSL6DT0) (C1MSL6DT1) 13-65 H'0080 1568 CAN1 Message Slot 6 Data 2 CAN1 Message Slot 6 Data 3 13-66 (C1MSL6DT2) (C1MSL6DT3) 13-67 H'0080 156A CAN1 Message Slot 6 Data 4 CAN1 Message Slot 6 Data 5 13-68 (C1MSL6DT4) (C1MSL6DT5) 13-69 H'0080 156C CAN1 Message Slot 6 Data 6 CAN1 Message Slot 6 Data 7 13-70 (C1MSL6DT6) (C1MSL6DT7) 13-71 H'0080 156E CAN1 Message Slot 6 Timestamp 13-72 (C1MSL6TSP) H'0080 1570 CAN1 Message Slot 7 Standard ID 0 CAN1 Message Slot 7 Standard ID 1 13-58 (C1MSL7SID0) (C1MSL7SID1) 13-59 H'0080 1572 CAN1 Message Slot 7 Extended ID 0 CAN1 Message Slot 7 Extended ID 1 13-60 (C1MSL7EID0) (C1MSL7EID1) 13-61 H'0080 1574 CAN1 Message Slot 7 Extended ID 2 CAN1 Message Slot 7 Data Length Register 13-62 (C1MSL7EID2) (C1MSL7DLC) 13-63 H'0080 1576 CAN1 Message Slot 7 Data 0 CAN1 Message Slot 7 Data 1 13-64 (C1MSL7DT0) (C1MSL7DT1) 13-65 H'0080 1578 CAN1 Message Slot 7 Data 2 CAN1 Message Slot 7 Data 3 13-66 (C1MSL7DT2) (C1MSL7DT3) 13-67 H'0080 157A CAN1 Message Slot 7 Data 4 CAN1 Message Slot 7 Data 5 13-68 (C1MSL7DT4) (C1MSL7DT5) 13-69 H'0080 157C CAN1 Message Slot 7 Data 6 CAN1 Message Slot 7 Data 7 13-70 (C1MSL7DT6) (C1MSL7DT7) 13-71 H'0080 157E CAN1 Message Slot 7 Timestamp 13-72 (C1MSL7TSP) H'0080 1580 CAN1 Message Slot 8 Standard ID 0 CAN1 Message Slot 8 Standard ID 1 13-58 (C1MSL8SID0) (C1MSL8SID1) 13-59 H'0080 1582 CAN1 Message Slot 8 Extended ID 0 CAN1 Message Slot 8 Extended ID 1 13-60 (C1MSL8EID0) (C1MSL8EID1) 13-61 H'0080 1584 CAN1 Message Slot 8 Extended ID 2 CAN1 Message Slot 8 Data Length Register 13-62 (C1MSL8EID2) (C1MSL8DLC) 13-63 H'0080 1586 CAN1 Message Slot 8 Data 0 CAN1 Message Slot 8 Data 1 13-64 (C1MSL8DT0) (C1MSL8DT1) 13-65 H'0080 1588 CAN1 Message Slot 8 Data 2 CAN1 Message Slot 8 Data 3 13-66 (C1MSL8DT2) (C1MSL8DT3) 13-67 H'0080 158A CAN1 Message Slot 8 Data 4 CAN1 Message Slot 8 Data 5 13-68 (C1MSL8DT4) (C1MSL8DT5) 13-69 H'0080 158C CAN1 Message Slot 8 Data 6 CAN1 Message Slot 8 Data 7 13-70 (C1MSL8DT6) (C1MSL8DT7) 13-71 H'0080 158E CAN1 Message Slot 8 Timestamp 13-72 (C1MSL8TSP)

3-3032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (21/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 1590 CAN1 Message Slot 9 Standard ID 0 CAN1 Message Slot 9 Standard ID 1 13-58 (C1MSL9SID0) (C1MSL9SID1) 13-59 H'0080 1592 CAN1 Message Slot 9 Extended ID 0 CAN1 Message Slot 9 Extended ID 1 13-60 (C1MSL9EID0) (C1MSL9EID1) 13-61 H'0080 1594 CAN1 Message Slot 9 Extended ID 2 CAN1 Message Slot 9 Data Length Register 13-62 (C1MSL9EID2) (C1MSL9DLC) 13-63 H'0080 1596 CAN1 Message Slot 9 Data 0 CAN1 Message Slot 9 Data 1 13-64 (C1MSL9DT0) (C1MSL9DT1) 13-65 H'0080 1598 CAN1 Message Slot 9 Data 2 CAN1 Message Slot 9 Data 3 13-66 (C1MSL9DT2) (C1MSL9DT3) 13-67 H'0080 159A CAN1 Message Slot 9 Data 4 CAN1 Message Slot 9 Data 5 13-68 (C1MSL9DT4) (C1MSL9DT5) 13-69 H'0080 159C CAN1 Message Slot 9 Data 6 CAN1 Message Slot 9 Data 7 13-70 (C1MSL9DT6) (C1MSL9DT7) 13-71 H'0080 159E CAN1 Message Slot 9 Timestamp 13-72 (C1MSL9TSP) H'0080 15A0 CAN1 Message Slot 10 Standard ID 0 CAN1 Message Slot 10 Standard ID 1 13-58 (C1MSL10SID0) (C1MSL10SID1) 13-59 H'0080 15A2 CAN1 Message Slot 10 Extended ID 0 CAN1 Message Slot 10 Extended ID 1 13-60 (C1MSL10EID0) (C1MSL10EID1) 13-61 H'0080 15A4 CAN1 Message Slot 10 Extended ID 2 CAN1 Message Slot 10 Data Length Register 13-62 (C1MSL10EID2) (C1MSL10DLC) 13-63 H'0080 15A6 CAN1 Message Slot 10 Data 0 CAN1 Message Slot 10 Data 1 13-64 (C1MSL10DT0) (C1MSL10DT1) 13-65 H'0080 15A8 CAN1 Message Slot 10 Data 2 CAN1 Message Slot 10 Data 3 13-66 (C1MSL10DT2) (C1MSL10DT3) 13-67 H'0080 15AA CAN1 Message Slot 10 Data 4 CAN1 Message Slot 10 Data 5 13-68 (C1MSL10DT4) (C1MSL10DT5) 13-69 H'0080 15AC CAN1 Message Slot 10 Data 6 CAN1 Message Slot 10 Data 7 13-70 (C1MSL10DT6) (C1MSL10DT7) 13-71 H'0080 15AE CAN1 Message Slot 10 Timestamp 13-72 (C1MSL10TSP) H'0080 15B0 CAN1 Message Slot 11 Standard ID 0 CAN1 Message Slot 11 Standard ID 1 13-58 (C1MSL11SID0) (C1MSL11SID1) 13-59 H'0080 15B2 CAN1 Message Slot 11 Extended ID 0 CAN1 Message Slot 11 Extended ID 1 13-60 (C1MSL11EID0) (C1MSL11EID1) 13-61 H'0080 15B4 CAN1 Message Slot 11 Extended ID 2 CAN1 Message Slot 11 Data Length Register 13-62 (C1MSL11EID2) (C1MSL11DLC) 13-63 H'0080 15B6 CAN1 Message Slot 11 Data 0 CAN1 Message Slot 11 Data 1 13-64 (C1MSL11DT0) (C1MSL11DT1) 13-65 H'0080 15B8 CAN1 Message Slot 11 Data 2 CAN1 Message Slot 11 Data 3 13-66 (C1MSL11DT2) (C1MSL11DT3) 13-67 H'0080 15BA CAN1 Message Slot 11 Data 4 CAN1 Message Slot 11 Data 5 13-68 (C1MSL11DT4) (C1MSL11DT5) 13-69 H'0080 15BC CAN1 Message Slot 11 Data 6 CAN1 Message Slot 11 Data 7 13-70 (C1MSL11DT6) (C1MSL11DT7) 13-71 H'0080 15BE CAN1 Message Slot 11 Timestamp 13-72 (C1MSL11TSP) H'0080 15C0 CAN1 Message Slot 12 Standard ID 0 CAN1 Message Slot 12 Standard ID 1 13-58 (C1MSL12SID0) (C1MSL12SID1) 13-59 H'0080 15C2 CAN1 Message Slot 12 Extended ID 0 CAN1 Message Slot 12 Extended ID 1 13-60 (C1MSL12EID0) (C1MSL12EID1) 13-61 H'0080 15C4 CAN1 Message Slot 12 Extended ID 2 CAN1 Message Slot 12 Data Length Register 13-62 (C1MSL12EID2) (C1MSL12DLC) 13-63 H'0080 15C6 CAN1 Message Slot 12 Data 0 CAN1 Message Slot 12 Data 1 13-64 (C1MSL12DT0) (C1MSL12DT1) 13-65 H'0080 15C8 CAN1 Message Slot 12 Data 2 CAN1 Message Slot 12 Data 3 13-66 (C1MSL12DT2) (C1MSL12DT3) 13-67 H'0080 15CA CAN1 Message Slot 12 Data 4 CAN1 Message Slot 12 Data 5 13-68 (C1MSL12DT4) (C1MSL12DT5) 13-69 H'0080 15CC CAN1 Message Slot 12 Data 6 CAN1 Message Slot 12 Data 7 13-70 (C1MSL12DT6) (C1MSL12DT7) 13-71 H'0080 15CE CAN1 Message Slot 12 Timestamp 13-72 (C1MSL12TSP)

3-3132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SFR Area Register Map (22/22) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 15D0 CAN1 Message Slot 13 Standard ID 0 CAN1 Message Slot 13 Standard ID 1 13-58 (C1MSL13SID0) (C1MSL13SID1) 13-59 H'0080 15D2 CAN1 Message Slot 13 Extended ID 0 CAN1 Message Slot 13 Extended ID 1 13-60 (C1MSL13EID0) (C1MSL13EID1) 13-61 H'0080 15D4 CAN1 Message Slot 13 Extended ID 2 CAN1 Message Slot 13 Data Length Register 13-62 (C1MSL13EID2) (C1MSL13DLC) 13-63 H'0080 15D6 CAN1 Message Slot 13 Data 0 CAN1 Message Slot 13 Data 1 13-64 (C1MSL13DT0) (C1MSL13DT1) 13-65 H'0080 15D8 CAN1 Message Slot 13 Data 2 CAN1 Message Slot 13 Data 3 13-66 (C1MSL13DT2) (C1MSL13DT3) 13-67 H'0080 15DA CAN1 Message Slot 13 Data 4 CAN1 Message Slot 13 Data 5 13-68 (C1MSL13DT4) (C1MSL13DT5) 13-69 H'0080 15DC CAN1 Message Slot 13 Data 6 CAN1 Message Slot 13 Data 7 13-70 (C1MSL13DT6) (C1MSL13DT7) 13-71 H'0080 15DE CAN1 Message Slot 13 Timestamp 13-72 (C1MSL13TSP) H'0080 15E0 CAN1 Message Slot 14 Standard ID 0 CAN1 Message Slot 14 Standard ID 1 13-58 (C1MSL14SID0) (C1MSL14SID1) 13-59 H'0080 15E2 CAN1 Message Slot 14 Extended ID 0 CAN1 Message Slot 14 Extended ID 1 13-60 (C1MSL14EID0) (C1MSL14EID1) 13-61 H'0080 15E4 CAN1 Message Slot 14 Extended ID 2 CAN1 Message Slot 14 Data Length Register 13-62 (C1MSL14EID2) (C1MSL14DLC) 13-63 H'0080 15E6 CAN1 Message Slot 14 Data 0 CAN1 Message Slot 14 Data 1 13-64 (C1MSL14DT0) (C1MSL14DT1) 13-65 H'0080 15E8 CAN1 Message Slot 14 Data 2 CAN1 Message Slot 14 Data 3 13-66 (C1MSL14DT2) (C1MSL14DT3) 13-67 H'0080 15EA CAN1 Message Slot 14 Data 4 CAN1 Message Slot 14 Data 5 13-68 (C1MSL14DT4) (C1MSL14DT5) 13-69 H'0080 15EC CAN1 Message Slot 14 Data 6 CAN1 Message Slot 14 Data 7 13-70 (C1MSL14DT6) (C1MSL14DT7) 13-71 H'0080 15EE CAN1 Message Slot 14 Timestamp 13-72 (C1MSL14TSP) H'0080 15F0 CAN1 Message Slot 15 Standard ID 0 CAN1 Message Slot 15 Standard ID 1 13-58 (C1MSL15SID0) (C1MSL15SID1) 13-59 H'0080 15F2 CAN1 Message Slot 15 Extended ID 0 CAN1 Message Slot 15 Extended ID 1 13-60 (C1MSL15EID0) (C1MSL15EID1) 13-61 H'0080 15F4 CAN1 Message Slot 15 Extended ID 2 CAN1 Message Slot 15 Data Length Register 13-62 (C1MSL15EID2) (C1MSL15DLC) 13-63 H'0080 15F6 CAN1 Message Slot 15 Data 0 CAN1 Message Slot 15 Data 1 13-64 (C1MSL15DT0) (C1MSL15DT1) 13-65 H'0080 15F8 CAN1 Message Slot 15 Data 2 CAN1 Message Slot 15 Data 3 13-66 (C1MSL15DT2) (C1MSL15DT3) 13-67 H'0080 15FA CAN1 Message Slot 15 Data 4 CAN1 Message Slot 15 Data 5 13-68 (C1MSL15DT4) (C1MSL15DT5) 13-69 H'0080 15FC CAN1 Message Slot 15 Data 6 CAN1 Message Slot 15 Data 7 13-70 (C1MSL15DT6) (C1MSL15DT7) 13-71 H'0080 15FE CAN1 Message Slot 15 Timestamp 13-72 (C1MSL15TSP) (Use inhibited area) H'0080 3FFE (Use inhibited area) Note1. Address H'0080 0600 - H'0080 0603 are dummy areas. When there is access to these areas, writing value is disabled and reading value is undefined. In addition, it does not effect on the other SFR area by writing and reading out operation to dummy access area.

3-3232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The EIT vector entry is located at the beginning of the internal ROM/external extension areas. The branch instruction for jumping to the start address of each EIT event processing handler is written here. Note that it is the branch instruction and not the jump address itself that is written here. For details, see Chapter 4, “EIT.” H'0000 0040 H'0000 0044 H'0000 0048 H'0000 004C H'0000 0050 H'0000 0054 H'0000 0058 H'0000 005C H'0000 0060 H'0000 0064 H'0000 0068 H'0000 006C H'0000 0070 H'0000 0074 H'0000 0078 H'0000 007C H'0000 0080 H'0000 0030 H'0000 0020 H'0000 0010 H'0000 0000 H'0000 0034 H'0000 0038 H'0000 003C H'0000 0024 H'0000 0028 H'0000 002C H'0000 0004 H'0000 0008 H'0000 000C H'0000 0014 H'0000 0018 H'0000 001C TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 AE (Address Exception) EI (External Interrupt) (Note 1) RI (Reset Interrupt) SBI (System Break Interrupt) RIE (Reserved Instruction Exception) 03 1 Note 1: When flash entry bit = 1 (flash E/W enable mode), the EI vector entry is located at H'0080 4000. Figure 3.5.1 EIT Vector Entry

3-3332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The ICU vector table is used by the internal interrupt controller of the microcomputer. This table has the addresses shown below, at which the start addresses of interrupt handlers for the interrupt requests from respective internal peripheral I/Os are set. For details, see Chapter 5, “Interrupt Controller.” ICU Vector Table Memory Map (1/2) Address +0 address +1 address b0 b7 b8 b15 H'0000 0094 MJT Input Interrupt 4 Handler Start Address (A0–A15) H'0000 0096 MJT Input Interrupt 4 Handler Start Address (A16–A31) H'0000 0098 MJT Input Interrupt 3 Handler Start Address (A0–A15) H'0000 009A MJT Input Interrupt 3 Handler Start Address (A16–A31) H'0000 009C MJT Input Interrupt 2 Handler Start Address (A0–A15) H'0000 009E MJT Input Interrupt 2 Handler Start Address (A16–A31) H'0000 00A0 MJT Input Interrupt 1 Handler Start Address (A0–A15) H'0000 00A2 MJT Input Interrupt 1 Handler Start Address (A16–A31) H'0000 00A4 H'0000 00A6 H'0000 00A8 MJT Output Interrupt 7 Handler Start Address (A0–A15) H'0000 00AA MJT Output Interrupt 7 Handler Start Address (A16–A31) H'0000 00AC MJT Output Interrupt 6 Handler Start Address (A0–A15) H'0000 00AE MJT Output Interrupt 6 Handler Start Address (A16–A31) H'0000 00B0 MJT Output Interrupt 5 Handler Start Address (A0–A15) H'0000 00B2 MJT Output Interrupt 5 Handler Start Address (A16–A31) H'0000 00B4 MJT Output Interrupt 4 Handler Start Address (A0–A15) H'0000 00B6 MJT Output Interrupt 4 Handler Start Address (A16–A31) H'0000 00B8 MJT Output Interrupt 3 Handler Start Address (A0–A15) H'0000 00BA MJT Output Interrupt 3 Handler Start Address (A16–A31) H'0000 00BC MJT Output Interrupt 2 Handler Start Address (A0–A15) H'0000 00BE MJT Output Interrupt 2 Handler Start Address (A16–A31) H'0000 00C0 MJT Output Interrupt 1 Handler Start Address (A0–A15) H'0000 00C2 MJT Output Interrupt 1 Handler Start Address (A16–A31) H'0000 00C4 MJT Output Interrupt 0 Handler Start Address (A0–A15) H'0000 00C6 MJT Output Interrupt 0 Handler Start Address (A16–A31) H'0000 00C8 DMA0–4 Interrupt Handler Start Address (A0–A15) H'0000 00CA DMA0–4 Interrupt Handler Start Address (A16–A31) H'0000 00CC SIO1 Receive Interrupt Handler Start Address (A0–A15) H'0000 00CE SIO1 Receive Interrupt Handler Start Address (A16–A31) H'0000 00D0 SIO1 Transmit Interrupt Handler Start Address (A0–A15) H'0000 00D2 SIO1 Transmit Interrupt Handler Start Address (A16–A31) H'0000 00D4 SIO0 Receive Interrupt Handler Start Address (A0–A15) H'0000 00D6 SIO0 Receive Interrupt Handler Start Address (A16–A31)

3-3432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 ICU Vector Table Memory Map (2/2) Address +0 address +1 address b0 b7 b8 b15 H'0000 00D8 SIO0 Transmit Interrupt Handler Start Address (A0–A15) H'0000 00DA SIO0 Transmit Interrupt Handler Start Address (A16–A31) H'0000 00DC A/D0 Conversion Interrupt Handler Start Address (A0–A15) H'0000 00DE A/D0 Conversion Interrupt Handler Start Address (A16–A31) H'0000 00E0 H'0000 00E2 H'0000 00E4 H'0000 00E6 H'0000 00E8 DMA5–9 Interrupt Handler Start Address (A0–A15) H'0000 00EA DMA5–9 Interrupt Handler Start Address (A16–A31) H'0000 00EC SIO2, 3 Transmit/receive Interrupt Handler Start Address (A0–A15) H'0000 00EE SIO2, 3 Transmit/receive Interrupt Handler Start Address (A16–A31) H'0000 00F0 RTD Interrupt Handler Start Address (A0–A15) H'0000 00F2 RTD Interrupt Handler Start Address (A16–A31) H'0000 00F4 H'0000 00F6 H'0000 00F8 H'0000 00FA H'0000 00FC H'0000 00FE H'0000 0100 H'0000 0102 H'0000 0104 H'0000 0106 H'0000 0108 H'0000 010A H'0000 010C CAN0 Transmit/receive & Error Interrupt Handler Start Address (A0–A15) H'0000 010E CAN0 Transmit/receive & Error Interrupt Handler Start Address (A16–A31) H'0000 0110 CAN1 Transmit/receive & Error Interrupt Handler Start Address (A0–A15) H'0000 0112 CAN1 Transmit/receive & Error Interrupt Handler Start Address (A16–A31)

3-3532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

Virtual flash emulation function The microcomputer has the function to map up to two 8-kbyte memory blocks of the internal RAM into areas of the internal flash memory (L banks) that are divided in 8-kbyte units, as well as to map up to two 4-kbyte memory blocks of the internal RAM into areas of the internal flash memory (S banks) that are divided in 4-kbyte units. This function is referred to as the virtual flash emulation function. For details about this function, refer to Section 6.6, “Virtual Flash Emulation Function.”
Dummy access areas Address H'0080 0600 - H'0080 0603 are dummy areas. When there is access to these areas, writing value is disabled and reading value is undefined. In addition, it does not effect on the other SFR area by writing and reading out operation to dummy access area.

3-3632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 This page is blank for reasons of layout.

4.1 Outline of EIT

4.2 EIT Events

4.3 EIT Processing Procedure

4.4 EIT Processing Mechanism

4.5 Acceptance of EIT Events

4.6 Saving and Restoring the PC and PSW

4.7 EIT Vector Entry

4.8 Exception Processing

4.9 Interrupt Processing

4.10 Trap Processing

4.11 EIT Priority Levels

4.12 Example of EIT Processing

4.13 Notes on EIT

4-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. Events like this one are referred to by a generic name as EIT (Exception, Interrupt and Trap). (1) Exception This is an event related to the context being executed. It is generated by an error or violation during instruction execution. This type of event includes Address Exception (AE) and Reserved Instruction Exception (RIE) . (2) Interrupt This is an event generated irrespective of the context being executed. It is generated by a hardware-derived signal from an external source. This type of event includes Reset Interrupt (RI), System Break Interrupt (SBI) and External Interrupt (EI). (3) Trap This refers to a software interrupt generated by executing a TRAP instruction. This type of event is intentionally generated in a program as in the OS’s system call by the programmer. Figure 4.1.1 Classification of EITs EIT Exception (Exception) Reserved Instruction Exception (RIE) Address Exception (AE) Reset Interrupt (RI) System Break Interrupt (SBI) External Interrupt (EI) Trap (TRAP) Interrupt (Interrupt) Trap (Trap)

4-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

4.2.1 Exceptions

(1) Reserved Instruction Exception (RIE) Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (unimplemented instruction) is detected. (2) Address Exception (AE) Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions.

4.2.2 Interrupts

(1) Reset Interrupt (RI) Reset Interrupt (RI) is always accepted by entering the RESET# signal. The reset interrupt is assigned the highest priority. (2) System Break Interrupt (SBI) System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. This interrupt can only be used in cases when after interrupt processing, control will not return to the program that was being executed when the interrupt occurred. (3) External Interrupt (EI) External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt controller. The internal interrupt controller manages these interrupts by assigning each one of eight priority levels includ- ing an interrupt-disabled state.

4.2.3 Trap

Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector addresses are provided corresponding to TRAP instruction operands 0–15.

4-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except for a reset interrupt, is shown below. Figure 4.3.1 Outline of the EIT Processing Procedure Instruction A PC BPC PSW (B)PSW EIT vector entry EIT handler except for SBI RTE instruction Program suspended and EIT request accepted Instruction processing-canceled type (RIE, AE) Instruction processing-completed type (EI, TRAP) Program execution restarted EIT request generated Hardware preprocessing BPC, PSW and general-purpose registers are saved to the stack Branch instruction General-purpose registers, PSW and BPC are restored from the stack Hardware postprocessing (SBI) Program terminated or system is reset User-created EIT handler (B)PSW PSW BPC PC Processing by handler Note 1: (B)PSW indicates the BPSW field for the PSW register. (Note 1) SBI (System Break Interrupt processing) Instruction B Instruction C Instruction C Instruction D

4-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 When an EIT is accepted, the CPU branches to the EIT vector after hardware preprocessing (as will be described later). The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction for the EIT handler (not the jump address itself) is written. In the hardware preprocessing, the content of the PC and PSW registers is transferred to the backup register (BPC register and BPSW field in the PSW register). Other necessary operations must be performed in the user-created EIT handler. These include saving the BPC register and PSW register (including the BPSW field) and the general-purpose registers to be used in the EIT handler to the stack. In addition, the accumulator must be saved to the stack as necessary. Remember that all these registers must be saved to the stack in a program by the user. When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute the RTE instruction. Control is thereby returned from the EIT processing to the program that was being executed when the EIT occurred. (This does not apply to the System Break Interrupt, however.) In the hardware postprocessing, the content of the backup register (BPC register and BPSW field in the PSW register) is returned to the PC and PSW registers. Note that the values stored in the BPC and the PSW register’s BPSW field after executing the RTE instruction are undefined.

4-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/Os. It also has the backup registers for the PC and PSW (the BPC register and the BPSW field in the PSW register). The EIT processing mechanism is shown below. Figure 4.4.1 EIT Processing Mechanism Interrupt controller (ICU) SBI EIInternal peripheral I/Os RESET# RI AE, RIE, TRAP IE flag (PSW) M32R CPU core SBI# Low High Priority SBI EI RI M32R/ECU PSW register PSWBPSW BPC register PC register

4-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 When an EIT event occurs, the CPU suspends the program it has hitherto been executing and branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are accepted are shown below. Table 4.5.1 Acceptance of EIT Events EIT Event Type of Processing Acceptance Timing Values Set in BPC Register Reserved Instruction Instruction processing- During instruction execution PC value of the instruction that Exception (RIE) canceled type generated RIE Address Exception (AE) Instruction processing- During instruction execution PC value of the instruction that canceled type generated AE Reset Interrupt (RI) Instruction processing- Each machine cycle Undefined value aborted type System Break Interrupt Instruction processing- Break in instructions PC value of the next instruction (SBI) completed type (word boundary only) External Interrupt (EI) Instruction processing- Break in instructions PC value of the next instruction completed type (word boundary only) Trap (TRAP) Instruction processing- Break in instructions PC value of TRAP instruction + 4 completed type The following describe operation of the microcomputer at the time when it accepts an EIT and when it executes the RTE instruction. (1) Hardware preprocessing when an EIT is accepted [1] Save the PSW register’s SM, IE and C bits in its backup field. BSM ← SM BIE ← IE BC ← C [2] Update the PSW register’s SM, IE and C bits SM ← Remains unchanged (RIE, AE, TRAP) or cleared to "0" (SBI, EI, RI) IE ← Cleared to "0" C ← Cleared to "0" [3] Save the PC register BPC ← PC [4] Set the vector address in the PC register Branches to the EIT vector and executes the branch (BRA) instruction written in it, thereby transferring control to the user-created EIT handler. (2) Hardware postprocessing when the RTE instruction is executed [A] Restore the PSW register’s SM, IE and C bits from its backup field. SM ← BSM IE ← BIE C ← BC [B] Restore the PC register from the BPC register. PC ← BPC Note: The values stored in the BPC and the PSW register’s BSM, BIE and BC bits after executing the RTE instruction are undefined.

4-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 [1] Saving the SM, IE and C bits BSM BIE BC SM IE C [2] Updating the SM, IE and C bits SM IE C Unchanged or 0 [3] Saving the PC BPC PC← [4] Setting the vector address in the PC PC Vector address← [B] Restoring the PC from the BPC register The value stored in the BPC register after executing the RTE instruction is undefined. [A] Restoring the SM, IE and C bits from the backup field SM IE C The values stored in the BSM, BIE and BC bits after executing the RTE instruction are undefined. BSM BIE BC [1] [A] [B] [2] [3] [4] Figure 4.6.1 Saving and Restoring the PC and PSW 16 17 23 24 25 31(LSB)15870(MSB) SM IE CBCBSM BIE 00000000000000000000000000PSW BPSW field PSW field

4-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The EIT vector entry is located in the user space beginning with the address H’0000 0000. The table below lists the EIT vector entry. Table 4.7.1 EIT Vector Entry Name Abbreviation Vector Address SM IE BPC Reset Interrupt RI H'0000 0000 (Note 1) 0 0 Undefined System Break SBI H'0000 0010 0 0 PC of the next instruction Interrupt Reserved Instruction RIE H'0000 0020 Unchanged 0 PC of the instruction that generated RIE Exception Address Exception AE H'0000 0030 Unchanged 0 PC of the instruction that generated AE Trap TRAP0 H'0000 0040 Unchanged 0 PC of TRAP instruction + 4 TRAP1 H'0000 0044 Unchanged 0 PC of TRAP instruction + 4 TRAP2 H'0000 0048 Unchanged 0 PC of TRAP instruction + 4 TRAP3 H'0000 004C Unchanged 0 PC of TRAP instruction + 4 TRAP4 H'0000 0050 Unchanged 0 PC of TRAP instruction + 4 TRAP5 H'0000 0054 Unchanged 0 PC of TRAP instruction + 4 TRAP6 H'0000 0058 Unchanged 0 PC of TRAP instruction + 4 TRAP7 H'0000 005C Unchanged 0 PC of TRAP instruction + 4 TRAP8 H'0000 0060 Unchanged 0 PC of TRAP instruction + 4 TRAP9 H'0000 0064 Unchanged 0 PC of TRAP instruction + 4 TRAP10 H'0000 0068 Unchanged 0 PC of TRAP instruction + 4 TRAP11 H'0000 006C Unchanged 0 PC of TRAP instruction + 4 TRAP12 H'0000 0070 Unchanged 0 PC of TRAP instruction + 4 TRAP13 H'0000 0074 Unchanged 0 PC of TRAP instruction + 4 TRAP14 H'0000 0078 Unchanged 0 PC of TRAP instruction + 4 TRAP15 H'0000 007C Unchanged 0 PC of TRAP instruction + 4 External Interrupt EI H'0000 0080 (Note 2) 0 0 PC of the next instruction Note 1: During boot mode, the CPU starts executing the boot program after exiting the reset state. For details, see Section 6.5, “Programming the Internal Flash Memory.” Note 2: During flash E/W enable mode, this vector address is moved to the beginning of the internal RAM (address H’0080 4000). For details, see Section 6.5, “Programming the Internal Flash Memory.”

4-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

4.8.1 Reserved Instruction Exception (RIE)

[Occurrence Conditions] Reserved Instruction Exception (RIE) occurs when a reserved instruction (unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a reserved instruction exception occurs, the instruction that generated it is not executed. If an external interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved instruction exception that is accepted. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC The PC value of the instruction that generated the reserved instruction exception is set in the BPC regis- ter. For example, if the instruction that generated the reserved instruction exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction that generated the reserved instruction exception is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC[30] = 0) or not on a word boundary (BPC[30] = 1). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.) Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE) H'00 Address RIE occurredH'04 H'08 H'0C +0 +1 +2 +3 H'00 Address RIE occurredH'04 H'08 H'0C +0 +1 +2 +3 Return address BPC H'06BPC H'04 Return address

4-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0020 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0020 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from a word-boundary instruction including the instruction that generated a RIE (see Figure 4.8.1). Except when using reserved instruction exceptions intentionally, occurrence of a reserved instruction exception suggests that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the reserved instruction exception handler to the program that was being executed when the exception occurred.

4-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 4.8.2 Example of a Return Address for Address Exception (AE) H'00 Address AE occurredH'04 H'08 H'0C +0 +1 +2 +3 H'00 Address AE occurredH'04 H'08 H'0C +0 +1 +2 +3 BPC H'06BPC H'04 Return address Return address

4.8.2 Address Exception (AE)

[Occurrence Conditions] Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions. The following lists the combination of instructions and accessed addresses that may cause address exceptions to occur. Two low-order address bits accessed in the LDH, LDUH or STH instruction are ‘01’ or ‘11’ Two low-order address bits accessed in the LD, ST, LOCK or UNLOCK instruction are ‘01,’ ‘10’ or ‘11’ When an address exception occurs, memory access by the instruction that generated the exception is not performed. If an external interrupt is requested at the same time an address exception is detected, it is the address exception that is accepted. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC The PC value of the instruction that generated the address exception is set in the BPC register. For example, if the instruction that generated the address exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction that generated the address exception is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC[30] = 0) or not on a word boundary (BPC[30] = 1). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.)

4-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0030 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0030 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from a word-boundary instruction including the instruction that generated an AE (see Figure 4.8.2). Except when using address exceptions intentionally, occurrence of an address exception suggests that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the address exception handler to the program that was being executed when the exception occurred.

4-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

4.9.1 Reset Interrupt (RI)

[Occurrence Conditions] A reset interrupt is accepted in machine cycle by pulling the RESET# input signal "L." The reset interrupt is assigned the highest priority among all EITs. [EIT Processing] (1) Initializing SM, IE and C bits The PSW register’s SM, IE and C bits are initialized as shown below. SM ← 0 IE ← 0 C ← 0 For the reset interrupt, the values of BSM, BIE and BC bits are undefined. (2) Branching to the EIT vector entry The CPU branches to the address H’0000 0000 in the user space. However, when operating in boot mode, the CPU jumps to the boot program. For details, see Section 6.5, “Programming the Internal Flash Memory.” (3) Jumping from the EIT vector entry to the user program The CPU executes the instruction written by the user at the address H’0000 0000 of the EIT vector entry. In the reset vector entry, be sure to initialize the PSW and SPI registers before jumping to the start address of the user program.

4-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

4.9.2 System Break Interrupt (SBI)

System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt cannot be masked by the PSW register IE bit. Therefore, the system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred. [Occurrence Conditions] A system break interrupt is accepted by a falling edge on SBI# input pin. (The system break interrupt cannot be masked by the PSW register IE bit.) In no case will a system break interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immedi- ately after branching.) Note also that because of the instruction processing-completed type, a system break interrupt is accepted after the instruction is completed. Order in which instructions are executed 32-bit instruction Address 1000 Address 1002 Address 1004 Address 1008 Interrupt may be accepted Interrupt cannot be accepted 16-bit instruction Interrupt may be accepted Interrupt may be accepted Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted

4-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving the PC The content of the PC register (always on word boundary) is saved to the BPC register. If the interrupt was detected in a branch instruction, then the next instruction is one that exists at the jump address. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0010 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0010 of the EIT vector entry to jump to the start address of the user-created handler. The system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break inter- rupt occurred.

4-1732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 4.9.2 Timing at Which External Interrupt (EI) is Accepted

4.9.3 External Interrupt (EI)

An external interrupt is generated upon an interrupt request which is output by the microcomputer’s internal interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority levels. For details, see Chapter 5, “Interrupt Controller.” For details about the interrupt request sources, see each section in which the relevant internal peripheral I/O is described. [Occurrence Conditions] External interrupts are managed by the microcomputer’s internal interrupt controller based on interrupt requests from each internal peripheral I/O, and are sent to the CPU via the interrupt controller. The CPU checks these interrupt requests at a break in instructions residing on word boundaries, and when an interrupt request is detected and the PSW register IE flag = "1", accepts it as an external interrupt. In no case will an external interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately after branching.) Order in which instructions are executed 32-bit instruction Address 1000 Address 1002 Address 1004 Address 1008 Interrupt may be accepted Interrupt cannot be accepted 16-bit instruction Interrupt may be accepted Interrupt may be accepted

4-1832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving the PC The content of the PC register (always on word boundary) is saved to the BPC register. (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0080 in the user space. However, when operating in flash E/W enable mode, the CPU goes to the beginning of the internal RAM (address H’0080 4000). (For details, see Section 6.5, “Programming the Internal Flash Memory.”) This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0080 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed.

4-1932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 4.10.1 Example of a Return Address for Trap (TRAP) H'00 Address H'04 H'08 H'0C +0 +1 +2 +3 H'00 Address H'04 H'08 H'0C +0 +1 +2 +3 BPC H'0ABPC H'08 TRAP instruction Return address Return address TRAP instruction

4.10.1 Trap

[Occurrence Conditions] Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen traps are generated, each corresponding to one of TRAP instruction operands 0–15. Accordingly, sixteen vector entries are provided. [EIT Processing] (1) Saving SM, IE and C bits The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE and C bits The PSW register’s SM, IE and C bits are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC When the trap instruction is executed, the PC value of TRAP instruction + 4 is set in the BPC register. For example, if the TRAP instruction is located at address 4, the value H’08 is set in the BPC register. Similarly, if the TRAP instruction is located at address 6, the value H’0A is set in the BPC register. The value of the BPC register bit 30 indicates whether the trap instruction resides on a word boundary (BPC register 30 = "0") or not on a word boundary (BPC register 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 8. (This is because the 2 low-order address bits are cleared to ‘00’ when returned to the PC.)

4-2032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (4) Branching to the EIT vector entry The CPU branches to the addresses H’0000 0040–H’0000 007C in the user space. This is the last opera- tion performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the addresses H’0000 0040–H’0000 007C of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user- created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed.

4-2132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The table below lists the priority levels of EIT events. When two or more EITs occur simultaneously, the event with the highest priority is accepted first. Table 4.11.1 Priority of EIT Events and How Returned from EIT Priority EIT Event Type of Processing Values Set in BPC Register 1 (Highest) Reset Interrupt (RI) Instruction processing-aborted type Undefined

2 Address Exception (AE) Instruction processing-canceled type PC of the instruction that

Reserved Instruction Instruction processing-canceled type PC of the instruction that Exception (RIE) generated RIE Trap (TRAP) Instruction processing-completed type TRAP instruction + 4

3 System Break Interrupt Instruction processing-completed type PC of the next instruction

(SBI)

4 External Interrupt (EI) Instruction processing-completed type PC of the next instruction

Note that for External Interrupt (EI), the priority levels of interrupt requests from each peripheral I/O are set by the microcomputer’s internal interrupt controller. For details, see Chapter 5, “Interrupt Controller.”

4-2232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (1) When RIE, AE, SBI, EI or TRAP occurs singly Figure 4.12.1 Processing of Events When RIE, AE, SBI, EI or TRAP Occurs Singly (2) When RIE, AE or TRAP and EI occur simultaneously Figure 4.12.2 Processing of Events When RIE, AE or TRAP and EI Occur Simultaneously RTE instruction IE = 0 RIE, AE or TRAP is accepted first. BPC register = Return address AIE = 1 RIE, AE or TRAP and EI occur simultaneously Return address A: IE = 1 IE = 0 IE = 1 RTE instruction : EIT handler EI is accepted next. BPC register = Return address A RTE instruction IE = 0 IE = 1 BPC register = Return address A IE = 1 RIE, AE, SBI, EI or TRAP occurs singly Return address A: If IE = 0, no events but reset and SBI are accepted. : EIT handler

4-2332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 4.12.3 Example of EIT Processing BRA instruction RTE EIT handler EIT vector entry Program being executed Save BPC to the stack Save PSW to the stack Save general-purpose registers to the stack Processing by EIT handler Restore general-purpose registers from the stack Restore PSW from the stack Restore BPC from the stack EIT event occurs (SBI) System Break Interrupt (SBI) processing Program terminated or system reset (Other than SBI) PC BPC PSW (B)PSWHardware preprocessing Hardware postprocessing (B)PSW PSW BPC PC (Note 1) (Note 1) Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields.

4-2432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The Address Exception (AE) requires caution because if one of the instructions that use “register indirect + register update” addressing mode (following three) generates an address exception when it is executed, the values of the registers to be automatically updated (Rsrc and Rsrc2) become undefined. Except that the values of Rsrc and Rsrc2 become undefined, these instructions behave the same way as when used in other addressing modes. Applicable instructions LD Rdest, @Rsrc+ ST Rsrc1, @-Rsrc2 ST Rsrc1, @+Rsrc2 If the above case applies, consider the fact that the register values become undefined when you design the processing to be performed after executing said instructions. (If an address exception occurs, it means that the system has some fatal fault already existing in it. Therefore, address exceptions must be used on condition that control will not be returned from the address exception handler to the program that was being executed when the exception occurred.)

INTERRUPT CONTROLLER (ICU)

5.1 Outline of the Interrupt Controller

5.2 ICU Related Registers

5.3 Interrupt Request Sources in Internal

5.4 ICU Vector Table

5.5 Description of Interrupt Operation

5.6 Description of System Break Interrupt (SBI)

INTERRUPT CONTROLLER (ICU) 5-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are sent to the M32R CPU as external interrupts (EI). The maskable interrupts from internal peripheral I/Os are managed by assigning them one of eight priority levels including an interrupt-disabled state. If two or more interrupt requests with the same priority level occur at the same time, their priorities are resolved by predetermined hardware priority. The source of an interrupt request generated in internal peripheral I/Os is identified by reading the relevant interrupt status register provided for internal peripheral I/Os. On the other hand, the system break interrupt (SBI) is recognized when a falling edge occurs on the SBI# signal input pin. This interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer, so that it is always accepted irrespective of the PSW register IE bit status. After processing of an SBI, shut down or reset the system without returning to the program that was being executed when the interrupt occurred. Specifications of the Interrupt Controller are outlined below. Table 5.1.1 Outline of the Interrupt Controller (ICU) Item Specification Interrupt request source Maskable interrupt requests from internal peripheral I/Os: 23 sources (Note 1) System break interrupt request: 1 source (input from SBI# pin) Priority management 8 priority levels including an interrupt-disabled state (However, interrupts with the same priority level have their priorities resolved by fixed hardware priority.) Note 1: This is the number of interrupt requests divided into groups. There are actually a total of 123 interrupt request sources when counted individually.

INTERRUPT CONTROLLER (ICU) 5-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 NEW_IMASK ILEVEL SBI# EI SBI SBIREQ IREQ IREQ IREQ IREQ IREQ IREQ Interrupt Vector Register (IVECT) Interrupt Request Mask Register (IMASK) External Interrupt (EI) request generated (maskable) IMASK compari- son System Break Interrupt (SBI) request generated (nonmaskable) Interrupt Controller (ICU) Interrupt Control Register SBI Control Register (SBICR) To the CPU core To the CPU core Priority resolved by interrupt priority levels set Priority resolved by fixed hardware priority Peripheral circuits Interrupt control circuit Interrupt request Interrupt request Interrupt request Interrupt control circuit Interrupt control circuit Edge Edge Edge Level Level Level (Note 1) Note 1. Interrupt control circuit indicates Interrupt request status register and Interrupt request mask register in each peripheral function. Figure 5.1.1 Block Diagram of the Interrupt Controller

INTERRUPT CONTROLLER (ICU) 5-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The diagram below shows a register map associated with the Interrupt Controller (ICU). ICU Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0000 Interrupt Vector Register 5-5 (IVECT) H'0080 0002 (Use inhibited area) H'0080 0004 Interrupt Request Mask Register (Use inhibited area) 5-6 (IMASK) H'0080 0006 SBI Control Register (Use inhibited area) 5-7 (SBICR) (Use inhibited area) H'0080 0060 CAN0 Transmit/Receive & Error Interrupt Control Register (Use inhibited area) 5-8 (ICAN0CR) H'0080 0062 (Use inhibited area) H'0080 0064 (Use inhibited area) H'0080 0066 (Use inhibited area) RTD Interrupt Control Register 5-8 (IRTDCR) H'0080 0068 SIO2,3 Transmit/Receive Interrupt Control Register DMA5–9 Interrupt Control Register 5-8 (ISIO23CR) (IDMA59CR) H'0080 006A (Use inhibited area) H'0080 006C A/D0 Conversion Interrupt Control Register SIO0 Transmit Interrupt Control Register 5-8 (IAD0CCR) (ISIO0TXCR) H'0080 006E SIO0 Receive Interrupt Control Register SIO1 Transmit Interrupt Control Register 5-8 (ISIO0RXCR) (ISIO1TXCR) H'0080 0070 SIO1 Receive Interrupt Control Register DMA0–4 Interrupt Control Register 5-8 (ISIO1RXCR) (IDMA04CR) H'0080 0072 MJT Output Interrupt Control Register 0 MJT Output Interrupt Control Register 1 5-8 (IMJTOCR0) (IMJTOCR1) H'0080 0074 MJT Output Interrupt Control Register 2 MJT Output Interrupt Control Register 3 5-8 (IMJTOCR2) (IMJTOCR3) H'0080 0076 MJT Output Interrupt Control Register 4 MJT Output Interrupt Control Register 5 5-8 (IMJTOCR4) (IMJTOCR5) H'0080 0078 MJT Output Interrupt Control Register 6 MJT Output Interrupt Control Register 7 5-8 (IMJTOCR6) (IMJTOCR7) H'0080 007A (Use inhibited area) MJT Input Interrupt Control Register 1 5-8 (IMJTICR1) H'0080 007C MJT Input Interrupt Control Register 2 MJT Input Interrupt Control Register 3 5-8 (IMJTICR2) (IMJTICR3) H'0080 007E MJT Input Interrupt Control Register 4 CAN1 Transmit/Receive & Error Interrupt Control Register 5-8 (IMJTICR4) (ICAN1CR)

INTERRUPT CONTROLLER (ICU) 5-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

5.2.1 Interrupt Vector Register

Interrupt Vector Register (IVECT) <Address: H’0080 0000> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 IVECT <Upon exiting reset: Undefined> b Bit Name Function R W 0-15 IVECT When an interrupt request is accepted, the 16-low-order R N 16 low-order bits of ICU vector table addressbits of the ICU vector table address for the accepted interrupt request source are stored in this register. Note: This register must always be accessed in halfwords (2 bytes). (This is a read-only register.) The Interrupt Vector Register (IVECT) is used when an interrupt request is accepted to store the 16-low-order bits of the ICU vector table address for the accepted interrupt request source. Before this function can work, the ICU vector table (addresses H’0000 0094 through H’0000 0113) must have set in it the start addresses of interrupt handlers for each internal peripheral I/O. When an interrupt request is accepted, the 16-low-order bits of the ICU vector table address for the accepted interrupt request source are stored in the IVECT register. In the EIT handler, read the content of this IVECT register using the LDH instruc- tion to get the ICU vector table address. When the IVECT register is read, operations (1) to (4) below are automatically performed in hardware. (1) The interrupt priority level (ILEVEL) of the accepted interrupt request source is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.) (2) The interrupt request bit for the accepted interrupt request source is cleared (not cleared for level-recog- nized interrupt request sources). (3) The interrupt request (EI) to the CPU core is deasserted. (4) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Notes: Do not read the Interrupt Vector Register (IVECT) in the EIT handler unless interrupts are dis- abled (PSW register IE bit = "0"). In the EIT handler, furthermore, read the Interrupt Request Mask Register (IMASK) first before reading the IVECT register. To reenable interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register (IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts. (The ICU vector table readout in the EI handler processing example in Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O is an access to the internal ROM and, there- fore, does not require adding a dummy access.)

INTERRUPT CONTROLLER (ICU) 5-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

5.2.2 Interrupt Request Mask Register

Interrupt Request Mask Register (IMASK) <Address: H’0080 0004> 123456 b 7b0 IMASK 1110 0 0 0 0 <Upon exiting reset: H’07> b Bit Name Function R W 0–4 No function assigned. Fix to "0" 00 5–7 IMASK 000: Disable maskable interrupts R W Interrupt request mask bit 001: Accept interrupts with priority level 0 010: Accept interrupts with priority levels 0–1 011: Accept interrupts with priority levels 0–2 100: Accept interrupts with priority levels 0–3 101: Accept interrupts with priority levels 0–4 110: Accept interrupts with priority levels 0–5 111: Accept interrupts with priority levels 0–6 The Interrupt Request Mask Register (IMASK) is used to finally determine whether or not to accept an interrupt request after comparing its priority with the priority levels (Interrupt Control Register ILEVEL bits) that have been set for each interrupt request source. When the Interrupt Vector Register (IVECT) described above is read, the interrupt priority level of the accepted interrupt request source is set in this IMASK register as a new mask value. When any value is written to the IMASK register, operations (1) to (2) below are automatically performed in hardware. (1) The interrupt request (EI) to the CPU core is deasserted. (2) The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Notes: Do not write to the Interrupt Request Mask Register (IMASK) unless interrupts are disabled (PSW register IE bit = "0"). To reenable interrupts (by setting the IE bit to "1") after writing to the Interrupt Request Mask Register (IMASK), perform a dummy access to the internal memory, etc. before reenabling inter- rupts. (1) Write to the Interrupt Request Mask Register (IMASK) (2) Perform a dummy access to the internal memory and SFR once or more (3) Issue one or more instructions (Note 1) (4) Enable interrupts (by setting the IE bit to "1") Note 1: Any instructions other than NOP that does not require clock cycles (one that is automati- cally inserted by the assembler for alignment adjustment: instruction code H'F000).

INTERRUPT CONTROLLER (ICU) 5-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

5.2.3 SBI (System Break Interrupt) Control Register

SBI (System Break Interrupt) Control Register (SBICR) <Address: H’0080 0006> 123456 b 7b0 SBIREQ 00 0 0 0 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 0–6 No function assigned. Fix to "0" 00

7 SBIREQ 0: SBI not requested R (Note 1)

SBI request bit 1: SBI requested Note 1: This bit can only be cleared (see below) The System Break Interrupt (SBI) is an interrupt request generated by a falling edge on the SBI# signal input pin. When a falling edge on the SBI# signal input pin is detected and this bit is set to "1", a system break interrupt (SBI) request is generated to the CPU. This bit cannot be set to "1" in software, it can only be cleared. To clear this bit to "0", follow the procedure described below. 1. Write "1" to the SBI request bit. 2. Write "0" to the SBI request bit. Notes: Unless this bit is set to "1", do not perform the above clearing operation. If falling edge is inputted to SBI# pin again, system break is not occurred while SBI request bit is set to "1."

INTERRUPT CONTROLLER (ICU) 5-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

5.2.4 Interrupt Control Registers

CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) <Address: H’0080 0060> RTD Interrupt Control Register (IRTDCR) <Address: H’0080 0067> SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) <Address: H’0080 0068> DMA5–9 Interrupt Control Register (IDMA59CR) <Address: H’0080 0069> A/D0 Conversion Interrupt Control Register (IAD0CCR) <Address: H’0080 006C> SIO0 Transmit Interrupt Control Register (ISIO0TXCR) <Address: H’0080 006D> SIO0 Receive Interrupt Control Register (ISIO0RXCR) <Address: H’0080 006E> SIO1 Transmit Interrupt Control Register (ISIO1TXCR) <Address: H’0080 006F> SIO1 Receive Interrupt Control Register (ISIO1RXCR) <Address: H’0080 0070> DMA0–4 Interrupt Control Register (IDMA04CR) <Address: H’0080 0071> MJT Output Interrupt Control Register 0 (IMJTOCR0) <Address: H’0080 0072> MJT Output Interrupt Control Register 1 (IMJTOCR1) <Address: H’0080 0073> MJT Output Interrupt Control Register 2 (IMJTOCR2) <Address: H’0080 0074> MJT Output Interrupt Control Register 3 (IMJTOCR3) <Address: H’0080 0075> MJT Output Interrupt Control Register 4 (IMJTOCR4) <Address: H’0080 0076> MJT Output Interrupt Control Register 5 (IMJTOCR5) <Address: H’0080 0077> MJT Output Interrupt Control Register 6 (IMJTOCR6) <Address: H’0080 0078> MJT Output Interrupt Control Register 7 (IMJTOCR7) <Address: H’0080 0079> MJT Input Interrupt Control Register 1 (IMJTICR1) <Address: H’0080 007B> MJT Input Interrupt Control Register 2 (IMJTICR2) <Address: H’0080 007C> MJT Input Interrupt Control Register 3 (IMJTICR3) <Address: H’0080 007D> MJT Input Interrupt Control Register 4 (IMJTICR4) <Address: H’0080 007E> CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR) <Address: H’0080 007F>

INTERRUPT CONTROLLER (ICU) 5-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 9 1 01 11 21 31 4 b 1 5 )(b8 123456 b 7b0 ILEVELIREQ 0 1110 0 0 0 <Upon exiting reset: H’07> b Bit Name Function R W 0–2 No function assigned. Fix to "0" 00 (8–10)

3 IREQ <Edge recognized type> R W

(11) Interrupt request bit At read 0: Interrupt not requested 1: Interrupt requested At write 0: Clear interrupt request 1: Generate interrupt request <Level-recognized type> R 0 At read 0: Interrupt not requested 1: Interrupt requested 4 No function assigned. Fix to "0" 00 (12) 5–7 ILEVEL 000: Interrupt priority level 0 R W (13–15) Interrupt priority level bits 001: Interrupt priority level 1 010: Interrupt priority level 2 011: Interrupt priority level 3 100: Interrupt priority level 4 101: Interrupt priority level 5 110: Interrupt priority level 6 111: Interrupt priority level 7 (interrupt disabled) (1) IREQ (Interrupt Request) bit (Bit 3 or 11) When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Request) bit is set to "1." This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for level-recognized interrupt request sources). Also, when this bit is set by an edge-recognized interrupt re- quest generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not cleared in the case of level-recognized interrupt request). If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Register (IVECT) at the same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority. Note: External Interrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External Interrupt (EI) to the CPU core can only be deasserted by the following operation: (1) Reset (2) IVECT register read (3) Write to the IMASK register

INTERRUPT CONTROLLER (ICU) 5-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) ILEVEL (Interrupt Priority Level) (Bits 5–7 or bits 13–15) These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set these bits to ‘111’ to disable or any value ‘000’ through ‘110’ to enable the interrupt from some internal peripheral I/O. When an interrupt occurs, the Interrupt Controller resolves priority between this interrupt and other interrupt sources based on ILEVEL settings and finally compares priority with the IMASK value to determine whether to forward an EI request to the CPU or keep the interrupt request pending. The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts are accepted. Table 5.2.1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 (ILEVEL = "000") Accepted when IMASK is 1–7 1 (ILEVEL = "001") Accepted when IMASK is 2–7 2 (ILEVEL = "010") Accepted when IMASK is 3–7 3 (ILEVEL = "011") Accepted when IMASK is 4–7 4 (ILEVEL = "100") Accepted when IMASK is 5–7 5 (ILEVEL = "101") Accepted when IMASK is 6–7 6 (ILEVEL = "110") Accepted when IMASK is 7 7 (ILEVEL = "111") Not accepted (interrupts disabled) Figure 5.2.1 Configuration of the Interrupt Control Register (Edge-recognized Type) Interrupt request from each internal peripheral I/O Interrupt enabled ILEVEL (levels 0-7) Data bus b5-7 or b13-15 F/F Set Set/clear IREQ Interrupt priority resolving circuit F/F Reset IVECT read IMASK write Clear To the CPU core b3 or b11 Set EI Interrupt request from each group internal peripheral I/O Interrupt enabled b3 or b11Data bus b5-7 or b13-15 Read IREQ Read-only circuit ILEVEL (levels 0-7) Group interrupt Interrupt priority resolving circuit F/F Clear To the CPU coreSet EI Reset IVECT read IMASK write Figure 5.2.2 Configuration of the Interrupt Control Register (Level-recognized Type)

INTERRUPT CONTROLLER (ICU) 5-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

5.3 Interrupt Request Sources in Internal Peripheral I/O

The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial interface, A/D converter, RTD and CAN. For details about these interrupts, see each section in which the relevant internal peripheral I/O is described. Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O Interrupt Request Sources Contents Number of ICU Type of Input Input Sources Source ( Note 1) A/D0 conversion interrupt request A/D0 converter’s scan mode one-shot operation, 1 Edge-recognized single mode or comparate mode completed SIO0 transmit interrupt request SIO0 transmission-completed or transmit buffer empty interrupt 1 Edge-recognized SIO0 receive interrupt request SIO0 reception-completed or receive error interrupt 1 Edge-recognized SIO1 transmit interrupt request SIO1 transmission-completed or transmit buffer empty interrupt 1 Edge-recognized SIO1 receive interrupt request SIO1 reception-completed or receive error interrupt 1 Edge-recognized SIO2,3 transmit/receive interrupt SIO2,3 reception-completed or receive error interrupt, 4 Level-recognized request transmission-completed or transmit buffer empty interrupt RTD interrupt request RTD interrupt generation command 1 Edge-recognized DMA transfer interrupt request 0 DMA0–4 transfer completed 5 Level-recognized DMA transfer interrupt request 1 DMA5–9 transfer completed 5 Level-recognized CAN0 transmit/receive & errorCAN0 transmission or reception completed, CAN0 errorpassive, 35 Level-recognized interrupt request CAN0 error bus-off, CAN0 bus error, CAN0 single shot CAN1 transmit/receive & errorCAN1 transmission or reception completed, CAN1 error passive,35 Level-recognized interrupt request CAN1 error bus-off, CAN1 bus error, CAN1 single shot MJT output interrupt request 7 MJT output interrupt rgroup 7 (TMS0, TMS1 output) 2 Level-recognized MJT output interrupt request 6 MJT output interrupt rgroup 6 (TOP8, TOP9 output) 2 Level-recognized MJT output interrupt request 5 MJT output interrupt rgroup 5 (TOP10 output) 1 Edge-recognized MJT output interrupt request 4 MJT output interrupt rgroup 4 (TIO4–TIO7 outputs) 4 Level-recognized MJT output interrupt request 3 MJT output interrupt rgroup 3 (TIO8, TIO9 outputs) 2 Level-recognized MJT output interrupt request 2 MJT output interrupt rgroup 2 (TOP0–TOP5 outputs) 6 Level-recognized MJT output interrupt request 1 MJT output interrupt rgroup 1 (TOP6,TOP7 outputs) 2 Level-recognized MJT output interrupt request 0 MJT output interrupt rgroup 0 (TIO0–TIO3 outputs) 4 Level-recognized MJT input interrupt request 4 MJT input interrupt group 4 (TIN3 input) 1 Level-recognized MJT input interrupt request 3 MJT input interrupt group 3 (TIN20–TIN23 inputs) 4 Level-recognized MJT input interrupt request 2 MJT input interrupt group 2 (TIN16–TIN19 inputs) 4 Level-recognized MJT input interrupt request 1 MJT input interrupt group 1 (TIN0 input) 1 Level-recognized Note 1: ICU type of input source Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU. Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held low. For this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software.

INTERRUPT CONTROLLER (ICU) 5-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The 23-source interrupt requests are assigned the following vector table addresses. Table 5.4.1 ICU Vector Table Addresses Priority Interrupt Request Source ICU Vector Table Addresses Number of Input Source Input Source Type (Note 1) High MJT input interrupt 4 (TIN3 input) H'0000 0094 – H'0000 0097 1 Level-recognized MJT input interrupt 3 (TIN20–23 input) H'0000 0098 – H'0000 009B 4 Level-recognized MJT input interrupt 2 (TIN16–19 input) H'0000 009C – H'0000 009F 4 Level-recognized MJT input interrupt 1 (TIN0 input) H'0000 00A0 – H'0000 00A3 1 Level-recognized MJT output interrupt 7 (TMS0,1 output) H'0000 00A8 – H'0000 00AB 2 Level-recognized MJT output interrupt 6 (TOP8,9 output) H'0000 00AC–H'0000 00AF 2 Level-recognized MJT output interrupt 5 (TOP10 output) H'0000 00B0 – H'0000 00B3 1 Edge-recognized MJT output interrupt 4 (TIO4–7 output) H'0000 00B4 – H'0000 00B7 4 Level-recognized MJT output interrupt 3 (TIO8,9 output) H'0000 00B8 – H'0000 00BB 2 Level-recognized MJT output interrupt 2 (TOP0–5 output) H'0000 00BC – H'0000 00BF 6 Level-recognized MJT output interrupt 1 (TOP6,7 output) H'0000 00C0 – H'0000 00C3 2 Level-recognized MJT output interrupt 0 (TIO0–3 output) H'0000 00C4 – H'0000 00C7 4 Level-recognized DMA0–4 interrupt H'0000 00C8 – H'0000 00CB 5 Level-recognized SIO1 receive interrupt H'0000 00CC – H'0000 00CF 1 Edge-recognized SIO1 transmit interrupt H'0000 00D0 – H'0000 00D3 1 Edge-recognized SIO0 receive interrupt H'0000 00D4 – H'0000 00D7 1 Edge-recognized SIO0 transmit interrupt H'0000 00D8 – H'0000 00DB 1 Edge-recognized A/D0 conversion interrupt H'0000 00DC – H'0000 00DF 1 Edge-recognized DMA5–9 interrupt H'0000 00E8 – H'0000 00EB 5 Level-recognized SIO2,3 transmit/receive interrupt H'0000 00EC – H'0000 00EF 4 Level-recognized RTD interrupt H'0000 00F0 – H'0000 00F3 1 Edge-recognized CAN0 transmit/receive & error interrupt H'0000 010C – H'0000 010F 35 Level-recognized Low CAN1 transmit/receive & error interrupt H'0000 0110 – H'0000 0113 35 Level-recognized Note 1: ICU type of input source Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU. Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held low. For this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software.

INTERRUPT CONTROLLER (ICU) 5-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 5.5.1 Example of Priority Resolution when Accepting Interrupt Requests

5.5.1 Acceptance of Internal Peripheral I/O Interrupts

An interrupt request from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set in the Interrupt Control Register and the IMASK value of the Interrupt Request Mask Register. If its priority is higher than the IMASK value, the interrupt request is accepted. However, if two or more interrupt requests occur simultaneously, the Interrupt Controller resolves priority between these interrupt requests fol- lowing the procedure described below. 1) The ILEVEL values set in the Interrupt Control Registers for the respective internal peripheral I/Os are compared with each other. 2) If the ILEVEL values are the same, priorities are resolved according to the predetermined hardware priority. 3) The ILEVEL and IMASK values are compared. If two or more interrupt requests occur simultaneously, the Interrupt Controller first compares their priority levels set in each Interrupt Control Register’s ILEVEL bit to select an interrupt request that has the highest priority. If the interrupt requests have the same ILEVEL value, their priorities are resolved according to the hardware fixed priority. The interrupt request thus selected has its ILEVEL value compared with the IMASK value and if its priority is higher than the IMASK value, the Interrupt Controller sends an EI request to the CPU. Interrupt requests may be masked by setting the Interrupt Request Mask Register and the Interrupt Control Register’s ILEVEL bit (disabled at level 7) provided for each internal peripheral I/O and the PSW register IE bit. Level (ILEVEL) Resolve priority according to hardware priority Compare with IMASK value MJT input interrupt request 4 MJT output interrupt request 3 MJT output interrupt request 2 MJT output interrupt request 1 DMA0-4 interrupt request A/D0 conversion interrupt request (ILEVEL settings) Level 3 Level 4 Level 5 Level 3 Level 1 Level 3 Not requested Requested Requested Requested Requested Requested Hardware fixed priority Accept interrupt if PSW register IE bit = 1 Level 3 Level 3 Level 3 Can be accepted when IMASK = 4-7 1) 2) 3)

INTERRUPT CONTROLLER (ICU) 5-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 5.5.1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 (ILEVEL = "000") Accepted when IMASK is 1–7 1 (ILEVEL = "001") Accepted when IMASK is 2–7 2 (ILEVEL = "010") Accepted when IMASK is 3–7 3 (ILEVEL = "011") Accepted when IMASK is 4–7 4 (ILEVEL = "100") Accepted when IMASK is 5–7 5 (ILEVEL = "101") Accepted when IMASK is 6–7 6 (ILEVEL = "110") Accepted when IMASK is 7 7 (ILEVEL = "111") Not accepted (interrupts disabled)

INTERRUPT CONTROLLER (ICU) 5-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers

(1) Branching to the interrupt handler Upon accepting an interrupt request, the CPU branches to the EIT vector entry after performing the hard- ware preprocessing as described in Section 4.3, “EIT Processing Procedure.” The EIT vector entry for External Interrupt (EI) is located at the address H’0000 0080. This address is where the instruction (not the jump address itself) for branching to the beginning of the interrupt handler routine for external interrupt requests is written. (2) Processing in the External Interrupt (EI) handler A typical operation of the External Interrupt (EI) handler (for interrupts from internal peripheral I/O) is shown in Figure 5.5.2. [1] Saving each register to the stack Save the BPC, PSW and general-purpose registers to the stack. Also, save the accumulator as neces- sary. [2] Reading the Interrupt Request Mask Register (IMASK) and saving to the stack Read the Interrupt Request Mask Register and save its content to the stack. [3] Reading the Interrupt Vector Register (IVECT) Read the Interrupt Vector Register. This register holds the 16 low-order address bits of the ICU vector table for the accepted interrupt request source that was stored in it when accepting an interrupt request. When the Interrupt Vector Register is read, the following processing is automatically performed in hardware: The interrupt priority level of the accepted interrupt request (ILEVEL) is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.) The accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources). The interrupt request (EI) to the CPU core is dropped. The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). [4] Reading and overwriting the Interrupt Request Mask Register (IMASK) Read the Interrupt Request Mask Register and overwrite it with the read value. This write to the IMASK register causes the following processing to be automatically performed in hardware: The interrupt request (EI) to the CPU core is dropped. The ICU’s internal sequencer is activated to start internal processing (interrupt priority resolution). Note: Processing in [4] here is unnecessary when multiple interrupts are to be enabled in [6] below. [5] Reading the ICU vector table Read the ICU vector table for the accepted interrupt request source. The relevant ICU vector table address can be obtained by zero-extending the content of the Interrupt Vector Register that was read in [3] (i.e., the 16 low-order address bits of the ICU vector table for the accepted interrupt request source). The ICU vector table must have set in it the start address of the interrupt handler for the interrupt request source concerned.) [6] Enabling multiple interrupts To enable another higher priority interrupt while processing the accepted interrupt (i.e., enabling mul- tiple interrupts), set the PSW register IE bit to "1". Note: There are precautions to be take when reenabling interrupts (by setting the IE bit to "1") after writing the Interrupt Mask Register (IMASK). For details, see the Section 5.2.2, "Interrupt MASK Register."

INTERRUPT CONTROLLER (ICU) 5-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 [7] Branching to the internal peripheral I/O interrupt handler Branch to the start address of the interrupt handler that was read out in [5]. [8] Processing in the internal peripheral I/O interrupt handler [9] Disabling interrupts Clear the PSW register IE bit to "0" to disable interrupts. [10] Restoring the Interrupt Request Mask Register (IMASK) Restore the Interrupt Request Mask Register that was saved to the stack in [2]. [11] Restoring registers from the stack Restore the registers that were saved to the stack in [1]. [12] Completion of external interrupt processing Execute the RTE instruction to complete the external interrupt processing. The program returns to the state in which it was before the currently processed interrupt request was accepted. (3) Identifying the source of the interrupt request generated If any internal peripheral I/O has two or more interrupt request sources, check the Interrupt Request Status Register provided for each internal peripheral I/O to identify the source of the interrupt request generated. (4) Enabling multiple interrupts To enable multiple interrupts in the interrupt handler, set the PSW register IE (Interrupt Enable) bit to enable interrupt requests to be accepted. However, before writing "1" to the IE bit, be sure to save each register (BPC, PSW, general-purpose registers and IMASK) to the stack. Note: Before enabling multiple interrupts, read the Interrupt Vector Register (IVECT) and then the ICU vector table, as shown in Figure 5.5.2, “Typical Handler Operation for Interrupts from Internal Peripheral I/O.”

INTERRUPT CONTROLLER (ICU) 5-1732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O Note 1: For operations at EIT acceptance and return from EIT, also see Section 4.3, "EIT Processing Procedure." Note 2: Do not read the Interrupt Vector Register (IVECT) or write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts are disabled (PSW register IE bit = 0). Note 3: When multiple interrupts are disabled, execute processing in [4]. Processing in [4] is unnecessary if multiple interrupts are enabled by executing processing in [6] and [9]. Note 4: To enable multiple interrupts, execute processing in [6] and [9]. Note 5: To reenable interrupts (by setting the IE bit to 1) after reading the Interrupt Vector Register (IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts. In the example here, there is no need to add a dummy access because the ICU vector table is read after reading the IVECT register. Similarly, to reenable interrupts (by setting the IE bit to 1) after writing to the Interrupt Request Mask Register (IMASK), there are precautions to be taken when reenabling interrupts (by setting the IE bit to "1") after writing the Interrupt Mask Register (IMASK). For details, see the section 5.5.2 "Interrupt Mask Register." H'0000 0080 BRA instruction Read Interrupt Vector Register (IVECT) Read ICU vector table Branch to the interrupt handler for each internal peripheral I/O RTE H'0080 0004 H'0000 0094 H'0000 0113 Interrupt handler EI (External Interrupt) handler EI (External Interrupt) vector entry Interrupt handler start address Program being executed Interrupt generated IVECT Save BPC to the stack Save PSW to the stack Save general-purpose registers to the stack Restore BPC from the stack Restore PSW from the stack Restore general-purpose registers from the stack Read and save Interrupt Request Mask Register (IMASK) to the stack IMASK H'0080 0000 Set PSW register IE bit to 1 Clear PSW register IE bit to 0 Restore Interrupt Request Mask Register (IMASK) from the stack [1] [2] [3] [5] [7] [8] [9] [6] [10] [11] ICU vector table (Note 1) (Note 1) Hardware preprocessing when EIT is accepted Hardware postprocessing when RTE instruction is executed Read and overwrite Interrupt Request Mask Register (IMASK) [4] [12] (Note 2) (Note 2) (Note 3) (Note 4) (Note 5) (Note 4) (Note 2) Interrupt handler [1] to [12]: Processing of EI by interrupt handler

INTERRUPT CONTROLLER (ICU) 5-1832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

5.6 Description of System Break Interrupt (SBI) Operation

5.6.1 Acceptance of SBI

System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt is accepted anytime upon detection of a falling edge on the SBI# signal input pin no matter how the PSW register IE bit is set, and cannot be masked. If falling edge is inputted to SBI# pin again, system break is not occured while SBI request bit is set to "1."

5.6.2 SBI Processing by Handler

When the system break interrupt generated has been serviced, shut down or reset the system without return- ing to the program that was being executed when the interrupt occurred. Figure 5.6.1 Typical SBI Operation H'0000 0010 BRA instruction SBI (System Break Interrupt) handler SBI (System Break Interrupt) vector entry Program being executed SBI generated Processing to shut down the system (Note 1) Note 1: Do not return to the program that was being executed when the interrupt occurred. Shut down or reset the system

6.1 Outline of the Internal Memory

6.2 Internal RAM

6.3 Internal Flash Memory

6.4 Registers Associated with the Internal

6.5 Programming the Internal Flash Memory

6.6 Virtual Flash Emulation Function

6.7 Connecting to a Serial Programmer (CSIO

Mode)

6.8 Connecting to a Serial Programmer (UART

Mode)

6.9 Internal Flash Memory Protect Function

6.10 Notes on the Internal RAM

6.11 Notes on the Internal Flash Memory

6-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The 32176 internally contains the following types of memory:

24-Kbyte RAM 512-Kbyte, 384-Kbyte or 256-Kbyte flash memory

Specifications of the internal RAM are shown below. Table 6.2.1 Specifications of the Internal RAM Item Specification Size 24 Kbytes Location address H’0080 4000 to H’0080 9FFF Wait insertion Operates with zero wait states Internal bus connection Connected by 32-bit bus Dual port By using the Real-Time Debugger (RTD), data can be read (monitored) or written to any area of the internal RAM via serial communication from external devices independently of the CPU. (See Chapter 14, “Real-Time Debugger.”) Notes: Immediately after power-on reset (for the power-on case in which VDDE also goes up from GND), the value of the RAM is undefined. If the RAM is reset during RAM backup (power for only VDDE is on), the RAM retains the value it had immediately before being reset. Specifications of the internal flash memory are shown below. Table 6.3.1 Specifications of the Internal Flash Memory Item Specification Size M32176F4: 512 Kbytes M32176F3: 384 Kbytes M32176F2: 256 Kbytes Location address M32176F4: H’0000 0000 to H’0007 FFFF M32176F3: H’0000 0000 to H’0005 FFFF M32176F2: H’0000 0000 to H’0003 FFFF Wait insertion Operates with zero wait state Durability Standard product : 100 times 10000 (10k) times rewritable : 4-Kbyte block (Note 2) : 10000 (10k) times -product (Note 1) : Other blocks : 1000 (1k) times Internal bus connection Connected by 32-bit bus Other Virtual flash emulation function is incorporated. (See Section 6.6, “Virtual Flash Emulation Function.”) Note 1: The 10000 (10k) times rewritable product is offered as an optional item. For details about it, please contact your nearest office of Renesas or its distributor. Note 2: Block 1: H’0000 2000 to H’0000 2FFF Block 2: H’0000 3000 to H’0000 3FFF

6-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.3.1 Block Configuration of the M32176F4’s Internal Flash Memory H'0002 0000 8KB 8KB 32KB 64KB H'0000 7FFF H'0000 8000 H'0001 FFFF H'0000 5FFF H'0000 FFFF H'0001 0000 H'0000 4000 H'0000 6000 64KB H'0002 FFFF 64KB 64KB 64KB 64KB 64KB H'0003 0000 H'0003 FFFF H'0004 0000 H'0004 FFFF H'0005 0000 H'0005 FFFF H'0006 0000 H'0006 FFFF H'0007 0000 H'0007 FFFF H'0000 0000 H'0000 1FFF 8KB 4KB 4KB H'0000 2000 H'0000 2FFF H'0000 3000 H'0000 3FFF Block 0 Internal flash memory area of the M32176F4 (512 Kbytes) Unequal blocks Equal blocks Block 2 Block 1 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3

6-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.3.2 Block Configuration of the M32176F3’s Internal Flash Memory H'0002 0000 8KB 8KB 32KB 64KB H'0000 7FFF H'0000 8000 H'0001 FFFF H'0000 5FFF H'0000 FFFF H'0001 0000 H'0000 4000 H'0000 6000 64KB H'0002 FFFF 64KB 64KB 64KB H'0003 0000 H'0003 FFFF H'0004 0000 H'0004 FFFF H'0005 0000 H'0005 FFFF H'0000 0000 H'0000 1FFF 8KB 4KB 4KB H'0000 2000 H'0000 2FFF H'0000 3000 H'0000 3FFF Block 0 Internal flash memory area of the M32176F3 (384 Kbytes) Unequal blocks Equal blocks Block 2 Block 1 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3

6-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.3.3 Block Configuration of the M32176F2’s Internal Flash Memory H'0002 0000 8KB 8KB 32KB 64KB H'0000 7FFF H'0000 8000 H'0001 FFFF H'0000 5FFF H'0000 FFFF H'0001 0000 H'0000 4000 H'0000 6000 64KB H'0002 FFFF 64KB H'0003 0000 H'0003 FFFF H'0000 0000 H'0000 1FFF 8KB 4KB 4KB H'0000 2000 H'0000 2FFF H'0000 3000 H'0000 3FFF Block 0 Internal flash memory area of the M32176F2 (256 Kbytes) Unequal blocks Equal blocks Block 2 Block 1 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3

6-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.4 Registers Associated with the Internal Flash Memory

A register map associated with the internal flash memory is shown below. Internal Flash Memory Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 07E0 Flash Mode Register Flash Status Register 6-7 (FMOD) (FSTAT) 6-8 H'0080 07E2 Flash Control Register 1 Flash Control Register 2 6-9 (FCNT1) (FCNT2) 6-10 H'0080 07E4 Flash Control Register 3 Flash Control Register 4 6-11 (FCNT3) (FCNT4) 6-13 H'0080 07E6 (Use inhibited area) H'0080 07E8 Virtual Flash L Bank Register 0 6-15 (FELBANK0) H'0080 07EA Virtual Flash L Bank Register 1 6-15 (FELBANK1) (Use inhibited area) H'0080 07F0 Virtual Flash S Bank Register 0 6-16 (FESBANK0) H'0080 07F2 Virtual Flash S Bank Register 1 6-16 (FESBANK1)

6-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.4.1 Flash Mode Register

Flash Mode Register (FMOD) <Address: H’0080 07E0> <Upon exiting reset: H’1?> b Bit Name Function R W 0–2 No function assigned. Fix to "0" 00

3 FAENS 0: Flash access disabled R –

Flash access enable status bit 1: Flash access enabled 4–6 No function assigned. Fix to "0" 00

7 FPMOD 0: FP pin = "L" R –

External FP pin status bit 1: FP pin = "H" (1) FAENS (Flash Access Enable Status) bit (Bit 3) The FAENS bit shows whether access to the flash memory is enabled or disabled. When the flash memory is reset by the FRESET bit in Flash Control Register 4 (FCNT4) or accessed for programming/erasing, this bit is cleared to "0", resulting in the flash memory being disabled against access. When the flash memory becomes ready for access, this bit is set to "1." However, it requires up to 20µs for FAENS bit to be "1" from "0" after exiting Flash reset by FRESET bit or executing programming and erasing operation for Flash memory. (2) FPMOD (External FP Pin Status) bit (Bit 7) The FPMOD is a status bit which indicates the FP (Flash Protect) pin status. The internal flash memory is enabled for programming and erasing operation only when FPMOD = "1", and is protected against programming and erasing operation when FPMOD = "0". b 0 123456 b 7 FAENS FPMOD 0001000?

6-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.4.2 Flash Status Register

Flash Status Register (FSTAT) <Address: H’0080 07E1> <Upon exiting reset: H’80> b Bit Name Function R W

8 FBUSY 0: Being programmed or erased R –

Flash busy bit 1: Ready state 9 No function assigned. Fix to "0". 00

10 ERASE 0: Erase normally operating or teminated R –

Erase status confirmation bit 1: Erase error occurred

11 WRERR 0: Programming normally operating or terminated R –

Write status confirmation bit 1: Programming error occurred 12 No function assigned. Fix to "0". 00 13 FESQ1 ?– Reserved bit 14 FESQ2 ?– Reserved bit 15 No function assigned. Fix to "0". 00 Flash Status Register (FSTAT) consists of the following status bits that indicate the operation condition of the flash memory. (1) FBUSY (Flash Busy) bit (Bit 8) The FBUSY bit is used to determine whether the operation on the flash memory is finished when it is being programmed or erased. When FBUSY = "0", it means that the programming or erasing operation is being executed; when FBUSY = "1", the operation is finished. (2) ERASE (Erase Status Confirmation) bit (Bit 10) The ERASE bit is used to determine after execution of processing whether the erasing operation performed on the flash memory resulted in an error. When ERASE = "0", it means that the erasing operation terminated normally; when ERASE = "1", the erasing operation terminated in an error. Also, this bit is set to "1" when invalid command is issued. (3) WRERR (Write Status Confirmation) bit (Bit 11) The WRERR bit is used to determine after completion of processing whether the programming operation performed on the flash memory resulted in an error. When WRERR = "0", it means that the programming operation terminated normally; when WRERR = "1", the programming operation terminated in an error. Also, this bit is set to "1" when invalid command is issued. Note: Except when programming/erasing processing on the flash memory is forcibly terminated, do not manipulate the FRESET bit in Flash Control Register 4 (FCNT4) while the FBUSY bit = "0" (programming/erasure in progress). b 8 9 1 01 11 21 31 4 b 1 5 FBUSY ERASE WRERR FESQ1 FESQ2 10000000

6-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.4.3 Flash Control Registers

Flash Control Register 1 (FCNT1) <Address: H’0080 07E2> <Upon exiting reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00

3 FENTRY 0: Normal read R W

Flash E/W enable mode entry bit 1: Program/erase enable 4–6 No function assigned. Fix to "0". 00

7 FEMMOD 0: Normal mode R W

Virtual flash emulation mode bit 1: Virtual flash emulation mode Flash Control Register 1 (FCNT1) consists of the following two bits to control the internal flash memory. (1) FENTRY (Flash E/W Enable Mode Entry) bit (Bit 3) The FENTRY bit controls entry to flash E/W enable mode. Flash E/W enable mode can only be entered when FENTRY = "1". To set the FENTRY bit to "1", write "0" and then "1" to the FENTRY bit in succession while the FP pin = "H". To clear the FENTRY bit, check to see that the Flash Status Register (FSTAT) FBUSY bit = "1" (ready), issue Read Array commands (or Flash memory reset by FRESET bit), make sure that FAENS bit = "1", and then write "0" to the FENTRY bit. Note that the following operations cannot be performed while programming or erasing the internal flash memory (FSTAT register FBUSY bit = "0"). If one of these operations is attempted, the FENTRY bit is cleared to "0" in hardware. 1) Writing "0" to the FENTRY bit 2) Entering a "L" level signal to the FP pin 3) Entering a "L" level signal to the RESET# pin When running a program resident in the internal flash memory while the FENTRY bit = "0", the EI vector entry is located at the address H’0000 0080 of the internal flash memory. When running the flash write/ erase program in the RAM while the FENTRY bit = "1", the EI vector entry is located at the address H’0080 4000 of the RAM, allowing the flash programming/erasing operation to be controlled using interrupts. Table 6.4.1 Changes of the EI Vector Entry by FENTRY FENTRY EI Vector Entry Address

0 Internal flash memory area H'0000 0080

1 Internal RAM area H'0080 4000

(2) FEMMOD (Virtual Flash Emulation Mode) bit (Bit 7) The FEMMOD bit controls entry to virtual flash emulation mode. Virtual flash emulation mode is entered by setting the FEMMOD bit to "1" while the FENTRY bit = "0". (For details, see Section 6.6, “Virtual Flash Emulation Function.”) b 0 123456 b 7 FENTRY FEMMOD 00000000

6-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Flash Control Register 2 (FCNT2) <Address: H’0080 07E3> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 FLOCKS 0: Memory area read mode R (Note 1)

Lock bit read mode select bit 1: Register read mode 12–14 No function assigned. Fix to "0". 00

15 FPROT 0: Protection by lock bit effective R (Note 1)

Lock bit protect control bit 1: Protection by lock bit invalidated Note 1: It can be accessed for write only during the Flash E/W entry mode (FENTRY bit = "1"). (1) FLOCKS (Lock Bit Read Mode Select) bit (Bit 11) The FLOCKS bit is used to select a method for reading out the lock bit status. When the FLOCKS bit = "0", the internal flash memory is placed in memory area read mode, so that it is possible to inspect the lock bit status by issuing command data H’7171 to any address of the flash memory and then reading the last even address of the target block. When the FLOCKS bit = "1", the internal flash memory is placed in register read mode, so that it is possible to inspect the lock bit status by first issuing command data H’7171 and H’D0D0 to any address of the target block in succession and then, when the FBUSY bit is set to "1", by reading the FLOCKST bit in Flash Control Register 4. The FLOCKS bit can only be accessed for write when the FENTRY bit = "1". If one of the following operations is attempted, the FLOCKS bit is cleared to "0". 1) Writing "0" to the FLOCKS bit 2) Entering a "L" level signal to the FP pin 3) Clearing the FENTRY bit to "0" 4) Entering a "L" level signal to the RESET# pin (2) FPROT (Lock Bit Protect Control) bit (Bit 15) The FPROT bit controls invalidation of the internal flash memory protection by a lock bit (protection against programming/erasing operation). Protection of the internal flash memory is invalidated by setting the FPROT bit to "1", so that any blocks protected by a lock bit can now be programmed or erased. To set the FPROT bit to "1", write "0" and then "1" to the FPROT bit in succession while the FENTRY bit = "1". To clear the FPROT bit to "0", write "0" to the FPROT bit. If one of the following operations is attempted, the FPROT bit is cleared to "0". 1) Writing "0" to the FPROT bit 2) Entering a "L" level signal to the FP pin 3) Clearing the FENTRY bit to "0" 4) Entering a "L" level signal to the RESET# pin b 8 9 1 01 11 21 31 4 b 1 5 FLOCKS FPROT 00000000

6-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 FPROT = 0 FENTRY = 1 YES NO FENTRY = 1 FPROT = 1 FPROT is not set to 1 if a write cycle to any other area occurs during this time. FPRO T = 0 FPRO T = Figure 6.4.1 Protection Unlocking Flow Flash Control Register 3 (FCNT3) <Address: H’0080 07E4> <Upon exiting reset: H’11> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00

3 FBSYCK 0: Command accepted normally R –

Busy check bit 1: Command not accepted normally 4–6 No function assigned. Fix to "0". 00

7 FPBSYCK 0: Command accepted normally R –

Prebusy check bit 1: Command not accepted normally Flash Control Register 3 (FCNT3) is used when developing an internal flash memory write/erase program to check whether commands have been accepted normally. This register does not need to be used for a program that has been verified to be able to operate properly. (1) FBSYCK (Busy Check) bit (Bit 3) The FBSYCK bit is used to check whether a 2-cycle command (confirmation command H’D0D0 or a command that requires write data) issued to the flash memory during flash E/W enable mode has been accepted nor- mally. If the FBSYCK bit is found to be "0" after issuing a command in the second cycle (confirmation command H’D0D0 or write data), it means that the command in the second cycle has been accepted normally. Con- versely, if the FBSYCK bit is found to be "1", it means that the command in the second cycle has not been accepted normally. In addition to the above, the FBSYCK bit is set to "1" in the following cases: 1) When a command in the first cycle of 2-cycle commands has been accepted 2) When the FRESET bit = "1" 3) When input on RESET# pin is pulled "L" b 0 123456 b 7 FBSYCK FPBSYCK 00010001

6-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) FPBSYCK (Prebusy Check) bit (Bit 7) The FPBSYCK bit is used to check whether a 2-cycle command (confirmation command H’D0D0 or a command that requires write data) issued to the flash memory during flash E/W enable mode has been accepted normally. If the FPBSYCK bit is found to be "0" after issuing a command in the first cycle, it means that the command in the first cycle has been accepted normally. Conversely, if the FPBSYCK bit is found to be "1", it means that the command in the first cycle has not been accepted normally. In addition to the above, the FPBSYCK bit is set to "1" in the following cases: 1) When in a ready state (FBUSY = "H" after a command in the second cycle has been accepted) 2) When the Clear Status Register command is issued 3) When the FRESET bit = "1" 4) When input on RESET# pin is pulled "L" END Check FSTAT for program error START Write a first-cycle command FBUSY = "1" TIME OUT ? YES NO Processing forcibly terminated YES NO FPBSYCK = "0" YES Write a second-cycle command or data Operation starts FBSYCK = "0" YES Write the Clear Status Register command H'5050 NO NO Figure 6.4.2 Method to Confirm the Command Acceptance by Checking FCNT3

6-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 b 8 9 1 01 11 21 31 4 b 1 5 FLOCKST FRESET 00000000 Flash Control Register 4 (FCNT4) <Address: H’0080 07E5> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 FLOCKST 0: Protected (Note 1)–

Lock bit status bit 1: Unprotected 12–14 No function assigned. Fix to "0". 00

15 FRESET 0: No operation R W

Flash reset bit 1: Reset Note 1. Under setting FLOCKS bit of the flash control register 2 as "1" (register read mode), only the reading out value becomes effective after issuing read rock bit status command. The reading out value is undefined after issuing that read rock bit status command under setting FLOCKS bit as "0" (memory area read mode) and that other internal flash control command. (1) FLOCKST (Lock Bit Status) bit (Bit 11) The FLOCKST bit is used to read the lock bit status. If the FLOCKST bit = "0", it means that the relevant memory block is protected. If the FLOCKST bit = "1", it means that the relevant memory block is not pro- tected. Confirmation of the lock bit status by the FLOCKST bit is possible when the FLOCKS bit = "1". In this case, the lock bit status can be checked by first issuing command data H’7171 and H’D0D0 to any address of the target block in succession and then, when the FBUSY bit is set to "1", by reading the FLOCKST bit. (2) FRESET (Flash Reset) bit (Bit 15) The FRESET bit controls forcible termination of the internal flash memory programming/erasing operation, initialization (to H’80) of each status bit in the Flash Status Register (FSTAT), and initialization of the FPBSYCK bit in Flash Control Register 3 (FCNT3). Setting the FRESET bit to "1" forcibly terminates programming/erasing operation and initializes each status bit in the FSTAT (to H’80) and the FPBSYCK bit in FCNT3. Make sure FRESET is held high (= "1") for at least 10 µs during a flash reset. After a flash reset, the internal flash memory is disabled against access until the FAENS bit is set to "1". The FRESET bit is effective only when the FENTRY bit = "1". Unless the FENTRY bit = "1", settings made to the FRESET bit are ignored. Make sure the FRESET bit = "0" while programming or erasing the flash memory.

6-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.4.3 Example of FRESET Bit 1 (Initializing Flash Status Register 2) Figure 6.4.4 Example of FRESET Bit 2 (Forcibly Terminating Programming/Erasing Operation) YES NO 10µs wait (by hardware timer or software timer) FMOD register FAENS = 1? YES NO FRESET = 1 FENTRY = 1 Program/erase the flash memory Error found FRESET = 0 Program/erase the flash memory FENTRY = 0 Programming/erasing operation terminated normally YES NO FRESET = 1 FRESET = 0 Forcibly terminate Flash programming/erasing operation has timed out 10µs wait (by hardware timer or software timer) FMOD register FAENS = 1?

6-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.4.4 Virtual Flash L Bank Registers

Virtual Flash L Bank Register 0 (FELBANK0) <Address: H’0080 07E8> Virtual Flash L Bank Register 1 (FELBANK1) <Address: H’0080 07EA> <Upon exiting reset: H’0000> b Bit Name Function R W

0 MODENL 0: Disable virtual flash emulation function R W

Virtual flash emulation L enable bit 1: Enable virtual flash emulation function 1–7 No function assigned. Fix to "0". 00 8–14 LBANKAD Start address A12–A18 of the relevant L bank R W L bank address bit 15 No function assigned. Fix to "0". 00 Note: These registers must always be accessed in halfwords. (1) MODENL (Virtual Flash Emulation L Enable) bit (Bit 0) The MODENL bit can be set to "1" after entering virtual flash emulation mode (by setting the FEMMOD bit to "1" while the FENTRY bit = "0"). This causes the virtual flash emulation function to be enabled for the L bank area selected by the LBANKAD bits. (2) LBANKAD (L Bank Address) bits (Bits 8–14) The LBANKAD bits are provided for selecting one of the L banks that are separated every 8 Kbytes. Use these LBANKAD bits to set the seven bits A12–A18 (b8 corresponds to the address A12, and b14 corre- sponds to the address A18) of the 32-bit start address of the desired L bank. Note: For details, see Section 6.6, “Virtual Flash Emulation Function.” b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 LBANKAD 000000000000000 MOD ENL

6-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.4.5 Virtual Flash S Bank Registers

Virtual Flash S Bank Register 0 (FESBANK0) <Address: H’0080 07F0> Virtual Flash S Bank Register 1 (FESBANK1) <Address: H’0080 07F2> <Upon exiting reset: H’0000> b Bit Name Function R W

0 MODENS 0: Disable virtual flash emulation function R W

Virtual flash emulation S enable bit 1: Enable virtual flash emulation function 1–7 No function assigned. Fix to "0". 00 8–15 SBANKAD Start address A12–A19 of the relevant S bank R W S bank address bit Note: These registers must always be accessed in halfwords. (1) MODENS (Virtual Flash Emulation S Enable) bit (Bit 0) The MODENS bit can be set to "1" after entering virtual flash emulation mode (by setting the FEMMOD bit to "1" while the FENTRY bit = "0"). This causes the virtual flash emulation function to be enabled for the S bank area selected by the SBANKAD bits. (2) SBANKAD (S Bank Address) bits (Bits 8–15) The SBANKAD bits are provided for selecting one of the S banks that are separated every 4 Kbytes. Use these SBANKAD bits to set the eight bits A12–A19 (b8 corresponds to the address A12, and b15 corre- sponds to the address A19) of the 32-bit start address of the desired S bank. Note: For details, see Section 6.6, “Virtual Flash Emulation Function.” b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 SBANKAD 000000000000000 MOD ENS

6-1732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.5.1 Outline of Internal Flash Memory Programming

To program or erase the internal flash memory, there are following two methods to choose depending on the situation: (1) When the flash write/erase program does not exist in the internal flash memory (2) When the flash write/erase program already exists in the internal flash memory For (1), set the FP pin = "H", MOD0 = "H" and MOD1 = "L" to enter boot mode. In this case, the CPU starts running the boot program immediately after reset. The boot program transfers the flash write/erase program into the internal RAM. After the transfer, jump to a location in the RAM and use the RAM-resident program to set the Flash Control Register 1 (FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erasing operation (i.e., placed in boot mode + flash E/W enable mode). When the above is done, use the flash write/erase program that has been transferred into the internal RAM to program or erase the internal flash memory. For (2), set the FP pin = "H", MOD0 = "L" and MOD1 = "L" to enter single-chip mode. Transfer the flash write/ erase program from the internal flash memory in which it has been prepared into the internal RAM. After the transfer, jump to the RAM and use the program transferred into the RAM to set the Flash Control Register 1 (FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erasing operation (i.e., placed in single-chip mode + flash E/W enable mode). When the above is done, use the flash write/erase program that has been transferred into the internal RAM to program or erase the internal flash memory. Or flash E/W enable mode can be entered from external extension mode by setting the FP pin = "H", MOD0 = "L" and MOD1 = "H." During flash E/W enable mode (FP pin = 1, FENTRY = 1), the EIT vector entry for External Interrupt (EI) is relocated to the start address (H’0080 4000) of the internal RAM. During normal mode, it is located in the flash area (H’0000 0080). To use an external interrupt (EI) in flash E/W enable mode, write at the beginning of the internal RAM an instruction for branching to the external interrupt (EI) handler that has been transferred into the internal RAM. Furthermore, because the IVECT register which is read out in the external interrupt (EI) handler has stored in it the flash memory address of the ICU vector table, make sure the ICU vector table to be used during flash E/ W enable mode is prepared in the internal RAM so that the value of the IVECT register will be converted into the internal RAM address of the ICU vector table (for example, by adding an offset) before performing branch processing. When started by boot mode, internal RAM value is indefinite after started by boot mode in order to "Flash writing/erasing program" is transferred to internal RAM.

6-1832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 EI vector entry (H'0000 0080) Internal ROM area Internal RAM H'0000 0000 H'00FF FFFF H'0080 4000 Internal ROM area Internal RAM H'0080 3FFF Flash E/W enable mode (FENTRY = 1) Normal mode (FENTRY = 0) H'0000 0000 H'0080 3FFF EI vector entry (H'0080 4000)H'0080 4000 H'00FF FFFF Figure 6.5.1 EI Vector Entry during Flash E/W Enable Mode

6-1932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.5.2 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase program does not exist in it) (1) When the flash write/erase program does not exist in the internal flash memory In this case, the boot program is used to program or erase the internal flash memory. To transfer the write data, use SIO1 in clock-synchronized serial interface or clock-asynchronized serial interface mode. To program or erase the internal flash memory using a flash programmer, follow the procedure described below. MOD1 = L SIO1 CPU Internal RAM Flash memory FP = L or H Internal RAM Internal RAM <Step 1> Initial state (Flash write/erase program nonexistent in the internal flash memory) <Step 2> Set the FP pin "H", MOD0 pin "H" and MOD1 pin "L" to place the flash memory in boot mode + flash E/W enable mode. Deassert reset signal and start up with the boot program. Transfer the flash write/erase program into the internal RAM. (Note 1) Jump to the flash write/erase program in the internal RAM. <Step 3> Using the flash write/erase program in the internal RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1. Program or erase the internal flash memory using the flash write/erase program. When finished, set the MOD0 "L" and jump to the internal flash memory or apply a reset to enter normal mode. M32R/ECU M32R/ECU M32R/ECU External device (e.g., flash programmer) External device (e.g., flash programmer) Flash memory Flash write data Flash memory MOD0 = L Boot program Boot program Boot program MOD1 = LFP = H MOD0 = H MOD1 = LFP = H MOD0 = H RESET# = L RESET# = H RESET# = H Flash write/ erase program Write data Write data Write data External device (e.g., flash programmer) Note 1. When started by boot mode, internal RAM value is indefinite after started by boot mode in order to "Flash writing/ erasing program" is transferred to internal RAM.

6-2032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 RESET# pin MOD0 pin FENTRY bit FP pin MOD1 pin POWER ON Mode selected Reset signal deasserted (Boot program starts) Mode selected Reset signal deasserted Flash programming/erasing by the boot program Settings by the boot program Figure 6.5.3 Internal Flash Memory Write/Erase Timing (when the flash write/erase program does not exist in it)

6-2132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.5.4 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase program already exists in it) (2) When the flash write/erase program already exists in the internal flash memory In this case, the flash write/erase program prepared in the internal flash memory is used to program or erase the internal flash memory. For programming/erasing operation here, use the internal peripheral circuits in the manner suitable for the programming system. (All resources of the internal peripheral circuits such as the data bus, serial interface and ports can be used.) The following shows an example for programming or erasing the internal flash memory by using SIO0 in single-chip mode. SIO0 CPU Flash write/ erase program SIO0 CPU Flash write/ erase program MOD1 = L SIO0 CPU Internal RAM Flash write/ erase program FP = L or H Write data Internal RAM Internal RAM <Step 1> Initial state (Flash write/erase program existing in the internal flash memory) An ordinary program in the internal flash memory is being executed. <Step 2> Set the FP pin "H", MOD1 pin "L" and MOD0 pin "L" to place the flash memory in single-chip + flash E/W enable mode. After determining the FP pin and MOD1 pin levels, transfer the flash write/erase program from the internal flash memory area into the internal RAM. (Note 1) Jump to the flash write/erase program in the internal RAM. <Step 3> Using the flash write/erase program in the internal RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1. Program or erase the internal flash memory using the flash write/erase program in the internal RAM. When finished, jump to the program in the flash memory or apply a reset to enter normal mode. M32R/ECU M32R/ECU M32R/ECU External device External device External device Flash memory Flash write data Flash memory MOD0 = L MOD1 = LFP = H MOD0 = L MOD1 = LFP = H MOD0 = L Write data Write data Note 1. When started by boot mode, internal RAM value is indefinite after started by boot mode in order to "Flash writing/ erasing program" is transferred to internal RAM.

6-2232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 RESET# pin MOD0 pin FENTRY bit FP pin "H" or "L" "H" or "L" (single-chip or external extension)MOD1 pin "L" "H" or "L" Flash programming/erasing by the flash write/erase program Flash rewrite starts Flash mode turned on Flash mode turned off Flash write/erase program transferred into the RAM Figure 6 .5.5 Internal Flash Memory Write/Erase Timing (when the flash write/erase program already exists in it)

6-2332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.5.2 Controlling Operation Modes during Flash Programming

The microcomputer’s operation mode is set by MOD0, MOD1 and Flash Control Register 1 (FCNT1) FENTRY bit. The table below lists operation modes that may be used when programming or erasing the internal flash memory. Table 6.5.1 Operation Modes Set during Flash Programming/erasing FP MOD0 MOD1 FENTRY (Note 1) Operation Mode Reset Vector Entry EI Vector Entry 0 0 0 0 Single-chip mode Start address of internal Flash area 1 0 0 0 flash memory (H'0000 0080) (H'0000 0000) 0 1 0 0 Processor mode Start address of externalExternal area area (H'0000 0000) (H'0000 0080) 0 0 1 0 External extension Start address of internal Flash area 1 0 1 0 mode flash memory (H'0000 0080) (H'0000 0000) 1 0 0 1 Single-chip mode Start address of internal Beginning of internal RAM + flash E/W enable flash memory (H'0080 4000) (H'0000 0000) 1 1 0 0 Boot mode Boot program startup Flash area address (H'0000 0080) 1 1 0 1 Boot mode + flash Boot program startup Beginning of internal RAM E/W enable address (H'0080 4000) 1 0 1 1 External extension Start address of internal Beginning of internal RAM mode + flash E/W flash memory (H'0080 4000) enable (H'0000 0000) – 1 1 – Use inhibited – – Note 1: Indicates the Flash Control Register 1 (FCNT1) FENTRY bit status (– denotes “Don’t care”). However, if FP = "0", writing "1" to FENTRY only results in it cleared to "0". Note 2: Always make sure the MOD2 pin is connected low (= 0) to ground (GND).

6-2432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (1) Flash E/W enable mode Flash E/W enable mode is a mode in which the internal flash memory can be programmed or erased. In flash E/W enable mode, no programs can be executed in the internal flash memory. Therefore, the neces- sary program must be transferred into the internal RAM before entering flash E/W enable mode, so that it can be executed in the internal RAM. (2) Entering flash E/W enable mode Flash E/W enable mode can only be entered when operating in single-chip, external extension or boot mode. Furthermore, it is only when the FP pin = "H" and the Flash Control Register 1 (FCNT1) FENTRY bit = "1" that flash E/W enable mode can be entered. Flash E/W enable mode cannot be entered when operat- ing in processor mode or the FP pin = "L." (3) Detecting the MOD0 and MOD1 pin levels The MOD0 and MOD1 pin levels ("H" or "L") can be known by checking the P8 Data Register (Port Data Register, H’0080 0708) MOD0DT and MOD1DT bits. P8 Data Register (P8DATA) <Address: H’0080 0708> 123456 b 7b0 P87DTP86DTP85DTP84DTP83DTP82DTMOD1DTMOD0DT <Upon exiting reset: Undefined> b Bit Name Function R W

0 MOD0DT 0: MOD0 pin = "L" R –

MOD0 data bit 1: MOD0 pin = "H"

1 MOD1DT 0: MOD1 pin = "L" R –

MOD1 data bit 1: MOD1 pin = "H"

2 P82DT At read R W

Port P82 data bit Depends on how the Port Direction Register is set

3 P83DT If direction bit = "0" (input mode)

Port P83 data bit 0: Port input pin = "L"

4 P84DT 1: Port input pin = "H"

Port P84 data bit If direction bit = "1" (output mode) (Note 1)

5 P85DT 0: Port output latch = "0" / Port pin level = "L"

Port P85 data bit 1: Port output latch = "1" / Port pin level = "H"

6 P86DT At write

Port P86 data bit Write to the port output latch

7 P87DT

Note 1: To select the port data to read, use the Port Input Special Function Control Register’s port input data select bit (PISEL).

6-2532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.5.6 Procedure for Entering Flash E/W Enable Mode END START Enter one of the following modes:

Single-chip mode Boot mode External extension modeTransfer the flash write/erase program into the internal RAM Set the FENTRY bit in the Flash Control Register (FCNT1) to "0" Set the FENTRY bit of Flash Control Register (FCNT1) to "1" Execute flash wirte/erase command and various read commands (Note 1) Switched to the flash write/erase program Wait for 1µs (using a hardware or software timer) Switched to normal mode Check MOD0/1 and FP pin levels(Note2) YES NO END Note 1: For details about each command, see Section 6.6.3, "Procedure for Programming/Erasing the Internal Flash Memory." Note 2: C hecked by FPMOD bit in FMOD register and MOD0DT and MOD1DT bits in P8DATA register Note 3: For details about the procedure for switching process to normal mode, see Figure 6.5.7 " Procedure for switching to nomal mode." → Go to flash E/W enable mode Jump to the flash memory or apply reset Switching to normal mode process (Note 3)

6-2632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.5.7 Procedure for switching to normal mode START Execute flash write/erase command and various read commands FBUSY bit = 1 (Note 2) YES NO Issue read array command or reset flash memory by the FRESET Switched to normal mode FAENS bit = 1 (Note 3) YES NO Set the FENTRY bit of the Flash Control Register (FCNT1) to "0" Wait for more than 4 CPUCLK cycles (Note 4) END Note1: For details about each command, see Section 6.6.3, "Procedure for Programming/Erasing the Internal Flash Memory." Note2: If it is checked that the value of FBUSY bit in Flash Status Register (FSTAT) is "1" after executing the command in flash E/W enable mode, it is not necessary to check that the value of FBUSY bit is "1". Note3: If flash memory reset by FRESET bit in Flash Control Register 4 (FCNT4) is not executed, it is not necessary to check that the value of FAENS bit in Flash Mode Register (FMOD) is "1". Note4: Insert any instructions for more than 4 CPUCLK waits other than NOP that do not require clock cycles (one that is automatically inserted by the assembler for alignment adjustment: instruction code H'F000). Note: . When switching to normal mode by entering a "L" level signal to the RESET# pin in flash E/W enable mode, enter the signal to the RESET# pin after checking that the value of FBUSY bit is "1"(ready). Jump to the flash memory or apply reset

6-2732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.5.3 Procedure for Programming/Erasing the Internal Flash Memory

To program or erase the internal flash memory, set up chip mode to enter flash E/W enable mode and execute the flash write/erase program in the internal RAM into which it has been transferred from the internal flash memory. In flash E/W enable mode, because the internal flash memory cannot be accessed for read as in normal mode, no programs present in it can be executed. Therefore, the flash write/erase program must be made available in the internal RAM before entering flash E/W enable mode. Once flash E/W enable mode is entered into, only flash command and no other commands can be used to access the internal flash memory. To access the internal flash memory in flash E/W enable mode, issue commands for the internal flash memory address to be operated on. The table below lists the commands that can be issued in flash E/W enable mode. Note: During flash E/W enable mode, the internal flash memory cannot be accessed for read or write wordwise. Table 6.5.2 Commands in Flash E/W Enable Mode Command Name Issued Command Data Read Array command H'FFFF Halfword Program command H'4040 Lock Bit Program command H'7777 Block Erase command H'2020 Clear Status Register command H'5050 Read Lock Bit Status command H'7171 Verify command (Note 1) H'D0D0 Note 1: This command must be issued immediately after the Lock Bit Program, Block Erase or Read Lock Bit Status command. If the Lock Bit Program, Block Erase or Read Lock Bit Status command is followed by other than the Verify (H'D0D0) command, the Lock Bit Program, Block Erase or Read Lock Bit Status command is not executed normally and terminated in error. (1) Read Array command Writing the Read Array command (H’FFFF) to any address of the internal flash memory places it in read mode. Then read the desired flash memory address, and the content of that address will be read out. Before exiting flash E/W enable mode, always be sure to execute the Read Array command. Write the Read Array command (H'FFFF) to any address of the internal flash memory Read the desired flash memory address END Figure 6.5.8 Read Array

6-2832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Confirm the result of execution of the programming process (Note 1) Last address? YES NO START Write the program data to the internal flash memory address to be programmed Write the Halfword Program command (H'4040) to any address of the internal flash memory Internal flash memory is programmed by Halfword Program Wait for 1 µs (using a hardware or software timer) FBUSY bit = 1 TIME OUT? 600 µs (Note 2) YES NO Forcibly terminated YES NO To next halfword Note 1: Check Flash Status Register (FSTAT) ERASE bit (for the erase status) and WRERR bit (for the write status). Note 2: It is the TIME OUT period of 4K-byte block, which is 10k times rewritable product. The TIME OUT period of Other blocks and standard products (Flash rewrite durability: 100 times) is 200µs. (2) Halfword Program command The internal flash memory is programmed a halfword at a time, each halfword consisting of 2 bytes. To program the flash memory, write the Program command (H’4040) to any address of the internal flash memory and then the program data to the address to be programmed. The protected flash memory blocks cannot be accessed for write by the Halfword Program command. Halfword programming is automatically performed by the internal control circuit, and whether the Halfword Program command has finished can be known by checking the Flash Status Register FBUSY bit. While the FBUSY bit = "0", the next programming cannot be performed. Figure 6.5.9 Halfword Program

6-2932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (3) Lock Bit Program command The internal flash memory can be protected against programming/erasing operation one block at a time. The Lock Bit Program command is provided for protecting the flash memory blocks. Write the Lock Bit Program command (H’7777) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to the last even address of the flash memory block to be protected, and this memory block is thereby protected against programming/erasing operation. To remove protection, use the Flash Control Register 2 (FCNT2) FPROT bit to invalidate protection by a lock bit and erase the flash memory block whose protection is to be removed. (The content of that memory block is also erased.) Lock bit programming is automatically performed by the internal control circuit, and whether the Lock Bit Program command has finished can be known by checking the Flash Status Register (FSTAT) FBUSY bit. While the FBUSY bit = "0", the next programming cannot be performed. The table below lists the target flash memory blocks and their addresses to be specified when writing the Verify command data. Table 6.5.3 M32176F4 Target Blocks and Specified Addresses Target Block Specified Address

0 H'0000 1FFE

1 H'0000 2FFE

2 H'0000 3FFE

3 H'0000 5FFE

4 H'0000 7FFE

5 H'0000 FFFE

6 H'0001 FFFE

7 H'0002 FFFE

8 H'0003 FFFE

9 H'0004 FFFE

10 H'0005 FFFE

11 H'0006 FFFE

12 H'0007 FFFE

Table 6.5.4 M32176F3 Target Blocks and Specified Addresses Target Block Specified Address

6-3032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 END START Write the Verify command (H'D0D0) to the last even address of the flash memory block to be protected Write the Lock Bit Program command (H'7777) to any address of the internal flash memory Lock bit is programmed by Lock Bit Program Wait for 1 µs (using a hardware or software timer) FBUSY bit = 1 TIME OUT? YES NO Forcibly terminated YES NO Confirm the result of execution of the programming process (Note 1) Note 1: Check Flash Status Register (FSTAT) ERASE bit (for the erase status) and WRERR bit (for the write status). Note 2: It is the TIME OUT period of 4K-byte block, which is 10k times rewritable product. The TIME OUT period of Other blocks and standard products (Flash rewrite durability: 100 times) is 200µs. 600 µs (Note 2) Figure 6.5.10 Lock Bit Program Table 6.5.5 M32176F2 Target Blocks and Specified Addresses Target Block Specified Address

6-3132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 END START Write the Verify command (H'D0D0) to the last even address of the flash memory block to be erased Write the Block Erase command (H'2020) to any address of the internal flash memory Internal flash memory contents are erased by the Block Erase command Wait for 1 µs (using a hardware or software timer) TIME OUT? YES NO Forcibly terminated YES NO Confirm the result of execution of the erase process (Note 1) FBUSY bit = 1 8 s (Note 2) Note 1: Check Flash Status Register (FSTAT) ERASE bit (for the erase status) and WRERR bit (for the write status). Note 2: It is the TIME OUT period of 4K-byte block, which is 10k times rewritable product. The TIME OUT period of Other blocks and standard products (Flash rewrite durability: 100 times) is 6s. Figure 6.5.11 Block Erase (4) Block Erase command The Block Erase command erases the content of the internal flash memory one block at a time. To perform this operation, write the command data (H’2020) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to the last even address of the flash memory block to be erased (see Tables The protected flash memory blocks cannot be erased by the Block Erase command. Block erase operation is automatically performed by the internal control circuit, and whether the Block Erase command has finished can be known by checking the Flash Status Register (FSTAT) FBUSY bit. (See Section 6.4.2, “Flash Status Registers.”) While the FBUSY bit = "0", the next block erase operation cannot be performed.

6-3232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (7) Clear Status Register command The Clear Status Register command clears the Flash Status Register (FSTAT) ERASE (erase status), and WRERR (write status) bits to "0". Write the command data (H’5050) to any address of the internal flash memory, and Flash Status Register is thereby initialized. Also, issue the Clear Status Register command, and Flash Status Register 3 (FCNT3) is initialized. If an error occurs when programming or erasing the flash memory and the Flash Status Register (FSTAT) ERASE (erase status) or WRERR (write status) bit is set to "1", the next programming or erasing operation cannot be executed unless each status bit is cleared to "0". START Write the Clear Status Register command (H'5050) to any address of the internal flash memory END Figure 6.5.12 Clear Status Register

6-3332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 FLBST Write the Read Lock Bit Status command (H'7171) to any address of the internal flash memory Read the last even address of the flash memory block to be checked END Figure 6.5.13 Read Lock Bit Status (Memory Area Read Mode) (8) Read Lock Bit Status command The Read Lock Bit Status command is provided for checking whether a flash memory block is protected against programming/erasing operation. The method for reading lock bit can be chosen from the following depends on the setting for Flash Control Register 2 (FCNT2) FLOCKS (Lock bit read mode select) bit. 1) Memory area read mode (FLOCKS bit = 0) Write the command data (H’7171) to any address of the internal flash memory. Next, read the last even Blocks and Specified Addresses”), and the read data shows whether the target block is protected. If the FLBST (lock bit) in the read data is "0", it means that the target memory block is protected. If the FLBST (lock bit) is "1", it means that the target memory block is not protected. Lock Bit Status Register (FLBST) <Upon exiting reset: Undefined> b Bit Name Function R W 0–8 No function assigned. ?0

9 FLBST 0: Protected R –

Lock bit 1: Not protected 10–15 No function assigned. ? 0 The Lock Bit Status Register is a read-only register, which is included for each memory block independently of one another. To read this register, Flash Control Register 2 (FCNT2) FLOCKS bit must be set to "0".

6-3432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 2) Register read mode (FLOCKS bit = 1) Write the command data (H’7171) to any address of the target block. Next, write the verify command data (H'D0D0), and the Flash Control Register 4 (FCNT4) FLOCKST (Lock Bit Status) bit shows whether the target block is protected. END START Write the Verify command (H'D0D0) to any address of the block Write the Read Lock Bit Status command (H'7171) to any address of the block to be read TIME OUT? YES NO Forcibly terminated YES NO Confirm the Lock bit status bit (Note 1) FBUSY bit = 1 10 µs Note 1: Check Flash Status Register 4 (FSTAT4) FLOCKST bit. Figure 6.5.14 Read Lock Bit Status (Register Read Mode) The following describes how to write to the lock bit. a) To clear the lock bit to "0" (flash protected) Issue the Lock Bit Program command (H’7777) to the memory block to be protected. b) To set the lock bit to "1" (flash unprotected) After setting the FPROT bit in Flash Control Register 2 to 1 (protection by lock bit disabled), use the Block Erase command (H’2020) to erase the memory block to be unprotected. The lock bit cannot be set to "1" directly by writing to it. c) Lock bit status when reset Because the lock bit is a nonvolatile bit, it remains unaffected when the microcomputer is reset or powered off.

6-3532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.5.4 Flash Programming Time (Reference)

The following shows the time needed to program internal flash memory for reference. (1) M32176F4 [1] Time required for transfer by SIO (for a transfer data size of 512 Kbytes) 1/57,600 bps × 1 (frame) × 11 (number of bits transferred) × 512 KB = approx. 100.1 [s] [2] Time required for programming the flash memory 512 KB / 2-byte × 25 µs = approx. 6.6 [s] [3] Time required for erasing the entire area 0.3 s × 5 (blocks) + 0.5 s × 1 (block) + 0.8 s × 7 (blocks) = 7.6 [s] [4] Total flash programming time (entire 512 Kbytes area) When communicating at 57,600 bps via UART, the flash programming time can be ignored because it is very short compared to the serial communication time. Therefore, the total flash programming time can be calculated using the equation below. [1] + [3] = approx. 108 [s] If the transfer time can be ignored by speeding up the serial communication or by other means, the fastest programming time possible can be calculated using the equation below. [2] + [3] = approx. 15 [s] (2) M32176F3 1) Time required for transfer by SIO (for a transfer data size of 384 Kbytes) 1/57,600 bps × 1 (frame) × 11 (number of bits transferred) × 384 KB = approx. 75.1 [s] 2) Time required for programming the flash memory 384 KB / 2-byte × 25 µs = approx. 4.9 [s] 3) Time required for erasing the entire area 0.3 s × 5 (blocks) + 0.5 s × 1 (block) + 0.8 s × 5 (blocks) = 6 [s] 4) Total flash programming time (entire 384 Kbytes area) When communicating at 57,600 bps via UART, the flash programming time can be ignored because it is very short compared to the serial communication time. Therefore, the total flash programming time can be calculated using the equation below. [1] + [3] = approx. 82 [s] If the transfer time can be ignored by speeding up the serial communication or by other means, the fastest programming time possible can be calculated using the equation below. [2] + [3] = approx. 11 [s]

6-3632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (3) M32176F2 1) Time required for transfer by SIO (for a transfer data size of 256 Kbytes) 1/57,600 bps × 1 (frame) × 11 (number of bits transferred) × 256 KB = approx. 50.1 [s] 2) Time required for programming the flash memory 256 KB / 2-byte × 25 µs = approx. 3.3 [s] 3) Time required for erasing the entire area 0.3 s × 5 (blocks) + 0.5 s × 1 (block) + 0.8 s × 3 (blocks) = 4.4 [s] 4) Total flash programming time (entire 256 Kbytes area) When communicating at 57,600 bps via UART, the flash programming time can be ignored because it is very short compared to the serial communication time. Therefore, the total flash programming time can be calculated using the equation below. [1] + [3] = approx. 55 [s] If the transfer time can be ignored by speeding up the serial communication or by other means, the fastest programming time possible can be calculated using the equation below. [2] + [3] = approx. 8 [s]

6-3732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The microcomputer has the function to map 8-Kbyte memory blocks of the internal RAM (max. 2 blocks) into areas (L banks) of the internal flash memory that are divided in 8-Kbyte units and to map 4-Kbyte memory blocks of the internal RAM (max. 2 blocks) into areas (S banks) of the internal flash memory that are divided in 4-Kbyte units. This functions is referred to as the Virtual Flash Emulation Function. This function allows the data located in 4-Kbyte or 8-Kbyte blocks of the internal RAM to be changed with the contents of internal flash memory at the addresses specified by the Virtual Flash Bank Register. That way, the relevant internal RAM data can read out by reading the content of internal flash memory. For applications that require modifying the contents of internal flash memory (e.g., data table) during operation, this function enables dynamic data modification by modifying the relevant internal RAM data. The internal RAM blocks allocated for virtual flash emulation can be accessed for read and write the same way as in usual internal RAM. This function, when used in combination with the microcomputer’s internal Real-Time Debugger (RTD), allows the data table, etc. created in the internal flash memory to be referenced or rewritten from the outside, thereby facilitating data table tuning from an external device. Note: Before programming/erasing the internal flash memory, always be sure to exit this virtual flash emulation mode. Figure 6.6.1 Internal RAM Bank Configuration of the M32176 (FELBANK0)

8 Kbytes

H'0080 4000 H'0080 6000 H'0080 5FFF H'0080 6FFF H'0080 7000 RAM bank S block 0 (FESBANK0)

4 Kbytes

(FESBANK1)

4 KbytesH'0080 7FFF

(FELBANK1) H'0080 8000 H'0080 9FFF

6-3832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.6.1 Virtual Flash Emulation Area

The following shows the internal flash memory areas in which the Virtual Flash Emulation Function is appli- cable. Using the Virtual Flash L Bank Register (FELBANK0, FELBANK1), select one among all L banks of internal flash memory that are divided in 8-Kbyte units (by setting the seven start address bits A12–A18 of the desired L bank in the Virtual Flash L Bank Register LBANKAD bits). Then set the Virtual Flash L Bank Register’s flash emulation L enable bit (MODENL) to "1", and the selected L bank area will be replaced with 8-Kbyte blocks of the internal RAM, up to two blocks in all. Using the Virtual Flash S Bank Register (FESBANK0, FESBANK1), select one among all S banks of internal flash memory that are divided in 4-Kbyte units (by setting the eight start address bits A12–A19 of the desired S bank in the Virtual Flash S Bank Register SBANKAD bits). Then set the Virtual Flash S Bank Register’s flash emulation S enable bit (MODENS) to "1", and the selected S bank area will be replaced with 4-Kbyte blocks of the internal RAM, up to two blocks in all. Two 8-Kbyte units L banks and two 4-Kbyte units S banks, total of four banks (maximum), can be selected. Notes: If the same bank area is set in two or more Virtual Flash Bank Registers and each register’s flash emulation enable bit is enabled, the bank is assigned the corresponding internal RAM area (8- Kbyte or 4-Kbyte) according to the priority given below. FELBANK0 > FESBANK0 > FESBANK1 > FELBANK1 During virtual flash emulation mode, RAM can be accessed for read and write from the internal RAM area and the virtual flash set area. Before reading any virtual flash area after setting the Flash Control Register 1 virtual flash emu- lation mode bit to "1", be sure that there must be an interval of at least three clocks (CPU clocks). Before reading any virtual flash area after setting the Virtual Flash Bank Register (L bank and S bank registers) virtual flash emulation enable bit and bank address bits, be sure that there must be an interval of at least three clocks (CPU clocks).

6-3932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.6.2 M32176F4 Virtual Flash Emulation Area divided in 8-Kbyte units Figure 6.6.3 M32176F4 Virtual Flash Emulation Area divided in 4-Kbyte units H'0000 0000 H'0000 2000 H'0080 4000 H'0000 4000 H'0007 E000 H'0007 C000 H'0080 6000 H'0080 7000 H'0080 8000 (8 Kbytes) L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) L bank 62 (8 Kbytes) L bank 63 (8 Kbytes) <Internal flash> <Internal RAM> Notes: If the same bank area is set in two or more Virtual Flash Bank Registers and each register's flash emulation enable bit is enabled, the bank is assigned the corresponding internal RAM area in order of priority: FELBANK0 > FESBANK0 > FESBANK1 > FELBANK1. If any 8-Kbyte area (L bank) specified by the Virtual Flash L Bank Registers 0 and 1 is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the virtual flash set area. H'0000 0000 H'0000 1000 H'0080 4000 H'0000 2000 H'0007 F000 H'0007 E000 H'0080 6000 H'0080 7000 H'0080 8000 (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes) S bank 126 (4 Kbytes) S bank 127 (4 Kbytes) <Internal flash> <Internal RAM> Notes: If the same bank area is set in two or more Virtual Flash Bank Registers and each register's flash emulation enable bit is enabled, the bank is assigned the corresponding internal RAM area in order of priority: FELBANK0 > FESBANK0 > FESBANK1 > FELBANK1. If any 4-Kbyte area (S bank) specified by the Virtual Flash S Bank Registers 0 and 1 is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the virtual flash set area.

6-4032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.6.4 M32176F3 Virtual Flash Emulation Area divided in 8-Kbyte units Figure 6.6.5 M32176F3 Virtual Flash Emulation Area divided in 4-Kbyte units H'0000 0000 H'0000 2000 H'0080 4000 H'0000 4000 H'0005 E000 H'0005 C000 H'0080 6000 H'0080 7000 H'0080 8000 (8 Kbytes) L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) L bank 46 (8 Kbytes) L bank 47 (8 Kbytes) <Internal flash> <Internal RAM> Notes: If the same bank area is set in two or more Virtual Flash Bank Registers and each register's flash emulation enable bit is enabled, the bank is assigned the corresponding internal RAM area in order of priority: FELBANK0 > FESBANK0 > FESBANK1 > FELBANK1. If any 8-Kbyte area (L bank) specified by the Virtual Flash L Bank Registers 0 and 1 is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the virtual flash set area. H'0000 0000 H'0000 1000 H'0080 4000 H'0000 2000 H'0005 F000 H'0005 E000 H'0080 6000 H'0080 7000 H'0080 8000 (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes) S bank 94 (4 Kbytes) S bank 95 (4 Kbytes) <Internal flash> <Internal RAM> Notes: If the same bank area is set in two or more Virtual Flash Bank Registers and each register's flash emulation enable bit is enabled, the bank is assigned the corresponding internal RAM area in order of priority: FELBANK0 > FESBANK0 > FESBANK1 > FELBANK1. If any 4-Kbyte area (S bank) specified by the Virtual Flash S Bank Registers 0 and 1 is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the virtual flash set area.

6-4132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.6.6 M32176F2 Virtual Flash Emulation Area divided in 8-Kbyte units Figure 6.6.7 M32176F2 Virtual Flash Emulation Area divided in 4-Kbyte units H'0000 0000 H'0000 2000 H'0080 4000 H'0000 4000 H'0003 E000 H'0003 C000 H'0080 6000 H'0080 7000 H'0080 8000 (8 Kbytes) L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) L bank 30 (8 Kbytes) L bank 31 (8 Kbytes) <Internal flash> <Internal RAM> Notes: If the same bank area is set in two or more Virtual Flash Bank Registers and each register's flash emulation enable bit is enabled, the bank is assigned the corresponding internal RAM area in order of priority: FELBANK0 > FESBANK0 > FESBANK1 > FELBANK1. If any 8-Kbyte area (L bank) specified by the Virtual Flash L Bank Registers 0 and 1 is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the virtual flash set area. H'0000 0000 H'0000 1000 H'0080 4000 H'0000 2000 H'0003 F000 H'0003 E000 H'0080 6000 H'0080 7000 H'0080 8000 (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes) S bank 62 (4 Kbytes) S bank 63 (4 Kbytes) <Internal flash> <Internal RAM> Notes: If the same bank area is set in two or more Virtual Flash Bank Registers and each register's flash emulation enable bit is enabled, the bank is assigned the corresponding internal RAM area in order of priority: FELBANK0 > FESBANK0 > FESBANK1 > FELBANK1. If any 4-Kbyte area (S bank) specified by the Virtual Flash S Bank Registers 0 and 1 is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the virtual flash set area.

6-4232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.6.8 Values Set in the M32176F4’s Virtual Flash Bank Register when divided in 8-Kbyte units Figure 6.6.9 Values Set in the M32176F4’s Virtual Flash Bank Register when divided in 4-Kbyte units H'0000 0000 L bank Start address of bank in flash memory Values set in L bank address (LBANKAD) bit L bank 0 L bank 1 L bank 2 L bank 62 L bank 63 H'0000 2000 H'0000 4000 H'0007 C000 H'0007 E000 H'00 H'02 H'04 H'7C H'7E (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Note 1: Set the seven start address bits A12-A18 of each L bank of internal flash memory that is divided in 8-Kbyte units in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. H'0000 0000 S bank S bank 0 S bank 1 S bank 2 S bank 126 S bank 127 H'0000 1000 H'0000 2000 H'0007 E000 H'0007 F000 H'00 H'01 H'02 H'7E H'7F Start address of bank in flash memory Values set in S bank address (SBANKAD) bit (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Note 1: Set the eight start address bits A12-A19 of each S bank of internal flash memory that is divided in 4-Kbyte units in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits.

6-4332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.6.10 Values Set in the M32176F3’s Virtual Flash Bank Register when divided in 8-Kbyte units Figure 6.6.11 Values Set in the M32176F3’s Virtual Flash Bank Register when divided in 4-Kbyte units H'0000 0000 L bank L bank 0 L bank 1 L bank 2 L bank 46 L bank 47 H'0000 2000 H'0000 4000 H'0005 C000 H'0005 E000 H'00 H'02 H'04 H'5C H'5E Start address of bank in flash memory Values set in L bank address (LBANKAD) bit (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Note 1: Set the seven start address bits A12-A18 of each L bank of internal flash memory that is divided in 8-Kbyte units in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. H'0000 0000 S bank S bank 0 S bank 1 S bank 2 S bank 94 S bank 95 H'0000 1000 H'0000 2000 H'0005 E000 H'0005 F000 H'00 H'01 H'02 H'5E H'5F Start address of bank in flash memory Values set in S bank address (SBANKAD) bit (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Note 1: Set the eight start address bits A12-A19 of each S bank of internal flash memory that is divided in 4-Kbyte units in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits.

6-4432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.6.12 Values Set in the M32176F2’s Virtual Flash Bank Register when divided in 8-Kbyte units Figure 6.6.13 Values Set in the M32176F2’s Virtual Flash Bank Register when divided in 4-Kbyte units H'0000 0000 L bank L bank 0 L bank 1 L bank 2 L bank 30 L bank 31 H'0000 2000 H'0000 4000 H'0003 C000 H'0003 E000 H'00 H'02 H'04 H'3C H'3E Start address of bank in flash memory Values set in L bank address (LBANKAD) bit (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Note 1: Set the seven start address bits A12-A18 of each L bank of internal flash memory that is divided in 8-Kbyte units in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. H'0000 0000 S bank S bank 0 S bank 1 S bank 2 S bank 62 S bank 63 H'0000 1000 H'0000 2000 H'0003 E000 H'0003 F000 H'00 H'01 H'02 H'3E H'3F Start address of bank in flash memory Values set in S bank address (SBANKAD) bit (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Note 1: Set the eight start address bits A12-A19 of each S bank of internal flash memory that is divided in 4-Kbyte units in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits.

6-4532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.6.2 Entering Virtual Flash Emulation Mode

To enter virtual flash emulation mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit by writing "1". After entering virtual flash emulation mode, set the Virtual Flash Bank Register MODEN bit to "1" to enable the Virtual Flash Emulation Function. Even during virtual flash emulation mode, the internal RAM area (H’0080 4000 through H’0080 9FFF) can be accessed the same way as in usual internal RAM. Figure 6.6.14 Virtual Flash Emulation Mode Sequence Set RAM location address in Virtual Flash Bank Register LBANKAD ← Address A12–A18 SBANKAD ← Address A12–A19 Write flash data to RAM Enable virtual flash emulation MODENL ← 1 MODENS ← 1 Settings completed Enter virtual flash emulation mode FEMMOD ← 1 Settings start

6-4632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.6.3 Application Example of Virtual Flash Emulation Mode

By using two RAM areas that have been set in the same flash area by the Virtual Flash Emulation Function, the data in the flash memory can be replaced successively. Figure 6.6.15 Application Example of Virtual Flash Emulation Mode (1/2) Replace area Flash memory RAM block 0 Data write to RAM0 RAM block 1 (1) Operation when reset Replaced Data write to RAM1 (2) Programming operation using RAM block 0 Flash memory Initial value Initial value RAM block 0 RAM block 1 Replaced (3) Programming operation switched from RAM block 0 to RAM block 1 Flash memory Initial value RAM block 0 RAM block 1 RAM block 1Bank xx Bank xx Bank xx Bank xx specified Bank xx specified Bank xx specified (settings invalid) RAM block 0 RAM block 0

6-4732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Replaced (4) Programming operation using RAM block 1 Flash memory Initial value RAM block 0 RAM block 1 RAM block 1Bank xx Bank xx specified Replaced (5) Programming operation switched from RAM block 1 to RAM block 0 RAM block 0 Flash memory Initial value RAM block 0 RAM block 1 RAM block 1Bank xx Bank xx specified Bank xx specified (settings invalid) (6) Go to (2) Note: Enclosed in are the valid area. Data write to RAM0 Figure 6.6.16 Application Example of Virtual Flash Emulation Mode (2/2)

6-4832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.7 Connecting to a Serial Programmer(CSIO Mode)

6.7 Connecting to a Serial Programmer (CSIO Mode)

For the internal flash memory to be rewritten in boot mode + flash E/W enable mode by using a general-purpose serial programmer, several pins on the microcomputer must be processed to make them suitable for the serial programmer, as shown below. Table 6.7.1 Processing Microcomputer Pins before Using a Serial Programmer Notes Pin processing is not required for those that are not listed above. Pin Name Pin No. Function Remark SCLKI1 71 Transfer clock input Pull high RXD1 70 Serial data input (received data) Pull high TXD1 69 Serial data output (transmit data) P84 68 Transmit/receive enable output Pull high FP 94 Flash memory protect Pull high MOD0 92 Operation mode 0 Connect to the main power supply MOD1 93 Operation mode 1 Connect to ground MOD2 123 Operation mode 2 Connect to ground RESET# 91 Reset After setting MOD0/MOD1, ground and back to main power supply X IN 4 Clock input XOUT 5 Clock output SBI# 77 System Break interrupt (SBI) input Pull high or low VREF0 42 Reference voltage input for A/D converter Connect to the main power supply AVCC0 43 Analog power supply Connect to the main power supply AVSS0 60 Analog ground Connect to ground VDDE 108 RAM backup power supply Connect to the main power supply VCCE 20, 65, 95, 132 Main power supply 5 V +/- 10% or 3.3 V +/- 10% EXCVCC 61, 137 Connects external capacitance for the internal power supply Need to be grounded to earth via capacitor EXCVDD 73 Connects external capacitance for the RAM power supply Need to be grounded to earth via capacitor EX COSC- VCC 6 Connects external capacitance for the oscillator power supply Need to be grounded to earth via capacitor VSS 3, 21, 62, 72, 96, 138 Ground 0V JTRST 111 JTAG reset input Pull low (0-100 k Ω)

6-4932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 6.7.1 Pin Connection Diagram The diagram below shows an example of a user system configuration which has had a serial programmer con- nected. After the user system is powered on, the serial programmer writes to the internal flash memory in clock- synchronized serial mode. No communication problems associated with the oscillator frequency may occur. If the system uses any pins that are to be connected to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the ad- dresses H’0000 0084 through H’0000 0093 as an area in which to check the ID for flash memory protection. If the internal flash memory needs to be protected, set any ID in this area. 2kΩ (Note 1) SBI# 32176 XOUT XIN JTRST MOD1 OSC-VSS AVSS0 VSS RESET# FP MOD0 P84/SCLKI0/SCLKO0 P87/SCLKI1/SCLKO1 P86/RXD1 P85/TXD1 EXCVDD EXCVCC VREF0 AVCC0 EXCOSC-VCC VDDE VCCE Connect to the VCCE (5 or 3.3 V) power supply rail Main power supply Connect to the VCCE (5 or 3.3V) power supply rail Main power supply (for reference) RxD (input) TxD (output) SCLK0 (output) BUSY (input) MOD0 (output) FP (output) RESET (output) GND (common) ConnectorFlash programmer signals To system circuit Set microcomputer operating conditions User system board Notes: Turn on the power for the user system before writing to the internal flash memory. If P84-P87 are used in the system circuit, connection to a serial programmer must be taken into consideration. SBI# must be fixed "H" or "L" to ensure that no interrupts will be generated. The pullup resistance values of P84, P86 and P87 must be selected to suit the system design condition. The typical pullup resistance values of P84, P86 and P87 are 4.7 to 10 KΩ. The status of any other ports that are not shown here will not affect flash memory programming. Make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes while rewriting the internal flash memory. MOD2 Note 1: SBI# must be fixed "H" or "L" to ensure that no interrupts will be generated.

6-5032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

6.8 Connecting to a Serial Programmer (UART Mode)

For the internal flash memory to be rewritten in boot mode + flash E/W enable mode by using a general-purpose serial programmer, several pins on the microcomputer must be processed to make them suitable for the serial programmer, as shown below. Table 6.8.1 Processing Microcomputer Pins before Using a Serial Programmer for 32176 (UART Mode) Note Pin processing is not required for those that are not listed above. Pin Name Pin No. Function Remark SCLKI1 71 SIO mode selection Pull low ("L" level input) RXD1 70 Serial data input (received data) Pull high TXD1 69 Serial data output (transmit data) P84 68 General-purpose port input Not used during UART mode Pull high or pull low FP 94 Flash memory protect Pull high MOD0 92 Operation mode 0 Connect to the main power supply MOD1 93 Operation mode 1 Connect to ground MOD2 123 Operation mode 2 Connect to ground RESET# 91 Reset XIN 4 Cl oc k i nput XOUT 5 Clock output SBI# 77 System Break interrupt (SBI) input Pull high or low VREF0 42 Reference voltage input for A/D conv erter Connect to the main power supply AVCC0 43 Analog power supply Connect to the main power supply AVSS0 60 Analog gr ound Connect to ground VDDE 108 RAM backup power supply Connect to the main power supply VCCE 20, 65, 95, 132 Main power supply 5 V +/- 10% or 3.3 V +/- 10% EXCVCC 61, 137 Connects external capacitance for the internal power supply Need to be grounded to earth via capacitor EXCVDD 73 Connects external capacitance for the RAM power supply Need to be grounded to earth via capacitor EXCOSC-VCC 6 Connects external capacitance for the oscillator power supply Need to be grounded to earth via capacitor VSS 3, 21, 62, 72, 96, 138 Ground 0V JTRST 111 JTAG reset input Pull low (0-100 k Ω)

6-5132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The diagram below shows an example of a user system configuration which has had a serial programmer con- nected. After the user system is powered on, the serial programmer writes to the internal flash memory in clock- asynchronous serial mode (UART mode). No communication problems associated with the oscillator frequency may occur. If the system uses any pins that are to be connected to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the addresses H’0000 0084 through H’0000 0093 as an area in which to check the ID for flash memory protection. If the internal flash memory needs to be protected, set any ID in this area. Figure 6.8.1 Pin Connection Diagram (UART Mode) 32176 XOUT XIN JTRST MOD1 MOD2 AVSS0 VSS RESET# FP MOD0 P84/SCLKI0/SCLKO0 P87/SCLKI1/SCLKO1 P86/RXD1 P85/TXD1 EXCVDD EXCVCC EXCOSC-VCC VREF0 AVCC0 VDDE Connect to the VCCE (5 or 3.3 V) power supply rail Main power supply Connect to the VCCE (5 or 3.3V) power supply rail Main power supply (for reference) RxD (input) TxD (output) Mode selection (output) GND (common) ConnectorFlash programmer signals To system circuit Set microcomputer operating conditions User system board VCCE SBI#(Note 1) Note 1: SBI# must be fixed "H" or "L" to ensure that no interrupts will be generated. Notes: Turn on the power for the user system before writing to the internal flash memory. If P84-P87 are used in the system circuit, connection to a serial programmer must be taken into consideration. The pullup/pulldown resistance values of P84, P86, P87, FP and MOD0 must be selected to suit the system design condition. The typical pullup/pulldown resistance values of P84, P86, P87, FP and MOD0 are 4.7 to 10 KΩ. The status of any other ports that are not shown here will not affect flash memory programming. Make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes while rewriting the internal flash memory.

6-5232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The internal flash memory has the following four types of protect functions to prevent it from being inadvertently rewritten or illegally copied, programmed or erased. (1) Flash memory protect ID When using a tool to program/erase the internal flash memory such as a general-purpose programmer or emulator, the ID entered by a tool and the ID stored in the internal flash memory are collated. Unless the correct ID is entered, the internal flash memory cannot be read out, programmed nor erased. (For some tools, tool execution is enabled after erasing the entire flash memory area, and the internal flash memory becomes accessible for write.) (2) Protection by FP pin The internal flash memory is protected in hardware against programming/erasing operation by pulling the FP (Flash Protect) pin "L" level. For systems that do not require rewriting flash memory or systems in which flash reprogramming is prohibited as in the case of automotive applications, make sure the FP pin is fixed "L" level except when programming or erasing the internal flash memory. Furthermore, because the FP pin level can be known by reading the Flash Mode Register (FMOD)’s FPMOD (external FP pin status) bit in the flash write/ erase program, the internal flash memory can also be protected in software. For systems that do not require protection by setting external pins, the FP pin may be fixed high to simplify the operation to program/erase the internal flash memory. However, to prevent the flash memory from being inadvertently rewritten by an erratic operation in software, use the protection by a lock bit described in (4) below. When programming/erasing via JTAG, the flash memory can be programmed or erased regardless of the pin state because the FP pin is controlled internally within the chip. (3) Protection by FENTRY bit Flash E/W enable mode cannot be entered into unless the Flash Control Register 1 (FCNT1)’s FENTRY (flash mode entry) bit is set to "1". To set the FENTRY bit to "1", write "0" and then "1" in succession while the FP pin is high. (4) Protection by a lock bit Any block of internal flash memory can be protected by setting the lock bit provided for it to "0". That memory block is disabled against programming/erasing operation.

6-5332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The following describes notes on the internal RAM When started by boot mode, internal RAM value is indefinite after started by boot mode in order to "Flash writing/erasing program" is transferred to internal RAM. The following describes precautions to be taken when programming/erasing the internal flash memory. When the internal flash memory is programmed or erased, a high voltage is generated internally. Because mode transitions during programming/erasing operation may cause the chip to break down, make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes. If the system uses any pins that are to be used by a general-purpose programming/erasing tool, care must be taken to prevent adverse effects on the system when the tool is connected. If the internal flash memory needs to be protected while using a general-purpose programming/erasing tool, set any ID in the flash memory protect ID verification area (H’0000 0084 to H’0000 0093). If the internal flash memory does not need to be protected while using a general-purpose programming/erasing tool, fill the entire flash memory protect ID verification area (H’0000 0084 to H’0000 0093) with H’FF. If the Flash Status Register (FSTAT)’s each error status is to be cleared (initialized to H’80) by resetting the Flash Control Register 4 (FCNT4) FRESET bit, check to see that the Flash Status Register (FSTAT) FBUSY bit = "1" (ready) before clearing the error status. Before resetting the Flash Control Register 1 (FCNT1) FENTRY bit from "1" to "0", check to see that the Flash Status Register (FSTAT) FBUSY bit = "1" (ready). Do not clear the FENTRY bit if the Flash Control Register 1 (FCNT1) FENTRY bit = "1" and the Flash Status Register (FSTAT) FBUSY bit = "0" (being programmed or erased). When programming/erasing via JTAG, the flash memory can be programmed or erased regardless of the pin state because the FP pin is controlled internally within the chip.

6-5432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 This page is blank for reasons of layout.

7.1 Outline of Reset

7.2 Reset Operation

7.3 Internal State Immediately after Exiting Reset

7.4 Things to Be Considered after Exiting Reset

7-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The microcomputer is reset by applying a "L" level signal to the RESET# input pin. The microcomputer is gotten out of a reset state by releasing the RESET# input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the CPU starts executing from the reset vector entry. When a "L" level signal in width of more than 200 ns (a duration needed for noise cancellation) is applied to the RESET# pin, the microcomputer enters a reset state. At this time, the internal circuits (including the CPU) are reset. (For details about the pin state when reset, see Table 1.4.1, “Pin Assignments”) When the RESET# input is returned "H", the internal circuits get out of a reset state 512-513 BCLK periods after that. Internal circuit reset signal Flip-flop Counter RESET# Extended for a duration during which the RESET# input is held low 512–513BCLK RESET# pin Reset signal (internal signal) past the noise canceller Internal circuit reset signal (internal signal) Duration needed for noise cancellation: 200ns (Note 1) Note 1: If the low level duration of the reset signal is less than 200 ns, it is cancelled by the noise canceller. Figure 7.2.2 Reset Sequence Figure 7.2.1 Reset Circuit

7-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

7.2.1 Reset at Power-on

When powering on the microcomputer, hold the RESET# signal input pin "L" level until the rated power supply voltage is reached and the microcomputer’s internal x4 clock generator becomes oscillating stably.

7.2.2 Reset during Operation

To reset the microcomputer during operation, hold the RESET# signal input pin "L" level for more than 200 ns.

7.2.3 Reset Vector Relocation during Flash Programming

When the microcomputer is reset after entering boot mode, the reset vector entry address is moved to the boot program startup address. The boot program starts running after the reset state is deasserted. For details, see Section 6.5, “Programming the Internal Flash Memory.”

7-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The table below lists the internal state of the microcomputer immediately after it has gotten out of a reset state. For details about the initial register state of each internal peripheral I/O, see each section in this manual in which the relevant internal peripheral I/O is described. Table 7.3.1 Internal State Immediately after Exiting Reset Register State after Reset PSW (CR0) B'0000 0000 0000 0000 ??00 000? 0000 0000 (BSM, BIE, BC bits = undefined) CBR (CR1) H'0000 0000 (C bits = 0) SPI (CR2) Undefined SPU (CR3) Undefined BPC (CR6) Undefined PC H'0000 0000 (Executed beginning with the address H’0000 0000) (Note 1) R0–R15 Undefined ACC (accumulator) Undefined RAM Undefined when reset at power-on. (However, if the RAM is gotten out of reset after returning from backup mode, it retains the content it had before being reset.) Note 1: When in boot mode, the CPU executes the boot program.

Input/output ports After exiting the reset state, the microcomputer’s input/output ports are disabled against input in order to pre- vent current from flowing through the port. To use any ports in input mode, set the Port Input Special Function Control Register (PICNT) PIEN0 bit to enable them for input. For details, see Section 8.3, “Input/Output Port Related Registers.”

8.1 Outline of Input/Output Ports

8.2 Selecting Pin Functions

8.3 Input/Output Port Related Registers

8.4 Port Input Level Switching Function

8.5 Port Peripheral Circuits

8.6 Notes on Input/Output Ports

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The 32176 has a total of 96 input/output ports from P0-P13, P15, P17 and P22 (except P5, which is reserved for future use). These input/output ports can be used as input or output ports by setting the respective direction registers. Each input/output port is a dual-function or triple-function pin, sharing the pin with other internal peripheral I/O or external extension bus signal line. Pin functions are selected depending on the current operation mode or by setting the input/output port operation mode registers. (If any internal peripheral I/O has still another function, it is also necessary to set the register provided for that peripheral I/O.) The microcomputer also has a port input function enable bit that can be used to prevent current from flowing into the input ports. This helps to simplify the software and hardware processing to be performed immediately after reset or during flash programming. Note that before any ports can be used in input mode, this port input function enable bit must be set accordingly. The input/output ports are outlined below. Table 8.1.1 Outline of Input/Output Ports Item Specification Number of ports Total 96 ports P0 : P00–P07 (8 ports) P1 : P10–P17 (8 ports) P2 : P20–P27 (8 ports) P3 : P30–P37 (8 ports) P4 : P41–P47 (7 ports) P6 : P61–P63 (3 ports) P7 : P70–P77 (8 ports) P8 : P82–P87 (6 ports) P9 : P93–P97 (5 ports) P10 : P100–P107 (8 ports) P11 : P110–P117 (8 ports) P12 : P124–P127 (4 ports) P13 : P130–P137 (8 ports) P15 : P150, P153 (2 ports) P17 : P174, P175 (2 ports) P22 : P220, P221, P225 (3 ports) Port function The input/output ports can individually be set for input or output mode using the direction control register provided for each input/output port. (However, P221 is a CAN input-only port.) Pin function Shared with peripheral I/O or external extension signals to serve dual-functions (or shared with two or more peripheral I/O functions to serve triple-functions) Pin function P0–P4, P225: Depends on the CPU operation mode (that is set by MOD0 and MOD1 pins). selection P6–P22: As set by each input/output port’s operation mode register. (However, peripheral I/O pin functions are selected by peripheral I/O registers.) Note: P5, P14, P16, P18-P21 are nonexist.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Each input/output port serves dual functions sharing the pin with other internal peripheral I/O or external exten- sion bus signal line (or triple functions sharing the pin with two or more peripheral I/O functions). Pin functions are selected depending on the current operation mode or by setting the input/output port operation mode registers. P0–P4 and P225, when the CPU is set to operate in external extension mode or processor mode, all are switched to serve as signal pins for external access. The CPU operation mode is determined depending on how the MOD0 and MOD1 pins are set (see the table below). Table 8.2.1 CPU Operation Modes and P0–P4 and P225 Pin Functions MOD0 MOD1 Operation Mode P0–P4 and P225 Pin Function VSS VSS Single-chip mode Input/output port pin VSS VCCE External extension mode External extension signal pin VCCE VSS Processor mode VCCE VCCE Reserved (use inhibited) – Note: VCCE and VSS are connected to main power supply and GND, respectively. Each input/output port has their functions switched between input/output port pins and internal peripheral I/O pins by setting the respective port operation mode registers. If any internal peripheral I/O has two or more pin functions, use the register provided for that peripheral I/O to select the desired pin function. Note that FP and MOD1 pin settings during internal flash memory programming do not affect the pin functions.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 8.2.1 Input/Output Ports and Pin Function Assignments P10 P11 P12 P13 P14 P15 DB0 01234567 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 A23 A24 A25 A26 A27 A28 A29 A30 A15 A16 A17 A18 A19 A20 A21 A22 BLW#/ BLE# BHW#/ BHE# RD# CS0# CS1# A13 A14 (P61) (P62) (P63) BCLK/ WR# WAIT# HREQ# HACK# RTDTXD/ TXD3(Note 2) RTDRXD/ RXD3 (Note 2) RTDACK/ CTX1 (Note 2) RTDCLK/ CRX1 (Note 2) TXD0 RXD0 SCLKI0/ SCLKO0 TXD1 RXD1 SCLKI1/ SCLKO1 TO16 TO17 TO18 TO19 TO20 TO11 TO12 TO13 TO14 TO15TO10TO9TO8 TO3 TO4 TO5 TO6 TO7TO2TO1TO0 TCLK0 TCLK1 TCLK2 TCLK3 TIN16 TIN17 TIN18 TIN19 TIN20 TIN21 TIN22 TIN23 P16 P17 TXD2 P18 P19 P20 P21 P22 CTX0 CRX0 RXD2 TIN0 TIN3 MOD1 (Note 3) MOD0 (Note 3) A12 (Note 1) SBI# (Note 3) Input/output port operation mode setting (Reserved) CPU operation mode settings (Note 1) Note 1: The pin function changes depending on the setting for MOD0 and MOD1 pins. Note 2: These are triple-function pins. Their desired output function must be selected using the port peripheral function select register. Note 3: These ports cannot be used for input/output port function. The SBI#, MOD0 and MOD1 pin input levels can be read from these ports. Note: • P5, P14, P16, P18, P19, P20 and P21 are not provided.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The input/output port related registers included in the microcomputer consists of the port data register, port direction register and port operation mode register. Note that P5 is reserved for future use. The tables below show an input/output port related register map. Input/Output Port Related Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0700 P0 Data Register P1 Data Register 8-7 (P0DATA) (P1DATA) H'0080 0702 P2 Data Register P3 Data Register 8-7 (P2DATA) (P3DATA) H'0080 0704 P4 Data Register (Use inhibited area) 8-7 (P4DATA) H'0080 0706 P6 Data Register P7 Data Register 8-7 (P6DATA) (P7DATA) H'0080 0708 P8 Data Register P9 Data Register 8-7 (P8DATA) (P9DATA) H'0080 070A P10 Data Register P11 Data Register 8-7 (P10DATA) (P11DATA) H'0080 070C P12 Data Register P13 Data Register 8-7 (P12DATA) (P13DATA) H'0080 070E (Use inhibited area) P15 Data Register 8-7 (P15DATA) H'0080 0710 (Use inhibited area) P17 Data Register 8-7 (P17DATA) H'0080 0712 (Use inhibited area) (Use inhibited area) H'0080 0714 (Use inhibited area) (Use inhibited area) H'0080 0716 P22 Data Register (Use inhibited area) 8-7 (P22DATA) (Use inhibited area) H'0080 0720 P0 Direction Register P1 Direction Register 8-8 (P0DIR) (P1DIR) H'0080 0722 P2 Direction Register P3 Direction Register 8-8 (P2DIR) (P3DIR) H'0080 0724 P4 Direction Register (Use inhibited area) 8-8 (P4DIR) H'0080 0726 P6 Direction Register P7 Direction Register 8-8 (P6DIR) (P7DIR) H'0080 0728 P8 Direction Register P9 Direction Register 8-8 (P8DIR) (P9DIR) H'0080 072A P10 Direction Register P11 Direction Register 8-8 (P10DIR) (P11DIR) H'0080 072C P12 Direction Register P13 Direction Register 8-8 (P12DIR) (P13DIR) H'0080 072E (Use inhibited area) P15 Direction Register 8-8 (P15DIR) H'0080 0730 (Use inhibited area) P17 Direction Register 8-8 (P17DIR) H'0080 0732 (Use inhibited area) (Use inhibited area) H'0080 0734 (Use inhibited area) (Use inhibited area) H'0080 0736 P22 Direction Register (Use inhibited area) 8-8 (P22DIR)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Input/Output Port Related Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0744 (Use inhibited area) Port Input Special Function Control Register 8-15 (PICNT) H'0080 0746 (Use inhibited area) P7 Operation Mode Register 8-9 (P7MOD) H'0080 0748 P8 Operation Mode Register P9 Operation Mode Register 8-9 (P8MOD) (P9MOD) 8-10 H'0080 074A P10 Operation Mode Register P11 Operation Mode Register 8-10 (P10MOD) (P11MOD) 8-11 H'0080 074C P12 Operation Mode Register P13 Operation Mode Register 8-11 (P12MOD) (P13MOD) 8-12 H'0080 074E (Use inhibited area) P15 Operation Mode Register 8-12 (P15MOD) H'0080 0750 (Use inhibited area) P17 Operation Mode Register 8-13 (P17MOD) H'0080 0752 (Use inhibited area) (Use inhibited area) H'0080 0754 (Use inhibited area) (Use inhibited area) H'0080 0756 P22 Operation Mode Register (Use inhibited area) 8-13 (P22MOD) (Use inhibited area) H'0080 0760 Port Group 0,1 Input Level Setting Register Port Group 3 Input Level Setting Register 8-19 (PG01LEV) (PG3LEV) H'0080 0762 Port Group 4,5 Input Level Setting Register Port Group 6,7 Input Level Setting Register 8-19 (PG45LEV) (PG67LEV) H'0080 0764 Port Group 8 Input Level Setting Register (Use inhibited area) 8-19 (PG8LEV) H'0080 0766 (Use inhibited area) P7 Peripheral Function Select Register 8-14 (P7SMOD)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

8.3.1 Port Data Registers

P0 Data Register (P0DATA) <Address: H’0080 0700> P1 Data Register (P1DATA) <Address: H’0080 0701> P2 Data Register (P2DATA) <Address: H’0080 0702> P3 Data Register (P3DATA) <Address: H’0080 0703> P4 Data Register (P4DATA) <Address: H’0080 0704> P6 Data Register (P6DATA) <Address: H’0080 0706> P7 Data Register (P7DATA) <Address: H’0080 0707> P8 Data Register (P8DATA) <Address: H’0080 0708> P9 Data Register (P9DATA) <Address: H’0080 0709> P10 Data Register (P10DATA) <Address: H’0080 070A> P11 Data Register (P11DATA) <Address: H’0080 070B> P12 Data Register (P12DATA) <Address: H’0080 070C> P13 Data Register (P13DATA) <Address: H’0080 070D> P15 Data Register (P15DATA) <Address: H’0080 070F> P17 Data Register (P17DATA) <Address: H’0080 0711> P22 Data Register (P22DATA) <Address: H’0080 0716> n = 0–13, 15, 17, 22 (not including P5) <Upon exiting reset: Undefined> b Bit Name Function R W 0(b8) Pn0DT (Port Pn0 data bit) <At read> R W 1(b9) Pn1DT (Port Pn1 data bit) Depends on how the Port Direction Register is set 2(b10) Pn2DT (Port Pn2 data bit) If direction bit = "0" (input mode) 3(b11) Pn3DT (Port Pn3 data bit) 0: Port input pin = "L" 4(b12) Pn4DT (Port Pn4 data bit) 1: Port input pin = "H" 5(b13) Pn5DT (Port Pn5 data bit) If direction bit = "1" (output mode) (Note 1) 6(b14) Pn6DT (Port Pn6 data bit) 0: Port output latch = "0" / Port pin level = "L" 7(b15) Pn7DT (Port Pn7 data bit) 1: Port output latch = "1" / Port pin level = "H" <At write> Write to the port output latch Note 1: To select the port data to read, use the Port Input Special Function Control Register’s port input data select bit (PISEL). Notes: Following bits are not provided (read as "0", writing has no effect): P40, P60, P65–P67, P90–P92, P120–P123, P151, P152, P154–P157, P170–P173, P176, P177, P222–P224, P226, P227 The SBI# pin level can be read out by reading the P64DT bit. Writing to the P64DT bit has no effect. The MOD0 and MOD1 pin levels can be read out by reading the P80DT and P81DT bits, respectively. Writing to the P80DT and P81DT bits has no effect. P221 is an input-only port. Writing to the P221DT bit has no effect. (b8 9 10 11 12 13 14 b15) Pn0DT Pn1DT Pn2DT Pn3DT Pn4DT Pn5DT Pn6DT Pn7DT

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

8.3.2 Port Direction Registers

P0 Direction Register (P0DIR) <Address: H’0080 0720> P1 Direction Register (P1DIR) <Address: H’0080 0721> P2 Direction Register (P2DIR) <Address: H’0080 0722> P3 Direction Register (P3DIR) <Address: H’0080 0723> P4 Direction Register (P4DIR) <Address: H’0080 0724> P6 Direction Register (P6DIR) <Address: H’0080 0726> P7 Direction Register (P7DIR) <Address: H’0080 0727> P8 Direction Register (P8DIR) <Address: H’0080 0728> P9 Direction Register (P9DIR) <Address: H’0080 0729> P10 Direction Register (P10DIR) <Address: H’0080 072A> P11 Direction Register (P11DIR) <Address: H’0080 072B> P12 Direction Register (P12DIR) <Address: H’0080 072C> P13 Direction Register (P13DIR) <Address: H’0080 072D> P15 Direction Register (P15DIR) <Address: H’0080 072F> P17 Direction Register (P17DIR) <Address: H’0080 0731> P22 Direction Register (P22DIR) <Address: H’0080 0736> n = 0–13, 15, 17, 22 (not including P5) <Upon exiting reset: H’00> b Bit Name Function R W 0(b8) Pn0DR (Port Pn0 direction bit) 0: Input mode R W 1(b9) Pn1DR (Port Pn1 direction bit) 1: Output mode 2(b10) Pn2DR (Port Pn2 direction bit) 3(b11) Pn3DR (Port Pn3 direction bit) 4(b12) Pn4DR (Port Pn4 direction bit) 5(b13) Pn5DR (Port Pn5 direction bit) 6(b14) Pn6DR (Port Pn6 direction bit) 7(b15) Pn7DR (Port Pn7 direction bit) Notes: Following bits are not provided (read as 0, writing has no effect): P40, P60, P64–P67, P80, P81, P90–P92, P120–P123, P151, P152, P154–P157, P170–P173, P176, P177, P221, P222-–P224, P226, P227 All ports are set for input mode upon exiting the reset state. b 0 123456 b 7 (b8 9 10 11 12 13 14 b15) Pn0DIR Pn1DIR Pn2DIR Pn3DIR Pn4DIR Pn5DIR Pn6DIR Pn7DIR 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

8.3.3 Port Operation Mode Registers

P7 Operation Mode Register (P7MOD) <Address: H’0080 0747> <Upon exiting reset: H’00> b Bit Name Function R W

8 P70MOD 0: P70 R W

Port P70 operation mode bit (Note 2) 1: BCLK/WR#

9 P71MOD 0: P71 R W

Port P71 operation mode bit 1: WAIT#

10 P72MOD 0: P72 R W

Port P72 operation mode bit 1: HREQ#

11 P73MOD 0: P73 R W

Port P73 operation mode bit 1: HACK#

12 P74MOD 0: P74 R W

Port P74 operation mode bit 1: RTDTXD/TXD3 (Note 1)

13 P75MOD 0: P75 R W

Port P75 operation mode bit 1: RTDRXD/RXD3 (Note 1)

14 P76MOD 0: P76 R W

Port P76 operation mode bit 1: RTDACK/CTX1 (Note 1)

15 P77MOD 0: P77 R W

Port P77 operation mode bit 1: RTDCLK/CRX1 (Note 1) Note 1: These functions are selected using the P7 Peripheral Function Select Register. Note 2: When BUSMOD bit of the BUSMODC register is set to 1 (byte enable separate mode) in the external extension mode, regardless of setting P7MOD register , P70/BCLK/WR# pin becomes a pin to output WR# signal. P8 Operation Mode Register (P8MOD) <Address: H’0080 0748> <Upon exiting reset: H’00> b Bit Name Function R W 0,1 No function assigned. Fix to "0". 00

2 P82MOD 0: P82 R W

Port P82 operation mode bit 1: TXD0

3 P83MOD 0: P83 R W

Port P83 operation mode bit 1: RXD0

4 P84MOD 0: P84 R W

Port P84 operation mode bit 1: SCLKI0/SCLKO0

5 P85MOD 0: P85 R W

Port P85 operation mode bit 1: TXD1

6 P86MOD 0: P86 R W

Port P86 operation mode bit 1: RXD1

7 P87MOD 0: P87 R W

Port P87 operation mode bit 1: SCLKI1/SCLKO1 Note: Ports P80 and P81 are nonexistent. b 8 9 1 01 11 21 31 4 b 1 5 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD 00000000 b 0 123456 b 7 P82MOD P83MOD P84MOD P85MOD P86MOD P87MOD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 P9 Operation Mode Register (P9MOD) <Address: H’0080 0749> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 P93MOD 0: P93 R W

Port P93 operation mode bit 1: TO16

12 P94MOD 0: P94 R W

Port P94 operation mode bit 1: TO17

13 P95MOD 0: P95 R W

Port P95 operation mode bit 1: TO18

14 P96MOD 0: P96 R W

Port P96 operation mode bit 1: TO19

15 P97MOD 0: P97 R W

Port P97 operation mode bit 1: TO20 Note: Ports P90–P92 are nonexistent. P10 Operation Mode Register (P10MOD) <Address: H’0080 074A> <Upon exiting reset: H’00> b Bit Name Function R W

0 P100MOD 0: P100 R W

Port P100 operation mode bit 1: TO8

1 P101MOD 0: P101 R W

Port P101 operation mode bit 1: TO9

2 P102MOD 0: P102 R W

Port P102 operation mode bit 1: TO10

3 P103MOD 0: P103 R W

Port P103 operation mode bit 1: TO11

4 P104MOD 0: P104 R W

Port P104 operation mode bit 1: TO12

5 P105MOD 0: P105 R W

Port P105 operation mode bit 1: TO13

6 P106MOD 0: P106 R W

Port P106 operation mode bit 1: TO14

7 P107MOD 0: P107 R W

Port P107 operation mode bit 1: TO15 b 8 9 1 01 11 21 31 4 b 1 5 P93MOD P94MOD P95MOD P96MOD P97MOD 00000000 b 0 123456 b 7 P100MOD P101MOD P102MOD P103MOD P104MOD P105MOD P106MOD P107MOD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 P11 Operation Mode Register (P11MOD) <Address: H’0080 074B> <Upon exiting reset: H’00> b Bit Name Function R W

8 P110MOD 0: P110 R W

Port P110 operation mode bit 1: TO0

9 P111MOD 0: P111 R W

Port P111 operation mode bit 1: TO1

10 P112MOD 0: P112 R W

Port P112 operation mode bit 1: TO2

11 P113MOD 0: P113 R W

Port P113 operation mode bit 1: TO3

12 P114MOD 0: P114 R W

Port P114 operation mode bit 1: TO4

13 P115MOD 0: P115 R W

Port P115 operation mode bit 1: TO5

14 P116MOD 0: P116 R W

Port P116 operation mode bit 1: TO6

15 P117MOD 0: P117 R W

Port P117 operation mode bit 1: TO7 P12 Operation Mode Register (P12MOD) <Address: H’0080 074C> <Upon exiting reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00

4 P124MOD 0: P124 R W

Port P124 operation mode bit 1: TCLK0

5 P125MOD 0: P125 R W

Port P125 operation mode bit 1: TCLK1

6 P126MOD 0: P126 R W

Port P126 operation mode bit 1: TCLK2

7 P127MOD 0: P127 R W

Port P127 operation mode bit 1: TCLK3 Note: Ports P120–P123 are nonexistent. P124MOD P125MOD P126MOD P127MOD 00000000 b 8 9 1 01 11 21 31 4 b 1 5 P110MOD P111MOD P112MOD P113MOD P114MOD P115MOD P116MOD P117MOD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 P13 Operation Mode Register (P13MOD) <Address: H’0080 074D> <Upon exiting reset: H’00> b Bit Name Function R W

8 P130MOD 0: P130 R W

Port P130 operation mode bit 1: TIN16

9 P131MOD 0: P131 R W

Port P131 operation mode bit 1: TIN17

10 P132MOD 0: P132 R W

Port P132 operation mode bit 1: TIN18

11 P133MOD 0: P133 R W

Port P133 operation mode bit 1: TIN19

12 P134MOD 0: P134 R W

Port P134 operation mode bit 1: TIN20

13 P135MOD 0: P135 R W

Port P135 operation mode bit 1: TIN21

14 P136MOD 0: P136 R W

Port P136 operation mode bit 1: TIN22

15 P137MOD 0: P137 R W

Port P137 operation mode bit 1: TIN23 P15 Operation Mode Register (P15MOD) <Address: H’0080 074F> <Upon exiting reset: H’00> b Bit Name Function R W

8 P150MOD 0: P150 R W

Port P150 operation mode bit 1: TIN0 9, 10 No function assigned. Fix to "0". 00

11 P153MOD 0: P153 R W

Port P153 operation mode bit 1: TIN3 12-15 No function assigned. Fix to "0". 00 Note : Ports P151, P152 and P154–P157 are nonexistent. b 8 9 1 01 11 21 31 4 b 1 5 P150MOD P153MOD 00000000 b 8 9 1 01 11 21 31 4 b 1 5 P130MOD P131MOD P132MOD P133MOD P134MOD P135MOD P136MOD P137MOD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 P17 Operation Mode Register (P17MOD) <Address: H’0080 0751> <Upon exiting reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00

12 P174MOD 0: P174 R W

Port P174 operation mode bit 1: TXD2

13 P175MOD 0: P175 R W

Port P175 operation mode bit 1: RXD2 14, 15 No function assigned. Fix to "0". 00 Notes: Ports P170–P173, P176 and P177 are nonexistent. P22 Operation Mode Register (P22MOD) <Address: H’0080 0756> <Upon exiting reset: H’00> b Bit Name Function R W

0 P220MOD 0: P220 R W

Port P220 operation mode bit 1: CTX0 1– 7 No function assigned. Fix to "0". 00 Note 1: Port P221 is a CAN input-only pin. Note 2: The pin function for P225 changes depending on the MOD0 and MOD1pin settings. Note 3: Ports P222–P224, P226 and P227 are nonexistent. b 8 9 1 01 11 21 31 4 b 1 5 P174MOD P175MOD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

8.3.4 Port Peripheral Function Select Register

P7 Peripheral Function Select Register (P7SMOD) <Address: H’0080 0767> <Upon exiting reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00

12 P74SMOD 0: RTDTXD R W

Port P74 peripheral function select bit 1: TXD3

13 P75SMOD 0: RTDRXD R W

Port P75 peripheral function select bit 1: RXD3

14 P76SMOD 0: RTDACK R W

Port P76 peripheral function select bit 1: CTX1

15 P77SMOD 0: RTDCLK R W

Port P77 peripheral function select bit 1: CRX1 The P7 Peripheral Function Select Register is used to select a peripheral function when the corresponding bit in the P7 Operation Mode Register = "1". To use this register, first rewrite it when the P7 Operation Mode Register = "0", and then set the P7 Operation Mode Register to "1" to enable peripheral functions. b 8 9 1 01 11 21 31 4 b 1 5 P74SMOD P75SMOD P76SMOD P77SMOD 00000000

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

8.3.5 Port Input Special Function Control Register

Port Input Special Function Control Register (PICNT) <Address: H’0080 0745> 9 1 01 11 21 31 4 b 1 5b8 PIEN0PISELXSTAT 0 000 0 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 XSTAT 0: XIN oscillating R (Note 1)

XIN oscillation status bit 1: XIN inactive 12, 13 No function assigned. Fix to "0". 00

14 PISEL 0: Content of port output latch R W

Port input data select bit 1: Port pin level

15 PIEN0 0: Disable input R W

Port input enable bit 1: Enable input Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. (1) XSTAT (XIN oscillation status) bit (Bit 11) 1) Conditions under which XSTAT is set to "1" XSTAT is set to "1" upon detecting that XIN oscillation has stopped. When XIN remains at the same level for a predetermined time (3 BCLK periods up to 4 BCLK periods), XIN oscillation is assumed to have stopped. When operating normally, XIN changes state ("H" or "L") once every BCLK period. 2) Conditions under which XSTAT is cleared to "0" XSTAT is cleared to "0" by a system reset or by writing "0". If XSTAT is cleared at the same time it is set in (1) above, the former has priority. Writing "1" to XSTAT is ignored. 3) Method for using XSTAT to detect XIN oscillation stoppage Because the M32R/ECU internally contains a PLL, the internal clock remains active even when XIN oscilla- tion has stopped. By reading XSTAT without clearing it never once after reset, it is possible to know whether XIN has ever stopped since the reset signal was deasserted. Similarly, by reading XSTAT after clearing it by writing "0", it is possible to know the current oscillating status of XIN. However, there must be an interval of at least 10 BCLK periods (20 CPU clock periods) between read and write. Pay attention about processing when XSTAT bit is set to "1," make double check after clearing XSTAT bit etc.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (1) To know whether XIN oscillation has ever stopped after being reset Write XSTAT = 0 (2) To know the current status of XIN oscillation Wait for 20 CPU clock periods or more Read XSTAT Wait before inspecting XSTAT Note. Pay attention about processing when XSTAT bit is set to "1," make double check after clearing XSTAT bit etc. Figure 8.3.1 Procedure for Setting XSTAT (2) PISEL (Port input data select) bit (Bit 14) When the Port Direction Register is set for output, this bit selects the target data to be read from the Port Data Register. At this time, this bit is unaffected by the Port Operation Mode Register. Table 8.3.1 PISEL Bit Settings and the Target Data To Be Read from the Port Data Register Direction Register PISEL Settings Target Data to Be Read 0 (input) 0/1 Port pin level 1 (output) 0 Port output latch

1 Port pin level

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (3) PIEN0 (Port input enable) bit (Bit 15) This bit is used to prevent current from flowing into the port input pins. Because the input/output ports are disabled against input after reset, if any ports need to be used in input mode they must be enabled for input by setting this bit to "1". When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a "L" level input applied. Consequently, if a peripheral input function is selected for any port while disabled against input by using the Port Operation Mode Register, the port may operate unexpectedly due to the "L" level input on it. The following shows the procedure for selecting a peripheral input function. (1) Enable the port for input when its pin level is valid ("H" or "L") (2) Select a function using the port operation mode bit During boot mode, the pins shared with serial interface functions are enabled for input and can therefore be protected against current flowing in from the pins other than serial interface functions during flash program- ming by clearing PIEN0. The table below lists the pins that can be controlled by the PIEN0 bit in each operation mode. Table 8.3.2 Pins Controllable by PIEN0 Bit Mode Name Controllable Pins Uncontrolled Pins P00–P07, P10–P17, P20–P27 P221, FP, SBI#, MOD0, MOD1, MOD2, RESET# P30–P37, P41–P47, P61–P63 Single-chip P70–P77, P82–P87, P93–P97 P100–P107, P110–P117, P124–P127 P130–P137, 150, P153, P174, P175 P220, P225 P61–P63, P70–P77, P82–P87 P00–P07, P10–P17 External extension P93–P97, P100–P107, P110–P117 P20–P27, P30–P37 Microprocessor P124–P127, P130–P137 P41–P47, P221, P225 P150, P153, P174, P175, P220 FP, SBI#, MOD0, MOD1, MOD2, RESET# P00–P07, P10–P17, P20–P27 P82–P87, P174, P175 Boot P30–P37, P41–P47, P61–P63 P221, FP, SBI#, MOD0, MOD1, MOD2, RESET# (single-chip) P67, P70–P77, P93–P97 P100–P107, P110–P117, P124–P127 P130–P137, P150, P153, P220, P225

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The port input level switching function allows the port threshold to be switched to one of three voltage levels (with or without Schmitt as selected) in units of the following port group. This can be set to the following registers in units of group. Group 0: P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P70–P73, P225 Group 1: P82–P87, P174–P177 Group 3: P93–P97, P110–P117 Group 4: P124–P127 Group 5: P61–P63, SBI# Group 6: P74–P77, P100–P107 Group 7: P220, P221 Group 8: P130–P137, P150–P153 Figure 8.4.1 Port Level Switching Function VT+ VT- Schmitt Peripheral function input Port input Pin 0.7VCCE 0.5VCCE 0.35VCCE CMOS S S S S S WFnSEL PTnSEL VTnSEL Threshold Input function enable Standard input level for each peripheral function pin PIEN0

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-1932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Port Group 0,1 Input Level Setting Register (PG01LEV) <Address: H’0080 0760> Port Group 3 Input Level Setting Register (PG3LEV) <Address: H’0080 0761> Note: The PG3LEV register bits 8–11 have no functions assigned. Port Group 4,5 Input Level Setting Register (PG45LEV) <Address: H’0080 0762> Port Group 6,7 Input Level Setting Register (PG67LEV) <Address: H’0080 0763> Port Group 8 Input Level Setting Register (PG8LEV) <Address: H’0080 0764> Note: The PG8LEV register bits 4–7 have no functions assigned. b 8 9 1 01 11 21 31 4 b 1 5 WF3SEL PT3SEL VT3SEL0 VT3SEL1 00000001 b 0 123456 b 7 WF0SEL PT0SEL VT0SEL0 VT0SEL1 WF1SEL PT1SEL VT1SEL0 VT1SEL1 00010001 b 0 123456 b 7 WF4SEL PT4SEL VT4SEL0 VT4SEL1 WF5SEL PT5SEL VT5SEL0 VT5SEL1 00010001 b 8 9 1 01 11 21 31 4 b 1 5 WF6SEL PT6SEL VT6SEL0 VT6SEL1 WF7SEL PT7SEL VT7SEL0 VT7SEL1 00010001 b 0 123456 b 7 WF8SEL PT8SEL VT8SEL0 VT8SEL1 00010000 <Upon exiting reset: :H'11, H'01, H'10> (Note 2) b Bit Name Function R W 0(8) WFnSEL (Note 1) 0: Select standard input for each pin R W Group n dual-function input select bit 1: Select threshold switching function 1–3 PTnSEL 000 : Input CMOS, Select 0.35VCCE R W (9–11) (Group n port input select bit ) 001 : Input CMOS, Select 0.50VCCE VTnSEL0, VTnSEL1 010 : Input CMOS, Select 0.70VCCE (Group n input threshold select bit) 011 : Settings inhibited 100 : Schmitt input , VT += 0.50VCCE, VT -= 0.35VCCE 101 : Settings inhibited 110 : Schmitt input , VT += 0.70VCCE, VT -= 0.35VCCE 111 : Schmitt input , VT += 0.70VCCE, VT -= 0.50VCCE 4(12) WFnSEL (Note 1) 0: Select standard input for each pin R W Group n dual-function input select bit 1: Select threshold switching function 5–7 PTnSEL 000 : Input CMOS, Select 0.35VCCE R W (13 –15) (Group n port input select bit) 001 : Input CMOS, Select 0.50VCCE VTnSEL0, VTnSEL1 010 : Input CMOS, Select 0.70VCCE (Group n input threshold select bit) 011 : Settings inhibited 100 : Schmitt input , VT += 0.50VCCE, AVT -= 0.35VCCE 101 : Settings inhibited 110 : Schmitt input , VT += 0.70VCCE, AVT -= 0.35VCCE 111 : Schmitt input , VT += 0.70VCCE, AVT -= 0.50VCCE Note 1.When the multipurpose port function pin is selected (Set bit corresponding Px operation mode register(PxMOD) to "0".), setting value for WFnSEL is invalid and threshold switch function is effective. Note 2. Upon exiting reset, VTnSEL1 bit value is "1" and the other bit is set to "0" .

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figures 8.5.1 through 8.5.5 show the peripheral circuit diagrams of the input/output ports described in the pre- ceding pages. Figure 8.5.1 Port Peripheral Circuit Diagram (1) P00–P07(DB0–DB7) P10–P17(DB8–DB15) P20–P27(A23–A30) P30–P37(A15–A22) P41(BLW#/BLE#) P42(BHW#/BHE#) P43(RD#) P44(CS0#) P45(CS1#) P46–P47(A13–A14) P61–P63 P225(A12) P83(RXD0) P86(RXD1) P124–P127(TCLK0–TCLK3) P150, P153(TIN0, TIN3) P175(RXD2) Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Note 2: "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Notes: During external extension and processor modes, P00-P07, P10-P17, P20-P27, P30-P37, P41-P47, and P225 are external bus interface control signal pins, but their functional description in this block diagram is omitted. The circle denotes a pin. The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. The input capacitance of each pin is approximately 10 pF. Data bus Data bus Port output latch Input function enable Peripheral function input (Note 2) Direction register Direction register Port output latch Operation mode register Port level switching function (Standard: peripheral TTL) (Note 1) (Note 1) Input function enable Port level switching function (Standard: peripheral schmitt) P130–P137(TIN16–TIN23)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 8.5.2 Port Peripheral Circuit Diagram (2) SBI# P221/CRX0 Data bus SBI# , CRX0 (Note 2) P72(HREQ#) HREQ# Data bus Direction register Port output latch Operation mode register Port level switching function (Standard: peripheral schmitt) (Note 1) Port level switching function (Standard: peripheral schmitt) (Note 1) P71(WAIT#) Data bus WAIT# (Note 2) Direction register Port output latch Operation mode register Port level switching function (Standard: peripheral schmitt) Input function enable (Note 1) Input function enable Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Note 2: "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Notes: The circle denotes a pin. The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. The input capacitance of each pin is approximately 10 pF.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 P70(BCLK/WR#) P73(HACK#) P82(TXD0) P85(TXD1) P93–P97(TO16–TO20) P100–P107(TO8–TO15) P110–P117(TO0–TO7) P174(TXD2) P220(CTX0) Data bus Peripheral function output Direction register Port output latch Operation mode register Port level switching function (Standard: peripheral schmitt) Input function enable (Note 1) P84(SCLKI0,SCLKO0) P87(SCLKI1,SCLKO1) Data bus SCLKIi input (Note 2) SCLKOi output Direction register Port output latch Operation mode register Port level switching function (Standard: peripheral schmitt) Input function enable (Note 1) UART/CSIO function select bit Internal/external clock select bit Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Note 2: "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Notes: The circle denotes a pin. The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. The input capacitance of each pin is approximately 10 pF. Figure 8.5.3 Port Peripheral Circuit Diagram (3)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 8.5.4 Port Peripheral Circuit Diagram (4) P75(RTDRXD/RXD3) P77(RTDCLK/CRX1) P74(RTDTXD/TXD3) P76(RTDACK/CTX1) Data bus Peripheral function input 2 (Note 2) Peripheral function input 1 (Note 2) Direction register Port output latch Operation mode register Port level switching function (Standard: peripheral schmitt) Input function enable (Note 1) P7 peripheral function select register Data bus Peripheral function output 2 Peripheral function output 1 Direction register Port output latch Operation mode register Port level switching function (Standard: no peripheral input) Input function enable (Note 1) P7 peripheral function select register Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Note 2: "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Notes: The circle denotes a pin. The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. The input capacitance of each pin is approximately 10 pF.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 8.5.5 Port Peripheral Circuit Diagram (5) RESET# XIN JTRST RESET#, XIN, JTRST MOD0 MOD1 FP MOD0, MOD1, FP JTDI JTCK JTMS JTDI, JTCK, JTMS JTDO JTDO VCCI VCCE VDD AVCC0 VCCI, VCCE, VDD , AVCC0 AD0IN0–15 VREF0 XOUT AD0IN0–15, VREF0, XOUT Notes: The circle denotes a pin. The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. The input capacitance of each pin is approximately 10 pF.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

When using input/output ports in output mode Because the value of the Port Data Register is undefined when exiting the reset state, the Port Data Register must have its initial value set in it before the Port Direction Register can be set for output. Conversely, if the Port Direction Register is set for output before setting data in the Port Data Register, the Port Data Register outputs an undefined value until any data is written into it.
About the port input disable function Because the input/output ports are disabled against input after reset, they must be enabled for input by setting the Port Input Enable (PIEN0) bit to "1" before their input functions can be used. When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a "L" level input applied. Consequently, if a peripheral input function is selected for any port while disabled against input by using the Port Operation Mode Register, the port may operate unexpectedly due to the "L" level input on it.
About the peripheral function input when it is set to the general purpose port In the pin for both peripheral function input and general-purpose port, "H" level is entered to the peripheral function input when it is set to the general-purpose port in the operation mode register. Therefore, when "L" level is entered to the peripheral function input pin, edge signal is entered to the peripheral function input at manipulating operation mode register.

INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8-2632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 This page is blank for reasons of layout.

9.1 Outline of the DMAC

9.2 DMAC Related Registers

9.3 Functional Description of the DMAC

9.4 Notes on the DMAC

9-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The microcomputer internally contains a 10-channel DMAC (Direct Memory Access Controller). It allows data to be transferred at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, or between internal RAMs, as initiated by a software trigger or requested from an internal peripheral I/O. Table 9.1.1 Outline of the DMAC Item Description Number of channels 10 channels Transfer request sources • Software trigger Request from internal peripheral I/Os: A/D converter, multijunction timer, serial interface (reception completed, transmit buffer empty) or CAN DMA channels can be cascaded (Note 1) Maximum number of 256 times times transferred Transferable address 64 Kbytes (address space from H’0080 0000 to H’0080 FFFF) space Transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs are supported. Transfer data size 16 or 8 bits Transfer method Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual- address transfer Transfer mode Single transfer mode Direction of transfer One of three modes can be selected for the source and destination: Address fixed Address incremental Ring buffered Channel priority DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9 (Priority is fixed) Maximum transfer rate 13.3 Mbytes per second (when internal peripheral clock BCLK = 20 MHz) Interrupt request Group interrupt request can be generated when each transfer count register underflows. Transfer area 64 Kbytes from H’0080 0000 to H’0080 FFFF Note 1: The DMA channels can be cascaded in the manner described below. Start DMA transfer on DMA1 upon completion of one DMA transfer on DMA0 Start DMA transfer on DMA2 upon completion of one DMA transfer on DMA1 Start DMA transfer on DMA0 upon completion of one DMA transfer on DMA2 Start DMA transfer on DMA4 upon completion of one DMA transfer on DMA3 Start DMA transfer on DMA6 upon completion of one DMA transfer on DMA5 Start DMA transfer on DMA7 upon completion of one DMA transfer on DMA6 Start DMA transfer on DMA5 upon completion of one DMA transfer on DMA7 Start DMA transfer on DMA9 upon completion of one DMA transfer on DMA8 Start DMA transfer on DMA5 upon completion of all DMA transfers on DMA0 (upon underflow of the transfer count register)

9-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 9.1.1 Block Diagram of the DMAC S S S S S S S S S (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) A/D0 conversion completed TIO8_udf Software start Software start Software start SIO0_TXD SIO1_RXD Software start SIO0_RXD Software start Software start DMA0–4 interrupt DMA5–9 interrupt SIO2_RXD SIO1_TXD Software start SIO2_TXD Software start SIO3_RXD Software start CAN0_S0/S15 (Note 1) TIN0S (Note 1) TIN19S (Note 1) TIN20S SIO3_TXD Software start (Note 1) TIN18S CAN0_S1/S14 CAN1_S0/S15 CAN1_S1/S14 Note 1: Indicates edge select output at the timer input pin. Note 2: Indicates an input signal from each peripheral circuit. 0123 Input event bus Output event bus 3210 3210 0123

9-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The diagram below shows a memory map of the DMAC related registers. DMAC Related Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0400 DMA0–4 Interrupt Request Status Register DMA0–4 Interrupt Request Mask Register 9-18 (DM04ITST) (DM04ITMK) 9-19 (Use inhibited area) H'0080 0408 DMA5–9 Interrupt Request Status Register DMA5–9 Interrupt Request Mask Register 9-18 (DM59ITST) (DM59ITMK) 9-19 (Use inhibited area) H'0080 0410 DMA0 Channel Control Register DMA0 Transfer Count Register 9-6 (DM0CNT) (DM0TCT) 9-15 H'0080 0412 DMA0 Source Address Register 9-13 (DM0SA) H'0080 0414 DMA0 Destination Address Register 9-14 (DM0DA) H'0080 0416 (Use inhibited area) H'0080 0418 DMA5 Channel Control Register DMA5 Transfer Count Register 9-8 (DM5CNT) (DM5TCT) 9-15 H'0080 041A DMA5 Source Address Register 9-13 (DM5SA) H'0080 041C DMA5 Destination Address Register 9-14 (DM5DA) H'0080 041E (Use inhibited area) H'0080 0420 DMA1 Channel Control Register DMA1 Transfer Count Register 9-6 (DM1CNT) (DM1TCT) 9-15 H'0080 0422 DMA1 Source Address Register 9-13 (DM1SA) H'0080 0424 DMA1 Destination Address Register 9-14 (DM1DA) H'0080 0426 (Use inhibited area) H'0080 0428 DMA6 Channel Control Register DMA6 Transfer Count Register 9-9 (DM6CNT) (DM6TCT) 9-15 H'0080 042A DMA6 Source Address Register 9-13 (DM6SA) H'0080 042C DMA6 Destination Address Register 9-14 (DM6DA) H'0080 042E (Use inhibited area) H'0080 0430 DMA2 Channel Control Register DMA2 Transfer Count Register 9-7 (DM2CNT) (DM2TCT) 9-15 H'0080 0432 DMA2 Source Address Register 9-13 (DM2SA) H'0080 0434 DMA2 Destination Address Register 9-14 (DM2DA) H'0080 0436 (Use inhibited area) H'0080 0438 DMA7 Channel Control Register DMA7 Transfer Count Register 9-9 (DM7CNT) (DM7TCT) 9-15 H'0080 043A DMA7 Source Address Register 9-13 (DM7SA) H'0080 043C DMA7 Destination Address Register 9-14 (DM7DA) H'0080 043E (Use inhibited area)

9-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 DMAC Related Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0440 DMA3 Channel Control Register DMA3 Transfer Count Register 9-7 (DM3CNT) (DM3TCT) 9-15 H'0080 0442 DMA3 Source Address Register 9-13 (DM3SA) H'0080 0444 DMA3 Destination Address Register 9-14 (DM3DA) H'0080 0446 (Use inhibited area) H'0080 0448 DMA8 Channel Control Register DMA8 Transfer Count Register 9-10 (DM8CNT) (DM8TCT) 9-15 H'0080 044A DMA8 Source Address Register 9-13 (DM8SA) H'0080 044C DMA8 Destination Address Register 9-14 (DM8DA) H'0080 044E (Use inhibited area) H'0080 0450 DMA4 Channel Control Register DMA4 Transfer Count Register 9-8 (DM4CNT) (DM4TCT) 9-15 H'0080 0452 DMA4 Source Address Register 9-13 (DM4SA) H'0080 0454 DMA4 Destination Address Register 9-14 (DM4DA) H'0080 0456 (Use inhibited area) H'0080 0458 DMA9 Channel Control Register DMA9 Transfer Count Register 9-10 (DM9CNT) (DM9TCT) 9-15 H'0080 045A DMA9 Source Address Register 9-13 (DM9SA) H'0080 045C DMA9 Destination Address Register 9-14 (DM9DA) H'0080 045E (Use inhibited area) H'0080 0460 DMA0 Software Request Generation Register 9-12 (DM0SRI) H'0080 0462 DMA1 Software Request Generation Register 9-12 (DM1SRI) H'0080 0464 DMA2 Software Request Generation Register 9-12 (DM2SRI) H'0080 0466 DMA3 Software Request Generation Register 9-12 (DM3SRI) H'0080 0468 DMA4 Software Request Generation Register 9-12 (DM4SRI) (Use inhibited area) H'0080 0470 DMA5 Software Request Generation Register 9-12 (DM5SRI) H'0080 0472 DMA6 Software Request Generation Register 9-12 (DM6SRI) H'0080 0474 DMA7 Software Request Generation Register 9-12 (DM7SRI) H'0080 0476 DMA8 Software Request Generation Register 9-12 (DM8SRI) H'0080 0478 DMA9 Software Request Generation Register 9-12 (DM9SRI)

9-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

9.2.1 DMA Channel Control Registers

DMA0 Channel Control Register (DM0CNT) <Address: H’0080 0410> <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL0 0: Normal mode R W

DMA0 transfer mode select bit 1: Ring buffer mode

1 TREQF0 0: Transfer not requested R(Note 1)

DMA0 transfer request flag bit 1: Transfer requested 2, 3 REQSL0 00: Software start or one DMA2 transfer completed R W DMA0 transfer request source select bit 01: A/D0 conversion completed 10: MJT (TIO8_udf) 11: MJT (input event bus 2)

4 TENL0 0: Disable transfer R W

DMA0 transfer enable bit 1: Enable transfer

5 TSZSL0 0: 16 bits R W

DMA0 transfer size select bit 1: 8 bits

6 SADSL0 0: Fixed R W

DMA0 source address direction select bit 1: Increment

7 DADSL0 0: Fixed R W

DMA0 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA1 Channel Control Register (DM1CNT) <Address: H’0080 0420> <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL1 0: Normal mode R W

DMA1 transfer mode select bit 1: Ring buffer mode

1 TREQF1 0: Transfer not requested R(Note 1)

DMA1 transfer request flag bit 1: Transfer requested 2, 3 REQSL1 00: Software start R W DMA1 transfer request source select bit 01: MJT (output event bus 0) 10: Settings inhibited 11: One DMA0 transfer completed

4 TENL1 0: Disable transfer R W

DMA1 transfer enable bit 1: Enable transfer

5 TSZSL1 0: 16 bits R W

DMA1 transfer size select bit 1: 8 bits

6 SADSL1 0: Fixed R W

DMA1 source address direction select bit 1: Increment

7 DADSL1 0: Fixed R W

DMA1 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MDSEL0 TREQF0 REQSL0 TENL0 TSZSL0 SADSL0 DADSL0 00000000 b 0 123456 b 7 MDSEL1 TREQF1 REQSL1 TENL1 TSZSL1 SADSL1 DADSL1 00000000

9-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 DMA2 Channel Control Register (DM2CNT) <Address: H’0080 0430> <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL2 0: Normal mode R W

DMA2 transfer mode select bit 1: Ring buffer mode

1 TREQF2 0: Transfer not requested R(Note 1)

DMA2 transfer request flag bit 1: Transfer requested 2, 3 REQSL2 00: Software start R W DMA2 transfer request source select bit 01: MJT (output event bus 1) 10: MJT (TIN18S) 11: One DMA1 transfer completed

4 TENL2 0: Disable transfer R W

DMA2 transfer enable bit 1: Enable transfer

5 TSZSL2 0: 16 bits R W

DMA2 transfer size select bit 1: 8 bits

6 SADSL2 0: Fixed R W

DMA2 source address direction select bit 1: Increment

7 DADSL2 0: Fixed R W

DMA2 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA3 Channel Control Register (DM3CNT) <Address: H’0080 0440> <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL3 0: Normal mode R W

DMA3 transfer mode select bit 1: Ring buffer mode

1 TREQF3 0: Transfer not requested R(Note 1)

DMA3 transfer request flag bit 1: Transfer requested 2, 3 REQSL3 00: Software start R W DMA3 transfer request source select bit 01: SIO0_TXD (transmit buffer empty) 10: SIO1_RXD (reception completed) 11: MJT (TIN0S)

4 TENL3 0: Disable transfer R W

DMA3 transfer enable bit 1: Enable transfer

5 TSZSL3 0: 16 bits R W

DMA3 transfer size select bit 1: 8 bits

6 SADSL3 0: Fixed R W

DMA3 source address direction select bit 1: Increment

7 DADSL3 0: Fixed R W

DMA3 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MDSEL2 TREQF2 REQSL2 TENL2 TSZSL2 SADSL2 DADSL2 00000000 b 0 123456 b 7 MDSEL3 TREQF3 REQSL3 TENL3 TSZSL3 SADSL3 DADSL3 00000000

9-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 DMA4 Channel Control Register (DM4CNT) <Address: H’0080 0450> <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL4 0: Normal mode R W

DMA4 transfer mode select bit 1: Ring buffer mode

1 TREQF4 0: Transfer not requested R(Note 1)

DMA4 transfer request flag bit 1: Transfer requested 2, 3 REQSL4 00: Software start R W DMA4 transfer request source select bit 01: One DMA3 transfer completed 10: SIO0_RXD (reception completed) 11: MJT (TIN19S)

4 TENL4 0: Disable transfer R W

DMA4 transfer enable bit 1: Enable transfer

5 TSZSL4 0: 16 bits R W

DMA4 transfer size select bit 1: 8 bits

6 SADSL4 0: Fixed R W

DMA4 source address direction select bit 1: Increment

7 DADSL4 0: Fixed R W

DMA4 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA5 Channel Control Register (DM5CNT) <Address: H’0080 0418> <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL5 0: Normal mode R W

DMA5 transfer mode select bit 1: Ring buffer mode

1 TREQF5 0: Transfer not requested R(Note 1)

DMA5 transfer request flag bit 1: Transfer requested 2, 3 REQSL5 00: Software start or one DMA7 transfer completed R W DMA5 transfer request source select bit 01: All DMA0 transfers completed 10: SIO2_RXD (reception completed) 11: MJT (TIN20S)

4 TENL5 0: Disable transfer R W

DMA5 transfer enable bit 1: Enable transfer

5 TSZSL5 0: 16 bits R W

DMA5 transfer size select bit 1: 8 bits

6 SADSL5 0: Fixed R W

DMA5 source address direction select bit 1: Increment

7 DADSL5 0: Fixed R W

DMA5 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MDSEL4 TREQF4 REQSL4 TENL4 TSZSL4 SADSL4 DADSL4 00000000 b 0 123456 b 7 MDSEL5 TREQF5 REQSL5 TENL5 TSZSL5 SADSL5 DADSL5 00000000

9-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 DMA6 Channel Control Register (DM6CNT) <Address: H’0080 0428> <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL6 0: Normal mode R W

DMA6 transfer mode select bit 1: Ring buffer mode

1 TREQF6 0: Transfer not requested R(Note 1)

DMA6 transfer request flag bit 1: Transfer requested 2, 3 REQSL6 00: Software start R W DMA6 transfer request source select bit 01: SIO1_TXD (transmit buffer empty) 10: CAN (CAN0_S0/S15) 11: One DMA5 transfer completed

4 TENL6 0: Disable transfer R W

DMA6 transfer enable bit 1: Enable transfer

5 TSZSL6 0: 16 bits R W

DMA6 transfer size select bit 1: 8 bits

6 SADSL6 0: Fixed R W

DMA6 source address direction select bit 1: Increment

7 DADSL6 0: Fixed R W

DMA6 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA7 Channel Control Register (DM7CNT) <Address: H’0080 0438> <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL7 0: Normal mode R W

DMA7 transfer mode select bit 1: Ring buffer mode

1 TREQF7 0: Transfer not requested R(Note 1)

DMA7 transfer request flag bit 1: Transfer requested 2, 3 REQSL7 00: Software start R W DMA7 transfer request source select bit 01: SIO2_TXD (transmit buffer empty) 10: CAN (CAN0_S1/S14) 11: One DMA6 transfer completed

4 TENL7 0: Disable transfer R W

DMA7 transfer enable bit 1: Enable transfer

5 TSZSL7 0: 16 bits R W

DMA7 transfer size select bit 1: 8 bits

6 SADSL7 0: Fixed R W

DMA7 source address direction select bit 1: Increment

7 DADSL7 0: Fixed R W

DMA7 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MDSEL6 TREQF6 REQSL6 TENL6 TSZSL6 SADSL6 DADSL6 00000000 b 0 123456 b 7 MDSEL7 TREQF7 REQSL7 TENL7 TSZSL7 SADSL7 DADSL7 00000000

9-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 DMA8 Channel Control Register (DM8CNT) <Address: H’0080 0448> <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL8 0: Normal mode R W

DMA8 transfer mode select bit 1: Ring buffer mode

1 TREQF8 0: Transfer not requested R(Note 1)

DMA8 transfer request flag bit 1: Transfer requested 2, 3 REQSL8 00: Software start R W DMA8 transfer request source select bit 01: MJT (input event bus 0) 10: SIO3_RXD (reception completed) 11: CAN (CAN1_S0/S15)

4 TENL8 0: Disable transfer R W

DMA8 transfer enable bit 1: Enable transfer

5 TSZSL8 0: 16 bits R W

DMA8 transfer size select bit 1: 8 bits

6 SADSL8 0: Fixed R W

DMA8 source address direction select bit 1: Increment

7 DADSL8 0: Fixed R W

DMA8 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA9 Channel Control Register (DM9CNT) <Address: H’0080 0458> <Upon exiting reset: H’00> b Bit Name Function R W

0 MDSEL9 0: Normal mode R W

DMA9 transfer mode select bit 1: Ring buffer mode

1 TREQF9 0: Transfer not requested R(Note 1)

DMA9 transfer request flag bit 1: Transfer requested 2, 3 REQSL9 00: Software start R W DMA9 transfer request source select bit 01: SIO3_TXD (transmit buffer empty) 10: CAN (CAN1_S1/S14) 11: One DMA8 transfer completed

4 TENL9 0: Disable transfer R W

DMA9 transfer enable bit 1: Enable transfer

5 TSZSL9 0: 16 bits R W

DMA9 transfer size select bit 1: 8 bits

6 SADSL9 0: Fixed R W

DMA9 source address direction select bit 1: Increment

7 DADSL9 0: Fixed R W

DMA9 destination address direction select bit 1: Increment Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MDSEL9 TREQF9 REQSL9 TENL9 TSZSL9 SADSL9 DADSL9 00000000 b 0 123456 b 7 MDSEL8 TREQF8 REQSL8 TENL8 TSZSL8 SADSL8 DADSL8 00000000

9-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The DMA Channel Control Register consists of the bits to select DMA transfer mode on each channel, set the DMA transfer request flag, select the cause or source of DMA request and enable DMA transfer, as well as those to set the transfer size and the source/destination address directions. (1) MDSELn (DMAn Transfer Mode Select) bit (Bit 0) When performing DMA transfer in single transfer mode, this bit selects normal mode or ring buffer mode. Setting this bit to "0" selects normal mode and setting it to "1" selects ring buffer mode. In ring buffer mode, transfer begins from the transfer start address and after performing transfers 32 times, control is returned back to the transfer start address, from which transfer operation is repeated. In this case, the Transfer Count Register counts in free-run mode, during which time transfer operation is continued until the transfer enable bit is reset to "0" (to disable transfer). In ring buffer mode, no interrupt is generated at completion of DMA transfer. (2) TREQFn (DMAn Transfer Request Flag) bit (Bit 1) This flag indicates if there are DMA transfer requests for each channel. This bit is set to "1", when DMA transfer requests are occurred in spite of TENLn bit setting value and then after completing transmission it is cleared to "0." And when write "0" to this bit, it clear DMA transfer requests occurred. When write "1", it keeps value which before writing. If a new DMA transfer request occurs on a channel for which the DMA transfer request flag has already been set to "1", the next DMA transfer request is not accepted until the transfer being performed on that channel is completed. (3) REQSLn (DMAn Transfer Request Source Select) bits (Bits 2–3) These bits select the cause or source of DMA transfer request on each DMA channel. (4) TENLn (DMAn Transfer Enable) bit (Bit 4) When setting this bit to "1" (enable transfer), DMA transfer is enable and when all transmissions are com- pleted (underflow of transfer count register), it is "0" cleared. And when DMA transfer request is already occurred and set to transfer enable, DMA transfer starts immediately so that make sure not to do that. When setting this bit to "0" (disable transfer), DMA transfer is disable. However, if a transfer request has already been accepted, transfers on that channel are not disabled until after the requested transfer is com- pleted. (5) TSZSLn (DMAn Transfer Size Select) bit (Bit 5) This bit selects the number of bits to be transferred in one DMA transfer operation (the unit of one transfer). The unit of one transfer is 16 bits when TSZSL = "0" or 8 bits when TSZSL = "1". (6) SADSLn (DMAn Source Address Direction Select) bit (Bit 6) This bit selects the direction in which the source address changes. This mode can be selected from two choices: Address fixed or Address incremental. (7) DADSLn (DMAn Destination Address Direction Select) bit (Bit 7) This bit selects the direction in which the destination address changes. This mode can be selected from two choices: Address fixed or Address incremental.

9-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

9.2.2 DMA Software Request Generation Registers

DMA0 Software Request Generation Register (DM0SRI) <Address: H’0080 0460> DMA1 Software Request Generation Register (DM1SRI) <Address: H’0080 0462> DMA2 Software Request Generation Register (DM2SRI) <Address: H’0080 0464> DMA3 Software Request Generation Register (DM3SRI) <Address: H’0080 0466> DMA4 Software Request Generation Register (DM4SRI) <Address: H’0080 0468> DMA5 Software Request Generation Register (DM5SRI) <Address: H’0080 0470> DMA6 Software Request Generation Register (DM6SRI) <Address: H’0080 0472> DMA7 Software Request Generation Register (DM7SRI) <Address: H’0080 0474> DMA8 Software Request Generation Register (DM8SRI) <Address: H’0080 0476> DMA9 Software Request Generation Register (DM9SRI) <Address: H’0080 0478> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 DM0SRI–DM9SRI DMA transfer request is generated by writing any ? W DMA software request generation data to these bits. Note: This register may be accessed in either bytes or halfwords. The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA transfer request can be generated by writing any data to this register when “Software start” has been selected for the cause of DMA request. (1) DM0SRI–DM9SRI (DMA Software Request Generation) A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in byte (8 bits) beginning with an even or odd address when “Software start” is selected as the cause of DMA transfer request (by setting the DMAn Channel Control Register bits 2–3 to ‘00’). b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 DM0SRI-DM9SRI

9-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

9.2.3 DMA Source Address Registers

DMA0 Source Address Register (DM0SA) <Address: H’0080 0412> DMA1 Source Address Register (DM1SA) <Address: H’0080 0422> DMA2 Source Address Register (DM2SA) <Address: H’0080 0432> DMA3 Source Address Register (DM3SA) <Address: H’0080 0442> DMA4 Source Address Register (DM4SA) <Address: H’0080 0452> DMA5 Source Address Register (DM5SA) <Address: H’0080 041A> DMA6 Source Address Register (DM6SA) <Address: H’0080 042A> DMA7 Source Address Register (DM7SA) <Address: H’0080 043A> DMA8 Source Address Register (DM8SA) <Address: H’0080 044A> DMA9 Source Address Register (DM9SA) <Address: H’0080 045A> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 DM0SA–DMA9SA Source address bits A16–A31 R W DMA source address (A0–A15 are fixed to H’0080) Note: This register must always be accessed in halfwords. The DMA Source Address Register is used to set the source address of DMA transfer in such a way that bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the values read from this register are always the current value. When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Source Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. (1) DM0SA–DM9SA (Source Address A16–A31) Set this register to specify the source address of DMA transfer in the SFR area or internal RAM space from the address H’0080 0000 to the address H’0080 FFFF. The 16 high-order source address bits (A0–A15) are always fixed to H’0080. Use this register to set the 16 low-order source address bits (with bit 0 corresponding to the source address A16, and bit 15 correspond- ing to the source address A31). b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 DM0SA-DM9SA

9-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

9.2.4 DMA Destination Address Registers

DMA0 Destination Address Register (DM0DA) <Address: H’0080 0414> DMA1 Destination Address Register (DM1DA) <Address: H’0080 0424> DMA2 Destination Address Register (DM2DA) <Address: H’0080 0434> DMA3 Destination Address Register (DM3DA) <Address: H’0080 0444> DMA4 Destination Address Register (DM4DA) <Address: H’0080 0454> DMA5 Destination Address Register (DM5DA) <Address: H’0080 041C> DMA6 Destination Address Register (DM6DA) <Address: H’0080 042C> DMA7 Destination Address Register (DM7DA) <Address: H’0080 043C> DMA8 Destination Address Register (DM8DA) <Address: H’0080 044C> DMA9 Destination Address Register (DM9DA) <Address: H’0080 045C> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 DM0DA–DM9DA Destination address bits A16–A31 R W DMA destination address (A0–A15 are fixed to H’0080) Note: This register must always be accessed in halfwords The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the values read from this register are always the current value. When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if “Address fixed” is selected, is the same source address that was set in it before the DMA transfer began; if “Address incremental” is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Destination Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. (1) DM0DA–DM9DA (Destination Address bits A16–A31) Set this register to specify the destination address of DMA transfer in the SFR area or internal RAM space from the address H’0080 0000 to the address H’0080 FFFF. The 16 high-order destination address bits (A0–A15) are always fixed to H’0080. Use this register to set the 16 low-order destination address bits (with bit 0 corresponding to the destination address A16, and bit 15 corresponding to the destination address A31). b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 DM0DA-DM9DA

9-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

9.2.5 DMA Transfer Count Registers

DMA0 Transfer Count Register (DM0TCT) <Address: H’0080 0411> DMA1 Transfer Count Register (DM1TCT) <Address: H’0080 0421> DMA2 Transfer Count Register (DM2TCT) <Address: H’0080 0431> DMA3 Transfer Count Register (DM3TCT) <Address: H’0080 0441> DMA4 Transfer Count Register (DM4TCT) <Address: H’0080 0451> DMA5 Transfer Count Register (DM5TCT) <Address: H’0080 0419> DMA6 Transfer Count Register (DM6TCT) <Address: H’0080 0429> DMA7 Transfer Count Register (DM7TCT) <Address: H’0080 0439> DMA8 Transfer Count Register (DM8TCT) <Address: H’0080 0449> DMA9 Transfer Count Register (DM9TCT) <Address: H’0080 0459> <Upon exiting reset: Undefined> b Bit Name Function R W 8–15 DM0TCT–DM9TCT DMA transfer count R W DMA transfer count (Has no effect during 32-channel ring buffer mode) The DMA Transfer Count Register is used to set the number of times data is transferred on each channel. However, the value in this register has no effect during ring buffer mode. The transfer count is the (value set in the transfer count register + 1). Because the DMA Transfer Count Register is comprised of a current register, the values read from this register are always the current value. (However, if the register is read in a cycle immediately after transfer, the value obtained is one that was stored in the count register before the transfer began.) When transfer finishes, this count register underflows and the value read from it is H’FF. When transfer is enabled, this register is protected in hardware and cannot be accessed for write. During ring buffer mode, the register counts down in free-run mode and continues counting until transfer is disabled. No interrupt is generated at underflow. If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all trans- fers on a channel are completed (i.e., the transfer count register underflows), transfer on the cascaded channel starts. b 8 9 1 01 11 21 31 4 b 1 5 DM0TCT-DM9TCT

9-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

9.2.6 DMA Interrupt Related Registers

The DMA interrupt related registers are used to control the interrupt request signals sent from the DMAC to the Interrupt Controller. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt request mask bit, it can be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "0" to enable interrupt requests or "1" to disable interrupt requests. Figure 9.2.1 Interrupt Request Status and Mask Registers To the Interrupt Controller Interrupt request from each peripheral function Interrupt request status Data bus Set Group interrupt Interrupt request enabled clear F/F F/F Data = 0

9-1732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 9.2.2 Example for Clearing Interrupt Request Status b4 5 b7 Interrupt request status Initial state Event occurs on bit 6 Interrupt request Event occurs on bit 4 Only bit 6 cleared Bit 4 data retained b4 5 b7 1 1 0 1 Write to the interrupt request status Example for clearing interrupt request status 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 Program example ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */ To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. b4 5 6 b7 Interrupt request status Event occurs on bit 6 Event occurs on bit 4 Only bit 6 cleared Bit 4 also cleared 0 0 1 0 1 0 1 0 0 0 0 0 Read 0 0 1 0 0 0 0 0 Clear bit 6 (AND'ing with 1101) Write ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */

9-1832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 DMA0–4 Interrupt Request Status Register (DM04ITST) <Address: H’0080 0400> <Upon exiting reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00

3 DMITST4 (DMA4 interrupt request status bit) 0: Interrupt not requested R(Note 1)

4 DMITST3 (DMA3 interrupt request status bit) 1: Interrupt requested

5 DMITST2 (DMA2 interrupt request status bit)

6 DMITST1 (DMA1 interrupt request status bit)

7 DMITST0 (DMA0 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. DMA5–9 Interrupt Request Status Register (DM59ITST) <Address: H’0080 0408> <Upon exiting reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00

3 DMITST9 (DMA9 interrupt request status bit) 0: Interrupt not requested R(Note 1)

4 DMITST8 (DMA8 interrupt request status bit) 1: Interrupt requested

5 DMITST7 (DMA7 interrupt request status bit)

6 DMITST6 (DMA6 interrupt request status bit)

7 DMITST5 (DMA5 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. The Interrupt Request Status Register helps to know the status of interrupt requests on each channel. If the DMAn interrupt request status bit (n = 0–9) is set to "1", it means that a DMA interrupt request on the correspond- ing channel has been generated. (1) DMITSTn (DMAn Interrupt Request Status) bit (n = 0–9) [Setting the DMAn interrupt request status bit] This bit is set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing "0" in software. Note: The DMAn interrupt request status bit cannot be cleared by writing "0" to the DMA Interrupt Control Register’s “interrupt request bit” included in the Interrupt Controller. When writing to the DMA Interrupt Request Status Register, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write. b 0 123456 b 7 DMITST9 DMITST8 DMITST7 DMITST6 DMITST5 00000000 b 0 123456 b 7 DMITST4 DMITST3 DMITST2 DMITST1 DMITST0 00000000

9-1932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 DMA0–4 Interrupt Request Mask Register (DM04ITMK) <Address: H’0080 0401> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 DMITMK4 (DMA4 interrupt request mask bit) 0: Enable interrupt request R W

12 DMITMK3 (DMA3 interrupt request mask bit) 1: Mask (disable) interrupt request

13 DMITMK2 (DMA2 interrupt request mask bit)

14 DMITMK1 (DMA1 interrupt request mask bit)

15 DMITMK0 (DMA0 interrupt request mask bit)

DMA5–9 Interrupt Request Mask Register (DM59ITMK) <Address: H’0080 0409> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 DMITMK9 (DMA9 interrupt request mask bit) 0: Enable interrupt request R W

12 DMITMK8 (DMA8 interrupt request mask bit) 1: Mask (disable) interrupt request

13 DMITMK7 (DMA7 interrupt request mask bit)

14 DMITMK6 (DMA6 interrupt request mask bit)

15 DMITMK5 (DMA5 interrupt request mask bit)

The DMA Interrupt Request Mask Register is used to mask interrupt requests on each DMA channel. (1) DMITMKn (DMAn Interrupt Request Mask) bit (n = 0–9) Setting the DMAn interrupt request mask bit to "1" masks the interrupt requests on DMAn channel. How- ever, if an interrupt request occurs, the DMAn interrupt request status bit is always set to "1" irrespective of the contents of this mask register. b 8 9 1 01 11 21 31 4 b 1 5 DMITMK4 DMITMK3 DMITMK2 DMITMK1 DMITMK0 00000000 b 8 9 1 01 11 21 31 4 b 1 5 DMITMK9 DMITMK8 DMITMK7 DMITMK6 DMITMK5 00000000

9-2032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 F/F F/F DMITMK0 DMITST0 F/F F/F DMITMK1 DMITST1 F/F F/F DMITMK2 DMITST2 F/F F/F DMITMK3 DMITST3 F/F F/F DMITMK4 DMITST4 b15 b14 b13 b12 b11 Data bus DMA4UDF DMA3UDF DMA2UDF DMA1UDF DMA0UDF DMA transfer interrupt request 0(Level) 5-source inputs DM04ITST (H'0080 0400) DM04ITMK (H'0080 0401) Figure 9.2.3 Block Diagram of DMA Transfer Interrupt Request 0

9-2132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 F/F F/F DMITMK5 DMITST5 F/F F/F DMITMK6 DMITST6 F/F F/F DMITMK7 DMITST7 F/F F/F DMITMK8 DMITST8 F/F F/F DMITMK9 DMITST9 b15 b14 b13 b12 b11 Data bus DMA9UDF DMA8UDF DMA7UDF DMA6UDF DMA5UDF DMA transfer interrupt request 1(Level) 5-source inputs DM59ITST (H'0080 0408) DM59ITMK (H'0080 0409) Figure 9.2.4 Block Diagram of DMA Transfer Interrupt Request 1

9-2232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

9.3.1 DMA Transfer Request Sources

For each DMA channel (channels 0–9), DMA transfer can be requested from two or more sources. There are various causes or sources of DMA transfer request, so that DMA transfer can be started by a request from some internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all transfers on another DMA channel (cascade mode). The causes or sources of DMA transfer requests are selected using the transfer request source select bits REQSLn on each channel (DMAn Channel Control Register bits 2 and 3). The tables below list the causes or sources of DMA transfer requests on each channel. Table 9.3.1 DMA Transfer Request Sources and Generation Timings on DMA0 REQSL0 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start or one DMA2 When any data is written to the DMA0 Software Request Generation Register transfer completed (software start) or when one DMA2 transfer is completed (cascade mode) 0 1 A/D0 conversion completed When A/D0 conversion is completed 1 0 MJT (TIO8_udf) When MJT TIO8 underflows 1 1 MJT (input event bus 2) When MJT input event bus 2 signal is generated Table 9.3.2 DMA Transfer Request Sources and Generation Timings on DMA1 REQSL1 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA1 Software Request Generation Register 0 1 MJT (output event bus 0) When MJT output event bus 0 signal is generated 1 0 Settings inhibited – 1 1 One DMA0 transfer completed When one DMA0 transfer is completed (cascade mode) Table 9.3.3 DMA Transfer Request Sources and Generation Timings on DMA2 REQSL2 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA2 Software Request Generation Register 0 1 MJT (output event bus 1) When MJT output event bus 1 signal is generated 1 0 MJT (TIN18S) When MJT TIN18 input signal is generated (edge select output) 1 1 One DMA1 transfer completed When one DMA1 transfer is completed (cascade mode)

9-2332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 9.3.4 DMA Transfer Request Sources and Generation Timings on DMA3 REQSL3 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA3 Software Request Generation Register 0 1 SIO0_TXD (transmit buffer empty) When SIO0 transmit buffer is empty 1 0 SIO1_RXD (reception completed) When SIO1 reception is completed 1 1 MJT (TIN0S) When MJT TIN0 input signal is generated (edge select output) Table 9.3.5 DMA Transfer Request Sources and Generation Timings on DMA4 REQSL4 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA4 Software Request Generation Register 0 1 One DMA3 transfer completed When one DMA3 transfer is completed (cascade mode) 1 0 SIO0_RXD (reception completed) When SIO0 reception is completed 1 1 MJT (TIN19S) When MJT TIN19 input signal is generated (edge select output) Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5 REQSL5 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start or one DMA7 When any data is written to the DMA5 Software Request Generation Register transfer completed (software start) or when one DMA7 transfer is completed (cascade mode) 0 1 All DMA0 transfers completed When all DMA0 transfers are completed (cascade mode) 1 0 SIO2_RXD (reception completed) When SIO2 reception is completed 1 1 MJT (TIN20S) When MJT TIN20 input signal is generated (edge select output) Table 9.3.7 DMA Transfer Request Sources and Generation Timings on DMA6 REQSL6 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA6 Software Request Generation Register 0 1 SIO1_TXD (transmit buffer empty) When SIO1 transmit buffer is empty 1 0 CAN (CAN0_S0/S15) CAN0: when slot 0 transmission failed or slot 15 transmission/reception completed 1 1 One DMA5 transfer completed When one DMA5 transfer is completed (cascade mode)

9-2432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 9.3.8 DMA Transfer Request Sources and Generation Timings on DMA7 REQSL7 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA7 Software Request Generation Register 0 1 SIO2_TXD (transmit buffer empty) When SIO2 transmit buffer is empty 1 0 CAN (CAN0_S1/S14) CAN0: when slot 1 transmission failed or slot 14 transmission/reception completed 1 1 One DMA6 transfer completed When one DMA6 transfer is completed (cascade mode) Table 9.3.9 DMA Transfer Request Sources and Generation Timings on DMA8 REQSL8 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA8 Software Request Generation Register 0 1 MJT (input event bus 0) When MJT input event bus 0 signal is generated 1 0 SIO3_RXD (reception completed) When SIO3 reception is completed 1 1 CAN (CAN1_S0/S15) CAN1: when slot 0 transmission failed or slot 15 transmission/reception completed Table 9.3.10 DMA Transfer Request Sources and Generation Timings on DMA9 REQSL9 DMA Transfer Request Source DMA Transfer Request Generation Timing 0 0 Software start When any data is written to the DMA9 Software Request Generation Register 0 1 SIO3_TXD (transmit buffer empty) When SIO3 transmit buffer is empty 1 0 CAN (CAN1_S1/S14) CAN1: when slot 1 transmission failed or slot 14 transmission/reception completed 1 1 One DMA8 transfer completed When one DMA8 transfer is completed (cascade mode)

9-2532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 DMA transfer starts as requested by internal peripheral I/O DMA transfer processing starts Transfer count register underflows Interrupt request generated Set DMA0 Channel Control Register Set DMA0-4 Interrupt Request Status Register Set DMA0 Channel Control Register Set DMA0 Source Address Register Set DMA0 Destination Address Register Set DMA0 Count Register Setting DMAC-related registers Starting DMA transfer DMA transfer completed Transfers disabled Interrupt request status bits cleared Set DMA0-4 Interrupt Request Mask Register Source address of transfer Destination address of transfer Number of times DMA transfer is performed Transfer mode, request source, transfer size, address direction and transfer enable DMA operation completed Interrupt request enabled Set the interrupt controller's DMA0-4 Interrupt Control Register Interrupt priority level Setting interrupt controller-related registers Figure 9.3.1 Example of a DMA Transfer Processing Procedure

9.3.2 DMA Transfer Processing Procedure

Shown below is an example of how to control DMA transfer in cases when performing transfer on DMA0.

9-2632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 9.3.2 Gaining and Releasing Control of the Internal Bus One DMA transfer DMAC CPU Internal bus arbitration (requests from the DMAC) Internal bus R: Read W: Write RW RW RW Requested Gained Requested Gained Requested Gained One DMA transfer One DMA transfer Released Released Released

9.3.3 Starting DMA

Use the DMAn Channel Control Register (DMnCNT) REQSL (DMA transfer request source select) bit to set the cause or source of DMA transfer request. To enable DMA, set the TENL (DMA transfer enable) bit to "1". DMA transfer begins when the specified cause or source of DMA transfer request becomes effective after setting the TENL (DMA transfer enable) bit to "1". Note: If the transfer request source selected by the REQSL (DMA transfer request source select) bit is MJT (TIN input signal), the time required for DMA transfer to begin after detecting the rising or falling or both edges of the TIN input signal is three cycles (150 ns when the internal peripheral clock = 20 MHz) at the shortest. Or, depending on the preceding or following bus usage condition, up to six cycles (300 ns when the internal peripheral clock = 20 MHz) may be required. (However, this applies when the external bus, HOLD and the LOCK instruction all are unused.) To ensure that changes of the TIN input signal state will be detected correctly, make sure the TIN input signal is held active for a duration of more than 7tc (BCLK)/2. (For details, see Chapter 21 ELECTRI- CAL CHARACTERISTICS.)

9.3.4 DMA Channel Priority

DMA0 has the highest priority. The priority of this and other channels is shown below. DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9 This order of priority is fixed. Channel priority is resolved every transfer cycle (i.e., every three DMA buy cycles), and the channel with the highest priority among those that are requesting a DMA transfer is selected.

9.3.5 Gaining and Releasing Control of the Internal Bus

For any channel, control of the internal bus is gained and released in “single transfer DMA” mode. In single transfer DMA, the DMAC gains control of the internal bus (in one peripheral clock cycle) when DMA transfer request is accepted and after executing one DMA transfer (in one read and one write peripheral clock cycle), returns bus control to the CPU. The diagram below shows the operation in single transfer DMA.

9-2732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

9.3.6 Transfer Units

Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one DMA transfer.

9.3.7 Transfer Counts

Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be performed up to 256 times. The value of the DMA Transfer Count Register is decremented by one every time one transfer unit is transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-run mode, with the value set in it ignored.

9.3.8 Address Space

The address space in which data can be transferred by DMA is 64 Kbytes of SFR area or internal RAM space (H’0080 0000 through H’0080 FFFF) for both source and destination. To set the source and destination addresses on each DMA channel, use the DMA Source Address Register and DMA Destination Address Register.

9.3.9 Transfer Operation

(1) Dual-address transfer Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and one for destination write access. (The transfer data is taken into the DMAC’s internal temporary register before being transferred.) (2) Bus protocol and bus timing Because the bus interface is shared with the CPU, DMA transfer is performed with the same bus protocol and the same bus timing as when peripheral modules are accessed by the CPU. (3) Transfer rate Transfer is performed using a total of three peripheral clock cycles, one cycle to gain control of the bus and one read and one write cycle to perform one transfer. Therefore, the maximum transfer rate is calculated by the equation below: Maximum transfer rate [bytes per second] = 2 bytes × 1 1/f(BCLK) × 3 cycles

9-2832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 9.3.3 Transfer Byte Positions (4) Address count direction and address changes The direction in which the source and destination addresses are counted as transfer proceeds (“Address fixed” or “Address incremental”) is set for each channel using the SADSL (source address direction select) and DADSL (destination address direction select) bits. When the transfer size is 16 bits, the address is incremented by two for each DMA transfer performed; when the transfer size is 8 bits, the address is incremented by one. Table 9.3.11 Address Count Direction and Address Changes Address Count Direction Transfer Unit Address Change for One DMA Address fixed 8 bits 0 16 bits 0 Address incremental 8 bits +1 16 bits +2 (5) Transfer count value The transfer count value is decremented one at a time, irrespective of the size of transfer unit (8 or 16 bits). (6) Transfer byte positions When the transfer unit is 8 bits, the LSB of the address register is effective for both source and destination. (Therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address or vice versa.) When the transfer unit is 16 bits, the LSB of the address register (= bit 15) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus. The diagram below shows the valid byte positions in DMA transfer. b0 b7 b8 b15 8 bits +0 +1 Source Destination <When transfer size = 8 bits> 8 bits 8 bits 8 bits 16 bits 16 bits b0 b7 b8 b15 +0 +1 <When transfer size = 16 bits>

9-2932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 9.3.4 Example of How Addresses Are Incremented in 32-channel Ring Buffer Mode <When transfer size = 8 bits> Transfer count Transfer address

1 H'0080 1000

2 H'0080 1001

3 H'0080 1002

31 H'0080 101E

32 H'0080 101F

↓ ↓ ↓ ↓ <When transfer size = 16 bits> Transfer count Transfer address

2 H'0080 1002

3 H'0080 1004

31 H'0080 103C

32 H'0080 103E

| | | | | | | | (7) Ring buffer mode When ring buffer mode is selected, transfer begins from the transfer start address and after performing transfers 32 times, control returns to the transfer start address, from which transfer operation is repeated. In this case, however, the five low-order bits of the ring buffer start address must always be B’00000 (if transfer size = 16 bits, the six low-order bits must be B’000000). The following describes how addresses are incremented in ring buffer mode. [1] When the transfer size is 8 bits The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented by one at a time. When as transfer proceeds the five low-order bits reach B’11111, they are recycled to B’00000 by the next increment operation, thus returning to the start address again. [2] When the transfer size is 16 bits The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented by two at a time. When as transfer proceeds the six low-order bits reach B’111110, they are recycled to B’000000 by the next increment operation, thus returning to the start address again. If the source address has been set to be incremented, it is the source address that recycles to the start address; if the destination address has been set to be incremented, it is the destination address that re- cycles to the start address. If both source and destination addresses have been set to be incremented, both addresses recycle to the start address. However, the start address on either side must have their five low- order bits initially set to B’00000 (if transfer size = 16 bits, the six low-order bits must be B’000000). During ring buffer mode, the transfer count register is ignored. Once DMA operation starts, the counter operates in free-run mode, and the transfer continues until the transfer enable bit is cleared to "0" (to disable transfer).

9-3032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

9.3.10 End of DMA and Interrupt

In normal mode, DMA transfer is terminated by an underflow of the transfer count register. When transfer finishes, the transfer enable bit is cleared to "0" and transfers are thereby disabled. Also, an interrupt request is generated at completion of transfer. However, if interrupt requests on any channel have been masked by the DMA Interrupt Request Mask Register, no interrupt requests are generated on that channel. During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the transfer enable bit is cleared to "0" (to disable transfer). In this case, therefore, no interrupt requests are generated at completion of DMA transfer. Nor are these DMA transfer-completed interrupt requests are gener- ated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit.

9.3.11 Each Register Status after Completion of DMA Transfer

When DMA transfer is completed, the status of the source and destination address registers becomes as follows: (1) Address fixed The values set in the address registers before DMA transfer started remain intact (fixed). (2) Address incremental For 8-bit transfer, the values of the address registers are the last transfer address + 1. For 16-bit transfer, the values of the address registers are the last transfer address + 2. The transfer count register at completion of DMA transfer is in an underflow state (H’FF). Therefore, before another DMA transfer can be performed, the transfer count register must be set newly again, except when trying to perform transfers 256 times (H’FF).

9-3132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

About writing to the DMAC related registers Because DMA transfer involves exchanging data via the internal bus, the DMAC related registers basically can only be accessed for write immediately after reset or when transfer is disabled (transfer enable bit = "0"). When transfer is enabled, do not write to the DMAC related registers, except the DMA transfer enable bit, the transfer request flag and the DMA Transfer Count Register that is protected in hardware. This is a precaution necessary to ensure stable DMA operation. The table below lists the registers that can or cannot be accessed for write. Table 9.4.1 DMAC Related Registers That Can or Cannot Be Accessed for Write Status Transfer Transfer DMA interrupt Other DMAC enable bit request flag related registers related registers Transfer enabled Can be accessed Can be accessed Can be accessed Cannot be accessed Transfer disabled Can be accessed Can be accessed Can be accessed Can be accessed Even for registers that can exceptionally be written to while transfer is enabled, the following conditions must be observed: (1) DMA Channel Control Register transfer enable bit and transfer request flag For all other bits than transfer enable bit and transfer request flag in this register, be sure to write the same data that those bits had before the write. Note, however, that only writing "0" is effective for the transfer request flag. (2) DMA Transfer Count Register When transfer is enabled, this register is protected in hardware, so that any data rewritten to it is ignored. (3) Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer Although this operation means accessing the DMAC related registers while DMA is enabled, there is no problem. Note, however, that no data can be transferred by DMA to the DMAC related registers on the currently active channel itself.
Manipulating the DMAC related registers by DMA transfer When manipulating the DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related registers with the initial values by DMA transfer), do not write to the DMAC related registers on the currently active channel through that channel. (If this precaution is neglected, device operation cannot be guaranteed.) It is only the DMAC related registers on other channels that can be rewritten by means of DMA transfer. (For example, the DMAn Source Address and DMAn Destination Address Registers on channel 1 can be rewritten by DMA transfer through channel 0.)
About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register, be sure to write "1" to all bits, except those to be cleared. Writing "1" to any bits in this register has no effect, so that they retain the data they had before the write.

9-3232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

About the stable operation of DMA transfer To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except the channel control register’s transfer enable bit, unless transfer is disabled. One exception is that even when transfer is enabled, the DMA Source Address and DMA Destination Address Registers can be rewritten by DMA transfer from one channel to another.

10.1 Outline of Multijunction Timers

10.2 Common Units of Multijunction Timers

10.3 TOP (Output-Related 16-Bit Timer)

10.4 TIO (Input/Output-Related 16-Bit Timer)

10.5 TMS (Input-Related 16-Bit Timer)

10.6 TML (Input-Related 32-Bit Timer)

10-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to being used as a single unit, the timers can be internally connected to each other. This capability allows for highly flexible timer configuration, making it possible to meet various application needs. It is because the timers are connected to the internal event buses at multiple points that they are called the “multijunction” timers. The 32176 has four types of MJT as listed in the table below, providing a total of 37-channel timers. Table 10.1.1 Outline of MJT Name Type No. of Channels Description TOP Output-related 11 One of three output modes can be selected by software. (Timer 16-bit timer <With correction function> Output) (down-counter) Single-shot output mode Delayed single-shot output mode <Without correction function> Continuous output mode TIO Input/output-related 10 One of three input modes or four output modes can be selected (Timer 16-bit timer by software. Input (down-counter) <Input modes> Output) Measure clear input mode Measure free-run input mode Noise processing input mode <Output modes without correction function> PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode TMS Input-related 8 16-bit input measure timer (Timer 16-bit timer Measure (up-counter) Small) TML Input-related 8 32-bit input measure timer (Timer 32-bit timer Measure (up-counter) Large)

10-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 10.1.2 Interrupt Generation Functions of MJT Signal Name MJT Interrupt Request Source Source of Interrupt Request No. of ICU Input Sources IRQ0 TIO0–3 output MJT output interrupt 0 4 IRQ1 TOP6, TOP7 output MJT output interrupt 1 2 IRQ2 TOP0–5 output MJT output interrupt 2 6 IRQ3 TIO8, TIO9 output MJT output interrupt 3 2 IRQ4 TIO4–7 output MJT output interrupt 4 4 IRQ5 TOP10 output MJT output interrupt 5 1 IRQ6 TOP8, TOP9 output MJT output interrupt 6 2 IRQ7 TMS0, TMS1 output MJT output interrupt 7 2 IRQ9 TIN0 input MJT input interrupt 1 1 IRQ10 TIN16–TIN19 input MJT input interrupt 2 4 IRQ11 TIN20–TIN23 input MJT input interrupt 3 4 IRQ12 TIN3 input MJT input interrupt 4 1 Table 10.1.3 DMA Transfer Request Generation by MJT Corresponding DMAC Channel No. DMA Transfer Request Source DMA0 TIO8_udf Input event bus 2 DMA1 Output event bus 0 DMA2 Output event bus 1 TIN18 input signal (TIN18S) DMA3 TIN0 input signal (TIN0S) DMA4 TIN19 input signal (TIN19S) DMA5 TIN20 input signal (TIN20S) DMA8 Input event bus 0 Table 10.1.4 A/D Conversion Start Request by MJT Signal Name A/D Conversion Start Request Source A/D Converter AD0TRG Input event bus 2, Can be input to A/D0 conversion start trigger input event bus 3, output event bus 3, TIN23

10-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.1.1 Block Diagram of MJT (1/3) IRQ2 IRQ12 clk en udfTOP 0 clk en udfTOP 1 clk en udfTOP 2 clk en udfTOP 3 TCLK0S TO 0 (P110) IRQ9 3 2 1 0 BCLK/2 clk en udfTOP 4 clk en udfTOP 5 TCLK0 (P124) TIN0 (P150) TCLK1 (P125) S STIN0S clk en udfTOP 6 clk en udfTOP 7 S S S S S clk en udfTOP 8 clk en udfTOP 9 clk en udfTOP 10 clk en/cap udfTIO 0 clk en/cap udfTIO 1 clk en/cap udfTIO 2 clk en/cap udfTIO 3 clk en/cap udfTIO 4 S STIN3 (P153) S S S S PRS1 PRS0 clk en/cap udfTIO 5S S TCLK2 (P126) clk en/cap udfTIO 6S S clk en/cap udfTIO 7S S S S clk en/cap udfTIO 8 clk en/cap udfTIO 9S S F/F0 F/F1 F/F2 F/F3 F/F4 F/F5 F/F6 F/F7 F/F8 F/F9 F/F10 F/F11 F/F12 F/F13 F/F14 F/F15 F/F16 F/F17 F/F18 F/F19 F/F20 S : SelectorF/F : Output flip-flopPRS0 - 2 : Prescalers S S S S S S S S S S S S S S S IRQ2 IRQ2 IRQ2 IRQ2 IRQ2 TO 1 (P111) TO 2 (P112) TO 3 (P113) TO 4 (P114) TO 5 (P115) TO 6 (P116) TO 7 (P117) TO 8 (P100) TO 9 (P101) TO 10 (P102) TO 11 (P103) TO 12 (P104) TO 13 (P105) TO 14 (P106) TO 15 (P107) IRQ1 IRQ1 IRQ6 IRQ6 IRQ5 IRQ0 IRQ0 IRQ0 IRQ0 IRQ4 TO 16 (P93) TO 17 (P94) TO 18 (P95) TO 19 (P96) TO 20 (P97) IRQ4 DMA0 IRQ3 IRQ3 3 2 1 0 0 1 2 3 3 2 1 0 3 2 1 0 PRS2 IRQ4 IRQ4 0 1 2 3 TIN3S TCLK1S TCLK2S DMA3 Clock bus Input event bus Output event bus Notes: • IRQ0-7 and IRQ9-12 denote interrupt signals, of which the same number represents the same group of interrupts. (See Table 10.1.2) AD0TRG denotes trigger signal to the A/D0 converter. (See Table 10.1.4)

10-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 3 2 1 0 3 2 1 0 clk TMS 0 ovfcap3 cap2 cap1 cap0 S clk TML 0 cap3 cap2 cap1 cap0 S S S S TIN20 (P134) TIN21 (P135) TIN22 (P136) TIN23 (P137) IRQ11 IRQ11 IRQ11 IRQ11 BCLK/2 0 1 2 3 IRQ7 3 2 1 0 3 2 1 0 0 1 2 3 TIN20S TIN21S TIN22S TIN23S S DMA5 clk TMS 1 ovfcap3 cap2 cap1 cap0 S S S S S DMA2 TIN16 (P130) TIN17 (P131) TIN18 (P132) TIN19 (P133) DMA4 IRQ10 IRQ10 IRQ10 IRQ10 IRQ7 TIN16S TIN17S TIN18S TIN19S clk TML 1 cap3 cap2 cap1 cap0 S TCLK3 (P127) TCLK3S S S S S S S S S AD0TRG (to A/D0 converter) AD0TRG (to A/D0 converter) AD0TRG (to A/D0 converter) AD0TRG (to A/D0 converter) BCLK/2 Clock bus Input event bus Output event bus Notes: IRQ0-7 and IRQ9-12 denote interrupt signals, of which the same number represents the same group of interrupts. (See Table 10.1.2) AD0TRG denotes trigger signal to the A/D0 converter. (See Table 10.1.4) Figure 10.1.2 Block Diagram of MJT (2/3)

10-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.1.3 Block Diagram of MJT (3/3) S DMA0 udf end DMA1 udf end DMA2 udf end DMA3 udf end DMA4 udf end DMA5 udf end DMA6 udf end DMA7 udf end DMA8 udf end DMA9 udf end S S S S S S S S S A/D0 conversion completed TIO8_udf Software start Software start Software start SIO0_TXD SIO1_RXD Software start SIO0_RXD Software start Software start SIO2_RXD SIO1_TXD Software start SIO2_TXD Software start SIO3_RXD Software start CAN0_S0/S15 (Note 1) TIN0S(P150) (Note 1) TIN19S(P133) (Note 1) TIN20S(P134) SIO3_TXD Software start (Note 1) TIN18S(P132) CAN0_S1/S14 CAN1_S0/S15 CAN1_S1/S14 Note 1. Indicates edge select output at the timer input pin. DMA0-4 interrupts DMA5-9 interrupts 0123 Input event bus Output event bus 3210 3210 0123

10-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The common units of MJT include the following: Prescaler Unit Clock Bus and Input/Output Event Bus Control Unit Input Processing Control Unit Output Flip-flop Control Unit Interrupt Control Unit

10-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.2.1 MJT Common Unit Register Map

The table below shows a common unit register map of MJT. MJT Common Unit Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0200 (Use inhibited area) Clock Bus & Input Event Bus Control Register 10-13 (CKIEBCR) H'0080 0202 Prescaler Register 0 Prescaler Register 1 10-9 (PRS0) (PRS1) H'0080 0204 Prescaler Register 2 Output Event Bus Control Register 10-9 (PRS2) (OEBCR) 10-14 (Use inhibited area) H'0080 0210 TCLK Input Processing Control Register 10-17 (TCLKCR) H'0080 0212 TIN Input Processing Control Register 0 10-18 (TINCR0) H'0080 0214 (Use inhibited area) H'0080 0216 (Use inhibited area) H'0080 0218 TIN Input Processing Control Register 3 10-19 (TINCR3) H'0080 021A TIN Input Processing Control Register 4 10-19 (TINCR4) H'0080 021C (Use inhibited area) H'0080 021E (Use inhibited area) H'0080 0220 F/F Source Select Register 0 10-21 (FFS0) H'0080 0222 (Use inhibited area) F/F Source Select Register 1 10-22 (FFS1) H'0080 0224 F/F Protect Register 0 10-23 (FFP0) H'0080 0226 F/F Data Register 0 10-24 (FFD0) H'0080 0228 (Use inhibited area) F/F Protect Register 1 10-23 (FFP1) H'0080 022A (Use inhibited area) F/F Data Register 1 10-24 (FFD1) (Use inhibited area) H'0080 0230 TOP Interrupt Control Register 0 TOP Interrupt Control Register 1 10-29 (TOPIR0) (TOPIR1) H'0080 0232 TOP Interrupt Control Register 2 TOP Interrupt Control Register 3 10-31 (TOPIR2) (TOPIR3) 10-32 H'0080 0234 TIO Interrupt Control Register 0 TIO Interrupt Control Register 1 10-33 (TIOIR0) (TIOIR1) 10-34 H'0080 0236 TIO Interrupt Control Register 2 TMS Interrupt Control Register 10-35 (TIOIR2) (TMSIR) 10-36 H'0080 0238 TIN Interrupt Control Register 0 TIN Interrupt Control Register 1 10-37 (TINIR0) (TINIR1) 10-38 H'0080 023A (Use inhibited area) H'0080 023C TIN Interrupt Control Register 4 TIN Interrupt Control Register 5 10-39 (TINIR4) (TINIR5) H'0080 023E TIN Interrupt Control Register 6 (Use inhibited area) 10-41 (TINIR6)

10-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.2.2 Prescaler Unit

The Prescalers PRS0–2 are an 8-bit counter, which generates clocks supplied to each timer (TOP, TIO, TMS and TML) from the internal peripheral clock (BCLK) divided by 2 (10 MHz when f(BCLK) = 20 MHz). The values of prescaler registers are initialized to H’00 upon exiting the reset state. When the set value of any prescaler register is rewritten, the prescaler starts operating with the new value at the same time it has underflowed. Values H’00 to H’FF can be set in the prescaler register. The prescaler’s divide-by ratio is given by the equation below: Prescaler divide-by ratio = 1 prescaler set value + 1 Prescaler Register 0 (PRS0) <Address: H’0080 0202> Prescaler Register 1 (PRS1) <Address: H’0080 0203> Prescaler Register 2 (PRS2) <Address: H’0080 0204> <Upon exiting reset: H’00> b Bit Name Function R W 0–7 PRS0, PRS2 Set the prescaler divide-by value R W (8–15) PRS1 Prescaler Prescaler Registers 0–2 start counting after exiting the reset state. If the prescaler register is accessed for read during operation, the value written into it, not the current count, is read out. b 0 123456 b 7 (b8 9 10 11 12 13 14 b15) PRS0-PRS2 00000000

10-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.2.3 Clock Bus and Input/Output Event Bus Control Unit

(1) Clock bus The clock bus is provided for supplying clock to each timer, and is comprised of four lines of clock bus 0–3. Each timer can use these clock bus signals as clock input signals. The table below lists the signals that can be fed into the clock bus. Table 10.2.1 Acceptable Clock Bus Signals Clock Bus Acceptable Signal

3 TCLK0 input

2 Internal prescaler (PRS2) or TCLK3 input

1 Internal prescaler (PRS1)

0 Internal prescaler (PRS0)

(2) Input event bus The input event bus is provided for supplying a count enable signal or measure capture signal to each timer, and is comprised of four lines of input event bus 0–3. Each timer can use these input event bus signals as enable (or capture) input. Furthermore, they can also be used as request signals to start A/D conversion or DMA transfer. The table below lists the signals that can be fed into the input event bus. Table 10.2.2 Connectable (Acceptable) Input Event Bus Signals Input Event Bus Connectable (Acceptable) Signal (Note 1)

3 TIN3 input, output event bus 2 or TIO7 underflow signal

2 TIN0 input

1 TIO6 underflow signal

0 TIO5 underflow signal

Note 1: For the destination (output) to which the input event bus signals are connected, see Figure 10.1.1, “Block Diagram of MJT.” (3) Output event bus The output event bus has the underflow signal from each timer connected to it, and is comprised of four lines of output event bus 0–3. Output event bus signals are connected to output flip-flops, and output event buses 3, 0 and 1 can be connected to the A/D0 converter, DMA channel 1 and DMA channel 2, respectively. Furthermore, output event bus 2 can be connected to input event bus 3. The table below lists the signals that can be connected to the output event bus. Table 10.2.3 Connectable (Acceptable) Output Event Bus Signals Input Event Bus Connectable (Acceptable) Signal (Note 1)

3 TOP8, TIO3, TIO4 or TIO8 underflow signal

2 TOP9 or TIO2 underflow signal

1 TOP7 or TIO1 underflow signal

0 TOP6 or TIO0 underflow signal

Note 1: For the destination (output) to which the output event bus signals are connected, see Figure 10.1.1, “Block Diagram of MJT.” Note that the signals from each timer to the output event bus (and TIO5, 6 signals to the input event bus) are generated with the timing shown in Table 10.2.4, and not the timing at which signals are output from the timer to the output flip-flop.

10-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 10.2.4 Timing at Which Signals are Generated to the Output Event Bus by Each Timer Timer Mode Timing at which signals are generated to the output event bus TOP Single-shot output mode When the counter underflows Delayed single-shot output mode When the counter underflows Continuous output mode When the counter underflows TIO(Note 1) Measure clear input mode When the counter underflows Measure free-run input mode When the counter underflows Noise processing input mode When the counter underflows PWM output mode When the counter underflows Single-shot output mode When the counter underflows Delayed single-shot output mode When the counter underflows Continuous output mode When the counter underflows TMS (16-bit measure input) No signals generated TML (32-bit measure input) No signals generated Note 1: TIO5,6 output an underflow signal to the input event bus.

10-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.2.1 Conceptual Diagram of the Clock Bus and Input/Output Event Bus Clock bus Input event bus TCLK0S 3 2 1 0 BCLK/2 TCLK0 (P124) TIN0 (P150) TIN3 (P153) PRS1 PRS0 PRS0 - 2 : Prescaler 3 2 1 0 3 2 1 0 3 2 1 0 PRS2 TCLK3 (P127) udfTIO 5 udfTIO 6 S Output event bus 0 1 2 3 udfTIO 7 clk en udfTOP 6 clk en udfTOP 7 clk en udfTOP 8 clk en udfTOP 9 udfTIO 0 udfTIO 1 udfTIO 2 udfTIO 3 udfTIO 4 udfTIO 8 0 1 2 3S : Selector TCLK3S TIN0S TIN3S

10-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The Clock Bus and Input/Output Event Bus Control Unit has the following registers: Clock Bus & Input Event Bus Control Register (CKIEBCR) Output Event Bus Control Register (OEBCR) Clock Bus & Input Event Bus Control Register (CKIEBCR) <Address: H’0080 0201> <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 IEB3S 0X: Select external input 3 (TIN3) R W Input event bus 3 input select bit 10: Select output event bus 2 11: Select TIO7 output 10, 11 IEB2S 00: Select external input 0 (TIN0) R W Input event bus 2 input select bit 01: Does not use input event bus 2 10: Does not use input event bus 2 11: Does not use input event bus 2

12 IEB1S 0: Does not use input event bus 1 R W

Input event bus 1 input select bit 1: Select TIO6 output

13 IEB0S 0: Does not use input event bus 0 R W

Input event bus 0 input select bit 1: Select TIO5 output 14 No function assigned. Fix to "0". 00

15 CKB2S 0: Select prescaler 2 R W

Clock bus 2 input select bit 1: Select external clock 3 (TCLK3) The CKIEBCR register is used to select the clock source (external input or prescaler) supplied to the clock bus and the count enable/capture signal (external input or output event bus) supplied to the input event bus. b 8 9 1 01 11 21 31 4 b 1 5 IEB3S IEB2S IEB1S IEB0S CKB2S 0 0000000

10-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Output Event Bus Control Register (OEBCR) <Address: H’0080 0205> <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 OEB3S 00: Select TOP8 output R W Output event bus 3 input select bit 01: Select TIO3 output 10: Select TIO4 output 11: Select TIO8 output 10 No function assigned. Fix to "0". 00

11 OEB2S 0: Select TOP9 output R W

Output event bus 2 input select bit 1: Select TIO2 output 12 No function assigned. Fix to "0". 00

13 OEB1S 0: Select TOP7 output R W

Output event bus 1 input select bit 1: Select TIO1 output 14 No function assigned. Fix to "0". 00

15 OEB0S 0: Select TOP6 output R W

Output event bus 0 input select bit 1: Select TIO0 output The OEBCR register is used to select the timer (TOP or TIO) whose underflow signal is supplied to the output event bus.

10.2.4 Input Processing Control Unit

The Input Processing Control Unit processes TCLK and TIN input signals to the MJT. In TCLK input process- ing, it selects the source of TCLK signal, and for external input, it selects the active edge (rising or falling or both) or level ("H" or "L") of the signal, at which to generate the clock signal supplied to the clock bus. In TIN input processing, the unit selects the active edge (rising or falling or both) or level ("H" or "L") of the signal, at which to generate the enable, measure or count source signal for each timer or the signal supplied to each event bus. Following input processing registers are included: TLCK Input Processing Control Register (TCLKCR) TIN Input Processing Control Register 0 (TINCR0) TIN Input Processing Control Register 3 (TINCR3) TIN Input Processing Control Register 4 (TINCR4) b 8 9 1 01 11 21 31 4 b 1 5 OEB3S OEB2S OEB1S OEB0S 00000000

10-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Count clock Count clock Count clock BCLK/2 Count clock BCLK/2 TCLK TCLK Count clock TCLK TCLK TCLK Count clock BCLK/2 Item Function BCLK/2 Rising edge Falling edge Both edges L level H level (1) Functions of TCLK Input Processing Control Registers

10-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) Functions of TIN Input Processing Control Registers Internal edge signal Internal edge signal Internal edge signal Prescaler output period or TCLK input period TIN TIN Internal edge signal TIN TIN TIN Internal edge signal Prescaler output period or TCLK input period Item Function Rising edge Falling edge Both edges L level H level

10-1732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TLCK Input Processing Control Register (TCLKCR) <Address: H’0080 0210> <Upon exiting reset: H’0000> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00 2, 3 TCLK3S 00: BCLK/2 R W TCLK3 input processing select bit 01: Rising edge 10: Falling edge 11: Both edges 4 No function assigned. Fix to "0". 00 5–7 TCLK2S 000: Disable input R W TCLK2 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: L level 101: L level 110: H level 111: H level 8 No function assigned. Fix to "0". 00 9–11 TCLK1S 000: Disable input R W TCLK1 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: L level 101: L level 110: H level 111: H level 12,13 No function assigned. Fix to "0". 00 14,15 TCLK0S 00: BCLK/2 R W TCLK0 input processing select bit 01: Rising edge 10: Falling edge 11: Both edges Note: This register must always be accessed in halfwords. b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TCLK3S TCLK2S TCLK1S TCLK0S 0000000000000000

10-1832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIN Input Processing Control Register 0 (TINCR0) <Address: H’0080 0212> <Upon exiting reset: H’0000> b Bit Name Function R W 0 No function assigned. Fix to "0". 00 1–3 TIN4S Fix to "0". 0 0 Reserved bit 4 No function assigned. Fix to "0". 00 5–7 TIN3S 000: Disable input R W TIN3 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges 100: L level 101: L level 110: H level 111: H level 8, 9 No function assigned. Fix to "0". 00 10,11 TIN2S Fix to "0". 0 0 Reserved bit 12,13 TIN1S Fix to "0". 0 0 Reserved bit 14,15 TIN0S 00: Disable input R W TIN0 input processing select bit 01: Rising edge 10: Falling edge 11: Both edges Note: This register must always be accessed in halfwords. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIN4S TIN3S TIN2S TIN1S TIN0S 0000000000000000

10-1932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIN Input Processing Control Register 3 (TINCR3) <Address: H’0080 0218> <Upon exiting reset: H’0000> b Bit Name Function R W 0, 1 TIN19S (TIN19 input processing select bit) 00: Disable input R W 2, 3 TIN18S (TIN18 input processing select bit) 01: Rising edge 4, 5 TIN17S (TIN17 input processing select bit) 10: Falling edge 6, 7 TIN16S (TIN16 input processing select bit) 11: Both edges 8, 9 TIN15S (Reserved bit) Fix to "0". 0 0 10, 11 TIN14S (Reserved bit) 12, 13 TIN13S (Reserved bit) 14, 15 TIN12S (Reserved bit) Note: This register must always be accessed in halfwords. TIN Input Processing Control Register 4 (TINCR4) <Address: H’0080 021A> <Upon exiting reset: H’0000> b Bit Name Function R W 0, 1 TIN33S (Reserved bit) Fix to "0". 0 0 2, 3 TIN32S (Reserved bit) 4, 5 TIN31S (Reserved bit) 6, 7 TIN30S (Reserved bit) 8, 9 TIN23S (TIN23 input processing select bit) 00: Disable input R W 10, 11 TIN22S (TIN22 input processing select bit) 01: Rising edge 12, 13 TIN21S (TIN21 input processing select bit) 10: Falling edge 14, 15 TIN20S (TIN20 input processing select bit) 11: Both edges Note: This register must always be accessed in halfwords. b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TIN19S TIN18S TIN17S TIN16S TIN15S TIN14S TIN13S TIN12S 0000000000000000 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIN33S TIN32S TIN31S TIN30S TIN23S TIN22S TIN21S TIN20S 0000000000000000

10-2032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.2.5 Output Flip-flop Control Unit

The Output Flip-flop Control Unit controls the flip-flops (F/F) provided for each timer. Following flip-flop control registers are included: F/F Source Select Register 0 (FFS0) F/F Source Select Register 1 (FFS1) F/F Protect Register 0 (FFP0) F/F Protect Register 1 (FFP1) F/F Data Register 0 (FFD0) F/F Data Register 1 (FFD1) The timing at which signals are generated to the output flip-flop by each timer are shown in Table 10.2.5. (Note that this timing is different from one at which signals are output from the timer to the output event bus.)

10.2.5 Timing at Which Signals Are Generated to the Output Flip-Flop by Each Timer

Timer Mode Timing at which signals are generated to the output flip-flop TOP Single-shot output mode When counter is enabled or underflows Delayed single-shot output mode When counter underflows Continuous output mode When counter is enabled or underflows TIO Measure clear input mode When counter underflows Measure free-run input mode When counter underflows Noise processing input mode When counter underflows PWM output mode When counter is enabled or underflows Single-shot output mode When counter is enabled or underflows Delayed single-shot output mode When counter underflows Continuous output mode When counter is enabled or underflows TMS (16-bit measure input) No signals generated TML (32-bit measure input) No signals generated Figure 10.2.2 Configuration of the F/F Output Circuit Table Output event bus 0 Data bus F/F protect (FPn) WR Data bus Output control (ON/OFF) TOn Internal edge signal Port operation mode register (PnMOD) F/Fn output data (FDn) TOP TIO F/F source selection (FFn) Output event bus 1 Output event bus 2 Output event bus 3 F/F F/F F/Fudf

10-2132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 F/F Source Select Register 0 (FFS0) <Address: H’0080 0220> <Upon exiting reset: H’0000> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00

3 FF15 0: TIO4 output R W

F/F15 source select bit 1: Output event bus 0

4 FF14 0: TIO3 output R W

F/F14 source select bit 1: Output event bus 0

5 FF13 0: TIO2 output R W

F/F13 source select bit 1: Output event bus 3

6 FF12 0: TIO1 output R W

F/F12 source select bit 1: Output event bus 2

7 FF11 0: TIO0 output R W

F/F11 source select bit 1: Output event bus 1 8, 9 FF10 00: TOP10 output R W F/F10 source select bit 01: TOP10 output 10: Output event bus 0 11: Output event bus 1 10, 11 FF9 00: TOP9 output R W F/F9 source select bit 01: TOP9 output 10: Output event bus 0 11: Output event bus 1 12, 13 FF8 00: TOP8 output R W F/F8 source select bit 01: Output event bus 0 10: Output event bus 1 11: Output event bus 2

14 FF7 0: TOP7 output R W

F/F7 source select bit 1: Output event bus 0

15 FF6 0: TOP6 output R W

F/F6 source select bit 1: Output event bus 1 Note: This register must always be accessed in halfwords. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 FF15 FF14 FF13 FF12 FF11 FF10 FF9 FF8 FF7 FF6 0000000000000000

10-2232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 F/F Source Select Register 1 (FFS1) <Address: H’0080 0223> <Upon exiting reset: H’0000> b Bit Name Function R W 8, 9 FF19 00: TIO8 output R W F/F19 source select bit 01: TIO8 output 10: Output event bus 0 11: Output event bus 1 10, 11 FF18 00: TIO7 output R W F/F18 source select bit 01: TIO7 output 10: Output event bus 0 11: Output event bus 1 12, 13 FF17 00: TIO6 output R W F/F17 source select bit 01: TIO6 output 10: Output event bus 0 11: Output event bus 1 14, 15 FF16 00: TIO5 output R W F/F16 source select bit 01: Output event bus 0 10: Output event bus 1 11: Output event bus 3 These registers select the signal source for each output F/F (flip-flop). This signal source can be chosen to be a signal from the internal output bus or an underflow output from each timer. b 8 9 1 01 11 21 31 4 b 1 5 FF19 FF18 FF17 FF16 0 0000000

10-2332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 F/F Protect Register 0 (FFP0) <Address: H’0080 0224> <Upon exiting reset: H’0000> b Bit Name Function R W

0 FP15 (F/F15 protect bit) 0: Enable write to F/F output bit R W

1 FP14 (F/F14 protect bit) 1: Disable write to F/F output bit

2 FP13 (F/F13 protect bit)

3 FP12 (F/F12 protect bit)

4 FP11 (F/F11 protect bit)

5 FP10 (F/F10 protect bit)

6 FP9 (F/F9 protect bit)

7 FP8 (F/F8 protect bit)

8 FP7 (F/F7 protect bit)

9 FP6 (F/F6 protect bit)

10 FP5 (F/F5 protect bit)

11 FP4 (F/F4 protect bit)

12 FP3 (F/F3 protect bit)

13 FP2 (F/F2 protect bit)

14 FP1 (F/F1 protect bit)

15 FP0 (F/F0 protect bit)

Note: This register must always be accessed in halfwords. F/F Protect Register 1 (FFP1) <Address: H’0080 0229> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 FP20 (F/F20 protect bit) 0: Enable write to F/F output bit R W

12 FP19 (F/F19 protect bit) 1: Disable write to F/F output bit

13 FP18 (F/F18 protect bit)

14 FP17 (F/F17 protect bit)

15 FP16 (F/F16 protect bit)

These registers enable or disable write to each output F/F (flip-flop). If write to any output F/F is disabled, writing to the corresponding F/F data register has no effect. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 0000000000000000 b 8 9 1 01 11 21 31 4 b 1 5 FP20 FP19 FP18 FP17 FP16 00000000

10-2432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 F/F Data Register 0 (FFD0) <Address: H’0080 0226> <Upon exiting reset: H’0000> b Bit Name Function R W

0 FD15 (F/F15 output data bit) 0: F/F output data = 0 R W

1 FD14 (F/F14 output data bit) 1: F/F output data = 1

2 FD13 (F/F13 output data bit)

3 FD12 (F/F12 output data bit)

4 FD11 (F/F11 output data bit)

5 FD10 (F/F10 output data bit)

6 FD9 (F/F9 output data bit)

7 FD8 (F/F8 output data bit)

8 FD7 (F/F7 output data bit)

9 FD6 (F/F6 output data bit)

10 FD5 (F/F5 output data bit)

11 FD4 (F/F4 output data bit)

12 FD3 (F/F3 output data bit)

13 FD2 (F/F2 output data bit)

14 FD1 (F/F1 output data bit)

15 FD0 (F/F0 output data bit)

Note: This register must always be accessed in halfwords. F/F Data Register 1 (FFD1) <Address: H’0080 022B> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 00

11 FD20 (F/F20 output data bit) 0: F/F output data = 0 R W

12 FD19 (F/F19 output data bit) 1: F/F output data = 1

13 FD18 (F/F18 output data bit)

14 FD17 (F/F17 output data bit)

15 FD16 (F/F16 output data bit)

These registers are used to set the data for each output F/F (flip-flop). Although the F/F outputs normally change state depending on timer outputs, the F/F outputs can be set to 1 or cleared to 0 as necessary by writing to this register. The F/F data register can only be operated on when the F/F protect register described previously is enabled for write. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 FD15 FD14 FD13 FD12 FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 0000000000000000 b 8 9 1 01 11 21 31 4 b 1 5 FD20 FD19 FD18 FD17 FD16 00000000

10-2532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.2.6 Interrupt Control Unit

The Interrupt Control Unit controls the interrupt request signals output to the Interrupt Controller by each timer. Following timer interrupt control registers are provided for each timer: TOP Interrupt Control Register 0 (TOPIR0) TOP Interrupt Control Register 1 (TOPIR1) TOP Interrupt Control Register 2 (TOPIR2) TOP Interrupt Control Register 3 (TOPIR3) TIO Interrupt Control Register 0 (TIOIR0) TIO Interrupt Control Register 1 (TIOIR1) TIO Interrupt Control Register 2 (TIOIR2) TMS Interrupt Control Register (TMSIR) TIN Interrupt Control Register 0 (TINIR0) TIN Interrupt Control Register 1 (TINIR1) TIN Interrupt Control Register 4 (TINIR4) TIN Interrupt Control Register 5 (TINIR5) TIN Interrupt Control Register 6 (TINIR6) For interrupts which have only one interrupt source in the interrupt vector table, no interrupt control registers are included in the timer, and the interrupt status flags are automatically managed within the Interrupt Control- ler. The relevant timer interrupt is the following. (For details, see Chapter 5, “Interrupt Controller.”) TOP10 MJT Output Interrupt 5 (IRQ5)

10-2632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.2.3 Interrupt Request Status and Mask Registers For interrupts which have two or more interrupt sources in the interrupt vector table, interrupt control registers are included, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in the Interrupt Controller only serve as a bit to determine interrupt requests from interrupt-enabled sources and cannot be accessed for write. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt mask bit, it can be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt mask bit This bit is used to disable unnecessary interrupts within the grouped interrupt. Set this bit to "0" to enable interrupts or "1" to disable interrupts. To the Interrupt Controller Timer or TIN input interrupt request Interrupt request status Data bus Set Group interrupt Interrupt enabled clear F/F F/F Data = 0

10-2732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.2.4 Example for Clearing Interrupt Request Status b4 5 b7 Interrupt request status Initial state Event occurs on bit 6 Interrupt request Event occurs on bit 4 Only bit 6 cleared Bit 4 data retained b4 5 b7 1 1 0 1 Write to the interrupt request status Example for clearing interrupt request status 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 Program example ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */ To clear the Interrupt Request Status Register (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. b4 5 6 b7 Interrupt request status Event occurs on bit 6 Event occurs on bit 4 Only bit 6 cleared Bit 4 also cleared 0 0 1 0 1 0 1 0 0 0 0 0 Read 0 0 1 0 0 0 0 0 Clear bit 6 (ANDing with 1101) Write ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */

10-2832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The table below shows the relationship between the interrupt signals generated by multijunction timers and the interrupt sources input to the Interrupt Controller (ICU). Table 10.2.6 Interrupt Signals Generated by MJT Signal Name Generated by ICU Interrupt Input Source (Note 1) No. of Input Sources IRQ0 TIO0, TIO1, TIO2, TIO3 MJT output interrupt 0 4 IRQ1 TOP6, TOP7 MJT output interrupt 1 2 IRQ2 TOP0, TOP1, TOP2, TOP3, TOP4, TOP5 MJT output interrupt 2 6 IRQ3 TIO8, TIO9 MJT output interrupt 3 2 IRQ4 TIO4, TIO5, TIO6, TIO7 MJT output interrupt 4 4 IRQ6 TOP8, TOP9 MJT output interrupt 6 2 IRQ7 TMS0, TMS1 MJT output interrupt 7 2 IRQ9 TIN0 MJT input interrupt 1 1 IRQ10 TIN16, TIN17, TIN18, TIN19 MJT input interrupt 2 4 IRQ11 TIN20, TIN21, TIN22, TIN23 MJT input interrupt 3 4 IRQ12 TIN3 MJT input interrupt 4 1 Note 1: See Chapter 5, “Interrupt Controller (ICU).” Note: TOP10 has only one interrupt source in each interrupt group, so that their status and mask registers are nonexistent in the MJT interrupt control registers. (They are controlled directly by the Interrupt Controller.)

10-2932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TOP Interrupt Control Register 0 (TOPIR0) <Address: H’0080 0230> <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00

2 TOPIS5 (TOP5 interrupt request status bit) 0: Interrupt not requested R(Note 1)

3 TOPIS4 (TOP4 interrupt request status bit) 1: Interrupt requested

4 TOPIS3 (TOP3 interrupt request status bit)

5 TOPIS2 (TOP2 interrupt request status bit)

6 TOPIS1 (TOP1 interrupt request status bit)

7 TOPIS0 (TOP0 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TOP Interrupt Control Register 1 (TOPIR1) <Address: H’0080 0231> <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 No function assigned. Fix to "0". 00

10 TOPIM5 (TOP5 interrupt request mask bit) 0: Enable interrupt request R W

11 TOPIM4 (TOP4 interrupt request mask bit) 1: Mask (disable) interrupt request

12 TOPIM3 (TOP3 interrupt request mask bit)

13 TOPIM2 (TOP2 interrupt request mask bit)

14 TOPIM1 (TOP1 interrupt request mask bit)

15 TOPIM0 (TOP0 interrupt request mask bit)

TOPIS5 TOPIS4 TOPIS3 TOPIS2 TOPIS1 TOPIS0 0 0000000 b 8 9 1 01 11 21 31 4 b 1 5 TOPIM5 TOPIM4 TOPIM3 TOPIM2 TOPIM1 TOPIM0 0 0000000

10-3032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.2.5 Block Diagram of MJT Output Interrupt 2 MJT output interrupt 2 IRQ2 Data bus TOPIS5 F/F TOPIM5 F/Fb10 TOPIS4 F/F TOPIM4 F/Fb11 b4 TOPIS3 F/F TOPIM3 F/Fb12 b5 TOPIS2 F/F TOPIM2 F/Fb13 b6 TOPIS1 F/F TOPIM1 F/Fb14 TOPIS0 F/F TOPIM0 F/Fb15 (Level) 6-source inputs TOPIR0 <H'0080 0230> TOPIR1 <H'0080 0231> TOP5udf TOP4udf TOP3udf TOP2udf TOP1udf TOP0udf

10-3132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TOP Interrupt Control Register 2 (TOPIR2) <Address: H’0080 0232> <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00

2 TOPIS7 (TOP7 interrupt request status bit) 0: Interrupt not requested R(Note 1)

3 TOPIS6 (TOP6 interrupt request status bit) 1: Interrupt requested

4, 5 No function assigned. Fix to "0". 00

6 TOPIM7 (TOP7 interrupt request mask bit) 0: Enable interrupt request R W

7 TOPIM6 (TOP6 interrupt request mask bit) 1: Mask (disable) interrupt request

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MJT output interrupt 1 IRQ1 Data bus TOPIS7 F/F TOPIM7 F/Fb6 TOPIS6 F/F TOPIM6 F/Fb7 (Level) 2-source inputs TOPIR2 <H'0080 0232> TOP7udf TOP6udf Figure 10.2.6 Block Diagram of MJT Output Interrupt 1 b 0 123456 b 7 TOPIS7 TOPIS6 TOPIM7 TOPIM6 00000000

10-3232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TOP Interrupt Control Register 3 (TOPIR3) <Address: H’0080 0233> <Upon exiting reset: H’00> b Bit Name Function R W 8,9 No function assigned. Fix to "0". 00

10 TOPIS9 (TOP9 interrupt request status bit) 0: Interrupt not requested R(Note 1)

11 TOPIS8 (TOP8 interrupt request status bit) 1: Interrupt requested

12,13 No function assigned. Fix to "0". 00

14 TOPIM9 (TOP9 interrupt request mask bit) 0: Enable interrupt request R W

15 TOPIM8 (TOP8 interrupt request mask bit) 1: Mask (disable) interrupt request

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Note: TOP10 has only one interrupt source in the interrupt group, so that its status and mask registers are nonexistent in the MJT interrupt control registers. (They are controlled directly by the Interrupt Controller.) b10 TOPIS9 F/F TOPIM9 F/Fb14 b11 TOPIS8 F/F TOPIM8 F/Fb15 MJT output interrupt 6 IRQ6(Level) 2-source inputs TOPIR3 <H'0080 0233> Data bus TOP9udf TOP8udf Figure 10.2.7 Block Diagram of MJT Output Interrupt 6 b 8 9 1 01 11 21 31 4 b 1 5 TOPIS9 TOPIS8 TOPIM9 TOPIM8 00000000

10-3332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIO Interrupt Control Register 0 (TIOIR0) <Address: H’0080 0234> <Upon exiting reset: H’00> b Bit Name Function R W

0 TIOIS3 (TIO3 interrupt request status bit) 0: Interrupt not requested R(Note 1)

1 TIOIS2 (TIO2 interrupt request status bit) 1: Interrupt requested

2 TIOIS1 (TIO1 interrupt request status bit)

3 TIOIS0 (TIO0 interrupt request status bit)

4 TIOIM3 (TIO3 interrupt request mask bit) 0: Enable interrupt request R W

5 TIOIM2 (TIO2 interrupt request mask bit) 1: Mask (disable) interrupt request

6 TIOIM1 (TIO1 interrupt request mask bit)

7 TIOIM0 (TIO0 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MJT output interrupt 0 IRQ0 Data bus TIOIS3 F/F TIOIM3 F/Fb4 TIOIS2 F/F TIOIM2 F/Fb5 b2 TIOIS1 F/F TIOIM1 F/Fb6 b3 TIOIS0 F/F TIOIM0 F/Fb7 (Level) 4-source inputs TIOIR0 <H'0080 0234> TIO3udf TIO2udf TIO1udf TIO0udf Figure 10.2.8 Block Diagram of MJT Output Interrupt 0 b 0 123456 b 7 TIOIS3 TIOIS2 TIOIS1 TIOIS0 TIOIM3 TIOIM2 TIOIM1 TIOIM0 00000000

10-3432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIO Interrupt Control Register 1 (TIOIR1) <Address: H’0080 0235> <Upon exiting reset: H’00> b Bit Name Function R W

8 TIOIS7 (TIO7 interrupt request status bit) 0: Interrupt not requested R(Note 1)

9 TIOIS6 (TIO6 interrupt request status bit) 1: Interrupt requested

10 TIOIS5 (TIO5 interrupt request status bit)

11 TIOIS4 (TIO4 interrupt request status bit)

12 TIOIM7 (TIO7 interrupt request mask bit) 0: Enable interrupt request R W

13 TIOIM6 (TIO6 interrupt request mask bit) 1: Mask (disable) interrupt request

14 TIOIM5 (TIO5 interrupt request mask bit)

15 TIOIM4 (TIO4 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MJT output interrupt 4 IRQ4 Data bus TIOIS7 F/F TIOIM7 F/Fb12 b9 TIOIS6 F/F TIOIM6 F/Fb13 b10 TIOIS5 F/F TIOIM5 F/Fb14 b11 TIOIS4 F/F TIOIM4 F/Fb15 (Level) 4-source inputs TIOIR1 <H'0080 0235> TIO7udf TIO6udf TIO5udf TIO4udf Figure 10.2.9 Block Diagram of MJT Output Interrupt 4 b 8 9 1 01 11 21 31 4 b 1 5 TIOIS7 TIOIS6 TIOIS5 TIOIS4 TIOIM7 TIOIM6 TIOIM5 TIOIM4 00000000

10-3532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIO Interrupt Control Register 2 (TIOIR2) <Address: H’0080 0236> <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00

2 TIOIS9 (TIO9 interrupt request status bit) 0: Interrupt not requested R(Note 1)

3 TIOIS8 (TIO8 interrupt request status bit) 1: Interrupt requested

4, 5 No function assigned. Fix to "0". 00

6 TIOIM9 (TIO9 interrupt request mask bit) 0: Enable interrupt request R W

7 TIOIM8 (TIO8 interrupt request mask bit) 1: Mask (disable) interrupt request

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MJT output interrupt 3 IRQ3 Data bus TIOIS9 F/F TIOIM9 F/Fb6 TIOIS8 F/F TIOIM8 F/Fb7 (Level) 2-source inputs TIOIR2 <H'0080 0236> TIO9udf TIO8udf Figure 10.2.10 Block Diagram of MJT Output Interrupt 3 b 0 123456 b 7 TIOIS9 TIOIS8 TIOIM9 TIOIM8 00000000

10-3632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TMS Interrupt Control Register (TMSIR) <Address: H’0080 0237> <Upon exiting reset: H’00> b Bit Name Function R W 8, 9 No function assigned. Fix to "0". 00

10 TMSIS1 (TMS1 interrupt request status bit) 0: Interrupt not requested R(Note 1)

11 TMSIS0 (TMS0 interrupt request status bit) 1: Interrupt requested

12, 13 No function assigned. Fix to "0". 00

14 TMSIM1 (TMS1 interrupt request mask bit) 0: Enable interrupt request R W

15 TMSIM0 (TMS0 interrupt request mask bit) 1: Mask (disable) interrupt request

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. MJT output interrupt 7 IRQ7 Data bus b10 TMSIS1 F/F TMSIM1 F/Fb14 b11 TMSIS0 F/F TMSIM0 F/Fb15 (Level) 2-source inputs TMSIR <H'0080 0237> TMS1ovf TMS0ovf Figure 10.2.11 Block Diagram of MJT Output Interrupt 7 b 8 9 1 01 11 21 31 4 b 1 5 TMSIS1 TMSIS0 TMSIM1 TMSIM0 00000000

10-3732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIN Interrupt Control Register 0 (TINIR0) <Address: H’0080 0238> <Upon exiting reset: H’00> b Bit Name Function R W 0-2 No function assigned. Fix to "0". 00

3 TINIS0 0: Interrupt not requested R(Note 1)

TIN0 interrupt request status bit 1: Interrupt requested 4 No function assigned. Fix to "0". 00 5 TINIM2 Fix to "0". 0 0 Reserved bit

6 TINIM1

7 TINIM0 0: Enable interrupt request R W

TIN0 interrupt request mask bit 1: Mask (disable) interrupt request Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Figure 10.2.12 Block Diagram of MJT Input Interrupt 1 MJT input interrupt 1 IRQ9 Data bus b3 TINIS0 F/F TINIM0 F/Fb7 (Level) TINIR0 <H'0080 0238> TIN0edge b 0 123456 b 7 TINIS0 TINIM2 TINIM1 TINIM0 00000000

10-3832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIN Interrupt Control Register 1 (TINIR1) <Address: H’0080 0239> <Upon exiting reset: H’00> b Bit Name Function R W 8-10 No function assigned. Fix to "0". 00

11 TINIS3 0: Interrupt not requested R(Note 1)

TIN3 interrupt request status bit 1: Interrupt requested 12 TINIM6 Fix to "0". 0 0 Reserved bit

13 TINIM5

14 TINIM4

15 TINIM3 0: Enable interrupt request R W

TIN3 interrupt request mask bit 1: Mask (disable) interrupt request Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Figure 10.2.13 Block Diagram of MJT Input Interrupt 4 MJT input interrupt 4 IRQ12 Data bus (Level) TINIR1 <H'0080 0239> b11 TINIS3 F/F TINIM3 F/Fb15 TIN3edge b 8 9 1 01 11 21 31 4 b 1 5 TINIS3 TINIM6 TINIM5 TINIM4 TINIM3 00000000

10-3932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIN Interrupt Control Register 4 (TINIR4) <Address: H’0080 023C> <Upon exiting reset: H’00> b Bit Name Function R W

0 TINIS19 (TIN19 interrupt request status bit) 0: Interrupt not requested R(Note 1)

1 TINIS18 (TIN18 interrupt request status bit) 1: Interrupt requested

2 TINIS17 (TIN17 interrupt request status bit)

3 TINIS16 (TIN16 interrupt request status bit)

4-7 No function assigned. Fix to "0". 00 Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. TIN Interrupt Control Register 5 (TINIR5) <Address: H’0080 023D> <Upon exiting reset: H’00> b Bit Name Function R W

8 TINIM19 (TIN19 interrupt request mask bit) 0: Enable interrupt request R W

9 TINIM18 (TIN18 interrupt request mask bit) 1: Mask (disable) interrupt request

10 TINIM17 (TIN17 interrupt request mask bit)

11 TINIM16 (TIN16 interrupt request mask bit)

12 TINIM15 (Reserved bit) Fix to "0". 0 0

13 TINIM14 (Reserved bit)

14 TINIM13 (Reserved bit)

15 TINIM12 (Reserved bit)

TINIS19 TINIS18 TINIS17 TINIS16 00000000 b 8 9 1 01 11 21 31 4 b 1 5 TINIM19 TINIM18 TINIM17 TINIM16 TINIM15 TINIM14 TINIM13 TINIM12 00000000

10-4032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.2.14 Block Diagram of MJT Input Interrupt 2 MJT input interrupt 2 IRQ10 Data bus TINIS19 F/F TINIM19 F/Fb8 TINIS18 F/F TINIM18 F/Fb9 b2 TINIS17 F/F TINIM17 F/Fb10 b3 TINIS16 F/F TINIM16 F/Fb11 (Level) 4-source inputs TINIR4 <H'0080 023C> TINIR5 <H'0080 023D> TIN19edge TIN18edge TIN17edge TIN16edge

10-4132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIN Interrupt Control Register 6 (TINIR6) <Address: H’0080 023E> <Upon exiting reset: H’00> b Bit Name Function R W

0 TINIS23 (TIN23 interrupt request status bit) 0: Interrupt not requested R(Note 1)

1 TINIS22 (TIN22 interrupt request status bit) 1: Interrupt requested

2 TINIS21 (TIN21 interrupt request status bit)

3 TINIS20 (TIN20 interrupt request status bit)

4 TINIM23 (TIN23 interrupt request mask bit) 0: Enable interrupt request R W

5 TINIM22 (TIN22 interrupt request mask bit) 1: Mask (disable) interrupt request

6 TINIM21 (TIN21 interrupt request mask bit)

7 TINIM20 (TIN20 interrupt request mask bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Figure 10.2.15 Block Diagram of MJT Input Interrupt 3 MJT input interrupt 3 IRQ11 Data bus TINIS23 F/F TINIM23 F/Fb4 TINIS22 F/F TINIM22 F/Fb5 b2 TINIS21 F/F TINIM21 F/Fb6 b3 TINIS20 F/F TINIM20 F/Fb7 4-source inputs TINIR6 <H'0080 023E> TIN23edge TIN22edge TIN21edge TIN20edge (Level) b 0 123456 b 7 TINIS23 TINIS22 TINIS21 TINIS20 TINIM23 TINIM22 TINIM21 TINIM20 00000000

10-4232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.3.1 Outline of TOP

TOP (Timer OutPut) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software:

Single-shot output mode Delayed single-shot output mode Continuous output mode Table 10.3.1 Specifications of TOP (Output-Related 16-Bit Timer) Item Specification Number of channels 11 channels Counter 16-bit down-counter Reload register 16-bit reload register Correction register 16-bit correction register Timer startup Started by writing to the enable bit in software or enabled by external input (rising or falling edge or both) Mode switching <With correction function> Single-shot output mode Delayed single-shot output mode <Without correction function> Continuous output mode Interrupt request generation Can be generated by a counter underflow

10-4332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.3.1 Block Diagram of TOP (Output-Related 16-Bit Timer) IRQ2 clk en udf TOP 0 Clock bus Input event bus clk en udfTOP 1 clk en udfTOP 2 clk en udfTOP 3 Output event bus TCLK0S TO 0 (P110) IRQ9 3 2 1 0 clk en udfTOP 4 clk en udfTOP 5 TCLK0 (P124) TIN0 (P150) S STIN0S clk en udfTOP 6 clk en udfTOP 7 S S S S S clk en udfTOP 8 clk en udfTOP 9 clk en udfTOP 10 F/F0 F/F1 F/F2 F/F3 F/F4 F/F5 F/F6 F/F7 F/F8 F/F9 F/F10 S : SelectorF/F :Output flip-flop S S S S S IRQ2 IRQ2 IRQ2 IRQ2 IRQ2 TO 1 (P111) TO 2 (P112) TO 3 (P113) TO 4 (P114) TO 5 (P115) TO 6 (P116) TO 7 (P117) TO 8 (P100) TO 9 (P101) TO 10 (P102) IRQ1 IRQ1 IRQ6 IRQ6 IRQ5 3 2 1 0 0 1 2 3 Reload register Down-counter Correction register 3 2 1 0 3 2 1 0 0 1 2 3 (16-bit) DMA3

10-4432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.3.2 Outline of Each Mode of TOP

Each mode of TOP is outlined below. For each TOP channel, only one of the following modes can be selected. (1) Single-shot output mode In single-shot output mode, the timer generates a pulse in width of "reload register set value +1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload register, the counter is loaded with the content of "the reload register -1" and starts counting synchro- nously with the count clock at the next cycle. The counter counts down and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted at enable and upon underflow, generating a single-shot pulse waveform in width of "reload register set value + 1" only once. An interrupt request can be generated when the counter underflows. The counter value is "setting value of reload register +1." (2) Delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of "reload register set value + 1" after a finite time equal to "counter set value +1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. The next cycle after first time counter underflow, it is loaded with "the reload register -1" and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first time and next, generating a single-shot pulse waveform in width of "reload register set value +1" after a finite time equal to "first set value of counter +1" only once. An interrupt request can be generated when the counter underflows first time and next. The effective counter value is "counter set value + 1" or "reload register set value +1." (3) Continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses, invert in width of "reload register set value +1." When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. At the cycle after this underflow, the counter to be loaded with the content of "the reload register -1" and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each time the counter underflows. The effective counter value is "counter set value + 1" or "reload register set value +1."

10-4532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 <Count clock-dependent delay> Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated by the time when the timer actually starts operating after writing to the enable bit. In operation mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is inverted. BCLK Count clock Enable F/F operation (Note 1) Count clock period Count clock-dependent delay Write to the enable bit Note 1: This applies to the case where F/F output is inverted when the timer is enabled. Inverted Figure 10.3.2 Count Clock Dependent Delay

10-4632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.3.3 TOP Related Register Map

Shown below is a TOP related register map. TOP Related Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0240 TOP0 Counter 10-53 (TOP0CT) H'0080 0242 TOP0 Reload Register 10-54 (TOP0RL) H'0080 0244 (Use inhibited area) H'0080 0246 TOP0 Correction Register 10-55 (TOP0CC) (Use inhibited area) H'0080 0250 TOP1 Counter 10-53 (TOP1CT) H'0080 0252 TOP1 Reload Register 10-54 (TOP1RL) H'0080 0254 (Use inhibited area) H'0080 0256 TOP1 Correction Register 10-55 (TOP1CC) (Use inhibited area) H'0080 0260 TOP2 Counter 10-53 (TOP2CT) H'0080 0262 TOP2 Reload Register 10-54 (TOP2RL) H'0080 0264 (Use inhibited area) H'0080 0266 TOP2 Correction Register 10-55 (TOP2CC) (Use inhibited area) H'0080 0270 TOP3 Counter 10-53 (TOP3CT) H'0080 0272 TOP3 Reload Register 10-54 (TOP3RL) H'0080 0274 (Use inhibited area) H'0080 0276 TOP3 Correction Register 10-55 (TOP3CC) (Use inhibited area) H'0080 0280 TOP4 Counter 10-53 (TOP4CT) H'0080 0282 TOP4 Reload Register 10-54 (TOP4RL) H'0080 0284 (Use inhibited area) H'0080 0286 TOP4 Correction Register 10-55 (TOP4CC) (Use inhibited area) H'0080 0290 TOP5 Counter 10-53 (TOP5CT) H'0080 0292 TOP5 Reload Register 10-54 (TOP5RL) H'0080 0294 (Use inhibited area) H'0080 0296 TOP5 Correction Register 10-55 (TOP5CC) H'0080 0298 (Use inhibited area)

10-4732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TOP Related Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 029A TOP0–5 Control Register 0 10-49 (TOP05CR0) H'0080 029C (Use inhibited area) TOP0–5 Control Register 1 10-49 (TOP05CR1) H'0080 029E (Use inhibited area) H'0080 02A0 TOP6 Counter 10-53 (TOP6CT) H'0080 02A2 TOP6 Reload Register 10-54 (TOP6RL) H'0080 02A4 (Use inhibited area) H'0080 02A6 TOP6 Correction Register 10-55 (TOP6CC) H'0080 02A8 (Use inhibited area) H'0080 02AA TOP6,7 Control Register 10-51 (TOP67CR) (Use inhibited area) H'0080 02B0 TOP7 Counter 10-53 (TOP7CT) H'0080 02B2 TOP7 Reload Register 10-54 (TOP7RL) H'0080 02B4 (Use inhibited area) H'0080 02B6 TOP7 Correction Register 10-55 (TOP7CC) (Use inhibited area) H'0080 02C0 TOP8 Counter 10-53 (TOP8CT) H'0080 02C2 TOP8 Reload Register 10-54 (TOP8RL) H'0080 02C4 (Use inhibited area) H'0080 02C6 TOP8 Correction Register 10-55 (TOP8CC) (Use inhibited area) H'0080 02D0 TOP9 Counter 10-53 (TOP9CT) H'0080 02D2 TOP9 Reload Register 10-54 (TOP9RL) H'0080 02D4 (Use inhibited area) H'0080 02D6 TOP9 Correction Register 10-55 (TOP9CC) (Use inhibited area) H'0080 02E0 TOP10 Counter 10-53 (TOP10CT) H'0080 02E2 TOP10 Reload Register 10-54 (TOP10RL) H'0080 02E4 (Use inhibited area) H'0080 02E6 TOP10 Correction Register 10-55 (TOP10CC) H'0080 02E8 (Use inhibited area) H'0080 02EA TOP8–10 Control Register 10-52 (TOP810CR) (Use inhibited area) H'0080 02FA TOP0-10 External Enable Permit Register 10-56 (TOPEEN) H'0080 02FC TOP0-10 Enable Protect Register 10-56 (TOPPRO) H'0080 02FE TOP0-10 Count Enable Register 10-57 (TOPCEN)

10-4832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.3.4 TOP Control Registers

The TOP control registers are used to select operation modes of TOP0–10 (single-shot output, delayed single- shot output or continuous output mode), as well as select the count enable and count clock sources. Following TOP control registers are provided for each timer group. TOP0–5 Control Register 0 (TOP05CR0) TOP0–5 Control Register 1 (TOP05CR1) TOP6,7 Control Register (TOP67CR) TOP8–10 Control Register (TOP810CR)

10-4932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TOP0–5 Control Register 0 (TOP05CR0) <Address: H’0080 029A> <Upon exiting reset: H’0000> b Bit Name Function R W 0, 1 TOP3M (TOP3 operation mode select bit) 00: Single-shot output mode R W 2, 3 TOP2M (TOP2 operation mode select bit) 01: Delayed single-shot output mode 4, 5 TOP1M (TOP1 operation mode select bit) 10: Continuous output mode 6, 7 TOP0M (TOP0 operation mode select bit) 11: Continuous output mode 8 No function assigned. Fix to "0". 00 9–11 TOP05ENS 000: External TIN0 input R W TOP0–5 enable source select bit 001: External TIN0 input 010: External TIN0 input 011: External TIN0 input 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12, 13 No function assigned. Fix to "0". 00 14, 15 TOP05CKS 00: Clock bus 0 R W TOP0–5 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes: This register must always be accessed in halfwords. Operation mode can only be set or changed while the counter is inactive. TOP0–5 Control Register 1 (TOP05CR1) <Address: H’0080 029D> <Upon exiting reset: H’00> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12, 13 TOP5M (TOP5 operation mode select bit) 00: Single-shot output mode R W 14, 15 TOP4M (TOP4 operation mode select bit) 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode Note: Operation mode can only be set or changed while the counter is inactive. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP3M TOP2M TOP1M TOP0M TOP05ENS TOP05CKS 0 000000000000000 b 8 9 1 01 11 21 31 4 b 1 5 TOP5M TOP4M 00000000

10-5032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 clk en TOP 0 Clock bus Input event bus clk en TOP 1 clk en TOP 2 clk en TOP 3 3 2 1 0 clk en TOP 4 clk en TOP 5 S S : Selector TIN0 (P150) S TIN0S 3 2 1 0 Note: This diagram only illustrates TOP control registers and is partly omitted. IRQ9 DMA3 Figure 10.3.3 Outline Diagram of TOP0–5 Clock and Enable Inputs

10-5132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TOP6,7 Control Register (TOP67CR) <Address: H’0080 02AA> <Upon exiting reset: H’0000> b Bit Name Function R W 0 No function assigned. Fix to "0". 00

1 TOP7ENS 0: Result selected by TOP67ENS bit R W

TOP7 enable source select bit 1: TOP6 output 2, 3 TOP7M 00: Single-shot output mode R W TOP7 operation mode select bit 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode 4, 5 No function assigned. Fix to "0". 00 6, 7 TOP6M 00: Single-shot output mode R W TOP6 operation mode select bit 01: Delayed single-shot output mode 10: Continuous output mode 11: Continuous output mode 8 No function assigned. Fix to "0". 00 9–11 TOP67ENS 000: Does not select enable source R W TOP6, TOP7 enable source select bit 001: Does not select enable source (Note 1) 010: Does not select enable source 011: Does not select enable source 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12, 13 No function assigned. Fix to "0". 00 14, 15 TOP67CKS 00: Clock bus 0 R W TOP6, TOP7 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Note 1: This register must always be accessed in halfwords. Note : Operation mode can only be set or changed while the counter is inactive. Clock bus Input event bus 3 2 1 0 clk en udfTOP 6 clk en udfTOP 7 S S S : Selector 3 2 1 0 S Note: This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.4 Outline Diagram of TOP6, TOP7 Clock and Enable Inputs b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP7M TOP6M TOP67ENS TOP67CKS 0 00000000000000 TOP7 ENS

10-5232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Clock bus Input event bus 3 2 1 0 S S clk en TOP 8 clk en TOP 9 clk en TOP 10 S : Selector 3 2 1 0 Note: This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.5 Outline Diagram of TOP8–10 Clock and Enable Inputs TOP8–10 Control Register (TOP810CR) <Address: H’0080 02EA> <Upon exiting reset: H’0000> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00 2, 3 TOP10M 00: Single-shot output mode R W TOP10 operation mode select bit 01: Delayed single-shot output mode 4, 5 TOP9M 10: Continuous output mode TOP9 operation mode select bit 11: Continuous output mode 6, 7 TOP8M TOP8 operation mode select bit 8–10 No function assigned. Fix to "0". 00

11 TOP810ENS 0: Does not select enable source R W

TOP8–10 enable source select bit 1: Input event bus 3 12, 13 No function assigned. Fix to "0". 00 14, 15 TOP810CKS 00: Clock bus 0 R W TOP8–10 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Notes: This register must always be accessed in halfwords. Operation mode can only be set or changed while the counter is inactive. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP10M TOP9M TOP8M TOP810CKS 0 0000000000 0000 TOP810 ENS

10-5332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.3.5 TOP Counters (TOP0CT–TOP10CT)

TOP0 Counter (TOP0CT) <Address: H’0080 0240> TOP1 Counter (TOP1CT) <Address: H’0080 0250> TOP2 Counter (TOP2CT) <Address: H’0080 0260> TOP3 Counter (TOP3CT) <Address: H’0080 0270> TOP4 Counter (TOP4CT) <Address: H’0080 0280> TOP5 Counter (TOP5CT) <Address: H’0080 0290> TOP6 Counter (TOP6CT) <Address: H’0080 02A0> TOP7 Counter (TOP7CT) <Address: H’0080 02B0> TOP8 Counter (TOP8CT) <Address: H’0080 02C0> TOP9 Counter (TOP9CT) <Address: H’0080 02D0> TOP10 Counter (TOP10CT) <Address: H’0080 02E0> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TOP0CT–TOP10CT 16-bit counter value R W Note: These registers must always be accessed in halfwords. The TOP counters are a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by external input), the counter starts counting synchronously with the count clock. b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TOP0CT-TOP10CT

10-5432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.3.6 TOP Reload Registers (TOP0RL–TOP10RL)

TOP0 Reload Register (TOP0RL) <Address: H’0080 0242> TOP1 Reload Register (TOP1RL) <Address: H’0080 0252> TOP2 Reload Register (TOP2RL) <Address: H’0080 0262> TOP3 Reload Register (TOP3RL) <Address: H’0080 0272> TOP4 Reload Register (TOP4RL) <Address: H’0080 0282> TOP5 Reload Register (TOP5RL) <Address: H’0080 0292> TOP6 Reload Register (TOP6RL) <Address: H’0080 02A2> TOP7 Reload Register (TOP7RL) <Address: H’0080 02B2> TOP8 Reload Register (TOP8RL) <Address: H’0080 02C2> TOP9 Reload Register (TOP9RL) <Address: H’0080 02D2> TOP10 Reload Register (TOP10RL) <Address: H’0080 02E2> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TOP0RL–TOP10RL 16-bit reload register value R W Note: These registers must always be accessed in halfwords. The TOP reload registers are used to load data into the TOP counter registers (TOP0CT–TOP10CT). The content of "the reload register -1" is loaded into the counter synchronously with the count clock at the following timing: At the next cycle when the counter is enabled in single-shot output mode At the next cycle when the counter underflowed in delayed single-shot or continuous output mode Simply because data is written to the reload register does not mean that the data is loaded into the counter. The counter is loaded with data in only the above cases. Note that reloading of data after an underflow is performed synchronously with a clock pulse at which the counter underflowed. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP0RL-TOP10RL

10-5532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.3.7 TOP Correction Registers (TOP0CC–TOP10CC)

TOP0 Correction Register (TOP0CC) <Address: H’0080 0246> TOP1 Correction Register (TOP1CC) <Address: H’0080 0256> TOP2 Correction Register (TOP2CC) <Address: H’0080 0266> TOP3 Correction Register (TOP3CC) <Address: H’0080 0276> TOP4 Correction Register (TOP4CC) <Address: H’0080 0286> TOP5 Correction Register (TOP5CC) <Address: H’0080 0296> TOP6 Correction Register (TOP6CC) <Address: H’0080 02A6> TOP7 Correction Register (TOP7CC) <Address: H’0080 02B6> TOP8 Correction Register (TOP8CC) <Address: H’0080 02C6> TOP9 Correction Register (TOP9CC) <Address: H’0080 02D6> TOP10 Correction Register (TOP10CC) <Address: H’0080 02E6> (Acceptable range of values: +32767 to –32768) <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TOP0CC–TOP10CC 16-bit correction register value R W Note: These registers must always be accessed in halfwords. The TOP correction registers are used to correct the TOP counter value by adding or subtracting in the middle of operation. To increase or reduce the counter value, write to this correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the correction register. The counter is corrected synchronously with a clock pulse next to one at which the correction value was written to the TOP correction register. If the counter is corrected this way, note that because one down count in that clock period is canceled, the counter value actually is corrected by (correction register value + 1). For example, if the initial counter value is 10 and the value 3 is written to the correction register when the counter has counted down to 5, then the counter counts a total of 15 before it underflows. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TOP0CC-TOP10CC

10-5632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.3.8 TOP Enable Control Registers

TOP0-10 External Enable Permit Register (TOPEEN) <Address: H’0080 02FA> <Upon exiting reset: H’0000> b Bit Name Function R W 0–4 No function assigned. Fix to "0". 00

5 TOP10EEN (TOP10 external enable permit bit) 0: Disable external enable R W

6 TOP9EEN (TOP9 external enable permit bit) 1: Enable external enable

7 TOP8EEN (TOP8 external enable permit bit)

8 TOP7EEN (TOP7 external enable permit bit)

9 TOP6EEN (TOP6 external enable permit bit)

10 TOP5EEN (TOP5 external enable permit bit)

11 TOP4EEN (TOP4 external enable permit bit)

12 TOP3EEN (TOP3 external enable permit bit)

13 TOP2EEN (TOP2 external enable permit bit)

14 TOP1EEN (TOP1 external enable permit bit)

15 TOP0EEN (TOP0 external enable permit bit)

Note: This register must always be accessed in halfwords. The TOP0-10 External Enable Permit Register controls enable operation on TOP counters from external de- vices by enabling or disabling it. TOP0-10 Enable Protect Register (TOPPRO) <Address: H’0080 02FC> <Upon exiting reset: H’0000> b Bit Name Function R W 0–4 No function assigned. Fix to "0". 00

5 TOP10PRO (TOP10 enable protect bit) 0: Enable for rewriting R W

6 TOP9PRO (TOP9 enable protect bit) 1: Protect against rewriting

7 TOP8PRO (TOP8 enable protect bit)

8 TOP7PRO (TOP7 enable protect bit)

9 TOP6PRO (TOP6 enable protect bit)

10 TOP5PRO (TOP5 enable protect bit)

11 TOP4PRO (TOP4 enable protect bit)

12 TOP3PRO (TOP3 enable protect bit)

13 TOP2PRO (TOP2 enable protect bit)

14 TOP1PRO (TOP1 enable protect bit)

15 TOP0PRO (TOP0 enable protect bit)

Note: This register must always be accessed in halfwords. The TOP0-10 Enable Protect Register controls rewriting of the TOP0-10 count enable bit by enabling for or protecting it against rewriting. TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 EEN EEN EEN EEN EEN EEN EEN EEN EEN EEN EEN 00000000000 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 00000 TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO 00000000000 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 00000

10-5732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TOP0-10 Count Enable Register (TOPCEN) <Address: H’0080 02FE> <Upon exiting reset: H’0000> b Bit Name Function R W 0–4 No function assigned. Fix to "0". 00

5 TOP10CEN (TOP10 count enable bit) 0: Stop counting R W

6 TOP9CEN (TOP9 count enable bit) 1: Enable counting

7 TOP8CEN (TOP8 count enable bit)

8 TOP7CEN (TOP7 count enable bit)

9 TOP6CEN (TOP6 count enable bit)

10 TOP5CEN (TOP5 count enable bit)

11 TOP4CEN (TOP4 count enable bit)

12 TOP3CEN (TOP3 count enable bit)

13 TOP2CEN (TOP2 count enable bit)

14 TOP1CEN (TOP1 count enable bit)

15 TOP0CEN (TOP0 count enable bit)

Note: This register must always be accessed in halfwords. The TOP0-10 Count Enable Register controls operation of TOP counters. To enable any TOP counter in software, enable its corresponding enable protect bit for write and set the count enable bit by writing "1". To stop any TOP counter, enable its corresponding enable protect bit for write and reset the count enable bit by writing "0". In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable bit is automatically reset to "0". Therefore, the TOP0-10 Count Enable Register when accessed for read serves as a status register indicating whether the counter is operating or idle. WR bn TOPm enable protect (TOPmPRO) WR EN-ON TOPm external enable (TOPmEEN) TINnS TOPm enable (TOPmCEN) TOP enable control Input processing selection F/F F/F F/F Event bus TINn Figure 10.3.6 Configuration of the TOP Enable Circuit b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 00000 TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 CEN CEN CEN CEN CEN CEN CEN CEN CEN CEN CEN 00000000000

10-5832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function)

(1) Outline of TOP single-shot output mode In single-shot output mode, the timer generates a pulse in width of "reload register set value + 1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload register, at the next cycle the counter is loaded with the content of "the reload register -1" and starts counting synchronously with the count clock. The counter counts down and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from "L" to "H" or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of "reload register set value + 1" only once. An interrupt request can be generated when the counter underflows. The count value is "reload register set value + 1." For example, if the initial reload register value is 7, then the count value is 8. Figure 10.3.7 Example of Counting in TOP Single-shot Output Mode 12345678 6 5 4 3 H'FFFF 2 1 (Note 3) Enable Reload register Counter Interrupt request Underflow Count value = 8 Note 1: What actually is seen in the cycle immediately during enable is the previous counter value, and not 7. Note 2: A count clock dependent delay is included before F/F output changes state after the timer is enabled. Note 3: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. F/F output Count clock (Note 2) (Note 1)

10-5932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 In the example below, the reload register is initially set to H’A000. (The initial counter value can be undefined, and does not have to be specific.) When the timer starts, the value that "the reload register -1" is loaded into the counter, letting it start counting. Thereafter, it continues counting down until it underflows after reaching the minimum count. H'FFFF H'0000 H'A000 H'FFFF H'(A000-1) Count clock Correction register Enabled (by writing to the enable bit or by external input) F/F output Disabled (by underflow) (Unused) TOP interrupt request due to underflow Enable bit Starts counting down from the reload register set value Reload register Data inverted by enable Counter Data inverted by underflow Indeterminate value (Note 1) (Note 2) Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled. Note 2: The value that "reload register - 1" is reloaded. Note: This diagram does not show detailed timing information. Figure 10.3.8 Typical Operation in TOP Single-shot Output Mode

10-6032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. (2) Correction function of TOP single-shot output mode To change the counter value while in progress, write to the TOP correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the correction register. The counter is corrected synchronously with a count clock pulse next to one at which the correction value was written to the TOP correction register. If the counter is corrected this way, note that because one down count in that clock period is canceled, the counter value actually is corrected by (correction register value + 1). For example, if the initial counter value is 7 and the value 3 is written to the correction register when the counter has counted down to 3, then the counter counts a total of 12 before it underflows. Figure 10.3.9 Example of Counting in TOP Single-shot Output Mode When Count is Corrected 123456789 1 0 1 1 1 2 6 5 4 3 2 1 0 6 5 4 3 H'FFFF Correction register Underflow Count value = (7 + 1) + (3 + 1) = 12 Count clock dependent delay Enable Reload register Counter Interrupt request Count clock (Note 1) Note 1: What actually is seen in the cycle immediately after enable is the previous counter value, and not 7. Note 2: The value that "reload register - 1" is reloaded. Note: This diagram does not show detailed timing information. Indeterminate value (Note 2) + 3

10-6132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.3.10 Typical Operation in TOP Single-shot Output Mode When Count is Corrected H'(8000 - 1) H'FFFF H'0000 H'8000 H'5000 H'5000 + H'4000 H'8000 H'FFFF H'4000Undefined F/F output TOP interrupt request due to underflow Count clock Correction register Enabled (by writing to the enable bit or by external input) Enable bit Reload register Write to the correction register Undefined value Disabled (by underflow) Counter (Note 1) Note 1: What actually is seen in the cycle immediately after enable is the previous counter value, and not 7. Note 2: The value that "reload register - 1" is reloaded. Note: This diagram does not show detailed timing information. (Note 2) Data inverted by enable Data inverted by underflow In the example below, the reload register is initially set to H’8000. When the timer starts, the value that "the reload register -1" is loaded into the counter, letting it start counting down. In the diagram below, the value H’4000 is written to the correction register when the counter has counted down to H’5000. As a result of this correction, the count has been increased to H’9000, so that the counter counts a total of (H’8000 + 1 + H’4000 + 1) before it stops.

10-6232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (3) Precautions on using TOP single-shot output mode The following describes precautions to be observed when using TOP single-shot output mode. If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops. If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled. If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. Because the timer operates synchronously with the count clock, a count clock-dependent delay is included before starting F/F operation after the timer is enabled. When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. Therefore, if the counter underflows in the subsequent down-count after an overflow, a false interrupt request is generated for an underflow that includes the overflowed count.

10-6332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 H'FFFF H'0000 H'FFF8 H'(FFF0+0014) H'0004 H'FFF0 H'0014 H'FFF8 H'FFFF H'(FFF8-1) Data inverted by enable Data inverted by underflow Counter Count clock Correction register F/F output Enable bit Reload register Write to the correction register Enabled (by writing to the enable bit or by external input) Undefined value Actual count after overflow Overflow occurs Undefined TOP interrupt request due to underflow Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled. Note 2: The value that "reload register - 1" is reloaded. Note: This diagram does not show detailed timing information. (Note 2) (Note 1) Figure 10.3.11 Example of an Operation in TOP Single-shot Output Mode Where Count Overflows Due to Correction In the example below, the reload register is initially set to H’FFF8. When the timer starts, the value that "the reload register -1" is loaded into the counter, letting it start counting down. In the diagram below, the value H’0014 is written to the correction register when the counter has counted down to H’FFF0. As a result of this correction, the count overflows to H’0004 and the counter fails to count correctly. Also, an interrupt request is generated for an erroneous overflowed count.

10-6432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function)

(1) Outline of TOP delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of "reload register set value + 1" after a finite time equal to "counter set value + 1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock. At the cycle after the first time the counter underflows, it is loaded with the value that "the reload register -1" and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of "reload register set value + 1" after a finite time equal to "first set value of counter + 1" only once. An interrupt request can be generated when the counter underflows first time and next. The "counter set value + 1" and "reload register set value + 1" are effective as count values. For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates as shown below. Figure 10.3.12 Example of Counting in TOP Delayed Single-shot Output Mode 123 45 678 9 10 11 4 3 2 1 3 2 1 0 H'FFFFH'FFFF F/F output (Note 1) Count clock dependent delay Enable Reload register Counter Interrupt request Count clock Underflow Underflow Count value = (4 + 1) + (5 + 1) = 11 (Note 2) Note 1: What actually is seen in the cycle immediately during underflow is H'FFFF(underflow value), and not 5. Note 2: The value that "reload register - 1" is reloaded. Note: This diagram does not show detailed timing information.

10-6532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respec- tively. When the timer is enabled, the counter starts counting down at the cycle after it underflows, the counter is loaded with the content of "the reload register -1" and continues counting down. The counter stops when it underflows second time. Figure 10.3.13 Typical Operation in TOP Delayed Single-shot Output Mode H'FFFF H'0000 Underflow (first time) Count down from the counter's set valueH'A000 Underflow (second time) H'F000 Count down from the reload register's set value H'(F000-1) (Unused) H'FFFF H'F000 Data inverted by underflow Data inverted by underflow Count clock Correction register Enabled (by writing to the enable bit or by external input) F/F output TOP interrupt request due to underflow Enable bit Reload register Counter (Note 1) Note 1: The value that "reload register - 1" is reloaded. Note: This diagram does not show detailed timing information.

10-6632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) Correction function of TOP delayed single-shot output mode To change the counter value while in progress, write to the TOP correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is. To subtract, write the 2’s complement of the value to be subtracted to the correction register. The counter is corrected synchronously with a count clock pulse next to one at which the correction value was written to the TOP correction register. If the counter is corrected this way, note that because one down count in that clock period is canceled, the counter value actually is corrected by (correction register value + 1). For example, if the reload register value is 7 and the value 3 is written to the correction register when the counter has counted down to 3 after being reloaded, then the counter counts a total of 12 after being reloaded before it underflows. 6 5 4 3 2 1 0 123456789 1 0 1 1 1 2 6 5 4 3 H'FFFF H'FFFF Enable = "H" (Note 1) Underflow Correction register Reload register Counter Interrupt request Count clock Count value after being reloaded = (7 + 1) + (3 + 1) = 12 (Note 2) Note 1: What actually is seen in the cycle immediately during underflow is H'FFFF(the underflow value), and not 7. Note 2: The value that "reload register - 1" is reloaded. Note: This diagram does not show detailed timing information. Figure 10.3.14 Example of Counting in TOP Delayed Single-shot Output Mode When Count is Corrected When writing to the correction register, be careful not to cause the counter to overflow. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow.

10-6732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.3.15 Typical Operation in TOP Delayed Single-shot Output Mode when Count is Corrected H'FFFF H'0000 H'9000+H'0008 H'F000 H'A000 H'F000 H'(F000+0008+1) H'0008 Write to the correction register H'9000 Data inverted by underflow Data inverted by underflow Correction register F/F output TOP interrupt request due to underflow Enable bit Note 1: The value that "reload register - 1" is reloaded. Note: This diagram does not show detailed timing information. Reload register Counter Count clock Underflow (first time) Underflow (second time) Enabled (by writing to the enable bit or by external input) Undefined (Note 1) In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respec- tively. When the timer is enabled, the counter starts counting down and at the cycle after the first underflow, the counter is loaded with the content of "the reload register -1" and continues counting down. In the dia- gram below, the value H’0008 is written to the correction register when the counter has counted down to H’9000. As a result of this correction, the counter has its count value increased to H’9008 and counts (H’F000 + 1 + H’0008 + 1) after the first underflow before it stops.

10-6832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (3) Precautions on using TOP delayed single-shot output mode The following describes precautions to be observed when using TOP delayed single-shot output mode. If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops. If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled. If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. Even if the counter overflows due to correction of counts, no interrupt requests are generated for reasons of an overflow. Therefore, if the counter underflows in the subsequent down-count after an overflow, a false interrupt request is generated for an underflow that includes the overflowed count. If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF. The reload reads the value that "the reload register -1" into the counter at the timing of the counter clock after the underflow. Figure 10.3.16 Counter Value Immediately after Underflow Count clock Enable bit "H" H'0001 H'0000 H'FFFF H'AAA9 H'AAA8Counter value H'AAAAReload register underflow H'(AAAA-1) H'(AAAA-2) What is seen during underflow cycle is always H'FFFF, and not the reload register value (in this case, H'AAAA). Count down from the reload register value Reload cycle The value that "reload register - 1" is reloaded by count clock next underflow

10-6932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.3.11 Operation in TOP Continuous Output Mode (without Correction Function)

(1) Outline of TOP continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and at the cycle after the counter underflows, it is loaded with the value that "the reload register -1." Thereafter, this opera- tion is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of "reload register set value + 1." When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. At the cycle after this under- flow, the counter to be loaded with the content of "the reload register -1" and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. An interrupt request can be generated each time the counter underflows. The "counter set value + 1" and "reload register set value + 1" are effective as count values. For example, if the initial counter value is 4 and the initial reload register value is 5, then the timer operates as shown below. Figure 10.3.17 Example of Counting in TOP Continuous Output Mode 12345 123456123456 (4) 3 2 1 0 3 2 1 0 4 3 2 1 0 (Note 1) F/F output (Note 2) Interrupt request Underflow Note 1: What actually is seen in the cycle immediately during enable is the previous counter value, and not 4. Note 2: What actually is seen in the cycle immediately during underflow is H'FFFF (underflow value), and not 5. Note 3: The value that "reload register - 1" is reloaded. Note: This diagram does not show detailed timing information. Underflow Underflow (Note 2) (Note 2) Count clock dependent delay Enable Counter Count clock Count value = 5 Count value = 6 Count value = 6 (Note 3) (Note 3) (Note 3 Reload register

10-7032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 In the example below, the counter and the reload register are initially set to H’A000 and H’E000, respec- tively. When the timer is enabled, the counter starts counting down and when it underflows after reaching the minimum count, the counter is loaded with the content of "the reload register -1" and continues counting down. However, the timing for reloading is at the cycle after underflow. H'FFFF H'0000 H'E000 H'A000 H'FFFF H'FFFF Data inverted by underflow Data inverted by underflow Data inverted by enable Count clock Correction register F/F output TOP interrupt request due to underflow Enable bit Reload register Counter Underflow (first time) Underflow (second time) Enabled (by writing to the enable bit or by external input) Count down from the counter's set value Count down from the reload register's set value Count down from the reload register's set value (Unused) (Note 2) Note 1: A count clock dependent delay is included before F/F output changes state after the timer is enabled. Note 2: The value that "reload register - 1" is reloaded. Note: This diagram does not show detailed timing information. (Note 2) (Note 1) Figure 10.3.18 Typical Operation in TOP Continuous Output Mode

10-7132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) Precautions on using TOP continuous output mode The following describes precautions to be observed when using TOP continuous output mode. If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF. The reload reads the value that "the reload register -1" into the counter at the timing of the counter clock after the underflow. Because the timer operates synchronously with the count clock, a count clock-dependent delay is included before F/F output is inverted after the timer is enabled.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-7232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.1 Outline of TIO

TIO (Timer Input/Output) is an input/output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time: <Input modes>

Measure clear input mode Measure free-run input mode Noise processing input mode <Output modes without correction function> PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode The table below shows specifications of TIO. The diagram in the next page shows a block diagram of TIO. Table 10.4.1 Specifications of TIO (Input/Output-Related 16-Bit Timer) Item Specification Number of channels 10 channels Counter 16-bit down-counter Reload register 16-bit reload register Measure register 16-bit capture register Timer startup Started by writing to the enable bit in software or enabled by external input (rising or falling or both edges or "H" or "L" level) Mode switching <Input modes> Measure clear input mode Measure free-run input mode Noise processing input mode <Output modes without correction function> PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode Interrupt request generation Can be generated by a counter underflow DMA transfer request generationCan be generated by a counter underflow (for only the TIO8)

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-7332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.4.1 Block Diagram of TIO (Input/Output-Related 16-Bit Timer) IRQ12 Clock bus Input event bus Output event bus 3 2 1 0 BCLK/2 TCLK1 (P125) clk en/cap udf TIO 0 clk en/cap udfTIO 1 clk en/cap udfTIO 2 clk en/cap udfTIO 3 clk en/cap udfTIO 4 S STIN3STIN3 (P153) S S S S PRS1 PRS0 clk en/cap udfTIO 5STCLK1S S TCLK2 (P126) clk en/cap udfTIO 6STCLK2S S clk en/cap udfTIO 7S S S S clk en/cap udfTIO 8 clk en/cap udfTIO 9S S F/F11 F/F12 F/F13 F/F14 F/F15 S F/F16 F/F17 F/F18 F/F19 S S S S S S S S S TO 11 (P103) TO 12 (P104) TO 13 (P105) TO 14 (P106) TO 15 (P107) IRQ0 IRQ0 IRQ0 IRQ0 IRQ4 TO 16 (P93) TO 17 (P94) TO 18 (P95) TO 19 (P96) TO 20 (P97) IRQ4 IRQ4 IRQ4 DMA0 IRQ3 3 2 1 0 0 1 2 3 0 1 2 33 2 1 0 3 2 1 0 PRS2 Reload 0/measure register Down-counter Reload 1 register (Note 1) (16-bit) IRQ3 F/F20 S : SelectorF/F : Flip-flopPRS0–2 : Prescaler Note 1: The reload 1 register is used in only PWM output mode.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-7432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.2 Outline of Each Mode of TIO

Each mode of TIO is outlined below. For each TIO channel, only one of the following modes can be selected. (1) Measure clear/free-run input modes In measure clear/free-run input modes, the timer is used to measure a duration of time from when the counter starts counting till when an external capture signal is entered. And also it is possible to generate both an interrupt requested by underflow at the counter or execution of measurement operation and a DMA transfer request (for only the TIO8) upon underflow of the counter. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchro- nously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written into a register called the “measure register.” In measure clear input mode, the counter value is initialized to H’FFFF upon capture, from which the counter starts counting down again. The counter returns to H'FFFF upon underflow, from which it starts counting down. Furthermore, when it underflows goes back to H'FFFF and continues down counting. In measure free-run input mode, the counter continues counting down even after capture. The counter returns to H’FFFF upon underflow, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. (2) Noise processing input mode In noise processing input mode, the timer is used to detect that the input signal remained in the same state for over a predetermined time. In noise processing input mode, a "H" or "L" level on external input activates the counter and if the input signal remains in the same state for over a predetermined time before the counter underflows, the counter generates an interrupt request before stopping. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and at the next cycle when a valid- level signal is entered again, the counter is reloaded with the value that "the reload register -1" and restarts counting. The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8) upon underflow of the counter. (3) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the value that "the reload 0 register -1" and starts counting down synchronously with the count clock at the next cycle. The next cycle after the first time the counter underflows, it is loaded with the value that "the reload 1 register -1" and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The effective counter value is "reload 0 register set value +1" or "reload 1 register set value +1." The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted when the counter starts counting and each time it underflows.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-7532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Furthermore, it is possible to generate an interrupt request at even-numbered occurrences of underflow after the counter is enabled and a DMA transfer request (for only the TIO8) every time the counter underflows. In addition, PWM output mode of TIO does not have function of correction. (4) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of "reload 0 register set value + 1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload 0 register, the counter is loaded with the value that "the reload 0 register -1" and starts counting synchronously with the count clock at the next cycle. The counter counts down and when the minimum count is reached, stops upon underflow. The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of "reload 0 register set value + 1" only once. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TI08) upon underflow of the counter. (5) Delayed single-shot output mode (without correction function) In delayed single-shot output mode, the timer generates a pulse in width of "reload 0 register set value + 1" after a finite time equal to "counter set value + 1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock. The next cycle after the first time the counter underflows, it is loaded with the value that "the reload 0 register -1" and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first time and next, generating a single-shot pulse waveform in width of "reload 0 register set value + 1" after a finite time equal to "first set value of counter + 1" only once. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TI08) upon the first and next underflows of the counter. (6) Continuous output mode (without correction function) In continuous output mode, the timer counts down starting from the set value of the counter and the next cycle after the counter underflows, it is loaded with the value that "the reload 0 register -1." Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses in width of "reload 0 register set value + 1." When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be loaded with the content of the reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The timing for reloading to counter is the cycle after underflow. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TI08) each time the counter underflows.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-7632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 <Count clock-dependent delay> Because the timer operates synchronously with the count clock, there is a count clock-dependent delay from when the timer is enabled till when it actually starts operating. In operation mode where the F/F output is inverted when the timer is enabled, the F/F output is inverted synchronously with the count clock. BCLK Count clock Enable F/F operation (Note 1) Count clock period Count clock-dependent delay Write to the enable bit Note 1: This applies to the case where F/F output is inverted when the timer is enabled. Inverted Figure 10.4.2 Count Clock Dependent Delay

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-7732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.3 TIO Related Register Map

Shown below is a TIO related register map. TIO Related Register Map (1/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0300 TIO0 Counter 10-87 (TIO0CT) H'0080 0302 (Use inhibited area) H'0080 0304 TIO0 Reload 1 Register 10-89 (TIO0RL1) H'0080 0306 TIO0 Reload 0/Measure Register 10-88 (TIO0RL0) (Use inhibited area) H'0080 0310 TIO1 Counter 10-87 (TIO1CT) H'0080 0312 (Use inhibited area) H'0080 0314 TIO1 Reload 1 Register 10-89 (TIO1RL1) H'0080 0316 TIO1 Reload 0/Measure Register 10-88 (TIO1RL0) H'0080 0318 (Use inhibited area) H'0080 031A TIO0–3 Control Register 0 10-80 (TIO03CR0) H'0080 031C (Use inhibited area) TIO0–3 Control Register 1 10-81 (TIO03CR1) H'0080 031E (Use inhibited area) H'0080 0320 TIO2 Counter 10-87 (TIO2CT) H'0080 0322 (Use inhibited area) H'0080 0324 TIO2 Reload 1 Register 10-89 (TIO2RL1) H'0080 0326 TIO2 Reload 0/Measure Register 10-88 (TIO2RL0) (Use inhibited area) H'0080 0330 TIO3 Counter 10-87 (TIO3CT) H'0080 0332 (Use inhibited area) H'0080 0334 TIO3 Reload 1 Register 10-89 (TIO3RL1) H'0080 0336 TIO3 Reload 0/Measure Register 10-88 (TIO3RL0) (Use inhibited area) H'0080 0340 TIO4 Counter 10-87 (TIO4CT) H'0080 0342 (Use inhibited area) H'0080 0344 TIO4 Reload 1 Register 10-89 (TIO4RL1) H'0080 0346 TIO4 Reload 0/Measure Register 10-88 (TIO4RL0) H'0080 0348 (Use inhibited area) H'0080 034A TIO4 Control Register TIO5 Control Register 10-82 (TIO4CR) (TIO5CR) 10-84 (Use inhibited area) H'0080 0350 TIO5 Counter 10-87 (TIO5CT) H'0080 0352 (Use inhibited area)

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-7832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIO Related Register Map (2/2) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 0354 TIO5 Reload 1 Register 10-89 (TIO5RL1) H'0080 0356 TIO5 Reload 0/Measure Register 10-88 (TIO5RL0) (Use inhibited area) H'0080 0360 TIO6 Counter 10-87 (TIO6CT) H'0080 0362 (Use inhibited area) H'0080 0364 TIO6 Reload 1 Register 10-89 (TIO6RL1) H'0080 0366 TIO6 Reload 0/Measure Register 10-88 (TIO6RL0) H'0080 0368 (Use inhibited area) H'0080 036A TIO6 Control Register TIO7 Control Register 10-85 (TIO6CR) (TIO7CR) 10-86 (Use inhibited area) H'0080 0370 TIO7 Counter 10-87 (TIO7CT) H'0080 0372 (Use inhibited area) H'0080 0374 TIO7 Reload 1 Register 10-89 (TIO7RL1) H'0080 0376 TIO7 Reload 0/Measure Register 10-88 (TIO7RL0) (Use inhibited area) H'0080 0380 TIO8 Counter 10-87 (TIO8CT) H'0080 0382 (Use inhibited area) H'0080 0384 TIO8 Reload 1 Register 10-89 (TIO8RL1) H'0080 0386 TIO8 Reload 0/Measure Register 10-88 (TIO8RL0) H'0080 0388 (Use inhibited area) H'0080 038A TIO8 Control Register TIO9 Control Register 10-86 (TIO8CR) (TIO9CR) 10-87 (Use inhibited area) H'0080 0390 TIO9 Counter 10-87 (TIO9CT) H'0080 0392 (Use inhibited area) H'0080 0394 TIO9 Reload 1 Register 10-89 (TIO9RL1) H'0080 0396 TIO9 Reload 0/Measure Register 10-88 (TIO9RL0) (Use inhibited area) H'0080 03BC TIO0-9 Enable Protect Register 10-90 (TIOPRO) H'0080 03BE TIO0-9 Count Enable Register 10-91 (TIOCEN)

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-7932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.4 TIO Control Registers

The TIO control registers are used to select operation modes of TIO0–9 (measure input, noise processing input, PWM output, single-shot output, delayed single-shot output or continuous output mode), as well as select the count enable and count clock sources. Following TIO control registers are provided for each timer group. TIO0–3 Control Register 0 (TIO03CR0) TIO0–3 Control Register 1 (TIO03CR1) TIO4 Control Register (TIO4CR) TIO5 Control Register (TIO5CR) TIO6 Control Register (TIO6CR) TIO7 Control Register (TIO7CR) TIO8 Control Register (TIO8CR) TIO9 Control Register (TIO9CR)

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-8032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIO0–3 Control Register 0 (TIO03CR0) <Address: H’0080 031A> <Upon exiting reset: H’0000> b Bit Name Function R W

0 TIO3EEN (Note 1) 0: Disable external input R W

TIO3 external input enable bit 1: Enable external input 1–3 TIO3M 000: Single-shot output mode R W TIO3 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode

4 TIO2ENS (Reserved bit) Fix to "0" 0 0

5–7 TIO2M 000: Single-shot output mode R W TIO2 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Use inhibited 111: Use inhibited

8 TIO1ENS (Reserved bit) Fix to "0" 0 0

9–11 TIO1M 000: Single-shot output mode R W TIO1 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Use inhibited 111: Use inhibited

12 TIO0ENS 0: Does not use enable/measure input source R W

TIO0 enable/measure input source select bit 1: External input TIN3 13–15 TIO0M 000: Single-shot output mode R W TIO0 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note 1: During measure free-run/clear input mode, even if this bit is set to "0" (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written into the measure register. In measure clear input mode, however, if this bit = "0" (external input disabled), the counter value is not initialized (H’FFFF) upon capture and, therefore, this bit should be set to "1" (external input enabled). Notes: This register must always be accessed in halfwords. Operation mode can only be set or changed while the counter is inactive. To select TIO3 enable/measure input sources, use the TIO4 Control Register TIO34ENS (TIO3, TIO4 enable/measure input source select) bits. TIO1 and TIO2 do not have the capture function during measure free-run/clear input mode. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO3M TIO2M TIO1M TIO0M 000 000 000 000 TIO3 TIO2 TIO1 TIO0 EEN ENS ENS ENS 0000

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-8132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIO0–3 Control Register 1 (TIO03CR1) <Address: H’0080 031D> <Upon exiting reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0". 00 14, 15 TIO03CKS 00: Clock bus 0 R W TIO0–3 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 Figure 10.4.3 Outline Diagram of TIO0–4 Clock and Enable Inputs Clock bus Input event bus 3 2 1 0 clk en/cap TIO 0 clk en/cap TIO 1 clk en/cap TIO 2 clk en/cap TIO 3 clk en/cap TIO 4 S STIN3STIN3 (P153) S S S S S : Selector 3 2 1 0 3 2 1 0 3 2 1 0 Note: This diagram only illustrates TIO control registers and is partly omitted. b 8 9 1 01 11 21 31 4 b 1 5 TIO03CKS 00000000

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-8232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIO4 Control Register (TIO4CR) <Address: H’0080 034A> <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 TIO4CKS 00: Clock bus 0 R W TIO4 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3

2 TIO4EEN (Note 1) 0: Disable external input R W

TIO4 external input enable bit 1: Enable external input 3, 4 TIO34ENS 00: Does not use enable/measure input source R W TIO3,4 enable/measure input source select bit 01: Does not use enable/measure input source 10: Input event bus 2 11: Input event bus 3 5–7 TIO4M 000: Single-shot output mode R W TIO4 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note 1: During measure free-run/clear input mode, even if this bit is set to "0" (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written into the measure register. In measure clear input mode, however, if this bit = "0" (external input disabled), the counter value is not initialized (H’FFFF) upon capture and, therefore, this bit should be set to "1" (external input enabled). Note: Operation mode can only be set or changed while the counter is inactive. b 0 123456 b 7 TIO4CKS TIO4EEN TIO34ENS TIO4M 00000000

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-8332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 clk en/capS TCLK2S S Clock bus Input event bus 3 2 1 0 TCLK1 (P125) clk en/cap TIO 5S TCLK1S S TCLK2 (P126) TIO 6 clk en/cap TIO 7S S S S clk en/cap TIO 8 clk en/cap TIO 9S S S : Selector 3 2 1 0 3 2 1 0 3 2 1 0 Note: This diagram only illustrates TIO control registers and is partly omitted. Figure 10.4.4 Outline Diagram of TIO5–9 Clock and Enable Inputs

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-8432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIO5 Control Register (TIO5CR) <Address: H’0080 034B> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 TIO5CKS 000: External input TCLK1 R W TIO5 clock source select bit 001: External input TCLK1 010: External input TCLK1 011: External input TCLK1 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 11, 12 TIO5ENS 00: Does not use enable/measure input source R W TIO5 enable/measure input source select bit 01: Does not use enable/measure input source 10: Does not use enable/measure input source 11: Input event bus 3 13–15 TIO5M 000: Single-shot output mode R W TIO5 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note: Operation mode can only be set or changed while the counter is inactive. b 8 9 1 01 11 21 31 4 b 1 5 TIO5CKS TIO5ENS TIO5M 00000000

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-8532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIO6 Control Register (TIO6CR) <Address: H’0080 036A> <Upon exiting reset: H’00> b Bit Name Function R W 0–2 TIO6CKS 000: External input TCLK2 R W TIO6 clock source select bit 001: External input TCLK2 010: External input TCLK2 011: External input TCLK2 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 3, 4 TIO6ENS 00: Does not use enable/measure input source R W TIO6 enable/measure input source select bit 01: Does not use enable/measure input source 10: Input event bus 2 11: Input event bus 3 5–7 TIO6M 000: Single-shot output mode R W TIO6 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note: Operation mode can only be set or changed while the counter is inactive. b 0 123456 b 7 TIO6CKS TIO6ENS TIO6M 00000000

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-8632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TIO7 Control Register (TIO7CR) <Address: H’0080 036B> <Upon exiting reset: H’00> b Bit Name Function R W 8 No function assigned. Fix to "0". 00 9, 10 TIO7CKS 00: Clock bus 0 R W TIO7 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11, 12 TIO7ENS 00: Does not use enable/measure input source R W TIO7 enable/measure input source select bit 01: Does not use enable/measure input source 10: Input event bus 0 11: Input event bus 3 13–15 TIO7M 000: Single-shot output mode R W TIO7 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note: Operation mode can only be set or changed while the counter is inactive. TIO8 Control Register (TIO8CR) <Address: H’0080 038A> <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 TIO8CKS 00: Clock bus 0 R W TIO8 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 2–4 TIO8ENS 000: Does not use enable/measure input source R W TIO8 enable/measure input source select bit 001: Does not use enable/measure input source 010: Does not use enable/measure input source 011: Does not use enable/measure input source 100: Does not use enable/measure input source 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 5–7 TIO8M 000: Single-shot output mode R W TIO8 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note: Operation mode can only be set or changed while the counter is inactive. b 8 9 1 01 11 21 31 4 b 1 5 TIO7CKS TIO7ENS TIO7M 00000000 b 0 123456 b 7 TIO8CKS TIO8ENS TIO8M 00000000

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-8732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.5 TIO Counters (TIO0CT–TIO9CT)

TIO0 Counter (TIO0CT) <Address: H’0080 0300> TIO1 Counter (TIO1CT) <Address: H’0080 0310> TIO2 Counter (TIO2CT) <Address: H’0080 0320> TIO3 Counter (TIO3CT) <Address: H’0080 0330> TIO4 Counter (TIO4CT) <Address: H’0080 0340> TIO5 Counter (TIO5CT) <Address: H’0080 0350> TIO6 Counter (TIO6CT) <Address: H’0080 0360> TIO7 Counter (TIO7CT) <Address: H’0080 0370> TIO8 Counter (TIO8CT) <Address: H’0080 0380> TIO9 Counter (TIO9CT) <Address: H’0080 0390> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TIO0CT–TIO9CT 16-bit counter value R(Note 1) Note 1: Protected against write during PWM output mode. Note: These registers must always be accessed in halfwords. The TIO counter is a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by external input), the counter starts counting synchronously with the count clock. These counters are protected against write during PWM output mode. TIO9 Control Register (TIO9CR) <Address: H’0080 038B> <Upon exiting reset: H’00> b Bit Name Function R W 8 No function assigned. Fix to "0". 0– 9, 10 TIO9CKS 00: Clock bus 0 R W TIO9 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11, 12 TIO9ENS 00: Does not use enable/measure input source R W TIO9 enable/measure input source select bit 01: Does not use enable/measure input source 10: Input event bus 1 11: Input event bus 3 13–15 TIO9M 000: Single-shot output mode R W TIO9 operation mode select bit 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 110: Noise processing input mode 111: Noise processing input mode Note: Operation mode can only be set or changed while the counter is inactive. b 8 9 1 01 11 21 31 4 b 1 5 TIO9CKS TIO9ENS TIO9M 00000000 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO0CT-TIO9CT

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-8832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0)

TIO0 Reload 0/ Measure Register (TIO0RL0) <Address: H’0080 0306> TIO1 Reload 0/ Measure Register (TIO1RL0) <Address: H’0080 0316> TIO2 Reload 0/ Measure Register (TIO2RL0) <Address: H’0080 0326> TIO3 Reload 0/ Measure Register (TIO3RL0) <Address: H’0080 0336> TIO4 Reload 0/ Measure Register (TIO4RL0) <Address: H’0080 0346> TIO5 Reload 0/ Measure Register (TIO5RL0) <Address: H’0080 0356> TIO6 Reload 0/ Measure Register (TIO6RL0) <Address: H’0080 0366> TIO7 Reload 0/ Measure Register (TIO7RL0) <Address: H’0080 0376> TIO8 Reload 0/ Measure Register (TIO8RL0) <Address: H’0080 0386> TIO9 Reload 0/ Measure Register (TIO9RL0) <Address: H’0080 0396> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TIO0RL0–TIO9RL0 16-bit reload register value R(Note 1) Note 1: These registers are protected against write during measure input mode. Note: These registers must always be accessed in halfwords. The TIO Reload 0/ Measure Registers serve dual purposes as a register for reloading data into the TIO Counter Registers (TIO0CT–TIO9CT) and as a measure register during measure input mode. These registers are protected against write during measure input mode. The content of "the reload 0 register -1" is loaded into the counter synchronously with the count clock at the following timing: At the next cycle when after the counter started counting in noise processing input mode, the input signal is inverted and a valid-level signal is entered again before the counter underflows At the next cycle when the counter is enabled in single-shot output mode At the next cycle when the counter underflowed in delayed single-shot output or continuous output mode At the next cycle when the counter is enabled in PWM output mode and when the counter value set by the reload 1 register underflowed Simply because data is written to the reload 0 register does not mean that the data is loaded into the counter. If this register is used as a measure register, the counter value is latched into that measure register by event input. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO0RL0-TIO9RL0

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-8932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1)

TIO0 Reload 1 Register (TIO0RL1) <Address: H’0080 0304> TIO1 Reload 1 Register (TIO1RL1) <Address: H’0080 0314> TIO2 Reload 1 Register (TIO2RL1) <Address: H’0080 0324> TIO3 Reload 1 Register (TIO3RL1) <Address: H’0080 0334> TIO4 Reload 1 Register (TIO4RL1) <Address: H’0080 0344> TIO5 Reload 1 Register (TIO5RL1) <Address: H’0080 0354> TIO6 Reload 1 Register (TIO6RL1) <Address: H’0080 0364> TIO7 Reload 1 Register (TIO7RL1) <Address: H’0080 0374> TIO8 Reload 1 Register (TIO8RL1) <Address: H’0080 0384> TIO9 Reload 1 Register (TIO9RL1) <Address: H’0080 0394> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TIO0RL1–TIO9RL1 16-bit reload register value R W Note: These registers must always be accessed in halfwords. The TIO Reload 1 Registers are used to reload data into the TIO Counter Registers (TIO0CT–TIO9CT). The content of "the reload 1 register -1" is loaded into the counter counting synchronously with the count clock at the following timing: At the next cycle when the count value set by the reload 0 register underflowed in PWM output mode Simply because data is written to the reload 1 register does not mean that the data is loaded into the counter. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TIO0RL1-TIO9RL1

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-9032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.8 TIO Enable Control Registers

TIO0-9 Enable Protect Register (TIOPRO) <Address: H’0080 03BC> <Upon exiting reset: H’0000> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00

6 TIO9PRO (TIO9 enable protect bit) 0: Enable rewrite R W

7 TIO8PRO (TIO8 enable protect bit) 1: Disable rewrite

8 TIO7PRO (TIO7 enable protect bit)

9 TIO6PRO (TIO6 enable protect bit)

10 TIO5PRO (TIO5 enable protect bit)

11 TIO4PRO (TIO4 enable protect bit)

12 TIO3PRO (TIO3 enable protect bit)

13 TIO2PRO (TIO2 enable protect bit)

14 TIO1PRO (TIO1 enable protect bit)

15 TIO0PRO (TIO0 enable protect bit)

Note: This register must always be accessed in halfwords. The TIO0-9 Enable Protect Register controls rewriting of the TIO count enable bit described in the next page by enabling or disabling it. TIO9 TIO8 TIO7 TIO6 TIO5 TIO4 TIO3 TIO2 TIO1 TIO0 PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO 0000000000 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 000000

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-9132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 WR bn TIOm enable protect (TIOmPRO) WR EN-ON TIOm external enable (TIOmEEN or TIOmENS) TINnS TIOm enable (TIOmCEN) TIO enable control Input processing selection F/F F/F F/F Event bus TINn Figure 10.4.5 Configuration of the TIO Enable Circuit TIO0-9 Count Enable Register (TIOCEN) <Address: H’0080 03BE> <Upon exiting reset: H’0000> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00

6 TIO9CEN (TIO9 count enable bit) 0: Stop count R W

7 TIO8CEN (TIO8 count enable bit) 1: Enable count

8 TIO7CEN (TIO7 count enable bit)

9 TIO6CEN (TIO6 count enable bit)

10 TIO5CEN (TIO5 count enable bit)

11 TIO4CEN (TIO4 count enable bit)

12 TIO3CEN (TIO3 count enable bit)

13 TIO2CEN (TIO2 count enable bit)

14 TIO1CEN (TIO1 count enable bit)

15 TIO0CEN (TIO0 count enable bit)

Note: This register must always be accessed in halfwords The TIO0-9 Count Enable Register controls operation of the TIO counters. To enable any TIO counter in software, enable its corresponding enable protect bit for write and set the count enable bit by writing "1". To stop any TIO counter, enable its corresponding enable protect bit for write and reset the count enable bit by writing "0". In all but continuous output mode, when the counter stops due to occurrence of an underflow, the count enable bit is automatically reset to "0". Therefore, the TIO0-9 Count Enable Register when accessed for read serves as a status register indicating whether the counter is operating or idle. TIO9 TIO8 TIO7 TIO6 TIO5 TIO4 TIO3 TIO2 TIO1 TIO0 CEN CEN CEN CEN CEN CEN CEN CEN CEN CEN 0000000000 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 0 00000

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-9232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.9 Operation in TIO Measure Free-Run/Clear Input Modes

(1) Outline of TIO measure free-run/clear input modes In measure free-run/clear input modes, the timer is used to measure a duration of time from when the counter starts counting till when an external capture signal is entered. It is possible to generate an interrupt request upon underflow of the counter or execution of measurement operation and a DMA transfer request (for only the TIO8) upon underflow of the counter. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchro- nously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written into a register called the “measure register.” In measure clear input mode, the counter value is initialized to H’FFFF upon capture, from which the counter starts counting down again. The counter returns to H'FFFF upon underflow, from which starts counting down. In measure free-run input mode, the counter continues counting down even after capture. The counter returns to H’FFFF upon underflow, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. Figure 10.4.6 Typical Operation in Measure Free-Run Input Mode Count clock Counter H'FFFF H'0000 Enabled (by writing to the enable bit) TIO interrupt request Measure event (capture) occurs Enable bit Note: This diagram does not show detailed timing information. Measure register TIN interrupt request due to external event input H'7000 H'9000 Measure event (capture) TIN interrupt request due to external event input TIN interrupt request Undefined value TIO interrupt request due to underflow H'7000Undefined H'9000 TIO8 DMA transfer request TIO8 DMA transfer request due to underflow

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-9332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) Precautions on using TIO measure free-run/clear input modes The following describes precautions to be observed when using TIO measure free-run/clear input modes. If measure event input and write to the counter occur in the same clock period, the write value is set in the counter while at the same time latched into the measure register. Figure 10.4.7 Typical Operation in Measure Clear Input Mode H'FFFF H'0000 H'7000 H'7000 Enabled (by writing to the enable bit) Measure event (capture) occurs Count clock Counter TIO interrupt request Enable bit Note: This diagram does not show detailed timing information. Measure register TIN interrupt request Undefined value TIN interrupt request due to external event input Undefined TIO8 DMA transfer request TIO8 DMA transfer request due to underflow TIO interrupt request due to underflow

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-9432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.10 Operation in TIO Noise Processing Input Mode

In noise processing input mode, the timer is used to detect that the input signal remained in the same state for over a predetermined time. In noise processing input mode, a "H" or "L" level on external input activates the counter and if the input signal remains in the same state for over a predetermined time before the counter underflows, the counter generates an interrupt request before stopping. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and at the next cycle after a valid-level signal is entered again, the counter is reloaded with the value that "reload register -1" and restarts counting, synchro- nously with the count clock. The effective count width is "reload 0 register set value + 1." The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TI08) upon underflow of the counter. Figure 10.4.8 Typical Operation in Noise Processing Input Mode H'FFFF H'0000 H'A000 H'A000 DMA transfer request (Note 1) Note 1: Only TIO8 can be generated. Note 2: The value that "reload register - 1" is reloaded. Note: • This diagram does not show detailed timing information. DMA transfer request due to underflow Reload 0 register External input (noise processing) Effective signal width Invalid Disabled by underflow Count clock Counter Enabled (by writing to the enable bit) TIO interrupt request Enable bit Invalid TIO interrupt request due to underflow Undefined value (Note 2) (Note 2) (Note 2)

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-9532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 H'FFFF H'0000 H'A000 (Note 3) (Note 2) H'C000 H'A000 H'C000 H'A000(Note 2) Count clock Enabled (by writing to the enable bit or by external input) Underflow (first time) Enable bit Reload 0 register Count down from the reload 1 register set value Reload 1 register Reload 1 buffer Count down from the reload 0 register set value DMA transfer request (Note 1) Note 1: Only TIO8 can be generated. Note 2: The value that "reload 0 register - 1" is reloaded. Note 3: The value that "reload 1 buffer - 1" is reloaded. Note 4: When reload0 is reloaded after updating reload0 register, reload 1 buffer is tranferd. Note 5: Updating of reload 0 and reload 1 during timer operation does not effect PWM waveform that is outputting at present. Updating is reflected at the next PWM period after updating reload 0 register. Note: This diagram does not show detailed timing information. DMA transfer request due to underflow TIO interrupt request DMA transfer request due to underflow TIO interrupt request due to even-numbered occurrences of underflow Undefined value Underflow (second time) Count down from the reload 0 register set value H'A000 H'C000 H'A000 Counter PWM output period (Note 4) (Note 4) F/F output (Note 5) Data inverted by enable Data inverted by underflow Data inverted by underflow Figure 10.4.9 Typical Operation in PWM Output Mode

10.4.11 Operation in TIO PWM Output Mode

(1) Outline of TIO PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the value that "the reload 0 register -1" and starts counting down synchronously with the count clock at the next cycle. At the cycle after the first time the counter underflows, it is loaded with the value that "the reload 1 register -1" and continues counting. Thereafter, the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The "reload 0 register set value +1" and "reload 1 register set value +1" respectively are effective as count values. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter starts counting and each time it underflows. Furthermore, it is possible to generate an interrupt request at even-numbered occurrences of underflow after the counter is enabled and a DMA transfer request (for only the TI08) every time the counter underflows. Note that TIO’s PWM output mode does not have the count correction function.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-9632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 To rewrite the reload 0 and reload 1 registers while the timer is operating, rewrite the reload 1 register first and then the reload 0 register. That way, the reload 0 and reload 1 registers both are updated synchro- nously with PWM period, from which the timer starts operating. This operation can normally be performed collectively by accessing 32-bit addresses beginning with the reload 1 register address wordwise. (Data are automatically written to the reload 1 and then the reload 0 registers in succession.) Note also that if the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have been written to the respective registers, and not the reload values being actually used. When altering PWM period by rewriting the reload registers, if the PWM period terminates before the CPU finishes writing to reload 0, the PWM period is not altered in the current session and the data written to the register is reflected in the next period. When operating in the PWM output mode, writing the reload 0 register and reloard 1 register more than twice within the PWM period and meet the following conditions at the same time, the PWM waveform is output with the value that the last time written reload 0 register and finally written reload 1 register. Condition 1: Start writing reload 0 register after latching the reload 0 register PWM period of the old PWM output period. Condition 2: Rewrite reload 1 register before latching PWM period of the new PWM output period and start writing reload 0 register after latching PWM period. (2) Reload register updates in TIO PWM output mode In PWM output mode, when the timer remains idle, the reload 0 and reload 1 registers are updated at the same time data are written to the respective registers. But when the timer is operating, the reload 1 register is updated at the reloading the updated reload 0 register by updating the reload 0 register. However, if the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have been written to the respective registers. F/F TO TIOnRL0 TIOnRL1 Internal bus Reload 1 Reload 1 WR Reload 0 WR Reload 1 Buffer 16-bit counterPrescaler output Reload 0 PWM mode control Note1. It is transferd from reload 1 register to reload 1 buffer when reload 0 register is reloaded after updating reload 0 register during counter operation. (Note1) Figure 10.4.10 PWM Circuit Diagram

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-9732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 To update PWM period correctly, take either one of the following measures. Identify the completion timing of PWM period by reading counter value at writing reload 1 register and reload 0 register, and then start writing reload 1 register and reload 0 register without crossing PWM period. When writing to reload 1 register and reload 0 register by using interruption, set the prescaler value of counter as small as possible. By doing this, write to reload 1 register and reload 0 register later than the counter to be H'FFFF in the PWM period. Writing reload 1 register and reload 0 register is performed under the period, less than one time per PWM period. (Extend the reload register's rewrite period against PWM period.) (3) Precautions on using TIO PWM output mode The following describes precautions to be observed when using TIO PWM output mode. If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF but changes to "reload value – 1" at the next clock timing. Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated before F/F output is inverted after writing to the enable bit. Figure 10.4.11 Update timing of PWM period Count clock Counter H'FFFF H'0000 F/F output Underflow (1st time) Reload 0 register (Note 2) (Note 1) Reload 1 register PWM period (Note 1) Note 1. The value that "the reload 0 register -1" is reloaded. Note 2. The value that "the reload 1 buffer -1" is reloaded. Notes . : Indicate sampling points. . This diagram does not show detailed timing information. Reload 1 buffer Condition 1 Old PWM output period Condition 2 New PWM putput period Reloading "reload 0 register" (Loading PWM period) Reloading "reload 0 register" (Loading PWM period) Underflow (2nd time) Underflow (2nd time)

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-9832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.4.12 Reload 0 and Reload 1 Register Updates in PWM Output Mode (a) When reload register updates take effect in the current period (reflected in the next period) Count clock H'FFFF H'7FFF H'8000 Timing at which reload 0 is updated Operation by new reload value written Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (Reload 1 data latched) H'1000 H'2000 H'8000 H'9000 Timing at which PWM period latched and reload 1 buffer is updated. Reload 0 register Reload 1 register Counter Interrupt due to underflow F/F output Reload 1 buffer H'9000 H'1000 H'8000 H'9000 H'0001 H'FFFF H'1000 H'7FFF H'2000 H'8000 H'9000 H'7FFEH'0000 H'2000 H'9000 New PWM output period Old PWM output period Enlarged view New PWM output period Note: This diagram does not show detailed timing information. H'1000 H'0FFF H'2000 H'8000 H'9000 (b) When reload register updates take effect in the next period (reflected one period later) Operation by old reload value H'1000 H'2000 H'8000 H'9000 H'0FFE H'2000 H'9000 Write to reload 1 Write to reload 0 (Reload 1 data latched) Timing at which reload 0 is updated PWM period latched Count clock Reload 0 register Reload 1 register Counter Interrupt due to underflow Reload 0 register Reload 1 register F/F output F/F output Reload 1 buffer H'1000 H'2000 H'9000 H'0001 H'FFFF H'1000 H'0FFF H'8000 H'9000 H'0FFEH'0000 H'2000 Old PWM output period Old PWM output period Old PWM output period Enlarged view

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-9932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function)

(1) Outline of TIO single-shot output mode In single-shot output mode, the timer generates a pulse in width of "reload 0 register set value + 1" only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload 0 register, the counter is loaded with the content of "the reload 0 register -1" and starts counting synchronously with the count clock at the next cycle. The counter counts down and when the minimum count is reached, stops upon underflow. The F/F output waveform in single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of "reload 0 register set value + 1" only once. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TI08) upon underflow of the counter. The count value is "reload 0 register set value + 1." (For counting operation, see also Section 10.3.9, “Operation of TOP Single-shot Output Mode.”) (2) Precautions on using TIO single-shot output mode The following describes precautions to be observed when using TIO single-shot output mode. If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops. If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled. If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated before F/F output is inverted after writing to the enable bit.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-10032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 H'FFFF H'0000 H'A000 H'A000 (Note 2) DMA transfer request (Note 1) DMA transfer request due to underflow Count clock Enabled (by writing to the enable bit or by external input) F/F output Disabled (by underflow) (Unused) TIO interrupt request Enable bit Reload 0 register Counter Reload 1 register Undefined value Data inverted by enable Data inverted by underflow TIO interrupt request due to underflow Note 1: Only TIO8 can be generated. Note 2: The value that "reload 0 register - 1" is reloaded. Note: This diagram does not show detailed timing information. Figure 10.4.13 Typical Operation in TIO Single-shot Output Mode (without Correction Function)

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-10132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function)

(1) Outline of TIO delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of "reload 0 register set value + 1" after a finite time equal to (counter set value + 1) only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock. At the cycle after the first time the counter underflows, it is loaded with the value that "the reload 0 register -1" and continues counting down. The counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from "L" to "H" or vice versa) when the counter underflows first time and next, generating a single-shot pulse wave- form in width of "reload 0 register set value + 1" after a finite time equal to "first set value of counter + 1" only once. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TI08) upon the first and next underflows of the counter. The "counter set value + 1" and "reload 0 register set value + 1" are effective as count values. (For counting operation, see also Section 10.3.10, “Operation of TOP Delayed Single-shot Output Mode.”) (2) Precautions on using TIO delayed single-shot output mode The following describes precautions to be observed when using TIO delayed single-shot output mode. If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops. If the counter stops due to an underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority so that count is enabled. If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF. The reload reads the value that "the reload register -1" into the counter at the timing of the counter clock after the underflow.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-10232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 H'FFFF H'0000 H'A000 H'F000 H'F000 DMA transfer request due to underflow DMA transfer request due to underflow TIO interrupt request due to underflow TIO interrupt request due to underflow DMA transfer request (Note 1) Underflow (first time) Count down from the counter set value Underflow (second time) Count down from the reload 0 register set value Count clock F/F output (Unused) TIO interrupt request Enable bit Reload 0 register Counter Reload 1 register Enabled (by writing to the enable bit or by external input) Data inverted by underflow Data inverted by underflow (Note 2) Note 1: Only TIO8 can be generated. Note 2: The value that "reload 0 register - 1" is reloaded. Note: This diagram does not show detailed timing information. Figure 10.4.14 Typical Operation in TIO Delayed Single-shot Output Mode (without Correction Function)

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-10332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.4.14 Operation in TIO Continuous Output Mode (without Correction Function)

(1) Outline of TIO continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and the next cycle when the counter underflows, it is loaded with the value that "the reload 0 register -1." Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose wave- form is inverted in width of "reload 0 register set value + 1." When the timer is enabled (by writing to the enable bit in software or by external input) after setting the counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the count clock and when the minimum count is reached, generates an underflow. The cycle after this under- flow causes the counter to be loaded with the content of "the reload 0 register -1" and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The timing for reloading to counter is the cycle after underflow. The F/F output waveform in continuous output mode is inverted (F/F output level changes from "L" to "H" or vice versa) at startup and upon underflow, generating a waveform of consecutive pulses until the timer stops counting. Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TI08) each time the counter underflows. The "counter set value + 1" and "reload 0 register set value + 1" are effective as count values. (For counting operation, see also Section 10.3.11, “Operation of TOP Continuous Output Mode.”) (2) Precautions on using TIO continuous output mode The following describes precautions to be observed when using TIO continuous output mode. If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled. If the counter is accessed for read at the cycle of underflow, the counter value is read as H’FFFF but changes to "reload register value – 1" at the next count clock timing. Because the timer operates synchronously with the count clock, up to one count clock-dependent delay is generated before F/F output is inverted after writing to the enable bit.

10 10.4 TIO (Input/Output-Related 16-Bit Timer) MULTIJUNCTION TIMERS 10-10432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 H'FFFF H'0000 H'E000 H'A000 H'E000 H'DFFF H'DFFF Data inverted by enable Data inverted by underflow Data inverted by underflow DMA transfer request (Note 1) DMA transfer request due to underflow TIO interrupt request due to underflow TIO interrupt request due to underflow DMA transfer request due to underflow (Unused) Count clock F/F output TIO interrupt request Enable bit Reload 0 register Counter Reload 1 register Underflow (first time) Count down from the counter set value Underflow (second time) Enabled (by writing to the enable bit or by external input) (Note 2) Note 1: Only TIO8 can be generated. Note 2: The value that "reload 0 register - 1" is reloaded. Note: This diagram does not show detailed timing information. (Note 2) Figure 10.4.15 Typical Operation in TIO Continuous Output Mode (without Correction Function)

10-10532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.5.1 Outline of TMS

TMS (Timer Measure Small) is an input-related 16-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table below shows specifications of TMS. Figure 10.5.1 shows a block diagram of TMS. Table 10.5.1 Specifications of TMS (Input-Related 16-Bit Timer) Item Specification Number of channels 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) Counter 16-bit up-counter × 2 Measure register 16-bit measure register × 8 Timer startup Started by writing to the enable bit in software Interrupt request generation Can be generated by a counter overflow

10.5.2 Outline of TMS Operation

In TMS, when the timer is enabled (by writing to the enable bit in software), the counter starts operating. The counter is a 16-bit up-counter, where the counter value is latched into each measure register when a measure signal is entered from an external device. The counter stops counting at the same time count is disabled by writing to the enable bit in software. TIN and TMS interrupt requests can be generated by external measure signal input and counter overflow, respectively (however, TMS0 does not have a TIN interrupt).

10-10632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Clock bus Input event bus 3 2 1 0 3 2 1 0 clk TMS 0 S ovf cap3 cap2 cap1 cap0 S S S S TCLK3 (P127) TCLK3S S S S S S TIN16S DMA4 TIN17S TIN16 (P130) TIN17 (P131) TIN18STIN18 (P132) TIN19STIN19 (P133) DMA2 IRQ10 IRQ10 IRQ10 IRQ10 Output event bus 0 1 2 3 IRQ7 S : Selector 3 2 1 0 3 2 1 0 0 1 2 3 Measure register 3 Measure registe 2 Measure registe 1 Measure registe 0 Counter (16-bit) clk TMS 1 ovf cap3 cap2 cap1 cap0 IRQ7 Measure registe 3 Measure registe 2 Measure registe 1 Measure registe 0 Counter (16-bit) Figure 10.5.1 Block Diagram of TMS (Input-Related 16-Bit Timer) <Count clock-dependent delay>

Because the timer operates synchronously with the count clock, there is a count clock-dependent delay from when the timer is enabled till when it actually starts operating. Figure 10.5.2 Count Clock-Dependent Delay BCLK Count clock Enable Count clock period Count clock-dependent delay Write to the enable bit

10-10732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.5.3 TMS Related Register Map

Shown below is a TMS related register map. TMS Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 03C0 TMS0 Counter 10-109 (TMS0CT) H'0080 03C2 TMS0 Measure 3 Register 10-109 (TMS0MR3) H'0080 03C4 TMS0 Measure 2 Register 10-109 (TMS0MR2) H'0080 03C6 TMS0 Measure 1 Register 10-109 (TMS0MR1) H'0080 03C8 TMS0 Measure 0 Register 10-109 (TMS0MR0) H'0080 03CA TMS0 Control Register TMS1 Control Register 10-108 (TMS0CR) (TMS1CR) (Use inhibited area) H'0080 03D0 TMS1 Counter 10-109 (TMS1CT) H'0080 03D2 TMS1 Measure 3 Register 10-109 (TMS1MR3) H'0080 03D4 TMS1 Measure 2 Register 10-109 (TMS1MR2) H'0080 03D6 TMS1 Measure 1 Register 10-109 (TMS1MR1) H'0080 03D8 TMS1 Measure 0 Register 10-109 (TMS1MR0)

10-10832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.5.4 TMS Control Registers

The TMS control registers are used to select TMS0/1 input events and count clock sources, as well as control count enable. Following two TMS control registers are included: TMS0 Control Register (TMS0CR) TMS1 Control Register (TMS1CR) TMS0 Control Register (TMS0CR) <Address: H’0080 03CA> <Upon exiting reset: H’00> b Bit Name Function R W

0 TMS0SS0 0: Does not use measure source R W

TMS0 measure 0 source select bit 1: Input event bus 0

1 TMS0SS1 0: Does not use measure source R W

TMS0 measure 1 source select bit 1: Input event bus 1

2 TMS0SS2 0: Does not use measure source R W

TMS0 measure 2 source select bit 1: Input event bus 2

3 TMS0SS3 0: Does not use measure source R W

TMS0 measure 3 source select bit 1: Input event bus 3 4, 5 TMS0CKS 00: External input TCLK3 R W TMS0 clock source select bit 01: Clock bus 0 10: Clock bus 1 11: Clock bus 3 6 No function assigned. Fix to "0". 00

7 TMS0CEN 0: Stop count R W

TMS0 count enable bit 1: Start count TMS1 Control Register (TMS1CR) <Address: H’0080 03CB> <Upon exiting reset: H’00> b Bit Name Function R W

8 TMS1SS0 0: External input TIN19 R W

TMS1 measure 0 source select bit 1: Input event bus 0

9 TMS1SS1 0: External input TIN18 R W

TMS1 measure 1 source select bit 1: Input event bus 1

10 TMS1SS2 0: External input TIN17 R W

TMS1 measure 2 source select bit 1: Input event bus 2

11 TMS1SS3 0: External input TIN16 R W

TMS1 measure 3 source select bit 1: Input event bus 3 12 No function assigned. Fix to "0". 00

13 TMS1CKS 0: Clock bus 0 R W

TMS1 clock source select bit 1: Clock bus 3 14 No function assigned. Fix to "0". 00

15 TMS1CEN 0: Stop count R W

TMS1 count enable bit 1: Start count b 0 123456 b 7 TMS0CKS TMS0CEN 00000000 TMS0 TMS0 TMS0 TMS0 SS0 SS1 SS2 SS3 b 8 9 1 01 11 21 31 4 b 1 5 TMS1CKS TMS1CEN 00000000 TMS1 TMS1 TMS1 TMS1 SS0 SS1 SS2 SS3

10-10932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.5.5 TMS Counters (TMS0CT, TMS1CT)

TMS0 Counter (TMS0CT) <Address: H’0080 03C0> TMS1 Counter (TMS1CT) <Address: H’0080 03D0> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TMS0CT, TMS1CT 16-bit counter value R W Note: These registers must always be accessed in halfwords. The TMS counter is a 16-bit up-counter, which starts counting when the timer is enabled (by writing to the enable bit in software). The counters can be read during operation.

10.5.6 TMS Measure Registers (TMS0MR3–0, TMS1MR3–0)

TMS0 Measure 3 Register (TMS0MR3) <Address: H’0080 03C2> TMS0 Measure 2 Register (TMS0MR2) <Address: H’0080 03C4> TMS0 Measure 1 Register (TMS0MR1) <Address: H’0080 03C6> TMS0 Measure 0 Register (TMS0MR0) <Address: H’0080 03C8> TMS1 Measure 3 Register (TMS1MR3) <Address: H’0080 03D2> TMS1 Measure 2 Register (TMS1MR2) <Address: H’0080 03D4> TMS1 Measure 1 Register (TMS1MR1) <Address: H’0080 03D6> TMS1 Measure 0 Register (TMS1MR0) <Address: H’0080 03D8> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TMS0MR3-TMS0MR0 16-bit counter value R – TMS1MR3-TMS1MR0 Notes: This register is a read-only register. This register can be accessed in either byte or halfword. The TMS measure registers are used to latch counter contents upon event input. The TMS measure registers are a read-only register. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TMS0CT, TMS1CT b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TMS0MR3-0, TMS1MR3-0

10-11032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.5.7 Operation of TMS Measure Input

(1) Outline of TMS measure input In TMS measure input, the timer starts counting up when it is enabled (by writing to the enable bit in soft- ware). Then when event input to TMS is detected while the timer is operating, the counter value is latched into measure registers 0–3. The timer stops counting at the same time count is disabled by writing to the enable bit. A TIN interrupt request can be generated by measure signal input from an external device (TMS1 alone has a TIN interrupt. TMS0 does not have a TIN interrupt.) A TMS interrupt request can be generated when the counter overflows. Count clock Counter H'FFFF H'0000 Enabled (by writing to the enable bit) Measure event 1 occurs Initial value (Undefined) Enable bit Note 1: TMS1 alone has a TIN interrupt. (TMS0 does not have a TIN interrupt.) Note: This diagram does not show detailed timing information. Measure 0 register H'8000 Overflow occurs TIN19 interrupt request (Note 1) H'C000 Measure 1 register TIN18 interrupt request (Note 1) Measure event 0 occurs TMS interrupt request due to overflow H'6000 H'D000 H'6000H'8000 Undefined value Initial value (Undefined) H'D000H'C000 Measure event 1 occurs Measure event 0 occurs Figure 10.5.3 Typical Operation of TMS Measure Input (2) Precautions on using TMS measure input The following describes precautions to be observed when using TMS measure input. If measure event input and write to the counter occur in the same clock period, the write value is set in the counter while at the same time latched into the measure register.

10-11132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 10.6.1 Block Diagram of TML (Input-Related 32-Bit Timer) Clock bus Input event bus 3 2 1 0 3 2 1 0 S S S S TIN20S TIN21S TIN20 (P134) TIN21 (P135) TIN22STIN22 (P136) TIN23STIN23 (P137) IRQ11 IRQ11 IRQ11 IRQ11 BCLK/2 Output event bus 0 1 2 3 S : Selector 3 2 1 0 3 2 1 0 0 1 2 3 clk TML0 cap3 cap2 cap1 cap0 Measure register 3 Measure register 2 Measure register 1 Measure register 0 Counter (32-bit) S S S S S clk TML1 cap3 cap2 cap1 cap0 Measure register 3 Measure register 2 Measure register 1 Measure register 0 Counter (32-bit) S DMA5 AD0TRG (to A/D0 converter)

10.6.1 Outline of TML

TML (Timer Measure Large) is an input-related 32-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table below shows specifications of TML. Figure 10.6.1 shows a block diagram of TML. Table 10.6.1 Specifications of TML (Input-Related 32-Bit Timer) Item Specification Number of channels 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) Input clock BCLK/2 (10.0 MHz when f(BCLK) = 20 MHz) or clock bus 1 input Counter 32-bit up-counter × 2 Measure register 32-bit measure register × 8 Timer startup Start counting after exiting the reset state

10-11232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.6.2 Outline of TML Operation

In TML, the timer starts counting upon deassertion of the reset input signal. The counter included in the timer is a 32-bit up-counter, where when a measure event signal is entered from an external device, the counter value at that point in time is stored in each 32-bit measure register. When the reset input signal is deasserted, the counter starts operating with a BCLK/2, and cannot be stopped once it has started. The counter is idle only when the microcomputer remains reset. A TIN interrupt request can be generated by external measure signal input (TML0 alone has a TIN interrupt. TML1 does not have a TIN interrupt.) However, no TML counter overflow interrupts are available.

10.6.3 TML Related Register Map

Shown below is a TML related register map. TML Related Register Map Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 03E0 TML0 Counter (Upper) 10-114 (TML0CTH) H'0080 03E2 TML0 Counter (Lower) 10-114 (TML0CTL) (Use inhibited area) H'0080 03EA (Use inhibited area) TML0 Control Register 10-113 (TML0CR) (Use inhibited area) H'0080 03F0 TML0 Measure 3 Register (Upper) 10-115 (TML0MR3H) H'0080 03F2 TML0 Measure 3 Register (Lower) 10-115 (TML0MR3L) H'0080 03F4 TML0 Measure 2 Register (Upper) 10-115 (TML0MR2H) H'0080 03F6 TML0 Measure 2 Register (Lower) 10-115 (TML0MR2L) H'0080 03F8 TML0 Measure 1 Register (Upper) 10-115 (TML0MR1H) H'0080 03FA TML0 Measure 1 Register (Lower) 10-115 (TML0MR1L) H'0080 03FC TML0 Measure 0 Register (Upper) 10-115 (TML0MR0H) H'0080 03FE TML0 Measure 0 Register (Lower) 10-115 (TML0MR0L) (Use inhibited area) H'0080 0FE0 TML1 Counter (Upper) 10-114 (TML1CTH) H'0080 0FE2 TML1 Counter (Lower) 10-114 (TML1CTL) (Use inhibited area) H'0080 0FEA (Use inhibited area) TML1 Control Register 10-113 (TML1CR) (Use inhibited area) H'0080 0FF0 TML1 Measure 3 Register (Upper) 10-116 (TML1MR3H) H'0080 0FF2 TML1 Measure 3 Register (Lower) 10-116 (TML1MR3L) H'0080 0FF4 TML1 Measure 2 Register (Upper) 10-116 (TML1MR2H) H'0080 0FF6 TML1 Measure 2 Register (Lower) 10-116 (TML1MR2L) H'0080 0FF8 TML1 Measure 1 Register (Upper) 10-116 (TML1MR1H) H'0080 0FFA TML1 Measure 1 Register (Lower) 10-116 (TML1MR1L) H'0080 0FFC TML1 Measure 0 Register (Upper) 10-116 (TML1MR0H) H'0080 0FFE TML1 Measure 0 Register (Lower) 10-116 (TML1MR0L)

10-11332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.6.4 TML Control Registers

TML0 Control Register (TML0CR) <Address: H’0080 03EB> <Upon exiting reset: H’00> b Bit Name Function R W

8 TML0SS0 0: External input TIN23 R W

TML0 measure 0 source select bit 1: Input event bus 0

9 TML0SS1 0: External input TIN22 R W

TML0 measure 1 source select bit 1: Input event bus 1

10 TML0SS2 0: External input TIN21 R W

TML0 measure 2 source select bit 1: Input event bus 2

11 TML0SS3 0: External input TIN20 R W

TML0 measure 3 source select bit 1: Input event bus 3 12–14 No function assigned. Fix to "0". 00

15 TML0CKS (Note 1) 0: BCLK/2 R W

TML0 clock source select bit 1: Clock bus 1 Note 1: The counter can only be written normally when BCLK/2 is used as the clock source for the counter. If the selected clock source is not BCLK/2, do not write to the counter because it cannot be written normally. TML1 Control Register (TML1CR) <Address: H’0080 0FEB> <Upon exiting reset: H’00> b Bit Name Function R W

8 TML1SS0 0: Does not use measure source R W

TML1 measure 0 source select bit 1: Input event bus 0

9 TML1SS1 0: Does not use measure source R W

TML1 measure 1 source select bit 1: Input event bus 1

10 TML1SS2 0: Does not use measure source R W

TML1 measure 2 source select bit 1: Input event bus 2

11 TML1SS3 0: Does not use measure source R W

TML1 measure 3 source select bit 1: Input event bus 3 12–14 No function assigned. Fix to "0". 00

15 TML1CKS (Note 1) 0: BCLK/2 R W

TML1 clock source select bit 1: Clock bus 1 Note 1: The counter can only be written normally when BCLK/2 is used as the clock source for the counter. If the selected clock source is not BCLK/2, do not write to the counter because it cannot be written normally. The TML control register is used to select TML input event and count clock. b8 9 10 11 12 13 14 b15 TML0SS0 TML0SS1 TML0SS2 TML0SS3 TML0CKS 00000000 b 8 9 1 01 11 21 31 4 b 1 5 TML1SS0 TML1SS1 TML1SS2 TML1SS3 TML1CKS 00000000

10-11432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.6.5 TML Counters

TML0 Counter (Upper) (TML0CTH) <Address: H’0080 03E0> TML0 Counter (Lower) (TML0CTL) <Address: H’0080 03E2> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TML0CTH 32-bit counter value (16 high-order bits) R W TML0CTL 32-bit counter value (16 low-order bits) Note: This register must always be accessed wordwise (in 32 bits) beginning with the address of the TML0CTH. The TML0 counter is a 32-bit up-counter, which starts counting upon deassertion of the reset input signal. The TML0CTH accommodates the 16 high-order bits of the 32-bit counter, and the TML0CTL accommodates the 16 low-order bits. The counters can be read during operation. TML1 Counter (Upper) (TML1CTH) <Address: H’0080 0FE0> TML1 Counter (Lower) (TML1CTL) <Address: H’0080 0FE2> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TML1CTH 32-bit counter value (16 high-order bits) R W TML1CTL 32-bit counter value (16 low-order bits) Note: This register must always be accessed wordwise (in 32 bits) beginning with the address of the TML1CTH. The TML1 counter is a 32-bit up-counter, which starts counting upon deassertion of the reset input signal. The TML1CTH accommodates the 16 high-order bits of the 32-bit counter, and the TML1CTL accommodates the 16 low-order bits. The counters can be read during operation. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TML0CTH (16 high-order bits) b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TML0CTL (16 low-order bits) b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TML1CTH (16 high-order bits) b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TML1CTL (16 low-order bits)

10-11532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.6.6 TML Measure Registers

TML0 Measure 3 Register (TML0MR3H) <Address: H’0080 03F0> TML0 Measure 3 Register (TML0MR3L) <Address: H’0080 03F2> TML0 Measure 2 Register (TML0MR2H) <Address: H’0080 03F4> TML0 Measure 2 Register (TML0MR2L) <Address: H’0080 03F6> TML0 Measure 1 Register (TML0MR1H) <Address: H’0080 03F8> TML0 Measure 1 Register (TML0MR1L) <Address: H’0080 03FA> TML0 Measure 0 Register (TML0MR0H) <Address: H’0080 03FC> TML0 Measure 0 Register (TML0MR0L) <Address: H’0080 03FE> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TML0MR3H–0H 32-bit measure register value (16 high-order bits) R – TML0MR3L–0L 32-bit measure register value (16 low-order bits) Notes: These registers are a read-only register. These registers must always be accessed wordwise (in 32 bits) beginning with the word boundary. The TML0 measure register is used to latch the counter content upon event input. The TML0 measure register consists of 32 bits, which TML0MR3H–0H and TML0MR3L–0L are 16 high-order bits and 16 low-order bits, respectively. The TML0 measure registers can only be read, and cannot be written to. The register must always be accessed wordwise beginning with the word boundary. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TML0MR3H-TML0MR0H (16 high-order bits) b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TML0MR3L-TML0MR0L (16 low-order bits)

10-11632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 TML1 Measure 3 Register (TML1MR3H) <Address: H’0080 0FF0> TML1 Measure 3 Register (TML1MR3L) <Address: H’0080 0FF2> TML1 Measure 2 Register (TML1MR2H) <Address: H’0080 0FF4> TML1 Measure 2 Register (TML1MR2L) <Address: H’0080 0FF6> TML1 Measure 1 Register (TML1MR1H) <Address: H’0080 0FF8> TML1 Measure 1 Register (TML1MR1L) <Address: H’0080 0FFA> TML1 Measure 0 Register (TML1MR0H) <Address: H’0080 0FFC> TML1 Measure 0 Register (TML1MR0L) <Address: H’0080 0FFE> <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 TML1MR3H–0H 32-bit measure register value (16 high-order bits) R – TML1MR3L–0L 32-bit measure register value (16 low-order bits) Notes: These registers are a read-only register. These registers must always be accessed wordwise (in 32 bits) beginning with the word boundary. The TML1 measure register is used to latch the counter content upon event input. The TML1 measure register consists of 32 bits, which TML1MR3H–0H and TML1MR3L–0L are 16 high-order bits and 16 low-order bits, respectively. The TML1 measure registers can only be read, and cannot be written to. The register must always be accessed wordwise beginning with the word boundary. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TML1MR3H-TML1MR0H (16 high-order bits) b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TML1MR3L-TML1MR0L (16 low-order bits)

10-11732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

10.6.7 Operation of TML Measure Input

(1) Outline of TML measure input In TML measure input, the counter starts counting up when the reset input signal is deasserted. Upon event input to measure registers 0–3, the counter value is latched into each measure register. A TIN interrupt request can be generated by measure signal input from an external device (TML0 alone has a TIN interrupt. TML1 does not have a TIN interrupt.) However, no TML counter overflow interrupts are available. Figure 10.6.2 Typical Operation of TML Measure Input Count clock Counter (32-bit) H'FFFF FFFF H'0000 0000 Enabled (by deassertion of reset) Undefined Reset Note 1: TML0 alone has a TIN interrupt. (TML1 does not have a TIN interrupt.) Note: • This diagram does not show detailed timing information. Measure 0 register Overflow occurs TIN23 interrupt request (Note 1) Measure 1 register TIN22 interrupt request (Note 1) Measure event 0 occurs H'8000 0000 H'C000 0000 H'8000 0000 H'6000 0000 H'6000 0000 H'D000 0000 Undefined value Undefined H'C000 0000 H'D000 0000 Measure event 1 occurs Measure event 0 occurs Measure event 1 occurs

10-11832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) Precautions on using TML measure input The following describes precautions to be observed when using TML measure input. If measure event input and write to the counter occur in the same clock period, the write value is set in the counter, whereas the up-count value (before being rewritten) is latched into the measure register. If clock bus 1 is selected and any clock other than BCLK/2 is used for the timer, the counter cannot be written normally. Therefore, when using any clock other than BCLK/2, do not write to the counter. If clock bus 1 is selected and any clock other than BCLK/2 is used for the timer, the value captured into the measure register is one count larger the counter value. During the count clock to BCLK/2 period interval, however, the captured value is exactly the counter value. The diagram below shows the relationship between counter operation and the valid data that can be cap- tured. Counter BAC D E F AB CD E When BCLK/2 is selected BCLK/2 Captured Counter BA C When clock bus 1 is selected BCLK/2 Count clock Captured BC D F Figure 10.6.3 Mistimed Counter Value and the Captured Value

11.1 Outline of A/D Converter

11.2 A/D Converter Related Registers

11.3 Functional Description of A/D Converter

11.4 Inflow Current Bypass Circuit

11.5 Notes on Using A/D Converter

11-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The 32176 contains 10-bit resolution A/D Converter of the successive approximation type. The A/D converter has 16 analog input pins (channels) AD0IN0–AD0IN15. In addition to performing conversion individually on each channel, the A/D Converter can perform conversion successively on all of N channels (N = 1–16) as a single group. The conversion result can be read out in either 10 or 8 bits. There are following conversion and operation modes for the A/D conversion: (1) Conversion Modes A/D conversion mode : Ordinary mode in which analog input voltages are converted into digital quantities. Comparator mode (Note 1): A mode in which analog input voltage is compared with a preset comparison voltage to find only the relative magnitude of two quantities. (Useful in only single operation mode) (2) Operation Modes Single mode : Analog input voltage on one channel is A/D converted once or comparated (Note 1) with a given quantity. Scan mode : Analog input voltages on two or more selected channels (in N channel units, N = 1–16) are sequentially A/D converted. Single-shot scan mode : Scan operation is performed for one cycle. Continuous scan mode : Scan operation is repeatedly until stopped. (3) Special Operation Modes Forcible single mode execution during scan mode : Conversion is forcibly executed in single mode (compara- tor mode) during scan operation. Scan mode start after single mode execution : Scan operation is started subsequently after executing conversion in single mode. Conversion restart : A/D conversion being executed in single or scan mode is restarted. (4) Sample-and-Hold Function The analog input voltage is sampled when starting A/D conversion, and A/D conversion is performed on the sampled voltage. This function can be enabled or disabled as necessary. (5) A/D Disconnection Detection Assist Function To suppress influences of the analog input voltage leakage from any preceding channel during scan mode operation, a function is incorporated that helps to fix the electric charge on the chopper amp capacitor to the given state (AVCC0 or AVSS0) before starting A/D conversion. This function provides a sure and reliable means of detecting a disconnection in the wiring patterns connecting to the analog input pins. (6) Inflow Current Bypass Circuit If an overvoltage or negative voltage is applied to any analog input channel which is currently inactive, a current flows into or out of the analog input channel currently being A/D converted via the internal circuit, causing the conversion accuracy to degrade. To solve this problem, the A/D Converter incorporates a circuit that bypasses such inflow current. This circuit is always enabled. (7) Conversion Speed The A/D conversion and comparate speed can be selected from a total of four speeds available: slow mode (normal or double speed) and fast mode (normal or double speed). The normal speed and double speed in slow mode are compatible with the 32170 group of Renesas microcomputers.

11-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (8) Interrupt Request and DMA Transfer Request Generation Functions An A/D conversion interrupt or DMA transfer request can be generated each time A/D conversion or comparate operation in single mode is completed, as well as when a single-shot scan operation or one cycle of continuous scan operation is completed. Note 1: To discriminate between the comparison performed internally by the successive approximation- type A/D Converter and that performed in comparator mode using the same A/D Converter as a comparator, the comparison in comparator mode is referred to in this manual as “comparate.” Table 11.1.1 Outline of the A/D Converter Item Description Analog input 16 channels A/D conversion method Successive approximation method Resolution 10 bits (Conversion result can be read out in either 8 or 10 bits) Absolute accuracy (Note 1)When sample-and-hold disabled Slow mode Normal speed ±2LSB Conditions: Ta = 25°C, or normal sample-and-hold enabled Double speed ±2LSB AVCC0 = 5.12 V, Fast mode Normal speed ±3LSB VREF0 = 5.12 V Double speed ±3LSB When fast sample-and-hold enabled Slow mode Normal speed ±3LSB Double speed ±3LSB Fast mode Normal speed ±3LSB Double speed ±8LSB Conversion mode A/D conversion mode and comparator mode Operation mode Single mode, single-shot scan mode and continuous scan mode Conversion start trigger Software start Started by setting the A/D conversion start bit to "1" Hardware start A/D0 Converter MJT (input event bus 2), MJT (input event bus 3), MJT (output event bus 3) and MJT (TIN23S) Conversion speed During single mode Slow mode Normal speed299BCLK 14.95µs (Note 2) BCLK: ( When sample-and-hold disabled Double speed173BCLK 8.65µs Internal peripheral clock When normal sample-and-hold enabled)Fast mode Normal speed131BCLK 6.55µs Double speed 89BCLK 4.45µs During single mode Slow mode Normal speed191BCLK 9.55µs (When fast sample-and-hold enabled) Double speed101BCLK 5.05µs Fast mode Normal speed 95BCLK 4.75µs Double speed 53BCLK 2.65µs During comparator mode Slow mode Normal speed 47BCLK 2.35µs Double speed 29BCLK 1.45µs Fast mode Normal speed 23BCLK 1.15µs Double speed 17BCLK 0.85µs Sample-and-hold functionSample-and-hold function can be enabled or disabled as necessary. A/D disconnection Influences of the analog input voltage leakage from any preceding channel during scan detection assist functionmode operation are suppressed. Interrupt request Generated when A/D conversion (single mode operation, single-shot scan operation or one cycle of generation function continuous operation) or comparate operation is completed DMA transfer request Generated when A/D conversion (single mode operation, single-shot scan operation or one cycle of generation function continuous operation) or comparate operation is completed Note 1: The conversion accuracy stipulated here refers to that of the microcomputer alone, with influences of the power supply wiring and noise on the board not taken into account. Note 2: This indicates the conversion time when f(BCLK) = 20 MHz (1 BCLK = 50 ns).

11-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11 11.1 Outline of A/D Converter Figure 11.1.1 Block Diagram of the A/D0 Converter AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 Selector Interrupt requestAVSS0 VREF0 10-bit A/D Successive Approximation Register (AD0SAR) 10-bit A/D0 Data Register 0 10-bit A/D0 Data Register 1 A/D0 Single Mode Register A/D Comparate Data Register A/D Control Circuit

Mode selection Channel selection Conversion time selection Interrupt control Flag control10-bit D/A Converter Comparator AD0IN8 AD0IN9 AD0N10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 AD0CMP AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0DT12 AD0DT13 AD0DT14 AD0DT15 DMA transfer request DMA0 Successive Approximation-type A/D Converter Unit Internal data bus A/D0 Scan Mode RegisterAD0SCM0, 1 AD0SIM0, 1 AVCC0 10-bit readout 8-bit readout Shifter 10-bit A/D0 Data Register 2 10-bit A/D0 Data Register 3 10-bit A/D0 Data Register 4 10-bit A/D0 Data Register 5 10-bit A/D0 Data Register 6 10-bit A/D0 Data Register 7 10-bit A/D0 Data Register 8 10-bit A/D0 Data Register 9 10-bit A/D0 Data Register 10 10-bit A/D0 Data Register 11 10-bit A/D0 Data Register 12 10-bit A/D0 Data Register 13 10-bit A/D0 Data Register 14 10-bit A/D0 Data Register 15 Input event bus 3 Input event bus 2 Output event bus 3 TIN23S S S AD0CTRG1 AD0STRG1 Sample-and-Hold Control Circuit

11-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 11.1.2 Operation in Single Mode (A/D Conversion) A/D conversion interrupt or DMA transfer request Note 1: A/D0 conversion start: Software trigger → Started by setting the A/D0 conversion start bit to "1" Hardware trigger → Started by input event bus 3, input event bus 2, output event bus 3 or TIN23S signal input ADiINn Completed ADiDTn 10-bit A/Di Data Register Conversion starts (Note 1) i=0 n=0–15

11.1.1 Conversion Modes

The A/D Converter has two conversion modes: “A/D Conversion mode” and “Comparator mode.” (1) A/D Conversion Mode In A/D conversion mode, the analog input voltage on a specified channel is A/D converted. In single mode, A/D conversion is performed on a channel selected by the A/D Single Mode Register 1 analog input pin select bit. In scan mode, A/D conversion is performed on channels selected by A/D Scan Mode Register 1 according to settings of A/D Scan Mode Register 0. The conversion result is stored in each channel’s corresponding 10-bit A/D Data Register. There is also an 8-bit A/D Data Register for each channel, from which 8-bit A/D conversion results can be read out. An A/D conversion interrupt or DMA transfer request can be generated when A/D conversion in single mode is completed, as well as when one cycle of scan loop in scan mode is completed. (2) Comparator Mode In comparator mode, the analog input voltage on a specified channel is “comparated” (compared) with the successive approximation register value, and the result (relative magnitude of two values) is returned to a flag. The channel to be comparated is selected using the A/D Single Mode Register 1 analog input pin select bit. The result of comparate operation is flagged ("0" or "1") by setting the A/D Comparate Data Register bit that corresponds to the selected channel. An A/D conversion interrupt or DMA transfer request can be generated when comparate operation is completed.

11.1.2 Operation Modes

There are two operation modes for the A/D Converter: “Single mode” and “Scan mode.” When comparator mode is selected as A/D conversion mode, only single mode can be used. (1) Single Mode In single mode, the analog input voltage on one selected channel is A/D converted or comparated once. An A/D conversion interrupt or DMA transfer request can be generated when A/D conversion or comparate operation is completed.

11-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 A/D conversion interrupt or DMA transfer request ADiIN0 Completed here when operating in single-shot scan mode ADiDT010-bit A/Di Data Register Conversion starts (Note 1) ADiIN1 ADiINn-1 ADiINn ADiDT1 ADiDTn-1 ADiDTn During continuous scan mode <n-channel scan> i= 0 n=0–15 Note 1: A/D0 conversion start: Software trigger → Started by setting the A/D0 conversion start bit to "1" Hardware trigger → Started by input event bus 3, input event bus 2, output event bus 3 or TIN23S signal input Figure 11.1.4 Operation of A/D Conversion in Scan Mode Figure 11.1.3 Operation in Single Mode (Comparate) (2) Scan Mode In scan mode, the analog input voltages from channel 0 to the channel selected by the A/D Scan Mode Register 1 scan loop select bit (channels 0–15) are sequentially A/D converted. There are two types of scan mode: “Single-shot scan mode” in which A/D conversion is completed after performing one cycle of scan operation, and “Continuous scan mode” in which scan operation is continued until halted by setting the A/D scan mode register 0’s A/D conversion stop bit to "1". These types of scan mode are selected using A/D Scan Mode Register 0. The channels to be scanned are selected using A/D Scan Mode Register 1. The selected channels are scanned sequentially beginning with channel 0. An A/D conversion interrupt or DMA transfer request can be generated when one cycle of scan operation is completed. A/D conversion interrupt or DMA transfer request Note 1: Comparate operation is started by writing a comparison value to the Successive Approximation Register (ADiSAR) ADiINn Completed ADiCMP A/Di Comparate Data Register Conversion starts (Note 1) ADiSAR A/D Successive Approximation Register Comparate result ADiCMP=0 (ANn > ADiSAR) ADiCMP=1 (ANn < ADiSAR) i=0 n=0–15

11-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 11.1.2 Registers in Which Scan Mode A/D Conversion Results Are Stored Scan Mode Register 1 Selected channels Selected channels A/D conversion result channel selection for single-shot scan for continuous scan storage register B'0000:0 ADiIN0 ADiIN0 10-bit A/Di Data Register 0 (ADiIN0) Completed ADiIN0 10-bit A/Di Data Register 0 (Repeated until forcibly terminated) B'0001:1 ADiIN0 ADiIN0 10-bit A/Di Data Register 0 (ADiIN1) ADiIN1 ADiIN1 10-bit A/Di Data Register 1 Completed ADiIN0 10-bit A/Di Data Register 0 (Repeated until forcibly terminated) B'0010:2 ADiIN0 ADiIN0 10-bit A/Di Data Register 0 (ADiIN2) ADiIN1 ADiIN1 10-bit A/Di Data Register 1 ADiIN2 ADiIN2 10-bit A/Di Data Register 2 Completed ADiIN0 10-bit A/Di Data Register 0 (Repeated until forcibly terminated) B'0011:3 ADiIN0 ADiIN0 10-bit A/Di Data Register 0 (ADiIN3) ADiIN1 ADiIN1 10-bit A/Di Data Register 1 ADiIN2 ADiIN2 10-bit A/Di Data Register 2 ADiIN3 ADiIN3 10-bit A/Di Data Register 3 Completed ADiIN0 10-bit A/Di Data Register 0 (Repeated until forcibly terminated) B'XXXX:n ADiIN0 ADiIN0 10-bit A/Di Data Register 0 (ADiINn) ADiIN1 ADiIN1 10-bit A/Di Data Register 1 ADiIN2 ADiIN2 10-bit A/Di Data Register 2 n≤15 ... ADiINn ADiINn 10-bit A/Di Data Register n Completed ADiIN0 10-bit A/Di Data Register 0 (Repeated until forcibly terminated) (i=0) … …

11-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

11.1.3 Special Operation Modes

(1) Forcible single mode execution during scan mode In this special operation mode, single mode conversion (A/D conversion or comparate) is forcibly executed on a specified channel during scan mode operation. For A/D conversion mode, the conversion result is stored in the 10-bit A/D Data Register corresponding to the specified channel, whereas for comparate mode, the conversion result is stored in the 10-bit A/D Comparate Data Register. When the A/D conversion or comparate operation on a specified channel finishes, scan mode A/D conversion is restarted from where it was canceled during scan operation. To start single mode conversion during scan mode operation in software, choose a software trigger using the A/D Single Mode Register 0 A/D conversion start trigger select bit. Then, for A/D conversion, set the said register’s A/D conversion start bit to "1". For comparate mode, write a comparison value to the A/D Succes- sive Approximation Register (AD0SAR) during scan mode operation. To start single mode conversion during scan mode operation in hardware, choose a hardware trigger using the A/D Single Mode Register 0 A/D conversion start trigger select bit. Then enter the hardware trigger selected with the said register. An A/D conversion interrupt or DMA transfer request can be generated when conversion on a specified channel or one cycle of scan operation is completed. Figure 11.1.5 Forcible Single Mode Execution during Scan Mode A/D conversion interrupt or DMA transfer request ADiIN0 ADiDT010-bit A/Di Data Register Scan mode conversion starts ADiIN1 ADiDT1 ADiDT5 Note 1: The canceled convert operation on channel 2 is reexecuted from the beginning. <To perform single mode conversion on channel ADiIN5 during ADiIN2 conversion in n-channel single-shot scan mode> CompletedADiIN2 ADiINn ADiDT2 ADiDTn ADiIN5 Forcible single mode execution starts (Note 1) ADiIN2 i=0 n=0–15

11-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 11.1.6 Scan Mode Start after Single Mode Execution A/D conversion interrupt or DMA transfer request ADiIN0 ADiDT010-bit A/Di Data Register Instructed to start scan mode conversion ADiIN1 ADiDT1ADiDT5 <To start n-channel single-shot scan mode subsequently after single mode conversion on channel ADiIN5> CompletedADiINn-1 ADiINn ADiDTn-1 ADiDTn ADiIN5 Single mode conversion starts i=0 n=0–15 (2) Scan mode start after single mode execution In this special operation mode, scan operation is started subsequently after executing single mode conver- sion (A/D conversion or comparate). To start this mode in software, choose a software trigger using the A/D Scan Mode Register 0 A/D conver- sion start trigger select bit. Then set the said register’s A/D conversion start bit to "1" during single mode conversion operation. To start this mode in hardware, choose a hardware trigger using the A/D Scan Mode Register 0 A/D conver- sion start trigger select bit. Then enter the hardware trigger selected with the said register during single mode conversion operation. If a hardware trigger is selected using the A/D conversion start trigger select bit in both A/D Single Mode Register 0 and A/D Scan Mode Register 0 and the selected hardware triggers are entered, the A/D Con- verter first performs single mode conversion and then scan mode conversion in succession. An A/D conversion interrupt or DMA transfer request can be generated when single mode conversion on a specified channel or one cycle of scan operation is completed.

11-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

11.1.4 A/D Converter Interrupt and DMA Transfer Requests

The A/D Converter can generate an A/D conversion interrupt or DMA transfer request each time A/D conver- sion, comparate operation, single-shot scan or one cycle of continuous scan mode is completed. The A/D Single Mode Register 0 and A/D Scan Mode Register 0 are used to select between A/D conversion interrupt and DMA transfer requests. Figure 11.1.9 Selecting between Interrupt and DMA Transfer Requests

11.1.5 Sample-and-Hold Function

The analog input voltage that was sampled immediately after A/D conversion started is held on, and A/D conversion is performed on that seized voltage. The A/D conversion time in “normal” sample-and-hold mode is the same as in conventional A/D conversion mode of the 32170, etc. The A/D conversion time in “fast” sample-and-hold mode is significantly short, allowing to obtain conversion results more quickly than ever. Scan mode (when one cycle of scan is completed) Single mode (when A/D conversion or comparate operation is completed) A/D conversion interrupt request (To the Interrupt Controller) DMA transfer request (To the DMAC) A/D Scan Mode Register 0 interrupt/DMA transfer request select bit A/D Single Mode Register 0 interrupt/DMA transfer request select bit

11-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Shown below is an A/D converter related register map. A/D Converter Related Register Map (1/2) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0080 A/D0 Single Mode Register 0 A/D0 Single Mode Register 1 11-14 (AD0SIM0) (AD0SIM1) 11-16 H'0080 0082 (Use inhibited area) H'0080 0084 A/D0 Scan Mode Register 0 A/D0 Scan Mode Register 1 11-18 (AD0SCM0) (AD0SCM1) 11-20 H'0080 0086 A/D0 Disconnection Detection Assist Function Control RegisterA/D0 Conversion Speed Control Register 11-23 (AD0DDACR) (AD0CVSCR) 11-22 H'0080 0088 A/D0 Successive Approximation Register 11-27 (AD0SAR) H'0080 008A A/D0 Disconnection Detection Assist Method Select Register 11-24 (AD0DDASEL) H'0080 008C A/D0 Comparate Data Register 11-28 (AD0CMP) H'0080 008E (Use inhibited area) H'0080 0090 10-bit A/D0 Data Register 0 11-29 (AD0DT0) H'0080 0092 10-bit A/D0 Data Register 1 11-29 (AD0DT1) H'0080 0094 10-bit A/D0 Data Register 2 11-29 (AD0DT2) H'0080 0096 10-bit A/D0 Data Register 3 11-29 (AD0DT3) H'0080 0098 10-bit A/D0 Data Register 4 11-29 (AD0DT4) H'0080 009A 10-bit A/D0 Data Register 5 11-29 (AD0DT5) H'0080 009C 10-bit A/D0 Data Register 6 11-29 (AD0DT6) H'0080 009E 10-bit A/D0 Data Register 7 11-29 (AD0DT7) H'0080 00A0 10-bit A/D0 Data Register 8 11-29 (AD0DT8) H'0080 00A2 10-bit A/D0 Data Register 9 11-29 (AD0DT9) H'0080 00A4 10-bit A/D0 Data Register 10 11-29 (AD0DT10) H'0080 00A6 10-bit A/D0 Data Register 11 11-29 (AD0DT11) H'0080 00A8 10-bit A/D0 Data Register 12 11-29 (AD0DT12) H'0080 00AA 10-bit A/D0 Data Register 13 11-29 (AD0DT13) H'0080 00AC 10-bit A/D0 Data Register 14 11-29 (AD0DT14) H'0080 00AE 10-bit A/D0 Data Register 15 11-29 (AD0DT15) H'0080 00D0 (Use inhibited area) 8-bit A/D0 Data Register 0 11-30 (AD08DT0) H'0080 00D2 (Use inhibited area) 8-bit A/D0 Data Register 1 11-30 (AD08DT1) H'0080 00D4 (Use inhibited area) 8-bit A/D0 Data Register 2 11-30 (AD08DT2) H'0080 00D6 (Use inhibited area) 8-bit A/D0 Data Register 3 11-30 (AD08DT3) H'0080 00D8 (Use inhibited area) 8-bit A/D0 Data Register 4 11-30 (AD08DT4) H'0080 00DA (Use inhibited area) 8-bit A/D0 Data Register 5 11-30 (AD08DT5) H'0080 00DC (Use inhibited area) 8-bit A/D0 Data Register 6 11-30 (AD08DT6)

11-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 A/D Converter Related Register Map (2/2) Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 00DE (Use inhibited area) 8-bit A/D0 Data Register 7 11-30 (AD08DT7) H'0080 00E0 (Use inhibited area) 8-bit A/D0 Data Register 8 11-30 (AD08DT8) H'0080 00E2 (Use inhibited area) 8-bit A/D0 Data Register 9 11-30 (AD08DT9) H'0080 00E4 (Use inhibited area) 8-bit A/D0 Data Register 10 11-30 (AD08DT10) H'0080 00E6 (Use inhibited area) 8-bit A/D0 Data Register 11 11-30 (AD08DT11) H'0080 00E8 (Use inhibited area) 8-bit A/D0 Data Register 12 11-30 (AD08DT12) H'0080 00EA (Use inhibited area) 8-bit A/D0 Data Register 13 11-30 (AD08DT13) H'0080 00EC (Use inhibited area) 8-bit A/D0 Data Register 14 11-30 (AD08DT14) H'0080 00EE (Use inhibited area) 8-bit A/D0 Data Register 15 11-30 (AD08DT15)

11-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11 11.2 A/D Converter Related Registers

11.2.1 A/D Single Mode Register 0

A/D0 Single Mode Register 0 (AD0SIM0) <Address: H’0080 0080> 123456 b 7b0 ADSTRG0ADSTRG1 ADSSEL ADSREQ ADSSTT ADSSTPADSCMP 0 0001000 <Upon exiting reset: H’04> b Bit Name Function R W 0 ADSTRG1 (Note 1) Bits 0 and 2 are used to select an A/D hardware trigger. R W A/D hardware trigger select 1 bit b0 b2 0 0 : Input event bus 2 0 1 : Input event bus 3 1 0 : Output event bus 3 1 1 : TIN23S signal 1 No function assigned. Fix to "0". 00 2 ADSTRG0 (Note 1) Bits 0 and 2 are used to select an A/D hardware trigger. R W A/D hardware trigger select 0 bit (See the column for bit 0.)

3 ADSSEL 0: Software trigger R W

A/D conversion start trigger select bit 1: Hardware trigger (Note 2)

4 ADSREQ 0: A/D conversion interrupt request R W

A/D Interrupt/DMA transfer request select bit 1: DMA transfer request

5 ADSCMP 0: A/D conversion/comparate in progress R –

A/D conversion/comparate completed bit 1: A/D conversion/comparate completed

6 ADSSTP 0: No operation 0 W

A/D conversion stop bit 1: Stop A/D conversion

7 ADSSTT 0: No operation 0 W

A/D conversion start bit 1:Start A/D conversion Note 1: Two bits—bit 0 (A/D hardware trigger select 1) and bit 2 (A/D hardware trigger select 0)—are used to select an A/D hardware trigger. Note 2: During comparator mode, hardware triggers, if any selected, are ignored and operation is started by a software trigger. A/D Single Mode Register 0 is used to control operation of the A/D Converter during single mode (including “Forcible single mode execution during scan mode”). (1) ADSTRG (A/D Hardware Trigger Select) bits (Bits 0 and 2) These bits select a hardware trigger when A/D conversion by the A/D Converter is to be started in hardware. Select one from the following hardware trigger sources: A/D0 Converter: Input event bus 2 Input event bus 3 Output event bus 3 TIN23 edge select output The contents of these bits are ignored if a software trigger is selected by ADSSEL (A/D conversion start trigger select bit).

11-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) ADSSEL (A/D Conversion Start Trigger Select) bit (Bit 3) This bit selects whether to use a software or hardware trigger to start A/D conversion during single mode. If a software trigger is selected, A/D conversion is started by setting the ADSSTT (A/D conversion start) bit to "1". If a hardware trigger is selected, A/D conversion is started by the trigger source selected with the ADSTRG (hardware trigger select) bits. (3) ADSREQ (A/D Interrupt Request/DMA Transfer Request Select) bit (Bit 4) This bit selects whether to request an A/D conversion interrupt or a DMA transfer when single mode opera- tion (A/D conversion or comparate) is completed. If neither an interrupt nor a DMA transfer are used, choose to request an A/D conversion interrupt and use the A/D Conversion Interrupt Control Register of the Inter- rupt Controller (ICU) to mask the interrupt request, or choose to request a DMA transfer and use the DMA Channel Control Register to disable DMA transfers to be performed upon completion of A/D conversion. (4) ADSCMP (A/D Conversion/Comparate Completed) bit (Bit 5) This is a read-only bit, whose value when exiting the reset state is "1". This bit is "0" when the A/D Converter is performing single mode operation (A/D conversion or comparate) and is set to "1" when the operation finishes. This bit is also set to "1" when A/D conversion or comparate operation is forcibly terminated by setting the ADSSTP (A/D conversion stop) bit to "1" during A/D conversion or comparate operation. (5) ADSSTP (A/D Conversion Stop) bit (Bit 6) Setting this bit to "1" while the A/D Converter is performing single mode operation (A/D conversion or comparate) causes the operation being performed to stop. Manipulation of this bit is ignored while single mode operation is idle or scan mode operation is under way. Operation stops immediately after writing to this bit. If the A/D Successive Approximation Register is read after being stopped, the content read from the register is the value in the middle of conversion (not trans- ferred to the A/D Data Register). If the A/D conversion start bit and A/D conversion stop bit are set to "1" at the same time, the A/D conversion stop bit has priority. If this bit is set to "1" when performing single mode operation in special mode “Forcible single mode execu- tion during scan mode,” only single mode conversion stops and scan mode operation restarts. (6) ADSSTT (A/D Conversion Start) bit (Bit 7) If this bit is set to "1" when a software trigger has been selected with the ADSSEL (A/D conversion start trigger select) bit, the A/D Converter starts A/D conversion. If the A/D conversion start bit and A/D conversion stop bit are set to "1" at the same time, the A/D conversion stop bit has priority. If this bit is set to "1" again while performing single mode conversion, special operation mode “Conversion restart” is turned on, so that single mode conversion restarts. If this bit is set to "1" again while performing A/D conversion in scan mode, special operation mode “Forcible single mode execution during scan mode” is turned on, so that the channel being converted in scan mode is canceled and single mode conversion is performed. When the single mode conversion finishes, scan mode A/D conversion restarts beginning with the canceled channel.

11-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11 11.2 A/D Converter Related Registers

11.2.2 A/D Single Mode Register 1

A/D0 Single Mode Register 1 (AD0SIM1) <Address: H’0080 0081> 9 1 01 11 21 31 4 b 1 5b8 ADSMSL ADSSPD ADSSHSL ANSEL 00000000 ADSSHSPD <Upon exiting reset: H’00> b Bit Name Function R W

8 ADSMSL 0: A/D0 conversion mode R W

A/D conversion mode select bit 1: Comparator mode

9 ADSSPD (Note 1) 0: Normal speed R W

A/D conversion speed select bit 1: Double speed

10 ADSSHSL 0: Disable sample-and-hold R W

A/D conversion method select bit 1: Enable sample-and-hold

11 ADSSHSPD (Note 2) 0: Normal sample-and-hold R W

A/D sample-and-hold conversion speed select bit 1: Fast sample-and-hold 12–15 ANSEL 0000 : Select ADiIN0 (i = 0) R W A/D analog input pin select bit 0001 : Select ADiIN1 0010 : Select ADiIN2 0011 : Select ADiIN3 0100 : Select ADiIN4 0101 : Select ADiIN5 0110 : Select ADiIN6 0111 : Select ADiIN7 1000 : Select ADiIN8 1001 : Select ADiIN9 1010 : Select ADiIN10 1011 : Select ADiIN11 1100 : Select ADiIN12 1101 : Select ADiIN13 1110 : Select ADiIN14 1111 : Select ADiIN15 Note 1: The A/D conversion speed is determined by a combination of ADSSPD, ADSSHSL and ADSSHSPD bits and the A/D Conversion Speed Control Register ADCVSD bit. Note 2: Setting of this bit is effective when the sample-and-hold function is enabled by ADSSHSL bit. A/D Single Mode Register 1 is used to select operation mode, conversion speed and analog input pins when the A/D Converter is operating in single mode.

11-1732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (1) ADSMSL (A/D Conversion Mode Select) bit (Bit 8) This bit selects A/D conversion mode when the A/D Converter is operating in single mode. Setting this bit to "0" selects A/D conversion mode, and setting this bit to "1" selects comparator mode. (2) ADSSPD (A/D Conversion Speed Select) bit (Bit 9) This bit selects the A/D conversion speed when the A/D Converter is operating in single mode. Setting this bit to "0" selects normal speed, and setting this bit to "1" selects double speed. (3) ADSSHSL (A/D Conversion Method Select) bit (Bit 10) This bit enables or disables the sample-and-hold function when the A/D Converter is operating in single mode. Setting this bit to "0" disables the sample-and-hold function, and setting this bit to "1" enables the sample-and-hold function. Setting of this bit has no effect if comparator mode is selected with the ADSMSL (A/D conversion mode select) bit. (4) ADSSHSPD (A/D Sample-and-Hold Speed Select) bit (Bit 11) When the A/D Converter’s sample-and-hold function is enabled, this bit selects a conversion speed. When this bit is "0", the conversion speed is the same as normal A/D conversion speed. When this bit is "1", conversion is performed at a speed faster than normal A/D conversion speed. Setting of this bit has no effect if the sample-and-hold function is disabled by setting the ADSSHSL (A/D conversion method select) bit to "0". For details about the conversion time, see Section 11.3.4, “Calculating the A/D Conversion Time.” (5) ANSEL (A/D Analog Input Pin Select) bits (Bits 12–15) These bits select the analog input pins when the A/D Converter is operating in single mode. A/D conversion or comparate operation is performed on the channels selected with these bits. If these bits are accessed for read, the value written to them is read out. Notes: If either A/D conversion method select (ADSSHSL) bit in A/D0 Single Mode Register 1 (AD0SIM1) or A/D conversion method select (ADCSHSL) bit in A/D0 Scan Mode Register 1 (AD0SCM1) is selected as sample-and-hold enabled, both single and scan mode operate under sample-and-hold enabled mode. If either A/D conversion method select (ADSSHSL) bit in A/D0 Single Mode Register 1 (AD0SIMI1) or A/D conversion method select (ADCSHSL) bit in A/D0 Scan Mode Register 1 (AD0SCM1) is selected as sample-and-hold enabled, and A/D sample-and-hold conversion speed select (ADSSHSPD) bit in A/D0 Single Mode Register 1 (AD0SM1) or A/D sample- and-hold conversion speed select (ADCSHSPD) bit in A/D0 Scan Mode Register 1 (AD0SCM1) is selected as fast sample-and-hold, both single and scan mode operate in fast sample-and-hold conversion spped. To use single or scan mode under sample-and-hold enabled mode, make sure that A/D con- version method select (ADSSHSL) bit in A/D0 Single Mode Register 1 (AD0SIM1), A/D con- version method select (ADCSHSL) bit in A/D0 Scan Mode Register 1 (AD0SCM1), A/D sample-and-hold conversion spped select (ADSSHSPD)bit in A/D0 Single Mode Register 1 (AD0SIM1) and A/D sample-and-hold conversion speed select (ADCSHSPD) bit in A/D0 Scan Mode Register 1 (AD0SCM1) are set in the same value.

11-1832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11 11.2 A/D Converter Related Registers

11.2.3 A/D Scan Mode Register 0

A/D0 Scan Mode Register 0 (AD0SCM0) <Address: H’0080 0084> <Upon exiting reset: H’04> b Bit Name Function R W 0 ADCTRG1 (Note 1) Bits 0 and 2 are used to select an A/D hardware trigger. R W A/D hardware trigger select 1 bit b0 b2 0 0 : Input event bus 2 0 1 : Input event bus 3 1 0 : Output event bus 3 1 1 : TIN23S signal

1 ADCMSL 0: Single-shot mode R W

A/D scan mode select bit 1: Continuous mode 2 ADCTRG0 Bits 0 and 2 are used to select an A/D hardware trigger. R W A/D hardware trigger select 0 bit (See the column for bit 0.)

3 ADCSEL 0: Software trigger R W

A/D conversion start trigger select bit 1: Hardware trigger

4 ADCREQ 0: A/D conversion interrupt request R W

A/D Interrupt/DMA transfer request select bit 1: DMA transfer request

5 ADCCMP 0: A/D conversion in progress R –

A/D conversion completed bit 1: A/D conversion completed

6 ADCSTP 0: No operation 0 W

A/D conversion stop bit 1: Stop A/D conversion

7 ADCSTT 0: No operation 0 W

A/D conversion start bit 1: Start A/D conversion Note 1: Two bits—bit 0 (A/D hardware trigger select 1) and bit 2 (A/D hardware trigger select 0)—are used to select an A/D hardware trigger. A/D Scan Mode Register 0 is used to control operation of the A/D Converter during scan mode. (1) ADCTRG (A/D Hardware Trigger Select) bits (Bits 0 and 2) These bits select a hardware trigger when A/D conversion by the A/D Converter is to be started in hardware. Select one from the following hardware trigger sources: A/D0 Converter: Input event bus 2 Input event bus 3 Output event bus 3 TIN23 edge select output The contents of these bits are ignored if a software trigger is selected by ADCSEL (A/D conversion start trigger select bit). b 0 123456 b 7 ADCTRG1 ADCMSL ADCTRG0 ADCSEL ADCREQ ADCCMP ADCSTP ADCSTT 0 0000100

11-1932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) ADCMSL (A/D Scan Mode Select) bit (Bit 1) This bit selects scan mode of the A/D Converter between single-shot scan and continuous scan. Setting this bit to "0" selects single-shot scan mode, where the channels selected with the ANSCAN (A/D scan loop select) bits are sequentially A/D converted and when A/D conversion on all selected channels is completed, the conversion operation stops. Setting this bit to "1" selects continuous scan mode, where after operation in single-shot scan mode fin- ishes, A/D conversion is reexecuted beginning with the first channel and continued until stopped by setting the ADCSTP (A/D conversion stop) bit to "1". (3) ADCSEL (A/D Conversion Start Trigger Select) bit (Bit 3) This bit selects whether to use a software or hardware trigger to start A/D conversion during scan mode. If a software trigger is selected, A/D conversion is started by setting the ADCSTT (A/D conversion start) bit to "1". If a hardware trigger is selected, A/D conversion is started by the trigger source selected with the ADCTRG (hardware trigger select) bits. (4) ADCREQ (A/D Interrupt Request/DMA Transfer Request Select) bit (Bit 4) This bit selects whether to request an A/D conversion interrupt or a DMA transfer when one cycle of scan mode operation is completed. If neither an interrupt nor a DMA transfer are used, choose to request an A/D conversion interrupt and use the A/D Conversion Interrupt Control Register of the Interrupt Controller (ICU) to mask the interrupt request, or choose to request a DMA transfer and use the DMA Channel Control Register to disable DMA transfers to be performed upon completion of A/D conversion. (5) ADCCMP (A/D Conversion Completed) bit (Bit 5) This is a read-only bit, whose value when exiting the reset state is "1". This bit is "0" when the A/D Converter is performing scan mode A/D conversion and is set to "1" when single-shot scan mode finishes or continu- ous scan mode is stopped by setting the ADCSTP (A/D conversion stop) bit to "1". (6) ADCSTP (A/D Conversion Stop) bit (Bit 6) Setting this bit to "1" while the A/D Converter is performing scan mode A/D conversion causes the operation being performed to stop. This bit is effective only for scan mode operation, and does not affect single mode operation even when single and scan modes both are active during special operation mode. Operation stops immediately after writing to this bit, and the A/D conversion being performed on any chan- nel is aborted in the middle, without transferring the result to the A/D data register. If the A/D conversion start bit and A/D conversion stop bit are set to "1" at the same time, the A/D conversion stop bit has priority. (7) ADCSTT (A/D Conversion Start) bit (Bit 7) This bit is used to start scan mode operation of the A/D Converter in software. Only when a software trigger has been selected with the ADCSEL (A/D conversion start trigger select) bit, setting this bit to "1" causes A/ D conversion to start. If the A/D conversion start bit and A/D conversion stop bit are set to "1" at the same time, the A/D conversion stop bit has priority. If this bit is set to "1" again while performing scan mode conversion, special operation mode “Conversion restart” is turned on, so that scan mode operation is restarted using the contents set by A/D Scan Mode Registers 0 and 1. If this bit is set to "1" again while performing A/D conversion in single mode, special operation mode “Scan mode start after single mode execution” is turned on, so that scan mode operation starts subsequently after single mode has finished.

11-2032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11 11.2 A/D Converter Related Registers

11.2.4 A/D Scan Mode Register 1

A/D0 Scan Mode Register 1 (AD0SCM1) <Address: H’0080 0085> <Upon exiting reset: H’00> b Bit Name Function R W 8 No function assigned. Fix to "0". 00

9 ADCSPD (Note 1) 0: Normal speed R W

A/D conversion speed select bit 1: Double speed

10 ADCSHSL 0: Disable sample-and-hold R W

A/D conversion method select bit 1: Enable sample-and-hold

11 ADCSHSPD (Note 2) 0: Normal sample-and-hold R W

A/D sample-and-hold conversion speed select bit 1: Fast sample-and-hold 12–15 ANSCAN <For write> R W A/D scan loop select bit ‘B0000–1111 (channels 0–15) <For read during conversion> (i = 0) 0000: Converting ADiIN0 0001: Converting ADiIN1 0010: Converting ADiIN2 0011: Converting ADiIN3 0100: Converting ADiIN4 0101: Converting ADiIN5 0110: Converting ADiIN6 0111: Converting ADiIN7 1000: Converting ADiIN8 1001: Converting ADiIN9 1010: Converting ADiIN10 1011: Converting ADiIN11 1100: Converting ADiIN12 1101: Converting ADiIN13 1110: Converting ADiIN14 1111: Converting ADiIN15 Note 1: The A/D conversion speed is determined by a combination of ADCSPD, ADCSHSL and ADCSHSPD bits and the A/D Conversion Speed Control Register ADCVSD bit. Note 2: Setting of this bit is effective when the sample-and-hold function is enabled by ADCSHSL bit. A/D Scan Mode Register 1 is used to select operation mode, conversion speed and scan loop when the A/D Converter is operating in scan mode. The channels selected with the scan loop select bit are scanned sequen- tially beginning with channel 0 (n-channel scan). b 8 9 1 01 11 21 31 4 b 1 5 ADCSPD ADCSHSL ADCSHSPD ANSCAN 00000000

11-2132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (1) ADCSPD (A/D Conversion Speed Select) bit (Bit 9) This bit selects an A/D conversion speed when the A/D Converter is operating in scan mode. Setting this bit to "0" selects normal speed, and setting this bit to "1" selects double speed. (2) ADCSHSL (A/D Conversion Method Select) bit (Bit 10) This bit enables or disables the sample-and-hold function when the A/D Converter is operating in scan mode. Setting this bit to "0" disables the sample-and-hold function, and setting this bit to "1" enables the sample-and-hold function. (3) ADCSHSPD (A/D Sample-and-Hold Conversion Speed Select) bit (Bit 11) When the A/D Converter’s sample-and-hold function is enabled, this bit selects a conversion speed. When this bit is "0", the conversion speed is the same as normal A/D conversion speed. When this bit is "1", conversion is performed at a speed faster than normal A/D conversion speed. Setting of this bit has no effect if the sample-and-hold function is disabled by setting the ADCSHSL (A/D conversion method select) bit to "0". For details about the conversion time, see Section 11.3.4, “Calculating the A/D Conversion Time.” (4) ANSCAN (A/D Scan Loop Select) bits (Bits 12–15) The ANSCAN (A/D scan loop select) bits set the channels to be scanned during scan mode of the A/D Converter. The ANSCAN (A/D scan loop select) bits when accessed for read during scan operation serve as a status register indicating the channel being scanned. The value read from these bits during single mode is always B’0000. When accessed for read after scan operation in single-shot mode is completed, the value read from these bits indicates the channel whose A/D conversion has been finished last. If A/D conversion is stopped by setting A/D Scan Mode Register 0 ADCSTP (A/D conversion stop) bit to "1" while executing scan mode, the value read from these bits indicates the channel whose A/D conversion has been canceled. Also, if read during single mode conversion of special operation mode “Forcible single mode execution during scan mode,” the value of these bits indicates the channel whose A/D conversion has been canceled in the middle of scan. Notes: If either A/D conversion method select (ADSSHSL) bit in A/D0 Single Mode Register 1 (AD0SIM1) or A/D conversion method select (ADCSHSL) bit in A/D0 Scan Mode Register 1 (AD0SCM1) is selected as sample-and-hold enabled, both single and scan mode operate under sample-and-hold enabled mode. If either A/D conversion method select (ADSSHSL) bit in A/D0 Single Mode Register 1 (AD0SIMI1) or A/D conversion method select (ADCSHSL) bit in A/D0 Scan Mode Register 1 (AD0SCM1) is selected as sample-and-hold enabled, and A/D sample-and-hold conversion speed select (ADSSHSPD) bit in A/D0 Single Mode Register 1 (AD0SM1) or A/D sample- and-hold conversion speed select (ADCSHSPD) bit in A/D0 Scan Mode Register 1 (AD0SCM1) is selected as fast sample-and-hold, both single and scan mode operate in fast sample-and-hold conversion spped. To use single or scan mode under sample-and-hold enabled mode, make sure that A/D con- version method select (ADSSHSL) bit in A/D0 Single Mode Register 1 (AD0SIM1), A/D con- version method select (ADCSHSL) bit in A/D0 Scan Mode Register 1 (AD0SCM1), A/D sample-and-hold conversion spped select (ADSSHSPD)bit in A/D0 Single Mode Register 1 (AD0SIM1) and A/D sample-and-hold conversion speed select (ADCSHSPD) bit in A/D0 Scan Mode Register 1 (AD0SCM1) are set in the same value.

11-2232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11 11.2 A/D Converter Related Registers

11.2.5 A/D Conversion Speed Control Register

A/D0 Conversion Speed Control Register (AD0CVSCR) <Address: H’0080 0087> <Upon exiting reset: H’00> b Bit Name Function R W 8–14 No function assigned. Fix to "0". 00

15 ADCVSD (Note 1) 0: Slow mode R W

A/D conversion speed control bit 1: Fast mode Note 1: The A/D conversion speed is determined by a combination of ADCVSD bit and A/D Single Mode Register 1’s relevant bit during single mode, or a combination of ADCVSD bit and A/D Scan Mode Register 1’s relevant bit during scan mode. The A/D Conversion Speed Control Register controls the A/D conversion speed during single and scan modes of the A/D Converter. The A/D conversion speed is determined in combination with A/D Single Mode Register 1's conversion speed select bit (Double/Normal). b 8 9 1 01 11 21 31 4 b 1 5 ADCVSD 00000000

11-2332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

11.2.6 A/D Disconnection Detection Assist Function Control Register

A/D0 Disconnection Detection Assist Function Control Register (AD0DDACR) <Address: H’0080 0086> 123456 b 7b0 ADDDAEN 00 0 0 0 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 0–6 No function assigned. Fix to "0". 00

7 ADDDAEN (Note 1) 0: Disable A/D disconnection detection assist function R W

A/D disconnection detection assist function enable bit 1: Enable A/D disconnection detection assist function Note 1: For the A/D disconnection detection assist function to be enabled, the conversion start state (discharge or precharge) must be set using the A/D disconnection detection assist method select register after setting the ADDDAEN bit to "1". The A/D Disconnection Detection Assist Function Control Register is used to enable or disable the content of the A/D Disconnection Detection Assist Method Select Register. Note: If any analog input wiring is disconnected, the conversion result varies depending on the circuits fitted external to the chip. This function must be fully evaluated in the actual application system before it can be used.

11-2432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11 11.2 A/D Converter Related Registers

11.2.7 A/D Disconnection Detection Assist Method Select Register

A/D0 Disconnection Detection Assist Method Select Register (AD0DDASEL) <Address: H’0080 008A> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 ADDDA SEL0 ADDDA SEL1 ADDDA SEL2 ADDDA SEL3 ADDDA SEL4 ADDDA SEL6 ADDDA SEL7 ADDDA SEL8 ADDDA SEL9 ADDDA SEL10 ADDDA SEL11 ADDDA SEL12 ADDDA SEL13 ADDDA SEL14 ADDDA SEL15 ADDDA SEL5 <Upon exiting reset: Undefined> b Bit Name Function R W

0 ADDDASEL0 0: Discharge before conversion R W

Channel 0 disconnection detection assist method select bit 1: Precharge before conversion

1 ADDDASEL1

Channel 1 disconnection detection assist method select bit

2 ADDDASEL2

Channel 2 disconnection detection assist method select bit

3 ADDDASEL3

Channel 3 disconnection detection assist method select bit

4 ADDDASEL4

Channel 4 disconnection detection assist method select bit

5 ADDDASEL5

Channel 5 disconnection detection assist method select bit

6 ADDDASEL6

Channel 6 disconnection detection assist method select bit

7 ADDDASEL7

Channel 7 disconnection detection assist method select bit

8 ADDDASEL8

Channel 8 disconnection detection assist method select bit

9 ADDDASEL9

Channel 9 disconnection detection assist method select bit

10 ADDDASEL10

Channel 10 disconnection detection assist method select bit

11 ADDDASEL11

Channel 11 disconnection detection assist method select bit

12 ADDDASEL12

Channel 12 disconnection detection assist method select bit

13 ADDDASEL13

Channel 13 disconnection detection assist method select bit

14 ADDDASEL14

Channel 14 disconnection detection assist method select bit

15 ADDDASEL15

Channel 15 disconnection detection assist method select bit Notes: This register must always be accessed in halfwords. For these bits to be enabled, the ADDDAEN bit (A/D Disconnection Detection Assist Function Control Register bit 7) must be set to "1" before setting these bits. In order to prevent the A/D conversion result from being affected by the analog input voltage leakage from any preceding channel, the A/D Disconnection Detection Assist Method Select Register is used to control the conversion start state by selecting whether to discharge or precharge the chopper amp capacitor before start- ing regular conversion operation.

11-2532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 11.2.1 shows an example of A/D disconnection detection assist method in which the conversion start of A/D disconnection detection assist method in which the conversion start state is set to the AVSS0 side (i.e., discharge before conversion is selected). Figure 11.2.1 Example of A/D Disconnection Detection on AVCC0 Side (Precharge Before Conversion Selected) Figure 11.2.2 Example of A/D Disconnection Detection on AVSS0 Side (Discharge Before Conversion Selected) Analog input ADiINn Precharge Broken wire R C Precharge control signal Chopper amp capacitor Discharge control signal Typical external circuit (Note 1) On Off Note 1: In case of broken wire, the conversion result varies with external circuits. Therefore, careful evaluation is required before this function can be used. ADDDAEN Analog input ADiINn Discharge Broken wire RC Precharge control signal Chopper amp capacitor Discharge control signal Typical external circuit (Note 1) Off On Note 1: In case of broken wire, the conversion result varies with external circuits. Therefore, careful evaluation is required before this function can be used. ADDDAEN

11-2732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

11.2.8 A/D Successive Approximation Register

A/D0 Successive Approximation Register(AD0SAR) <Address: H’0080 0088> <Upon exiting reset: Undefined> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00 6–15 ADSAR A/D successive approximation value (A/D conversion mode)RW A/D successive approximation value/comparison value Comparison value (comparator mode) Note: This register must always be accessed in halfwords. The A/D Successive Approximation Register (ADSAR) is used to read the conversion result of the A/D Con- verter when operating in A/D conversion mode or write a comparison value when operating in comparator mode. In A/D conversion mode, the successive approximation method is used to perform A/D conversion. With this method, the reference voltage VREF0 and analog input voltages are sequentially compared bitwise beginning with the high-order bit, and the comparison result is set in the A/D Successive Approximation Register (ADSAR) bits 6–15. When the A/D conversion has finished, the value of this register is transferred to the 10-bit A/D Data Register (ADDTn) corresponding to each converted channel. When this register is accessed for read in the middle of A/D conversion, the value read from the register indicates the intermediate result of conversion. In comparator mode, this register is used to write a comparison value (the voltage with which to “comparate”). Simultaneously with a write to this register, the A/D Converter starts comparing the voltage on the analog input pin selected with A/D Single Mode Register 1 and the value written in this register. After comparate operation, the result is stored in the A/D Comparate Data Register (ADCMP). Use the calculation formula shown below to find the comparison value to be written to the A/D Successive Approximation Register (ADSAR) during comparator mode. Comparison value = H’3FF x Comparate comparison voltage [V] VREF0 input voltage [V] b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 ADSAR

11-2832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11 11.2 A/D Converter Related Registers

11.2.9 A/D Comparate Data Register

A/D0 Comparate Data Register (AD0CMP) <Address: H’0080 008C> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 AD CMP0 AD CMP1 AD CMP2 AD CMP3 AD CMP4 AD CMP6 AD CMP7 AD CMP8 AD CMP9 AD CMP10 AD CMP11 AD CMP12 AD CMP13 AD CMP14 AD CMP15 AD CMP5 <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 ADCMP0–ADCMP15 (Note 1) 0: Analog input voltage > comparison voltage R – A/D comparate result flag 1: Analog input voltage < comparison voltage Note 1: During comparator mode, the bits in this register correspond one for one to channels 0–15. Note: This register must always be accessed in halfwords. When comparator mode is selected using the A/D Single Mode Register 1 ADSMSL (A/D conversion mode select) bit, the selected analog input voltage is compared with the value written to the A/D Successive Approxi- mation Register and the result is stored in the corresponding bit of this comparate data register. The bit or flag in this register is "0" when analog input voltage > comparison voltage, or "1" when analog input voltage < comparison voltage.

11-2932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11.2.10 10-bit A/D Data Registers 10-bit A/D0 Data Register 0(AD0DT0) <Address: H’0080 0090> 10-bit A/D0 Data Register 1(AD0DT1) <Address: H’0080 0092> 10-bit A/D0 Data Register 2(AD0DT2) <Address: H’0080 0094> 10-bit A/D0 Data Register 3(AD0DT3) <Address: H’0080 0096> 10-bit A/D0 Data Register 4(AD0DT4) <Address: H’0080 0098> 10-bit A/D0 Data Register 5(AD0DT5) <Address: H’0080 009A> 10-bit A/D0 Data Register 6(AD0DT6) <Address: H’0080 009C> 10-bit A/D0 Data Register 7(AD0DT7) <Address: H’0080 009E> 10-bit A/D0 Data Register 8(AD0DT8) <Address: H’0080 00A0> 10-bit A/D0 Data Register 9(AD0DT9) <Address: H’0080 00A2> 10-bit A/D0 Data Register 10(AD0DT10) <Address: H’0080 00A4> 10-bit A/D0 Data Register 11(AD0DT11) <Address: H’0080 00A6> 10-bit A/D0 Data Register 12(AD0DT12) <Address: H’0080 00A8> 10-bit A/D0 Data Register 13(AD0DT13) <Address: H’0080 00AA> 10-bit A/D0 Data Register 14(AD0DT14) <Address: H’0080 00AC> 10-bit A/D0 Data Register 15(AD0DT15) <Address: H’0080 00AE> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 AD0DT0-AD0DT15 <Upon exiting reset: Undefined> b Bit Name Function R W 0–5 No function assigned. 0– 6–15 AD0DT0-AD0DT15 10-bit A/D conversion result R – 10-bit A/D data Note: These registers must always be accessed in halfwords. During single mode, the 10-bit A/D Data Registers are used to store the result of A/D conversion performed on each corresponding channel. During single-shot or continuous scan mode, the content of the A/D Successive Approximation Register is transferred to the 10-bit A/D Data Register for the corresponding channel when A/D conversion on each chan- nel has finished. Each 10-bit A/D Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time.

11-3032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11.2.11 8-bit A/D Data Registers 8-bit A/D0 Data Register 0(AD08DT0) <Address: H’0080 00D1> 8-bit A/D0 Data Register 1(AD08DT1) <Address: H’0080 00D3> 8-bit A/D0 Data Register 2(AD08DT2) <Address: H’0080 00D5> 8-bit A/D0 Data Register 3(AD08DT3) <Address: H’0080 00D7> 8-bit A/D0 Data Register 4(AD08DT4) <Address: H’0080 00D9> 8-bit A/D0 Data Register 5(AD08DT5) <Address: H’0080 00DB> 8-bit A/D0 Data Register 6(AD08DT6) <Address: H’0080 00DD> 8-bit A/D0 Data Register 7(AD08DT7) <Address: H’0080 00DF> 8-bit A/D0 Data Register 8(AD08DT8) <Address: H’0080 00E1> 8-bit A/D0 Data Register 9(AD08DT9) <Address: H’0080 00E3> 8-bit A/D0 Data Register 10(AD08DT10) <Address: H’0080 00E5> 8-bit A/D0 Data Register 11(AD08DT11) <Address: H’0080 00E7> 8-bit A/D0 Data Register 12(AD08DT12) <Address: H’0080 00E9> 8-bit A/D0 Data Register 13(AD08DT13) <Address: H’0080 00EB> 8-bit A/D0 Data Register 14(AD08DT14) <Address: H’0080 00ED> 8-bit A/D0 Data Register 15(AD08DT15) <Address: H’0080 00EF> <Upon exiting reset: Undefined> b Bit Name Function R W 8–15 AD08DT0-AD08DT15 8-bit A/D conversion result R – 8-bit A/D data The A/D data register is used to store the 8-bit conversion data for the A/D converter. During single mode, the 8-bit A/D Data Registers store the result of A/D conversion performed on each corre- sponding channel. During single-shot or continuous scan mode, the content of the A/D Successive Approximation Register is transferred to the 8-bit A/D Data Register for the corresponding channel when A/D conversion on each channel has finished. Each 8-bit A/D Data Register retains the last conversion result until they receive the next conver- sion result transferred, allowing the content to be read out at any time. b 8 9 1 01 11 21 31 4 b 1 5 AD08DT0-AD08DT15

11-3132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

11.3.1 How to Find Analog Input Voltages

The A/D Converter performs A/D conversion using a 10-bit successive approximation method. The equation shown below is used to calculate the actual analog input voltage from the digital value obtained by executing A/D conversion. Analog input voltage [v] = A/D conversion result x VREF input voltage [V] 1,024 The A/D Converter is a 10-bit converter, providing a resolution of 1,024 discrete voltage levels. Because the reference voltage for the A/D Converter is the voltage applied to the VREF0 pin, make sure that an exact and stable constant-voltage power supply is connected to VREF0. Also make sure the analog circuit power supply and ground (AVCC0, AVSS0) are separated from those of the digital circuit, with sufficient noise prevention measures incorporated. For details about the conversion accuracy, see Section 11.3.5, “Accuracy of A/D Conversion.” Figure 11.3.1 Outline Block Diagram of the Successive Approximation-type A/D Converter Unit ADiIN0 ADiIN1 ADiIN2 ADiIN3 ADiIN4 ADiIN5 ADiIN6 ADiIN7 Selector AVSSi VREFi 10-bit A/Di Successive Approximation Register (ADiSAR) 10-bit A/Di Data Register A/Di Comparate Data Register A/D Control Circuit 10-bit D/A Converter Comparator ADiIN8 ADiIN9 ADiIN10 ADiIN11 ADiIN12 ADiIN13 ADiIN14 ADiIN15 ADiCMP ADiDT0–15 Successive Approximation-type A/D Converter Unit AVCCi Vref VIN Sample-and-Hold Control Circuit i=0

11-3232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

11.3.2 A/D Conversion by Successive Approximation Method

The A/D Converter use an A/D conversion start trigger (software or hardware) as they start A/D conversion. Once A/D conversion begins, the following operation is automatically performed. 1. During single mode, A/D Single Mode Register 0’s A/D conversion/comparate completion bit is cleared to "0". During scan mode, A/D Scan Mode Register 0’s A/D conversion completion bit is cleared to "0". 2. The content of the A/D Successive Approximation Register is cleared to H’0000. 3. The A/D Successive Approximation Register’s most significant bit (bit 6) is set to "1". 4. The comparison voltage, Vref (Note 1), is fed from the D/A Converter into the comparator. 5. The comparison voltage, Vref, and the analog input voltage, VIN, are compared, and the comparison result will be stored in bit 6. If Vref < VIN, then bit 6 = "1" If Vref > VIN, then bit 6 = "0" 6. Operations in 3 through 5 above are executed for all other bits from bit 7 to bit 15. 7. The value stored in the A/D Successive Approximation Register by the time comparison for bit 15 has finished is held in it as the A/D conversion result. b 6 7 8 9 1 01 11 21 31 4 b 1 5 1000000000 n9 1 0 0 0 0 0 0 0 0 n 9 n 8 10000000 n9 n8 n7 n6 n5 n4 n3 n2 n1 1 2nd comparison 3rd comparison 10th comparison Conversion completed n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 Result of 1st comparison Result of 2nd comparison If Vref > VIN, then nX = 0 If Vref < VIN, then nX = 1 A/D Successive Approximation Register (ADiSAR) i = 0 Figure 11.3.2 Changes of the A/D Successive Approximation Register during A/D Convert Operation Note 1: The comparison voltage, Vref (the voltage fed from the D/A Converter into the comparator), is determined according to changes of the A/D Successive Approximation Register content. Shown below are the equations used to calculate the comparison voltage, Vref. If the A/D Successive Approximation Register content = 0 Vref [V] = 0 If the A/D Successive Approximation Register content = 1 to 1,023 Vref [V] = (reference voltage VREF0 / 1,024) × (A/D Successive Approximation Register content – 0.5)

11-3332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The conversion result is stored in the 10-bit A/D Data Register (AD0DTn) corresponding to each converted channel. There is also an 8-bit A/D Data Register (AD08DTn) for each channel, from which the 8 high-order bits of the 10-bit A/D conversion result can be read out. The following shows the procedure for A/D conversion by a successive approximation method in each operation mode. (1) Single mode The convert operation stops when comparison for the A/D Successive Approximation Register bit 15 is completed. The content (A/D conversion result) of the A/D Successive Approximation Register is trans- ferred to the 10-bit A/D Data Registers 0–15 for the converted channel. (2) Single-shot scan mode When comparison for the A/D Successive Approximation Register bit 15 on a specified channel is completed, the content of the A/D Successive Approximation Register is transferred to the corresponding 10-bit A/D Data Reg- isters 0–15, and the convert operations in steps 2 to 7 above are reexecuted for the next channel to be converted. In single-shot scan mode, the convert operation stops when A/D conversion in one specified scan loop is completed. (3) Continuous scan mode When comparison for the A/D Successive Approximation Register bit 15 on a specified channel is completed, the content of the A/D Successive Approximation Register is transferred to the corresponding 10-bit A/D Data Registers 0–15, and the convert operations in steps 2 to 7 above are reexecuted for the next channel to be converted. In continuous scan mode, the convert operation is executed continuously until scan operation is forcibly termi- nated by setting the A/D conversion stop bit (Scan Mode Register 0 bit 6) to "1".

11.3.3 Comparator Operation

When comparator mode (single mode only) is selected, the A/D Converter functions as a comparator which compares analog input voltages with the comparison voltage that is set by software. When a comparison value is written to the successive approximation register, the A/D Converter starts “comparating” the analog input voltage selected by the Single Mode Register 1 analog input select bit with the value written into the successive approximation register. Once comparate begins, the following operation is automatically executed. 1. The A/D Single Mode Register 0 A/D conversion/comparate completion bit is cleared to "0". 2. The comparison voltage, Vref (Note 1), is fed from the D/A Converter into the comparator. 3. The comparison voltage, Vref, and the analog input voltage, VIN, are compared, and the comparison result will be stored in the comparate result flag for the corresponding channel. If Vref < VIN, then the comparate result flag = 0 If Vref > VIN, then the comparate result flag = 1 4. The comparate operation is stopped after storing the comparison result. The comparison result is stored in the A/D Comparate Data Register (AD0CMP)’s corresponding bit. Note 1: The comparison voltage, Vref (the voltage fed from the D/A Converter into the comparator), is determined according to changes of the A/D Successive Approximation Register content. Shown below are the equations used to calculate the comparison voltage, Vref. If the A/D Successive Approximation Register content = 0 Vref [V] = 0 If the A/D Successive Approximation Register content = 1 to 1,023 Vref [V] = (reference voltage VREF0 / 1,024) x (A/D0 Successive Approximation Register content – 0.5)

11-3432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11 11.3 Functional Description of A/D Converter

11.3.4 Calculating the A/D Conversion Time

The A/D conversion time is expressed by the sum of dummy cycle time and actual execution cycle time. The following shows each time factor necessary to calculate the conversion time. 1. Start dummy time A time from when the CPU executed the A/D conversion start instruction to when the A/D Converter starts A/D conversion 2. A/D conversion execution cycle time If sample-and-hold is enabled, the sampling time is included in this execution cycle time. 3. Comparate execution cycle time 4. End dummy time A time from when the A/D Converter has finished A/D conversion to when the CPU can stably read out the conversion result from the A/D data register. 5. Scan to scan dummy time A time during single-shot or continuous scan mode from when the A/D Converter has finished A/D conversion on a channel to when it starts A/D conversion on the next channel. The equation to calculate the A/D conversion time is as follows: A/D conversion time = Start dummy time + Execution cycle time (+ Scan to scan dummy time + Execution cycle time + Scan to scan dummy time + Execution cycle time + Scan to scan dummy time .... + Execution cycle time) + End dummy time Note: Enclosed in ( ) are the conversion time required for the second and subsequent channels to be converted in scan mode. (1) Calculating the conversion time during A/D conversion mode The following schematically shows the method for calculating the conversion time during A/D conversion mode. Start dummy Execution cycle A/D conversion start trigger Convert operation starts Transferred to the A/D data register <Scan mode> End dummy Start dummy Execution cycle Execution cycle <Single mode> Completed Execution cycle End dummy Scan to scan dummy Scan to scan dummy (Channel 0) (Channel 1) (Last channel) Figure 11.3.3 Conceptual Diagram of A/D Conversion Time

11-3532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) Calculating the conversion time when sample-and-hold is enabled The following schematically shows the method for calculating the conversion time when the sample-and- hold function is enabled. Start dummy Execution cycle A/D conversion start trigger Convert operation starts End dummy Completed Sampling time Figure 11.3.4 Conceptual Diagram of A/D Conversion Time when Sample-and-Hold is Enabled Table 11.3.1 Conversion Clock Periods in A/D conversion Mode when Sample-and-Hold is Disabled or Normal Sample-and-Hold is Enabled (Shortest Period) Unit: BCLK Conversion speed Start dummy (Note 1)Execution cycle End dummy Scan to scan dummy (Note 2) Slow mode Normal speed 4 294 1 4 Double speed 4 168 1 4 Fast mode Normal speed 4 126 1 4 Double speed 4 84 1 4 Note 1: The same applies to both software and hardware triggers. Note 2: Only during scan mode operation, execution time per channel is added. Table 11.3.2 Conversion Clock Periods in A/D Conversion Mode when Fast Sample-and-Hold is Enabled (Shortest Period) Unit: BCLK Conversion speed Start dummy (Note 1)Execution cycle End dummy Scan to scan dummy (Note 2) Slow mode Normal speed 4 186 1 4 Double speed 4 96 1 4 Fast mode Normal speed 4 90 1 4 Double speed 4 48 1 4 Note 1: The same applies to both software and hardware triggers. Note 2: Only during scan mode operation, execution time per channel is added.

11-3632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Start dummy Execution cycle A/D conversion start trigger Convert operation starts Transferred to the comparate data register End dummy Completed Figure 11.3.5 Conceptual Diagram of A/D Conversion Time during Comparator Mode Table 11.3.3 Conversion Clock Periods during Comparator Mode (Shortest Period) Unit: BCLK Conversion speed Start dummy Execution cycle End dummy Slow mode Normal speed 4 42 1 Double speed 4 24 1 Fast mode Normal speed 4 18 1 Double speed 4 12 1 (4) A/D conversion time A total A/D conversion time in various modes are shown in the table below. Table 11.3.4 A/D Conversion Time (Total Time) Unit: BCLK Conversion start method Conversion speed Conversion mode (Note 1) Conversion time When fast sample- and-hold enabled Software and Slow Normal speed Single mode 299 191 hardware triggers Mode n-channel single-shot scan/ (298 × n)+1 (190 × n)+1 (Note 2) continuous scan mode Comparator mode 47 47 Double speed Single mode 173 101 n-channel single-shot scan/ (172 × n)+1 (100 × n)+1 continuous scan mode Comparator mode 29 29 Fast Normal speed Single mode 131 95 Mode n-channel single-shot scan/ (130 × n)+1 (94 × n)+1 continuous scan mode Comparator mode 23 23 Double speed Single mode 89 53 n-channel single-shot scan/ (88 × n)+1 (52 × n)+1 continuous scan mode Comparator mode 17 17 Note 1: For single mode and comparator mode, this indicates an A/D conversion or comparate time per channel. For single- shot and continuous scan modes, this indicates an A/D conversion time per scan loop. Note 2: This indicates a time from when a register write cycle has finished to when an A/D conversion completion interrupt request is generated, or a time from when an event bus or other MJT event has occurred to when an A/D conversion completion interrupt request is generated. (3) Calculating the conversion time during comparator mode The following schematically shows the method for calculating the conversion time during comparator mode.

11-3732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

11.3.5 Accuracy of A/D Conversion

The accuracy of the A/D Converter is indicated by an absolute accuracy. The absolute accuracy refers to a difference expressed by LSB between the output code obtained by A/D converting the analog input voltages and the output code expected for an A/D converter with ideal characteristics. The analog input voltages used during accuracy measurement are the midpoint values of the voltage width in which an A/D converter with ideal characteristics produces the same output code. If VREF = 5.12 V, for example, the width of 1 LSB for a 10-bit A/D converter is 5 mV, so that 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, 25 mV and so on are selected as midpoints of the analog input voltage. If an A/D converter is said to have the absolute accuracy of ±2 LSB, it means that if the input voltage is 25 mV, for example, the output code expected for an A/D converter with ideal characteristics is H’005, and the actual A/D conversion result is in the range of H’003 to H’007. Note that the absolute accuracy includes zero and full-scale errors. When actually using the A/D Converter, the analog input voltages are in the range of AVSS0 to VREF0. Note, however, that low VREF0 voltages result in a poor resolution. Note also that output codes for the analog input voltages from VREF0 to AVCC0 are always H’3FF. H'000 H'001 H'002 H'003 H'3FE H'3FF A/D conversion result (hexade cimal) → Analog input voltage [V] VREF 1024 × 1 Ideal A/D conversion characteristics A/D conversion characteristics with infinite resolution

0 VREF

1024 × 2 VREF 1024 × 3 VREF 1024 × 1022 VREF 1024 × 1023 VREF 1024 × 1024 Figure 11.3.6 Ideal A/D Conversion Characteristics Relative to the 10-bit A/D Converter’s Analog Input Voltages

11-3832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11 11.3 Functional Description of A/D Converter H'000 H'001 H'002 H'003 H'004 H'005 H'006 Output code (hexadecimal) → Analog input voltage [mV] Ideal A/D conversion characteristics A/D conversion characteristics with infinite resolution 5 1 01 52 02 53 03 54 04 55 05 5 H'007 H'008 H'009 H'00A H'00B +2 LSB -2 LSB Figure 11.3.7 Absolute Accuracy of A/D Converter

11-3932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 If when the A/D Converter is A/D converting a selected analog input an overvoltage exceeding the converter’s absolute maximum rating is applied to any unselected analog input, the selector for the unselected analog input is inadvertently turned on by that overvoltage. This causes current to leak to the selected analog input, and the accuracy of the A/D conversion result is thereby deteriorated. The Inflow Current Bypass Circuit fixes the internal signals of unselected analog inputs to the GND level, so that when an overvoltage is applied, this circuit lets the current flow into the GND and prevents it from leaking to the selected analog input. That way, the accuracy of the A/D conversion result is prevented from being deteriorated by overvoltages. This circuit is always active while the A/D Converter is operating, and does not need to be controlled in software. Unselected channel Selected channel To the internal logic of the A/D Converte r OFF ON OFF ON ON OFF Fixed to GND level External input latched into Assist circuit Figure 11.4.1 Configuration of the Inflow Current Bypass Circuit Figure 11.4.2 Example of an Inflow Current Bypass Circuit where AVCC0 + 0.7 V or More is Applied Unselected channel Selected channel To the internal logic of the A/D Converte r OFF ON OFF ON ON OFF Assist circuit AVCC0 + 0.7 V or more Leakage current generated Sensor input Leakage current generated Unaffected by leakage

11-4032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 11 11.4 Inflow Current Bypass Circuit Figure 11.4.3 Example of an Inflow Current Bypass Circuit where GND – 0.7 V or Less is Applied Table 11.4.1 Accuracy Errors (Actual Performance Values) when Current is Injected into AD0IN0 Note 1: The conversion accuracy is not affected unless the injection current is greater than 1 mA. Unselected channel Selected channel To the internal logic of the A/D Converter OFF ON OFF ON ON OFF Assist circuit GND - 0.7V or less Leakage current generated Sensor input Unaffected by leakage Leakage current generated AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 1 0 m A 00000 0 9 m A 00000 0 8 m A 00000 0 7 m A 00000 0 6 m A 00000 0 5 m A 00000 0 4 m A 00000 0 3 m A 00000 0 2 m A 00000 0 1 m A 00000 0 0 m A 00000 0 - 1 m A 00000 0 - 2 m A - 10000 0 - 3 m A - 10000 0 - 4 m A - 10000 0 -5mA -2 -1 0 0 0 0 -6mA -3 -1 0 0 0 0 -7mA -3 -1 0 0 0 0 -8mA -3 -1 0 0 0 0 -9mA -4 -1 0 0 0 0 -10mA -5 -1 0 0 0 0 Analog input pin Injection current (Note 1) AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 00000000 0 Accuracy error on overcurrent injected ports (Unit: LSB)

11-4132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

Forcible termination during scan operation If A/D conversion is forcibly terminated by setting the A/D conversion stop bit (AD0CSTP) to "1" during scan mode operation and the A/D data register for the channel that was in the middle of conversion is accessed for read, the read value shows the last conversion result that had been transferred to the data register before the conversion was forcibly terminated.
Modification of the A/D converter related registers If the content of any register—A/D Conversion Interrupt Control Register, Single or Scan Mode Registers or A/D Successive Approximation Register, except the A/D conversion stop bit—is modified in the middle of A/D conver- sion, the conversion result cannot be guaranteed. Therefore, do not modify the contents of these registers while A/D conversion is in progress, or be sure to restart A/D conversion if register contents have been modified.
Handling of analog input signals When using the A/D Converter with its sample-and-hold function disabled, make sure the analog input level is fixed during A/D conversion.
A/D conversion completed bit read timing To read the A/D conversion completed bit (Single Mode Register 0 bit 5 or Scan Mode Register 0 bit 5) immediately after A/D conversion has started, be sure to adjust the timing 2 BCLK periods by, for example, inserting a NOP instruction before read.
Regarding the analog input pins Figure 11.5.1 shows the internal equivalent circuit of the A/D Converter’s analog input part. To obtain accurate A/D conversion results, make sure the internal capacitor C2 of the A/D conversion circuit is charged up within a predetermined time (sampling time). To meet this sampling time requirement, it is recommended that a stabilizing capacitor C1 be connected external to the chip. The method for determining the necessary value of this external stabilizing capacitor with respect to the output impedance of an analog output device is described below. Also, an explanation is made of the case where the output impedance of an analog output device is low and the external stabilizing capacitor C1 is unnecessary.
Rated value of the absolute accuracy The rated value of the absolute accuracy is the actual performance value of the microcomputer alone, with influences of the power supply wiring and noise on the board not taken into account. When designing the application system, use caution for the board layout by, for example, separating the analog circuit power supply and ground (AVCC0, AVSS0 and VREF0) from those of the digital circuit and incorporating measures to pre- vent the analog input pins from being affected by noise, etc. from other digital signals.
Single and scan mode operation under sample-and-hold enabled mode If either A/D conversion method select (ADSSHSL) bit in A/D0 Single Mode Register 1 (AD0SIM1) or A/D conversion method select (ADCSHSL) bit in A/D0 Scan Mode Register 1 (AD0SCM1) is selected as sample- and-hold enabled, both single and scan mode operate under sample-and-hold enabled mode. If either A/D conversion method select (ADSSHSL) bit in A/D0 Single Mode Register 1 (AD0SIMI1) or A/D conversion method select (ADCSHSL) bit in A/D0 Scan Mode Register 1 (AD0SCM1) is selected as sample- and-hold enabled, and A/D sample-and-hold conversion speed select (ADSSHSPD) bit in A/D0 Single Mode Register 1 (AD0SM1) or A/D sample-and-hold conversion speed select (ADCSHSPD) bit in A/D0 Scan Mode Register 1 (AD0SCM1) is selected as fast sample-and-hold, both single and scan mode operate in fast sample-and-hold conversion spped.

11-4232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 To use single or scan mode under sample-and-hold enabled mode, make sure that A/D conversion method select (ADSSHSL) bit in A/D0 Single Mode Register 1 (AD0SIM1), A/D conversion method select (ADCSHSL) bit in A/D0 Scan Mode Register 1 (AD0SCM1), A/D sample-and-hold conversion spped select (ADSSHSPD)bit in A/D0 Single Mode Register 1 (AD0SIM1) and A/D sample-and-hold conversion speed select (ADCSHSPD) bit in A/D0 Scan Mode Register 1 (AD0SCM1) are set in the same value.

11-4332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Thus, for a 10-bit resolution A/D Converter where C2 = 2.9 pF, C1 is 0.06 µF or more. Use this value for reference when setting up C1. (b) Maximum value of the output impedance R1 when C1 is not added If the external capacitor C1 in Figure 11.5.1 is not used, examination must be made to see if the analog output device can fully charge C2 within a predetermined time. First, the equation to find i2 when C1 in Figure 11.5.1 does not exist is shown below. Cin×R1+C2(R1+R2) Cin×R1+C2(R1+R2) (a) Example for calculating the external stabilizing capacitor C1 (addition of this capacitor is recom- mended) Assuming the R1 in Figure 11.5.1 is infinitely large and that the current necessary to charge the internal capacitor C2 is supplied from C1, if the potential fluctuation, Vp, caused by capacitance division of C1 and C2 is to be within 0.1 LSB, then what amount of capacitance C1 should have. For a 10-bit A/D Converter where VREF0 is 5.12 V, 1 LSB determination voltage = 5.12 V / 1,024 = 5 mV. The potential fluctuation of 0.1 LSB means a 0.5 mV fluctuation. Vp is also obtained by the equation below: The relationship between the capacitance division of C1 and C2 and the potential fluctuation, Vp, is obtained by the equation below: C1 + C2Vp = × (E - V2) Eq. A-1 2Vp = Vp1 × < Eq. A-2i VREF0 10 × 2x x - 1 i = 0 where Vp1 = potential fluctuation in the first A/D conversion performed and x = 10 for a 10-bit resolution A/D converter When Eq. A-1 and Eq. A-2 are solved, the following results: E - V2 Vp1C1 = C2 { - 1 } Eq. A-3 2∴ C1 > C2 {10 × 2x - 1 } Eq. A-4i x - 1 i = 0 Figure 11.5.1 Internal Equivalent Circuit of the Analog Input Part Comparator Inside the microcomputer 10-bit A/D Successive Approximation Register (ADiSAR) 10-bit D/A ConverterVREF0 V2 Cin : input pin capacitance (approx. 10 pF) R2 : parasitic resistance of the selector (1-2 KΩ) C2 : comparator capacitance (approx. 2.9 pF) Selector R2i i1 i2→ ADIN n C1E C1 : parasitic capacitance of the board + stabilizing capacitance R1 : resistance of analog output device Analog output device Cin E : voltage of analog output device V2 : voltage across C2 VREF : analog reference voltage

12.1 Outline of Serial Interface

12.2 Serial Interface Related Registers

12.3 Transmit Operation in CSIO Mode

12.4 Receive Operation in CSIO Mode

12.5 Notes on Using CSIO Mode

12.6 Transmit Operation in UART Mode

12.7 Receive Operation in UART Mode

12.8 Fixed Period Clock Output Function

12.9 Notes on Using UART Mode

12-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The 32176 contains a total of four serial interface channels, SIO0–SIO3. Channels SIO0 and SIO1 can be selected between CSIO mode (clock-synchronous serial interface) and UART mode (clock-asynchronous serial interface). Channels SIO2 and SIO3 are UART mode only.

CSIO mode (clock-synchronous serial interface) Communication is performed synchronously with a transfer clock, using the same clock on both transmit and receive sides. The transfer data is 8 bits long (fixed).
UART mode (clock-asynchronous serial interface) Communication is performed at any transfer rate in any transfer data format. The transfer data length can be selected from 7, 8 and 9 bits. Channels SIO0–SIO3 each have a transmit DMA transfer and a receive DMA transfer request. These serial interfaces, when combined with the internal DMA Controller (DMAC), allow serial communication to be performed at high speed, as well as reduce the data communication load of the CPU. Serial interface is outlined below. Table 12.1.1 Outline of Serial Interface Item Description Number of channels CSIO mode/UART mode : 2 channels (SIO0, SIO1) UART only : 2 channels (SIO2, SIO3) Clock During CSIO mode : Internal clock or external clock as selected (Note 1), clock polarity can be selected During UART mode : Internal clock only Transfer mode Transmit half-duplex, receive half-duplex, transmit/receive full-duplex BRG count source f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BLCK)/256 (Note 2) (when internal clock selected) f(BCLK): Peripheral clock operating frequency Data format CSIO mode : Data length = 8 bits (fixed) Order of transfer = LSB first (fixed) UART mode : Start bit = 1 bit Character length = 7, 8 or 9 bits Parity bit = Added (odd, even) or not added Stop bit = 1 or 2 bits Order of transfer = LSB first (fixed) Baud rate CSIO mode : 152 bits/sec to 2 Mbits/sec (when f(BCLK) = 20 MHz) UART mode : 19 bits/sec to 1.25 Mbits/sec (when f(BCLK) = 20 MHz) Error detection CSIO mode : Overrun error only UART mode : Overrun, parity and framing errors (Occurrence of any of these errors is indicated by an error sum bit) Fixed period clock output function When using SIO0 and SIO1 as UART, this function outputs a divided-by-2 BRG clock from the SCLK pin. Note 1: The maximum input frequency of an external clock during CSIO mode is f(BCLK)/16. Note 2: If f(BCLK) is selected as the count source, the BRG set value is subject to limitations.

12-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 12.1.2 Interrupt Generation Functions of Serial Interface Serial Interface Interrupt Request Source ICU Interrupt Sources SIO0 transmit buffer empty or transmission finished SIO0 transmit interrupt SIO0 reception finished or receive error SIO0 receive interrupt SIO1 transmit buffer empty or transmission finished SIO1 transmit interrupt SIO1 reception finished or receive error SIO1 receive interrupt SIO2 transmit buffer empty or transmission finished SIO2,3 transmit/receive interrupt (group interrupt) SIO2 reception finished or receive error SIO2,3 transmit/receive interrupt (group interrupt) SIO3 transmit buffer empty or transmission finished SIO2,3 transmit/receive interrupt (group interrupt) SIO3 reception finished or receive error SIO2,3 transmit/receive interrupt (group interrupt) Note: The transmission-finished interrupt is effective when the internal clock is selected in UART or CSIO mode. Table 12.1.3 DMA Transfer Request Generation Functions of Serial Interface Serial Interface DMA Transfer Request DMAC Input Channels SIO0 transmit buffer empty DMA3 SIO0 reception finished DMA4 SIO1 transmit buffer empty DMA6 SIO1 reception finished DMA3 SIO2 transmit buffer empty DMA7 SIO2 reception finished DMA5 SIO3 transmit buffer empty DMA9 SIO3 reception finished DMA8

12-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SCLKI0/SCLKO0 BCLK, BCLK/8, BCLK/32, BCLK/256 Baud Rate Generator (BRG) BCLK (set value + 1) Internal data b us CSIO mode When internal clock selected CSIO mode UART mode When internal clock selected Clock Divider RXD0 TXD0 Receive interrupt request Transmit/ Receive Control Circuit SIO0 Transmit Buffer Register SIO0 Transmit Shift Register Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request To DMA3SIO0 Receive Shift Register SIO0 Receive Buffer Register When external clock selected When UART mode selected Notes: When f(BCLK) is selected as BRG count source, the BRG set value is subjected to limitations. SIO2 and SIO3 do not have the SCLKI/SCLKO function. SCLKI1/SCLKO1 To DMA6 To the Interrupt Controller (ICU) SIO0 SIO1 SIO2 SIO3 RXD1 TXD1 Transmit/ Receive Control Circuit SIO1 Transmit Shift Register SIO1 Receive Shift Register To DMA7RXD2 TXD2 Transmit/ Receive Control Circuit SIO2 Transmit Shift Register SIO2 Receive Shift Register To DMA9 RXD3 TXD3 Transmit/ Receive Control Circuit SIO3 Transmit Shift Register SIO3 Receive Shift Register Receive interrupt request Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request Receive interrupt request Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request Receive interrupt request Receive DMA transfer request Transmit interrupt request Transmit DMA transfer request To the Interrupt Controller (ICU) To DMA8 To DMA5 To DMA3 To DMA4 To the Interrupt Controller (ICU) Figure 12.1.1 Block Diagram of SIO0–SIO3

12-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Shown below is a serial interface related register map. Serial Interface Related Register Map Address +0 address +1 address See b0 b7 b8 b15 pages H'0080 0100 SIO23 Interrupt Request Status Register SIO03 Interrupt Request Mask Register 12-9 (SI23STAT) (SI03MASK) 12-10 H'0080 0102 SIO03 Interrupt Source Select Register (Use inhibited area) 12-11 (SI03SEL) | (Use inhibited area) H'0080 0110 SIO0 Transmit Control Register SIO0 Transmit/Receive Mode Register 12-13 (S0TCNT) (S0MOD) 12-14 H'0080 0112 SIO0 Transmit Buffer Register 12-17 (S0TXB) H'0080 0114 SIO0 Receive Buffer Register 12-18 (S0RXB) H'0080 0116 SIO0 Receive Control Register SIO0 Baud Rate Register 12-19 (S0RCNT) (S0BAUR) 12-21 H'0080 0118 SIO0 Special Mode Register (Use inhibited area) 12-23 (S0SMOD) | (Use inhibited area) H'0080 0120 SIO1 Transmit Control Register SIO1 Transmit/Receive Mode Register 12-13 (S1TCNT) (S1MOD) 12-14 H'0080 0122 SIO1 Transmit Buffer Register 12-17 (S1TXB) H'0080 0124 SIO1 Receive Buffer Register 12-18 (S1RXB) H'0080 0126 SIO1 Receive Control Register SIO1 Baud Rate Register 12-19 (S1RCNT) (S1BAUR) 12-21 H'0080 0128 SIO1 Special Mode Register (Use inhibited area) 12-23 (S1SMOD) | (Use inhibited area) H'0080 0130 SIO2 Transmit Control Register SIO2 Transmit/Receive Mode Register 12-13 (S2TCNT) (S2MOD) 12-14 H'0080 0132 SIO2 Transmit Buffer Register 12-17 (S2TXB) H'0080 0134 SIO2 Receive Buffer Register 12-18 (S2RXB) H'0080 0136 SIO2 Receive Control Register SIO2 Baud Rate Register 12-19 (S2RCNT) (S2BAUR) 12-21 | (Use inhibited area) H'0080 0140 SIO3 Transmit Control Register SIO3 Transmit/Receive Mode Register 12-13 (S3TCNT) (S3MOD) 12-14 H'0080 0142 SIO3 Transmit Buffer Register 12-17 (S3TXB) H'0080 0144 SIO3 Receive Buffer Register 12-18 (S3RXB) H'0080 0146 SIO3 Receive Control Register SIO3 Baud Rate Register 12-19 (S3RCNT) (S3BAUR) 12-21

12-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.2.1 SIO Interrupt Related Registers

The SIO interrupt related registers are used to control the interrupt request signals output from SIO to the Interrupt Controller (ICU), as well as select the source of each interrupt request. (1) Interrupt request status bit This status bit is used to determine whether an interrupt is requested. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this bit is unaffected by the interrupt request mask bit, it can also be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "1" to enable interrupt requests or "0" to disable interrupt requests. Figure 12.2.1 Interrupt Request Status and Mask Registers To the Interrupt Controller Interrupt request from each peripheral function Interrupt request status Data bus Set Group interrupt Interrupt request enable clear F/F F/F Data=0

12-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.2.2 Example for Clearing Interrupt Request Status b4 5 b7 Interrupt request status Initial state Bit 6 event occurs Interrupt request Bit 4 event occurs Only bit 6 cleared Bit 4 data retained b4 5 b7 1 1 0 1 Write to the interrupt request status Example for clearing interrupt request status 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 Program example ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */ To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1: ISTAT1 (0x02 bit) To clear an interrupt request status, always be sure to write 1 to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. b4 5 6 b7 Interrupt request status Bit 6 event occurs Bit 4 event occurs Only bit 6 cleared Bit 4 also cleared 0 0 1 0 1 0 1 0 0 0 0 0 Read 0 0 1 0 0 0 0 0 Clear bit 6 (ANDing with 1101) Write ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */

12-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Receive DMA transfer request RFIN (Reception Finished bit) Note: No reception-finished DMA transfer requests are generated if a receive error occurs. Figure 12.2.4 Reception-finished DMA Transfer Request (3) Selecting the source of an interrupt request The interrupt request signals sent from each SIO to the Interrupt Controller (ICU) are classified into transmit interrupts and receive interrupts. Transmit interrupt requests can be generated when the transmit buffer is empty or transmission is finished, and the receive interrupt requests can be generated when reception is finished or an receive error is detected, as selected by the Interrupt Source Select Register (SI03SEL). Notes: No interrupt request signals are generated unless interrupts are generated by the SIO Interrupt Request Mask Register after enabling the TEN (Transmit Enable) bit or REN (Receive Enable) bit for the corresponding SIO. SIO2 and SIO3 together comprise one interrupt group. The transmission-finished interrupt is effective when the internal clock is selected in UART or CSIO mode. (4) Notes on using transmit interrupts When the interupt request is enable in SIO Interrupt Request Mask Register and the transmit buffer empty interrupt is selected in SIO Interrupt Request Source Slect Register, a transmit interrupt request is gener- ated upon enabling the corresponding TEN (Transmit Enable) bit. (5) About DMA transfer requests from SIO Each SIO can generate a transmit DMA transfer and a reception-finished DMA transfer request. These DMA transfer requests can be generated by enabling each SIO’s corresponding TEN (Transmit Enable) bit or REN (Receive Enable) bit. When using DMA transfers to communicate with external devices, be sure to set the DMA Controller (DMAC) before enabling the TEN or REN bit. No reception-finished DMA transfer requests are generated if a receive error occurs.

Transmit DMA transfer request Generated when the transmit buffer is empty and the TEN bit is enabled. TEN (Transmit Enable bit) TBE (Transmit Buffer Empty bit) Transmit DMA transfer request Figure 12.2.3 Transmit DMA Transfer Request
Reception-finished DMA transfer request A DMA transfer request is generated when the receive buffer is filled.

12-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SIO23 Interrupt Request Status Register (SI23STAT) <Address: H’0080 0100> <Upon exiting reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00

4 IRQT2 0: Interrupt not requested R (Note 1)

SIO2 transmit interrupt request status bit 1: Interrupt requested

5 IRQR2 0: Interrupt not requested R (Note 1)

SIO2 receive interrupt request status bit 1: Interrupt requested

6 IRQT3 0: Interrupt not requested R (Note 1)

SIO3 transmit interrupt request status bit 1: Interrupt requested

7 IRQR3 0: Interrupt not requested R (Note 1)

SIO3 receive interrupt request status bit 1: Interrupt requested Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. The register indicates the transmit/receive interrupt requests from SIO2 and SIO3. [Setting the interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the interrupt request status bit] This bit is cleared by writing "0" in software. Note: If the status bit is set in hardware at the same time it is cleared in software, the former has priority and the status bit is set. When writing to the SIO Interrupt Request Status Register, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write. b 0 123456 b 7 IRQT2 IRQR2 IRQT3 IRQR3 00000000

12-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SIO03 Interrupt Request Mask Register (SI03MASK) <Address: H’0080 0101> <Upon exiting reset: H’00> b Bit Name Function R W

8 T0MASK 0: Mask (disable) interrupt request R W

SIO0 transmit interrupt request mask bit 1: Enable interrupt request

9 R0MASK 0: Mask (disable) interrupt request R W

SIO0 receive interrupt request mask bit 1: Enable interrupt request

10 T1MASK 0: Mask (disable) interrupt request R W

SIO1 transmit interrupt request mask bit 1: Enable interrupt request

11 R1MASK 0: Mask (disable) interrupt request R W

SIO1 receive interrupt request mask bit 1: Enable interrupt request

12 T2MASK 0: Mask (disable) interrupt request R W

SIO2 transmit interrupt request mask bit 1: Enable interrupt request

13 R2MASK 0: Mask (disable) interrupt request R W

SIO2 receive interrupt request mask bit 1: Enable interrupt request

14 T3MASK 0: Mask (disable) interrupt request R W

SIO3 transmit interrupt request mask bit 1: Enable interrupt request

15 R3MASK 0: Mask (disable) interrupt request R W

SIO3 receive interrupt request mask bit 1: Enable interrupt request The register enables or disables the interrupt requests generated by each SIO. Interrupt requests from any SIO are enabled by setting its corresponding interrupt request mask bit to "1". b 8 9 1 01 11 21 31 4 b 1 5 T0MASK R0MASK T1MASK R1MASK T2MASK R2MASK T3MASK R3MASK 00000000

12-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 SIO03 Interrupt Request Source Select Register (SI03SEL) <Address: H’0080 0102> <Upon exiting reset: H’00> b Bit Name Function R W

0 IST0 0: Transmit buffer empty interrupt R W

SIO0 transmit interrupt request source select bit 1: Transmission finished interrupt

1 IST1 0: Transmit buffer empty interrupt R W

SIO1 transmit interrupt request source select bit 1: Transmission finished interrupt

2 IST2 0: Transmit buffer empty interrupt R W

SIO2 transmit interrupt request source select bit 1: Transmission finished interrupt

3 IST3 0: Transmit buffer empty interrupt R W

SIO3 transmit interrupt request source select bit 1: Transmission finished interrupt

4 ISR0 0: Reception finished interrupt R W

SIO0 receive interrupt request source select bit 1: Receive error interrupt

5 ISR1 0: Reception finished interrupt R W

SIO1 receive interrupt request source select bit 1: Receive error interrupt

6 ISR2 0: Reception finished interrupt R W

SIO2 receive interrupt request source select bit 1: Receive error interrupt

7 ISR3 0: Reception finished interrupt R W

SIO3 receive interrupt request source select bit 1: Receive error interrupt The register selects the source of interrupt requests generated by each SIO when transmit or receive operation is completed. (1) SIOn transmit interrupt source select bit [When set to "0"] The transmit buffer empty interrupt is selected. A transmit buffer empty interrupt request is generated when data is transferred from the transmit buffer register to the transmit shift register. Also, a transmit buffer empty interrupt request is generated when the TEN (Transmit Enable) bit is set to "1" (interrupt enabled). [When set to "1"] The transmission finished (transmit shift buffer empty) interrupt is selected. A transmission finished interrupt request is generated when all of the data in the transmit shift register has been transferred. Note: Do not select the transmission finished interrupt when an external clock is selected in CSIO mode. (2) SIOn receive interrupt request source select bit [When set to "0"] The reception finished (receive buffer full) interrupt is selected. A reception finished interrupt request is also generated when a receive error (except overrun error) occurs. [When set to "1"] The receive error interrupt is selected. Following types of errors constitute a receive error: CSIO mode: Overrun error UART mode: Overrun, parity and framing errors b 0 123456 b 7 IST0 IST1 IST2 IST3 ISR0 ISR1 ISR2 ISR3 00000000

12-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.2.5 Block Diagram of SIO2,3 Transmit/Receive Interrupt Requests F/F F/F R3MASK IRQR3 F/F F/F T3MASK IRQT3 F/F F/F R2MASK IRQR2 F/F F/F T2MASK IRQT2 b15 b14 b13 b12 Data bus SIO2, 3 transmit/receive interrupt requests(Level) 4-source inputs <SI23STAT : H'0080 0100> <SI03MASK : H'0080 0101> F/F SIO2 reception finished SIO2 receive error ISR2 F/F SIO2 transmit buffer empty SIO2 transmission finished IST2 F/F SIO3 transmit buffer empty SIO3 transmission finished IST3 F/F SIO3 reception finished SIO3 receive error ISR3 <SI03SEL : H'0080 0102>

12-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.2.2 SIO Transmit Control Registers

SIO0 Transmit Control Register (S0TCNT) <Address: H'0080 0110> SIO1 Transmit Control Register (S1TCNT) <Address: H'0080 0120> SIO2 Transmit Control Register (S2TCNT) <Address: H'0080 0130> SIO3 Transmit Control Register (S3TCNT) <Address: H'0080 0140> <Upon exiting reset: H’12> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00 2, 3 CDIV b2 b3 R W BRG count source select bit 0 0: Select f(BCLK) 0 1: Select f(BCLK) divided by 8 1 0: Select f(BCLK) divided by 32 1 1: Select f(BCLK) divided by 256 4 No function assigned. Fix to "0". 00

5 TSTAT 0: Transmission stopped and no data in transmit buffer register R –

Transmit status bit 1: Transmitting now or data present in transmit buffer register

6 TBE 0:Data present in transmit buffer register R –

Transmit buffer empty bit 1: No data in transmit buffer register

7 TEN 0: Disable transmission R W

Transmit enable bit 1: Enable transmission b 0 123456 b 7 CDIV TSTAT TBE TEN 00010010 (1) CDIV (baud rate generator count source select) bits (Bits 2–3) These bits select the count source for the Baud Rate Generator (BRG). Note: When using internal clock (the internal clock CSIO mode) and selecting f(BCLK) as a BRG count source, set the BRG value for the transfer rate not to exceed 2Mbits / second. (2) TSTAT (Transmit Status) bit (Bit 5) [Set condition] This bit is set to "1" by a write to the transmit buffer register while transmission is enabled. [Clear condition] This bit is cleared to "0" when transmission is idle (no data in the transmit shift register) and no data exists in the transmit buffer register. This bit is also cleared by clearing the transmit enable bit. (3) TBE (Transmit Buffer Empty) bit (Bit 6) [Set condition] This bit is set to "1" when data is transferred from the transmit buffer register to the transmit shift register and the transmit buffer register is thereby emptied. This bit is also set by clearing the transmit enable bit to "0". [Clear condition] This bit is cleared to "0" by writing data to the lower byte of the transmit buffer register while transmis- sion is enabled (TEN = "1"). (4) TEN (Transmit Enable) bit (Bit 7) Transmission is enabled by setting this bit to "1" and disabled by clearing this bit to "0". If this bit is cleared to "0" while transmitting data, the transmit operation stops.

12-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.2.3 SIO Transmit/Receive Mode Registers

SIO0 Transmit/Receive Mode Register (S0MOD) <Address: H'0080 0111> SIO1 Transmit/Receive Mode Register (S1MOD) <Address: H'0080 0121> SIO2 Transmit/Receive Mode Register (S2MOD) <Address: H'0080 0131> SIO3 Transmit/Receive Mode Register (S3MOD) <Address: H'0080 0141> <Upon exiting reset: H’00> b Bit Name Function R W 8–10 SMOD b8 b9 b10 R W Serial interface mode select bit 0 0 0 : 7-bit UART (Note 1) 0 0 1 : 8-bit UART 0 1 0 : 9-bit UART 0 1 1 : 9-bit UART 1 0 0 : 8-bit clock-synchronous serial interface 1 0 1 : 8-bit clock-synchronous serial interface 1 1 0 : 8-bit clock-synchronous serial interface 1 1 1 : 8-bit clock-synchronous serial interface

11 CKS 0: Internal clock R W

Internal/external clock select bit 1: External clock (Note 4) (Note 2)

12 STB 0: One stop bit R W

Stop bit length select bit, UART mode only 1: Two stop bits (Note 3)

13 PSEL 0: Odd parity R W

Odd/even parity select bit, UART mode only 1: Even parity (Note 3)

14 PEN 0: Disable parity R W

Parity enable bit, UART mode only 1: Enable parity (Note 3)

15 SEN 0: Disable sleep function R W

Sleep select bit, UART mode only 1: Enable sleep function (Note 3) Note 1: For SIO2 and 3, bit 8 is fixed to "0" in hardware. This bit cannot be set to "1" in software (to select clock-synchronous serial interface). Note 2: Has no effect when UART mode selected. Note 3: Bits 12–15 have no effect during clock-synchronous mode. Note 4:The maximum frequency of the SCLKI pin input clock is f(BCLK)/16 when external clock is selected in CSIO mode. b 8 9 1 01 11 21 31 4 b 1 5 SMOD CKS STB PSEL PEN SEN 00000000

12-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The SIO Transmit/Receive Mode Registers consist of bits to set the serial interface operation mode, data format and the functions used during communication. The SIO Transmit/Receive Mode Registers must always be set before the serial interface starts operating. To change register settings after the serial interface starts sending or receiving data, first confirm that transmit and receive operations have finished and then disable transmit/receive operations (by clearing the SIO Transmit Control Register transmit enable bit and SIO Receive Control Register receive enable bit to "0") before making changes. (1) SMOD (Serial Interface Mode Select) bits (Bits 8–10) These bits select the operation mode of serial interface. (2) CKS (Internal/External Clock Select) bit (Bit 11) This bit is effective when CSIO mode is selected. Setting this bit has no effect when UART mode is selected, in which case the serial interface is clocked by the internal clock. (3) STB (Stop Bit Length Select) bit (Bit 12) This bit is effective during UART mode. Use this bit to select the stop bit length that indicates the end of data to transmit. Setting this bit to "0" selects one stop bit, and setting this bit to "1" selects two stop bits. During clock-synchronous mode, the content of this bit has no effect. (4) PSEL (Odd/Even Parity Select) bit (Bit 13) This bit is effective during UART mode. When parity is enabled (bit 14 = "1"), use this bit to select the parity attribute (whether odd or even). Setting this bit to "0" selects an odd parity, and setting this bit to "1" selects an even parity. When parity is disabled (bit 14 = "0") or during clock-synchronous mode, the content of this bit has no effect. (5) PEN (Parity Enable) bit (Bit 14) This bit is effective during UART mode. When this bit is set to "1", a parity bit is added immediately after the data bits of the transmit data, and the received data is checked for parity. The parity bit added to the transmit data is automatically determined to be "0" or "1" so that the attribute (odd/even) derived by adding the number of 1’s in data bits and the content of the parity bit agrees with one that was selected with the odd/even parity select bit (bit 13). Figure 12.2.6 shows an example of a data format when parity is enabled. (6) SEN (Sleep Select) bit (Bit 15) This bit is effective during UART mode. If the sleep function is enabled by setting this bit to "1", data is latched into the UART Receive Buffer Register only when the most significant bit (MSB) of the received data is "1".

12-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 When transmitting If the attribute (odd/even) represented by the number of 1's in data bits agrees with the selected parity attribute, a parity bit "0" is added. If the attribute (odd/even) represented by the number of 1's in data bits does not agree with the selected parity attribute, a parity bit "1" is added. b7 b6 b5 b4 b3 b2 b1 b0 PAR SPST Attribute derived from b7 + b6 + ... + b0 If it agrees with the selected parity attribute, PAR = "0" is added. If it does not agree with the selected parity attribute, PAR = "1" is added. LSB MSB When receiving The received data is checked to see if the number of 1's included in its data and parity bits agrees with the parity attribute (known as parity check). b7 b6 b5 b4 b3 b2 b1 b0 PAR SPST LSB MSB If the result of b7 + b6 + ... + b0 + PAR does not agree with the selected parity attribute, a parity error is assumed Notes : Shown above is an example of a data format in 8-bit UART mode. The data bit numbers (bn) above indicate bit numbers in a data list, and not the register bit numbers (bn). b8 b7 b6 b5 b4 b3 b2 b1 PAR SPST b0 9-bit UART mode b7 b6 b5 b4 b3 b2 b1 b0 PAR SPST 8-bit UART mode b6 b5 b4 b3 b2 b1 b0 PAR SPST (Note 1) 7-bit UART mode b7 b6 b5 b4 b3 b2 b1 Clock-synchronous mode b0 Note 1: Whether or not to add a parity bit is selectable. Note 2: The stop bit can be chosen to be one bit or two bits long. Direction of transfer ST : Start bit PAR : Parity bit : One frame equivalent b : Data bits SP : Stop bit (Note 2) (Note 1) (Note 1) (Note 2) (Note 2) Figure 12.2.6 Data Format When Parity is Enabled

12-1732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 TDATA

12.2.4 SIO Transmit Buffer Registers

SIO0 Transmit Buffer Register (S0TXB) <Address: H'0080 0112> SIO1 Transmit Buffer Register (S1TXB) <Address: H'0080 0122> SIO2 Transmit Buffer Register (S2TXB) <Address: H'0080 0132> SIO3 Transmit Buffer Register (S3TXB) <Address: H'0080 0142> <Upon exiting reset: Undefined> b Bit Name Function R W 0–6 No function assigned. Fix to "0". ?0 7–15 TDATA Transmit data is set in these bits. ? W Transmit data The SIO Transmit Buffer Registers are used to set transmit data. These registers are a write-only register, and the contents of these registers cannot be read out. Data must be LSB-aligned when set in these registers. Therefore, write transmit data to bits 9–15 for the 7-bit data format (UART mode only), bits 8–15 for the 8-bit data format, or bits 7–15 for the 9-bit data format (UART mode only). Before setting transmit data in these registers, enable the Transmit Control Register TEN (Transmit Enable) bit by setting it to "1". Writing data to these registers while the TEN bit is disabled (cleared to "0") has no effect. When data is written to the SIO Transmit Buffer Register while transmission is enabled, the data is transferred from that register to the SIO Transmit Shift Register, upon which the serial interface starts sending data. Note: For the 7-bit and 8-bit data formats, the register can be accessed bytewise.

12-1832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.2.5 SIO Receive Buffer Registers

SIO0 Receive Buffer Register (S0RXB) <Address: H'0080 0114> SIO1 Receive Buffer Register (S1RXB) <Address: H'0080 0124> SIO2 Receive Buffer Register (S2RXB) <Address: H'0080 0134> SIO3 Receive Buffer Register (S3RXB) <Address: H'0080 0144> <Upon exiting reset: Undefined> b Bit Name Function R W 0–6 No function assigned. 0– 8–15 RDATA Received data is stored in these bits. R – Received data The SIO Receive Buffer Registers are used to store the received data. When the serial interface has finished receiving data, the content of the SIO Receive Shift Register is transferred to the SIO Receive Buffer Register. These registers are a read-only register. For the 7-bit data format (UART mode only), data is set in bits 9–15, with bits 8 and 7 always set to "0". For the 8-bit data format, data is set in bits 8–15, with bit 7 always set to "0". When reading the content of the SIO Receive Buffer Register after reception is completed, if the serial interface finishes receiving the next data before the previous data is not read out, an overrun error occurs and the subsequent received data are not transferred to the Receive Buffer Register. To restart normal receive operation, clear the Receive Control Register REN (Receive Enable) bit to "0". Note: For the 7-bit and 8-bit data formats, the register can be accessed bytewise. b 0 123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 RDATA

12-1932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.2.6 SIO Receive Control Registers

SIO0 Receive Control Register (S0RCNT) <Address: H'0080 0116> SIO1 Receive Control Register (S1RCNT) <Address: H'0080 0126> SIO2 Receive Control Register (S2RCNT) <Address: H'0080 0136> SIO3 Receive Control Register (S3RCNT) <Address: H'0080 0146> <Upon exiting reset: H’00> b Bit Name Function R W 0 No function assigned. Fix to "0". 00

1 RSTAT 0: Reception stopped R –

Receive status bit 1: Reception in progress

2 RFIN 0: No data in receive buffer register R –

Reception finished bit 1: Data present in receive buffer register

3 REN 0: Disable reception R W

Receive enable bit 1: Enable reception

4 OVR 0: No overrun error R –

Overrun error bit 1: Overrun error occurred

5 PTY 0: No parity error R –

Parity error bit, UART mode only 1: Parity error occurred

6 FLM 0: No framing error R –

Framing error bit, UART mode only 1: Framing error occurred

7 ERS 0: No error R –

Error sum bit 1: Error occurred b 0 123456 b 7 RSTAT RFIN REN OVR PTY FLM ERS 00000000 (1) RSTAT (Receive Status) bit (Bit 1) [Set condition] This bit is set to "1" by a start of receive operation. When this bit = "1", the serial interface is receiving data. [Clear condition] This bit is cleared to "0" upon completion of receive operation or by clearing the REN (Receive Enable) bit. (2) RFIN (Reception Finished) bit (Bit 2) [Set condition] This bit is set to "1" when all data bits have been received in the Receive Shift Register and whose content is transferred to the Receive Buffer Register. [Clear condition] This bit is cleared to "0" by reading out the lower byte of the Receive Buffer Register or by clearing the REN (Receive Enable) bit. However, if an overrun error occurs, this bit cannot be cleared by reading out the lower byte of the Receive Buffer Register. In this case, clear REN (Receive Enable) bit to "0". (3) REN (Receive Enable) bit (Bit 3) Reception is enabled by setting this bit to "1", and is disabled by clearing this bit to "0", in which case the receiver unit is initialized. Accordingly, the receive status and reception finished flags, as well as the overrun error, framing error, parity error and error sum flags all are cleared. The receive operation stops if the Receive Enable bit is cleared to "0" while receiving data.

12-2032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (4) OVR (Overrun Error) bit (Bit 4) [Set condition] This bit is set to "1" when all bits of the next received data have been set in the Receive Shift Register while the Receive Buffer Register still contains the previous received data. In this case, the received data is not stored in the Receive Buffer Register. Although receive operation continues even when the overrun error flag = "1", the received data is not stored in the Receive Buffer Register. This error bit must be cleared before normal reception can be restarted. [Clear condition] This bit is cleared to "0" by only clearing the REN (Receive Enable) bit. (5) PTY (Parity Error) bit (Bit 5) This bit is effective in only UART mode. It is fixed to "0" during CSIO mode. [Set condition] The PTY (Parity Error) bit is set to "1" when the SIO Transmit/Receive Mode Register PEN (Parity Enable/Disable) bit is enabled and the parity (even or odd) of the received data does not agree with one that was set by the said register’s PSEL (Parity Select) bit. [Clear condition] The PTY bit is cleared to "0" by reading out the lower byte of the SIO Receive Buffer Register or by clearing the SIO Receive Control Register REN (Receive Enable) bit. However, if an overrun error occurs, this bit cannot be cleared by reading out the lower byte of the Receive Buffer Register. In this case, clear the REN (Receive Enable) bit. (6) FLM (Framing Error) bit (Bit 6) This bit is effective in only UART mode. It is fixed to "0" during CSIO mode. [Set condition] The FLM (Framing Error) bit is set to "1" when the number of received bits does not agree with one that was set by the SIO Transmit/Receive Mode Register. [Clear condition] The FLM bit is cleared to "0" by reading out the lower byte of the SIO Receive Buffer Register or by clearing the SIO Receive Control Register REN (Receive Enable) bit. However, if an overrun error occurs, this bit cannot be cleared by reading out the lower byte of the Receive Buffer Register. In this case, clear the REN (Receive Enable) bit to "0". (7) ERS (Error Sum) bit (Bit 7) [Set condition] This flag is set to "1" when any of overrun, framing or parity errors is detected at completion of recep- tion. [Clear condition] If the detected error was an overrun error, this flag is cleared by clearing the REN (Receive Enable) bit to "0". Otherwise, this flag is cleared by reading out the lower byte of the SIO Receive Buffer Register or by clearing the SIO Receive Control Register REN (Receive Enable) bit.

12-2132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.2.7 SIO Baud Rate Registers

SIO0 Baud Rate Register (S0BAUR) <Address: H'0080 0117> SIO1 Baud Rate Register (S1BAUR) <Address: H'0080 0127> SIO2 Baud Rate Register (S2BAUR) <Address: H'0080 0137> SIO3 Baud Rate Register (S3BAUR) <Address: H'0080 0147> <Upon exiting reset: Undefined> b Bit Name Function R W 8–15 BRG Set a baud rate divide value R W Baud rate divide value (1) BRG (baud rate divide value) (Bits 8–15) The SIO Baud Rate Registers are used to set a baud rate divide value, so that the baud rate count source selected by SIO Mode Register is divided by (BRG set value + 1). Because the BRG value initially is undefined, be sure to set the divide value before the serial interface starts operating. The value written to the BRG during transmit/receive operation takes effect in the next cycle after the BRG counter has finished counting. When using the internal clock (to output the SCLKO signal) in CSIO mode, the serial interface divides the internal BCLK using a clock divider and then divides the resulting clock by (BRG set value + 1) and further by 2, thereby generating a transmit/receive shift clock. When using an external clock in CSIO mode, the serial interface does not use the BRG. (Transmit/receive operations are synchronized to the externally supplied clock.) During UART mode, the serial interface divides the internal BCLK using a clock divider and then divides the resulting clock by (BRG set value + 1) and further by 16, thereby generating a transmit/receive shift clock. When using SIO0 or SIO1 in UART mode, set the relevant port (P84 or P87) to function as an SCLKO pin, so that a BRG output clock divided by 2 can be output from that SCLKO pin. When using the internal clock (internally clocked CSIO mode), if f(BCLK) is selected as the BRG count source, make sure the transfer rate does not exceed 2 Mbits/second during CSIO mode. The baud rate register set value when internal clock CSIO mode is selected can be calcurated by the following equations.

CSIO Mode f(BCLK)SIO Baud Rate Register Set Value = Baud Rate × Clock Divider Divide Value × 2 -1
UART Mode f(BCLK)SIO Baud Rate Register Set Value = Baud Rate × Clock Divider Divide Value × 16 -1 Clock divider divide value: selected among 1, 8, 32 and 256 by setting the SIO Transmit Control Register BRG count source select bit. b 8 9 1 01 11 21 31 4 b 1 5 BRG

12-2232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 12.2.1 Example Settings of the SIO Baud Rate Register (CSIO Mode) items When f(BCLK) = 16MHz When f(BCLK) = 20MHz Baud Clock divider BRG Actual baud rate Clock divider BRG Actual baud rate rate divide value set [bps] divide value set [bps] [bps] [divided-by n] value [divided-by n] value 250 256 124 250.00 256 155 250.40 500 256 62 496.03 256 77 500.80 1000 32 249 1000.00 256 38 1001.60 2500 32 99 2500.00 32 124 2500.00 5000 8 199 5000.00 8 249 5000.00 10000 8 99 10000.00 8 124 10000.00 25000 8 39 25000.00 8 49 25000.00 50000 1 159 50000.00 1 199 50000.00 100000 1 79 100000.00 1 99 100000.00 250000 1 31 250000.00 1 39 250000.00 500000 1 15 500000.00 1 19 500000.00 1000000 1 7 1000000.00 1 9 1000000.00 2000000 1 3 2000000.00 1 4 2000000.00 2500000 - - - 1 3 2500000.00 Notes: This does not mean that the communication at the above baud rates is guaranteed. Careful consideration and inspection under your environment are required before use. Select divide-by value of clock divider in the CDIV bit of SIOn transmit control register (SnTCNT). Set BRG set value in the SIOn baud rate register (SnBAUR). Table 12.2.2 Example Settings of the SIO Baud Rate Register (UART Mode) items When f(BCLK) = 16MHz When f(BCLK) = 20MHz Baud Clock divider BRGA margin Actual baud rate Clock divider BRG A marginActual baud rate rate divide value set of error [bps] divide value set of error [bps] [bps] [divided-by n] value (%) [divided-by n] value (%) 300 32 103 0.16 300.48 32 129 0.16 300.48 600 32 51 0.16 600.96 32 64 0.16 600.96 1200 32 25 0.16 1201.92 32 32 -1.36 1183.71 2400 32 12 0.16 2403.85 32 15 1.73 2441.41 4800 1 207 0.16 4807.69 1 259 0.16 4807.69 9600 1 103 0.16 9615.38 1 129 0.16 9615.38 14400 1 68 0.64 14492.75 1 86 -0.22 14367.82 19200 1 51 0.16 19230.77 1 64 0.16 19230.77 38400 1 25 0.16 38461.54 1 32 -1.36 37878.79 57600 - - - - 1 21 -1.36 56818.18 115200 - - - - 1 10 -1.36 113636.36 250000 1 3 0.00 250000.00 1 4 0.00 250000.00 500000 1 1 0.00 500000.00 - - - - 625000 - - - - 1 1 0.00 625000.00 1000000 1 0 0.00 1000000.00 - - - - 1250000 - - - - 1 0 0.00 1250000.00 Notes: This does not mean that the communication at the above baud rates is guaranteed. Careful consideration and inspection under your environment are required before use. Select divide-by value of clock divider in the CDIV bit of SIOn transmit control register (SnTCNT). Set BRG set value in the SIOn baud rate register (SnBAUR).

12-2332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 b 0 123456 b 7 CKPOL 00000000

12.2.8 SIO Special Mode Registers

SIO0 Special Mode Register (S0SMOD) <Address: H'0080 0118> SIO1 Special Mode Register (S1SMOD) <Address: H'0080 0128> <Upon exiting reset: Undefined> b Bit Name Function R W 0–6 No function assigned. 00

7 CKPOL 0: Transmit data is output at a fall of SCLK R W

Transmit/receive clock polarity select bit receive data is latched in at a rise of SCLK 1: Transmit data is output at a rise of SCLK receive data is latched in at a fall of SCLK (1) CKPOL(transmit/receive clock polarity select) bit (Bit 7) This bit selects the polarity of the transmit/receive clock when in CSIO mode. When the CKPOL bit is set to "0", data is output from the TXD pin synchronously with a falling edge of SCLK, and data is taken in from the RXD pin synchronously with a rising edge of SCLK. When the CKPOL bit is set to "1", data is output from the TXD pin synchronously with a rising edge of SCLK, and data is taken in from the RXD pin synchronously with a falling edge of SCLK. Notes Do not rewrite the clock polarity select bit when the transmit enable bit or receive enable bit is enabled. Figure 12.2.7 Selecting the Transmit/receive Clock Polarity RXD Transmit/receive clock TXD Note: When the internal clock is selected, the SCLKO pin outputs a "H" level signal when the serial interface is neither transmitting nor receiving. RXD Transmit/receive clock TXD b7 b6 b5 b4 b3 b2 b1 b0 Note: When the internal clock is selected, the SCLKO pin outputs a "L" level signal when the serial interface is neither transmitting nor receiving. (1) When the clock polarity select bit = 0 (2) When the clock polarity select bit = 1 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

12-2432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.3.1 Setting the CSIO Baud Rate

The baud rate (data transfer rate) in CSIO mode is determined by a transmit/receive shift clock. The clock source from which a transmit/receive shift clock derives is selected from the internal clock f(BCLK) or external clock. The CKS (Internal/External Clock Select) bit (SIO Transmit/Receive Mode Register bit 11) is used to select the clock source. The equation used to calculate the transmit/receive baud rate differs depending on whether an internal or external clock is selected. (1) When internal clock is selected in CSIO mode When the internal clock is selected, f(BCLK) is divided by a clock divider before being supplied to the Baud Rate Generator (BRG). The clock divider’s divide-by value is selected from 1, 8, 32 or 256 by using the CDIV (baud rate generator count source select) bits (Transmit Control Register bits 2–3). The Baud Rate Generator divides the clock divider output by (baud rate register set value + 1) and further by 2, thus generating a transmit/receive shift clock. When the internal clock is selected in CSIO mode, the baud rate is calculated using the equation below. Baud rate = f(BCLK) [bps] Clock divider’s divide-by value x (baud rate register set value + 1) x 2 f(BCLK): Peripheral clock operating frequency Baud rate register set value = H’00 to H’FF (Note 1) Clock divider’s divide-by value = 1, 8, 32 or 256 Note 1: If divide-by-1 (i.e., f(BCLK) itself) is selected as the baud rate generator count source, use caution when setting the baud rate register so that the transfer rate will not exceed 2 Mbps. (2) When external clock is selected in CSIO mode In this case, the Baud Rate Generator is not used, and the input clock from the SCLKI pin serves directly as a transmit/receive shift clock for CSIO. The maximum frequency of the SCLKI pin input clock is f(BCLK)/16. Baud rate = SCLKI pin input clock [bps]

12-2532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.3.2 Initializing CSIO Transmission

To transmit data in CSIO mode, initialize the serial interface following the procedure described below. (1) Setting SIO Special Mode Register Select the clock polarity in CSIO mode. (2) Setting SIO Transmit/Receive Mode Register Set the register to CSIO mode. Select the internal or an external clock. (3) Setting SIO Transmit Control Register Select the clock divider’s divide-by ratio (when internal clock selected). (4) Setting SIO Baud Rate Register When the internal clock is selected, set a baud rate generator value. (See Section 12.3.1, “Setting the CSIO Baud Rate.”) (5) Setting SIO interrupt related registers Select the source of transmit interrupt request (transmit buffer empty or transmission finished) (SIO Inter- rupt Request Source Select Register). Enable or disable transmit interrupt requests (SIO Interrupt Request Mask Register). Note: Transmission finished interrupt requests are effective only when the internal clock is selected. (6) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) To use transmit interrupts, set their priority levels. (7) Setting DMAC To issue DMA transfer requests to the internal DMAC when the transmit buffer is empty, set up the DMAC. (See Chapter 9, “DMAC.”) (8) Selecting pin functions Because the serial interface related pins serve dual purposes, set the pin functions for use as SIO pins or input/output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”)

12-2632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.3.1 Procedure for Initializing CSIO Transmission Set SIO Transmit/Receive Mode Register Initialize CSIO transmission Note 1: Necessary when the internal clock is selected. Note 2: Caution must be used when internal clock CSIO mode, the transfer rate does not exceed 2Mbps. Note 3: Transmission finished interrupts are effective only when the internal clock is selected. Set the register to CSIO mode Select the internal or external clock (When using DMAC)Set DMAC (When using interrupts)Set the Interrupt Controller Set SIO interrupt related registers Divide-by ratio = H'00 to H'FF (Note 2)Set SIO Baud Rate Register Select the clock divider divide-by ratio (Note 1)Set SIO Transmit Control Register Set the Input/Output Port Operation Mode Register Serial interface related registers End of CSIO transmit initialization Enable or disable transmit interrupt requests Select the source of transmit interrupt request (Note 3) Set SIO Special Mode Register Select the clock polarity

12-2732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.3.3 Starting CSIO Transmission

The serial interface starts a transmit operation when all of the following conditions are met after being initial- ized. (1) Transmit conditions when CSIO mode internal clock is selected The SIO Transmit Control Register transmit enable bit is set to "1". Transmit data (8 bits) is written to the lower byte of the SIO Transmit Buffer Register (transmit buffer empty bit = "0") (2) Transmit conditions when CSIO mode external clock is selected The SIO Transmit Control Register transmit enable bit is set to "1". Transmit data is written to the lower byte of the SIO Transmit Buffer Register (transmit buffer empty bit = "0") When the clock polarity select bit = "0", the transmit clock input at the SCLKI pin goes low; when the clock polarity select bit = "1", the transmit clock input at the SCLKI pin goes high. A falling edge of transmit clock on the SCLKI pin is detected. While the transmit enable bit is cleared to "0", writes to the transmit buffer register are invalid. Always set the transmit enable bit to "1" before writing to the transmit buffer register. When the internal clock is selected, a write to the lower byte of the transmit buffer register in above triggers transmission to start. The transmit status bit is set to "1" at the time data is set in the lower byte of the SIO Transmit Buffer Register. When transmission starts, the serial interface sends data following the procedure described below. Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register. Set the transmit buffer empty bit to "1" (Note 1). Start sending data synchronously with the shift clock beginning with the LSB. Note 1: A transmit interrupt request can be generated for reasons that the transmit buffer is empty or transmission has finished. Also, a DMA transfer request can be generated when the transmit buffer is empty. No DMA transfer requests can be generated for reasons that transmission has finished.

12.3.4 Successive CSIO Transmission

Once data has been transferred from the transmit buffer register to the transmit shift register, the next data can be written to the transmit buffer register even when the serial interface has not finished sending the previous data. If the next data is written to the transmit buffer register before transmission has finished, the previous and the next data are transmitted successively. Check the SIO Transmit Control Register’s transmit buffer empty flag to see if data has been transferred from the transmit buffer register to the transmit shift register.

12-2832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.3.5 Processing at End of CSIO Transmission

When data transmission finishes, the following operation is automatically performed in hardware. (1) When not transmitting successively The transmit status bit is cleared to "0". (2) When transmitting successively When transmission of the last data in a consecutive data train finishes, the transmit status bit is cleared to "0".

12.3.6 Transmit Interrupts

(1) Transmit buffer empty interrupt If the transmit buffer empty interrupt was selected using the SIO Interrupt Request Source Select Register, a transmit buffer empty interrupt request is generated when data has been transferred from the transmit buffer register to the transmit shift register. A transmit buffer empty interrupt request is also generated when the TEN (Transmit Enable) bit is set to "1" (disabled → enabled) while the transmit buffer empty interrupt has been enabled. (2) Transmission finished interrupt If the transmission finished interrupt was selected using the SIO Interrupt Request Source Select Register, a transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse at which the last bit of data in the transmit shift register has been transmitted. The SIO Interrupt Request Mask Register and the Interrupt Controller (ICU) must be set before these trans- mit interrupts can be used.

12.3.7 Transmit DMA Transfer Request

When data has been transferred from the transmit buffer register to the transmit shift register, a transmit DMA transfer request for the corresponding SIO channel is output to the DMAC. A transmit DMA transfer request is also output when the TEN (Transmit Enable) bit is set to "1" (disabled → enabled). The DMAC must be set before DMA transfers can be used during data transmission.

12-2932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.3.2 Transmit Operation during CSIO Mode (Hardware Processing) The following processing is automatically performed in hardware. Transfer the content of the transmit buffer to the transmit shift register Set the transmit buffer empty bit to "1" Transmit data Y es (Successive transmission) Transmit conditions met? Transmit conditions met? Ye s No No Clear the transmit status bit to "0" Transmit DMA transfer request Transmit interrupt request (Note 1) CSIO transmit operation starts End of CSIO transmit operation Note 1: This applies when the transmit interrupt request was enabled using the SIO Interrupt Request Enable Register after selecting the transmit buffer empty interrupt with the SIO Interrupt Request Source Select Register.

12-3032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.3.8 Example of CSIO Transmit Operation

The following shows a typical transmit operation in CSIO mode. Figure 12.3.3 Example of CSIO Transmission (Transmitted Only Once) Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time) Note 3: When transmission finished interrupt is enabled Note 4: The Interrupt Controller's IVECT register is read or SIO Transmit Interrupt Control Register interrupt request bit is cleared. Note 5: A transmit interrupt request is generated when transmission is enabled. Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. Note 7: A transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse at which transmission of the transmit shift register data has finished. Note 8: It is inhibited to select the transmission finished interrupt when an external clock is selected. Internal clock selected External clock selected Set Transmit enable bit Transmit buffer empty bit Transmit status bit TXD (When transmit buffer empty interrupt is selected) Transmit interrupt request (Note 2) (Note 5) Transmit interrupt request (Note 2) (Note 6) Interrupt request accepted (Note 4) Set by a write to the transmit buffer Write to the transmit buffer register Transmit clock (SCLKO) <CSIO on transmit side> Cleared Cleared by completion of transmission b7 b6 b5 b4 b3 b2 b1 b0 Content of the transmit buffer register is transferred to the transmit shift register : Interrupt request generated : Processing by software <CSIO on transmit side> <CSIO on receive side> SCLKO TXD SCLKI RXD Transmit interrupt request (Note 3) (Note 7) Interrupt request accepted (Note 4) (When transmission finished interrupt is selected)(Note 8) (Internal transfer clock) SIO transmit interrupt request (Note 1)

12-3132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.3.4 Example of CSIO Transmission (Transmitted Successively) Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time) Note 3: When transmission finished interrupt is enabled Note 4: The Interrupt Controller's IVECT register is read or SIO Transmit Interrupt Control Register interrupt request bit is cleared. Note 5: A transmit interrupt request is generated when transmission is enabled. Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. Note 7: A transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse at which transmission of the transmit shift register data has finished. Note 8: It is inhibited to select the transmission finished interrupt when an external clock is selected. : Interrupt request generated : Processing by software Transmit enable bit Transmit buffer empty bit Transmit status bit TXD SIO transmit interrupt request (Note 1) Transmit clock (SCLKO) <CSIO on transmit side> <CSIO on transmit side> <CSIO on receive side> SCLKO TXD SCLKI RXD b7 b6 b5 b0 b7 b6 b5 b0 (Note 2) (Note 5) (Note 2) (Note 2)(Note 6) Next data is written at a transmit buffer empty interrupt First data Next data Write to the transmit buffer register (First data) (Next data) Write to the transmit buffer register Cleared Internal clock selected External clock selected Set (Internal transfer clock) (When transmit buffer empty interrupt is selected) (When transmission finished interrupt is selected) (Note 8) (Note 3) Transmit interrupt request (Note 3)(Note 7)Interrupt request accepted (Note 4) Interrupt request accepted (Note 4)

12-3232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.4.1 Initialization for CSIO Reception

To receive data in CSIO mode, initialize the serial interface following the procedure described below. Note, however, that because the receive shift clock is derived by an operation of the transmit circuit, transmit opera- tion must always be executed even when the serial interface is used for only receiving data. (1) Setting SIO Special Mode Register Set the clock polarity in CSIO mode. (2) Setting SIO Transmit/Receive Mode Register Set the register to CSIO mode. Select the internal or an external clock. (3) Setting SIO Transmit Control Register Select the clock divider’s divide-by ratio (when internal clock selected). (4) Setting SIO Baud Rate Register When the internal clock is selected, set a baud rate generator value. (See Section 12.3.1, “Setting the CSIO Baud Rate.”) (5) Setting SIO interrupt related registers Select the source of receive interrupt request (reception finished or error) (SIO Interrupt Request Source Select Register). Enable or disable receive interrupts (SIO Interrupt Request Mask Register). (6) Setting SIO Receive Control Register Set the receive enable bit. (7) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) To use receive interrupts, set their priority levels. (8) Setting DMAC Set up the DMAC when the DMA transfer is requested to the internal DMAC on completion of the transmis- sion. (See Chapter 9, “DMAC.”) (9) Selecting pin functions Because the serial interface related pins serve dual purposes, set the pin functions for use as SIO pins or input/output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”)

12-3332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.4.1 Procedure for Initializing CSIO Reception Note 1: Necessary when the internal clock is selected. Note 2: Caution must be used when internal clock CSIO mode, the transfer rate does not exceed 2Mbps. Set the register to CSIO mode Select the internal or external clock Set SIO Transmit/Receive Mode Register (When using DMAC)Set DMAC (When using interrupts)Set the Interrupt Controller Select the source of receive interrupt requestSet SIO interrupt related registers Divide-by ratio = H'00 to H'FF (Note 2) Set SIO Baud Rate Register Select the clock divider divide-by ratio (Note 1) Set SIO Transmit Control Register Set the Input/Output Port Operation Mode Register Serial interface related registers Set SIO Receive Control Register Set the receive enable bit End of CSIO receive initialization Enable or disable receive interrupt requests Initialize CSIO reception Select the clock polaritySet SIO Special Mode Register

12-3432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.4.2 Starting CSIO Reception

The serial interface starts receive operation when all of the following conditions are met after being initialized. (1) Receive conditions when CSIO mode internal clock is selected The SIO Receive Control Register receive enable bit is set to "1". Transmit conditions are met. (See Section 12.3.3, “Starting CSIO Transmission.”) (2) Receive conditions when CSIO mode external clock is selected The SIO Receive Control Register receive enable bit is set to "1". Transmit conditions are met. (See Section 12.3.3, “Starting CSIO Transmission.”) Note: The receive status bit is set to "1" at the time dummy data is set in the lower byte of the SIO Transmit Buffer Register. When the above conditions are met, the serial interface starts receiving 8-bit serial data (LSB first) synchro- nously with the receive shift clock.

12.4.3 Processing at End of CSIO Reception

When data reception finishes, the following operation is automatically performed in hardware. (1) When reception is completed normally The reception finished (receive buffer full) bit is set to "1". Notes: An interrupt request is generated if the reception finished (receive buffer full) interrupt has been en- abled. A DMA transfer request is generated. (2) When an error occurred during reception If an error (only overrun error in CSIO mode) occurred during reception, the overrun error bit and receive error sum bit are set to "1". Notes: If the reception finished interrupt has been selected (by SIO Receive Interrupt Request Source Select Register), neither a reception finished interrupt request nor a DMA transfer request is gener- ated. If the receive error interrupt has been selected (by SIO Receive Interrupt Request Source Select Register), a receive error interrupt request is generated when interrupt requests are enabled. No DMA transfer requests are generated.

12-3532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.4.2 Receive Operation during CSIO Mode (Hardware Processing) Receive data Set the SIO Receive Control Register reception finished bit to "1" Store the received data in the receive buffer register Set the SIO Receive Control Register overrun error and receive error sum bits to "1" Receive conditions met? Overrun error ? Ye s Ye s No No End of CSIO receive operation CSIO receive operation starts

12.4.4 About Successive Reception

If the following conditions are met when data reception has finished, data may be received successively. The receive enable bit is set to "1". Transmit conditions are met. No overrun error has occurred.

12-3632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.4.5 Flags Showing the Status of CSIO Receive Operation

There are following flags that indicate the status of receive operation during CSIO mode: SIO Receive Control Register receive status bit SIO Receive Control Register reception finished bit SIO Receive Control Register receive error sum bit SIO Receive Control Register overrun error bit When reading the content of the SIO Receive Buffer Register after reception is completed, if the serial interface finishes receiving the next data before the previous data is not read out, an overrun error occurs and the subsequent received data are not transferred to the receive buffer register. Before receive operation can be restarted, the receive enable bit must temporarily be cleared to "0" to initialize the receiver control unit. The above reception finished bit, if no receive errors occurred (Note 1), may be cleared by reading out the lower byte of the SIO Receive Buffer Register or clearing the REN (Receive Enable) bit. However, if any receive error occurred, the reception finished bit can only be cleared by clearing the REN (Receive Enable) bit, and cannot be cleared by reading out the lower byte of the SIO Receive Buffer Register. Note 1: Overrun errors are the only error that can be detected during reception in CSIO mode.

12-3732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.4.3 Example of CSIO Reception (When Received Normally) Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit Note 2: When reception finished interrupt is enabled (DMA transfer can also be requested at the same time) Note 3: The Interrupt Controller's IVECT register is read or SIO Receive Interrupt Control Register interrupt request bit is cleared <CSIO on receive side> <CSIO on transmit side><CSIO on receive side> SCLKO TXD SCLKI RXD Internal clock selected External clock selected Receive clock (SCLKO) Set Receive enable bit RXD Receive status bit Reception finished bit SIO receive interrupt request (Note 1) (When reception finished interrupt is selected) (When receive error interrupt is selected) No interrupt request Interrupt request accepted (Note 3) Reception finished interrupt request (Note 2) Read from the receive buffer : Interrupt request generated : Processing by software Automatically cleared for each receive operation performed Clock stops Cleared Set by a write to the transmit buffer b7 b6 b5 b4 b3 b2 b1 b0

12.4.6 Example of CSIO Receive Operation

The following shows a typical receive operation in CSIO mode.

12-3832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.4.4 Example of CSIO Reception (When Overrun Error Occurred) <CSIO on receive side> External clock selectedInternal clock selected <CSIO on receive side> <CSIO on transmit side> SCLKO RXD SCLKI TXD : Processing by software : Interrupt request generated Receive clock (SCLKI) Set Receive enable bit b7 b6 b0RXD b7 b6b0 Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit Note 2: When reception finished interrupt is enabled Note 3: When receive error interrupt is enabled Note 4: The receive enable bit is cleared. Note 5: The Interrupt Controller's IVECT register is read or SIO Receive Interrupt Control Register interrupt request bit is cleared. First data reception completed Next data reception completed Reception finished bit SIO receive interrupt request (Note 1) (When reception finished interrupt is selected) Receive buffer not read out during this interval Set Overrun error bit cleared (Note 4) Reception finished interrupt request (Note 2) Interrupt request accepted (Note 5) Cleared Receive error interrupt request (Note 3) Interrupt request accepted (Note 5) (When receive error interrupt is selected) Overrun error bit

12-3932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.5 Notes on Using CSIO Mod

Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register’s BRG count source select bit must always be set when the serial interface is not operating. If a transmit or receive operation is in progress, wait until the transmit and receive operations are finished and then clear the transmit and receive enable bits before making changes.
Settings of BRG (Baud Rate Register) If f(BCLK) is selected with the BRG clock source select bit, use caution when setting the BRG register so that the transfer rate will not exceed 2 Mbps.
About successive transmission To transmit data successively, make sure the next transmit data is set in the SIO Transmit Buffer Register before the current data transmission finishes.
About reception Because the receive shift clock in CSIO mode is derived by an operation of the transmit circuit, transmit operation must always be executed (by sending dummy data) even when the serial interface is used for only receiving data. In this case, be aware that if the port function is set for the TXD pin (by setting the operation mode register to "1"), dummy data may actually be output from the pin.
About successive reception To receive data successively, make sure that data (dummy data) is set in the SIO Transmit Buffer Register before a transmit operation on the transmitter side starts.
Transmission/reception using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before serial communication starts.
About reception finished bit If a receive error (overrun error) occurs, the reception finished bit can only be cleared by clearing the receive enable bit, and cannot be cleared by reading out the receive buffer register.
About overrun error If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored in the receive buffer register, with the previous received data retained in it. Although a receive operation continues there- after, the subsequent received data is not stored in the receive buffer register (receive status bit = "1"). Before normal receive operation can be restarted, the receive enable bit must be temporarily cleared to "0". And this is the only way that the overrun error flag can be cleared.
About DMA transfer request generation during SIO transmission If the transmit buffer register becomes empty (transmit buffer empty flag = "1") while the transmit enable bit remains set to "1" (transmission enabled), an SIO transmit buffer empty DMA transfer request is generated.
About DMA transfer request generation during SIO reception If the reception finished bit is set to "1" (receive buffer register full), a reception finished DMA transfer request is generated. Be aware, however, that if an overrun error occurred during reception, this DMA transfer request is not generated.

12-4032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

Switching from general-purpose to serial interface pin When switching general-purpose to serial interface pin, SCLKOn pin outputs "H" level (For the case of selecting internal clock and setting CKPOL bit to "0." When setting CKPOL bit to "1", it outputs "L" level.), and TXDn pin outputs undefined value. However, when switching general-purpose to serial interface pin with setting TEN bit of the SIOn transmit control register to "1" (transmit enable) , TXDn pin outputs the last bit level of the previously output serial data.

12-4132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.6.1 Example of a Transfer Data Format during UART Mode ST b7 b6 b5 b4 b3 b2 b1 b0 PAR SP SP LSB MSB ST Parity bit Stop bit Start bit Data bits (8 bits) Transmit data Next data

12.6.1 Setting the UART Baud Rate

The baud rate (data transfer rate) in UART mode is determined by a transmit/receive shift clock. During UART mode, the source for this transmit/receive shift clock is always the internal clock no matter how the internal/ external clock select bit (SIO Transmit/Receive Mode Register bit 11) is set. (1) Calculating the UART mode baud rate After being divided by a clock divider, f(BCLK) is supplied to the Baud Rate Generator (BRG), after which it is further divided by 16 to produce a transmit/receive shift clock. The clock divider’s divide-by value is selected from 1, 8, 32 or 256 by using the SIO Transmit Control Register CDIV (baud rate generator count source select) bits (bits 2–3). The Baud Rate Generator divides the clock divider output by (baud rate register set value + 1) and further by 16, thus generating a transmit/receive shift clock. When the internal clock is selected in UART mode, the baud rate is calculated using the equation below. Baud rate = f(BCLK) [bps] Clock divider’s divide-by value x (baud rate register set value + 1) x 16 Baud rate register set value = H’00 to H’FF Clock divider’s divide-by value = 1, 8, 32 or 256

12.6.2 UART Transmit/Receive Data Formats

The transmit/receive data format during UART mode is determined by setting the SIO Transmit/Receive Mode Register. Shown below is the transmit/receive data format that can be used in UART mode.

12-4232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 12.6.1 Transfer Data in UART Mode Bit Name Content ST (start bit) Indicates the beginning of data transmission. This is a "L" level signal of a one bit period, which is added immediately preceding the transmit data. Bits 0–8 (character bits) Transmit/receive data transferred via serial interface. In UART mode, 7, 8 or 9 bits of data can be transmitted/received. PAR (parity bit) Added to the transmit/receive character. When parity is enabled, parity is automatically set in such a way that the number of 1’s in the character including the parity bit itself is always even or odd as selected by the even/odd parity select bit. SP (stop bit) Indicates the end of data transmission, which is added immediately following the character (or if parity is enabled, immediately following the parity bit). The stop bit can be chosen to be one bit or two bits long. Figure 12.6.2 Selectable Data Formats during UART Mode ST b7 b6 b5 b4 b3 b2 b1 b0 PAR SP SP ST b7 b6 b5 b4 b3 b2 b1 b0 PAR SP ST b7 b6 b5 b4 b3 b2 b1 b0 SP SP ST b7 b6 b5 b4 b3 b2 b1 b0 SP LSB MSB 8-bit character ST b7 b6 b5 b4 b3 b2 b1 SP SPPAR ST b7 b6 b5 b4 b3 b2 b1 SP PAR ST b7 b6 b5 b4 b3 b2 b1 SP SP ST b7 b6 b5 b4 b3 b2 b1 SP LSB MSB 7-bit character 9-bit character ST b7 b6 b5 b4 b3 b2 b1 b0 PAR SP SP ST b7 b6 b5 b4 b3 b2 b1 b0 PAR SP ST b7 b6 b5 b4 b3 b2 b1 b0 SP SP ST b7 b6 b5 b4 b3 b2 b1 b0 SP LSB MSB Bits 0-8: Character (data) bits SP: Stop bit ST: Start bit PAR: Parity bitb0 b7 b8 b15 7-bit character 8-bit character 9-bit character SIO Transmit Buffer Register SIO Receive Buffer Register Notes: The high-order bits of the selected character length in the SIO Receive Buffer Register are fixed to "0". The data bit numbers (bn) above indicate bit numbers in a data list, and not the register bit numbers (bn).

12-4332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.6.3 Initializing UART Transmission

To transmit data in UART mode, initialize the serial interface following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register Set the register to UART mode. Set parity (when enabled, select odd/even). Set the stop bit length. Set the character length (Note 1). Note 1: During UART mode, settings of the internal/external clock select bit have no effect (only the internal clock is useful). (2) Setting SIO Transmit Control Register Select the clock divider’s divide-by ratio. (3) Setting SIO Baud Rate Register Set a baud rate generator value. (See Section 12.6.1, “Setting the UART Baud Rate.”) (4) Setting SIO interrupt related registers Select the source of transmit interrupt request (transmit buffer empty or transmission finished) (SIO Interrupt Request Source Select Register). Enable or disable SIO transmit interrupt requests (SIO Interrupt Request Mask Register). (5) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) To use transmit interrupts, set their priority levels. (6) Setting DMAC To issue DMA transfer requests to the internal DMAC when the transmit buffer is empty, set up the DMAC. (See Chapter 9, “DMAC.”) (7) Selecting pin functions Because the serial interface related pins serve dual purposes, set the pin functions for use as SIO pins or input/output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”)

12-4432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.6.3 Procedure for Initializing UART Transmission Initialize UART transmission Set the register to UART mode Set parity (when enabled, select odd/even) Set the stop bit length Set the character length Set SIO Transmit/Receive Mode Register (When using DMAC)Set DMAC related registers Set the Interrupt Controller Set SIO interrupt related registers Divide-by ratio = H'00 to H'FF Set SIO Baud Rate Register Select the clock divider divide-by ratioSet SIO Transmit Control Register Set the Input/Output Port Operation Mode Register Serial interface related registers End of UART transmit initialization (When using interrupts) Select the source of transmit interrupt request Enable or disable transmit interrupt requests

12-4532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.6.4 Starting UART Transmission

The serial interface starts a transmit operation when all of the following conditions are met after being initial- ized. SIO Transmit Control Register TEN (Transmit Enable) bit is set to "1" (Note 1). Transmit data is written to the SIO Transmit Buffer Register (transmit buffer empty bit = "0"). Note 1: While the transmit enable bit is cleared to "0", writes to the transmit buffer are ignored. Always be sure to set the transmit enable bit to "1" before writing to the transmit buffer register. When transmission starts, the serial interface sends data following the procedure described below. Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register. Set the transmit buffer empty bit to "1" (Note 2). Start sending data synchronously with the shift clock beginning with the LSB. Note 2: A transmit interrupt request can be generated for reasons that the transmit buffer is empty or transmission has finished. Also, a DMA transfer request can be generated when the transmit buffer is empty. No DMA transfer requests can be generated for reasons that transmission has finished.

12.6.5 Successive UART Transmission

Once data has been transferred from the transmit buffer register to the transmit shift register, the next data can be written to the transmit buffer register even when the serial interface has not finished sending the previous data. If the next data is written to the transmit buffer before transmission has finished, the previous and the next data are transmitted successively. Check the SIO Transmit Control Register’s transmit buffer empty flag to see if data has been transferred from the transmit buffer register to the transmit shift register.

12.6.6 Processing at End of UART Transmission

12.6.7 Transmit Interrupts

12-4632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.6.4 Transmit Operation during UART Mode (Hardware Processing) The following processing is automatically performed in hardware. Transfer the content of the transmit buffer to the transmit shift register Set the transmit buffer empty bit to "1" Transmit DMA transfer request Transmit interrupt request Transmit data Y es (Successive transmission) Transmit conditions met ? Transmit conditions met ? Clear the transmit status bit to "0" Ye s No No (Note 1) Note 1: This applies when the transmit interrupt was enabled using the SIO Interrupt Request Mask Register after selecting the transmit buffer empty interrupt with the SIO Interrupt Request Source Select Register. End of UART transmit operation UART transmit operation starts (2) Transmission finished interrupt If the transmission finished interrupt was selected using the SIO Interrupt Request Source Select Register, a transmission finished interrupt request is generated when data in the transmit shift register has all been transmitted. The SIO Interrupt Request Mask Register and the Interrupt Controller (ICU) must be set before these transmit interrupts can be used.

12.6.8 Transmit DMA Transfer Request

12-4732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.6.9 Example of UART Transmit Operation

The following shows a typical transmit operation in UART mode. <UART on transmit side> <UART on transmit side> <UART on receive side> TXD RXD Transmit enable bit Transmit buffer empty bit b0b6b7ST SP SPPAR Write to the transmit buffer register Transmit status bit TXD SIO transmit interrupt request (Note 1) Set Cleared : Processing by software : Interrupt request generated Cleared Transferred from the transmit buffer to the transmit shift register (transmission starts) Set Interrupt request accepted (Note 4) (Note 2)(Note 6) (Note 3)(Note 7) (Note 2) (Note 5) Transmit interrupt request Transmit interrupt request Transmit interrupt request Interrupt request accepted (Note 4) (When transmit buffer empty interrupt is selected) (When transmission finished interrupt is selected) Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time) Note 3: When transmission finished interrupt is enabled Note 4: The Interrupt Controller's IVECT register is read or SIO Transmit Interrupt Control Register interrupt request bit is cleared. Note 5: A transmit interrupt request is generated when transmission is enabled. Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. Note 7: A transmission finished interrupt request is generated when data in the transmit shift register has all been transmitted. Figure 12.6.5 Example of UART Transmission (Transmitted Only Once)

12-4832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.6.6 Example of UART Transmission (Transmitted Successively) : Processing by software : Interrupt request generated Set Transmit buffer empty bit Transmit enable bit Cleared Transmit status bit Transferred from the transmit buffer to the transmit shift register (transmission starts) TXD SIO transmit interrupt request (Note 1) (First data) (Next data) Write to the transmit buffer register First data Next data is written upon transmit interrupt (Note 5) (Note 2) (Note 2) <UART on transmit side> <UART on transmit side> <UART on receive side> TXD RXD ST b7 b0 STSP b7 b0 SP Cleared when transfer of the last data is completed Interrupt request accepted (Note 4) Next data (Note 2)(Note 6) (Note 3) (Note 3)(Note 7) Interrupt request accepted (Note 4) (When transmit buffer empty interrupt is selected) (When transmission finished interrupt is selected) Write to the transmit buffer register Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time) Note 3: When transmission finished interrupt is enabled Note 4: The Interrupt Controller's IVECT register is read or SIO Transmit Interrupt Control Register interrupt request bit is cleared. Note 5: A transmit interrupt request is generated when transmission is enabled. Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. Note 7: A transmission finished interrupt request is generated when data in the transmit shift register has all been transmitted.

12-4932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.7.1 Initialization for UART Reception

To receive data in UART mode, initialize the serial interface following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register Set the register to UART mode. Set parity (when enabled, select odd/even). Set the stop bit length. Set the character length. Note: During UART mode, settings of the internal/external clock select bit have no effect (only the internal clock is useful). (2) Setting SIO Transmit Control Register Set the clock divider’s divide-by ratio. (3) Setting SIO Baud Rate Register Set a baud rate generator value. (See Section 12.6.1, “Setting the UART Baud Rate.”) (4) Setting SIO interrupt related registers Select the source of receive interrupt request (reception finished or receive error) (Interrupt Request Source Select Register). Enable or disable receive interrupts (Interrupt Request Mask Register). (5) Setting the Interrupt Controller To use receive interrupt, set their priority levels. (6) Setting DMAC To issue DMA transfer requests to the internal DMAC when reception has finished, set up the DMAC. (See Chapter 9, “DMAC.”) (7) Selecting pin functions Because the serial interface related pins serve dual purposes, set the pin functions for use as SIO pins or input/output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”)

12-5032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.7.1 Procedure for Initializing UART Reception Initialize UART reception Set the register to UART mode Set parity (when enabled, select odd/even) Set the stop bit length Set the character length Set SIO Transmit/Receive Mode Register (When using DMAC)Set DMAC related registers Set the Interrupt Controller's SIO Receive Interrupt Control Register Set SIO interrupt related registers Select the source of receive interrupt request Enable or disable receive interrupt requests Set SIO Baud Rate Register Select the clock divider divide-by ratioSet SIO Transmit Control Register Serial interface related registers End of UART receive initialization (When using interrupts) Divide-by ratio = H'00 to H'FF Set the Input/Output Port Operation Mode Register

12-5132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.7.2 Starting UART Reception

The serial interface starts receive operation when all of the following conditions are met after being initialized. SIO Receive Control Register receive enable bit is set to "1" Start bit (falling edge signal) is applied to the RXD pin When the above conditions are met, the serial interface enters UART receive operation. However, the start bit is checked again at the first rise of the internal receive shift clock and if it is detected "H" for reasons of noise, etc., the serial interface stops receive operation and waits for the start bit again.

12.7.3 Processing at End of UART Reception

When data reception finishes, the following operation is automatically performed in hardware. (1) When reception is completed normally The reception finished (receive buffer full) bit is set to "1". Notes: An interrupt request is generated if the reception finished (receive buffer full) interrupt has been enabled. A DMA transfer request is generated. (2) When a receive error occurred If an error occurred, the corresponding error bit (OE, FE or PE) and the receive error sum bit are set to "1". Notes: If the reception finished interrupt has been selected (by SIO Receive Interrupt Request Source Select Register), a reception finished interrupt request is generated when interrupt requests are enabled. However, this does not apply when the detected error is an overrun error, in which case no reception finished interrupt requests are generated. If the receive error interrupt has been selected (by SIO Receive Interrupt Request Source Select Register), a receive error interrupt request is generated when interrupt requests are enabled. No DMA transfer requests are generated.

12-5232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.7.2 Receive Operation during UART Mode (Hardware Processing) The following processing is automatically performed in hardware. Receive data Ye s Ye s No Transfer data from the SIO Receive Shift Register to the SIO Receive Buffer Register Set the SIO Receive Control Register reception finished bit to "1" Set the receive status bit to "1" Overrun error ? Parity error or framing error ? Receive conditions met ? Start bit detected normally ? No Set the SIO Receive Control Register overrun error bit and error sum bit to "1" Set the SIO Receive Control Register's corresponding error bit and receive error sum bit to "1" No UART receive operation starts End of UART reception Ye s No Ye s

12-5332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

12.7.4 Example of UART Receive Operation

The following shows a typical receive operation in UART mode. Figure 12.7.3 Example of UART Reception (When Received Normally) <UART on receive side> <UART on receive side> <UART on transmit side> TXD RXD Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit Note 2: When reception finished interrupt is enabled (DMA transfer can also be requested at the same time) Note 3: The Interrupt Controller's IVECT register is read or SIO Receive Interrupt Control Register interrupt re quest bit is cleared Receive enable bit (SIO Receive Control Register) b0b6b7ST SP SP PAR Reception finished bit RXD Set Cleared : Processing by software : Interrupt request generated Internal clock selected Read from the receive buffer Reception finished interrupt request (Note 2) Interrupt request accepted (Note 3) Receive status bit Automatically cleared for each receive operation performed SIO receive interrupt request (Note 1) (When reception finished interrupt is selected) (When receive error interrupt is selected) No interrupt request

12-5432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.7.4 Example of UART Reception (When Overrun Error Occurred) <UART on receive side> <UART on receive side> <UART on transmit side> TXD RXD Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit Note 2: When reception finished interrupt is enabled Note 3: When receive error interrupt is enabled Note 4: This is done by clearing the receive enable bit to "0". Note 5: The Interrupt Controller's IVECT register is read or SIO Receive Interrupt Control Register interrupt request bit is cleared Receive enable bit b7ST SP SP Reception finished bit RXD Set : Processing by software : Interrupt request generated ST b7 Receive buffer not read during this interval First data reception completed Next data reception completed (Note 5) Overrun error bit cleared (Note 4) Overrun error bit Set SIO receive interrupt request (Note 1) (When reception finished interrupt is selected) Reception finished interrupt request Interrupt request accepted (Note 5) Receive error interrupt request (Note 3) Interrupt request accepted (Note 5) (When receive error interrupt is selected) (SIO Receive Control Register) (Note 2)

12-5532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 12.7.7 Delay in Receive Timing

12.7.5 Start Bit Detection during UART Reception

The start bit is sampled synchronously with the internal BRG output. If the received signal remains "L" for 8 BRG output cycles after the falling edge of the start bit, the CPU recognizes that part of the received signal as the start bit and starts latching the received data another 8 cycles after that, beginning with the LSB (first bit). If some sampled part of the received signal is "H" before being determined to be the start bit, the CPU starts detecting the falling edge of the received signal again. Because the start bit is sampled synchronously with the internal BRG output, there is a delay equivalent to one BRG output cycle at maximum. The subsequent re- ceived data is latched into the internal circuit with that delayed timing. Figure 12.7.5 Start Bit Detection and Data Sampling Timing Figure 12.7.6 Example of an Invalid Start Bit (Not Received) Internal BRG output RXD LSB data 8 cycles 8 cycles Note: • This diagram does not show detailed timing information. 8 cycles 8 cycles 16 cycles 16 cycles Data sampling (Data for first bit) Start bit determined Internal BRG output RXD 8 cycles Note: This diagram does not show detailed timing information. Internal RXD Internal BRG output RXD Delay equivalent to one BRG output cycle at maximum

12-5632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 When using SIO0 or SIO1 in UART mode, the relevant port (P84 or P87) can be switched for use as an SCLKO0 or SCLKO1 pin, respectively. That way, a BRG output clock divided by 2 can be output from the SCLKO pin. Note: This clock is output not just during data transfer. Figure 12.8.1 Example of Fixed Period Clock Output SCLKO TXD RXD Clock output to peripheral circuits UART transmission/reception ST SPData ST SPData 50% 50% BRG period Internal BRG output SCLKO output 1. Configuration when using BRG/2 clock 2. Operation timing

12-5732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register’s BRG count source select bit must always be set when the serial interface is not operating. If a transmit or receive operation is in progress, wait until the transmit and receive operations are finished and then clear the transmit and receive enable bits before making changes.
Settings of BRG (Baud Rate Register) Writes to the SIO Baud Rate Register take effect in the next cycle after the BRG counter has finished counting. However, if the register is accessed for write while transmission and reception are disabled, the written value takes effect at the same time it is written.
Transmission/reception using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before serial communication starts.
About overrun error If all bits of the next received data have been set in the SIO Receive Shift Register before reading out the SIO Receive Buffer Register (i.e., an overrun error occurred), the received data is not stored in the receive buffer register, with the previous received data retained in it. Once an overrun error occurs, although a receive operation continues, the subsequent received data is not stored in the receive buffer register. Before normal receive operation can be restarted, the receive enable bit must be temporarily cleared. And this is the only way that the overrun error flag can be cleared.
Flags showing the status of UART receive operation There are following flags that indicate the status of receive operation during UART mode: SIO Receive Control Register receive status bit SIO Receive Control Register reception finished bit SIO Receive Control Register receive error sum bit SIO Receive Control Register overrun error bit SIO Receive Control Register parity error bit SIO Receive Control Register framing error bit The manner in which the reception finished bit and various error flags are cleared differs depending on whether an overrun error occurred, as described below. [When an overrun error did not occur] Cleared by reading out the lower byte of the receive buffer register or by clearing the receive enable bit. [When an overrun error occurred] Cleared by only clearing the receive enable bit.
Switching from general-purpose to serial interface pin When switching from general-purpose port to the serial interface pin by the port operation mode regis- ter, the terminal TXDn pin outputs "H" level.

12-5832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 This page is blank for reasons of layout.

13.1 Outline of the CAN Module

13.2 CAN Module Related Registers

13.3 CAN Protocol

13.4 Initializing the CAN Module

13.5 Transmitting Data Frames

13.6 Receiving Data Frames

13.7 Transmitting Remote Frames

13.8 Receiving Remote Frames

13.9 Notes on CAN Module

13-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The 32176 contains two-channel Full CAN modules compliant with CAN (Controller Area Network) Specification V2.0 B Active. These CAN modules each have 16 message slots and three mask registers, effective use of which helps to reduce the data processing load of the CPU. The CAN modules are outlined below. Table 13.1.1 Outline of the CAN Module Item Description Protocol CAN Specification V2.0 B Active Number of message slots Total 16 slots (14 global slots, two local slots) Polarity 0: Dominant 1: Recessive Acceptance filter Global mask: 1 (Function to receive only a rangeLocal mask: 2 of IDs specified by receive ID filter) Baud rate 1 time quantum (Tq) = (BRP + 1) / CPU clock (BRP: Baud Rate Prescaler set value) Tq period × number of Tq’s for one bit BRP: 1–255 (0: inhibited) Number of Tq’s for one bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 Synchronization Segment : 1Tq Propagation Segment: 1–8Tq Phase Segment 1: 1–8Tq Phase Segment 2: 1–8Tq (IPT = 1) Remote frame automatic The slot that received a remote frame responds by automatically sending a data frame. response function Timestamp function This function is implemented using a 16-bit counter. The count period is derived from the CAN bus bit period by dividing it by 1, 2, 3 or 4. BasicCAN mode Slot 14 and 15 can be alternately received as receive-only. Transmit abort function Transmit requests can be canceled. Loopback function The CAN module receives the data transmitted by the module itself. Return bus off function Error active mode is forcibly entered into after clearing the error counter. Single shot function Transmission is not retried even when it failed due to arbitration-lost or a transmit error. DMA transfer function DMA transfer request is generated when transmission failed or transmit/receive operation finished. Self-diagnostic function Communication module is diagnosed by communicating internally in the CAN module. Note 1: The maximum allowable error of oscillation depends on the system configuration (e.g., bus length, clock error, CAN bus transceiver, sampling position and bit configuration). Table 13.1.2 DMA Transfer Requests Generated by CAN DMA Transfer Request by CAN DMAC Input Channel CAN0: Slot 0 transmission failed or slot 15 transmit/receive operation finished DMA6 CAN0: Slot 1 transmission failed or slot 14 transmit/receive operation finished DMA7 CAN1: Slot 0 transmission failed or slot 15 transmit/receive operation finished DMA8 CAN1: Slot 1 transmission failed or slot 14 transmit/receive operation finished DMA9

13-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 13.1.3 Interrupt Requests Generated by CAN Modules CAN Module Interrupt Request Source ICU Interrupt Request Source CAN0 transmission completed CAN0 transmit/receive & error interrupt CAN1 transmission completed CAN1 transmit/receive & error interrupt CAN0 reception completed CAN0 transmit/receive & error interrupt CAN1 reception completed CAN1 transmit/receive & error interrupt CAN0 bus error CAN0 transmit/receive & error interrupt CAN1 bus error CAN1 transmit/receive & error interrupt CAN0 error passive CAN0 transmit/receive & error interrupt CAN1 error passive CAN1 transmit/receive & error interrupt CAN0 bus off CAN0 transmit/receive & error interrupt CAN1 bus off CAN1 transmit/receive & error interrupt CAN0 single shot CAN0 transmit/receive & error interrupt CAN1 single shot CAN1 transmit/receive & error interrupt Acceptance Filter Self- diagnosis Control Baud Rate Prescaler CPUCLK Message Slot × 16 Transmit/receive completed, error or single shot DMA6,7 CAN0 Internal data bus Interrupt CTX0 CRX0 DAM Request CAN Protocol Controller Acceptance Filter Self- diagnosis Control Baud Rate Prescaler CPUCLK Message Slot × 16 Transmit/receive completed, error or single shot CAN1 Interrupt CTX1 CRX1 CAN Protocol Controller DMA8,9DAM Request Figure 13.1.1 Block Diagram of the CAN Modules

13-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Shown below is a CAN module related register map. CAN Module Related Register Map (1/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1000 CAN0 Control Register 13-15 (CAN0CNT) H'0080 1002 CAN0 Status Register 13-18 (CAN0STAT) H'0080 1004 CAN0 Extended ID Register 13-21 (CAN0EXTID) H'0080 1006 CAN0 Configuration Register 13-22 (CAN0CONF) H'0080 1008 CAN0 Timestamp Count Register 13-24 (CAN0TSTMP) H'0080 100A CAN0 Receive Error Count Register CAN0 Transmit Error Count Register 13-25 (CAN0REC) (CAN0TEC) H'0080 100C CAN0 Slot Interrupt Request Status Register 13-29 (CAN0SLIST) H'0080 100E (Use inhibited area) H'0080 1010 CAN0 Slot Interrupt Request Mask Register 13-30 (CAN0SLIMK) H'0080 1012 (Use inhibited area) H'0080 1014 CAN0 Error Interrupt Request Status Register CAN0 Error Interrupt Request Mask Register 13-31 (CAN0ERIST) (CAN0ERIMK) 13-32 H'0080 1016 CAN0 Baud Rate Prescaler CAN0 Cause of Error Register 13-26 (CAN0BRP) (CAN0EF) 13-45 H'0080 1018 CAN0 Mode Register CAN0 DMA Transfer Request Select Register 13-47 (CAN0MOD) (CAN0DMARQ) 13-48 (Use inhibited area) H'0080 1028 CAN0 Global Mask Register Standard ID0 CAN0 Global Mask Register Standard ID1 13-49 (C0GMSKS0) (C0GMSKS1) H'0080 102A CAN0 Global Mask Register Extended ID0 CAN0 Global Mask Register Extended ID1 13-50 (C0GMSKE0) (C0GMSKE1) H'0080 102C CAN0 Global Mask Register Extended ID2 (Use inhibited area) 13-51 (C0GMSKE2) H'0080 102E (Use inhibited area) H'0080 1030 CAN0 Local Mask Register A Standard ID0 CAN0 Local Mask Register A Standard ID1 13-49 (C0LMSKAS0) (C0LMSKAS1) H'0080 1032 CAN0 Local Mask Register A Extended ID0 CAN0 Local Mask Register A Extended ID1 13-50 (C0LMSKAE0) (C0LMSKAE1) H'0080 1034 CAN0 Local Mask Register A Extended ID2 (Use inhibited area) 13-51 (C0LMSKAE2) H'0080 1036 (Use inhibited area) H'0080 1038 CAN0 Local Mask Register B Standard ID0 CAN0 Local Mask Register B Standard ID1 13-49 (C0LMSKBS0) (C0LMSKBS1) H'0080 103A CAN0 Local Mask Register B Extended ID0 CAN0 Local Mask Register B Extended ID1 13-50 (C0LMSKBE0) (C0LMSKBE1) H'0080 103C CAN0 Local Mask Register B Extended ID2 (Use inhibited area) 13-51 (C0LMSKBE2) H'0080 103E (Use inhibited area) H'0080 1040 CAN0 Single-Shot Mode Control Register 13-53 (CAN0SSMODE) H'0080 1042 (Use inhibited area) H'0080 1044 CAN0 Single-Shot Interrupt Request Status Register 13-33 (CAN0SSIST) H'0080 1046 (Use inhibited area)

13 13.2 CAN Module Related Registers CAN MODULE 13-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN Module Related Register Map (2/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1048 CAN0 Single-Shot Interrupt Request Mask Register 13-34 (CAN0SSIMK) | (Use inhibited area) H'0080 1050 CAN0 Message Slot 0 Control Register CAN0 Message Slot 1 Control Register 13-54 (C0MSL0CNT) (C0MSL1CNT) H'0080 1052 CAN0 Message Slot 2 Control Register CAN0 Message Slot 3 Control Register 13-54 (C0MSL2CNT) (C0MSL3CNT) H'0080 1054 CAN0 Message Slot 4 Control Register CAN0 Message Slot 5 Control Register 13-54 (C0MSL4CNT) (C0MSL5CNT) H'0080 1056 CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register 13-54 (C0MSL6CNT) (C0MSL7CNT) H'0080 1058 CAN0 Message Slot 8 Control Register CAN0 Message Slot 9 Control Register 13-54 (C0MSL8CNT) (C0MSL9CNT) H'0080 105A CAN0 Message Slot 10 Control Register CAN0 Message Slot 11 Control Register 13-54 (C0MSL10CNT) (C0MSL11CNT) H'0080 105C CAN0 Message Slot 12 Control Register CAN0 Message Slot 13 Control Register 13-54 (C0MSL12CNT) (C0MSL13CNT) H'0080 105E CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register 13-54 (C0MSL14CNT) (C0MSL15CNT) (Use inhibited area) H'0080 1100 CAN0 Message Slot 0 Standard ID0 CAN0 Message Slot 0 Standard ID1 13-58 (C0MSL0SID0) (C0MSL0SID1) 13-59 H'0080 1102 CAN0 Message Slot 0 Extended ID0 CAN0 Message Slot 0 Extended ID1 13-60 (C0MSL0EID0) (C0MSL0EID1) 13-61 H'0080 1104 CAN0 Message Slot 0 Extended ID2 CAN0 Message Slot 0 Data Length Register 13-62 (C0MSL0EID2) (C0MSL0DLC) 13-63 H'0080 1106 CAN0 Message Slot 0 Data 0 CAN0 Message Slot 0 Data 1 13-64 (C0MSL0DT0) (C0MSL0DT1) 13-65 H'0080 1108 CAN0 Message Slot 0 Data 2 CAN0 Message Slot 0 Data 3 13-66 (C0MSL0DT2) (C0MSL0DT3) 13-67 H'0080 110A CAN0 Message Slot 0 Data 4 CAN0 Message Slot 0 Data 5 13-68 (C0MSL0DT4) (C0MSL0DT5) 13-69 H'0080 110C CAN0 Message Slot 0 Data 6 CAN0 Message Slot 0 Data 7 13-70 (C0MSL0DT6) (C0MSL0DT7) 13-71 H'0080 110E CAN0 Message Slot 0 Timestamp 13-72 (C0MSL0TSP) H'0080 1110 CAN0 Message Slot 1 Standard ID0 CAN0 Message Slot 1 Standard ID1 13-58 (C0MSL1SID0) (C0MSL1SID1) 13-59 H'0080 1112 CAN0 Message Slot 1 Extended ID0 CAN0 Message Slot 1 Extended ID1 13-60 (C0MSL1EID0) (C0MSL1EID1) 13-61 H'0080 1114 CAN0 Message Slot 1 Extended ID2 CAN0 Message Slot 1 Data Length Register 13-62 (C0MSL1EID2) (C0MSL1DLC) 13-63 H'0080 1116 CAN0 Message Slot 1 Data 0 CAN0 Message Slot 1 Data 1 13-64 (C0MSL1DT0) (C0MSL1DT1) 13-65 H'0080 1118 CAN0 Message Slot 1 Data 2 CAN0 Message Slot 1 Data 3 13-66 (C0MSL1DT2) (C0MSL1DT3) 13-67 H'0080 111A CAN0 Message Slot 1 Data 4 CAN0 Message Slot 1 Data 5 13-68 (C0MSL1DT4) (C0MSL1DT5) 13-69 H'0080 111C CAN0 Message Slot 1 Data 6 CAN0 Message Slot 1 Data 7 13-70 (C0MSL1DT6) (C0MSL1DT7) 13-71 H'0080 111E CAN0 Message Slot 1 Timestamp 13-72 (C0MSL1TSP) H'0080 1120 CAN0 Message Slot 2 Standard ID0 CAN0 Message Slot 2 Standard ID1 13-58 (C0MSL2SID0) (C0MSL2SID1) 13-59 H'0080 1122 CAN0 Message Slot 2 Extended ID0 CAN0 Message Slot 2 Extended ID1 13-60 (C0MSL2EID0) (C0MSL2EID1) 13-61 H'0080 1124 CAN0 Message Slot 2 Extended ID2 CAN0 Message Slot 2 Data Length Register 13-62 (C0MSL2EID2) (C0MSL2DLC) 13-63 H'0080 1126 CAN0 Message Slot 2 Data 0 CAN0 Message Slot 2 Data 1 13-64 (C0MSL2DT0) (C0MSL2DT1) 13-65 H'0080 1128 CAN0 Message Slot 2 Data 2 CAN0 Message Slot 2 Data 3 13-66 (C0MSL2DT2) (C0MSL2DT3) 13-67 H'0080 112A CAN0 Message Slot 2 Data 4 CAN0 Message Slot 2 Data 5 13-68 (C0MSL2DT4) (C0MSL2DT5) 13-69 H'0080 112C CAN0 Message Slot 2 Data 6 CAN0 Message Slot 2 Data 7 13-70 (C0MSL2DT6) (C0MSL2DT7) 13-71 H'0080 112E CAN0 Message Slot 2 Timestamp 13-72 (C0MSL2TSP)

13-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN Module Related Register Map (3/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1130 CAN0 Message Slot 3 Standard ID0 CAN0 Message Slot 3 Standard ID1 13-58 (C0MSL3SID0) (C0MSL3SID1) 13-59 H'0080 1132 CAN0 Message Slot 3 Extended ID0 CAN0 Message Slot 3 Extended ID1 13-60 (C0MSL3EID0) (C0MSL3EID1) 13-61 H'0080 1134 CAN0 Message Slot 3 Extended ID2 CAN0 Message Slot 3 Data Length Register 13-62 (C0MSL3EID2) (C0MSL3DLC) 13-63 H'0080 1136 CAN0 Message Slot 3 Data 0 CAN0 Message Slot 3 Data 1 13-64 (C0MSL3DT0) (C0MSL3DT1) 13-65 H'0080 1138 CAN0 Message Slot 3 Data 2 CAN0 Message Slot 3 Data 3 13-66 (C0MSL3DT2) (C0MSL3DT3) 13-67 H'0080 113A CAN0 Message Slot 3 Data 4 CAN0 Message Slot 3 Data 5 13-68 (C0MSL3DT4) (C0MSL3DT5) 13-69 H'0080 113C CAN0 Message Slot 3 Data 6 CAN0 Message Slot 3 Data 7 13-70 (C0MSL3DT6) (C0MSL3DT7) 13-71 H'0080 113E CAN0 Message Slot 3 Timestamp 13-72 (C0MSL3TSP) H'0080 1140 CAN0 Message Slot 4 Standard ID0 CAN0 Message Slot 4 Standard ID1 13-58 (C0MSL4SID0) (C0MSL4SID1) 13-59 H'0080 1142 CAN0 Message Slot 4 Extended ID0 CAN0 Message Slot 4 Extended ID1 13-60 (C0MSL4EID0) (C0MSL4EID1) 13-61 H'0080 1144 CAN0 Message Slot 4 Extended ID2 CAN0 Message Slot 4 Data Length Register 13-62 (C0MSL4EID2) (C0MSL4DLC) 13-63 H'0080 1146 CAN0 Message Slot 4 Data 0 CAN0 Message Slot 4 Data 1 13-64 (C0MSL4DT0) (C0MSL4DT1) 13-65 H'0080 1148 CAN0 Message Slot 4 Data 2 CAN0 Message Slot 4 Data 3 13-66 (C0MSL4DT2) (C0MSL4DT3) 13-67 H'0080 114A CAN0 Message Slot 4 Data 4 CAN0 Message Slot 4 Data 5 13-68 (C0MSL4DT4) (C0MSL4DT5) 13-69 H'0080 114C CAN0 Message Slot 4 Data 6 CAN0 Message Slot 4 Data 7 13-70 (C0MSL4DT6) (C0MSL4DT7) 13-71 H'0080 114E CAN0 Message Slot 4 Timestamp 13-72 (C0MSL4TSP) H'0080 1150 CAN0 Message Slot 5 Standard ID0 CAN0 Message Slot 5 Standard ID1 13-58 (C0MSL5SID0) (C0MSL5SID1) 13-59 H'0080 1152 CAN0 Message Slot 5 Extended ID0 CAN0 Message Slot 5 Extended ID1 13-60 (C0MSL5EID0) (C0MSL5EID1) 13-61 H'0080 1154 CAN0 Message Slot 5 Extended ID2 CAN0 Message Slot 5 Data Length Register 13-62 (C0MSL5EID2) (C0MSL5DLC) 13-63 H'0080 1156 CAN0 Message Slot 5 Data 0 CAN0 Message Slot 5 Data 1 13-64 (C0MSL5DT0) (C0MSL5DT1) 13-65 H'0080 1158 CAN0 Message Slot 5 Data 2 CAN0 Message Slot 5 Data 3 13-66 (C0MSL5DT2) (C0MSL5DT3) 13-67 H'0080 115A CAN0 Message Slot 5 Data 4 CAN0 Message Slot 5 Data 5 13-68 (C0MSL5DT4) (C0MSL5DT5) 13-69 H'0080 115C CAN0 Message Slot 5 Data 6 CAN0 Message Slot 5 Data 7 13-70 (C0MSL5DT6) (C0MSL5DT7) 13-71 H'0080 115E CAN0 Message Slot 5 Timestamp 13-72 (C0MSL5TSP) H'0080 1160 CAN0 Message Slot 6 Standard ID0 CAN0 Message Slot 6 Standard ID1 13-58 (C0MSL6SID0) (C0MSL6SID1) 13-59 H'0080 1162 CAN0 Message Slot 6 Extended ID0 CAN0 Message Slot 6 Extended ID1 13-60 (C0MSL6EID0) (C0MSL6EID1) 13-61 H'0080 1164 CAN0 Message Slot 6 Extended ID2 CAN0 Message Slot 6 Data Length Register 13-62 (C0MSL6EID2) (C0MSL6DLC) 13-63 H'0080 1166 CAN0 Message Slot 6 Data 0 CAN0 Message Slot 6 Data 1 13-64 (C0MSL6DT0) (C0MSL6DT1) 13-65 H'0080 1168 CAN0 Message Slot 6 Data 2 CAN0 Message Slot 6 Data 3 13-66 (C0MSL6DT2) (C0MSL6DT3) 13-67 H'0080 116A CAN0 Message Slot 6 Data 4 CAN0 Message Slot 6 Data 5 13-68 (C0MSL6DT4) (C0MSL6DT5) 13-69 H'0080 116C CAN0 Message Slot 6 Data 6 CAN0 Message Slot 6 Data 7 13-70 (C0MSL6DT6) (C0MSL6DT7) 13-71 H'0080 116E CAN0 Message Slot 6 Timestamp 13-72 (C0MSL6TSP)

13 13.2 CAN Module Related Registers CAN MODULE 13-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN Module Related Register Map (4/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1170 CAN0 Message Slot 7 Standard ID0 CAN0 Message Slot 7 Standard ID1 13-58 (C0MSL7SID0) (C0MSL7SID1) 13-59 H'0080 1172 CAN0 Message Slot 7 Extended ID0 CAN0 Message Slot 7 Extended ID1 13-60 (C0MSL7EID0) (C0MSL7EID1) 13-61 H'0080 1174 CAN0 Message Slot 7 Extended ID2 CAN0 Message Slot 7 Data Length Register 13-62 (C0MSL7EID2) (C0MSL7DLC) 13-63 H'0080 1176 CAN0 Message Slot 7 Data 0 CAN0 Message Slot 7 Data 1 13-64 (C0MSL7DT0) (C0MSL7DT1) 13-65 H'0080 1178 CAN0 Message Slot 7 Data 2 CAN0 Message Slot 7 Data 3 13-66 (C0MSL7DT2) (C0MSL7DT3) 13-67 H'0080 117A CAN0 Message Slot 7 Data 4 CAN0 Message Slot 7 Data 5 13-68 (C0MSL7DT4) (C0MSL7DT5) 13-69 H'0080 117C CAN0 Message Slot 7 Data 6 CAN0 Message Slot 7 Data 7 13-70 (C0MSL7DT6) (C0MSL7DT7) 13-71 H'0080 117E CAN0 Message Slot 7 Timestamp 13-72 (C0MSL7TSP) H'0080 1180 CAN0 Message Slot 8 Standard ID0 CAN0 Message Slot 8 Standard ID1 13-58 (C0MSL8SID0) (C0MSL8SID1) 13-59 H'0080 1182 CAN0 Message Slot 8 Extended ID0 CAN0 Message Slot 8 Extended ID1 13-60 (C0MSL8EID0) (C0MSL8EID1) 13-61 H'0080 1184 CAN0 Message Slot 8 Extended ID2 CAN0 Message Slot 8 Data Length Register 13-62 (C0MSL8EID2) (C0MSL8DLC) 13-63 H'0080 1186 CAN0 Message Slot 8 Data 0 CAN0 Message Slot 8 Data 1 13-64 (C0MSL8DT0) (C0MSL8DT1) 13-65 H'0080 1188 CAN0 Message Slot 8 Data 2 CAN0 Message Slot 8 Data 3 13-66 (C0MSL8DT2) (C0MSL8DT3) 13-67 H'0080 118A CAN0 Message Slot 8 Data 4 CAN0 Message Slot 8 Data 5 13-68 (C0MSL8DT4) (C0MSL8DT5) 13-69 H'0080 118C CAN0 Message Slot 8 Data 6 CAN0 Message Slot 8 Data 7 13-70 (C0MSL8DT6) (C0MSL8DT7) 13-71 H'0080 118E CAN0 Message Slot 8 Timestamp 13-72 (C0MSL8TSP) H'0080 1190 CAN0 Message Slot 9 Standard ID0 CAN0 Message Slot 9 Standard ID1 13-58 (C0MSL9SID0) (C0MSL9SID1) 13-59 H'0080 1192 CAN0 Message Slot 9 Extended ID0 CAN0 Message Slot 9 Extended ID1 13-60 (C0MSL9EID0) (C0MSL9EID1) 13-61 H'0080 1194 CAN0 Message Slot 9 Extended ID2 CAN0 Message Slot 9 Data Length Register 13-62 (C0MSL9EID2) (C0MSL9DLC) 13-63 H'0080 1196 CAN0 Message Slot 9 Data 0 CAN0 Message Slot 9 Data 1 13-64 (C0MSL9DT0) (C0MSL9DT1) 13-65 H'0080 1198 CAN0 Message Slot 9 Data 2 CAN0 Message Slot 9 Data 3 13-66 (C0MSL9DT2) (C0MSL9DT3) 13-67 H'0080 119A CAN0 Message Slot 9 Data 4 CAN0 Message Slot 9 Data 5 13-68 (C0MSL9DT4) (C0MSL9DT5) 13-69 H'0080 119C CAN0 Message Slot 9 Data 6 CAN0 Message Slot 9 Data 7 13-70 (C0MSL9DT6) (C0MSL9DT7) 13-71 H'0080 119E CAN0 Message Slot 9 Timestamp 13-72 (C0MSL9TSP) H'0080 11A0 CAN0 Message Slot 10 Standard ID0 CAN0 Message Slot 10 Standard ID1 13-58 (C0MSL10SID0) (C0MSL10SID1) 13-59 H'0080 11A2 CAN0 Message Slot 10 Extended ID0 CAN0 Message Slot 10 Extended ID1 13-60 (C0MSL10EID0) (C0MSL10EID1) 13-61 H'0080 11A4 CAN0 Message Slot 10 Extended ID2 CAN0 Message Slot 10 Data Length Register 13-62 (C0MSL10EID2) (C0MSL10DLC) 13-63 H'0080 11A6 CAN0 Message Slot 10 Data 0 CAN0 Message Slot 10 Data 1 13-64 (C0MSL10DT0) (C0MSL10DT1) 13-65 H'0080 11A8 CAN0 Message Slot 10 Data 2 CAN0 Message Slot 10 Data 3 13-66 (C0MSL10DT2) (C0MSL10DT3) 13-67 H'0080 11AA CAN0 Message Slot 10 Data 4 CAN0 Message Slot 10 Data 5 13-68 (C0MSL10DT4) (C0MSL10DT5) 13-69 H'0080 11AC CAN0 Message Slot 10 Data 6 CAN0 Message Slot 10 Data 7 13-70 (C0MSL10DT6) (C0MSL10DT7) 13-71 H'0080 11AE CAN0 Message Slot 10 Timestamp 13-72 (C0MSL10TSP)

13-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN Module Related Register Map (5/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 11B0 CAN0 Message Slot 11 Standard ID0 CAN0 Message Slot 11 Standard ID1 13-58 (C0MSL11SID0) (C0MSL11SID1) 13-59 H'0080 11B2 CAN0 Message Slot 11 Extended ID0 CAN0 Message Slot 11 Extended ID1 13-60 (C0MSL11EID0) (C0MSL11EID1) 13-61 H'0080 11B4 CAN0 Message Slot 11 Extended ID2 CAN0 Message Slot 11 Data Length Register 13-62 (C0MSL11EID2) (C0MSL11DLC) 13-63 H'0080 11B6 CAN0 Message Slot 11 Data 0 CAN0 Message Slot 11 Data 1 13-64 (C0MSL11DT0) (C0MSL11DT1) 13-65 H'0080 11B8 CAN0 Message Slot 11 Data 2 CAN0 Message Slot 11 Data 3 13-66 (C0MSL11DT2) (C0MSL11DT3) 13-67 H'0080 11BA CAN0 Message Slot 11 Data 4 CAN0 Message Slot 11 Data 5 13-68 (C0MSL11DT4) (C0MSL11DT5) 13-69 H'0080 11BC CAN0 Message Slot 11 Data 6 CAN0 Message Slot 11 Data 7 13-70 (C0MSL11DT6) (C0MSL11DT7) 13-71 H'0080 11BE CAN0 Message Slot 11 Timestamp 13-72 (C0MSL11TSP) H'0080 11C0 CAN0 Message Slot 12 Standard ID0 CAN0 Message Slot 12 Standard ID1 13-58 (C0MSL12SID0) (C0MSL12SID1) 13-59 H'0080 11C2 CAN0 Message Slot 12 Extended ID0 CAN0 Message Slot 12 Extended ID1 13-60 (C0MSL12EID0) (C0MSL12EID1) 13-61 H'0080 11C4 CAN0 Message Slot 12 Extended ID2 CAN0 Message Slot 12 Data Length Register 13-62 (C0MSL12EID2) (C0MSL12DLC) 13-63 H'0080 11C6 CAN0 Message Slot 12 Data 0 CAN0 Message Slot 12 Data 1 13-64 (C0MSL12DT0) (C0MSL12DT1) 13-65 H'0080 11C8 CAN0 Message Slot 12 Data 2 CAN0 Message Slot 12 Data 3 13-66 (C0MSL12DT2) (C0MSL12DT3) 13-67 H'0080 11CA CAN0 Message Slot 12 Data 4 CAN0 Message Slot 12 Data 5 13-68 (C0MSL12DT4) (C0MSL12DT5) 13-69 H'0080 11CC CAN0 Message Slot 12 Data 6 CAN0 Message Slot 12 Data 7 13-70 (C0MSL12DT6) (C0MSL12DT7) 13-71 H'0080 11CE CAN0 Message Slot 12 Timestamp 13-72 (C0MSL12TSP) H'0080 11D0 CAN0 Message Slot 13 Standard ID0 CAN0 Message Slot 13 Standard ID1 13-58 (C0MSL13SID0) (C0MSL13SID1) 13-59 H'0080 11D2 CAN0 Message Slot 13 Extended ID0 CAN0 Message Slot 13 Extended ID1 13-60 (C0MSL13EID0) (C0MSL13EID1) 13-61 H'0080 11D4 CAN0 Message Slot 13 Extended ID2 CAN0 Message Slot 13 Data Length Register 13-62 (C0MSL13EID2) (C0MSL13DLC) 13-63 H'0080 11D6 CAN0 Message Slot 13 Data 0 CAN0 Message Slot 13 Data 1 13-64 (C0MSL13DT0) (C0MSL13DT1) 13-65 H'0080 11D8 CAN0 Message Slot 13 Data 2 CAN0 Message Slot 13 Data 3 13-66 (C0MSL13DT2) (C0MSL13DT3) 13-67 H'0080 11DA CAN0 Message Slot 13 Data 4 CAN0 Message Slot 13 Data 5 13-68 (C0MSL13DT4) (C0MSL13DT5) 13-69 H'0080 11DC CAN0 Message Slot 13 Data 6 CAN0 Message Slot 13 Data 7 13-70 (C0MSL13DT6) (C0MSL13DT7) 13-71 H'0080 11DE CAN0 Message Slot 13 Timestamp 13-72 (C0MSL13TSP) H'0080 11E0 CAN0 Message Slot 14 Standard ID0 CAN0 Message Slot 14 Standard ID1 13-58 (C0MSL14SID0) (C0MSL14SID1) 13-59 H'0080 11E2 CAN0 Message Slot 14 Extended ID0 CAN0 Message Slot 14 Extended ID1 13-60 (C0MSL14EID0) (C0MSL14EID1) 13-61 H'0080 11E4 CAN0 Message Slot 14 Extended ID2 CAN0 Message Slot 14 Data Length Register 13-62 (C0MSL14EID2) (C0MSL14DLC) 13-63 H'0080 11E6 CAN0 Message Slot 14 Data 0 CAN0 Message Slot 14 Data 1 13-64 (C0MSL14DT0) (C0MSL14DT1) 13-65 H'0080 11E8 CAN0 Message Slot 14 Data 2 CAN0 Message Slot 14 Data 3 13-66 (C0MSL14DT2) (C0MSL14DT3) 13-67 H'0080 11EA CAN0 Message Slot 14 Data 4 CAN0 Message Slot 14 Data 5 13-68 (C0MSL14DT4) (C0MSL14DT5) 13-69 H'0080 11EC CAN0 Message Slot 14 Data 6 CAN0 Message Slot 14 Data 7 13-70 (C0MSL14DT6) (C0MSL14DT7) 13-71 H'0080 11EE CAN0 Message Slot 14 Timestamp 13-72 (C0MSL14TSP)

13 13.2 CAN Module Related Registers CAN MODULE 13-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN Module Related Register Map (6/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 11F0 CAN0 Message Slot 15 Standard ID0 CAN0 Message Slot 15 Standard ID1 13-58 (C0MSL15SID0) (C0MSL15SID1) 13-59 H'0080 11F2 CAN0 Message Slot 15 Extended ID0 CAN0 Message Slot 15 Extended ID1 13-60 (C0MSL15EID0) (C0MSL15EID1) 13-61 H'0080 11F4 CAN0 Message Slot 15 Extended ID2 CAN0 Message Slot 15 Data Length Register 13-62 (C0MSL15EID2) (C0MSL15DLC) 13-63 H'0080 11F6 CAN0 Message Slot 15 Data 0 CAN0 Message Slot 15 Data 1 13-64 (C0MSL15DT0) (C0MSL15DT1) 13-65 H'0080 11F8 CAN0 Message Slot 15 Data 2 CAN0 Message Slot 15 Data 3 13-66 (C0MSL15DT2) (C0MSL15DT3) 13-67 H'0080 11FA CAN0 Message Slot 15 Data 4 CAN0 Message Slot 15 Data 5 13-68 (C0MSL15DT4) (C0MSL15DT5) 13-69 H'0080 11FC CAN0 Message Slot 15 Data 6 CAN0 Message Slot 15 Data 7 13-70 (C0MSL15DT6) (C0MSL15DT7) 13-71 H'0080 11FE CAN0 Message Slot 15 Timestamp 13-72 (C0MSL15TSP) (Use inhibited area) H'0080 1400 CAN1 Control Register 13-15 (CAN1CNT) H'0080 1402 CAN1 Status Register 13-18 (CAN1STAT) H'0080 1404 CAN1 Extended ID Register 13-21 (CAN1EXTID) H'0080 1406 CAN1 Configuration Register 13-22 (CAN1CONF) H'0080 1408 CAN1 Timestamp Count Register 13-24 (CAN1TSTMP) H'0080 140A CAN1 Receive Error Count Register CAN1 Transmit Error Count Register 13-25 (CAN1REC) (CAN1TEC) H'0080 140C CAN1 Slot Interrupt Request Status Register 13-29 (CAN1SLIST) H'0080 140E (Use inhibited area) H'0080 1410 CAN1 Slot Interrupt Request Mask Register 13-30 (CAN1SLIMK) H'0080 1412 (Use inhibited area) H'0080 1414 CAN1 Error Interrupt Request Status Register CAN1 Error Interrupt Request Mask Register 13-31 (CAN1ERIST) (CAN1ERIMK) 13-32 H'0080 1416 CAN1 Baud Rate Prescaler CAN1 Cause of Error Register 13-26 (CAN1BRP) (CAN1EF) 13-45 H'0080 1418 CAN1 Mode Register CAN1 DMA Transfer Request Select Register 13-47 (CAN1MOD) (CAN1DMARQ) 13-48 (Use inhibited area) H'0080 1428 CAN1 Global Mask Register Standard ID0 CAN1 Global Mask Register Standard ID1 13-49 (C1GMSKS0) (C1GMSKS1) H'0080 142A CAN1 Global Mask Register Extended ID0 CAN1 Global Mask Register Extended ID1 13-50 (C1GMSKE0) (C1GMSKE1) H'0080 142C CAN1 Global Mask Register Extended ID2 (Use inhibited area) 13-51 (C1GMSKE2) H'0080 142E (Use inhibited area) H'0080 1430 CAN1 Local Mask Register A Standard ID0 CAN1 Local Mask Register A Standard ID1 13-49 (C1LMSKAS0) (C1LMSKAS1) H'0080 1432 CAN1 Local Mask Register A Extended ID0 CAN1 Local Mask Register A Extended ID1 13-50 (C1LMSKAE0) (C1LMSKAE1) H'0080 1434 CAN1 Local Mask Register A Extended ID2 (Use inhibited area) 13-51 (C1LMSKAE2) H'0080 1436 (Use inhibited area) H'0080 1438 CAN1 Local Mask Register B Standard ID0 CAN1 Local Mask Register B Standard ID1 13-49 (C1LMSKBS0) (C1LMSKBS1) H'0080 143A CAN1 Local Mask Register B Extended ID0 CAN1 Local Mask Register B Extended ID1 13-50 (C1LMSKBE0) (C1LMSKBE1) H'0080 143C CAN1 Local Mask Register B Extended ID2 (Use inhibited area) 13-51 (C1LMSKBE2) H'0080 143E (Use inhibited area)

13-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN Module Related Register Map (7/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1440 CAN1 Single-Shot Mode Control Register 13-53 (CAN1SSMODE) H'0080 1442 (Use inhibited area) H'0080 1444 CAN1 Single-Shot Interrupt Request Status Register 13-33 (CAN1SSIST) H'0080 1446 (Use inhibited area) H'0080 1448 CAN1 Single-Shot Interrupt Request Mask Register 13-34 (CAN1SSIMK) (Use inhibited area) H'0080 1450 CAN1 Message Slot 0 Control Register CAN1 Message Slot 1 Control Register 13-54 (C1MSL0CNT) (C1MSL1CNT) H'0080 1452 CAN1 Message Slot 2 Control Register CAN1 Message Slot 3 Control Register 13-54 (C1MSL2CNT) (C1MSL3CNT) H'0080 1454 CAN1 Message Slot 4 Control Register CAN1 Message Slot 5 Control Register 13-54 (C1MSL4CNT) (C1MSL5CNT) H'0080 1456 CAN1 Message Slot 6 Control Register CAN1 Message Slot 7 Control Register 13-54 (C1MSL6CNT) (C1MSL7CNT) H'0080 1458 CAN1 Message Slot 8 Control Register CAN1 Message Slot 9 Control Register 13-54 (C1MSL8CNT) (C1MSL9CNT) H'0080 145A CAN1 Message Slot 10 Control Register CAN1 Message Slot 11 Control Register 13-54 (C1MSL10CNT) (C1MSL11CNT) H'0080 145C CAN1 Message Slot 12 Control Register CAN1 Message Slot 13 Control Register 13-54 (C1MSL12CNT) (C1MSL13CNT) H'0080 145E CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register 13-54 (C1MSL14CNT) (C1MSL15CNT) (Use inhibited area) H'0080 1500 CAN1 Message Slot 0 Standard ID0 CAN1 Message Slot 0 Standard ID1 13-58 (C1MSL0SID0) (C1MSL0SID1) 13-59 H'0080 1502 CAN1 Message Slot 0 Extended ID0 CAN1 Message Slot 0 Extended ID1 13-60 (C1MSL0EID0) (C1MSL0EID1) 13-61 H'0080 1504 CAN1 Message Slot 0 Extended ID2 CAN1 Message Slot 0 Data Length Register 13-62 (C1MSL0EID2) (C1MSL0DLC) 13-63 H'0080 1506 CAN1 Message Slot 0 Data 0 CAN1 Message Slot 0 Data 1 13-64 (C1MSL0DT0) (C1MSL0DT1) 13-65 H'0080 1508 CAN1 Message Slot 0 Data 2 CAN1 Message Slot 0 Data 3 13-66 (C1MSL0DT2) (C1MSL0DT3) 13-67 H'0080 150A CAN1 Message Slot 0 Data 4 CAN1 Message Slot 0 Data 5 13-68 (C1MSL0DT4) (C1MSL0DT5) 13-69 H'0080 150C CAN1 Message Slot 0 Data 6 CAN1 Message Slot 0 Data 7 13-70 (C1MSL0DT6) (C1MSL0DT7) 13-71 H'0080 150E CAN1 Message Slot 0 Timestamp 13-72 (C1MSL0TSP) H'0080 1510 CAN1 Message Slot 1 Standard ID0 CAN1 Message Slot 1 Standard ID1 13-58 (C1MSL1SID0) (C1MSL1SID1) 13-59 H'0080 1512 CAN1 Message Slot 1 Extended ID0 CAN1 Message Slot 1 Extended ID1 13-60 (C1MSL1EID0) (C1MSL1EID1) 13-61 H'0080 1514 CAN1 Message Slot 1 Extended ID2 CAN1 Message Slot 1 Data Length Register 13-62 (C1MSL1EID2) (C1MSL1DLC) 13-63 H'0080 1516 CAN1 Message Slot 1 Data 0 CAN1 Message Slot 1 Data 1 13-64 (C1MSL1DT0) (C1MSL1DT1) 13-65 H'0080 1518 CAN1 Message Slot 1 Data 2 CAN1 Message Slot 1 Data 3 13-66 (C1MSL1DT2) (C1MSL1DT3) 13-67 H'0080 151A CAN1 Message Slot 1 Data 4 CAN1 Message Slot 1 Data 5 13-68 (C1MSL1DT4) (C1MSL1DT5) 13-69 H'0080 151C CAN1 Message Slot 1 Data 6 CAN1 Message Slot 1 Data 7 13-70 (C1MSL1DT6) (C1MSL1DT7) 13-71 H'0080 151E CAN1 Message Slot 1 Timestamp 13-72 (C1MSL1TSP)

13 13.2 CAN Module Related Registers CAN MODULE 13-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN Module Related Register Map (8/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1520 CAN1 Message Slot 2 Standard ID0 CAN1 Message Slot 2 Standard ID1 13-58 (C1MSL2SID0) (C1MSL2SID1) 13-59 H'0080 1522 CAN1 Message Slot 2 Extended ID0 CAN1 Message Slot 2 Extended ID1 13-60 (C1MSL2EID0) (C1MSL2EID1) 13-61 H'0080 1524 CAN1 Message Slot 2 Extended ID2 CAN1 Message Slot 2 Data Length Register 13-62 (C1MSL2EID2) (C1MSL2DLC) 13-63 H'0080 1526 CAN1 Message Slot 2 Data 0 CAN1 Message Slot 2 Data 1 13-64 (C1MSL2DT0) (C1MSL2DT1) 13-65 H'0080 1528 CAN1 Message Slot 2 Data 2 CAN1 Message Slot 2 Data 3 13-66 (C1MSL2DT2) (C1MSL2DT3) 13-67 H'0080 152A CAN1 Message Slot 2 Data 4 CAN1 Message Slot 2 Data 5 13-68 (C1MSL2DT4) (C1MSL2DT5) 13-69 H'0080 152C CAN1 Message Slot 2 Data 6 CAN1 Message Slot 2 Data 7 13-70 (C1MSL2DT6) (C1MSL2DT7) 13-71 H'0080 152E CAN1 Message Slot 2 Timestamp 13-72 (C1MSL2TSP) H'0080 1530 CAN1 Message Slot 3 Standard ID0 CAN1 Message Slot 3 Standard ID1 13-58 (C1MSL3SID0) (C1MSL3SID1) 13-59 H'0080 1532 CAN1 Message Slot 3 Extended ID0 CAN1 Message Slot 3 Extended ID1 13-60 (C1MSL3EID0) (C1MSL3EID1) 13-61 H'0080 1534 CAN1 Message Slot 3 Extended ID2 CAN1 Message Slot 3 Data Length Register 13-62 (C1MSL3EID2) (C1MSL3DLC) 13-63 H'0080 1536 CAN1 Message Slot 3 Data 0 CAN1 Message Slot 3 Data 1 13-64 (C1MSL3DT0) (C1MSL3DT1) 13-65 H'0080 1538 CAN1 Message Slot 3 Data 2 CAN1 Message Slot 3 Data 3 13-66 (C1MSL3DT2) (C1MSL3DT3) 13-67 H'0080 153A CAN1 Message Slot 3 Data 4 CAN1 Message Slot 3 Data 5 13-68 (C1MSL3DT4) (C1MSL3DT5) 13-69 H'0080 153C CAN1 Message Slot 3 Data 6 CAN1 Message Slot 3 Data 7 13-70 (C1MSL3DT6) (C1MSL3DT7) 13-71 H'0080 153E CAN1 Message Slot 3 Timestamp 13-72 (C1MSL3TSP) H'0080 1540 CAN1 Message Slot 4 Standard ID0 CAN1 Message Slot 4 Standard ID1 13-58 (C1MSL4SID0) (C1MSL4SID1) 13-59 H'0080 1542 CAN1 Message Slot 4 Extended ID0 CAN1 Message Slot 4 Extended ID1 13-60 (C1MSL4EID0) (C1MSL4EID1) 13-61 H'0080 1544 CAN1 Message Slot 4 Extended ID2 CAN1 Message Slot 4 Data Length Register 13-62 (C1MSL4EID2) (C1MSL4DLC) 13-63 H'0080 1546 CAN1 Message Slot 4 Data 0 CAN1 Message Slot 4 Data 1 13-64 (C1MSL4DT0) (C1MSL4DT1) 13-65 H'0080 1548 CAN1 Message Slot 4 Data 2 CAN1 Message Slot 4 Data 3 13-66 (C1MSL4DT2) (C1MSL4DT3) 13-67 H'0080 154A CAN1 Message Slot 4 Data 4 CAN1 Message Slot 4 Data 5 13-68 (C1MSL4DT4) (C1MSL4DT5) 13-69 H'0080 154C CAN1 Message Slot 4 Data 6 CAN1 Message Slot 4 Data 7 13-70 (C1MSL4DT6) (C1MSL4DT7) 13-71 H'0080 154E CAN1 Message Slot 4 Timestamp 13-72 (C1MSL4TSP) H'0080 1550 CAN1 Message Slot 5 Standard ID0 CAN1 Message Slot 5 Standard ID1 13-58 (C1MSL5SID0) (C1MSL5SID1) 13-59 H'0080 1552 CAN1 Message Slot 5 Extended ID0 CAN1 Message Slot 5 Extended ID1 13-60 (C1MSL5EID0) (C1MSL5EID1) 13-61 H'0080 1554 CAN1 Message Slot 5 Extended ID2 CAN1 Message Slot 5 Data Length Register 13-62 (C1MSL5EID2) (C1MSL5DLC) 13-63 H'0080 1556 CAN1 Message Slot 5 Data 0 CAN1 Message Slot 5 Data 1 13-64 (C1MSL5DT0) (C1MSL5DT1) 13-65 H'0080 1558 CAN1 Message Slot 5 Data 2 CAN1 Message Slot 5 Data 3 13-66 (C1MSL5DT2) (C1MSL5DT3) 13-67 H'0080 155A CAN1 Message Slot 5 Data 4 CAN1 Message Slot 5 Data 5 13-68 (C1MSL5DT4) (C1MSL5DT5) 13-69 H'0080 155C CAN1 Message Slot 5 Data 6 CAN1 Message Slot 5 Data 7 13-70 (C1MSL5DT6) (C1MSL5DT7) 13-71 H'0080 155E CAN1 Message Slot 5 Timestamp 13-72 (C1MSL5TSP)

13-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN Module Related Register Map (9/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 1560 CAN1 Message Slot 6 Standard ID0 CAN1 Message Slot 6 Standard ID1 13-58 (C1MSL6SID0) (C1MSL6SID1) 13-59 H'0080 1562 CAN1 Message Slot 6 Extended ID0 CAN1 Message Slot 6 Extended ID1 13-60 (C1MSL6EID0) (C1MSL6EID1) 13-61 H'0080 1564 CAN1 Message Slot 6 Extended ID2 CAN1 Message Slot 6 Data Length Register 13-62 (C1MSL6EID2) (C1MSL6DLC) 13-63 H'0080 1566 CAN1 Message Slot 6 Data 0 CAN1 Message Slot 6 Data 1 13-64 (C1MSL6DT0) (C1MSL6DT1) 13-65 H'0080 1568 CAN1 Message Slot 6 Data 2 CAN1 Message Slot 6 Data 3 13-66 (C1MSL6DT2) (C1MSL6DT3) 13-67 H'0080 156A CAN1 Message Slot 6 Data 4 CAN1 Message Slot 6 Data 5 13-68 (C1MSL6DT4) (C1MSL6DT5) 13-69 H'0080 156C CAN1 Message Slot 6 Data 6 CAN1 Message Slot 6 Data 7 13-70 (C1MSL6DT6) (C1MSL6DT7) 13-71 H'0080 156E CAN1 Message Slot 6 Timestamp 13-72 (C1MSL6TSP) H'0080 1570 CAN1 Message Slot 7 Standard ID0 CAN1 Message Slot 7 Standard ID1 13-58 (C1MSL7SID0) (C1MSL7SID1) 13-59 H'0080 1572 CAN1 Message Slot 7 Extended ID0 CAN1 Message Slot 7 Extended ID1 13-60 (C1MSL7EID0) (C1MSL7EID1) 13-61 H'0080 1574 CAN1 Message Slot 7 Extended ID2 CAN1 Message Slot 7 Data Length Register 13-62 (C1MSL7EID2) (C1MSL7DLC) 13-63 H'0080 1576 CAN1 Message Slot 7 Data 0 CAN1 Message Slot 7 Data 1 13-64 (C1MSL7DT0) (C1MSL7DT1) 13-65 H'0080 1578 CAN1 Message Slot 7 Data 2 CAN1 Message Slot 7 Data 3 13-66 (C1MSL7DT2) (C1MSL7DT3) 13-67 H'0080 157A CAN1 Message Slot 7 Data 4 CAN1 Message Slot 7 Data 5 13-68 (C1MSL7DT4) (C1MSL7DT5) 13-69 H'0080 157C CAN1 Message Slot 7 Data 6 CAN1 Message Slot 7 Data 7 13-70 (C1MSL7DT6) (C1MSL7DT7) 13-71 H'0080 157E CAN1 Message Slot 7 Timestamp 13-72 (C1MSL7TSP) H'0080 1580 CAN1 Message Slot 8 Standard ID0 CAN1 Message Slot 8 Standard ID1 13-58 (C1MSL8SID0) (C1MSL8SID1) 13-59 H'0080 1582 CAN1 Message Slot 8 Extended ID0 CAN1 Message Slot 8 Extended ID1 13-60 (C1MSL8EID0) (C1MSL8EID1) 13-61 H'0080 1584 CAN1 Message Slot 8 Extended ID2 CAN1 Message Slot 8 Data Length Register 13-62 (C1MSL8EID2) (C1MSL8DLC) 13-63 H'0080 1586 CAN1 Message Slot 8 Data 0 CAN1 Message Slot 8 Data 1 13-64 (C1MSL8DT0) (C1MSL8DT1) 13-65 H'0080 1588 CAN1 Message Slot 8 Data 2 CAN1 Message Slot 8 Data 3 13-66 (C1MSL8DT2) (C1MSL8DT3) 13-67 H'0080 158A CAN1 Message Slot 8 Data 4 CAN1 Message Slot 8 Data 5 13-68 (C1MSL8DT4) (C1MSL8DT5) 13-69 H'0080 158C CAN1 Message Slot 8 Data 6 CAN1 Message Slot 8 Data 7 13-70 (C1MSL8DT6) (C1MSL8DT7) 13-71 H'0080 158E CAN1 Message Slot 8 Timestamp 13-72 (C1MSL8TSP) H'0080 1590 CAN1 Message Slot 9 Standard ID0 CAN1 Message Slot 9 Standard ID1 13-58 (C1MSL9SID0) (C1MSL9SID1) 13-59 H'0080 1592 CAN1 Message Slot 9 Extended ID0 CAN1 Message Slot 9 Extended ID1 13-60 (C1MSL9EID0) (C1MSL9EID1) 13-61 H'0080 1594 CAN1 Message Slot 9 Extended ID2 CAN1 Message Slot 9 Data Length Register 13-62 (C1MSL9EID2) (C1MSL9DLC) 13-63 H'0080 1596 CAN1 Message Slot 9 Data 0 CAN1 Message Slot 9 Data 1 13-64 (C1MSL9DT0) (C1MSL9DT1) 13-65 H'0080 1598 CAN1 Message Slot 9 Data 2 CAN1 Message Slot 9 Data 3 13-66 (C1MSL9DT2) (C1MSL9DT3) 13-67 H'0080 159A CAN1 Message Slot 9 Data 4 CAN1 Message Slot 9 Data 5 13-68 (C1MSL9DT4) (C1MSL9DT5) 13-69 H'0080 159C CAN1 Message Slot 9 Data 6 CAN1 Message Slot 9 Data 7 13-70 (C1MSL9DT6) (C1MSL9DT7) 13-71 H'0080 159E CAN1 Message Slot 9 Timestamp 13-72 (C1MSL9TSP)

13 13.2 CAN Module Related Registers CAN MODULE 13-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN Module Related Register Map (10/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 15A0 CAN1 Message Slot 10 Standard ID0 CAN1 Message Slot 10 Standard ID1 13-58 (C1MSL10SID0) (C1MSL10SID1) 13-59 H'0080 15A2 CAN1 Message Slot 10 Extended ID0 CAN1 Message Slot 10 Extended ID1 13-60 (C1MSL10EID0) (C1MSL10EID1) 13-61 H'0080 15A4 CAN1 Message Slot 10 Extended ID2 CAN1 Message Slot 10 Data Length Register 13-62 (C1MSL10EID2) (C1MSL10DLC) 13-63 H'0080 15A6 CAN1 Message Slot 10 Data 0 CAN1 Message Slot 10 Data 1 13-64 (C1MSL10DT0) (C1MSL10DT1) 13-65 H'0080 15A8 CAN1 Message Slot 10 Data 2 CAN1 Message Slot 10 Data 3 13-66 (C1MSL10DT2) (C1MSL10DT3) 13-67 H'0080 15AA CAN1 Message Slot 10 Data 4 CAN1 Message Slot 10 Data 5 13-68 (C1MSL10DT4) (C1MSL10DT5) 13-69 H'0080 15AC CAN1 Message Slot 10 Data 6 CAN1 Message Slot 10 Data 7 13-70 (C1MSL10DT6) (C1MSL10DT7) 13-71 H'0080 15AE CAN1 Message Slot 10 Timestamp 13-72 (C1MSL10TSP) H'0080 15B0 CAN1 Message Slot 11 Standard ID0 CAN1 Message Slot 11 Standard ID1 13-58 (C1MSL11SID0) (C1MSL11SID1) 13-59 H'0080 15B2 CAN1 Message Slot 11 Extended ID0 CAN1 Message Slot 11 Extended ID1 13-60 (C1MSL11EID0) (C1MSL11EID1) 13-61 H'0080 15B4 CAN1 Message Slot 11 Extended ID2 CAN1 Message Slot 11 Data Length Register 13-62 (C1MSL11EID2) (C1MSL11DLC) 13-63 H'0080 15B6 CAN1 Message Slot 11 Data 0 CAN1 Message Slot 11 Data 1 13-64 (C1MSL11DT0) (C1MSL11DT1) 13-65 H'0080 15B8 CAN1 Message Slot 11 Data 2 CAN1 Message Slot 11 Data 3 13-66 (C1MSL11DT2) (C1MSL11DT3) 13-67 H'0080 15BA CAN1 Message Slot 11 Data 4 CAN1 Message Slot 11 Data 5 13-68 (C1MSL11DT4) (C1MSL11DT5) 13-69 H'0080 15BC CAN1 Message Slot 11 Data 6 CAN1 Message Slot 11 Data 7 13-70 (C1MSL11DT6) (C1MSL11DT7) 13-71 H'0080 15BE CAN1 Message Slot 11 Timestamp 13-72 (C1MSL11TSP) H'0080 15C0 CAN1 Message Slot 12 Standard ID0 CAN1 Message Slot 12 Standard ID1 13-58 (C1MSL12SID0) (C1MSL12SID1) 13-59 H'0080 15C2 CAN1 Message Slot 12 Extended ID0 CAN1 Message Slot 12 Extended ID1 13-60 (C1MSL12EID0) (C1MSL12EID1) 13-61 H'0080 15C4 CAN1 Message Slot 12 Extended ID2 CAN1 Message Slot 12 Data Length Register 13-62 (C1MSL12EID2) (C1MSL12DLC) 13-63 H'0080 15C6 CAN1 Message Slot 12 Data 0 CAN1 Message Slot 12 Data 1 13-64 (C1MSL12DT0) (C1MSL12DT1) 13-65 H'0080 15C8 CAN1 Message Slot 12 Data 2 CAN1 Message Slot 12 Data 3 13-66 (C1MSL12DT2) (C1MSL12DT3) 13-67 H'0080 15CA CAN1 Message Slot 12 Data 4 CAN1 Message Slot 12 Data 5 13-68 (C1MSL12DT4) (C1MSL12DT5) 13-69 H'0080 15CC CAN1 Message Slot 12 Data 6 CAN1 Message Slot 12 Data 7 13-70 (C1MSL12DT6) (C1MSL12DT7) 13-71 H'0080 15CE CAN1 Message Slot 12 Timestamp 13-72 (C1MSL12TSP) H'0080 15D0 CAN1 Message Slot 13 Standard ID0 CAN1 Message Slot 13 Standard ID1 13-58 (C1MSL13SID0) (C1MSL13SID1) 13-59 H'0080 15D2 CAN1 Message Slot 13 Extended ID0 CAN1 Message Slot 13 Extended ID1 13-60 (C1MSL13EID0) (C1MSL13EID1) 13-61 H'0080 15D4 CAN1 Message Slot 13 Extended ID2 CAN1 Message Slot 13 Data Length Register 13-62 (C1MSL13EID2) (C1MSL13DLC) 13-63 H'0080 15D6 CAN1 Message Slot 13 Data 0 CAN1 Message Slot 13 Data 1 13-64 (C1MSL13DT0) (C1MSL13DT1) 13-65 H'0080 15D8 CAN1 Message Slot 13 Data 2 CAN1 Message Slot 13 Data 3 13-66 (C1MSL13DT2) (C1MSL13DT3) 13-67 H'0080 15DA CAN1 Message Slot 13 Data 4 CAN1 Message Slot 13 Data 5 13-68 (C1MSL13DT4) (C1MSL13DT5) 13-69 H'0080 15DC CAN1 Message Slot 13 Data 6 CAN1 Message Slot 13 Data 7 13-70 (C1MSL13DT6) (C1MSL13DT7) 13-71 H'0080 15DE CAN1 Message Slot 13 Timestamp 13-72 (C1MSL13TSP)

13-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN Module Related Register Map (11/11) Address +0 address +1 address See pages b0 b7 b8 b15 H'0080 15E0 CAN1 Message Slot 14 Standard ID0 CAN1 Message Slot 14 Standard ID1 13-58 (C1MSL14SID0) (C1MSL14SID1) 13-59 H'0080 15E2 CAN1 Message Slot 14 Extended ID0 CAN1 Message Slot 14 Extended ID1 13-60 (C1MSL14EID0) (C1MSL14EID1) 13-61 H'0080 15E4 CAN1 Message Slot 14 Extended ID2 CAN1 Message Slot 14 Data Length Register 13-62 (C1MSL14EID2) (C1MSL14DLC) 13-63 H'0080 15E6 CAN1 Message Slot 14 Data 0 CAN1 Message Slot 14 Data 1 13-64 (C1MSL14DT0) (C1MSL14DT1) 13-65 H'0080 15E8 CAN1 Message Slot 14 Data 2 CAN1 Message Slot 14 Data 3 13-66 (C1MSL14DT2) (C1MSL14DT3) 13-67 H'0080 15EA CAN1 Message Slot 14 Data 4 CAN1 Message Slot 14 Data 5 13-68 (C1MSL14DT4) (C1MSL14DT5) 13-69 H'0080 15EC CAN1 Message Slot 14 Data 6 CAN1 Message Slot 14 Data 7 13-70 (C1MSL14DT6) (C1MSL14DT7) 13-71 H'0080 15EE CAN1 Message Slot 14 Timestamp 13-72 (C1MSL14TSP) H'0080 15F0 CAN1 Message Slot 15 Standard ID0 CAN1 Message Slot 15 Standard ID1 13-58 (C1MSL15SID0) (C1MSL15SID1) 13-59 H'0080 15F2 CAN1 Message Slot 15 Extended ID0 CAN1 Message Slot 15 Extended ID1 13-60 (C1MSL15EID0) (C1MSL15EID1) 13-61 H'0080 15F4 CAN1 Message Slot 15 Extended ID2 CAN1 Message Slot 15 Data Length Register 13-62 (C1MSL15EID2) (C1MSL15DLC) 13-63 H'0080 15F6 CAN1 Message Slot 15 Data 0 CAN1 Message Slot 15 Data 1 13-64 (C1MSL15DT0) (C1MSL15DT1) 13-65 H'0080 15F8 CAN1 Message Slot 15 Data 2 CAN1 Message Slot 15 Data 3 13-66 (C1MSL15DT2) (C1MSL15DT3) 13-67 H'0080 15FA CAN1 Message Slot 15 Data 4 CAN1 Message Slot 15 Data 5 13-68 (C1MSL15DT4) (C1MSL15DT5) 13-69 H'0080 15FC CAN1 Message Slot 15 Data 6 CAN1 Message Slot 15 Data 7 13-70 (C1MSL15DT6) (C1MSL15DT7) 13-71 H'0080 15FE CAN1 Message Slot 15 Timestamp 13-72 (C1MSL15TSP) (Use inhibited area) H'0080 3FFE (Use inhibited area)

13 13.2 CAN Module Related Registers CAN MODULE 13-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.1 CAN Control Registers

CAN0 Control Register (CAN0CNT) <Address: H’0080 1000> CAN1 Control Register (CAN1CNT) <Address: H’0080 1400> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 FR STTSPTSRRB O BCM LBM RST 0 0 0 0 0 00 0 0 0 0 1 0 0 01 <Upon exiting reset: H’0011> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00

4 RBO 0: Enable normal operation R(Note 1)

Return bus off bit 1: Request clearing of error counter

5 TSR 0: Enable count operation R(Note 1)

Timestamp counter reset bit 1: Initialize count (to H’0000) 6–7 TSP 00: Select CAN bus bit clock R W Timestamp prescaler bit 01: Select CAN bus bit clock divided by 2 10: Select CAN bus bit clock divided by 3 11: Select CAN bus bit clock divided by 4 8-10 No function assigned. Fix to "0". 00

11 FRST 0: Negate reset R W

Forcible reset bit 1: Forcibly reset

12 BCM 0: Disable BasicCAN mode R W

BasicCAN mode bit 1: BasicCAN mode 13 No function assigned. Fix to "0". 00

14 LBM 0: Disable loopback function R W

Loopback mode bit 1: Enable loopback function

15 RST 0: Negate reset R W

CAN reset bit 1: Request reset Note 1: Only writing "1" is effective. Automatically cleared to "0" in hardware.

13-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (1) RBO (Return Bus Off) bit (Bit 4) Setting this bit to "1" clears the CAN Receive Error Count Register (CANnREC) and CAN Transmit Error Count Register (CANnTEC) to H'00 and forcibly places the CAN module into an error active state. This bit is cleared when the CAN module goes to an error active state. Note: Communication becomes possible when 11 consecutive recessive bits are detected on the CAN bus after clearing the error counters. (2) TSR (Timestamp Counter Reset) bit (Bit 5) Setting this bit to "1" clears the value of the CAN Timestamp Count Register (CANnTSTMP) to H’0000. This bit is cleared after the value of the CAN Timestamp Count Register (CANnTSTMP) is cleared to H’0000. (3) TSP (Timestamp Prescaler) bits (Bits 6–7) These bits select the count clock source for the timestamp counter. Note: Do not change settings of the TSP bits while CAN is operating (CAN Status Register CRS bit = "0"). (4) FRST (Forcible Reset) bit (Bit 11) When the FRST bit is set to "1", the CAN module is separated from the CAN bus and the protocol control unit is reset regardless of whether the CAN module currently is communicating. Up to 5 BCLK periods are required before the protocol control unit is reset after setting the FRST bit. Notes: In order for CAN communication to start, the FRST and RST bits must be cleared to "0". If the FRST bit is set to "1" during communication, the CTX pin output goes high immediately after that. Therefore, setting the FRST bit to "1" while sending CAN frame may cause a CAN bus error. The CAN Message Slot Control Register’s transmit/receive requests are not cleared for rea- sons that the FRST or RST bits are set. When the protocol control unit is reset by setting the FRST bit to "1", the CAN Timestamp Count and CAN Transmit/Receive Error Count Registers are initialized to "0". (5) BCM (BasicCAN Mode) bit (Bit 12) By setting this bit to "1", local slot 14 and 15 of the CAN module can be operated in BasicCAN mode.

Operation during BasicCAN mode During BasicCAN mode, two local slots—slots 14 and 15—are used as dual buffers, and the received frames with matching ID are stored alternately in slots 14 and 15 by acceptance filtering. Used for this acceptance filtering when slot 14 is active (next received frame to be stored in slot 14) are the ID set in slot 14 and local mask A, and those when slot 15 is active are the ID set in slot 15 and local mask B. Two types of frames—data frame and remote frame—can be received in this mode. By setting the same ID and the same mask register value for the two slots, the possibility of loosing messages when, for example, receiving frames which have many IDs may be reduced.

13 13.2 CAN Module Related Registers CAN MODULE 13-1732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

Procedure for entering BasicCAN mode Follow the procedure below during initialization: 1) Set the ID for slots 14 and 15 and the local mask registers A and B. (We recommend setting the same value.) 2) Set the frame types to be handled by slots 14 and 15 (standard or extended) in the CAN Extended ID Register. (We recommend setting the same type.) 3) Set the Message Slot Control Registers for slots 14 and 15 for data frame reception. 4) Set the BCM bit to "1". Notes: Do not change settings of the BCM bit while CAN is operating (CAN Status Register CRS bit = "0"). The first slot that is active after clearing the RST bit is slot 14. Even during BasicCAN mode, slots 0 to 13 can be used the same way as in normal operation. (6) LBM (Loopback Mode) bit (Bit 14) When the LBM bit is set to "1", if a receive slot exists whose ID matches that of the frame sent by the CAN module itself, then the frame can be received. Notes: ACK is not returned for the transmit frame. Do not change settings of the LBM bit while CAN is operating (CAN Status Register CRS bit = "0"). After complete sending Frame correctly, TSC bit in CAN status register (CANnSTAT) is "1", but RSC bit is not "1." And it is possible to symbiotic for transmit complete interrupt request and receive complete interrupt request. (7) RST (CAN Reset) bit (Bit 15) When the RST bit is cleared to "0", the CAN module is connected to the CAN bus and becomes ready to communicate after detecting 11 consecutive recessive bits. Also, the CAN Timestamp Count Register thereby starts counting. When the RST bit is set to "1", the bus will enter an idle state (detects 11 consecutive recessive bits) after sending frames from the slots which have transmit requests set by that time, then the protocol control unit is reset and the CAN module is disconnected from the CAN bus. Frames received during this time are pro- cessed normally. When setting RST bit to "1" under bus off state, it exits from bus off state after detecting 11 consecutive recessive bits on CAN bus 128 times, and then protocol control unit enters a reset state. To exit from bus off state forcibly, use either RBO bit or FRST bit. Notes: It is inhibited to set a new transmit request until the protocol control unit is reset (until the CAN Status Register CRS bit is set to "1") after setting the RST bit to "1." When the protocol control unit is reset by setting the RST bit to "1", the CAN Timestamp Count and CAN Transmit/Receive Error Count Registers are initialized to "0." In order for CAN communication to start, the FRST and RST bits must be cleared to "0."

13-1832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.2 CAN Status Registers

CAN0 Status Register (CAN0STAT) <Address: H’0080 1002> CAN1 Status Register (CAN1STAT) <Address: H’0080 1402> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 TSCRSCTSBRSBCRSLBSBCSCBSEPSBOS MSN 0 0000 0 0100000000 <Upon exiting reset: H’0100> b Bit Name Function R W 0 No function assigned. Fix to "0". 00

1 BOS 0: Not bus off R –

Bus off status bit 1: Bus off state

2 EPS 0: Not error passive R –

Error passive status bit 1: Error passive state

3 CBS 0: No error occurred R –

CAN bus error bit 1: Error occurred

4 BCS 0: Normal mode R –

BasicCAN status bit 1: BasicCAN mode 5 No function assigned. Fix to "0". 00

6 LBS 0: Normal mode R –

Loopback status bit 1: Loopback mode

7 CRS 0: Operating R –

CAN reset status bit 1: Reset

8 RSB 0: Not receiving R –

Receive status bit 1: Receiving

9 TSB 0: Not sending R –

Transmit status bit 1: Sending

10 RSC 0: Reception not completed R –

Reception completed status bit 1: Reception completed

11 TSC 0: Transmission not completed R –

Transmission completed status bit 1: Transmission completed 12–15 MSN Number of the message slot which has finished R – Message slot number bit sending or receiving 0000: Slot 0 0001: Slot 1 0010: Slot 2 0011: Slot 3 0100: Slot 4 0101: Slot 5 0110: Slot 6 0111: Slot 7 1000: Slot 8 1001: Slot 9 1010: Slot 10 1011: Slot 11 1100: Slot 12 1101: Slot 13 1110: Slot 14 1111: Slot 15

13 13.2 CAN Module Related Registers CAN MODULE 13-1932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (1) BOS (Bus Off Status) bit (Bit 1) When BOS bit = "1", it means that the CAN module is in a bus off state. [Set condition] This bit is set to "1" when the transmit error count register value exceeded 255 and a bus off state is entered. [Clear condition] This bit is cleared when restored from the bus off state. (2) EPS (Error Passive Status) bit (Bit 2) When EPS bit = "1", it means that the CAN module is in an error passive state. [Set condition] This bit is set to "1" when the transmit or receive error count register value exceeded 127 and an error passive state is entered. [Clear condition] This bit is cleared when restored from the error passive state. (3) CBS (CAN Bus Error) bit (Bit 3) [Set condition] This bit is set to "1" when an error is detected on the CAN bus. [Clear condition] This bit is cleared when the CAN module finished sending or receiving normally. (4) BCS (BasicCAN Status) bit (Bit 4) When BCS bit = "1", it means that the CAN module is operating in BasicCAN mode. [Set condition] This bit is set to "1" when the CAN module is operating in BasicCAN mode. BasicCAN mode is useful when the following conditions are met: CAN Control Register BCM bit = "1" Slots 14 and 15 both are set for data frame reception [Clear condition] This bit is cleared by clearing the BCM bit to "0". (5) LBS (Loopback Status) bit (Bit 6) When LBS bit = "1", it means that the CAN module is operating in loopback mode. [Set condition] This bit is set to "1" by setting the CAN Control Register LBM (loopback mode) bit to "1". [Clear condition] This bit is cleared by clearing the LBM bit to "0".

13-2032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (6) CRS (CAN Reset Status) bit (Bit 7) When CRS bit = "1", it means that the protocol control unit is in a reset state. [Set condition] This bit is set to "1" when the CAN protocol control unit is in a reset state. [Clear condition] This bit is cleared by clearing the CAN Control Register RST (CAN reset) and FRST bits to "0". However, it requires one bit of set baud rate worth of time to have CRS bit cleared to "0" after RST bit and FRST bit are cleared to "0." (7) RSB (Receive Status) bit (Bit 8) [Set condition] This bit is set to "1" when the CAN module is operating as a receive node. [Clear condition] This bit is cleared when the CAN module starts operating as a transmit node or enters a bus idle state. (8) TSB (Transmit Status) bit (Bit 9) [Set condition] This bit is set to "1" when the CAN module is operating as a transmit node. [Clear condition] This bit is cleared when the CAN module starts operating as a receive node or enters a bus idle state. (9) RSC (Reception Completed Status) bit (Bit 10) [Set condition] This bit is set to "1" when the CAN module has finished receiving normally (regardless of whether there is any slot that meets receive conditions). [Clear condition] This bit is cleared when the CAN module has finished sending normally. (10) TSC (Transmission Completed Status) bit (Bit 11) [Set condition] This bit is set to "1" when the CAN module has finished sending normally. [Clear condition] This bit is cleared when the CAN module has finished receiving normally. (11) MSN (Message Slot Number) bits (Bits 12–15) These bits indicate the relevant slot number when the CAN module has finished sending or finished storing the received data. These bits cannot be cleared to "0" in software. Note: When CAN module receives the frame that is transmitted by the CAN module itself during loopback mode, the MSN bits indicate the transmit slot number.

13 13.2 CAN Module Related Registers CAN MODULE 13-2132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.3 CAN Extended ID Registers

CAN0 Extended ID Register (CAN0EXTID) <Address: H’0080 1004> CAN1 Extended ID Register (CAN1EXTID) <Address: H’0080 1404> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 IDE0 IDE1 IDE2 IDE3 IDE4 IDE6 IDE7 IDE8 IDE9 IDE10 IDE11 IDE12 IDE13 IDE14 IDE15IDE5 0000000000000000 <Upon exiting reset: H’0000> b Bit Name Function R W

0 IDE0 (slot 0 extended format bit) 0: Standard ID format R W

1 IDE1 (slot 1 extended format bit) 1: Extended ID format

2 IDE2 (slot 2 extended format bit)

3 IDE3 (slot 3 extended format bit)

4 IDE4 (slot 4 extended format bit)

5 IDE5 (slot 5 extended format bit)

6 IDE6 (slot 6 extended format bit)

7 IDE7 (slot 7 extended format bit)

8 IDE8 (slot 8 extended format bit)

9 IDE9 (slot 9 extended format bit)

10 IDE10 (slot 10 extended format bit)

11 IDE11 (slot 11 extended format bit)

12 IDE12 (slot 12 extended format bit)

13 IDE13 (slot 13 extended format bit)

14 IDE14 (slot 14 extended format bit)

15 IDE15 (slot 15 extended format bit)

This register selects the format of frames handled by message slots corresponding to the respective bits in the register. Setting any bit in this register to "0" selects the standard ID format, and setting any bit in this register to "1" selects the extended ID format. Note: Settings of any bit in this register can only be changed when the corresponding slot does not have transmit or receive requests set.

13-2232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.4 CAN Configuration Registers

CAN0 Configuration Register (CAN0CONF) <Address: H'0080 1006> CAN1 Configuration Register (CAN1CONF) <Address: H'0080 1406> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 SAMPRBPH1PH2SJW 000000000000 0 0 0 0 <Upon exiting reset: H’0000> b Bit Name Function R W 0–1 SJW 00: SJW = 1Tq R W reSynchronization Jump Width setting bit 01: SJW = 2Tq 10: SJW = 3Tq 11: SJW = 4Tq 2–4 PH2 000: Phase Segment2 = 1Tq R W Phase Segment2 setting bit 001: Phase Segment2 = 2Tq 010: Phase Segment2 = 3Tq 011: Phase Segment2 = 4Tq 100: Phase Segment2 = 5Tq 101: Phase Segment2 = 6Tq 110: Phase Segment2 = 7Tq 111: Phase Segment2 = 8Tq 5–7 PH1 000: Phase Segment1 = 1Tq R W Phase Segment1 setting bit 001: Phase Segment1 = 2Tq 010: Phase Segment1 = 3Tq 011: Phase Segment1 = 4Tq 100: Phase Segment1 = 5Tq 101: Phase Segment1 = 6Tq 110: Phase Segment1 = 7Tq 111: Phase Segment1 = 8Tq 8–10 PRB 000: Propagation Segment = 1Tq R W Propagation Segment setting bit 001: Propagation Segment = 2Tq 010: Propagation Segment = 3Tq 011: Propagation Segment = 4Tq 100: Propagation Segment = 5Tq 101: Propagation Segment = 6Tq 110: Propagation Segment = 7Tq 111: Propagation Segment = 8Tq

11 SAM 0: Sampled one time R W

Sampling count select bit 1: Sampled three times 12–15 No function assigned. Fix to "0". 00 Notes: Do not change settings of the CAN Configuration Register (CAN0CONF or CAN1CONF) during CAN operation (CAN Status Register CRS bit = "0"). Bit configuration is specified by the CAN protocol specification in such a way that it satisfies the conditions given below: Number of Tq’s for one bit: 8–25 Tq’s SJW ≤ min (Phase Segment1, Phase Segment2) Phase Segment2 = max (Phase Segment1, IPT) where IPT = 1 for the internal CAN modules of the 32176 min() is the function that returns the smaller of two values; max() is the function that returns the maximum value. * IPT is an abbreviation for Information Processing Time, which is the time immediately after the sampling point.

13 13.2 CAN Module Related Registers CAN MODULE 13-2332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (1) SJW bits (Bits 0–1) These bits set the reSynchronization Jump Width. (2) PH2 bits (Bits 2–4) These bits set the width of Phase Segment2. (3) PH1 bits (Bits 5–7) These bits set the width of Phase Segment1. (4) PRB bits (Bits 8–10) These bits set the width of Propagation Segment. (5) SAM bit (Bit 11) This bit sets the number of times each bit is sampled. When SAM = "0", the value sampled at the end of Phase Segment1 is assumed to be the value of the bit. When SAM = "1", the value of the bit is determined by a majority circuit from three sampled values, each sampled 2 Tq’s before, 1 Tq before, and at the end of Phase Segment1. Table 13.2.1 Typical Settings of Bit Timing when CPU Clock = 40 MHz Baud Rate BRP Set Value Tq Period (ns) No. of Tq’s in 1 Bit PROP + PH1 PH2 Sampling Point 1M bps 1 50 20 13 6 70% 3 100 10 7 2 80% 3 100 10 6 3 70% 3 100 10 5 4 60% 4 125 8 5 2 75% 4 125 8 4 3 63% 500K bps 4 125 16 13 2 88% (Note 1) 4 125 16 12 3 81% (Note 1) 4 125 16 11 4 75% 7 200 10 7 2 80% 7 200 10 6 3 70% 7 200 10 5 4 60% 9 250 8 5 2 75% 9 250 8 4 3 63% Note 1: PH2 = max (PH1, IPT), that is specified in CAN protocol, cannot be met. Note: . It does not mean that the communication at the above baud rate settings is guaranteed. Sufficient evaluation and verification are required before use. Table 13.2.2 Typical Settings of Bit Timing when CPU Clock = 32 MHz Baud Rate BRP Set Value Tq Period (ns) No. of Tq’s in 1 Bit PROP + PH1 PH2 Sampling Point 1M bps 1 62.5 16 10 5 69% 3 125 8 5 2 75% 3 125 8 4 3 63% 500K bps 3 125 16 13 2 88% (Note 1) 3 125 16 11 4 75% 7 250 8 5 2 75% 7 250 8 4 3 63% Note 1: PH2 = max (PH1, IPT), that is specified in CAN protocol, cannot be met. Note: . It does not mean that the communication at the above baud rate settings is guaranteed. Sufficient evaluation and verification are required before use.

13-2432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.5 CAN Timestamp Count Registers

CAN0 Timestamp Count Register (CAN0TSTMP) <Address: H’0080 1008> CAN1 Timestamp Count Register (CAN1TSTMP) <Address: H’0080 1408> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 CANTSTMP 0000000000000000 <Upon exiting reset: H’0000> b Bit Name Function R W 0–15 CANTSTMP 16-bit timestamp count value R – The CAN module contains a 16-bit up-count register. The count period can be selected from the CAN bus bit period divided by 1, 2, 3 or 4 by setting the CAN Control Register (CANnCNT) TSP (Timestamp Prescaler) bits. When the CAN module finishes sending or receiving, it captures the count register value and stores the value in a message slot. The counter is made to start counting by clearing the CAN Control Register (CANnCNT) RST bit to "0". Notes: The CAN protocol control unit can be reset and the counter initialized to H’0000 by setting the CAN Control Register (CANnCNT) RST (CAN Reset) bit to "1". Or the counter can be initial- ized to H’0000 while the CAN module remains operating by setting the TSR (Timestamp Counter Reset) bit to "1". If any slot with the matching ID exists during loopback mode, the CAN module stores the timestamp value in that slot when it finished receiving. (No timestamp values are stored this way when the CAN module finished sending.) The count period of the CAN Timestamp Count Register varies with the CAN resynchronization function.

13 13.2 CAN Module Related Registers CAN MODULE 13-2532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.6 CAN Error Count Registers

CAN0 Receive Error Count Register (CAN0REC) <Address: H’0080 100A> CAN1 Receive Error Count Register (CAN1REC) <Address: H’0080 140A> 123456 b 7b0 REC 00000000 <Upon exiting reset: H’00> b Bit Name Function R W 0–7 REC Receive error count value R – During an error active/error passive state, a receive error count value is stored in this register. The count is decremented when frames are received normally or incremented when an error occurred. If the CAN module finished receiving normally when REC ≥ 128 (error passive), REC is set to 127. During a bus off state, an undefined value is stored in this register. The count is reset to H’00 upon returning to an error active state. CAN0 Transmit Error Count Register (CAN0TEC) <Address: H’0080 100B> CAN1 Transmit Error Count Register (CAN1TEC) <Address: H’0080 140B> 9 10 11 12 13 14 b15b8 TEC 00000000 <Upon exiting reset: H’00> b Bit Name Function R W 8–15 TEC Transmit error count value R – During an error active/error passive state, a transmit error count value is stored in this register. The count is decremented when frames are transmitted normally or incremented when an error occurred. During a bus off state, an undefined value is stored in this register. The count is reset to H’00 upon returning to an error active state.

13-2632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.7 CAN Baud Rate Prescalers

CAN0 Baud Rate Prescaler (CAN0BRP) <Address: H’0080 1016> CAN1 Baud Rate Prescaler (CAN1BRP) <Address: H’0080 1416> 123456 b 7b0 BRP 00000001 <Upon exiting reset: H’01> b Bit Name Function R W 0–7 BRP Baud rate prescaler value R W This register sets the Tq period of CAN. The CAN baud rate is determined by (Tq period × number of Tq’s in one bit). Tq period = (BRP + 1) / (CPU clock) CAN transfer baud rate = 1 Tq period × number of Tq’s in one bit Number of Tq’s in one bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 Notes: Setting H’00 (divide by 1) is inhibited. Do not change settings of the CAN Baud Rate Prescaler (CANnBRP) during CAN operation (CAN Status Register CRS bit = "0").

13 13.2 CAN Module Related Registers CAN MODULE 13-2732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.8 CAN Interrupt Related Registers

The CAN interrupt related registers are used to control the interrupt request signals output to the Interrupt Con- troller by CAN. (1) Interrupt request status bit This status bit is used to determine whether an interrupt is requested. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this bit is unaffected by the interrupt request enable bit, it can also be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "1" to enable interrupt requests or "0" to disable interrupt requests. Figure 13.2.1 Interrupt Request Status and Mask Registers To the Interrupt Controller Interrupt request from each peripheral function Interrupt request status Data bus Set Group interrupt Interrupt request enable clear F/F F/F Data = 0

13-2832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 13.2.2 Example for Clearing Interrupt Request Status b4 5 b7 Interrupt request status Initial state Event occurs on bit 6 Interrupt request Event occurs on bit 4 Only bit 6 cleared Bit 4 data retained b4 5 b7 1 1 0 1 Write to the interrupt request status Example for clearing interrupt request status 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 Program example ISTREG = 0xfd; /* Clear ISTAT1 (0x02 bit) only */ To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit) To clear an interrupt request status, always be sure to write 1 to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. b4 5 6 b7 Interrupt request status Event occurs on bit 6 Event occurs on bit 4 Only bit 6 cleared Bit 4 also cleared 0 0 1 0 1 0 1 0 0 0 0 0 Read 0 0 1 0 0 0 0 0 Clear bit 6 (AND'ing with 1101) Write ISTREG &= 0xfd; /* Clear ISTAT1 (0x02 bit) only */

13 13.2 CAN Module Related Registers CAN MODULE 13-2932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Slot Interrupt Request Status Register (CAN0SLIST) <Address: H’0080 100C> CAN1 Slot Interrupt Request Status Register (CAN1SLIST) <Address: H’0080 140C> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 SSB0 SSB1 SSB2 SSB3 SSB4 SSB6 SSB7 SSB8 SSB9 SSB10 SSB11 SSB12 SSB13 SSB14 SSB15SSB5 0000000000000000 <Upon exiting reset: H’0000> b Bit Name Function R W

0 SSB0 (slot 0 interrupt request status bit) 0: Interrupt not requested R(Note 1)

1 SSB1 (slot 1 interrupt request status bit) 1: Interrupt requested

2 SSB2 (slot 2 interrupt request status bit)

3 SSB3 (slot 3 interrupt request status bit)

4 SSB4 (slot 4 interrupt request status bit)

5 SSB5 (slot 5 interrupt request status bit)

6 SSB6 (slot 6 interrupt request status bit)

7 SSB7 (slot 7 interrupt request status bit)

8 SSB8 (slot 8 interrupt request status bit)

9 SSB9 (slot 9 interrupt request status bit)

10 SSB10 (slot 10 interrupt request status bit)

11 SSB11 (slot 11 interrupt request status bit)

12 SSB12 (slot 12 interrupt request status bit)

13 SSB13 (slot 13 interrupt request status bit)

14 SSB14 (slot 14 interrupt request status bit)

15 SSB15 (slot 15 interrupt request status bit)

Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write. When using CAN interrupts, this register helps to know which slot requested an interrupt.

Slots set for transmission The corresponding bit is set to "1" when the CAN module finished sending. This bit is cleared by writing "0" in software.
Slots set for reception The corresponding bit is set to "1" when the CAN module finished receiving and finished storing the re- ceived message in the message slot. This bit is cleared by writing "0" in software. When writing to the CAN slot interrupt request status, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write. Notes: If the automatic response function is enabled for remote frame receive slots, the request status is set after the CAN module finished receiving a remote frame and after it finished sending a data frame. For remote frame transmit slots, the request status is set after the CAN module finished send- ing a remote frame and after it finished receiving a data frame. If the request status is set by an interrupt request at the same time it is cleared in software, the former has priority so that the request status is set.

13-3032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Slot Interrupt Request Mask Register (CAN0SLIMK) <Address: H’0080 1010> CAN1 Slot Interrupt Request Mask Register (CAN1SLIMK) <Address: H’0080 1410> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 IRB0 IRB1 IRB2 IRB3 IRB4 IRB6 IRB7 IRB8 IRB9 IRB10 IRB11 IRB12 IRB13 IRB14 IRB15IRB5 0000000000000000 <Upon exiting reset: H’0000> b Bit Name Function R W

0 IRB0 (slot 0 interrupt request mask bit) 0: Mask (disable) interrupt request R W

1 IRB1 (slot 1 interrupt request mask bit) 1: Enable interrupt request

2 IRB2 (slot 2 interrupt request mask bit)

3 IRB3 (slot 3 interrupt request mask bit)

4 IRB4 (slot 4 interrupt request mask bit)

5 IRB5 (slot 5 interrupt request mask bit)

6 IRB6 (slot 6 interrupt request mask bit)

7 IRB7 (slot 7 interrupt request mask bit)

8 IRB8 (slot 8 interrupt request mask bit)

9 IRB9 (slot 9 interrupt request mask bit)

10 IRB10 (slot 10 interrupt request mask bit)

11 IRB11 (slot 11 interrupt request mask bit)

12 IRB12 (slot 12 interrupt request mask bit)

13 IRB13 (slot 13 interrupt request mask bit)

14 IRB14 (slot 14 interrupt request mask bit)

15 IRB15 (slot 15 interrupt request mask bit)

This register is used to enable or disable the interrupt requests that will be generated when data transmission or reception in each corresponding slot is completed. Setting IRBn (n = 0–15) to "1" enables the interrupt request to be generated when data transmission or reception in the corresponding slot is completed. The CAN Slot Interrupt Request Status Register (CANnSLIST) helps to know which slot requested the interrupt.

13 13.2 CAN Module Related Registers CAN MODULE 13-3132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Error Interrupt Request Status Register (CAN0ERIST) <Address: H’0080 1014> CAN1 Error Interrupt Request Status Register (CAN1ERIST) <Address: H’0080 1414> 123456 b 7b0 EIS PIS OIS 0000 0 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 0–4 No function assigned. Fix to "0". 00

5 EIS 0: Interrupt not requested R(Note 1)

CAN bus error interrupt request status bit 1: Interrupt requested

6 PIS

Error passive interrupt request status bit

7 OIS

Bus off interrupt request status bit Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write. When using CAN interrupts, if the interrupt request sources are associated with errors, this register helps to know which source generated the interrupt. (1) EIS (CAN Bus Error Interrupt Request Status) bit (Bit 5) The EIS bit is set to "1" when a communication error is detected. This bit is cleared by writing "0" in software. (2) PIS (Error Passive Interrupt Request Status) bit (Bit 6) The PIS bit is set to "1" when the CAN module goes to an error passive state. This bit is cleared by writing "0" in software. (3) OIS (Bus Off Interrupt Request Status) bit (Bit 7) The OIS bit is set to "1" when the CAN module goes to a bus off passive state. This bit is cleared by writing "0" in software. When writing to the CAN error interrupt request status, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write.

13-3232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Error Interrupt Request Mask Register (CAN0ERIMK) <Address: H’0080 1015> CAN1 Error Interrupt Request Mask Register (CAN1ERIMK) <Address: H’0080 1415> 9 10 11 12 13 14 b15b8 EIM PIM OIM 0000 0 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 8–12 No function assigned. Fix to "0". 00

13 EIM 0: Mask (disable) interrupt request R W

CAN bus error interrupt request mask bit 1: Enable interrupt request

14 PIM

Error passive interrupt request mask bit

15 OIM

Bus off interrupt request mask bit (1) EIM (CAN Bus Error Interrupt Request Mask) bit (Bit 13) The EIM bit enables or disables the interrupt requests to be generated when CAN bus errors occurred. CAN bus error interrupt requests are enabled by setting this bit to "1". (2) PIM (Error Passive Interrupt Request Mask) bit (Bit 14) The PIM bit enables or disables the interrupt requests to be generated when the CAN module entered an error passive state. Error passive interrupt requests are enabled by setting this bit to "1". (3) OIM (Bus Off Interrupt Request Mask) bit (Bit 15) The OIM bit enables or disables the interrupt requests to be generated when the CAN module entered a bus off state. Bus off interrupt requests are enabled by setting this bit to "1".

13 13.2 CAN Module Related Registers CAN MODULE 13-3332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Single-Shot Interrupt Request Status Register (CAN0SSIST) <address: H’0080 1044> CAN1 Single-Shot Interrupt Request Status Register (CAN1SSIST) <Address: H’0080 1444> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 SSIST0 SSIST1 SSIST2 SSIST3 SSIST4 SSIST5 SSIST6 SSIST7 SSIST8 SSIST9 SSIST10 SSIST11 SSIST12 SSIST13 SSIST14 SSIST15 0000000000000000 <Upon exiting reset: H’0000> b Bit Name Function R W

0 SSIST0 0: No arbitration-lost or transmit error R(Note 1)

Slot 0 single-shot interrupt request status bit 1: Arbitration-lost or transmit error occurred

1 SSIST1

Slot 1 single-shot interrupt request status bit

2 SSIST2

Slot 2 single-shot interrupt request status bit

3 SSIST3

Slot 3 single-shot interrupt request status bit

4 SSIST4

Slot 4 single-shot interrupt request status bit

5 SSIST5

Slot 5 single-shot interrupt request status bit

6 SSIST6

Slot 6 single-shot interrupt request status bit

7 SSIST7

Slot 7 single-shot interrupt request status bit

8 SSIST8

Slot 8 single-shot interrupt request status bit

9 SSIST9

Slot 9 single-shot interrupt request status bit

10 SSIST10

Slot 10 single-shot interrupt request status bit

11 SSIST11

Slot 11 single-shot interrupt request status bit

12 SSIST12

Slot 12 single-shot interrupt request status bit

13 SSIST13

Slot 13 single-shot interrupt request status bit

14 SSIST14

Slot 14 single-shot interrupt request status bit

15 SSIST15

Slot 15 single-shot interrupt request status bit Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write. If transmission in any slot failed for reasons of a detection of arbitration-lost or a transmit error while operating Single-shot mode, the corresponding bit in this register is set to "1". The bit is cleared by writing "0" in software. Furthermore, if the corresponding bit in the CAN single-shot interrupt request mask register has been set to "1", an interrupt request can be generated when transmission failed. When writing to the CAN single-shot interrupt request status, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write.

13-3432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Single-Shot Interrupt Request Mask Register (CAN0SSIMK) <Address: H’0080 1048> CAN1 Single-Shot Interrupt Request Mask Register (CAN1SSIMK) <Address: H’0080 1448> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 SSIMK0 SSIMK1 SSIMK2 SSIMK3 SSIMK4 SSIMK5 SSIMK6 SSIMK7 SSIMK8 SSIMK9 SSIMK10 SSIMK11 SSIMK12 SSIMK13 SSIMK14 SSIMK15 0000000000000000 <Upon exiting reset: H’0000> b Bit Name Function R W

0 SSIMK0 0: Disable interrupt request R W

Slot 0 single-shot interrupt request mask bit 1: Enable interrupt request

1 SSIMK1

Slot 1 single-shot interrupt request mask bit

2 SSIMK2

Slot 2 single-shot interrupt request mask bit

3 SSIMK3

Slot 3 single-shot interrupt request mask bit

4 SSIMK4

Slot 4 single-shot interrupt request mask bit

5 SSIMK5

Slot 5 single-shot interrupt request mask bit

6 SSIMK6

Slot 6 single-shot interrupt request mask bit

7 SSIMK7

Slot 7 single-shot interrupt request mask bit

8 SSIMK8

Slot 8 single-shot interrupt request mask bit

9 SSIMK9

Slot 9 single-shot interrupt request mask bit

10 SSIMK10

Slot 10 single-shot interrupt request mask bit

11 SSIMK11

Slot 11 single-shot interrupt request mask bit

12 SSIMK12

Slot 12 single-shot interrupt request mask bit

13 SSIMK13

Slot 13 single-shot interrupt request mask bit

14 SSIMK14

Slot 14 single-shot interrupt request mask bit

15 SSIMK15

Slot 15 single-shot interrupt request mask bit This register is used to enable or disable the interrupt requests that will be generated when transmission in each corresponding slot has failed. Setting any bit in this register to "1" enables the interrupt request to be generated when transmission in the corresponding slot (in single-shot mode only) has failed. The CAN Single- Shot Interrupt Request Status Register helps to know which slot requested the interrupt.

13 13.2 CAN Module Related Registers CAN MODULE 13-3532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 F/F F/F F/F F/F F/F F/F F/F F/F IRB7 SSB7 IRB6 SSB6 IRB5 SSB5 IRB4 SSB4 F/F F/F IRB3 SSB3 F/F F/F IRB2 SSB2 F/F F/F IRB1 SSB1 F/F F/F IRB0 SSB0 Data bus Slot 0 transmission/reception completed Slot 1 transmission/reception completed Slot 2 transmission/reception completed Slot 3 transmission/reception completed Slot 4 transmission/reception completed Slot 5 transmission/reception completed Slot 6 transmission/reception completed Slot 7 transmission/reception completed To the remaining 27-source inputs in the succeeding pages CAN0 transmit/receive & error interrupt request(Level) 35-source inputs CAN0SLIST (H'0080 100C) CAN0SLIMK (H'0080 1010) Figure 13.2.3 Block Diagram of CAN0 Transmit/Receive & Error Interrupt Requests (1/5)

13-3632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 F/F F/F F/F F/F F/F F/F F/F F/F IRB15 SSB15 IRB14 SSB14 IRB13 SSB13 IRB12 SSB12 F/F F/F IRB11 SSB11 F/F F/F IRB10 SSB10 F/F F/F IRB9 SSB9 F/F F/F IRB8 SSB8 b15 b15 b14 b14 b13 b13 b12 b12 b11 b11 b10 b10 Data bus Slot 8 transmission/reception completed Slot 9 transmission/reception completed Slot 10 transmission/reception completed Slot 11 transmission/reception completed Slot 12 transmission/reception completed Slot 13 transmission/reception completed Slot 14 transmission/reception completed Slot 15 transmission/reception completed To the preceding page(Level) 27-source inputs CAN0SLIST (H'0080 100C) CAN0SLIMK (H'0080 1010) To the remaining 19-source inputs in the succeeding pages Figure 13.2.4 Block Diagram of CAN0 Transmit/Receive & Error Interrupt Requests (2/5)

13 13.2 CAN Module Related Registers CAN MODULE 13-3732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 13.2.5 Block Diagram of CAN0 Transmit/Receive & Error Interrupt Requests (3/5) F/F F/F OIM OIS F/F F/F PIM PIS F/F F/F EIM EIS b15 b14 b13 Data bus CAN bus error occurs Go to error passive state Go to bus off state To the preceding page(Level) 19-source inputs CAN0ERIST (H'0080 1014) CAN0ERIMK (H'0080 1015) To the remaining 16-source inputs in the succeeding pages

13-3832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 F/F F/F F/F F/F F/F F/F F/F F/F SSIMK7 SSIST7 SSIMK6 SSIST6 SSIMK5 SSIST5 SSIMK4 SSIST4 F/F F/F SSIMK3 SSIST3 F/F F/F SSIMK2 SSIST2 F/F F/F SSIMK1 SSIST1 F/F F/F SSIMK0 SSIST0 Data bus Slot 0 arbitration-lost/transmit error occurs Slot 1 arbitration-lost/transmit error occurs Slot 2 arbitration-lost/transmit error occurs Slot 3 arbitration-lost/transmit error occurs Slot 4 arbitration-lost/transmit error occurs Slot 5 arbitration-lost/transmit error occurs Slot 6 arbitration-lost/transmit error occurs Slot 7 arbitration-lost/transmit error occurs To the preceding page(Level) 16-source inputs CAN0SSIST (H'0080 1044) CAN0SSIMK (H'0080 1048) To the remaining 8-source inputs in the next page Figure 13.2.6 Block Diagram of CAN0 Transmit/Receive & Error Interrupt Requests (4/5)

13 13.2 CAN Module Related Registers CAN MODULE 13-3932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 13.2.7 Block Diagram of CAN0 Transmit/Receive & Error Interrupt Requests (5/5) F/F F/F F/F F/F F/F F/F F/F F/F SSIMK15 SSIST15 SSIMK14 SSIST14 SSIMK13 SSIST13 SSIMK12 SSIST12 F/F F/F SSIMK11 SSIST11 F/F F/F SSIMK10 SSIST10 F/F F/F SSIMK9 SSIST9 F/F F/F SSIMK8 SSIST8 b15 b15 b14 b14 b13 b13 b12 b12 b11 b11 b10 b10 Data bus Slot 8 arbitration-lost/transmit error occurs Slot 9 arbitration-lost/transmit error occurs Slot 10 arbitration-lost/transmit error occurs Slot 11 arbitration-lost/transmit error occurs Slot 12 arbitration-lost/transmit error occurs Slot 13 arbitration-lost/transmit error occurs Slot 14 arbitration-lost/transmit error occurs Slot 15 arbitration-lost/transmit error occurs To the preceding page(Level) 8-source inputs CAN0SSIST (H'0080 1044) CAN0SSIMK (H'0080 1048)

13-4032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 13.2.8 Block Diagram of CAN1 Transmit/Receive & Error Interrupt Requests (1/5) F/F F/F F/F F/F F/F F/F F/F F/F IRB7 SSB7 IRB6 SSB6 IRB5 SSB5 IRB4 SSB4 F/F F/F IRB3 SSB3 F/F F/F IRB2 SSB2 F/F F/F IRB1 SSB1 F/F F/F IRB0 SSB0 Data bus Slot 0 transmission/reception completed Slot 1 transmission/reception completed Slot 2 transmission/reception completed Slot 3 transmission/reception completed Slot 4 transmission/reception completed Slot 5 transmission/reception completed Slot 6 transmission/reception completed Slot 7 transmission/reception completed To the remaining 27-source inputs in the succeeding pages CAN1 transmit/receive & error interrupt request(Level) 35-source inputs CAN1SLIST (H'0080 140C) CAN1SLIMK (H'0080 1410)

13 13.2 CAN Module Related Registers CAN MODULE 13-4132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 F/F F/F F/F F/F F/F F/F F/F F/F IRB15 SSB15 IRB14 SSB14 IRB13 SSB13 IRB12 SSB12 F/F F/F IRB11 SSB11 F/F F/F IRB10 SSB10 F/F F/F IRB9 SSB9 F/F F/F IRB8 SSB8 b15 b15 b14 b14 b13 b13 b12 b12 b11 b11 b10 b10 Data bus Slot 8 transmission/reception completed Slot 9 transmission/reception completed Slot 10 transmission/reception completed Slot 11 transmission/reception completed Slot 12 transmission/reception completed Slot 13 transmission/reception completed Slot 14 transmission/reception completed Slot 15 transmission/reception completed To the preceding page(Level) 27-source inputs CAN1SLIST (H'0080 140C) CAN1SLIMK (H'0080 1410) To the remaining 19-source inputs in the succeeding pages Figure 13.2.9 Block Diagram of CAN1 Transmit/Receive & Error Interrupt Requests (2/5)

13-4232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 13.2.10 Block Diagram of CAN1 Transmit/Receive & Error Interrupt Requests (3/5) F/F F/F OIM OIS F/F F/F PIM PIS F/F F/F EIM EIS b15 b14 b13 Data bus CAN bus error occurs Go to error passive state Go to bus off state To the preceding page(Level) 19-source inputs CAN1ERIST (H'0080 1414) CAN1ERIMK (H'0080 1415) To the remaining 16-source inputs in the succeeding pages

13 13.2 CAN Module Related Registers CAN MODULE 13-4332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 13.2.11 Block Diagram of CAN1 Transmit/Receive & Error Interrupt Requests (4/5) F/F F/F F/F F/F F/F F/F F/F F/F SSIMK7 SSIST7 SSIMK6 SSIST6 SSIMK5 SSIST5 SSIMK4 SSIST4 F/F F/F SSIMK3 SSIST3 F/F F/F SSIMK2 SSIST2 F/F F/F SSIMK1 SSIST1 F/F F/F SSIMK0 SSIST0 Data bus Slot 0 arbitration-lost/transmit error occurs Slot 1 arbitration-lost/transmit error occurs Slot 2 arbitration-lost/transmit error occurs Slot 3 arbitration-lost/transmit error occurs Slot 4 arbitration-lost/transmit error occurs Slot 5 arbitration-lost/transmit error occurs Slot 6 arbitration-lost/transmit error occurs Slot 7 arbitration-lost/transmit error occurs To the remaining 8-source inputs in the next page To the preceding page (Level) 16-source inputs CAN1SSIST (H'0080 1444) CAN1SSIMK (H'0080 1488)

13-4432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 13.2.12 Block Diagram of CAN1 Transmit/Receive & Error Interrupt Requests (5/5) F/F F/F F/F F/F F/F F/F F/F F/F SSIMK15 SSIST15 SSIMK14 SSIST14 SSIMK13 SSIST13 SSIMK12 SSIST12 F/F F/F SSIMK11 SSIST11 F/F F/F SSIMK10 SSIST10 F/F F/F SSIMK9 SSIST9 F/F F/F SSIMK8 SSIST8 b15 b15 b14 b14 b13 b13 b12 b12 b11 b11 b10 b10 Data bus Slot 8 arbitration-lost/transmit error occurs Slot 9 arbitration-lost/transmit error occurs Slot 10 arbitration-lost/transmit error occurs Slot 11 arbitration-lost/transmit error occurs Slot 12 arbitration-lost/transmit error occurs Slot 13 arbitration-lost/transmit error occurs Slot 14 arbitration-lost/transmit error occurs Slot 15 arbitration-lost/transmit error occurs To the preceding page(Level) 8-source inputs CAN1SSIST (H'0080 1444) CAN1SSIMK (H'0080 1488)

13 13.2 CAN Module Related Registers CAN MODULE 13-4532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.9 CAN Cause of Error Registers

CAN0 Cause of Error Register (CAN0EF) <Address: H’0080 1017> CAN1 Cause of Error Register (CAN1EF) <Address: H’0080 1417> 9 10 11 12 13 14 b15b8 BITE1BITE0 STFE FORME CRCE ACKE 00000000 RCVETRE <Upon exiting reset: H’00> b Bit Name Function R W

8 TRE 0: Error not detected R (Note 1)

Transmit error detection bit 1: Transmit error detected

9 RCVE 0: Error not detected R (Note 1)

Receive error detection bit 1: Receive error detected

10 BITE0 0: No bit error is detected R (Note 1)

"0" sending bit error detection bit 1: Bit error is detected when sending a "0"

11 BITE1 0: No bit error is detected R (Note 1)

"1" sending bit error detection bit 1: Bit error is detected when sending a "1"

12 STFE 0: Error not detected R (Note 1)

Stuff error detection bit 1: Stuff error detected

13 FORME 0: Error not detected R (Note 1)

Form error detection bit 1: Form error detected

14 CRCE 0: Error not detected R (Note 1)

CRC error detection bit 1: CRC error detected

15 ACKE 0: Error not detected R (Note 1)

ACK error detection bit 1: ACK error detected Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write. This register indicates error information when a communication error occurred. Each bit in this register is set every time a communication error is detected, and is not cleared unless a program writes a "0" to the relevant bit. (1) TRE (Transmit Error Detection) bit (Bit 8) This bit is set to "1" when a communication error is detected while operating as a transmit node. The bit is cleared by writing a "0" in software. (2) RCVE (Receive Error Detection) bit (Bit 9) This bit is set to "1" when a communication error is detected while operating as a receive node. The bit is cleared by writing a "0" in software. (3) BITE0 ("0" Sending Bit Error Detection) bit (Bit 10) This bit is set to "1" when a bit error is detected while sending a "0" from CTX. The bit is cleared by writing a "0" in software. (4) BITE1 ("1" Sending Bit Error Detection) bit (Bit 11) This bit is set to "1" when a bit error is detected while sending a "1" from CTX. The bit is cleared by writing a "0" in software.

13-4632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (5) STFE (Stuff Error Detection) bit (Bit 12) This bit is set to "1" when a stuff error was detected. The bit is cleared by writing a "0" in software. (6) FORME (Form Error Detection) bit (Bit 13) This bit is set to "1" when a form error was detected. The bit is cleared by writing a "0" in software. (7) CRCE (CRC Error Detection) bit (Bit 14) This bit is set to "1" when a CRC error was detected. The bit is cleared by writing a "0" in software. (8) ACKE (ACK Error Detection) bit (Bit 15) This bit is set to "1" when an ACK error was detected. The bit is cleared by writing a "0" in software Note: Depending on the error status, two or more bits may be set at the same time.

13 13.2 CAN Module Related Registers CAN MODULE 13-4732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CRX pin CTX pin Self-diagnostic mode Ack signal generating circuit Rx Tx M32R/ECU CAN module

13.2.10 CAN Mode Registers

CAN0 Mode Register (CAN0MOD) <Address: H’0080 1018> CAN1 Mode Register (CAN1MOD) <Address: H’0080 1418> 123456 b 7b0 CMOD 000 0 0 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 0–5 No function assigned. Fix to "0". 00 6–7 CMOD 00: Normal mode R W CAN operation mode select bit 01: Bus monitor mode 10: Self-diagnostic mode 11: Settings inhibited (1) CMOD (CAN Operation Mode Select) bits (Bit 6, Bit 7) These bits select the CAN operation mode.

Normal operation mode Normal transmit/receive operations can be performed.
Bus monitor mode Only receive operation is performed. During bus monitor mode, the CTX output is fixed high and neither ACK nor an error frame can be returned. Note: During bus monitor mode, issuing transmit requests is inhibited. The ACK bit is handled as “Don’t care” during bus monitor mode. Therefore, if all bits of data including the CRC delimiter are received normally, it is assumed that data has been received normally no matter whether the ACK bit is high.
Self-diagnostic mode CTX and CRX are connected together internally in the CAN module. When combined with loopback mode, this mode allows communication to be performed within the CAN module alone. During self- diagnostic mode, the CTX pin output is fixed high even when transmitting. Figure 13.2.13 Conceptual Diagram of Self-Diagnostic Mode

13-4832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.11 CAN DMA Transfer Request Select Registers

CAN0 DMA Transfer Request Select Register (CAN0DMARQ) <Address: H’0080 1019> CAN1 DMA Transfer Request Select Register (CAN1DMARQ) <Address: H’0080 1419> 9 10 11 12 13 14 b15b8 CDMSEL1 CDMSEL0 000 0 0 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 8–13 No function assigned. Fix to "0". 00

14 CDMSEL1 0: Slot 1 transmission failed R W

CAN DMA1 transfer request source select bit 1: Slot 14 transmission/reception completed

15 CDMSEL0 0: Slot 0 transmission failed R W

CAN DMA0 transfer request source select bit 1: Slot 15 transmission/reception completed CAN0 and 1 can generate DMA transfer requests. This register is used to select the cause or source of that request. (1) CDMSEL1 (CAN DMA1 Transfer Request Source Select) bit (Bit 14) This bit selects one of the following two as the cause or source of a transfer request to DMA7 and DMA9.

Slot 1 transmission failed If the CDMSEL1 bit is set to "0", a transfer request is generated when transmission in slot 1 has failed for reasons of arbitration-lost or transmit error.
Slot 14 transmission/reception completed If the CDMSEL1 bit is set to "1", a transfer request is generated when transmission/reception in slot 14 is completed. Notes: If slot 14 has been set for remote frame transmission, a DMA transfer request is gener- ated when remote frame transmission is completed as well as when data frame reception is completed. If slot 14 has been set for remote frame reception (automatic response), a DMA transfer request is generated when remote frame reception is completed as well as when data frame transmission is completed. (2) CDMSEL0 (CAN DMA0 Transfer Request Source Select) bit (Bit 15) This bit selects one of the following two as the cause or source of a transfer request to DMA6 and DMA8.
Slot 0 transmission failed If the CDMSEL0 bit is set to "0", a transfer request is generated when transmission in slot 0 has failed for reasons of arbitration-lost or transmit error.
Slot 15 transmission/reception completed If the CDMSEL0 bit is set to "1", a transfer request is generated when transmission/reception in slot 15 is completed. Notes: If slot 15 has been set for remote frame transmission, a DMA transfer request is gener- ated when remote frame transmission is completed as well as when data frame reception is completed. If slot 15 has been set for remote frame reception (automatic response), a DMA transfer request is generated when remote frame reception is completed as well as when data frame transmission is completed.

13 13.2 CAN Module Related Registers CAN MODULE 13-4932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.12 CAN Mask Registers

CAN0 Global Mask Register Standard ID0 (C0GMSKS0) <Address: H’0080 1028> CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0) <Address: H’0080 1030> CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0) <Address: H’0080 1038> CAN1 Global Mask Register Standard ID0 (C1GMSKS0) <Address: H’0080 1428> CAN1 Local Mask Register A Standard ID0 (C1LMSKAS0) <Address: H’0080 1430> CAN1 Local Mask Register B Standard ID0 (C1LMSKBS0) <Address: H’0080 1438> 123456 b 7b0 SID0M SID1M SID2M SID3M SID4M 000000 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00 3–7 SID0M–SID4M 0: ID not checked R W (Standard mask ID0–standard mask ID4) 1: ID checked CAN0 Global Mask Register Standard ID1 (C0GMSKS1) <Address: H’0080 1029> CAN0 Local Mask Register A Standard ID1 (C0LMSKAS1) <Address: H’0080 1031> CAN0 Local Mask Register B Standard ID1 (C0LMSKBS1) <Address: H’0080 1039> CAN1 Global Mask Register Standard ID1 (C1GMSKS1) <Address: H’0080 1429> CAN1 Local Mask Register A Standard ID1 (C1LMSKAS1) <Address: H’0080 1431> CAN1 Local Mask Register B Standard ID1 (C1LMSKBS1) <Address: H’0080 1439> 9 10 11 12 13 14 b15b8 SID6MSID5M SID7M SID8M SID9M SID10M 0000000 0 <Upon exiting reset: H’00> b Bit Name Function R W 8–9 No function assigned. Fix to "0". 00 10–15 SID5M–SID10M 0: ID not checked R W (Standard mask ID5–standard mask ID10) 1: ID checked Three mask registers are used in acceptance filtering: global mask register, local mask register A and local mask register B. The global mask register is used for message slots 0-13, while local mask registers A and B are used for message slots 14 and 15, respectively. If any bit in this register is set to "0", the corresponding ID bit is masked (assumed to have matched) during acceptance filtering. If any bit in this register is set to "1", the corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set in the message slot, the received data is stored in it. Notes: SID0M corresponds to the MSB of the standard ID. The global mask register can only be modified when none of slots 0-13 have receive requests set. The local mask register A can only be modified when slot 14 does not have a receive request set. The local mask register B can only be modified when slot 15 does not have a receive request set.

13-5032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Global Mask Register Extended ID0 (C0GMSKE0) <Address: H’0080 102A> CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0) <Address: H’0080 1032> CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) <Address: H’0080 103A> CAN1 Global Mask Register Extended ID0 (C1GMSKE0) <Address: H’0080 142A> CAN1 Local Mask Register A Extended ID0 (C1LMSKAE0) <Address: H’0080 1432> CAN1 Local Mask Register B Extended ID0 (C1LMSKBE0) <Address: H’0080 143A> 123456 b 7b0 EID1MEID0M EID2M EID3M 00000 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00 4–7 EID0M–EID3M 0: ID not checked R W (Extended mask ID0–extended mask ID3) 1: ID checked CAN0 Global Mask Register Extended ID1 (C0GMSKE1) <Address: H’0080 102B> CAN0 Local Mask Register A Extended ID1 (C0LMSKAE1) <Address: H’0080 1033> CAN0 Local Mask Register B Extended ID1 (C0LMSKBE1) <Address: H’0080 103B> CAN1 Global Mask Register Extended ID1 (C1GMSKE1) <Address: H’0080 142B> CAN1 Local Mask Register A Extended ID1 (C1LMSKAE1) <Address: H’0080 1433> CAN1 Local Mask Register B Extended ID1 (C1LMSKBE1) <Address: H’0080 143B> 9 1 01 11 21 31 4 b 1 5b8 EID6MEID5MEID4M EID7M EID8M EID9M EID10M EID11M 00000000 <Upon exiting reset: H’00> b Bit Name Function R W 8–15 EID4M–EID11M 0: ID not checked R W (Extended mask ID4–extended mask ID11) 1: ID checked

13 13.2 CAN Module Related Registers CAN MODULE 13-5132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Global Mask Register Extended ID2 (C0GMSKE2) <Address: H’0080 102C> CAN0 Local Mask Register A Extended ID2 (C0LMSKAE2) <Address: H’0080 1034> CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2) <Address: H’0080 103C> CAN1 Global Mask Register Extended ID2 (C1GMSKE2) <Address: H’0080 142C> CAN1 Local Mask Register A Extended ID2 (C1LMSKAE2) <Address: H’0080 1434> CAN1 Local Mask Register B Extended ID2 (C1LMSKBE2) <Address: H’0080 143C>

123456 B 7b0

EID12M EID13M EID14M EID15M EID16M EID17M 0000000 0 <Upon exiting reset: H’00> b Bit Name Function R W 0,1 No function assigned. Fix to "0". 00 2–7 EID12M–EID17M 0: ID not checked R W (Extended mask ID12–extended mask ID17) 1: ID checked Three mask registers are used in acceptance filtering: global mask register, local mask register A and local mask register B. The global mask register is used for message slots 0-13, while local mask registers A and B are used for message slots 14 and 15, respectively. If any bit in this register is set to "0", the corresponding ID bit is masked (assumed to have matched) during acceptance filtering. If any bit in this register is set to "1", the corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set in the message slot, the received data is stored in it. Notes: EID0M corresponds to the MSB of the extended ID. The global mask register can only be modified when none of slots 0-13 have receive requests set. The local mask register A can only be modified when slot 14 does not have a receive request set. The local mask register B can only be modified when slot 15 does not have a receive request set.

13-5232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Slot 0 Slot 1 Slot 2 Slot 13 Slot 14 Slot 15 Slots controlled by the global mask register Slot controlled by local mask register A Slot controlled by local mask register B ID of received frame ID set in slot Mask register set value 0: The received message and slot IDs are not checked for matching and handled as "Don't care" (masked) 1: The received message and slot IDs are checked for matching Mask bit value Acceptance judgment signal Acceptance judgment signal 0: The received message is ignored (not stored in any slot) 1: The received message is stored in the slot that has the matching ID Figure 13.2.14 Relationship between the Mask Registers and the Controlled Slots Figure 13.2.15 Concept of Acceptance Filtering

13 13.2 CAN Module Related Registers CAN MODULE 13-5332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.13 CAN Single-Shot Mode Control Registers

CAN0 Single-Shot Mode Control Register (CAN0SSMODE) <Address: H’0080 1040> CAN1 Single-Shot Mode Control Register (CAN1SSMODE) <Address: H’0080 1440> b 0123456789 1 0 1 1 1 2 1 3 1 4 b 1 5 SSCNT0 SSCNT1 SSCNT2 SSCNT3 SSCNT4 SSCNT5 SSCNT6 SSCNT7 SSCNT8 SSCNT9 SSCNT10 SSCNT11 SSCNT12 SSCNT13 SSCNT14 SSCNT15 0000000000000000 <Upon exiting reset: H’0000> b Bit Name Function R W

0 SSCNT0 (Slot 0 single-shot mode bit) 0: Normal mode R W

1 SSCNT1 (Slot 1 single-shot mode bit) 1: Single-shot mode

2 SSCNT2 (Slot 2 single-shot mode bit)

3 SSCNT3 (Slot 3 single-shot mode bit)

4 SSCNT4 (Slot 4 single-shot mode bit)

5 SSCNT5 (Slot 5 single-shot mode bit)

6 SSCNT6 (Slot 6 single-shot mode bit)

7 SSCNT7 (Slot 7 single-shot mode bit)

8 SSCNT8 (Slot 8 single-shot mode bit)

9 SSCNT9 (Slot 9 single-shot mode bit)

10 SSCNT10 (Slot 10 single-shot mode bit)

11 SSCNT11 (Slot 11 single-shot mode bit)

12 SSCNT12 (Slot 12 single-shot mode bit)

13 SSCNT13 (Slot 13 single-shot mode bit)

14 SSCNT14 (Slot 14 single-shot mode bit)

15 SSCNT15 (Slot 15 single-shot mode bit)

Normally in CAN, if transmission has failed for reasons of arbitration-lost or transmit error, the transmit opera- tion is continued until successfully transmitted. This register is used to specify for each slot whether or not to retry a transmit operation in such a case. In single-shot mode, if transmission fails for reasons of arbitration-lost or transmit error, the transmit operation is not retried. If any bit in this register is set to "1", the corresponding slot operates in single-shot mode. Note: Settings of this register can only be changed when the message slot control register for the slot whose corresponding bit is to be modified is in the H’00 state.

13-5432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.14 CAN Message Slot Control Registers

CAN0 Message Slot 0 Control Register (C0MSL0CNT) <Address: H’0080 1050> CAN0 Message Slot 1 Control Register (C0MSL1CNT) <Address: H’0080 1051> CAN0 Message Slot 2 Control Register (C0MSL2CNT) <Address: H’0080 1052> CAN0 Message Slot 3 Control Register (C0MSL3CNT) <Address: H’0080 1053> CAN0 Message Slot 4 Control Register (C0MSL4CNT) <Address: H’0080 1054> CAN0 Message Slot 5 Control Register (C0MSL5CNT) <Address: H’0080 1055> CAN0 Message Slot 6 Control Register (C0MSL6CNT) <Address: H’0080 1056> CAN0 Message Slot 7 Control Register (C0MSL7CNT) <Address: H’0080 1057> CAN0 Message Slot 8 Control Register (C0MSL8CNT) <Address: H’0080 1058> CAN0 Message Slot 9 Control Register (C0MSL9CNT) <Address: H’0080 1059> CAN0 Message Slot 10 Control Register (C0MSL10CNT) <Address: H’0080 105A> CAN0 Message Slot 11 Control Register (C0MSL11CNT) <Address: H’0080 105B> CAN0 Message Slot12 Control Register (C0MSL12CNT) <Address: H’0080 105C> CAN0 Message Slot 13 Control Register (C0MSL13CNT) <Address: H’0080 105D> CAN0 Message Slot 14 Control Register (C0MSL14CNT) <Address: H’0080 105E> CAN0 Message Slot 15 Control Register (C0MSL15CNT) <Address: H’0080 105F> CAN1 Message Slot 0 Control Register (C1MSL0CNT) <Address: H’0080 1450> CAN1 Message Slot 1 Control Register (C1MSL1CNT) <Address: H’0080 1451> CAN1 Message Slot 2 Control Register (C1MSL2CNT) <Address: H’0080 1452> CAN1 Message Slot 3 Control Register (C1MSL3CNT) <Address: H’0080 1453> CAN1 Message Slot 4 Control Register (C1MSL4CNT) <Address: H’0080 1454> CAN1 Message Slot 5 Control Register (C1MSL5CNT) <Address: H’0080 1455> CAN1 Message Slot 6 Control Register (C1MSL6CNT) <Address: H’0080 1456> CAN1 Message Slot 7 Control Register (C1MSL7CNT) <Address: H’0080 1457> CAN1 Message Slot 8 Control Register (C1MSL8CNT) <Address: H’0080 1458> CAN1 Message Slot 9 Control Register (C1MSL9CNT) <Address: H’0080 1459> CAN1 Message Slot 10 Control Register (C1MSL10CNT) <Address: H’0080 145A> CAN1 Message Slot 11 Control Register (C1MSL11CNT) <Address: H’0080 145B> CAN1 Message Slot 12 Control Register (C1MSL12CNT) <Address: H’0080 145C> CAN1 Message Slot 13 Control Register (C1MSL13CNT) <Address: H’0080 145D> CAN1 Message Slot 14 Control Register (C1MSL14CNT) <Address: H’0080 145E> CAN1 Message Slot 15 Control Register (C1MSL15CNT) <Address: H’0080 145F>

13 13.2 CAN Module Related Registers CAN MODULE 13-5532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 123456 b 7 (b15)(b8)b0 RMRRTR RL RA ML TRSTAT TRFIN 00000000 <Upon exiting reset: H’00> b Bit Name Function R W 0 (8) TR 0: Do not use the message slot as transmit slot R W Transmit request bit 1: Use the message slot as transmit slot 1 (9) RR 0: Do not use the message slot as receive slot R W Receive request bit 1: Use the message slot as receive slot 2 (10) RM 0: Transmit/receive data frame R W Remote bit 1: Transmit/receive remote frame 3 (11) RL 0: Enable automatic response for remote frame R W Automatic response inhibit bit 1: Disable automatic response for remote frame 4 (12) RA During BasicCAN mode R – Remote active bit 0: Receive data frame (status) 1: Receive remote frame (status) During normal mode 0: Data frame 1: Remote frame 5 (13) ML 0: No message was lost R(Note 1) Message lost bit 1: Message was lost 6 (14) TRSTAT During a transmit slot R – Transmit/receive status bit 0: Transmission idle 1: Transmit request accepted During a receive slot 0: Reception idle 1: Storing received data 7 (15) TRFIN During a transmit slot R(Note 1) Transmission/reception finished bit 0: Not transmitted yet 1: Finished transmitting During a receive slot 0: Not received yet 1: Finished receiving Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the status it had before the write. Notes: If a transmit request is written to this register while the CAN module is reset (CANnCNT FRST or RST bit = "1"), it starts sending upon detecting 11 consecutive recessive bits on the CAN bus after exiting the reset state. If data/remote frame transmit requests are issued for two or more slots, the slot with the small- est slot number sends a frame. If data/remote frame receive requests are issued for two or more slots, the slot with the smallest slot number among the slots satisfying the receive condi- tion receives a frame. If transmission failed when single-shot mode is selected, this register is cleared to H’00. (1) TR (Transmit Request) bit (Bit 0, 8) To use the message slot as a transmit slot, set this bit to "1". To use the message slot as a data frame or remote frame receive slot, set this bit to "0".

13-5632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) RR (Receive Request) bit (Bit 1, 9) To use the message slot as a receive slot, set this bit to "1". To use the message slot as a data frame or remote frame transmit slot, set this bit to "0". If TR (Transmit Request) bit and RR (Receive Request) bit both are set to "1", device operation is unde- fined. (3) RM (Remote) bit (Bit 2, 10) To handle remote frames in the message slot, set this bit to "1". There are following two methods of settings to handle remote frames:

Set for remote frame transmission The data set in the message slot is transmitted as a remote frame. When the CAN module finished sending, the slot automatically changes to a data frame receive slot. However, if a data frame is received before the CAN module finished sending a remote frame, the received data is stored in the message slot and the remote frame is not transmitted.
Set for remote frame reception Remote frames are received. The processing to be performed after receiving a remote frame is selected by RL (automatic response inhibit) bit. (4) RL (Automatic Response Inhibit) bit (Bit 3, 11) This bit is effective when the message slot has been set as a remote frame receive slot. It selects the processing to be performed after receiving a remote frame. If this bit is set to "0", the message slot automati- cally changes to a transmit slot after receiving a remote frame and transmits the data set in it as a data frame. If this bit is set to "1", the message slot stops operating after receiving a remote frame. Note: Always set this bit to "0" unless the message slot is set for remote frame reception. (5) RA (Remote Active) bit (Bit 4, 12) This bit functions differently for slots 0-13 and slots 14 and 15.
Slots 0–13 This bit is set to "1" when the message slot is set for remote frame transmission (reception). Then, when remote frame transmission (reception) is completed, the bit is cleared to "0".
Slots 14 and 15 The function of this bit differs depending on how the CAN Control Register BCM (BasicCAN Mode) bit is set. If BCM = "0" (normal operation), this bit is set to "1" when the message slot is set for remote frame transmission (reception). If BCM = "1" (BasicCAN), this bit indicates which type of frame is received. During BasicCAN mode, the received data is stored in slots 14 and 15 for both data and remote frames. If RA = "0", it means that the frame stored in the slot is a data frame. If RA = "1", it means that the frame stored in the slot is a remote frame. (6) ML (Message Lost) bit (Bit 5, 13) This bit is effective for receive slots. It is set to "1" when unread received data contained in the message slot is overwritten by reception. This bit is cleared by writing "0" in software.

13 13.2 CAN Module Related Registers CAN MODULE 13-5732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (7) TRSTAT (Transmit/Receive Status) bit (Bit 6, 14) This bit indicates that the CAN module is sending or receiving and is accessing the message slot. This bit is set to "1" when the CAN module is accessing, and set to "0" when not accessing.

During a transmit slot This bit is set to "1" when a transmit request for the message slot is accepted. It is cleared to "0" when the CAN module lost in bus arbitration, when a CAN bus error occurs, or when transmission is completed.
During a receive slot This bit is set to "1" while the CAN module is receiving data, with the received data being stored in the message slot. Note that the value read from the message slot while the TRSTAT bit remains set is undefined. (8) TRFIN (Transmit/Receive Finished) bit (Bit 7, 15) This bit indicates that the CAN module finished sending or receiving.
When set for a transmit slot This bit is set to "1" when the CAN module finished sending the data stored in the message slot. This bit is cleared by writing "0" in software. However, it cannot be cleared when the TRSTAT (Transmit/Receive Status) bit = "1".
When set for a receive slot This bit is set to "1" when the CAN module finished receiving normally the data to be stored in the message slot. This bit is cleared by writing "0" in software. However, it cannot be cleared when the TRSTAT (Transmit/Receive Status) bit = "1". Notes: Before reading the received data out of the message slot, be sure to clear the TRFIN (Transmit/Receive Finished) bit to "0". If the TRFIN (Transmit/Receive Finished) bit hap- pens to be set to "1" after a read, it means that new received data was stored while reading and the read data contains an undefined value. In that case, discard the read data, clear the TRFIN bit to "0" and read out data again. When sending/receiving remote frames, the TRFIN bit is automatically cleared to "0" by hardware. Therefore, the TRFIN bit cannot be used as a transmission/reception-finished flag.

13-5832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.2.15 CAN Message Slots

CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) <Address: H’0080 1100> CAN0 Message Slot 1 Standard ID0 (C0MSL1SID0) <Address: H’0080 1110> CAN0 Message Slot 2 Standard ID0 (C0MSL2SID0) <Address: H’0080 1120> CAN0 Message Slot 3 Standard ID0 (C0MSL3SID0) <Address: H’0080 1130> CAN0 Message Slot 4 Standard ID0 (C0MSL4SID0) <Address: H’0080 1140> CAN0 Message Slot 5 Standard ID0 (C0MSL5SID0) <Address: H’0080 1150> CAN0 Message Slot 6 Standard ID0 (C0MSL6SID0) <Address: H’0080 1160> CAN0 Message Slot 7 Standard ID0 (C0MSL7SID0) <Address: H’0080 1170> CAN0 Message Slot 8 Standard ID0 (C0MSL8SID0) <Address: H’0080 1180> CAN0 Message Slot 9 Standard ID0 (C0MSL9SID0) <Address: H’0080 1190> CAN0 Message Slot 10 Standard ID0 (C0MSL10SID0) <Address: H’0080 11A0> CAN0 Message Slot 11 Standard ID0 (C0MSL11SID0) <Address: H’0080 11B0> CAN0 Message Slot 12 Standard ID0 (C0MSL12SID0) <Address: H’0080 11C0> CAN0 Message Slot 13 Standard ID0 (C0MSL13SID0) <Address: H’0080 11D0> CAN0 Message Slot 14 Standard ID0 (C0MSL14SID0) <Address: H’0080 11E0> CAN0 Message Slot 15 Standard ID0 (C0MSL15SID0) <Address: H’0080 11F0> CAN1 Message Slot 0 Standard ID0 (C1MSL0SID0) <Address: H’0080 1500> CAN1 Message Slot 1 Standard ID0 (C1MSL1SID0) <Address: H’0080 1510> CAN1 Message Slot 2 Standard ID0 (C1MSL2SID0) <Address: H’0080 1520> CAN1 Message Slot 3 Standard ID0 (C1MSL3SID0) <Address: H’0080 1530> CAN1 Message Slot 4 Standard ID0 (C1MSL4SID0) <Address: H’0080 1540> CAN1 Message Slot 5 Standard ID0 (C1MSL5SID0) <Address: H’0080 1550> CAN1 Message Slot 6 Standard ID0 (C1MSL6SID0) <Address: H’0080 1560> CAN1 Message Slot 7 Standard ID0 (C1MSL7SID0) <Address: H’0080 1570> CAN1 Message Slot 8 Standard ID0 (C1MSL8SID0) <Address: H’0080 1580> CAN1 Message Slot 9 Standard ID0 (C1MSL9SID0) <Address: H’0080 1590> CAN1 Message Slot 10 Standard ID0 (C1MSL10SID0) <Address: H’0080 15A0> CAN1 Message Slot 11 Standard ID0 (C1MSL11SID0) <Address: H’0080 15B0> CAN1 Message Slot 12 Standard ID0 (C1MSL12SID0) <Address: H’0080 15C0> CAN1 Message Slot 13 Standard ID0 (C1MSL13SID0) <Address: H’0080 15D0> CAN1 Message Slot 14 Standard ID0 (C1MSL14SID0) <Address: H’0080 15E0> CAN1 Message Slot 15 Standard ID0 (C1MSL15SID0) <Address: H’0080 15F0> 123456 b 7b0 SID1SID0 SID2 SID3 SID4 <Upon exiting reset: Undefined> b Bit Name Function R W 0–2 No function assigned. Fix to "0". 00 3–7 SID0–SID4 Standard ID0–standard ID4 R W (Standard ID0–standard ID4) These registers are the memory space for transmit and receive frames.

13 13.2 CAN Module Related Registers CAN MODULE 13-5932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) <Address: H’0080 1101> CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1) <Address: H’0080 1111> CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1) <Address: H’0080 1121> CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1) <Address: H’0080 1131> CAN0 Message Slot 4 Standard ID1 (C0MSL4SID1) <Address: H’0080 1141> CAN0 Message Slot 5 Standard ID1 (C0MSL5SID1) <Address: H’0080 1151> CAN0 Message Slot 6 Standard ID1 (C0MSL6SID1) <Address: H’0080 1161> CAN0 Message Slot 7 Standard ID1 (C0MSL7SID1) <Address: H’0080 1171> CAN0 Message Slot 8 Standard ID1 (C0MSL8SID1) <Address: H’0080 1181> CAN0 Message Slot 9 Standard ID1 (C0MSL9SID1) <Address: H’0080 1191> CAN0 Message Slot 10 Standard ID1 (C0MSL10SID1) <Address: H’0080 11A1> CAN0 Message Slot 11 Standard ID1 (C0MSL11SID1) <Address: H’0080 11B1> CAN0 Message Slot 12 Standard ID1 (C0MSL12SID1) <Address: H’0080 11C1> CAN0 Message Slot 13 Standard ID1 (C0MSL13SID1) <Address: H’0080 11D1> CAN0 Message Slot 14 Standard ID1 (C0MSL14SID1) <Address: H’0080 11E1> CAN0 Message Slot 15 Standard ID1 (C0MSL15SID1) <Address: H’0080 11F1> CAN1 Message Slot 0 Standard ID1 (C1MSL0SID1) <Address: H’0080 1501> CAN1 Message Slot 1 Standard ID1 (C1MSL1SID1) <Address: H’0080 1511> CAN1 Message Slot 2 Standard ID1 (C1MSL2SID1) <Address: H’0080 1521> CAN1 Message Slot 3 Standard ID1 (C1MSL3SID1) <Address: H’0080 1531> CAN1 Message Slot 4 Standard ID1 (C1MSL4SID1) <Address: H’0080 1541> CAN1 Message Slot 5 Standard ID1 (C1MSL5SID1) <Address: H’0080 1551> CAN1 Message Slot 6 Standard ID1 (C1MSL6SID1) <Address: H’0080 1561> CAN1 Message Slot 7 Standard ID1 (C1MSL7SID1) <Address: H’0080 1571> CAN1 Message Slot 8 Standard ID1 (C1MSL8SID1) <Address: H’0080 1581> CAN1 Message Slot 9 Standard ID1 (C1MSL9SID1) <Address: H’0080 1591> CAN1 Message Slot 10 Standard ID1 (C1MSL10SID1) <Address: H’0080 15A1> CAN1 Message Slot 11 Standard ID1 (C1MSL11SID1) <Address: H’0080 15B1> CAN1 Message Slot 12 Standard ID1 (C1MSL12SID1) <Address: H’0080 15C1> CAN1 Message Slot 13 Standard ID1 (C1MSL13SID1) <Address: H’0080 15D1> CAN1 Message Slot 14 Standard ID1 (C1MSL14SID1) <Address: H’0080 15E1> CAN1 Message Slot 15 Standard ID1 (C1MSL15SID1) <Address: H’0080 15F1> 9 10 11 12 13 14 b15b8 SID7SID6SID5 SID8 SID9 SID10 <Upon exiting reset: Undefined> b Bit Name Function R W 8, 9 No function assigned. Fix to "0". 00 10–15 SID5–SID10 Standard ID5–standard ID10 R W (Standard ID5–standard ID10) These registers are the memory space for transmit and receive frames.

13-6032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) <Address: H’0080 1102> CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0) <Address: H’0080 1112> CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0) <Address: H’0080 1122> CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0) <Address: H’0080 1132> CAN0 Message Slot 4 Extended ID0 (C0MSL4EID0) <Address: H’0080 1142> CAN0 Message Slot 5 Extended ID0 (C0MSL5EID0) <Address: H’0080 1152> CAN0 Message Slot 6 Extended ID0 (C0MSL6EID0) <Address: H’0080 1162> CAN0 Message Slot 7 Extended ID0 (C0MSL7EID0) <Address: H’0080 1172> CAN0 Message Slot 8 Extended ID0 (C0MSL8EID0) <Address: H’0080 1182> CAN0 Message Slot 9 Extended ID0 (C0MSL9EID0) <Address: H’0080 1192> CAN0 Message Slot 10 Extended ID0 (C0MSL10EID0) <Address: H’0080 11A2> CAN0 Message Slot 11 Extended ID0 (C0MSL11EID0) <Address: H’0080 11B2> CAN0 Message Slot 12 Extended ID0 (C0MSL12EID0) <Address: H’0080 11C2> CAN0 Message Slot 13 Extended ID0 (C0MSL13EID0) <Address: H’0080 11D2> CAN0 Message Slot 14 Extended ID0 (C0MSL14EID0) <Address: H’0080 11E2> CAN0 Message Slot 15 Extended ID0 (C0MSL15EID0) <Address: H’0080 11F2> CAN1 Message Slot 0 Extended ID0 (C1MSL0EID0) <Address: H’0080 1502> CAN1 Message Slot 1 Extended ID0 (C1MSL1EID0) <Address: H’0080 1512> CAN1 Message Slot 2 Extended ID0 (C1MSL2EID0) <Address: H’0080 1522> CAN1 Message Slot 3 Extended ID0 (C1MSL3EID0) <Address: H’0080 1532> CAN1 Message Slot 4 Extended ID0 (C1MSL4EID0) <Address: H’0080 1542> CAN1 Message Slot 5 Extended ID0 (C1MSL5EID0) <Address: H’0080 1552> CAN1 Message Slot 6 Extended ID0 (C1MSL6EID0) <Address: H’0080 1562> CAN1 Message Slot 7 Extended ID0 (C1MSL7EID0) <Address: H’0080 1572> CAN1 Message Slot 8 Extended ID0 (C1MSL8EID0) <Address: H’0080 1582> CAN1 Message Slot 9 Extended ID0 (C1MSL9EID0) <Address: H’0080 1592> CAN1 Message Slot 10 Extended ID0 (C1MSL10EID0) <Address: H’0080 15A2> CAN1 Message Slot 11 Extended ID0 (C1MSL11EID0) <Address: H’0080 15B2> CAN1 Message Slot 12 Extended ID0 (C1MSL12EID0) <Address: H’0080 15C2> CAN1 Message Slot 13 Extended ID0 (C1MSL13EID0) <Address: H’0080 15D2> CAN1 Message Slot 14 Extended ID0 (C1MSL14EID0) <Address: H’0080 15E2> CAN1 Message Slot 15 Extended ID0 (C1MSL15EID0) <Address: H’0080 15F2> 123456 b 7b0 EID1EID0 EID2 EID3 <Upon exiting reset: Undefined> b Bit Name Function R W 0–3 No function assigned. Fix to "0". 00 4–7 EID0–EID3 Extended ID0–extended ID3 R W (Extended ID0–extended ID3) These registers are the memory space for transmit and receive frames. Note: If the message slot is set for the receive slot standard ID format, an undefined value is written to the EID bits when storing received data.

13 13.2 CAN Module Related Registers CAN MODULE 13-6132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) <Address: H’0080 1103> CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1) <Address: H’0080 1113> CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1) <Address: H’0080 1123> CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1) <Address: H’0080 1133> CAN0 Message Slot 4 Extended ID1 (C0MSL4EID1) <Address: H’0080 1143> CAN0 Message Slot 5 Extended ID1 (C0MSL5EID1) <Address: H’0080 1153> CAN0 Message Slot 6 Extended ID1 (C0MSL6EID1) <Address: H’0080 1163> CAN0 Message Slot 7 Extended ID1 (C0MSL7EID1) <Address: H’0080 1173> CAN0 Message Slot 8 Extended ID1 (C0MSL8EID1) <Address: H’0080 1183> CAN0 Message Slot 9 Extended ID1 (C0MSL9EID1) <Address: H’0080 1193> CAN0 Message Slot 10 Extended ID1 (C0MSL10EID1) <Address: H’0080 11A3> CAN0 Message Slot 11 Extended ID1 (C0MSL11EID1) <Address: H’0080 11B3> CAN0 Message Slot 12 Extended ID1 (C0MSL12EID1) <Address: H’0080 11C3> CAN0 Message Slot 13 Extended ID1 (C0MSL13EID1) <Address: H’0080 11D3> CAN0 Message Slot 14 Extended ID1 (C0MSL14EID1) <Address: H’0080 11E3> CAN0 Message Slot 15 Extended ID1 (C0MSL15EID1) <Address: H’0080 11F3> CAN1 Message Slot 0 Extended ID1 (C1MSL0EID1) <Address: H’0080 1503> CAN1 Message Slot 1 Extended ID1 (C1MSL1EID1) <Address: H’0080 1513> CAN1 Message Slot 2 Extended ID1 (C1MSL2EID1) <Address: H’0080 1523> CAN1 Message Slot 3 Extended ID1 (C1MSL3EID1) <Address: H’0080 1533> CAN1 Message Slot 4 Extended ID1 (C1MSL4EID1) <Address: H’0080 1543> CAN1 Message Slot 5 Extended ID1 (C1MSL5EID1) <Address: H’0080 1553> CAN1 Message Slot 6 Extended ID1 (C1MSL6EID1) <Address: H’0080 1563> CAN1 Message Slot 7 Extended ID1 (C1MSL7EID1) <Address: H’0080 1573> CAN1 Message Slot 8 Extended ID1 (C1MSL8EID1) <Address: H’0080 1583> CAN1 Message Slot 9 Extended ID1 (C1MSL9EID1) <Address: H’0080 1593> CAN1 Message Slot 10 Extended ID1 (C1MSL10EID1) <Address: H’0080 15A3> CAN1 Message Slot 11 Extended ID1 (C1MSL11EID1) <Address: H’0080 15B3> CAN1 Message Slot 12 Extended ID1 (C1MSL12EID1) <Address: H’0080 15C3> CAN1 Message Slot 13 Extended ID1 (C1MSL13EID1) <Address: H’0080 15D3> CAN1 Message Slot 14 Extended ID1 (C1MSL14EID1) <Address: H’0080 15E3> CAN1 Message Slot 15 Extended ID1 (C1MSL15EID1) <Address: H’0080 15F3> 9 1 01 11 21 31 4 b 1 5b8 EID6EID5EID4 EID7 EID8 EID9 EID10 EID11 <Upon exiting reset: Undefined> b Bit Name Function R W 8–15 EID4–EID11 Extended ID4–extended ID11 R W (Extended ID4–extended ID11) These registers are the memory space for transmit and receive frames. Note: If the message slot is set for the receive slot standard ID format, an undefined value is written to the EID bits when storing received data.

13-6232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) <Address: H’0080 1104> CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2) <Address: H’0080 1114> CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2) <Address: H’0080 1124> CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2) <Address: H’0080 1134> CAN0 Message Slot 4 Extended ID2 (C0MSL4EID2) <Address: H’0080 1144> CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) <Address: H’0080 1154> CAN0 Message Slot 6 Extended ID2 (C0MSL6EID2) <Address: H’0080 1164> CAN0 Message Slot 7 Extended ID2 (C0MSL7EID2) <Address: H’0080 1174> CAN0 Message Slot 8 Extended ID2 (C0MSL8EID2) <Address: H’0080 1184> CAN0 Message Slot 9 Extended ID2 (C0MSL9EID2) <Address: H’0080 1194> CAN0 Message Slot 10 Extended ID2 (C0MSL10EID2) <Address: H’0080 11A4> CAN0 Message Slot 11 Extended ID2 (C0MSL11EID2) <Address: H’0080 11B4> CAN0 Message Slot 12 Extended ID2 (C0MSL12EID2) <Address: H’0080 11C4> CAN0 Message Slot 13 Extended ID2 (C0MSL13EID2) <Address: H’0080 11D4> CAN0 Message Slot 14 Extended ID2 (C0MSL14EID2) <Address: H’0080 11E4> CAN0 Message Slot 15 Extended ID2 (C0MSL15EID2) <Address: H’0080 11F4> CAN1 Message Slot 0 Extended ID2 (C1MSL0EID2) <Address: H’0080 1504> CAN1 Message Slot 1 Extended ID2 (C1MSL1EID2) <Address: H’0080 1514> CAN1 Message Slot 2 Extended ID2 (C1MSL2EID2) <Address: H’0080 1524> CAN1 Message Slot 3 Extended ID2 (C1MSL3EID2) <Address: H’0080 1534> CAN1 Message Slot 4 Extended ID2 (C1MSL4EID2) <Address: H’0080 1544> CAN1 Message Slot 5 Extended ID2 (C1MSL5EID2) <Address: H’0080 1554> CAN1 Message Slot 6 Extended ID2 (C1MSL6EID2) <Address: H’0080 1564> CAN1 Message Slot 7 Extended ID2 (C1MSL7EID2) <Address: H’0080 1574> CAN1 Message Slot 8 Extended ID2 (C1MSL8EID2) <Address: H’0080 1584> CAN1 Message Slot 9 Extended ID2 (C1MSL9EID2) <Address: H’0080 1594> CAN1 Message Slot 10 Extended ID2 (C1MSL10EID2) <Address: H’0080 15A4> CAN1 Message Slot 11 Extended ID2 (C1MSL11EID2) <Address: H’0080 15B4> CAN1 Message Slot 12 Extended ID2 (C1MSL12EID2) <Address: H’0080 15C4> CAN1 Message Slot 13 Extended ID2 (C1MSL13EID2) <Address: H’0080 15D4> CAN1 Message Slot 14 Extended ID2 (C1MSL14EID2) <Address: H’0080 15E4> CAN1 Message Slot 15 Extended ID2 (C1MSL15EID2) <Address: H’0080 15F4> 123456 b 7b0 EID15EID14EID13EID12 EID16 EID17 <Upon exiting reset: Undefined> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00 2–7 EID12–EID17 Extended ID12–extended ID17 R W (Extended ID12–extended ID17) These registers are the memory space for transmit and receive frames. Note: If the message slot is set for the receive slot standard ID format, an undefined value is written to the EID bits when storing received data.

13 13.2 CAN Module Related Registers CAN MODULE 13-6332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) <Address: H’0080 1105> CAN0 Message Slot 1 Data Length Register (C0MSL1DLC) <Address: H’0080 1115> CAN0 Message Slot 2 Data Length Register (C0MSL2DLC) <Address: H’0080 1125> CAN0 Message Slot 3 Data Length Register (C0MSL3DLC) <Address: H’0080 1135> CAN0 Message Slot 4 Data Length Register (C0MSL4DLC) <Address: H’0080 1145> CAN0 Message Slot 5 Data Length Register (C0MSL5DLC) <Address: H’0080 1155> CAN0 Message Slot 6 Data Length Register (C0MSL6DLC) <Address: H’0080 1165> CAN0 Message Slot 7 Data Length Register (C0MSL7DLC) <Address: H’0080 1175> CAN0 Message Slot 8 Data Length Register (C0MSL8DLC) <Address: H’0080 1185> CAN0 Message Slot 9 Data Length Register (C0MSL9DLC) <Address: H’0080 1195> CAN0 Message Slot 10 Data Length Register (C0MSL10DLC) <Address: H’0080 11A5> CAN0 Message Slot 11 Data Length Register (C0MSL11DLC) <Address: H’0080 11B5> CAN0 Message Slot 12 Data Length Register (C0MSL12DLC) <Address: H’0080 11C5> CAN0 Message Slot 13 Data Length Register (C0MSL13DLC) <Address: H’0080 11D5> CAN0 Message Slot 14 Data Length Register (C0MSL14DLC) <Address: H’0080 11E5> CAN0 Message Slot 15 Data Length Register (C0MSL15DLC) <Address: H’0080 11F5> CAN1 Message Slot 0 Data Length Register (C1MSL0DLC) <Address: H’0080 1505> CAN1 Message Slot 1 Data Length Register (C1MSL1DLC) <Address: H’0080 1515> CAN1 Message Slot 2 Data Length Register (C1MSL2DLC) <Address: H’0080 1525> CAN1 Message Slot 3 Data Length Register (C1MSL3DLC) <Address: H’0080 1535> CAN1 Message Slot 4 Data Length Register (C1MSL4DLC) <Address: H’0080 1545> CAN1 Message Slot 5 Data Length Register (C1MSL5DLC) <Address: H’0080 1555> CAN1 Message Slot 6 Data Length Register (C1MSL6DLC) <Address: H’0080 1565> CAN1 Message Slot 7 Data Length Register (C1MSL7DLC) <Address: H’0080 1575> CAN1 Message Slot 8 Data Length Register (C1MSL8DLC) <Address: H’0080 1585> CAN1 Message Slot 9 Data Length Register (C1MSL9DLC) <Address: H’0080 1595> CAN1 Message Slot 10 Data Length Register (C1MSL10DLC) <Address: H’0080 15A5> CAN1 Message Slot 11 Data Length Register (C1MSL11DLC) <Address: H’0080 15B5> CAN1 Message Slot 12 Data Length Register (C1MSL12DLC) <Address: H’0080 15C5> CAN1 Message Slot 13 Data Length Register (C1MSL13DLC) <Address: H’0080 15D5> CAN1 Message Slot 14 Data Length Register (C1MSL14DLC) <Address: H’0080 15E5> CAN1 Message Slot 15 Data Length Register (C1MSL15DLC) <Address: H’0080 15F5> 9 1 01 11 21 31 4 b 1 5b8 DLC0 DLC1 DLC2 DLC3 <Upon exiting reset: Undefined> b Bit Name Function R W 8–11 No function assigned. Fix to "0". 00 12–15 DLC0–DLC3 0000: 0 bytes R W Data length setting bit 0001: 1 bytes 0010: 2 bytes 0011: 3 bytes 0100: 4 bytes 0101: 5 bytes 0110: 6 bytes 0111: 7 bytes 1000: 8 bytes | | 1111: 8 bytes These registers are the memory space for transmit and receive frames. When sending, the register is used to set the transmit data length. When receiving, the register is used to store the receive frame DLC.

13-6432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Data 0 (C0MSL0DT0) <Address: H’0080 1106> CAN0 Message Slot 1 Data 0 (C0MSL1DT0) <Address: H’0080 1116> CAN0 Message Slot 2 Data 0 (C0MSL2DT0) <Address: H’0080 1126> CAN0 Message Slot 3 Data 0 (C0MSL3DT0) <Address: H’0080 1136> CAN0 Message Slot 4 Data 0 (C0MSL4DT0) <Address: H’0080 1146> CAN0 Message Slot 5 Data 0 (C0MSL5DT0) <Address: H’0080 1156> CAN0 Message Slot 6 Data 0 (C0MSL6DT0) <Address: H’0080 1166> CAN0 Message Slot 7 Data 0 (C0MSL7DT0) <Address: H’0080 1176> CAN0 Message Slot 8 Data 0 (C0MSL8DT0) <Address: H’0080 1186> CAN0 Message Slot 9 Data 0 (C0MSL9DT0) <Address: H’0080 1196> CAN0 Message Slot 10 Data 0 (C0MSL10DT0) <Address: H’0080 11A6> CAN0 Message Slot 11 Data 0 (C0MSL11DT0) <Address: H’0080 11B6> CAN0 Message Slot 12 Data 0 (C0MSL12DT0) <Address: H’0080 11C6> CAN0 Message Slot 13 Data 0 (C0MSL13DT0) <Address: H’0080 11D6> CAN0 Message Slot 14 Data 0 (C0MSL14DT0) <Address: H’0080 11E6> CAN0 Message Slot 15 Data 0 (C0MSL15DT0) <Address: H’0080 11F6> CAN1 Message Slot 0 Data 0 (C1MSL0DT0) <Address: H’0080 1506> CAN1 Message Slot 1 Data 0 (C1MSL1DT0) <Address: H’0080 1516> CAN1 Message Slot 2 Data 0 (C1MSL2DT0) <Address: H’0080 1526> CAN1 Message Slot 3 Data 0 (C1MSL3DT0) <Address: H’0080 1536> CAN1 Message Slot 4 Data 0 (C1MSL4DT0) <Address: H’0080 1546> CAN1 Message Slot 5 Data 0 (C1MSL5DT0) <Address: H’0080 1556> CAN1 Message Slot 6 Data 0 (C1MSL6DT0) <Address: H’0080 1566> CAN1 Message Slot 7 Data 0 (C1MSL7DT0) <Address: H’0080 1576> CAN1 Message Slot 8 Data 0 (C1MSL8DT0) <Address: H’0080 1586> CAN1 Message Slot 9 Data 0 (C1MSL9DT0) <Address: H’0080 1596> CAN1 Message Slot 10 Data 0 (C1MSL10DT0) <Address: H’0080 15A6> CAN1 Message Slot 11 Data 0 (C1MSL11DT0) <Address: H’0080 15B6> CAN1 Message Slot 12 Data 0 (C1MSL12DT0) <Address: H’0080 15C6> CAN1 Message Slot 13 Data 0 (C1MSL13DT0) <Address: H’0080 15D6> CAN1 Message Slot 14 Data 0 (C1MSL14DT0) <Address: H’0080 15E6> CAN1 Message Slot 15 Data 0 (C1MSL15DT0) <Address: H’0080 15F6>

123456 D 7D0

C0MSL0DT0–C0MSL15DT0, C1MSL0DT0–C1MSL15DT0 <Upon exiting reset: Undefined> b Bit Name Function R W 0–7 C0MSL0DT0–C0MSL15DT0, Message slot data 0 R W C1MSL0DT0–C1MSL15DT0 These registers are the memory space for transmit and receive frames. Notes: During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) = "0". The first byte of the CAN frame data field corresponds to message slot n data 0. Data is transmitted or received beginning with the MSB side of the register.

13 13.2 CAN Module Related Registers CAN MODULE 13-6532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Data 1 (C0MSL0DT1) <Address: H’0080 1107> CAN0 Message Slot 1 Data 1 (C0MSL1DT1) <Address: H’0080 1117> CAN0 Message Slot 2 Data 1 (C0MSL2DT1) <Address: H’0080 1127> CAN0 Message Slot 3 Data 1 (C0MSL3DT1) <Address: H’0080 1137> CAN0 Message Slot 4 Data 1 (C0MSL4DT1) <Address: H’0080 1147> CAN0 Message Slot 5 Data 1 (C0MSL5DT1) <Address: H’0080 1157> CAN0 Message Slot 6 Data 1 (C0MSL6DT1) <Address: H’0080 1167> CAN0 Message Slot 7 Data 1 (C0MSL7DT1) <Address: H’0080 1177> CAN0 Message Slot 8 Data 1 (C0MSL8DT1) <Address: H’0080 1187> CAN0 Message Slot 9 Data 1 (C0MSL9DT1) <Address: H’0080 1197> CAN0 Message Slot 10 Data 1 (C0MSL10DT1) <Address: H’0080 11A7> CAN0 Message Slot 11 Data 1 (C0MSL11DT1) <Address: H’0080 11B7> CAN0 Message Slot 12 Data 1 (C0MSL12DT1) <Address: H’0080 11C7> CAN0 Message Slot 13 Data 1 (C0MSL13DT1) <Address: H’0080 11D7> CAN0 Message Slot 14 Data 1 (C0MSL14DT1) <Address: H’0080 11E7> CAN0 Message Slot 15 Data 1 (C0MSL15DT1) <Address: H’0080 11F7> CAN1 Message Slot 0 Data 1 (C1MSL0DT1) <Address: H’0080 1507> CAN1 Message Slot 1 Data 1 (C1MSL1DT1) <Address: H’0080 1517> CAN1 Message Slot 2 Data 1 (C1MSL2DT1) <Address: H’0080 1527> CAN1 Message Slot 3 Data 1 (C1MSL3DT1) <Address: H’0080 1537> CAN1 Message Slot 4 Data 1 (C1MSL4DT1) <Address: H’0080 1547> CAN1 Message Slot 5 Data 1 (C1MSL5DT1) <Address: H’0080 1557> CAN1 Message Slot 6 Data 1 (C1MSL6DT1) <Address: H’0080 1567> CAN1 Message Slot 7 Data 1 (C1MSL7DT1) <Address: H’0080 1577> CAN1 Message Slot 8 Data 1 (C1MSL8DT1) <Address: H’0080 1587> CAN1 Message Slot 9 Data 1 (C1MSL9DT1) <Address: H’0080 1597> CAN1 Message Slot 10 Data 1 (C1MSL10DT1) <Address: H’0080 15A7> CAN1 Message Slot 11 Data 1 (C1MSL11DT1) <Address: H’0080 15B7> CAN1 Message Slot 12 Data 1 (C1MSL12DT1) <Address: H’0080 15C7> CAN1 Message Slot 13 Data 1 (C1MSL13DT1) <Address: H’0080 15D7> CAN1 Message Slot 14 Data 1 (C1MSL14DT1) <Address: H’0080 15E7> CAN1 Message Slot 15 Data 1 (C1MSL15DT1) <Address: H’0080 15F7> 9 10 11 12 13 14 b15b8 C0MSL0DT1–C0MSL15DT1, C1MSL0DT1–C1MSL15DT1 <Upon exiting reset: Undefined> b Bit Name Function R W 8–15 C0MSL0DT1–C0MSL15DT1, Message slot data 1 R W C1MSL0DT1–C1MSL15DT1 These registers are the memory space for transmit and receive frames. Note: During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) is equal to or less than 1.

13-6632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Data 2 (C0MSL0DT2) <Address: H’0080 1108> CAN0 Message Slot 1 Data 2 (C0MSL1DT2) <Address: H’0080 1118> CAN0 Message Slot 2 Data 2 (C0MSL2DT2) <Address: H’0080 1128> CAN0 Message Slot 3 Data 2 (C0MSL3DT2) <Address: H’0080 1138> CAN0 Message Slot 4 Data 2 (C0MSL4DT2) <Address: H’0080 1148> CAN0 Message Slot 5 Data 2 (C0MSL5DT2) <Address: H’0080 1158> CAN0 Message Slot 6 Data 2 (C0MSL6DT2) <Address: H’0080 1168> CAN0 Message Slot 7 Data 2 (C0MSL7DT2) <Address: H’0080 1178> CAN0 Message Slot 8 Data 2 (C0MSL8DT2) <Address: H’0080 1188> CAN0 Message Slot 9 Data 2 (C0MSL9DT2) <Address: H’0080 1198> CAN0 Message Slot 10 Data 2 (C0MSL10DT2) <Address: H’0080 11A8> CAN0 Message Slot 11 Data 2 (C0MSL11DT2) <Address: H’0080 11B8> CAN0 Message Slot 12 Data 2 (C0MSL12DT2) <Address: H’0080 11C8> CAN0 Message Slot 13 Data 2 (C0MSL13DT2) <Address: H’0080 11D8> CAN0 Message Slot 14 Data 2 (C0MSL14DT2) <Address: H’0080 11E8> CAN0 Message Slot 15 Data 2 (C0MSL15DT2) <Address: H’0080 11F8> CAN1 Message Slot 0 Data 2 (C1MSL0DT2) <Address: H’0080 1508> CAN1 Message Slot 1 Data 2 (C1MSL1DT2) <Address: H’0080 1518> CAN1 Message Slot 2 Data 2 (C1MSL2DT2) <Address: H’0080 1528> CAN1 Message Slot 3 Data 2 (C1MSL3DT2) <Address: H’0080 1538> CAN1 Message Slot 4 Data 2 (C1MSL4DT2) <Address: H’0080 1548> CAN1 Message Slot 5 Data 2 (C1MSL5DT2) <Address: H’0080 1558> CAN1 Message Slot 6 Data 2 (C1MSL6DT2) <Address: H’0080 1568> CAN1 Message Slot 7 Data 2 (C1MSL7DT2) <Address: H’0080 1578> CAN1 Message Slot 8 Data 2 (C1MSL8DT2) <Address: H’0080 1588> CAN1 Message Slot 9 Data 2 (C1MSL9DT2) <Address: H’0080 1598> CAN1 Message Slot 10 Data 2 (C1MSL10DT2) <Address: H’0080 15A8> CAN1 Message Slot 11 Data 2 (C1MSL11DT2) <Address: H’0080 15B8> CAN1 Message Slot 12 Data 2 (C1MSL12DT2) <Address: H’0080 15C8> CAN1 Message Slot 13 Data 2 (C1MSL13DT2) <Address: H’0080 15D8> CAN1 Message Slot 14 Data 2 (C1MSL14DT2) <Address: H’0080 15E8> CAN1 Message Slot 15 Data 2 (C1MSL15DT2) <Address: H’0080 15F8> 123456 b 7b0 C0MSL0DT2–C0MSL15DT2, C1MSL0DT2–C1MSL15DT2 <Upon exiting reset: Undefined> b Bit Name Function R W 0–7 C0MSL0DT2–C0MSL15DT2, Message slot data 2 R W C1MSL0DT2–C1MSL15DT2 These registers are the memory space for transmit and receive frames. Note: During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) is equal to or less than 2.

13 13.2 CAN Module Related Registers CAN MODULE 13-6732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Data 3 (C0MSL0DT3) <Address: H’0080 1109> CAN0 Message Slot 1 Data 3 (C0MSL1DT3) <Address: H’0080 1119> CAN0 Message Slot 2 Data 3 (C0MSL2DT3) <Address: H’0080 1129> CAN0 Message Slot 3 Data 3 (C0MSL3DT3) <Address: H’0080 1139> CAN0 Message Slot 4 Data 3 (C0MSL4DT3) <Address: H’0080 1149> CAN0 Message Slot 5 Data 3 (C0MSL5DT3) <Address: H’0080 1159> CAN0 Message Slot 6 Data 3 (C0MSL6DT3) <Address: H’0080 1169> CAN0 Message Slot 7 Data 3 (C0MSL7DT3) <Address: H’0080 1179> CAN0 Message Slot 8 Data 3 (C0MSL8DT3) <Address: H’0080 1189> CAN0 Message Slot 9 Data 3 (C0MSL9DT3) <Address: H’0080 1199> CAN0 Message Slot 10 Data 3 (C0MSL10DT3) <Address: H’0080 11A9> CAN0 Message Slot 11 Data 3 (C0MSL11DT3) <Address: H’0080 11B9> CAN0 Message Slot 12 Data 3 (C0MSL12DT3) <Address: H’0080 11C9> CAN0 Message Slot 13 Data 3 (C0MSL13DT3) <Address: H’0080 11D9> CAN0 Message Slot 14 Data 3 (C0MSL14DT3) <Address: H’0080 11E9> CAN0 Message Slot 15 Data 3 (C0MSL15DT3) <Address: H’0080 11F9> CAN1 Message Slot 0 Data 3 (C1MSL0DT3) <Address: H’0080 1509> CAN1 Message Slot 1 Data 3 (C1MSL1DT3) <Address: H’0080 1519> CAN1 Message Slot 2 Data 3 (C1MSL2DT3) <Address: H’0080 1529> CAN1 Message Slot 3 Data 3 (C1MSL3DT3) <Address: H’0080 1539> CAN1 Message Slot 4 Data 3 (C1MSL4DT3) <Address: H’0080 1549> CAN1 Message Slot 5 Data 3 (C1MSL5DT3) <Address: H’0080 1559> CAN1 Message Slot 6 Data 3 (C1MSL6DT3) <Address: H’0080 1569> CAN1 Message Slot 7 Data 3 (C1MSL7DT3) <Address: H’0080 1579> CAN1 Message Slot 8 Data 3 (C1MSL8DT3) <Address: H’0080 1589> CAN1 Message Slot 9 Data 3 (C1MSL9DT3) <Address: H’0080 1599> CAN1 Message Slot 10 Data 3 (C1MSL10DT3) <Address: H’0080 15A9> CAN1 Message Slot 11 Data 3 (C1MSL11DT3) <Address: H’0080 15B9> CAN1 Message Slot 12 Data 3 (C1MSL12DT3) <Address: H’0080 15C9> CAN1 Message Slot 13 Data 3 (C1MSL13DT3) <Address: H’0080 15D9> CAN1 Message Slot 14 Data 3 (C1MSL14DT3) <Address: H’0080 15E9> CAN1 Message Slot 15 Data 3 (C1MSL15DT3) <Address: H’0080 15F9> 9 10 11 12 13 14 b15b8 C0MSL0DT3–C0MSL15DT3, C1MSL0DT3–C1MSL15DT3 <Upon exiting reset: Undefined> b Bit Name Function R W 8–15 C0MSL0DT3–C0MSL15DT3, Message slot data 3 R W C1MSL0DT3–C1MSL15DT3 These registers are the memory space for transmit and receive frames. Note: During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) is equal to or less than 3.

13-6832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Data 4 (C0MSL0DT4) <Address: H’0080 110A> CAN0 Message Slot 1 Data 4 (C0MSL1DT4) <Address: H’0080 111A> CAN0 Message Slot 2 Data 4 (C0MSL2DT4) <Address: H’0080 112A> CAN0 Message Slot 3 Data 4 (C0MSL3DT4) <Address: H’0080 113A> CAN0 Message Slot 4 Data 4 (C0MSL4DT4) <Address: H’0080 114A> CAN0 Message Slot 5 Data 4 (C0MSL5DT4) <Address: H’0080 115A> CAN0 Message Slot 6 Data 4 (C0MSL6DT4) <Address: H’0080 116A> CAN0 Message Slot 7 Data 4 (C0MSL7DT4) <Address: H’0080 117A> CAN0 Message Slot 8 Data 4 (C0MSL8DT4) <Address: H’0080 118A> CAN0 Message Slot 9 Data 4 (C0MSL9DT4) <Address: H’0080 119A> CAN0 Message Slot 10 Data 4 (C0MSL10DT4) <Address: H’0080 11AA> CAN0 Message Slot 11 Data 4 (C0MSL11DT4) <Address: H’0080 11BA> CAN0 Message Slot 12 Data 4 (C0MSL12DT4) <Address: H’0080 11CA> CAN0 Message Slot 13 Data 4 (C0MSL13DT4) <Address: H’0080 11DA> CAN0 Message Slot 14 Data 4 (C0MSL14DT4) <Address: H’0080 11EA> CAN0 Message Slot 15 Data 4 (C0MSL15DT4) <Address: H’0080 11FA> CAN1 Message Slot 0 Data 4 (C1MSL0DT4) <Address: H’0080 150A> CAN1 Message Slot 1 Data 4 (C1MSL1DT4) <Address: H’0080 151A> CAN1 Message Slot 2 Data 4 (C1MSL2DT4) <Address: H’0080 152A> CAN1 Message Slot 3 Data 4 (C1MSL3DT4) <Address: H’0080 153A> CAN1 Message Slot 4 Data 4 (C1MSL4DT4) <Address: H’0080 154A> CAN1 Message Slot 5 Data 4 (C1MSL5DT4) <Address: H’0080 155A> CAN1 Message Slot 6 Data 4 (C1MSL6DT4) <Address: H’0080 156A> CAN1 Message Slot 7 Data 4 (C1MSL7DT4) <Address: H’0080 157A> CAN1 Message Slot 8 Data 4 (C1MSL8DT4) <Address: H’0080 158A> CAN1 Message Slot 9 Data 4 (C1MSL9DT4) <Address: H’0080 159A> CAN1 Message Slot 10 Data 4 (C1MSL10DT4) <Address: H’0080 15AA> CAN1 Message Slot 11 Data 4 (C1MSL11DT4) <Address: H’0080 15BA> CAN1 Message Slot 12 Data 4 (C1MSL12DT4) <Address: H’0080 15CA> CAN1 Message Slot 13 Data 4 (C1MSL13DT4) <Address: H’0080 15DA> CAN1 Message Slot 14 Data 4 (C1MSL14DT4) <Address: H’0080 15EA> CAN1 Message Slot 15 Data 4 (C1MSL15DT4) <Address: H’0080 15FA> 123456 b 7b0 C0MSL0DT4–C0MSL15DT4, C1MSL0DT4–C1MSL15DT4 <Upon exiting reset: Undefined> b Bit Name Function R W 0–7 C0MSL0DT4–C0MSL15DT4, Message slot data 4 R W C1MSL0DT4–C1MSL15DT4 These registers are the memory space for transmit and receive frames. Note: During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) is equal to or less than 4.

13 13.2 CAN Module Related Registers CAN MODULE 13-6932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Data 5 (C0MSL0DT5) <Address: H’0080 110B> CAN0 Message Slot 1 Data 5 (C0MSL1DT5) <Address: H’0080 111B> CAN0 Message Slot 2 Data 5 (C0MSL2DT5) <Address: H’0080 112B> CAN0 Message Slot 3 Data 5 (C0MSL3DT5) <Address: H’0080 113B> CAN0 Message Slot 4 Data 5 (C0MSL4DT5) <Address: H’0080 114B> CAN0 Message Slot 5 Data 5 (C0MSL5DT5) <Address: H’0080 115B> CAN0 Message Slot 6 Data 5 (C0MSL6DT5) <Address: H’0080 116B> CAN0 Message Slot 7 Data 5 (C0MSL7DT5) <Address: H’0080 117B> CAN0 Message Slot 8 Data 5 (C0MSL8DT5) <Address: H’0080 118B> CAN0 Message Slot 9 Data 5 (C0MSL9DT5) <Address: H’0080 119B> CAN0 Message Slot 10 Data 5 (C0MSL10DT5) <Address: H’0080 11AB> CAN0 Message Slot 11 Data 5 (C0MSL11DT5) <Address: H’0080 11BB> CAN0 Message Slot 12 Data 5 (C0MSL12DT5) <Address: H’0080 11CB> CAN0 Message Slot 13 Data 5 (C0MSL13DT5) <Address: H’0080 11DB> CAN0 Message Slot 14 Data 5 (C0MSL14DT5) <Address: H’0080 11EB> CAN0 Message Slot 15 Data 5 (C0MSL15DT5) <Address: H’0080 11FB> CAN1 Message Slot 0 Data 5 (C1MSL0DT5) <Address: H’0080 150B> CAN1 Message Slot 1 Data 5 (C1MSL1DT5) <Address: H’0080 151B> CAN1 Message Slot 2 Data 5 (C1MSL2DT5) <Address: H’0080 152B> CAN1 Message Slot 3 Data 5 (C1MSL3DT5) <Address: H’0080 153B> CAN1 Message Slot 4 Data 5 (C1MSL4DT5) <Address: H’0080 154B> CAN1 Message Slot 5 Data 5 (C1MSL5DT5) <Address: H’0080 155B> CAN1 Message Slot 6 Data 5 (C1MSL6DT5) <Address: H’0080 156B> CAN1 Message Slot 7 Data 5 (C1MSL7DT5) <Address: H’0080 157B> CAN1 Message Slot 8 Data 5 (C1MSL8DT5) <Address: H’0080 158B> CAN1 Message Slot 9 Data 5 (C1MSL9DT5) <Address: H’0080 159B> CAN1 Message Slot 10 Data 5 (C1MSL10DT5) <Address: H’0080 15AB> CAN1 Message Slot 11 Data 5 (C1MSL11DT5) <Address: H’0080 15BB> CAN1 Message Slot 12 Data 5 (C1MSL12DT5) <Address: H’0080 15CB> CAN1 Message Slot 13 Data 5 (C1MSL13DT5) <Address: H’0080 15DB> CAN1 Message Slot 14 Data 5 (C1MSL14DT5) <Address: H’0080 15EB> CAN1 Message Slot 15 Data 5 (C1MSL15DT5) <Address: H'0080 15FB> 9 10 11 12 13 14 b15b8 C0MSL0DT5–C0MSL15DT5, C1MSL0DT5–C1MSL15DT5 <Upon exiting reset: Undefined> b Bit Name Function R W 8–15 C0MSL0DT5–C0MSL15DT5, Message slot data 5 R W C1MSL0DT5–C1MSL15DT5 These registers are the memory space for transmit and receive frames. Note: During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) is equal to or less than 5.

13-7032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Data 6 (C0MSL0DT6) <Address: H’0080 110C> CAN0 Message Slot 1 Data 6 (C0MSL1DT6) <Address: H’0080 111C> CAN0 Message Slot 2 Data 6 (C0MSL2DT6) <Address: H’0080 112C> CAN0 Message Slot 3 Data 6 (C0MSL3DT6) <Address: H’0080 113C> CAN0 Message Slot 4 Data 6 (C0MSL4DT6) <Address: H’0080 114C> CAN0 Message Slot 5 Data 6 (C0MSL5DT6) <Address: H’0080 115C> CAN0 Message Slot 6 Data 6 (C0MSL6DT6) <Address: H’0080 116C> CAN0 Message Slot 7 Data 6 (C0MSL7DT6) <Address: H’0080 117C> CAN0 Message Slot 8 Data 6 (C0MSL8DT6) <Address: H’0080 118C> CAN0 Message Slot 9 Data 6 (C0MSL9DT6) <Address: H’0080 119C> CAN0 Message Slot 10 Data 6 (C0MSL10DT6) <Address: H’0080 11AC> CAN0 Message Slot 11 Data 6 (C0MSL11DT6) <Address: H’0080 11BC> CAN0 Message Slot 12 Data 6 (C0MSL12DT6) <Address: H’0080 11CC> CAN0 Message Slot 13 Data 6 (C0MSL13DT6) <Address: H’0080 11DC> CAN0 Message Slot 14 Data 6 (C0MSL14DT6) <Address: H’0080 11EC> CAN0 Message Slot 15 Data 6 (C0MSL15DT6) <Address: H’0080 11FC> CAN1 Message Slot 0 Data 6 (C1MSL0DT6) <Address: H’0080 150C> CAN1 Message Slot 1 Data 6 (C1MSL1DT6) <Address: H’0080 151C> CAN1 Message Slot 2 Data 6 (C1MSL2DT6) <Address: H’0080 152C> CAN1 Message Slot 3 Data 6 (C1MSL3DT6) <Address: H’0080 153C> CAN1 Message Slot 4 Data 6 (C1MSL4DT6) <Address: H’0080 154C> CAN1 Message Slot 5 Data 6 (C1MSL5DT6) <Address: H’0080 155C> CAN1 Message Slot 6 Data 6 (C1MSL6DT6) <Address: H’0080 156C> CAN1 Message Slot 7 Data 6 (C1MSL7DT6) <Address: H’0080 157C> CAN1 Message Slot 8 Data 6 (C1MSL8DT6) <Address: H’0080 158C> CAN1 Message Slot 9 Data 6 (C1MSL9DT6) <Address: H’0080 159C> CAN1 Message Slot 10 Data 6 (C1MSL10DT6) <Address: H’0080 15AC> CAN1 Message Slot 11 Data 6 (C1MSL11DT6) <Address: H’0080 15BC> CAN1 Message Slot 12 Data 6 (C1MSL12DT6) <Address: H’0080 15CC> CAN1 Message Slot 13 Data 6 (C1MSL13DT6) <Address: H’0080 15DC> CAN1 Message Slot 14 Data 6 (C1MSL14DT6) <Address: H’0080 15EC> CAN1 Message Slot 15 Data 6 (C1MSL15DT6) <Address: H’0080 15FC> 123456 b 7b0 C0MSL0DT6–C0MSL15DT6, C1MSL0DT6–C1MSL15DT6 <Upon exiting reset: Undefined> b Bit Name Function R W 0–7 C0MSL0DT6–C0MSL15DT6, Message slot data 6 R W C1MSL0DT6–C1MSL15DT6 These registers are the memory space for transmit and receive frames. Note: During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) is equal to or less than 6.

13 13.2 CAN Module Related Registers CAN MODULE 13-7132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Data 7 (C0MSL0DT7) <Address: H’0080 110D> CAN0 Message Slot 1 Data 7 (C0MSL1DT7) <Address: H’0080 111D> CAN0 Message Slot 2 Data 7 (C0MSL2DT7) <Address: H’0080 112D> CAN0 Message Slot 3 Data 7 (C0MSL3DT7) <Address: H’0080 113D> CAN0 Message Slot 4 Data 7 (C0MSL4DT7) <Address: H’0080 114D> CAN0 Message Slot 5 Data 7 (C0MSL5DT7) <Address: H’0080 115D> CAN0 Message Slot 6 Data 7 (C0MSL6DT7) <Address: H’0080 116D> CAN0 Message Slot 7 Data 7 (C0MSL7DT7) <Address: H’0080 117D> CAN0 Message Slot 8 Data 7 (C0MSL8DT7) <Address: H’0080 118D> CAN0 Message Slot 9 Data 7 (C0MSL9DT7) <Address: H’0080 119D> CAN0 Message Slot 10 Data 7 (C0MSL10DT7) <Address: H’0080 11AD> CAN0 Message Slot 11 Data 7 (C0MSL11DT7) <Address: H’0080 11BD> CAN0 Message Slot 12 Data 7 (C0MSL12DT7) <Address: H’0080 11CD> CAN0 Message Slot 13 Data 7 (C0MSL13DT7) <Address: H’0080 11DD> CAN0 Message Slot 14 Data 7 (C0MSL14DT7) <Address: H’0080 11ED> CAN0 Message Slot 15 Data 7 (C0MSL15DT7) <Address: H’0080 11FD> CAN1 Message Slot 0 Data 7 (C1MSL0DT7) <Address: H’0080 150D> CAN1 Message Slot 1 Data 7 (C1MSL1DT7) <Address: H’0080 151D> CAN1 Message Slot 2 Data 7 (C1MSL2DT7) <Address: H’0080 152D> CAN1 Message Slot 3 Data 7 (C1MSL3DT7) <Address: H’0080 153D> CAN1 Message Slot 4 Data 7 (C1MSL4DT7) <Address: H’0080 154D> CAN1 Message Slot 5 Data 7 (C1MSL5DT7) <Address: H’0080 155D> CAN1 Message Slot 6 Data 7 (C1MSL6DT7) <Address: H’0080 156D> CAN1 Message Slot 7 Data 7 (C1MSL7DT7) <Address: H’0080 157D> CAN1 Message Slot 8 Data 7 (C1MSL8DT7) <Address: H’0080 158D> CAN1 Message Slot 9 Data 7 (C1MSL9DT7) <Address: H’0080 159D> CAN1 Message Slot 10 Data 7 (C1MSL10DT7) <Address: H’0080 15AD> CAN1 Message Slot 11 Data 7 (C1MSL11DT7) <Address: H’0080 15BD> CAN1 Message Slot 12 Data 7 (C1MSL12DT7) <Address: H’0080 15CD> CAN1 Message Slot 13 Data 7 (C1MSL13DT7) <Address: H’0080 15DD> CAN1 Message Slot 14 Data 7 (C1MSL14DT7) <Address: H’0080 15ED> CAN1 Message Slot 15 Data 7 (C1MSL15DT7) <Address: H’0080 15FD> 9 1 01 11 21 31 4 b 1 5b8 C0MSL0DT7–C0MSL15DT7, C1MSL0DT7–C1MSL15DT7 <Upon exiting reset: Undefined> b Bit Name Function R W 8–15 C0MSL0DT7–C0MSL15DT7, Message slot data 7 R W C1MSL0DT7–C1MSL15DT7 These registers are the memory space for transmit and receive frames. Note: During a receive slot, an undefined value is written to the register if the data length of the data frame being stored (DLC value) is equal to or less than 7.

13-7232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 CAN0 Message Slot 0 Timestamp (C0MSL0TSP) <Address: H’0080 110E> CAN0 Message Slot 1 Timestamp (C0MSL1TSP) <Address: H’0080 111E> CAN0 Message Slot 2 Timestamp (C0MSL2TSP) <Address: H’0080 112E> CAN0 Message Slot 3 Timestamp (C0MSL3TSP) <Address: H’0080 113E> CAN0 Message Slot 4 Timestamp (C0MSL4TSP) <Address: H’0080 114E> CAN0 Message Slot 5 Timestamp (C0MSL5TSP) <Address: H’0080 115E> CAN0 Message Slot 6 Timestamp (C0MSL6TSP) <Address: H’0080 116E> CAN0 Message Slot 7 Timestamp (C0MSL7TSP) <Address: H’0080 117E> CAN0 Message Slot 8 Timestamp (C0MSL8TSP) <Address: H’0080 118E> CAN0 Message Slot 9 Timestamp (C0MSL9TSP) <Address: H’0080 119E> CAN0 Message Slot 10 Timestamp (C0MSL10TSP) <Address: H’0080 11AE> CAN0 Message Slot 11 Timestamp (C0MSL11TSP) <Address: H’0080 11BE> CAN0 Message Slot 12 Timestamp (C0MSL12TSP) <Address: H’0080 11CE> CAN0 Message Slot 13 Timestamp (C0MSL13TSP) <Address: H’0080 11DE> CAN0 Message Slot 14 Timestamp (C0MSL14TSP) <Address: H’0080 11EE> CAN0 Message Slot 15 Timestamp (C0MSL15TSP) <Address: H’0080 11FE> CAN1 Message Slot 0 Timestamp (C1MSL0TSP) <Address: H’0080 150E> CAN1 Message Slot 1 Timestamp (C1MSL1TSP) <Address: H’0080 151E> CAN1 Message Slot 2 Timestamp (C1MSL2TSP) <Address: H’0080 152E> CAN1 Message Slot 3 Timestamp (C1MSL3TSP) <Address: H’0080 153E> CAN1 Message Slot 4 Timestamp (C1MSL4TSP) <Address: H’0080 154E> CAN1 Message Slot 5 Timestamp (C1MSL5TSP) <Address: H’0080 155E> CAN1 Message Slot 6 Timestamp (C1MSL6TSP) <Address: H’0080 156E> CAN1 Message Slot 7 Timestamp (C1MSL7TSP) <Address: H’0080 157E> CAN1 Message Slot 8 Timestamp (C1MSL8TSP) <Address: H’0080 158E> CAN1 Message Slot 9 Timestamp (C1MSL9TSP) <Address: H’0080 159E> CAN1 Message Slot 10 Timestamp (C1MSL10TSP) <Address: H’0080 15AE> CAN1 Message Slot 11 Timestamp (C1MSL11TSP) <Address: H’0080 15BE> CAN1 Message Slot 12 Timestamp (C1MSL12TSP) <Address: H’0080 15CE> CAN1 Message Slot 13 Timestamp (C1MSL13TSP) <Address: H’0080 15DE> CAN1 Message Slot 14 Timestamp (C1MSL14TSP) <Address: H’0080 15EE> CAN1 Message Slot 15 Timestamp (C1MSL15TSP) <Address: H’0080 15FE> b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 C0MSL0TSP–C0MSL15TSP , C1MSL0TSP–C1MSL15TSP <Upon exiting reset: Undefined> b Bit Name Function R W 0–15 C0MSL0TSP–C0MSL15TSP, Message slot timestamp R W C1MSL0TSP–C1MSL15TSP These registers are the memory space for transmit and receive frames. When transmission/reception has finished, the CAN timestamp count register value is written to the register.

13-7332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 13.3.1 CAN Protocol Frames (1)

13.3.1 CAN Protocol Frames

There are four types of frames that are handled by CAN protocol: (1) Data frame (2) Remote frame (3) Error frame (4) Overload frame Frames are separated from each other by an interframe space. 11 1 6 0–64 16 2 7 11 1 1 1 18 6 0–64 16 2 7 SOF EOF 11 1 6 16 2 7 11 1 1 1 18 6 16 2 7 Data frame Remote frame Standard format Standard format Extended format Note: The number in each field denotes the number of bits. Extended format Arbitration field Control field CRC field ACK field

13-7432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 13.3.2 CAN Protocol Frames (2) Error flag Error delimiter Interframe space or overload flag 6–12 8 Overload flag Overload delimiter 6–12 8 Interframe space or overload flag Error frame Overload frame Interframe space Intermission Bus idle SOF of the next frame For the case of an error active state 3 0– Suspend transmission For the case of an error passive state 3 8 0– SOF of the next frame Bus idle Intermission Note: The number in each field denotes the number of bits.

13.3.2 Data Formats during CAN Transmission/Reception

Figure 13.3.3 shows an example of the transmit/receive transfer data format that can be used in CAN. Data is transmitted/received sequentially beginning with the MSB side of the CAN message slot (C0MSLnSID0- C0MSLnDT7 and C1MSLnSID0-C1MSLnDT7). Figure 13.3.3 Example of CAN Transmit/Receive Transfer Data Format SOF SID0 SID1 SID2 SID3 MSB Arbitration field CAN frame Arbitration field b0 b1 b2 b3 b4 MSB Data field Data field

13-7532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.3.3 CAN Controller Error States

The CAN controller assumes one of the following three error states depending on the transmit error and re- ceive error counter values. (1) Error active state This is a state where almost no errors have occurred. When an error is detected, an active error flag is transmitted. The CAN controller is in the state immediately after being initialized. (2) Error passive state This is a state where many errors have occurred. When an error is detected, a passive error flag is transmitted. (3) Bus off state This is a state where a very large number of errors have occurred. CAN communication with other nodes cannot be performed until the CAN module returns to an error active state. Error Status of the Unit Transmit Error Counter Receive Error Counter Error active state 0–127 AND 0–127 Error passive state 128–255 OR 128 and over Bus off state 256 and over – Transmit error counter > 255 Transmit error counter ≥ 128 OR receive error counter ≥ 128 Transmit error counter < 128 AND receive error counter < 128 11 consecutive recessive bits detected on CAN bus 128 times (Note 1) Error active state Error passive state Bus off state Initial setting Note 1: With RBO (Return Bus Off) bit and FRST (Forcible Reset) bit, it can be forcibly exited from bus off state. For detail, see CAN Control Register (CANnCNT). Figure 13.3.4 CAN Controller Error States

13-7632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.4.1 Initializing the CAN Module

Before performing communication, set up the CAN module as described below. (1) Selecting pin functions The CAN transmit data output pin (CTX) and CAN receive data input pin (CRX) are shared with input/output ports. Be sure to select the functions of these pins. (See Chapter 8, “Input/Output Ports and Pin Functions.” (2) Setting the Interrupt Controller (ICU) To use CAN module interrupts, set their interrupt priority levels. (3) Setting CAN Error, CAN Single-Shot and CAN Slot Interrupt Request Mask Registers To use CAN bus error, CAN error passive, CAN error bus off, CAN single-shot or CAN slot interrupts, set each corresponding bit to "1" to enable the interrupt request. (4) Setting DMAC To use DMA transfers by CAN, be sure to set the DMAC. (5) Setting CAN DMA transfer request select register To use DMA transfers by CAN, set the CAN DMA transfer request select register to choose the cause of transfer request. (6) Setting the bit timing and the number of times sampled Using the CAN Configuration Register and CAN Baud Rate Prescaler, set the bit timing and the number of times the CAN bus is sampled. 1) Setting the bit timing Determine the period Tq that is the base of bit timing, the configuration of Propagation Segment, Phase Segment1 and Phase Segment2, and reSynchronization Jump Width. The equation to calculate Tq is given below. Tq = (BRP + 1) / (CPU clock) The baud rate is determined by the number of Tq’s that comprise one bit. The equation to calculate the baud rate is given below. Baud rate (bps) = Tq period × number of Tq’s in one bit Number of Tq’s in one bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 Note: The maximum baud rate for communication depends on the system configuration (e.g., bus length, clock error, CAN bus transceiver, sampling position and bit configuration). Consider the system configuration when setting the baud rate and number of Tq's.

13-7732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Synchronization Segment Propagation Segment Phase Segment1 Phase Segment2 (1)(2)(3) Sampling Point This diagram shows the bit timing when one bit consists of 8 Tq's. If one-time sampling is selected, the value sampled at Sampling Point (1) is assumed to be the value of the bit. If three-time sampling is selected, the value of the bit is determined by majority from CAN bus values sampled at Sampling Points (1), (2) and (3). 1Tq

1 Bit

Figure 13.4.1 Example of Bit Timing 2) Setting the number of times sampled Select the number of times the CAN bus is sampled from “one time” and “three times.” If one-time sampling is selected, the value sampled at only the end of Phase Segment1 is assumed to be the value of the bit. If three-time sampling is selected, the value of the bit is determined by majority from three sampled values, one sampled at the end of Phase Segment1 and the other sampled 1 Tq before and 2 Tq’s before that. (7) Setting the ID mask registers Set the values of ID mask registers (Global Mask Register, Local Mask Register A and Local Mask Register B) that are used in acceptance filtering of received messages. (8) Settings for use in BasicCAN mode Set the CAN Extended ID Register IDE14 and IDE15 bits. (We recommend setting the same value in these bits.) Set IDs in message slots 14 and 15. Set the Message Control Registers 14 and 15 for data frame reception (H’40). (9) Settings for use in single-shot mode Using the CAN Mode Register (CANnMODE) and CAN Control Register (CANnCNT), select CAN module operation mode (BasicCAN, loopback mode) and the clock source for the timestamp counter. (10) Setting CAN module operation mode In the CAN Single-Shot Mode Control Register, set the slot that is to be operated in single-shot mode. (11) Releasing CAN module from reset When settings (1) through (10) above are finished, clear the CAN Control Register (CANnCNT)’s forcible reset (FRST) and reset (RST) bits to "0". Then, after detecting 11 consecutive recessive bits on the CAN bus, the CAN module becomes ready to communicate.

13-7832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Initialize CAN module Set the Input/Output Port Operation Mode Register Set the Interrupt Controller Set CAN related interrupt request mask registers Set CAN Configuration Register Set the ID Mask Register Set CAN operation mode Negate CAN reset CAN module initialization completed Set interrupt priority Set the bit timing (baud rate) Set the number of times sampled Set the ID mask bit Set BasicCAN mode Set the CAN Extended ID Register Set IDs in message slots 14 and 15 Set the Message Slot Control Register Release CAN module from reset Set CAN Error Interrupt Request Mask Register Enable/disable CAN bus error interrupt request Enable/disable CAN error passive interrupt request Enable/disable CAN bus off interrupt request Set CAN Slot Interrupt Request Mask Register Enable/disable the interrupt request to be generated when transmission or reception in the relevant slot has finished Set CAN Single-shot Interrupt Request Mask Regiter Enable/disable the interrupt request to be generated when single-shot transission in the relevant slot has failed. Set loopback mode Clear CAN Control Register (CANnCNT)'s FRST and RST bits Set DMAC Set CAN DMA transfer request select register Set DMAC Select DMA transfer request source Figure 13.4.2 Initializing CAN Module

13-7932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.5.1 Data Frame Transmit Procedure

The following describes the procedure for transmitting data frames. (1) Initializing CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot to be transmitted by writing H’00 to the register. (2) Confirming that transmission is idle Read the CAN Message Slot Control Register that has been initialized and check the TRSTAT (Transmit/ Receive Status) bit to see that transmission/reception has stopped and remains idle. If this bit = "1", it means that the CAN module is accessing the message slot. Therefore, wait until the bit is cleared to "0". (3) Setting transmit data Set the transmit ID and transmit data in the message slot. (4) Setting the Extended ID Register Set the corresponding bit in the Extended ID Register to "0" if the data is to be transmitted as a standard frame, or "1" if the data is to be transmitted as an extended frame. (5) Setting CAN Message Slot Control Register Write H’80 (Note 1) to the CAN Message Slot Control Register to set the TR (Transmit Request) bit to "1". Note 1: Always be sure to write H’80 when transmitting data frames.

13-8032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Data frame transmit procedure Initialize CAN Message Slot Control Register Set ID and data in the message slot Set the Extended ID Register Set CAN Message Slot Control Register End of setting Write H'00 Select standard ID or extended ID Write H'80 (transmit request) Read CAN Message Slot Control Register TRSTAT bit = 0 YES NO Confirm that transmission and reception are idle Figure 13.5.1 Data Frame Transmit Procedure

13.5.2 Data Frame Transmit Operation

The following describes data frame transmit operation. The operations described below are automatically per- formed in hardware. (1) Selecting a transmit frame The CAN module checks slots which have transmit requests (including remote frame transmit slots) every intermission to determine the frame to transmit. If two or more transmit slots exist, frames are transmitted in order of slot numbers beginning with the smallest. (2) Transmitting a data frame After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit to "1" and starts transmitting. (3) If lost in CAN bus arbitration or a CAN bus error occurs If the CAN module lost in CAN bus arbitration or a CAN bus error occurs in the middle of transmission, the CAN module clears the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit to "0". If the CAN module requested a transmit abort, the transmit abort is accepted and the message slot is enabled for write.

13-8132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (4) Completion of data frame transmission When data frame transmission has finished, the CAN Message Slot Control Register’s TRFIN (Transmit/ Receive Finished) bit and the CAN Slot Interrupt Request Status Register are set to "1". Also, a timestamp count value at which transmission has finished is written to the CAN Message Slot Timestamp (C0MSLnTSP, C1MSLnTSP), and the transmit operation is thereby completed. If the CAN slot interrupt request has been enabled, an interrupt request is generated at completion of transmit operation. The slot which has had transmission completed goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software. B'1000 0010 B'0000 0001 (Note 1) B'1000 0001 B'0000 0000 (Note 1) B'1000 0000 Write H'80 Transmission aborted Transmit request accepted Note 1: When in this state, data can be written to the message slot. Transmission aborted Transmit reque st accepted Transmission aborted Transmission completed Transmission aborted Transmission completed Wait for transmission B'0000 0010 Lost in CAN bus arbitration or a CAN bus error occurs Lost in CAN bus arbitration or a CAN bus e rror occurs 1 2 3 4 5 6 b7 (b15)(b8)b0 RMRRTR RL RA ML TRSTAT TRFIN 00000000 CAN message slot control register bit allocation Transmission completed Figure 13.5.2 Operation of CAN Message Slot Control Register during Data Frame Transmission

13.5.3 Transmit Abort Function

The transmit abort function is used to cancel a transmit request that has once been set. This is accomplished by writing H’0F to the CAN Message Slot Control Register for the slot to be canceled. When transmit abort is accepted, the CAN module clears the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Sta- tus) bit to "0", allowing for data to be written to the message slot. The following shows the conditions under which transmit abort is accepted. [Conditions] When the target message is waiting for transmission When a CAN bus error occurs during transmission When lost in CAN bus arbitration

13-8232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.6.1 Data Frame Receive Procedure

The following describes the procedure for receiving data frames. (1) Initializing CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot to be received by writing H’00 to the register. (2) Confirming that reception is idle Read the CAN Message Slot Control Register that has been initialized and check the TRSTAT (Transmit/ Receive Status) bit to see that transmission and reception have stopped and remains idle. If this bit = "1", it means that the CAN module is accessing the message slot. Therefore, wait until the bit is cleared to "0". (3) Setting the receive ID Set the desired receive ID in the message slot. (4) Setting the Extended ID Register Set the corresponding bit in the Extended ID Register to "0" if a standard frame is to be received, or "1" if an extended frame is to be received. (5) Setting CAN Message Slot Control Register Write H’40 to the CAN Message Slot Control Register to set the RR (Receive Request) bit to "1".

13-8332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Data frame receive procedure Initialize CAN Message Slot Control Register Set ID in the message slot Set the Extended ID Register Set CAN Message Slot Control Register End of setting Write H'00 Select standard ID or extended ID Write H'40 (receive request) Read CAN Message Slot Control Register TRSTAT bit = 0 YES NO Confirm that transmission and reception are idle Figure 13.6.1 Data Frame Receive Procedure

13.6.2 Data Frame Receive Operation

The following describes data frame receive operation. The operations described below are automatically per- formed in hardware. (1) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies the conditions for receiving the received message, sequentially from slot 0 (up to slot 15). The following shows receive condi- tions for the slots that have been set for data frame reception. [Conditions] The received frame is a data frame. The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to "0" are “Don’t care.” The standard and extended frame types are the same. Note: In BasicCAN mode, slots 14 and 15 while being set for data frame reception can also receive remote frames.

13-8432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 B'0100 0011 B'0000 0001 B'0100 0001 B'0000 0000 B'0100 0000 Clear the receive requestWrite H'40 Start storing the received data Clear the receive request Store the received data Clear the rec eive re quest Finished storing the received data Finished storing th e received data Clear the receive reque st B'0000 0011 B'0100 0111 Start storing the received data (Message lost occurs) B'0100 0101 Finished storing the received data B'0000 0111 B'0000 0101 Start store the received data (Message lost occurs) Wait for the received data Wait for the received data Finished storing the received data Clear the receive request Clear the receive request Clear the receive request Finished storing the received data Store the received data Clear the rec eive re quest Finished storing th e received data Clear the rece ive reque st 1 2 3 4 5 6 b7 (b15)(b8)b0 RMRRTR RL RA ML TRSTAT TRFIN 00000000 CAN message slot control register bit allocation CPU read & TRFIN bit clear CPU read & TRFIN bit clear B'0100 0111 Figure 13.6.2 Operation of CAN Message Slot Control Register during Data Frame Reception (2) When the receive conditions are met When the receive conditions in (1) above are met, the CAN module sets the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit and TRFIN (Transmit/Receive Finished) bit to "1" while at the same time writing the received data to the message slot. If the TRFIN (Transmit/Receive Finished) bit is already set to "1" at this time, the CAN module also sets the ML (Message Lost) bit to "1", indicating that the message slot has been overwritten. The message slot has both of its ID and DLC fields entirely overwritten and has an undefined value written in its unused area (e.g., extended ID field during standard frame recep- tion and an unused data field). Furthermore, a timestamp count value at which the message was received is written to the CAN Message Slot Timestamp (C0MSLnTSP, C1MSLnTSP) along with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot Interrupt Request Status bit to "1". If the interrupt request for the slot has been enabled, the CAN module generates an interrupt request and enters a wait state for the next reception. (3) When the receive conditions are not met The received frame is discarded, and the CAN module goes to the next transmit/receive operation without writing to the message slot.

13-8532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.6.3 Reading Out Received Data Frames

The following shows the procedure for reading out received data frames from the slot. (1) Clearing TRFIN (Transmit/Receive Finished) bit Write H’4E, H’40 or H’00 to the CAN Message Slot Control Register (C0MSLnCNT, C1MSLnCNT) to clear the TRFIN bit to "0". After this write, the slot operates as follows: Values Written to Slot Operation after Write C0MSLnCNT, C1MSLnCNT H’4E Operates as a data frame receive slot. Whether overwritten can be verified by ML bit. H’40 Operates as a data frame receive slot. Whether overwritten cannot be verified by ML bit. H’00 (Note 1) The slot stops transmit/receive operation. Note 1: When the CAN Message Slot Control Register (C0MSLnCNT, C1MSLnCNT) RR (Receive Request) bit is cleared to "0" by writing H'00, and the receive operation has started until just before the bit is cleared, the transmit/ receive control will be performed until the receive operation is finished. Note: To conduct message lost check by ML bit, write H'4E and clear TRFIN bit. (2) Reading out from the message slot Read out a message from the message slot. (3) Checking TRFIN (Transmit/Receive Finished) bit Read the CAN Message Slot Control Register to check the TRFIN (Transmit/Receive Finished) bit. 1) If TRFIN (Transmit/Receive Finished) bit = "1" It means that new data was stored in the slot while still reading out a message from it in (2) above. In this case, the data read out in (2) may contain an undefined value. Therefore, reexecute the above procedure beginning with clearing of the TRFIN (Transmit/Receive Finished) bit in (1). 2) If TRFIN (Transmit/Receive Finished) bit = "0" It means that the CAN module finished reading out from the slot normally.

13-8632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Read out from the message slot Finished reading out received data Read CAN Message Slot Control Register TRFIN bit = 0 YES NO Write H'4E, H'40 or H'00 Figure 13.6.3 Procedure for Reading Out Received Data

13-8732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.7.1 Remote Frame Transmit Procedure

The following describes the procedure for transmitting remote frames. (1) Initializing CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot to be transmitted by writing H’00 to the register. (2) Confirming that transmission is idle Read the CAN Message Slot Control Register that has been initialized and check the TRSTAT (Transmit/ Receive Status) bit to see that transmission/reception has stopped and remains idle. If this bit = "1", it means that the CAN module is accessing the message slot. Therefore, wait until the bit is cleared to "0". (3) Setting transmit ID Set the ID to be transmitted in the message slot. (4) Setting the Extended ID Register Set the corresponding bit in the Extended ID Register to "0" if the data is to be transmitted as a standard frame, or "1" if the data is to be transmitted as an extended frame. (5) Setting CAN Message Slot Control Register Write H’A0 to the CAN Message Slot Control Register to set the TR (Transmit Request) bit and RM (Re- mote) bit to "1".

13-8832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Initialize CAN Message Slot Control Register Set ID in the message slot Set the Extended ID Register Set CAN Message Slot Control Register End of setting Write H'00 Select standard ID or extended ID Write H'A0 (transmit request, remote) Read CAN Message Slot Control Register TRSTAT bit = 0 YES NO Confirm that transmission and reception are idle Figure 13.7.1 Remote Frame Transmit Procedure

13.7.2 Remote Frame Transmit Operation

The following describes remote frame transmit operation. The operations described below are automatically performed in hardware. (1) Setting RA (Remote Active) bit The RA (Remote Active) bit is set to "1" at the same time H’A0 (Transmit Request, Remote) is written to the CAN Message Slot Control Register, indicating that the corresponding slot is to handle remote frames. (2) Selecting a transmit frame The CAN module checks slots which have transmit requests (including data frame transmit slots) every intermission to determine the frame to transmit. If two or more transmit slots exist, frames are transmitted in order of slot numbers beginning with the smallest. (3) Transmitting a remote frame After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit to "1" and starts transmitting.

13-8932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (4) If lost in CAN bus arbitration or a CAN bus error occurs If the CAN module lost in CAN bus arbitration or a CAN bus error occurs in the middle of transmission, the CAN module clears the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit to "0". If the CAN module requested a transmit abort, the transmit abort is accepted and the message slot is enabled for write. (5) Completion of remote frame transmission When remote frame transmission finishes, the timestamp count value at which transmission finished is written to the CAN Message Slot Timestamp (C0MSLnTSP, C1MSLnTSP) and the CAN Message Slot Control Register’s RA (Remote Active) bit is cleared to "0". In addition, the CAN Slot Interrupt Request Status bit is set to "1" by completion of transmission, but the CAN Message Slot Control Register’s TRFIN (Transmit/Receive Finished) bit is not set to "1". If the CAN slot interrupt request has been enabled, an interrupt request is generated when transmission has finished. (6) Receiving a data frame When remote frame transmission finishes, the slot automatically starts functioning as a data frame receive slot. (7) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies the conditions for receiving the received message, sequentially from slot 0 (up to slot 15). The following shows receive condi- tions for the slots that have been set for data frame reception. [Conditions] The received frame is a data frame. The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to "0" are “Don’t care.” The standard and extended frame types are the same. Note: In BasicCAN mode, slots 14 and 15 cannot be used as a transmit slot. (8) When the receive conditions are met When the receive conditions in (7) above are met, the CAN module sets the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit and TRFIN (Transmit/Receive Finished) bit to "1" while at the same time writing the received data to the message slot. If the TRFIN (Transmit/Receive Finished) bit is already set to "1" at this time, the CAN module also sets the ML (Message Lost) bit to "1", indicating that the message slot has been overwritten. The message slot has both of its ID and DLC fields entirely overwritten and has an undefined value written in its unused area (e.g., extended ID field during standard frame recep- tion and an unused data field). Furthermore, a timestamp count value at which the message was received is written to the CAN Message Slot Timestamp (C0MSLnTSP, C1MSLnTSP) along with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot Interrupt Request Status bit to "1". If the interrupt request for the slot has been enabled, the CAN module generates an interrupt request and enters a wait state for the next reception. Note: If the CAN module receives a corresponding data frame before sending a remote frame, it stores the received data frame in the slot and does not transmit the remote frame. (9) When the receive conditions are not met The received frame is discarded, and the CAN module goes to the next transmit/receive operation without writing to the message slot.

13-9032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 B'0000 0000 B'0000 0000 Starting storing the received data Lost in C AN bus arbitr ation or a CAN bus error o ccurr ed Clear the transm it reque st B'0000 1010 B'1010 0011 Start storing the received data Clear the transmit request B'0000 0011 B'0000 0001 Finished sending a remote frame CPU read and TRFIN bit clear B'1010 0101 B'1010 1000 B'1010 1010 Finished storing th e receive d data Clear the rece ive request Store the received data Clear the receive request B'1010 0001 B'1010 0111B'0000 0111 B'0000 0101 Finished storing the received data Finished sending a remote frame B'1010 0000 Wait for received data B'1010 1011 B'0000 1011 Clear the transmit request B'0000 0001 Finished storing the received data B'0000 1000 CAN bus error occurred Finished storing the received data Start storing the received data (message lost occurs) Start storing the received data (message lost occurs) Wait for received data Finished storing the received data Store the received data Clear the receive request Finished st oring the received da ta C lear t he receive req uest Finished storing the received data Write H'A0 Transmission aborted 1 2 3 4 5 6 b7 (b15)(b8)b0 RMRRTR RL RA ML TRSTAT TRFIN 00000000 CAN message slot control register bit allocation Finished storing the received data Recieve the transmit request Figure 13.7.2 Operation of the CAN Message Slot Control Register during Remote Frame Transmission

13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission

The following shows the procedure for reading out the data frames that have been received in the slot when it is set for remote frame transmission. (1) Clearing TRFIN (Transmit/Receive Finished) bit Write H’AE or H’00 to the CAN Message Slot Control Register (C0MSLnCNT, C1MSLnCNT) to clear the TRFIN bit to "0". After this write, the slot operates as follows: Values Written to Slot Operation after Write C0MSLnCNT, C1MSLnCNT H’AE Operates as a data frame receive slot. Whether overwritten can be verified by ML bit. H’00 The slot stops transmit/receive operation. Notes: If message-lost check by the ML bit is needed, write H’AE to clear the TRFIN bit. If the TRFIN bit was cleared by writing H’AE or H’00, it is possible that new data will be stored in the slot while still reading out a message from it. The received data frame cannot be read out by writing H’A0 to the register. If the TRFIN bit is cleared by writing H’A0, the slot performs remote frame transmit operation.

13-9132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Reading out received data Clear TRFIN bit to 0 Read out from the message slot Finished reading out received data Read CAN Message Slot Control Register TRFIN bit = 0 YES NO Write H'AE or H'00 Figure 13.7.3 Procedure for Reading Out Received Data when Set for Remote Frame Transmission (2) Reading out from the message slot Read out a message from the message slot. (3) Checking TRFIN (Transmit/Receive Finished) bit Read the CAN Message Slot Control Register to check the TRFIN (Transmit/Receive Finished) bit. 1) If TRFIN (Transmit/Receive Finished) bit = "1" It means that new data was stored in the slot while still reading out a message from it in (2) above. In this case, the data read out in (2) may contain an undefined value. Therefore, reexecute the above procedure beginning with clearing of the TRFIN (Transmit/Receive Finished) bit in (1). 2) If TRFIN (Transmit/Receive Finished) bit = "0" It means that the CAN module finished reading out from the slot normally.

13-9232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

13.8.1 Remote Frame Receive Procedure

The following describes the procedure for receiving remote frames. (1) Initializing CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot to be received by writing H’00 to the register. (2) Confirming that reception is idle Read the CAN Message Slot Control Register that has been initialized and check the TRSTAT (Transmit/ Receive Status) bit to see that reception has stopped and remains idle. If this bit = "1", it means that the CAN module is accessing the message slot. Therefore, wait until the bit is cleared to "0". (3) Setting the receive ID Set the desired receive ID in the message slot. (4) Setting the Extended ID Register Set the corresponding bit in the Extended ID Register to "0" if a standard frame is to be received, or "1" if an extended frame is to be received. (5) Setting CAN Message Slot Control Register 1) When automatic response (data frame transmission) for remote frame reception is desired Write H’60 to the CAN Message Slot Control Register to set the RR (Receive Request) bit and RM (Remote) bit to "1". 2) When automatic response (data frame transmission) for remote frame reception is to be disabled Write H’70 to the CAN Message Slot Control Register to set the RR (Receive Request) bit, RM (Remote) bit and RL (Automatic Response Enable) bit to "1". Note: During BasicCAN mode, slots 14 and 15, although capable of receiving remote frames, cannot automatically respond to remote frame reception.

13-9332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 13.8.1 Remote Frame Receive Procedure

13.8.2 Remote Frame Receive Operation

The following describes remote frame receive operation. The operations described below are automatically performed in hardware. (1) Setting RA (Remote Active) bit The RA (Remote Active) bit indicating that the corresponding slot is to handle remote frames is set to "1" at the same time H’60 (Receive Request, Remote, Automatic Response Enable) or H’70 (Receive Request, Remote, Automatic Response Disable) is written to the CAN Message Slot Control Register. (2) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies the conditions for receiving the received message, sequentially from slot 0 (up to slot 15). The following shows receive condi- tions for the slots that have been set for remote frame reception. [Conditions] The received frame is a remote frame. The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to "0" are “Don’t care.” The standard and extended frame types are the same. Initialize CAN Message Slot Control Register Set ID in the message slot Set the Extended ID Register Set CAN Message Slot Control Register End of setting Write H'00 Select standard ID or extended ID Write H'60 (receive request, remote and automatic response enable) Write H'70 (receive request, remote and automatic response disable) Read CAN Message Slot Control Register TRSTAT bit = 0 YES NO Confirm that transmission and reception are idle

13-9432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (3) When the receive conditions are met When the receive conditions in (2) above are met, the CAN module sets the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit and TRFIN (Transmit/Receive Finished) bit to "1" while at the same time writing the received data to the message slot. In addition, a timestamp count value at which the message was received is written to the CAN Message Slot Timestamp (C0MSLnTSP, C1MSLnTSP) along with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot Interrupt Request Status bit to "1". If the interrupt request for the slot has been enabled, the CAN module generates an interrupt request. Notes: The ID field and DLC value are written to the message slot. An undefined value is written to the extended ID area when receiving standard format frames. The data field is not written to. The RA and TRFIN bits are cleared to "0" after writing the received remote frame data. (4) When the receive conditions are not met The received data is discarded, and the CAN module waits for the next receive frame. No data is written to the message slot. (5) Operation after receiving a remote frame The operation performed after receiving a remote frame differs depending on how automatic response is set. 1) When automatic response is disabled The slot which has had reception completed goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software. 2) When automatic response is enabled After receiving a remote frame, the slot automatically changes to a data frame transmit slot and performs the transmit operation described below. In this case, the transmitted data conforms to the ID and DLC of the received remote frame.

Selecting a transmit frame The CAN module checks slots which have transmit requests (including remote frame transmit slots) every intermission to determine the frame to transmit. If two or more transmit slots exist, frames are transmitted in order of slot numbers beginning with the smallest.
Transmitting a data frame After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit to "1" and starts transmitting.
If lost in CAN bus arbitration or a CAN bus error occurs If the CAN module lost in CAN bus arbitration or a CAN bus error occurs in the middle of transmission, the CAN module clears the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit to "0". If the CAN module requested a transmit abort, the transmit abort is accepted and the message slot is enabled for write.
Completion of data frame transmission When data frame transmission has finished, the CAN Message Slot Control Register’s TRFIN (Transmit/Receive Finished) bit and the CAN Slot Interrupt Request Status Register are set to "1". Also, a timestamp count value at which transmission has finished is written to the CAN Message Slot Timestamp (C0MSLnTSP, C1MSLnTSP), and the transmit operation is thereby completed. If the CAN slot interrupt request has been enabled, an interrupt request is generated at completion of transmit operation. The slot which has had transmission completed goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software.

13-9532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 13.8.2 Operation of CAN Message Slot Control Register during Remote Frame Reception B'0000 0000 B'0000 0000 Clear the receive request B'0000 1010 B'0110 0010 Store the received data Clear the receive request B'0000 0010 B'0000 0001 Finished storing the received data B'0110 1000 B'0110 1011 Finished storing the received data Clear the receive request B'0110 0001 B'0110 0000 B'0000 1011 B'0000 0000 Wait for reception Send a data frame Clear the receive request Finished sending a data frame Finished sending a data frame Send a data frame Finished storing the received data Store the received data B'0111 1011 Store the received data B'0111 0000 Finished storing the received data Finished storing the received dataClear the receive reque st Store the received data Clear the receive request Write H'60 (automatic response enabled) Write H'70 (automatic response disabled) 1 2 3 4 5 6 b7 (b15)(b8)b0 RMRRTR RL RA ML TRSTAT TRFIN 00000000 CAN message slot control register bit allocation B'0110 1000 B'0111 1000 Wait for reception Store the received data Clear the receiverequest Finished storing the received data Clear the receive request Store the received dataClear the receive request Lost in CAN bus arbitration CAN bus error occurred

13-9632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

Note for cancelation of transmit and receive CAN remote frame When aborting remote frame transmission or canceling remote frame receiving, make sure that the RA (Re- mote Active) bit is cleared to "0" after writing "H'00" or "H'0F" to the CAN Message Slot Control Register. (1) When aborting remote frame transmission Figure 13.9.1 Opertion Flow when Aborting Remote Frame Transmission (2) When canceling remote frame receiving Figure 13.9.2 Opertion Flow when Canceling Remote Frame Receiving RA (Remote Active) bit = "0" Complete transmission abort Note 1: H'00 or H'0F can be used. No Ye s Start transmission abort Write H'00 or H'0F to CAN message slot control register (Note 1) Read CAN message slot control register Complete receiving abort No Ye s Start receiving abort Write H'00 or H'0F to CAN message slot control register (Note 1) Read CAN message slot control register RA (Remote Active) bit = "0" Note 1: H'00 or H'0F can be used.

REAL TIME DEBUGGER (RTD)

14.1 Outline of the Real-Time Debugger (RTD)

14.2 Pin Functions of RTD

14.3 RTD Related Register

14.4 Functional Description of RTD

14.5 Typical Connection with the Host

REAL TIME DEBUGGER (RTD) 14-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The Real-Time Debugger (RTD) is a serial interface through which to read or write to any location in the entire area of the internal RAM by using commands from outside the microcomputer. Because data transfers between the RTD and internal RAM are performed via a dedicated internal bus independently of the M32R, RTD operation can be controlled without the need to stop the M32R. Table 14.1.1 Outline of the Real-Time Debugger (RTD) Item Description Transfer method Clock-synchronous serial interface Generation of transfer clock Generated by external host RAM access area Entire area of the internal RAM (controlled by A16–A29) Transmit/receive data length 32 bits (fixed) Bit transfer sequence LSB first Maximum transfer rate 2 Mbits/second Input/output pins 4 pins (RTDTXD, RTDRXD, RTDACK, RTDCLK) Number of commands Following five functions Monitor continuously Output real-time RAM content Forcibly rewrite RAM content (with verify) Recover from runaway condition Request RTD interrupt Figure 14.1.1 Block Diagram of the Real-Time Debugger (RTD)

REAL TIME DEBUGGER (RTD) 14-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Pin Functions of the RTD are shown below. Table 14.2.1 Pin Functions of RTD Pin Name Type Function RTDTXD Output RTD serial data output RTDRXD Input RTD serial data input RTDACK Output Output a "L" level pulse synchronously with the beginning clock edge of the output data word. The width of this pulse indicates the type of instruction or data the RTD has received. 1 clock period: VER (continuous monitor) command 1 clock period: VEI (RTD interrupt request) command 2 clock periods: RDR (real-time RAM content output) command 3 clock periods: WRR (RAM content forcible rewrite) command or the data to rewrite 4 clock periods or more: RCV (recover from runaway) command RTDCLK Input RTD transfer clock input The following shows an RTD related register map. RTD Related Register Map Address +0 address +1 address See b0 b7 b8 b15 page H'0080 077A (Use inhibited area) RTD write function disable register 14-3 (WRRDIS)

14.3.1 RTD Write Function Disable Register

RTD Write Function Disable Register (WRRDIS) <Address: H'0080 077B> 9 10 11 12 13 14 b15b8 RTDWR DIS 00 0 0 0 0 00 <Upon exiting reset: H'00> b Bit Name Function R W 8–14 No function assigned. Fix to "0" 00

15 RTDWRDIS 0: Write to RAM by RTD enabled R W

Write to RAM by RTD disable bit 1: Write to RAM by RTD disabled This register is used to select whether to enable or disable a write to RAM by the RTD. Setting the RTDWRDIS bit to 1 disables a write to RAM by the RTD, so that even when the RTD receives a command for write to RAM, the command is ignored and no write operation to RAM is executed. Notes Do not alter settings while using the RTD.

REAL TIME DEBUGGER (RTD) 14-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

14.4.1 Outline of RTD Operation

Operation of the RTD is specified by a command entered from devices external to the chip. A command is indicated by bits 16–19 (Note 1) of the RTD received data. Table 14.4.1 RTD Commands RTD Received Data Command b19 b18 b17 b16 Mnemonic RTD Function

0000 VER (VERify) Continuous monitor

0 1 1 0 VEI (VErify Interrupt request) RTD interrupt request

0010 RDR (ReaD RAM) Real-time RAM content output

0011 WRR (WRite RAM) RAM content forcible rewrite (with verify)

1111 RCV (ReCoVer) Recover from runaway condition (Note 2), (Note 3)

0001 System reserved (use inhibited)

↑ (Note 1) Note 1: The RTD received data bit 19 actually is not stored in the command register, and except for the RCV command, handled as a “Don’t care” bit. (Bits 16–18 are effective for the command specified.) Note 2: The RCV command must always be transmitted twice in succession. Note 3: For the RCV command, all bits, not just 16–19, (i.e., bits 0–15 and bits 20–31) must be set to "1".

14.4.2 Operation of RDR (Real-time RAM Content Output)

When the RDR (real-time RAM content output) command is issued, the RTD is enabled to transfer the contents of the internal RAM to external devices without causing the CPU’s internal bus to stop. Because the RTD reads data from the internal RAM while there are no transfers performed between the CPU and internal RAM, no extra CPU load is incurred. Only the 32-bit word-aligned addresses can be specified for read from the internal RAM. (The two low-order address bits specified by a command are ignored.) Data are read out and transferred from the internal RAM in 32-bit units. Figure 14.4.1 RDR Command Data Format X 0 0 10 19 18 17 16 14 13 12 1 A16 X A17A28A29 Command (RDR) Specified address Note: X = Don't care. (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) RTDRXD (MSB side)(LSB side)

REAL TIME DEBUGGER (RTD) 14-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 32 clock periods RDR (A1) RDR (A2) RDR (A3) D (A1) D (A2) Note: (An) = Specified address D(An) = Data at specified address (An) RTDCLK RTDRXD RTDTXD RTDACK 32 clock periods 32 clock periods 32 clock periods 2 clock periods Figure 14.4.2 Operation of RDR Command Figure 14.4.3 Read Data Transfer Format b31 b30 Read data RTDTXD Note: The read data is transferred LSB-first. (MSB side)(LSB side)

REAL TIME DEBUGGER (RTD) 14-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 32 clock periods 32 clock periods WRR(A1) (A1) Write data 3 clock periods RTDCLK RTDRXD RTDTXD RTDACK WRR(A2) (A2) Write data D (A1) Read value before writing D (A1) Verify value after writing Notes: (An) = Specified address D (An) = Data at specified address (An) 32 clock periods 32 clock periods Figure 14.4.5 Operation of WRR Command

14.4.3 Operation of WRR (RAM Content Forcible Rewrite)

When the WRR (RAM content forcible rewrite) command is issued, the RTD forcibly rewrites the contents of the internal RAM without causing the CPU’s internal bus to stop. Because the RTD writes data to the internal RAM while there are no transfers performed between the CPU and internal RAM, no extra CPU load is incurred. Only the 32-bit word-aligned addresses can be specified for read from the internal RAM. (The two low-order address bits specified by a command are ignored.) Data are written to the internal RAM in 32-bit units. The external host should transmit the command and address in the first frame and then the write data in the second frame. The RTD writes to the internal RAM in the third frame after receiving the write data. Figure 14.4.4 WRR Command Data Format The RTD reads out data from the specified address before writing to the internal RAM and again reads out data from the same address immediately after writing to the internal RAM (this helps to verify the data written to the internal RAM). The read data is output at the timing shown below. X 0 0 11 19 18 17 16 14 13 12 1 A16 X A17A28A29 Command (WRR) Specified address Notes: X = Don't care. (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) The specified address and write data are transferred LSB-first. b31 b30 Write data RTDRXD (MSB side) (MSB side) (LSB side) (LSB side) RTDRXD a) First frame b) Second frame

REAL TIME DEBUGGER (RTD) 14-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

14.4.4 Operation of VER (Continuous Monitor)

When the VER (continuous monitor) command is issued, the RTD outputs the data from the address that has been accessed by an instruction (either read or write) immediately before receiving the VER command. Figure 14.4.6 VER (Continuous Monitor) Command Data Format 32 clock periods RDR(A1) VER 2 clock periods RTDCLK RTDRXD RTDTXD RTDACK D (A1) Read value D (A1) Latest read value (Note 1) VER Note 1: WRR command can also be used. Notes: (An) = Specified address D(An) = Data at specified address (An) 32 clock periods 32 clock periods 32 clock periods Figure 14.4.7 Operation of VER (Continuous Monitor) Command

14.4.5 Operation of VEI (Interrupt Request)

When the VEI (interrupt request) command is issued, an RTD interrupt request is generated. Furthermore, the RTD outputs the data from the address that has been accessed by an instruction (either read or write) immediately before receiving the VEI command. X0 0 00 19 18 17 16 15 14 0 X Command (VER) Notes: X = Don't care. (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) RTDRXD X (MSB side)(LSB side) Figure 14.4.8 VEI (Interrupt Request) Command Data Format X0 1 10 19 18 17 16 15 14 0 X VEI (interrupt request generation) command RTDRXD X Note: X = Don't care. (However, if issued immediately after the VEI command, bits 20-31 must all be set to 1.) (MSB side)(LSB side)

REAL TIME DEBUGGER (RTD) 14-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 14.4.10 RCV Command Data Format 1 1 1 11 19 18 17 16 15 0 Command (RCV) RTDRXD 1 Notes: All of 32 data bits are 1's. The RCV command must always be issued twice in succession. (MSB side)(LSB side) 32 clock periods RDR(A1) VEI 2 clock periods RTDCLK RTDRXD RTDTXD RTDACK RTD interrupt request RTD interrupt D (A1) Read value Note 1: WRR command can also be used. Notes: (An) = Specified address D(An) = Data at specified address (An) 32 clock periods 32 clock periods 32 clock periods (Note 1) D (A1) Read value Figure 14.4.9 Operation of VEI (Interrupt Request) Command

14.4.6 Operation of RCV (Recover from Runaway)

If the RTD runs out of control, the RCV (recover from runaway) command may be issued to recover from the runaway condition without the need to reset the system. The RCV command must always be issued twice in succession. Also, any command issued immediately following the RCV command must have all of its bits 20– 31 set to 1.

REAL TIME DEBUGGER (RTD) 14-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 RCV RCV command stored RTDCLK RTDRXD RTDTXD RTDACK RCV Bits 20-31 D(A1)Undefined data during runaway condition Undefined value during runaway condition Note: The next command following the RCV command must have all of its bits 20-31 set to 1. Next command following RCV command 2 clock periods 1 1 RDR(A1) 32 clock periods 32 clock periods 32 clock periods 32 clock periods 2 clock periods Figure 14.4.11 Operation of RCV Command

14.4.7 Method for Setting a Specified Address when Using RTD

In the Real-Time Debugger (RTD), the low-order 16-bit addresses of the internal RAM can be specified. Be- cause the internal RAM is located in a 24-KB area ranging from H’0080 4000 to H’0080 9FFF, the low-order 16- bit address of that area (H’4000 to H’FFFF) can be set. However, to access any area other than RAM is inhibited. Note also that two least significant address bits, A31 and A30, area always 0 because data are read and written to and from the internal RAM in a fixed length of 32 bits. SFR 16KB H'0080 0000 H'0080 4000 Memory map H'0080 9FFF X X A29 – A16 Only H'0080 4000 to H'0080 9FFF can be specified RAM area 24 KB Figure 14.4.12 Setting Addresses in the Real-Time Debugger

REAL TIME DEBUGGER (RTD) 14-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

14.4.8 Resetting RTD

The RTD is reset by applying a system reset (i.e., RESET# signal input). The status of the RTD related output pins after a system reset are shown below. Table 14.4.2 RTD Pin Status after System Reset Pin Name Status RTDACK "H" level output RTDTXD "H" level output The first command transfer to the RTD after being reset is initiated by transferring data to the RTDRXD pin synchronously with the falling edge of RTDCLK. 32 clock periods Don't Care RDR(A1) RTDCLK RTDRXD RTDTXD RTDACK RESET# System reset "H" RDR(A2) 0000 0000 0000 0000 D(A2) Notes: (An) = Specified address D(An) = Data at specified address (An) "H" D(A1) 32 clock periods 32 clock periods 32 clock periods Figure 14.4.13 Command Transfer to RTD after System Reset

REAL TIME DEBUGGER (RTD) 14-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (8 bits) Check that the RTDACK signal is "L." RTDCLK RTDRXD RTDTXD RTDACK Transfer of one frame (32 bits) Transfer of the next frame (8 bits) (8 bits) Figure 14.5.2 Example of Communication with the Host (when Using VER Command) The host uses a serial synchronous interface to transfer data. The clock for synchronous communication should be generated by the host. An example for connecting the RTD and host is shown below. Figure 14.5.1 Connecting the RTD and Host The RTD communication is performed in a fixed length of 32 bits per frame. Because serial interfaces generally handle data in 8-bit units, data is transferred separately in four operations, 8 bits at a time. The RTDACK signal is used to verify that communication is performed normally. The RTDACK signal goes "L" after a command is sent, providing a means of verifying the communication status. When issuing the VER command, the RTDACK signal is pulled "L" for only one clock period. Therefore, after sending 32 bits in one frame via a serial interface, turn off RTDCLK output and check that RTDACK is "L." That way, it is possible to know whether the RTD is communicating normally. If it is desirable to identify the type of transmitted command by the width of RTDACK, use the microcomputer’s internal measurement timer (to count RTDCLK pulses while RTDACK is "L"), or design a dedicated circuit. RTDRXD RTDTXD RTDCLK RTDACK M32R/ECU Host microprocessor RXD TXD SCLK PORT(Note 1) Note 1: This applies to the case where the RTDACK level is checked between transfer frames.

REAL TIME DEBUGGER (RTD) 14-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 This page is blank for reasons of layout.

15.1 External Bus Interface Related Signals

15.2 External Bus Interface Related Registers

15.3 Read/Write Operations

15.4 Bus Arbitration

15.5 Typical Connection of External Extension

15-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The 32176 has the external bus interface related signals described below. These signals can be used in external extension and processor modes. The symbol “#” suffixed to the signal names (or pin names) means that the signals (or pins) are active "L." (1) Address The 32176 outputs a 19-bit address (A12–A30) for addressing any location in a 1-Mbyte space. The least significant A31 is not output. (2) Chip select (CS0#, CS1#) The CS0# and CS1# signals are output for external extension areas divided in 2-Mbyte units. The CS0# signal points to a 2-Mbyte area during processor mode or a 1-Mbyte area during external extension mode. (For details, see Chapter 3, “Address Space.”) (3) Read strobe (RD#) Output during an external read cycle, this signal indicates the timing at which to read data from the bus. This signal is driven "H" when writing to the bus or accessing the internal area. (4) Byte High Write/Byte High Enable (BHW#/BHE#) The pin function changes depending on the Bus Mode Control Register (BUSMODC). When BUSMOD = "0" and this signal is Byte High Write (BHW#), during external write access it indicates that the upper byte (DB0–DB7) of the data bus is the valid data transferred. During external read and when accessing the internal area it outputs a "H." When BUSMOD = "1" and this signal is Byte High Enable (BHE#), during external access (for read or write) it indicates that the upper byte (DB0–DB7) of the data bus is the valid data transferred. When accessing the internal area it outputs a "H." (5) Byte Low Write/Byte Low Enable (BLW#/BLE#) The pin function changes depending on the Bus Mode Control Register (BUSMODC). When BUSMOD = "0" and this signal is Byte Low Write (BLW#), during external write access it indicates that the lower byte (DB8–DB15) of the data bus is the valid data transferred. During external read and when accessing the internal area it outputs a "H." When BUSMOD = "1" and this signal is Byte Low Enable (BLE#), during external access (for read or write) it indicates that the lower byte (DB8–DB15) of the data bus is the valid data transferred. When accessing the internal area it outputs a "H." (6) Data bus (DB0–DB15) This is the 16-bit data bus used to access external devices. During external read access, data is latched from the bus synchronously with the rising edge of the read strobe. Even during 8-bit read, the microcom- puter always reads in 16 bits of data, with only the valid byte part of data transferred into the internal circuit. During external write access, data is output from the bus. During 8-bit write, the microcomputer outputs the valid byte part of data to be written as BHW#/BLW#. When accessing the internal area, the bus functions as an input bus.

15.1 Outline of the External Bus Interface

15-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (7) System clock/write (BCLK/WR#) The pin function changes depending on the Bus Mode Control Register (BUSMODC). When BUSMOD = "0" and this signal is System Clock (BCLK), it outputs the system clock necessary to synchronize operations in an external system. When the CPU clock = 40 MHz, a 20 MHz clock is output from BCLK. When not using the BCLK/WR function, this pin can be used as P70 by clearing the P7 Opera- tion Mode Register P70MOD bit to "0". When BUSMOD = "1" and this signal is Write (WR#), during external write access it indicates the valid data transferred on the data bus. During external read cycle and when accessing the internal area it outputs a "H." (8) Wait (WAIT#) When the 32176 started an external bus cycle, it automatically inserts wait states while the WAIT# input signal is asserted. For details, see Chapter 16, “Wait Controller.” When not using the WAIT function, this pin can be used as P71 by clearing the P7 Operation Mode Register P71MOD bit to "0". For external access, one or more wait cycles always need to be inserted. Therefore, the shortest possible access to an external device is equal to one wait cycle (2 BCLK periods). (9) Hold control (HREQ#, HACK#) The hold state means that internal bus and external bus stop accessing the bus and the bus interface related pins are tristated (high impedance). While the microcomputer is in a hold state, any bus master external to the chip can use the system bus to transfer data. Even during hold status the command in which command que is done though, if the command with access to bus is done, the command performance operation is stopped at that time. A "L" signal input on the HREQ# pin places the microcomputer into a hold state. While the microcomputer remains in a hold state after accepting the hold request and during a transition to the hold state, the HACK# pin outputs a "L" level signal. To exit the hold state and return to normal operating state, release the HREQ# signal back "H." Furthermore, when not using the HREQ and HACK functions, these pins can be used as P72 and P73 by clearing P72MOD and P73MOD in the P7 Operation Mode Register to 0. The status of each pin during hold are shown below. Table 15.1.1 Pin State during Hold Period Pin Name Pin State or Operation A12–A30, DB0–DB15, CS0#, CS1#, RD#, BHW#, BLW#, BHE#, BLE#, WR# High impedance HACK# Output a "L" Other pins (e.g., ports and timer output) Normal operation

15-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The following describes the external bus interface related registers.

15.2.1 Port Operation Mode Register

Ports P70–P73 can be switched for external access signal pins at any time irrespective of the CPU operation mode. P7 Operation Mode Register (P7MOD) <Address: H’0080 0747> <Upon exiting reset: H’00> b Bit Name Function R W Port P70 operation mode bit (Note 2) 1: BCLK/WR# Port P71 operation mode bit 1: WAIT# Port P72 operation mode bit 1: HREQ# Port P73 operation mode bit 1: HACK# Port P74 operation mode bit 1: RTDTXD/TXD3 (Note 1) Port P75 operation mode bit 1: RTDRXD/RXD3 (Note 1) Port P76 operation mode bit 1: RTDACK/CTX1 (Note 1) Port P77 operation mode bit 1: RTDCLK/CRX1 (Note 1) Note 1: Either of the functions is selected using the P7 Peripheral Function Select Register. Note 2: During external extension mode, when BUSMOD bit of the BUSMODC register is set to 1 (Byte enable separate mode), P70/ BCLK/WR# pin functions to output WR# signal regardless of the settings for the P7 Operation Mode Register. b 8 9 1 01 11 21 31 4 b 1 5 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD 00000000

15-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

15.2.2 Bus Mode Control Register

Bus Mode Control Register (BUSMODC) <Address: H’0080 077F> <Upon exiting reset: H’00> b Bit Name Function R W 8–14 No function assigned. Fix to "0" 00

15 BUSMOD 0: WR signal separate mode R W

Bus mode control bit (Note 1) 1: Byte enable separate mode Note 1: During external extension mode, when BUSMOD bit of the BUSMODC register is set to 1 (Byte enable separate mode), P70/ BCLK/WR# pin functions to output WR# signal regardless of the settings for the P7 Operation Mode Register. This register is used to facilitate memory connections during processor mode and external extension mode. When the Bus Mode Control bit (BUSMOD) = "0", the WR# signal is output separately for each byte area. Signals RD#, BHW#, BLW#, BCLK# and WAIT# can be used. For memory connection in boot mode, the Bus Mode Control Register has no effect, and the microcomputer operates in the same way as when the Bus Mode Control bit (BUSMOD) is cleared to "0". When the Bus Mode Control bit (BUSMOD) = "1", the byte enable signal is output separately for each byte area. Signals RD#, BHE#, BLE#, WR# and WAIT# can be used. In a WAIT control circuit configuration, be- cause BCLK output is not available, timing must be controlled external to the chip. Figure 15.2.1 Pin Functions when External Bus Modes are Changed CS0#, CS1# DB0–DB15 WAIT# RD# BHW# BLW# A12–A30 CS0#, CS1# DB0–DB15 WAIT# RD# WR# BHE# BLE# A12–A30 BCLK BUSMOD bit = 0 BUSMOD bit = 1 b 8 9 1 01 11 21 31 4 b 1 5 BUSMOD 00000000

15-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (1) When the Bus Mode Control Register is set to "0" External read/write operations are performed using the address bus, data bus and the signals CS0#,CS1#, RD#, BHW#, BLW#, WAIT# and BCLK. In the external read cycle, the RD# signal is "L" while BHW# and BLW# both are "H", with data read in from only the necessary byte position. In the external write cycle, the BHW# or BLW# signal output for the byte position to write is asserted "L" as data is written to the bus. When an external bus cycle starts, wait states are inserted as long as the WAIT# signal is "L." Unless necessary, the WAIT# signal must always be held "H." One wait cycle always need to be inserted even for the shortest external access. (The shortest possible bus cycle is 2 BCLK periods). Figure 15.3.1 Internal Bus Access during Bus Free State "H" BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" Hi-Z Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note: Hi-Z denotes a high-impedance state. (Don't Care) Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated)

15-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 15.3.2 Read/Write Timing (for Shortest External Access) Read Read (2 cycles) BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note: Circles in the above diagram denote the sampling timing. Internal 1 wait state (Don't Care)(Don't Care) Write Write (2 cycles) BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" Internal 1 wait state (Don't Care)(Don't Care) Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) "H" "H"

15-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 15.3.3 Read/Write Timing (for Access with Internal 2 and External 1 Wait States) Read Write Read (4 cycles) BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note: Circles in the above diagram denote the sampling timing. "L" Internal 2 wait states External 1 wait state (Don't Care) "H" (Don't Care) Write (4 cycles) BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" "L" (Don't Care) "H" (Don't Care) Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) Internal 2 wait states External 1 wait state

15-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) When the Bus Mode Control Register is set to "1" External read/write operations are performed using the address bus, data bus and the signals CS0#, CS1#, RD#, BHE#, BLE#, WAIT# and WR#. In the external read cycle, the RD# signal is "L" and the BHE# or BLE# signal output for the byte position from which to read is asserted "L", with data read in from only the neces- sary byte position of the bus. In the external write cycle, the WR# signal goes "L" and the BHE# or BLE# signal output for the byte position to write is asserted "L", with data written to the necessary byte position. When an external bus cycle starts, wait states are inserted as long as the WAIT# signal is "L." Unless necessary, the WAIT# signal must always be held "H." One wait cycle always need to be inserted even for the shortest external access. (The shortest possible bus cycle is 2 BCLK periods). When not using the WAIT function, this pin can be used as P71 by clearing the P7 Operation Mode Register P71MOD bit to "0". Figure 15.3.4 Internal Bus Access during Bus Free State "H"WR# Bus-free state Internal bus access "H" BCLK A12–A30 CS0#, CS1# BHE#, BLE# DB0–DB15 WAIT# RD# "H" Hi-Z (Don't Care) Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Notes: Hi-Z denotes a high-impedance state. BCLK is not output. Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated)

15-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 15.3.5 Read/Write Timing (for Shortest External Access) Read Read (2 cycles) BCLK A12–A30 CS0#, CS1# WR# DB0–DB15 WAIT# RD# "H" "H" Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Notes: Circles in the above diagram denote the sampling timing. BCLK is not output. (Don't Care) BHE#, BLE# Internal 1 wait state Write Write (2 cycles) BCLK A12–A30 CS0#, CS1# WR# DB0–DB15 WAIT# RD# "H" (Don't Care) (Don't Care) BHE#, BLE# Internal 1 wait state Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) (Don't Care) "H"

15-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 15.3.6 Read/Write Timing (for Access with Internal 2 and External 1 Wait States) Read Write Read (4 cycles) BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Notes: Circles in the above diagram denote the sampling timing. BCLK is not output. "H" Internal 2 wait states External 1 wait state WR# "L" (Don't Care) Write (4 cycles) BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" "H" WR# "L" (Don't Care) (Don't Care) (Don't Care) Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) Internal 2 wait states External 1 wait state

15-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (1) When the Bus Mode Control Register is set to "0" When the input signal on the HREQ# pin is pulled "L" and the hold request is accepted, the microcomputer goes to a hold state and outputs a "L" from the HACK# pin. During hold state, all bus related pins are placed in the high-impedance state, allowing data to be transferred on the system bus. To exit the hold state and return to normal operating state, release the HREQ# signal back "H." Figure 15.4.1 Bus Arbitration Timing DB0–DB15 BCLK Bus cycle Idle Go to hold state Hold state Return Next bus cycle Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Notes: Circles in the above diagram denote the sampling timing. Hi-Z denotes a high-impedance state. Idle cycles are inserted only when a hold state is entered immediately following an external read access. The number of cycles before a state transition to idle (recovery) of hold state occurs after input to the HREQ# pin is pulled "L" differs depending on the status of the bus access being executed then. HREQ# HACK# A12–A30 CS0#, CS1# RD# BHW#, BLW# WAIT# Hi-Z (Don't Care) Hi-Z Hi-Z Hi-Z Hi-Z Bus Mode Control Register (Note 1) BUSMOD bit = 0 (byte enable separated)

15-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) When the Bus Mode Control Register is set to "1" When the input signal on the HREQ# pin is pulled "L" and the hold request is accepted, the microcomputer goes to a hold state and outputs a "L" from the HACK# pin. During hold state, all bus related pins are placed in the high-impedance state, allowing data to be transferred on the system bus. To exit the hold state and return to normal operating state, release the HREQ# signal back "H." Figure 15.4.2 Bus Arbitration Timing DB0–DB15 BCLK Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Notes: Circles in the above diagram denote the sampling timing. Hi-Z denotes a high-impedance state. Idle cycles are inserted only when a hold state is entered immediately following an external read access. The number of cycles before a state transition to idle (recovery) of hold state occurs after input to the HREQ# pin is pulled "L" differs depending on the status of the bus access being executed then. HREQ# HACK# A12–A30 CS0#, CS1# RD# BHW#, BLW# WAIT# Hi-Z (Don't Care) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z WR# Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) Bus cycle Idle Go to hold state Hold state Return Next bus cycle

15-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

15.5 Typical Connection of External Extension Memory

(1) When the Bus Mode Control Register is set to "0" A typical memory connection when using external extension memory is shown in Figure 15.5.1. (External extension memory can only be used in external extension mode and processor mode.) Figure 15.5.1 Typical Connection of External Extension Memory (when BUSMOD bit = "0") Note: The address and data are connected in such a way that pin 0 is the MSB and pin 15 is the LSB. When connecting external extension memory, connections of the MSB and LSB sides must be reversed. Memory mapping Internal flash memory (384KB) Number of bus wait states can be set to 1-4. Normally used as port. WAIT is used only when four or more wait states are needed. H'0000 0000 H'001F FFFF H'0040 0000 H'0020 0000 H'0006 0000 Not used H'0010 0000 (1MB) 2M-CS1 area SRAM Flash memory A18 D15 RD# CS# max1MB A17 D15 RD#(D0-D15) CS# WR#(D0-D7) WR#(D8-D15) max512KB*2 (total1MB) M32176F3 A12 A30 D15 RD# CS0# CS1# BLW# BHW# WAIT# H'000F FFFF Ghost area H'0030 0000 External memory area (1MB) 1M-CS0 area External memory area

15-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) When the Bus Mode Control Register is set to "1" A typical memory connection when using external extension memory is shown in Figure 15.5.2. (External extension memory can only be used in external extension mode and processor mode.) Figure 15.5.2 Typical Connection of External Extension Memory (when BUSMOD bit = "1") Note: The address and data are connected in such a way that pin 0 is the MSB and pin 15 is the LSB. When connecting external extension memory, connections of the MSB and LSB sides must be reversed. SRAM M32176F3 A12 A30 D15 RD# CS0# CS1# BLE# BHE# Number of bus wait states can be set to 1-4. WAIT# Normally used as port. WAIT is used only when four or more wait states are needed. Flash memory A18 D15 RD# CS# max1MB A18 D15 RD#(D0-D15) CS# BHE#(D0-D7) BLE#(D8-D15) max1MB WR# WR#(D0-D15) Memory mapping Internal flash memory (384KB) H'0000 0000 H'001F FFFF H'0040 0000 H'0020 0000 H'0006 0000 Not used H'0010 0000 External memory area (1MB) 2M-CS1 area H'000F FFFF Ghost area H'0030 0000 External memory area (1MB) 1M-CS0 area

15-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (3) When the Bus Mode Control Register is set to "1" using a combination of 8/16-bit data bus memories The diagram below shows a typical connection of external extension memory, with an 8-bit data bus memory located in the CS0 area, and a 16-bit data bus memory located in the CS1 area. (External exten- sion memory can only be used in external extension mode and processor mode.) (384KB) External memory area (1MB) When CL = 50 pF, memory can be connected with only 2 ns of data delay. Normally used as port. WAIT is used only when four or more wait states are needed. H'0000 0000 H'0040 0000 H'0020 0000 H'0006 0000 Not used H'0010 0000 1M-CS0 area 2M-CS1 area SRAM 8-bit memory A18 RD# CS# max1MB A18 D15 BHE# CS# WR#(D0-D15) RD#(D0-D15) max1MB M32176F3 A12 A30 D15 RD# CS0# CS1# BHE# WR# WAIT# QS32X2245 A B OE BLE#BLE# A0 8-bit bus area Note: The QS32X2245 is a product made by the IDT Company. A B Number of bus wait states can be set to 1-4. H'000F FFFF External memory area (1MB) 16-bit bus area H'0030 0000 Ghost area WR# Figure 15.5.3 Typical Connection of External Extension Memory (when BUSMOD bit = "1" using a combina- tion of 8/16-Bit Memories) Note: The address and data are connected in such a way that pin 0 is the MSB and pin 15 is the LSB. When connecting external extension memory, connections of the MSB and LSB sides must be reversed.

16.1 Outline of the Wait Controller

16.2 Wait Controller Related Register

16.3 Typical Operation of the Wait Controller

16-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The Wait Controller controls the number of wait states inserted in bus cycles when accessing an external exten- sion area. The Wait Controller is outlined in the table below. Table 16.1.1 Outline of the Wait Controller Item Description Target space Control is applied to the following address spaces depending on operation mode: Single-chip mode: No target space (Settings of the Wait Controller have no effect) External extension mode: CS0 area (1 Mbyte), CS1 area (1 Mbyte), Processor mode: CS0 area (1 Mbyte), CS1 area (1 Mbyte) Number of wait states 1–4 wait states set by software + any number of wait states set from the WAIT# pin that can be inserted (The shortest possible bus cycle during external access is equal to one wait cycle inserted.) During external extension and processor modes, two chip select signals (CS0#, CS1#) are output, each corre- sponding to one of the two external extension areas referred to as CS0 and CS1. H'0000 0000 H'003F FFFF <Processor mode> CS1 area (1MB) CS0 area (1MB) CS1 area (1MB) <External extension mode> Internal ROM area (Note 1) H'001F FFFF H'0020 0000 CS0 area (1MB) H'000F FFFF H'0010 0000 Reserved area H'002F FFFF H'0030 0000 External e xtension area External e xtension area Ghost of (1MB) Note 1: Non-CS0 area Note: • Ghost area should not be used intentionally during programming. CS0 area Ghost of (1MB) CS0 area Ghost of (1MB) CS0 area Figure 16.1.1 CS0 and CS1 Area Address Map When accessing the external extension area, the Wait Controller controls the number of wait states inserted in bus cycles based on the number of wait states set by software and those entered from the WAIT# pin. The number of wait states that can be controlled in software is 1 to 4. (The shortest possible bus cycle during external access is equal to one wait cycle inserted.) When the input signal on the WAIT# pin is sampled "L" in the last cycle of internal wait state, the wait state is extended as long as the WAIT# input signal is held "L." Then when the WAIT# input signal is released back "H", the wait state is terminated and the next new bus cycle is entered into.

16-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Table 16.1.2 Number of Wait States that Can Be Set by the Wait Controller External Extension Area Address Number of Wait States Inserted CS0 area H’0010 0000 to H’001F FFFF 1 to 4 wait states set by software (external extension mode) + any number of wait states entered from the WAIT# pin H’0000 0000 to H’001F FFFF (However, software settings have priority.) (processor mode) (Note 1) CS1 area H’0020 0000 to H’002F FFFF 1 to 4 wait states set by software (external extension and + any number of wait states entered from the WAIT# pin processor modes) (Note 2) (However, software settings have priority.) Note 1: During processor mode, a ghost of the CS0 area (1 Mbytes) will appear in the H’0010 0000–H’001F FFFF area. Note 2: A ghost of the CS1 area (1 Mbytes) will appear in the H’0030 0000–H’003F FFFF area.

16-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 A Wait Controller related register map is shown below. Wait Controller Related Register Map Address +0 address +1 address See b0 b7 b8 b15 page H'0080 0180 Wait Cycles Control Register (Use inhibited area) 16-4 (WTCCR)

16.2.1 Wait Cycles Control Register

Wait Cycles Control Register (WTCCR) <Address: H’0080 0180> 123456 b 7b0 CS0WTC CS1WTC 00 000 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 0, 1 No function assigned. Fix to "0". 00 2, 3 CS0WTC 00: 4 wait states (Upon exiting reset) R W CS0 wait cycles select bit 01: 3 wait states 10: 2 wait states 11: 1 wait state 4, 5 No function assigned. Fix to "0". 00 6, 7 CS1WTC 00: 4 wait states (Upon exiting reset) R W CS1 wait cycles select bit 01: 3 wait states 10: 2 wait states 11: 1 wait state

16-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.1 Internal Bus Access during Bus Free State The following shows a typical operation of the Wait Controller. The Wait Controller can control bus access in 2 to 5 cycles. If more access cycles than that are needed, use the WAIT function in combination with the Wait Controller. (1) When the Bus Mode Control Register is set to 0 External read/write operations are performed using the address bus, data bus and the signals CS0#, CS1#, RD#, BHW#, BLW#, WAIT# and BCLK. "H" BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" Hi-Z (Don't Care) Bus free state Internal bus access Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note: Hi-Z denotes a high-impedance state. Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated)

16-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.2 Read/Write Timing (for Access with Internal 1 Wait State) Read BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" (Don't Care)(Don't Care) Write BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" (Don't Care)(Don't Care) Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) Wait Cycles Control Register (Note 2) CSnWTC bit = 11 (1 wait) "H" "H" Read (2 cycles) Internal 1 wait state Write (2 cycles) Internal 1 wait state Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note 2: For details about the Wait Cycles Control Register, see Section 16.2.1, "Wait Cycles Control Register." Note: Circles in the above diagram indicate the sampling timing.

16-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.3 Read/Write Timing (for Access with Internal 2 Wait States) BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" (Don't Care) "H" (Don't Care) BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" (Don't Care) "H" (Don't Care) Read Write Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) Wait Cycles Control Register (Note 2) CSnWTC bit = 10 (2 waits) Read (3 cycles) Internal 2 wait states Write (3 cycles) Internal 2 wait states Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note 2: For details about the Wait Cycles Control Register, see Section 16.2.1, "Wait Cycles Control Register." Note: Circles in the above diagram indicate the sampling timing.

16-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.4 Read/Write Timing (for Access with Internal 3 Wait States) BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" (Don't Care) "H" (Don't Care) BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" (Don't Care) "H" (Don't Care) Read Write Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) Wait Cycles Control Register (Note 2) CSnWTC bit = 01 (3 waits) Read (4 cycles) Internal 3 wait states Write (4 cycles) Internal 3 wait states Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note 2: For details about the Wait Cycles Control Register, see Section 16.2.1, "Wait Cycles Control Register." Note: Circles in the above diagram indicate the sampling timing.

16-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.5 Read/Write Timing (for Access with Internal 4 Wait States) Read BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" (Don't Care) "H" (Don't Care) Write BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" (Don't Care) "H" (Don't Care) Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) Wait Cycles Control Register (Note 2) CSnWTC bit = 00 (4 waits) Read (5 cycles) Internal 4 wait states Write (5 cycles) Internal 4 wait states Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note 2: For details about the Wait Cycles Control Register, see Section 16.2.1, "Wait Cycles Control Register." Note: Circles in the above diagram indicate the sampling timing.

16-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.6 Read/Write Timing (for Access with Internal 4 and External 1 Wait States) Read BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" "L" (Don't Care) "H" (Don't Care) Write BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" "L" (Don't Care) "H" (Don't Care) Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) Wait Cycles Control Register (Note 2) CSnWTC bit = 00 (4 waits) Read (6 cycles) Internal 4 wait states Write (6 cycles) Internal 4 wait states Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note 2: For details about the Wait Cycles Control Register, see Section 16.2.1, "Wait Cycles Control Register." Note: Circles in the above diagram indicate the sampling timing. External 1 wait state External 1 wait state

16-1132176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.7 Read/Write Timing (for Access with Internal 2 and External n Wait States) Read BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" "L" (Don't Care) "H" (Don't Care) Write BCLK A12–A30 CS0#, CS1# BHW#, BLW# DB0–DB15 WAIT# RD# "H" "L" (Don't Care) "H" (Don't Care) "L""L" "L""L" Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) Wait Cycles Control Register (Note 2) CSnWTC bit = 10 (2 waits) Read (3+n cycles) Internal 2 wait states Write (3+n cycles) Internal 2 wait states Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note 2: For details about the Wait Cycles Control Register, see Section 16.2.1, "Wait Cycles Control Register." Note: Circles in the above diagram indicate the sampling timing. External n wait states External n wait states

16-1232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (2) When the Bus Mode Control Register is set to 1 External read/write operations are performed using the address bus, data bus and the signals CS0#, CS1#, RD#, BHE#, BLE#, WAIT# and WR#. Figure 16.3.8 Internal Bus Access during Bus Free State "H"WR# Bus free state Internal bus access "H" BCLK A12–A30 CS0#, CS1# BHE#, BLE# DB0–DB15 WAIT# RD# "H" Hi-Z (Don't Care) Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Notes: Hi-Z denotes a high-impedance state. BCLK is not output. Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated)

16-1332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.9 Read/Write Timing (for Access with Internal 1 Wait State) Read BCLK A12–A30 CS0#, CS1# WR# DB0–DB15 WAIT# RD# "H" "H" (Don't Care) BHE#, BLE# Write BCLK A12–A30 CS0#, CS1# WR# DB0–DB15 WAIT# RD# "H" (Don't Care) (Don't Care) BHE#, BLE# Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) Wait Cycles Control Register (Note 2) CSnWTC bit = 11 (1 wait) (Don't Care) "H" Read (2 cycles) Internal 1 wait state Write (2 cycles) Internal 1 wait state Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note 2: For details about the Wait Cycles Control Register, see Section 16.2.1, "Wait Cycles Control Register." Notes: Circles in the above diagram indicate the sampling timing. BCLK is not output.

16-1432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.10 Read/Write Timing (for Access with Internal 2 Wait States) Read BCLK A12–A30 CS0#, CS1# WR# DB0–DB15 WAIT# RD# "H" (Don't Care) BHE#, BLE# (Don't Care) "H" Write BCLK A12–A30 CS0#, CS1# WR# DB0–DB15 WAIT# RD# "H" (Don't Care) BHE#, BLE# (Don't Care) "H" Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) Wait Cycles Control Register (Note 2) CSnWTC bit = 10 (2 waits) Read (3 cycles) Internal 2 wait states Write (3 cycles) Internal 2 wait states Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note 2: For details about the Wait Cycles Control Register, see Section 16.2.1, "Wait Cycles Control Register." Notes: Circles in the above diagram indicate the sampling timing. BCLK is not output.

16-1532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.11 Read/Write Timing (for Access with Internal 3 Wait States) Read BCLK A12–A30 CS0#, CS1# WR# DB0–DB15 WAIT# RD# "H" Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note 2: For details about the Wait Cycles Control Register, see Section 16.2.1, "Wait Cycles Control Register." Notes: Circles in the above diagram indicate the sampling timing. BCLK is not output. (Don't Care) BHE#, BLE# (Don't Care) "H" Write BCLK A12–A30 CS0#, CS1# WR# DB0–DB15 WAIT# RD# "H" (Don't Care) BHE#, BLE# (Don't Care) "H" Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) Wait Cycles Control Register (Note 2) CSnWTC bit = 01 (3 waits) Read (4 cycles) Internal 3 wait states Write (4 cycles) Internal 3 wait states

16-1632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.12 Read/Write Timing (for Access with Internal 4 Wait States) Read BCLK A12–A30 CS0#, CS1# WR# DB0–DB15 WAIT# RD# "H" Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note 2: For details about the Wait Cycles Control Register, see Section 16.2.1, "Wait Cycles Control Register." Notes: Circles in the above diagram indicate the sampling timing. BCLK is not output. (Don't Care) BHE#, BLE# (Don't Care) "H" Write Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) Wait Cycles Control Register (Note 2) CSnWTC bit = 00 (4 waits) BCLK A12–A30 CS0#, CS1# WR# DB0–DB15 WAIT# RD# "H" (Don't Care) BHE#, BLE# (Don't Care) "H" Read (5 cycles) Internal 4 wait states Write (5 cycles) Internal 4 wait states

16-1732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.13 Read/Write Timing (for Access with Internal 4 and External 1 Wait States) Read BCLK A13–A30 CS0#, CS1# BHE#, BLE# DB0–DB15 WAIT# RD# "H" Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note 2: For details about the Wait Cycles Control Register, see Section 16.2.1, "Wait Cycles Control Register." Notes: Circles in the above diagram indicate the sampling timing. BCLK is not output. "L" (Don't Care) "H" (Don't Care) Write BCLK A12–A30 CS0#, CS1# BHE#, BLE# DB0–DB15 WAIT# RD# "H" "L" (Don't Care) "H" (Don't Care) WR# WR# Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) Wait Cycles Control Register (Note 2) CSnWTC bit = 00 (4 waits) Read (6 cycles) Internal 4 wait states Write (6 cycles) Internal 4 wait states External 1 wait state External 1 wait state

16-1832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 16.3.14 Read/Write Timing (for Access with Internal 2 and External n Wait States) Read BCLK A12–A30 CS0#, CS1# BHE#, BLE# DB0–DB15 WAIT# RD# "H" Note 1: For details about the Bus Mode Control Register, see Section 15.2.2, "Bus Mode Control Register." Note 2: For details about the Wait Cycles Control Register, see Section 16.2.1, "Wait Cycles Control Register." Notes: Circles in the above diagram indicate the sampling timing. BCLK is not output. "L" (Don't Care) "H" (Don't Care) Write BCLK A12–A30 CS0#, CS1# BHE#, BLE# DB0–DB15 WAIT# RD# "H" "L" (Don't Care) "H" (Don't Care) "L""L" "L""L" WR# WR# Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) Wait Cycles Control Register (Note 2) CSnWTC bit = 10 (2 waits) Read (3+n cycles) Internal 2 wait states Write (3+n cycles) Internal 2 wait states External n wait states External n wait states

17.1 Outline of RAM Backup Mode

17.2 Example of RAM Backup when Power is Off

17.3 Example of RAM Backup for Saving Power

17.4 Exiting RAM Backup Mode (Wakeup)

17-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 In RAM backup mode, the contents of the internal RAM are retained while the power is turned off. RAM backup mode is used for the following two purposes. RAM backup area for 32176 is from H'0080 4000 to H'0080 9FFF (24KB).

Back up the internal RAM data when the power is forcibly turned off from the outside (RAM backup when the power is off) For the M32R/ECU to turn off the power to the CPU at any time as needed to reduce the system’s power consumption while retaining the internal RAM data (RAM backup for saving the power consumption) The M32R/ECU is placed in RAM backup mode by applying a voltage of 3.0–5.5 V to the VDDE pin (provided for RAM backup) and 0 V to all other pins. During RAM backup mode, the contents of the internal RAM are retained, while the CPU and internal peripheral I/O remain idle. Because all pins except VDDE are held "L" during RAM backup mode, the power consumption in the system can effectively be reduced. Figure 17.2.1 Typical Circuit for RAM Backup at Power Outage VREFn SBI# ADnINi M32R/ECU (Note 2) C Backup battery VCC VDD VBB VREF Reference voltage for power outage detection Power outage detection signal Backup power supply for power outage Output Power supply monitor IC Note 1: Power outage is detected by the DC IN (regulator input) voltage. Note 2: These pins are used to detect a RAM backup signal. Note 3: This pin outputs a "H" when the power is on and outputs a "L" when the power is off. DC IN Input Regulator (5V or 3.3V) VDDE AVCCn OUT VCCE EXCVCC EXCOSC-VCC EXCVDD VCCE(Note 3) (Note 1) H'0080 4000 H'0080 9FFF

32176 Internal RAM (24KB)

RAM backup area (24KB) Figure 17.1.1 RAM Backup Area A typical circuit for RAM backup at power outage is shown in Figure 17.2.1. The following explains how the RAM can be backed up by using this circuit as an example.

17-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

17.2.1 Normal Operating State

Figure 17.2.2 shows the normal operating state of the M32R/ECU. During normal operation, input on the SBI# pin or ADnINi (i = 0–15) pin which is used to detect a RAM backup signal remains "H." Figure 17.2.2 Normal Operating State Backup power supply for power outage Reference voltage for power outage detection Power outage detection signal "H" 3.3V or 5V VREFn SBI# ADnINi M32R/ECU C VCC VDD VBB VREF DC IN (5V or 3.3V) VDDE AVCCn OUT VCCE EXCVCC EXCOSC-VCC EXCVDD VCCE 3.3V or 5V (Note 2) Note 1: Power outage is detected by the DC IN (regulator input) voltage. Note 2: These pins are used to detect a RAM backup signal. Note 3: This pin outputs a "H" when the power is on and outputs a "L" when the power is down. Regulator (Note 3) Input Output (Note 1) Backup battery Power supply monitor IC

17.2 Example of RAM Backup when Power is Down

17-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (a) (b) (c) "L" VREFn SBI# ADnINi M32R/ECU C VCC VDD VBB VREF DC IN (5V or 3.3V) VDDE AVCCn OUT VCCE EXCVCC EXCOSC-VCC EXCVDD VCCE (Note 2) Backup battery Reference voltage for power outage detection Power outage detection signal Backup power supply for power outage Power supply monitor IC Note 1: Power outage is detected by the DC IN (regulator input) voltage. Note 2: These pins are used to detect a RAM backup signal. Note 3: This pin outputs a "H" when the power is on and outputs a "L" when the power is off Note 4: Determined by the input level on SBI# pin or ADnINi pin. Note 5: The time needed for processing in (b) is secured by adjusting the capacitance. Input OutputRegulator (Note 3) (Note 1) (Note 5) 3.0–5.5V Example of RAM backup processing Power goes off (Note 4) Create data for backup RAM check RAM backup mode

17.2.2 RAM Backup State

Figure 17.2.3 shows the power outage RAM backup state of the M32R/ECU. When the power supply goes off, the power supply monitor IC starts feeding current from the backup battery to the M32R/ECU. Also, the power supply monitor IC’s power outage detection pin outputs a "L", causing the SBI# pin or ADnINi pin to go "L", which generates a RAM backup signal ((a) in Figure 17.2.3). Determination of whether the power is off must be made with respect to the DC IN (regulator input) voltage in order to allow for a software processing time at power outage. To enable RAM backup mode, make the following setting: (1) Create data for RAM check to verify whether the RAM data has been retained normally after returning from RAM backup mode to normal mode ((b) in Figure 17.2.3). If the power supply to VCCE goes off after making above setting, the VDDE pin voltage goes to 3.0–3.3 V and all other pin voltages drop to 0 V, and the M32R/ECU is thereby placed in RAM backup mode ((c) in Figure 17.2.3). Figure 17.2.3 Power Outage RAM Backup State

17-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Port n IB DC IN Output Output VREFn SBI# ADnINi M32R/ECU VDDEAVCCnVCCE EXCVCC EXCOSC-VCC EXCVDD VCCE (5V or 3.3V) (5V or 3.3V) RAM backup signal External circuit (Note 1) (Note 3) RAM backup power supply Regulator Input Regulator (Note 2) Note 1: This circuit outputs a "L" during RAM backup. Note 2: This port outputs a "H" when the power is on, and is set for input mode when in RAM backup mode. Note 3: These pins are used to detect a RAM backup signal. Figure 17.3.1 Typical RAM Backup Circuit for Saving Power Consumption

17.3 Example of RAM Backup for Saving Power Consumption

A typical RAM backup circuit for saving the microcomputer’s power consumption is shown in Figure 17.3.1. The following explains how the RAM is backed up for the purpose of low-power operation by using this circuit as an example.

17-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

17.3.1 Normal Operating State

Figure 17.3.2 shows the normal operating state of the M32R/ECU. During normal operation, the RAM backup signal output by the external circuit is "H." Also, input on the SBI# pin or ADnINi (i = 0–15) pin which is used to detect a RAM backup signal remains "H." Port n, which connects to the transistor’s base, should output a "H." This causes the transistor’s base voltage, IB, to go "H" so that current is fed from the power supply to the VCCE pin via the transistor. Figure 17.3.2 Normal Operating State "H" "H" "H" IB DC IN VREFn SBI# ADnINi M32R/ECU VDDEAVCCnVCCE EXCVCC EXCOSC-VCC EXCVDD VCCE 3.3V or 5V (5V or 3.3V) (5V or 3.3V) 3.3V or 5V RAM backup signal (Note 1) External circuit Port n (Note 3) RAM backup power supply Regulator Input Output Regulator (Note 2) Output Note 1: This circuit outputs a "L" during RAM backup. Note 2: This port outputs a "H" when the power is on, and is set for input mode when in RAM backup mode (one of the port pins selected). Note 3: These pins are used to detect a RAM backup signal.

17-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

17.3.2 RAM Backup State

When the external circuit outputs a "L", input on the SBI# or ADnINi pin is pulled "L." A "L" on these input pins generates a RAM backup signal (A and (a) in Figure 17.3.3). To enable RAM backup mode, make the following settings: (1) Create data for RAM check to verify after returning from RAM backup mode to normal mode whether the RAM data has been retained normally ((b) in Figure 17.3.3). (2) To materialize low-power operation, set all programmable input/output pins except port n for input mode (or for output mode, with the output level fixed "L") ((c) in Figure 17.3.3). (3) Set port n for input mode (B and (d) in Figure 17.3.3). This causes the transistor’s base voltage, IB, to go "L", so that the power to all power supply pins except VDDE is shut off (C and D in Figure 17.3.3). By settings in (1) to (3), the VDDE pin voltage goes to 3.0–5.5 V and all other pin voltages drop to 0 V, and the M32R/ECU is thereby placed in RAM backup mode ((d) in Figure 17.3.3). Figure 17.3.3 RAM Backup State for Low Power Operation "L" B C (a) (b) (c) (d) "L" "L" "L" "L" IB A D DC IN VREFn SBI# ADnINi M32R/ECU VDDEAVCCnVCCE EXCVCC EXCOSC-VCC EXCVDD VCCE 3.3V or 5V (5V or 3.3V) (5V or 3.3V) Example of RAM backup processing RAM backup signal External circuit Port n (Note 1) (Note 3) RAM power supply Regulator Input Output Regulator (Note 2) Output Note 1: This circuit outputs a "L" during RAM backup. Note 2: This port outputs a "H" when the power is on, and is set for input mode when in RAM backup mode (one of the port pins selected). Note 3: These pins are used to detect a RAM backup signal. Note 4: Determined by the input level on SBI# pin or ADnINi pin. Note 5: Base voltage IB = 0 causes the power to all power supply pins except VDDE to stop. See A to D in the above explanation. Generate a RAM backup signal (Note 4) Create data for backup RAM check Set the pin connecting to the transistor's base (port n) for input mode (Note 5) RAM backup mode

17-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 RESET# SBI# ADnINi VDDE f(XIN) VCCE, VREFn , AVCCn 0V Oscillation stabilization time External input signal goes "L" RAM backup period Power on Port output setting ("H" level) External input signal goes "H" Port n Port input mode 5.0V or 3.3V Port output setting ("H" level) Oscillation stabilization time Figure 17.3.4 Example of a RAM Backup Sequence for Low Power Operation

17.3.3 Precautions to Be Observed at Power-On

When changing port n from input mode to output mode after power-on, pay attention to the following. If port n is set for output mode while no data is set in the Port n Data Register, the port’s initial output level is instable. Therefore, before changing port n for output mode, make sure the Port n Data Register is set to output a "H." Unless this precaution is followed, port output may go "L" at the same time the port is set for output after the oscillation has stabilized, causing the microcomputer to enter RAM backup mode.

17-932176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The processing to place the M32R/ECU out of RAM backup mode and return it to normal operation mode is referred to as “wakeup” processing. Figure 17.4.1 shows an example of wakeup processing. Wakeup processing is initiated by applying a reset. The following shows how to execute wakeup processing. (1) Reset the microcomputer ((a) in Figure 17.4.1). (2) Set port n for output mode and output a "H" from the port ((b) in Figure 17.4.1) (Note 1) (3) Compare the RAM content against the RAM check data created before entering RAM backup mode ((c) in Figure 17.4.1). (4) If the comparison in (3) did not match, initialize the RAM ((d) in Figure 17.4.1). If the comparison in (3) matched, use the retained data in the program. Note 1: For wakeup from power outage RAM backup mode, port n settings are unnecessary. Figure 17.4.1 Wakeup Processing OK Error Compare RAM content against backup RAM check data Initialize the RAM Example of wakeup processing Reset Set the transistor's base connecting pin (port n) for "H" level output mode (Note 1) Initialize each circuit To the main routine (a) (b) (c) (d) (e) (f) Note 1: For wakeup from power outage RAM backup mode, port n settings are unnecessary.

17-1032176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 This page is blank for reasons of layout.

18.1 Oscillator Circuit

18.2 Clock Generator Circuit

18-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The 32176 contains an oscillator circuit that supplies operating clocks for the CPU core, internal peripheral I/O and internal memory. The frequency supplied to the clock input pin (XIN) is multiplied by 4 by an internal PLL circuit to produce the CPU clock, which is the operating clock for the CPU core and internal memory. The fre- quency of this clock is divided by 2 in the subsequent circuit to produce the peripheral clock, which is the operat- ing clock for the internal peripheral I/O and external data bus.

18.1.1 Example of an Oscillator Circuit

An oscillator circuit can be configured by connecting a ceramic (or crystal) resonator between the XIN and XOUT pins external to the chip. Figure 18.1.1 shows an example of a system clock generating circuit illustrating a resonator connected external to the chip. For the constants Rf, Cin, Cout and Rd, the resonator manufacturer should be consulted to determine the appropriate values. To use an externally sourced clock signal without using an internal oscillator circuit, connect the external clock signal to the XIN pin and leave the XOUT pin open. Figure 18.1.1 Example of an Oscillator Circuit M32R/ECU EXCOSC-VCC XIN XOUTOSC-VSS Rf Rd CIN COUT BCLK/P70 C Oscillator circuit To the peripheral clock PLL circuit Oscillator module To the CPU clock Oscillation stoppage detection circuit

18-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

18.1.2 XIN Oscillation Stoppage Detection Function

The 32176 contains a detection circuit to find whether oscillation input to the PLL circuit has stopped. The PLL circuit oscillates with the frequency of its specific vibration in the absence of the reference oscillation input. The XIN oscillation input is sampled at the peripheral clock and when the XIN oscillation is found to be at the same level, the XSTAT bit is set. Because the CPU continues operating with the PLL circuit’s natural frequency even when the XIN oscillation has stopped, error handling for the stoppage of XIN oscillation can be accom- plished by inspecting XSTAT in software. Figure 18.1.2 Block Diagram of the XIN Oscillation Stoppage Detection Circuit Port Input Special Function Control Register (PICNT) <Address: H’0080 0745> 9 1 01 11 21 31 4 b 1 5b8 PIEN0PISELXSTAT 0 000 0 0 0 0 <Upon exiting reset: H’00> b Bit Name Function R W 8–10 No function assigned. Fix to "0". 0 0

11 XSTAT 0: XIN oscillating R (Note1)

XIN oscillation status bit 1: XIN inactive 12–13 No function assigned. Fix to "0". 0 0 Port input data select bit 1: Port pin level Port input enable bit 1: Enable input Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. For details about the function of the port input data select bit (PISEL) and port input enable bit (PIEN0), see Section 8.3.5, “Port Input Special Function Control Register.” Oscillator circuit PLL circuit Counter XIN XSTAT flag XIN oscillation stoppage detection circuit CLOCK RESET Edge detection XOUT

18-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 (1) XSTAT (XIN oscillation status) bit (Bit 11) 1) Conditions under which XSTAT is set to "1" XSTAT is set to "1" upon detecting that XIN oscillation has stopped. When XIN remains at the same level for a predetermined time (3 BCLK periods up to 4 BCLK periods), XIN oscillation is assumed to have stopped. When operating normally, XIN changes state (high or low) once every BCLK period. 2) Conditions under which XSTAT is cleared to "0" XSTAT is cleared to "0" by a system reset or by writing "0". If XSTAT is cleared at the same time it is set to "1" in 1) above, the former has priority so that XSTAT is cleared. Writing "1" to XSTAT is ignored. 3) Method for detecting XIN oscillation stoppage by using XSTAT Because the M32R/ECU internally contains a PLL, the internal clock remains active even when XIN oscilla- tion has stopped. By reading XSTAT without clearing it after exiting the reset state, it is possible to know whether XIN has stopped since the reset signal was deasserted. Similarly, by reading XSTAT after clearing it by writing 0, it is possible to know the current oscillating status of XIN. (However, there must be an interval of at least 10 BCLK periods (20 CPU clock periods) between read and write.) To carry out this function when XSTAT bit is set to 1, make sure to reconfirm after clearing XSTAT bit once, and pay extra attention before use. Figure 18.1.3 Procedure for Setting XSTAT Read XSTAT (1) To know whether XIN oscillation has stopped after being reset Write XSTAT = 0 (2) To know the current status of XIN oscillation Wait for 20 CPU clock periods or more Read XSTAT Wait before inspecting XSTAT Note: • To carry out this function when XSTAT bit is set to 1, make sure to reconfirm after clearing XSTAT bit once, and pay extra attention before use.

18-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

18.1.3 Oscillation Drive Capability Select Function

The microcomputer incorporates a four-stage oscillation drive capability select function. Once the oscillation of the oscillator circuit has stabilized, the XIN-XOUT drive capability can be lowered. The lower the drive capability, the smaller the amount of power consumption. Clock Control Register (CLKCR) <Address: H’0080 0786> 123456 b 7b0 XDRVP XDRV 0110 0 0 0 0 <Upon exiting reset: H’03> b Bit Name Function R W 0–4 No function assigned. Fix to "0". 00

5 XDRVP 0W

6–7 XDRV XIN-XOUT drive capability (performance ratio) R W XIN-XOUT drive capability select bit 00: Low 0.25 01: 0.50 10: 0.75 11: High 1.00 (1) XDRV write control bit (XDRVP) (Bit 5) This bit controls writing to the XIN-XOUT drive capability select bits. (2) XIN-XOUT drive capability select bits (Bits 6, 7) The following shows the procedure for writing to these bits. 1. Set the write control bit (XDRVP) to "1". 2. Immediately following the above, reset the write control bit (XDRVP) to "0" and write the appropriate value to the XIN-XOUT drive capability select bits. Note: If a write cycle to any other area occurs between 1 and 2, write to XDRV has no effect and the written value is not reflected. Therefore, disable interrupts and DMA transfers before setting the drive capability control bits. Note that a pair of two consecutive writes comprise a write operation.

18-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 If a write cycle to other area exists in this interval, settings of XDRV bits are not reflected. (Note 1) XDRVP "1" XDRVP "0" XDRV Set value Example of correct setting Settings that do not have effect Because a write cycle to other area exists, the set value is not reflected. (Note 1) XDRVP "1" Write to other area XDRVP "0" XDRV Set value (1) (2) Because these two consecutive writes comprise a pair, the next set value is not reflected. XDRVP "1" XDRVP "1" XDRVP "0" XDRV Set value Note 1: The writing cycle to the other area is the writing cycle from CPU, DMA, and SDI (tool) to any other area. There is no effect on the writing cycle from RTD. Figure 18.1.4 Procedure for Setting the Oscillation Drive Capability

18-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

18.1.4 System Clock Output Function

A clock whose frequency is twice that of the input clock (i.e., the peripheral clock) can be output from the BCLK pin. The BCLK pin is shared with port P70. To use this pin to output the peripheral clock, set the P7 Operation Mode Register (P7MOD) bit 8 to "1". Configuration of the P7 Operation Mode Register is shown below. P7 Operation Mode Register (P7MOD) <Address: H’0080 0747> <Upon exiting reset: H’00> b Bit Name Function R W

8 P70MD 0:P70 R W

Port P70 operation mode bit 1:BCLK

9 P71MD 0:P71 R W

Port P71 operation mode bit 1:WAIT#

10 P72MD 0:P72 R W

Port P72 operation mode bit 1:HREQ#

11 P73MD 0:P73 R W

Port P73 operation mode bit 1:HACK#

12 P74MD 0:P74 R W

Port P74 operation mode bit 1:RTDTXD

13 P75MD 0:P75 R W

Port P75 operation mode bit 1:RTDRXD

14 P76MD 0:P76 R W

Port P76 operation mode bit 1:RTDACK

15 P77MD 0:P77 R W

Port P77 operation mode bit 1:RTDCLK

18.1.5 Oscillation Stabilization Time at Power-On

The oscillator circuit comprised of a ceramic (or crystal) resonator requires a finite time before its oscillation stabilizes after being powered on. Therefore, there must be a certain amount of oscillation stabilization time that suits the oscillator circuit used. Figure 18.1.5 shows an oscillation stabilization time required at power-on. P70MD P71MD P72MD P73MD P74MD P75MD P76MD P77MD 00000000 Figure 18.1.5 Oscillation Stabilization Time at Power-On RESET# XIN Oscillation stabilization time Main power supply

18-832176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Supply independent clocks to the CPU and the internal peripheral circuit. XIN pin (8MHz–10MHz) BCLK(peripheral clock) (16MHz–20MHz) CPUCLK(CPU clock) (32MHz–40MHz) PLL Figure 18.2.1 Conceptual Diagram of Clock Generation

19.1 Outline of JTAG

19.2 Configuration of JTAG Circuit

19.3 JTAG Registers

19.4 Basic Operation of JTAG

19.5 Boundary Scan Description Language

19.6 Notes on Board Design when Connecting JTAG

19.7 Processing Pins when Not Using JTAG

19-232176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 The M32R/ECU contains a JTAG (Joint Test Action Group) interface compliant with IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1a-1993). This JTAG interface can be used as an input/ output path for boundary-scan test (boundary-scan path). For details about IEEE 1149.1 JTAG test access ports, see IEEE Std. 1149.1a-1993 documentation. Note: • The JTAG interface in the M32R/ECU is used to connect a JTAG emulator during debugging as well. In this chapter, the JTAG interface is explained assuming its use as an input/output path for bound- ary-scan test. Functions of the JTAG interface-related pins mounted on the M32R/ECU are shown below. Table 19.1.1 JTAG Pin Functions Type Pin Name Signal Name I/O Function TAP JTCK Test clock Input Clock input to the test circuit. (Note 1) JTDI Test data Input Input Synchronous serial data input pin used to supply the test instruction code and test data. This input is sampled on the rising edge of JTCK. JTDO Test data Output Output Synchronous serial data output pin used to output the test instruction code and test data. This signal changes state on the falling edge of JTCK, and is output in only the Shift-IR or Shift-DR state. Otherwise, it goes to a high-impedance state. JTMS Test mode select Input Test mode select input to control the test circuit’s state transition. This input is sampled on the rising edge of JTCK. JTRST Test reset Input Active "L" test reset input to initialize the test circuit asynchronously. To ensure that the test circuit is reset without fail, JTMS input signal must be held "H" while this signal changes state from "L" to "H." Note: TAP stands for Test Access Port (JTAG interface specified in IEEE 1149.1).

19-332176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Figure 19.2.1 Configuration of the JTAG Circuit The JTAG circuit consists of the following circuit blocks. Instruction register to hold the instruction code that is fetched through the boundary-scan path A set of registers which are accessed through the boundary-scan path Test access port (abbreviated TAP) controller to control the JTAG unit’s state transition Control logic to select input, output, etc. The figure below shows the configuration of the JTAG circuit. Instruction Register (6-bit) (JTAGIR) Decoder JTDO ID Code Register (JTAGIDR) Bypass Register (JTAGBPR) Boundary Scan Register (JTAGBSR) JTDI Data register set Buffer Output selection Output select ion M32R/ECU

19-432176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

19.3.1 Instruction Register (JTAGIR)

The Instruction Register is a 6-bit register to hold instruction code. This register is set in the IR path sequence. The instructions set in this register determine the data register to be selected in the subsequent DR path sequence. The initial value of this register after test is reset (to initialize the test circuit) is b’000010 (IDCODE instruction). After a test reset, the ID Code Register is selected as the data register until instruction code is set by an external device. In the Capture-IR state, this register always has b’110001 (fixed value) loaded into it. There- fore, when in the Shift-IR state, no matter what value was set in this register, the value b’110001 is always output from the JTDO pin (sequentially beginning with the LSB). However, this value normally is not handled as instruction code. Shown below is outside the scope of guaranteed operations. If this operation is attempted, the microcomputer may handle b’110001 as instruction code, which makes the microcomputer unable to operate normally. Capture-IR → Exit1-IR → Update-IR Following instructions are supported for the JTAG interface of the M32R/ECU: Three instructions specified as essential in IEEE 1149.1 (EXTEST, SAMPLE/PRELOAD, BYPASS) Device identification register access instruction (IDCODE) Table 19.3.1 JTAG Instruction List Instruction Code Abbreviation Operation b'000000 EXTEST Test the circuit/board-level connections external to the chip. b'000001 SAMPLE/PRELOAD Sample the operating status of the circuit and output the sampled status from the JTDO pin, while at the same time supplying the data used for boundary-scan test from the JTDI pin and preset it in the Boundary Scan Register. b'000010 IDCODE Select the ID Code Register to output the device and manufacturer identification data from the JTDO pin. b'111111 BYPASS Select the Bypass Register to inspect or set data. Notes: Do not set any other instruction code. For details about the IR path sequence, DR path sequence, test reset, Capture-IR state, Shift-IR state, Exit1-IR state and Update-IR state, see Section 19.4, “Basic Operation of JTAG.”

19-532176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

19.3.2 Data Register

(1) Boundary Scan Register (JTAGBSR) The Boundary Scan Register is a 475-bit register used to perform boundary-scan test. The bits in this register are assigned to each pin on the microcomputer. Connected between the JTDI and JTDO pins, this register is selected when issuing EXTEST or SAMPLE/ PRELOAD instruction. In the Capture-DR state, this register captures the status of input pins or internal logic outputs. In the Shift-DR state, while outputting the sampled value, this register receives the input data for boundary-scan test to set pin functions (direction of input/output and tristate output pins) and output values. (2) Bypass Register (JTAGBPR) The Bypass Register is a 1-bit register used to bypass the boundary-scan path when the microcomputer is not the target of boundary-scan test. Connected between the JTDI and JTDO pins, this register is selected when issuing BYPASS instruction. This register is loaded with b’0 (fixed value) in the Capture-DR state. (3) ID Code Register (JTAGIDR) The ID Code Register is a 32-bit register used to identify the device and manufacturer. It holds the following information: Version information (4 bits) : b’0000 Part number (16 bits) : b’0011 0010 0010 0100 Manufacturer ID (11 bits) : b’000 0001 1100 This register is connected between the JTDI and JTDO pins, and is selected when issuing IDCODE instruc- tion. This register is loaded with said IDCODE data in the Capture-DR state, and outputs it from the JTDO pin in the Shift-DR state. The ID Code Register is a read-only register. Because the data written from the JTDI pin during DR path sequence is ignored, make sure JTDI input = "L" while in the Shift-DR state. Note: For details about the Capture-DR and Shift-DR states, see Section 19.4, “Basic Operation of JTAG.” 30 4 19 20 31 30 1Manufacturer IDPart numberVersion 4 bits 16 bits 11 bits

19-632176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06

19.4.1 Outline of JTAG Operation

The instruction and data registers basically are accessed in conjunction with the following three operations, which are performed based on the TAP Controller’s state transition. The TAP Controller changes state accord- ing to JTMS input, and generates control signals required for operation in each state.

Capture operation The result of boundary-scan test or the fixed data defined for each register is sampled. As a register opera- tion, data input is latched into the shift register stage.
Shift operation The register is accessed from outside through the boundary-scan path. The sample value is output to the outside at the same time data is set from the outside. As a register operation, the bits are shifted right between each shift register stage.
Update operation The data set from the outside during shifting is driven. As a register operation, the value set in the shift register stage is transferred to the parallel output stage. The JTAG interface undergoes transition of the internal state depending on JTMS input and on such state transition, it performs the following two operations. In either case, the operation basically is performed in order of Capture → Shift → Update.
IR path sequence Instruction code is set in the instruction register to select the data register to be operated on in the subse- quent DR path sequence.
DR path sequence Data inspection or setting is performed for the selected data register.

19-732176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 Select-DR-Scan Test-Logic-Reset Run-Test/Idle Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR 1 0 Select-IR-Scan Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR 1 0 Note: • The values (0 or 1) in this diagram denote the state of JTMS input signal. Figure 19.4.1 TAP Controller State Transition The state transition of the TAP Controller and the basic configuration of the JTAG related registers are shown below. Data input G D T Q D T Q Shift-DR or Shift-IR Clock-DR or Clock-IR Update-DR or Update-IR From the preceding cell To the next cell Data output Parallel output stage Shift register stageInput multiplexer Note: This diagram only shows the basic configuration; not all DR and IR are configured the same way as shown here. Figure 19.4.2 Basic Configuration of the JTAG Related Registers

PDF text was truncated. Refer to the original document for complete details.

Product Information

32176 specifications and overview.

Summary

32-BIT RISC SINGLE-CHIP MICROCOMPUTER

Description

32-BIT RISC SINGLE-CHIP MICROCOMPUTER

Source title 32176 Datasheet(PDF) - Renesas Technology Corp

Related Parts

More parts from the same family.

Browse manufacturer