32174

32170 RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

Before using this material, please visit the above website to confirm that this is the most current document available. Rev. 2.1 Revision date: Jan. 16, 2003 Mitsubishi 32-bit RISC Single-chip Microcomputers M32R Family M32R/ECU Series User's Manual 32170 32174 Group

Keep safety first in your circuit designs! Notes regarding these materials

• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap.
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How to read internal I/O register tables ➀ Bit Numbers: Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the registers located at even addresses are D0-D7, and those at odd addresses are D8-D15. ➁ State of Register at Reset: Represents the initial state of each register immediately after reset with hexadecimal numbers (undefined bits after reset are indicated each in column ➂ .) ➂ At read: ... read enabled ? ... read disabled (read value invalid) 0 ... Read always as 0 1 ... Read always as 1 { At write: : Write enabled ∆ : Write enable conditionally (include some conditions at write) - : Write disabled (Written value invalid) Abit 1234D0 D Bit name Function WR <at reset: H'04> 0 Not assigned. 0

1 Abit

0: ----- 1: ----- Not implemented in the shaded portion. <Example of representation> Bbit Cbit Bbit Cbit 0: ----- 1: ----- 0: ----- 1: ----- Registers represented with thick rectangles are accessible only with halfwords or words (not accessible with bytes). 3 4

Rev. Date of Contents of revision issue Pages Points Revision History 32170/32174 Group User's Manual Overall Description of the 32174 group added P1-7 M32174F4 and M32174F3 added to the internal flash memory and internal RAM in Figure 1.2.1 P1-10 Table 1.2.4 added P1-11 Note 1 in Figure 1.3.1 corrected Incorrect) Operates with a 5 V power supply. Correct) Operates with 3.3 V and 5 V power supplies. P1-12 M32174F4VWG and M32174F3VWG added to Figure 1.3.2 Note 1 corrected Incorrect) Operates with a 5 V power supply. Correct) Operates with 3.3 V and 5 V power supplies. P1-13 Table 1.3.1, "Description of the 32170 Pin Function," corrected P1-19 M32174F4VFP and M32174F3VFP added to Figure 1.4.1 P1-22 M32174F4VWG and M32174F3VWG added to Figure 1.4.2 P2-14 Section 2.7, "Precautions on CPU," newly added P3-6 Address space of the M32174F4 added to Figure 3.1.4 P3-7 Address space of the M32174F3 added to Figure 3.1.5 P3-10 M32174F4 and M32174F3 added to Table 3.3.1 P3-11 M32174F4 and M32174F3 added to Table 3.4.1 P3-12 Internal RAM area/SFR (Special Function Register) area of the M32174F4 and M32174F3 added to Figure 3.4.3 P5-7 Caution corrected P5-8 Caution corrected P5-20- Section 5.5.2, "Processing by Internal Peripheral I/O Interrupt by Handlers," aftered P5-21 Figure 5.5.2 altered P6-2 M32174F4 and M32174F3 added to Table 6.2.1 P6-3 M32174F4 and M32174F3 added to Table 6.3.1 P6-40 Figure 6.5.15 corrected P6-45 Bank configuration of the M32174F4 and M32174F3’s internal RAM added to Figure 6.7.3 P6-46 Precautions in Notes 3 through 5 added P6-50 M32174F4’s virtual-flash emulation area divided in units of 8 Kbytes added to Figure 6.7.10 0.1 Mar.17,00 — First edition issued 2.1 Jan.16,03 ( 1 ⁄ 4 )

Rev. Date of Contents of revision issue Pages Points Revision History 32170/32174 Group User's Manual 2.1 Jan.16,03 ( 2 ⁄ 4 ) P6-50 M32174F4’s virtual-flash emulation area divided in units of 4 Kbytes added to Figure 6.7.11 P6-51 M32174F3’s virtual-flash emulation area divided in units of 8 Kbytes added to Figure 6.7.12 M32174F3’s virtual-flash emulation area divided in units of 8 Kbytes added to Figure 6.7.13 P6-60 Precautions added P7-4 Table 7.3.2 added P8-31– Figures 8.4.1 through 8.4.4 corrected P8-34 P8-35 Section 8.5, “Precautions on Input/output Ports,” newly added P10-1– Chapter 10 overall. Prescalers uniformly referred to as PRS P10-232 P10-83 Figure 10.3.8 corrected P10-184– (1) TOD timer counter write enable/disable conditions newly added P10-185 P10-213– (1) TOM timer counter write enable/disable conditions newly added P10-214 P11-3 Table 11.1.1 corrected P11-48 Contents of description in Section 11.3.5, “Definition of A-D Conversion Accuracy,” altered P11-49 Figure 11.3.5 altered Figures 11.3.6 and 11.3.7 deleted P11-51 Figure 11.4.1, “Internal Equivalent Circuit of the Analog Input Unit,” newly added P12-27 Description of the last line in Section 12.2.8, “SIO Baud Rate Register,” corrected Incorrect) 7 or less → Correct) 7 or more P12-61 Figure 12.7.5, “Timing at Which to Latch Data during UART Reception,” newly added P13-2 Description in Section 13.1, “Outline of the CAN Module,” corrected Incorrect) Compliant with CAN (Controller Area Network) Specification 2.0B Correct) Compliant with CAN (Controller Area Network) Specification 2.0B active

Rev. Date of Contents of revision issue Pages Points Revision History 32170/32174 Group User's Manual 2.1 Jan.16,03 ( 3 ⁄ 4 ) P13-2 Contents of protocol description in Table 13.1.1 corrected Incorrect) CAN Specification 2.0B Correct) CAN Specification 2.0B active Precautions added to Table 13.1.1 P13-9 Precautions added to (4) FRST (forcible reset) bit (D11) P13-14 Precautions added to (11) MSN (message slot number) bits (D12–D15) P13-17 Precautions added P13-21 Precautions added to Note 2 P13-35 Precautions added P13-37 Precautions in Note 2 deleted P13-44 Precautions added to description of CAN message slot data 0 (COMSLnDT) P13-59 Section 13.4.2, “CAN Timing,” newly added P13-81 Figure 13.8.2 corrected P13-82 Section 13.9, "Precautions about CAN Module," newly added P18-2 Precautions added to Figure 18.1.1 P19-14 Description of BSDL for the 32170 (Figures 19.5.1 through 19.5.19) deleted P19-15– Precautions added to Figures 19.6.1 and 19.7.2 P19-16 P19-17– Figure 19.7.1, “Processing Pins when Not Using JTAG (for 240QFP),” P19-18 and Figure 19.7.2, “Processing Pins when Not Using JTAG (for 255QFP),” newly added P20-1– Power turn-on/turn-off sequences during VCCE = 3.3 V added to diagrams P20-16 in Chapter 20 P21-3 Recommended operating conditions corrected P21-9 Standard sample’s ICCI-3V temperature characteristics (when operating: f = 8 MHz, 10 MHz) and standard sample’s ICCI-3V temperature characteristics (when reset: f = 8 MHz, 10 MHz) newly added P21-11 A-D conversion characteristics (referenced to AVCC = VREF = VCCE = 5.12 V, Ta = -40 to 85oC, f(XIN) = 10.0 MHz unless otherwise noted) and A-D conversion characteristics (referenced to AVCC = VREF = VCCE = 5.12 V, Ta = -40 to 125oC, f(XIN) = 8.0 MHz unless otherwise noted) corrected

Rev. Date of Contents of revision issue Pages Points Revision History 32170/32174 Group User's Manual P21-12– Section 21.2, “Electrical Characteristics (when VCCE = 3.3 V),” newly P21-19 added P21-23 Table of ratings in (9) RTD timing newly added P21-33 RTD timing added to Figure 21.3.12 Appendix 1 Appendix 1.1 "Dimensional Outline Drawing" altered Appendix 3 Appendix 3 altered or newly added overall Appendix 4“Processing of Unused Pins,” newly added 2.1 Jan.16,03 ( 4 ⁄ 4 )

(1) Table of contents CHAPTER 1 OVERVIEW CHAPTER 2 CPU User Stack Pointer: SPU (CR3)

(2) CHAPTER 3 ADDRESS SPACE CHAPTER 4 EIT

(3) CHAPTER 5 INTERRUPT CONTROLLER (ICU) CHAPTER 6 INTERNAL MEMORY

(4) CHAPTER 7 RESET CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

(5) CHAPTER 10 MULTIJUNCTION TIMERS CHAPTER 9 DMAC

(6) 10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) ..10-84

10.3.10 Operation in TOP Delayed Single-shot Output Mode (With Correction Function)10-91

10.3.11 Operation in TOP Continuous Output Mode (Without Correction Function) .10-96 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) ..10-134 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) ..10-136

(7) 10.4.14 Operation in TIO Continuous Output Mode (Without Correction Function) .10-138

(8) CHAPTER 11 A-D CONVERTERS 10.8.11 Operation in TOD Single-shot Output Mode (without Correction Function)10-199

10.8.12 Operation in TOD Delayed Single-shot Output Mode (without Correction Function)10-201

10.8.13 Operation in TOD Continuous Output Mode (Without Correction Function) .10-203 10.9.11 Operation in TOM Single-shot Output Mode (without Correction Function)10-224

(9) CHAPTER 12 SERIAL I/O

(10) CHAPTER 13 CAN MODULE

(11) 13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission ..13-75 CHAPTER 14 REAL-TIME DEBUGGER (RTD)

(12) CHAPTER 15 EXTERNAL BUS INTERFACE CHAPTER 16 WAIT CONTROLLER CHAPTER 17 RAM BACKUP MODE

(13) CHAPTER 18 OSCILLATION CIRCUIT CHAPTER 19 JTAG CHAPTER 20 POWER-ON/POWER-SHUTDOWN SEQUENCE

(14) CHAPTER 21 ELECTRICAL CHARACTERISTICS 21.2 CHAPTER 22 TYPICAL CHARACTERISTICS

(15) APPENDIX 1 MECHANICAL SPECIFICATIONS APPENDIX 2 INSTRUCTION PROCESSING TIME APPENDIX 3 PRECAUTIONS ABOUT NOISE Appendix 3.1.2 APPENDIX 4 PROCESSING OF UNUSED PINS

1.1 Outline

1.2 Block Diagram

1.3 Pin Function

1.4 Pin Layout

1-2 32170/32174 Group User's Manual (Rev. 2.1)

1.1.1 M32R Family CPU Core

(1) Based on RISC architecture

• The 32170 and 32174 are 32-bit RISC single-chip microcomputers; each of them is built around the M32R family CPU core (hereafter referred to as the M32R) and incorporates flash memory, RAM, and various other peripheral functions-all integrated into a single chip.
• The M32R is based on RISC architecture. Memory access is performed using load and store instructions, and various arithmetic operations are executed using register-to-register operation instructions. The M32R internally contains sixteen 32-bit general-purpose registers and has 83 distinct instructions.
• The M32R supports compound instructions such as Load & Address Update and Store & Address Update, in addition to ordinary load and store instructions. These compound instructions help to speed up data transfers. (2) 5-stage pipelined processing
• The M32R uses 5-stage pipelined instruction processing consisting of Instruction Fetch, Decode, Execute, Memory Access, and Write Back. Not just load and store instructions or register-to-register operation instructions, compound instructions such as Load & Address Update and Store & Address Update also are executed in one cycle.
• Instructions are entered into the execution stage in the order they are fetched, but this does not always mean that the first instruction entered is executed first. If the execution of a load or store instruction entered earlier is delayed by one or more wait cycles inserted in memory access, a register-to-register operation instruction entered later may be executed before said load or store instruction. By using "out-of-order-completion" like this, the M32R controls instruction execution without wasting clock cycles. (3) Compact instruction code
• The M32R instructions come in two types: one consisting of 16 bits in length, and the other consisting of 32 bits in length. Use of the 16-bit length instruction format especially helps to suppress the program code size.
• Some 32-bit long instructions can branch directly to a location 32 Mbytes forward or backward from the instruction address being executed. Compared to architectures where address space is segmented, this direct jump allows for easy programming. OVERVIEW

1-3 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW

1.1.2 Built-in Multiply-Accumulate Operation Function

(1) Built-in high-speed multiplier

• The M32R incorporates a 32-bit × 16-bit high-speed multiplier which enables it to execute a 32-bit × 32-bit integral multiplication instruction in three cycles (1 cycle = 25 ns when using a 40 MHz internal CPU clock). (2) Supports Multiply-Accumulate operation instructions comparable to DSP
• The M32R supports the following four modes of Multiply-Accumulate operation instructions (or multiplication instructions) using a 56-bit accumulator. Any of these operations can be executed in one cycle. (a) 16 high-order register bits × 16 high-order register bits (b) 16 low-order register bits × 16 low-order register bits (c) Entire 32 register bits × 16 high-order register bits (d) Entire 32 register bits × 16 low-order register bits
• The M32R has instructions to round off the value stored in the accumulator to 16 or 32 bits, as well as instructions to shift the accumulator value to adjust digits and store the digit-adjusted value in a register. These instructions also can be executed in one cycle, so that when combined with high-speed data transfer instructions such as Load & Address Update and Store & Address Update, they enable the M32R to exhibit high data processing capability comparable to that of DSP.

1.1.3 Built-in Flash Memory and RAM

• This microcomputer contains flash memory and RAM which can be accessed with no wait states, allowing you to build a high-speed embedded system.
• The internal flash memory allows for on-board programming (you can write to it while being mounted on the printed circuit board). Use of flash memory means the chip engineered at the development phase can be used directly in mass-production, so that you can smoothly migrate from prototype to mass-production without changing the printed circuit board.
• The internal flash memory can be rewritten 100 times.
• The internal flash memory has a pseudo-flash emulation function, allowing the internal RAM to be artificially mapped into part of the internal flash memory. This function, when combined with the internal Real-Time Debugger (RTD), facilitates data tuning on ROM tables.
• The internal RAM can be accessed for read or rewrite from an external device independently of the M32R by using RTD (real-time debugger). It is communicated with external devices by RTD's exclusive clock-synchronized serial I/O.

1-4 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW

1.1.4 Built-in Clock Frequency Multiplier

• This microcomputer internally multiplies the input clock signal frequency by 4 and the internal peripheral clock by 2. If the input clock frequency is 10.0 MHz, the CPU clock frequency will be 40 MHz and the internal clock frequency 20 MHz.

1.1.5 Built-in Powerful Peripheral Functions

(1) Built-in multijunction timer (MJT)

• The multijunction timer is configured with the following timers: (a) 16-bit output-related timer × 35 channels (b) 16-bit input/output-related timer × 10 channels (c) 16-bit input-related timer × 11 channels (incorporating three channels of multiply-by-4 counter) (d) 32-bit input-related timer × 8 channels Each timer has multiple modes of operation, which can be selected according of the purpose of use.
• The multijunction timer has internal clock bus, input event bus, and output event bus, allowing multiple timers to be combined for use internally. This provides a flexible way to make use of timer functions.
• The output-related timers (TOP) have a correction function. This function allows the timer's count value in progress to be increased or reduced as desired, thus materializing real-time output control. (2) Built-in 10-channel DMA
• The 10-channel DMA is built-in, supporting data transfers between internal peripheral I/Os or between internal peripheral I/O and internal RAM. Not only can DMA transfer requests be generated in software, but can also be triggered by a signal generated by an internal peripheral I/O (e.g., A-D converter, MJT, or serial I/O).
• Cascaded connection between DMA channels (DMA transfer in a channel is started by completion of transfer in another) is also supported, allowing for high-speed transfer processing without imposing any extra load on the CPU. (3) Built-in 16-channel A-D converters
• This microcomputer contains two 16-channel A-D converters which can convert data in 10-bit resolution. In addition to single A-D conversion in each channel, successive A-D conversion in four, eight, or 16 channels combined into one unit is possible.
• In addition to ordinary A-D conversion, a comparator mode is supported in which the A-D conversion result is compared with a given set value to determine the relative magnitudes of two quantities.
• When A-D conversion is completed, this microcomputer can generate not only an interrupt, but can also generate a DMA transfer request.
• This microcomputer supports two read out modes, so that A-D conversion results can be read out in 8 bits or 10 bits.

1-5 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW (4) High-speed serial I/O

• This microcomputer incorporates 6 channels of serial I/O, which can be set for clock- synchronized serial I/O or UART.
• When set for clock-synchronized serial I/O, the data transfer rate is a high 2 Mbits per second.
• When data reception is completed or the transmit buffer becomes empty, the serial I/O can generate a DMA transfer request signal. (5) Built-in Real-Time Debugger (RTD)
• The Real-Time Debugger (RTD) provides a function for the M32R/ECU's internal RAM to be accessed directly from an external device. The debugger communicates with external devices through its exclusive clock-synchronized serial I/O.
• By using the RTD, you can read the contents of the internal RAM or rewrite its data from an external device independently of the M32R.
• The debugger can generate an RTD interrupt to notify that RTD-based data transmission or reception is completed. (6) Eight-level interrupt controller
• The interrupt controller manages interrupt requests from each internal peripheral I/O by resolving interrupt priority in eight levels including an interrupt-disabled state. Also, it can accept external interrupt requests due to power-down detection or generated by a watchdog timer as a System Break Interrupt (SBI). (7) Three operation modes
• The M32R/ECU has three operation modes-single-chip mode, extended external mode, and processor mode. The address space and external pin functions of the M32R/ECU are switched over according to a mode in which it operates. The MOD0 and MOD1 pins are used to set a mode. (8) Wait controller
• The wait controller supports access to external devices by the M32R. In all but single-chip mode, the extended external area provides 4 Mbytes of space.

1-6 32170/32174 Group User's Manual (Rev. 2.1)

1.1.6 Built-in Full-CAN Function

• This microcomputer contains CAN Specification V2.0B active-compliant CAN module, thereby providing 16 message slots.

1.1.7 Built-in Debug Function

• This microcomputer supports JTAG interface. Boundary scan test can be performed using this JTAG interface. OVERVIEW

1-7 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW Figure 1.2.1 shows a block diagram of the 32170/32174. Features of each block are shown in Figure 1.2.1 Block Diagram of the 32170/32174 PLL clock generator circuit Internal bus interface AddressData Internal RAM (M32170F6:40KB) (M32170F4:32KB) (M32170F3:32KB) (M32174F4:40KB) (M32174F3:40KB) Internal flash memory (M32170F6:768KB) (M32170F4:512KB) (M32170F3:384KB) (M32174F4:512KB) (M32174F3:384KB) M32R CPU core (max 40MHz) Multiplier- accumulator (32 × 16 + 56) DMAC (10 channels) Multijunction timer (MJT: 64 channels) Serial I/O (6 channels) A-D converter (10-bit resolution, 16 channels) × 2 Wait controller Interrupt controller (31 sources, 8 levels) Real-time debugger (RTD) External bus interface Internal 16-bit bus Internal 32-bit bus Input/output port (JTAG), 157 lines Full CAN (1 channel)

1-8 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW Table 1.2.1 Features of the M32R Family CPU Core Functional Block Features M32R family • Bus specifications CPU core Basic bus cycle: 25 ns (when operating with 40 MHz CPU clock) Logical address space: 4Gbytes, linear Extended external area: Maximum 4 Mbytes External data bus: 16 bits

• Implementation: Five-stage pipeline
• Internal 32-bit architecture for the core
• Register configuration General-purpose register: 32 bits × 16 registers Control register: 32 bits × 5 registers
• Instruction set 16-bit and 32-bit instruction formats 83 distinct instructions and 6 addressing modes
• Built-in multiplier/accumulator (32 × 16 + 56) Table 1.2.2 Features of Internal Memory Functional Block Features RAM • Capacity M32170F6, M32174F4, M32174F3 : 40 Kbytes M32170F4, M32170F3 : 32 Kbytes
• No-wait access (when operating with 40 MHz CPU clock)
• By using RTD (real-time debugger), the internal RAM can be accessed for read or rewrite from external devices independently of the M32R. Flash memory • Capacity M32170F6 : 768 Kbytes M32170F4, M32174F4 : 512 Kbytes M32170F3, M32174F3 : 384 Kbytes
• No-wait access (when operating with 40 MHz CPU clock)
• Durability: Can be rewritten 100 times

1-9 32170/32174 Group User's Manual (Rev. 2.1) Table 1.2.3 Features of Internal Peripheral I/O Functional Block Features DMA • 10-channel DMA

• Supports transfer between internal peripheral I/Os and between internal peripheral I/O and internal RAM.
• Capable of advanced DMA transfer when operating in combination with internal peripheral I/O
• Capable of cascaded connection between DMA channels (DMA transfer in a channel is started by completion of transfer in another) Multijunction • 64-channel multifunction timer
• Contains output-related timer × 35 channels, input/output-related timer × 10 channels, 16-bit input-related timer × 11 channels, and 32-bit input-related timer × 8 channels.
• Capable of flexible timer configuration by mutual connection between each channel. A-D converter • 16-channel, 10-bit resolution A-D converter × 2 units
• Incorporates comparator mode
• Can generate interrupt or start DMA transfer upon completion of A-D conversion.
• Can read out conversion results in 8 or 10 bits. Serial I/O • 6-channel serial I/O
• Can be set for clock-synchronized serial I/O or UART.
• Capable of high-speed data transfer at 2 Mbits per second when clock synchronized or 156 Kbits per second during UART. Real-time debugger• Can rewrite or monitor the internal RAM independently of the CPU by command input from an external source.
• Has its exclusive clock-synchronized serial port. Interrupt controller• Accepts and manages interrupt requests from internal peripheral I/O.
• Resolves interrupt priority in 8 levels including interrupt-disabled state. Wait controller • Controls wait state for access to extended external areas.
• Can insert 1 to 4 wait cycles by setting in software and extend wait period by external WAIT signal. Clock PLL • Multiply-by-4 clock generator circuit
• Maximum 40 MHz of CPU clock (CPU, internal ROM, internal RAM access)
• Maximum 20 MHz of internal peripheral clock (peripheral module access)
• Maximum external input clock frequency=10 MHz CAN • Sixteen message slots JTAG • Capable of boundary scan OVERVIEW

1-10 32170/32174 Group User's Manual (Rev. 2.1) Table 1.2.4 List of Type Name Type Name RAM Size (K bytes) ROM Size (K bytes) Package Number of Pins M32170F3VFP 32 384 240QFP 240 M32170F4VFP 32 512 240QFP 240 M32170F6VFP 40 768 240QFP 240 M32170F3VWG 32 384 255FBGA 255 M32170F4VWG 32 512 255FBGA 255 M32170F6VWG 40 768 255FBGA 255 M32174F3VFP 40 384 240QFP 240 M32174F4VFP 40 512 240QFP 240 M32174F3VWG 40 384 255FBGA 255 M32174F4VWG 40 512 255FPGA 255 OVERVIEW

1-11 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW Figure 1.3.1 shows a pin function diagram of the 32170/32174 in 240QFP package. Figure explains the function of each pin of the 32170/32174. Table 1.3.2 explains the function of the dedicated debug pins of the 32170/32174 in 255FBGA package. Figure 1.3.1 Pin Function Diagram of 240QFP XIN RESET M32170F6VFP , M32170F4VFP , M32170F3VFP , M32174F4VFP , M32174F3VFP Clock Reset VCCI VSS P20 — P27/A23 — A30 P30 — P37/A15 — A22 P46, P47/A13, A14 Address bus20 P00 — P07/DB0 — DB7 P10 — P17/DB8 — DB15 Data bus P72/HREQ P73/HACK Bus control P71/WAIT Interrupt controller P43/RD P44/CS0 P45/CS1 P41/BLW/BLE P42/BHW/BHE Port 22 Port 2 Port 3 Port 4 Port 0 Port 1 Port 7 Port 4 XOUT VCNT OSC-VCC OSC-VSS MOD0 MOD1Mode P190 — P197/TIN26 — TIN33 P172, P173/TIN24, TIN25 P150 — P157/TIN0 — TIN7 P140 — P147/TIN8 — TIN15 P130 — P137/TIN16 — TIN23 Port 19 Port 17 Port 15 Port 14 Port 13 P124 — P127/ TCLK0 — TCLK 3 4Multi- junction timer P210-P217/TO37-TO44 P180-P187/TO29 -TO36 P160-P167/TO21-TO28 P110-P117/TO0- TO7 P100-P107/TO8-TO15 P93-P97/TO16 -TO20 Port 12 Port 21 Port 18 Port 16 Port 11 Port 10 Port 9 P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK Real-time debugger Port 7 P70/BCLK/WR Port 7 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 Serial I/O Port 8 AD1IN0 — AD1IN15 A-D converter P67/ADTRG AVCC0, AVCC1 AVSS0, AVSS1 Port 6 P61-P63Port 6 AVREF0, AVREF1 VDD FVCC FP VCCE 7 P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 Port 17 3.3V 3.3V 3.3V 3.3V Note1: : denotes blocks operating with a 3.3 V power supply. : denotes blocks operating with a 5 V or 3.3V power supply. AD0IN0 — AD0IN15 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 Port 20 P220/CTX P221/CRXCAN JTMS JTCK JTRST JTDO JTAG JTDI Port 22 P222, P223Port 22 P224/A11(Note2) P225/A12(Note2) Note2: Use caution when using this port because it has a debug event function. P65/SCLKI4/SCLKO4 P64/SBIPort 6 P66/SCLKI5/SCLKO5 Port 6

1-12 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW Figure 1.3.2 Pin Function Diagram of 255FBGA XIN RESET M32170F6VWG , M32170F4VWG , M32170F3VWG , M32174F4VWG , M32174F3VWG Clock Reset VCCI VSS P20—P27/A23—A30 P30—P37/A15—A22 P46, P47/A13, A14 Address bus20 P00—P07/DB0—DB7 P10—P17/DB8—DB15 Data bus P72/HREQ P73/HACK Bus control P71/WAIT Interrupt controller P43/RD P44/CS0 P45/CS1 P41/BLW/BLE P42/BHW/BHE Port 22 Port 2 Port 3 Port 4 Port 0 Port 1 Port 7 Port 4 XOUT VCNT OSC-VCC OSC-VSS MOD0 MOD1Mode P190—P197/TIN26—TIN33 P172, P173/TIN24, TIN25 P150 —P157/TIN0—TIN7 P140—P147/TIN8—TIN15 P130—P137/TIN16—TIN23 Port 19 Port 17 Port 15 Port 14 Port 13 P124—P127/ TCLK0 —TCLK 3 4Multi- junction timer P210—P217/TO37—TO44 P180—P187/TO29—TO36 P160—P167/TO21—TO28 P110—P117/TO0—TO7 P100—P107/TO8—TO15 P93—P97/TO16—TO20 Port 12 Port 21 Port 18 Port 16 Port 11 Port 10 Port 9 P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK Real-time debugger Port 7 P70/BCLK/WR Port 7 P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 Serial I/O Port 8 AD1IN0 —AD1IN15 A-D converter P67/ADTRG AVCC0, AVCC1 AVSS0, AVSS1 Port 6 P61—P63Port 6 AVREF0, AVREF1 VDD FVCC FP VCCE P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 Port17 3.3V 3.3V 3.3V 3.3V Note1: : denotes blocks operating with a 3.3 V power supply : denotes blocks operating with a 5 V or 3.3V power supply. AD0IN0 —AD0IN15 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 Port 20 P220/CTX P221/CRXCAN JTMS JTCK JTRST JTDO JTAG JTDI Port 22 P222, P223Port 22 P224/A11 (Note2) P225/A12 (Note2) Note2: Use caution when using this port because it has a debug event function. P65/SCLKI4/SCLKO4 P64/SBIPort 6 P66/SCLKI5/SCLKO5 Port 6 TRCLK TRSYNC TRDATA JDBI JEVENTO JEVENT1 DBGUG Note3: 255FBGA is currently under development.

1-13 32170/32174 Group User's Manual (Rev. 2.1) Table 1.3.1 Description of the 32170 Pin Function (1/6) Type Pin Name Signal Name Input/OutputFunction Power VCCE Power supply — Power supply to external I/O ports (5 V or 3.3V). supply VCCI Power supply — Power supply to internal logic (3.3 V). VDD RAM power supply — Power supply for internal RAM backup (3.3 V). FVCC FLASH power supply— Power supply for internal flash memory (3.3 V). VSS Ground — Connect all VSS to ground (GND). Clock XIN, Clock Input Clock input/output pins. These pins contains a PLL-based XOUT Output frequency multiplier circuit. Apply a clock whose frequency is 1/4 the operating frequency. (When using 40 MHz CPU clock, XIN input = 10.0 MHz) BCLK/WR System clock Output When BCLK pin is selected, it outputs a clock whose frequency is twice that of an external input clock (e.g., BCLK output = 20 MHz when an external input clock is 10 MHz). Use this facility for external synchronization design. When WR# pin is selected, it indicates the byte position in which valid data is transferred when writing to an external device. OSC-VCC Power supply — Power supply for PLL circuit. Connect OSC-VCC to the power supply rail. OSC-VSS Ground — Connect OSC-VSS to ground. VCNT PLL control Input This pin controls the PLL circuit. Connect a resistor and capacitor to it. (For external circuits, refer to Section 18.1.1, "Example of an Oscillator Circuit.") Reset RESET Reset Input This pin resets the internal circuit. Mode MOD0 Mode Input These pins set operation mode. MOD1 FP MOD0 MOD1 Mode X 0 0 Single-chip mode X 0 1 Extended external mode 0 1 0 Processor mode 1 1110 000 (Boot mode) (Note) X 1 1 (Reserved) Address A11 – A30 Address Output The device has 20 address lines (A11-A30) to allow two Bus Bus channels of up to 2 MB of memory space to be added external to the chip. A31 is not output. Note: For boot mode, refer to Chapter 6, "Internal Memory." OVERVIEW

1-14 32170/32174 Group User's Manual (Rev. 2.1) Table 1.3.1 Description of the 32170 Pin Function (2/6) Type Pin Name Signal Name Input/OutputFunction Data DB0-DB15 Data bus Input/OutputThese pins comprise 16-bit data bus to connect external devices. In write bus cycles, the valid byte positions to be___ ___ written on the 16-bit data bus are output as BHW/BHE and___ ___ BLW/BLE. In read cycles, data is always read from the 16- bit data bus. However, when transferring to the internal circuit of the M32R, only data at the valid byte positions are transferred. Bus ___ CS0, Chip select Output These pins comprise external device chip select signal. For control ___ CS1 areas for which a chip select signal is output, refer to Chapter 3, "Address Space." RD Read Output This signal is output when reading an external device. BHW/BHE Byte high Output Indicates the byte position to which valid data is transferred write/enable when writing to an external device. BHW/BHE corresponds BLW/BLE Byte low Output to the upper address (D0-D7 is valid); BLW/BLE write/enable corresponds to the lower address (D8-D15 is valid). ____ WAIT Wait Input When the M32R accesses an external device, a low on this ____ WAIT input extends the wait cycle. ____ HREQ Hold request Input This pin is used by an external device to request control of ____ the external bus. A low on this HREQ input causes the M32R to enter a hold state. ____ HACK Hold Output This signal is used to notify that the M32R has entered a acknowledge hold state and relinquished control of the external bus. TIN 0–TIN 33 Timer input Input Input pins for multijunction timer. TO 0– TO 44 Timer output Output Output pins for the multijunction timer. TCLK 0– TCLK 3 Timer clock Input Clock input pins for the multijunction timer. A-D AVCC0, Analog power supply — AVCC0 is the power supply for the A-D0 converter. AVCC1 converterAVCC1 is the power supply for the A-D1 converter. Connect AVCC0 and 1 to the power supply rail. AVSS0, Analog ground — AVSS0 is analog ground for the A-D0 converter. AVSS1 is AVSS1 — analog ground for the A-D1 converter. Connect AVSS0 and 1 to the ground. AD0IN0 Analog input Input 16-channel analog input pins for the A-D0 converter. –AD0IN15 AD1IN0 16-channel analog input pins for the A-D1 converter. –AD1IN15 OVERVIEW

1-15 32170/32174 Group User's Manual (Rev. 2.1) Table 1.3.1 Description of the 32170 Pin Function (3/6) Type Pin Name Signal Name Input/OutputFunction A-D VREF0, Reference Input VREF0 is the reference voltage input pin for the A-D0 converter. converterVREF1 voltage input VREF1 is the reference voltage input pin for the A-D1 converter. ADTRG Conversion Input Hardware trigger input pin to start A-D conversion. trigger Interrupt ___ SBI System break Input System break interrupt (SBI) input pin for the interrupt controller interrupt controller Serial I/O SCLKI0 /UART transmit/Input/outputWhen channel 0 is in UART mode: SCLKO0 receive clock This pin outputs a clock derived from BRG output by halving it. output or CSIO transmit/receive When channel 0 is in CSIO mode: clock input/output This pin accepts as its input a transmit/receive clock when external clock source is selected or outputs a transmit/receive clock when internal clock source is selected. SCLKI1 / UART transmit/Input/outputWhen channel 1 is in UART mode: SCLKO1 receive clock This pin outputs a clock derived from BRG output by halving it. output or CSIO transmit/receive When channel 1 is in CSIO mode: clock input/output This pin accepts as its input a transmit/receive clock when external clock source is selected or outputs a transmit/receive clock when internal clock source is selected. SCLKI4 / UART transmit/Input/outputWhen channel 4 is in UART mode: SCLKO4 receive clock This pin outputs a clock derived from BRG output by halving it. output or CSIO transmit/receive When channel 4 is in CSIO mode: clock input/output This pin accepts as its input a transmit/receive clock when external clock source is selected or outputs a transmit/receive clock when internal clock source is selected. SCLKI5 / UART transmit/Input/outputWhen channel 5 is in UART mode: SCLKO5 receive clock This pin outputs a clock derived from BRG output by halving it. output or CSIO transmit/receive When channel 5 is in CSIO mode: clock input/output This pin accepts as its input a transmit/receive clock when external clock source is selected or outputs a transmit/receive clock when internal clock source is selected. TXD0 Transmit data output Transmit data output pin for serial I/O channel 0 RXD0 Receive data Input Receive data input pin for serial I/O channel 0 OVERVIEW

1-16 32170/32174 Group User's Manual (Rev. 2.1) Real-time debugger TXD1 Transmit data Output Transmit data output pin for serial I/O channel 1. RXD1 Receive data Input Receive data input pin for serial I/O channel 1. TXD2 Transmit data Output Transmit data output pin for serial I/O channel 2. RXD2 Receive data Input Receive data input pin for serial I/O channel 2. TXD3 Transmit data Output Transmit data output pin for serial I/O channel 3. RXD3 Receive data Input Receive data input pin for serial I/O channel 3. TXD4 Transmit data Output Transmit data output pin for serial I/O channel 4. RXD4 Receive data Input Receive data input pin for serial I/O channel 4. TXD5 Transmit data Output Transmit data output pin for serial I/O channel 5. RXD5 Receive data Input Receive data input pin for serial I/O channel 5. RTDTXD Transmit data Output Serial data output pin for the real-time debugger. RTDRXD Receive data Input Serial data input pin for the real-time debugger. RTDCLK Clock input Input Serial data transmit/receive clock input pin for the real-time debugger. RTDACK Acknowledge Output This pin outputs a low pulse synchronously with the beginning clock of the real-time debugger's serial data output word. The duration of this low pulse indicates the type of command/data that the real-time debugger has received. Flash FP Flash Protect Input This mode pin has a function to protect the flash -only memory against E/W in hardware. CAN CTX Data output Output This pin outputs data from the CAN module. CRX Data input Input This pin is used to input data to the CAN module. JTAG JTMS Test mode Input Test mode select input to control state transition of the test circuit. JTCK clock Input Clock input for the debug module and test circuit. JTRST Test reset Input Test reset input to initialize the test circuit asynchronously. JTDI Serial input Input This pin is used to input test instruction code or test data serially. JTDO Serial output Output This pin outputs test instruction code or test data serially. OVERVIEW Table 1.3.1 Description of the 32170 Pin Function (4/6) Type Pin Name Signal Name Input/OutputFunction

1-17 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW Table 1.3.1 Description of the 32170 Pin Function (5/6) Type Pin Name Signal Name Input/OutputFunction P00 – P07 Input/output Input/outputProgrammable input/output port. port 0 P10 – P17 Input/output Input/outputProgrammable input/output port. port 1 P20 – P27 Input/output Input/outputProgrammable input/output port. port 2 P30 – P37 Input/output Input/outputProgrammable input/output port. port 3 P41 – P47 Input/output Input/outputProgrammable input/output port. port 4 P61 – P67 Input/output Input/outputProgrammable input/output port. port 6 (However, P64 is an input-only port.) P70 – P77 Input/output Input/outputProgrammable input/output port. port 7 P82 – P87 Input/output Input/outputProgrammable input/output port. port 8 P93 – P97 Input/output Input/outputProgrammable input/output port. port 9 P100 Input/output Input/outputProgrammable input/output port. – P107 port 10 P110 Input/output Input/outputProgrammable input/output port. – P117 port 11 P124 Input/output Input/outputProgrammable input/output port. – P127 port 12 P130 Input/output Input/outputProgrammable input/output port. – P137 port 13 P140 Input/output Input/outputProgrammable input/output port. – P147 port 14 P150 Input/output Input/outputProgrammable input/output port. – P157 port 15 P160 Input/output Input/outputProgrammable input/output port. – P167 port 16 Input/ output port (Note) Note: Input/output port 5 is reserved for future use.

1-18 32170/32174 Group User's Manual (Rev. 2.1) P172 Input/output Input/outputProgrammable input/output port. – P177 port 17 P180 Input/output Input/outputProgrammable input/output port. – P187 port 18 P190 Input/output Input/outputProgrammable input/output port. – P197 port 19 P200 Input/output Input/outputProgrammable input/output port. – P203 port 20 P210 Input/output Input/outputProgrammable input/output port. – P217 port 21 P220 Input/output Input/outputProgrammable input/output port. (Note) – P225 port 22 (However, P221 is an input only port.) Note: Use caution when using P224 and P225 because they have a debug event function. Table 1.3.2 Description of the Debug-only Pin Function of 255FBGA Type Pin Name Signal Name Input/OutputFunction DEBOG JDBI Debug interruptInput Debug interrupt request input pin. A low on this input request requests a debug interrupt. JEVENT0, Event output Output Output synchronously with TRCLK. When an event occurs, JEVENT1 this output is driven high for a 1 TRCLK period. TRCLK Trace clock Output Clock output pin for trace operation. Trace data is output output synchronously with this clock. TRSYNC Trace packet Output This is a trace packet output start signal. When the device output start signal starts outputting a trace packet, this signal is driven high for a 1 TRCLK period. TRDATA0 Trace packet Output Trace packet output pin. - TRDATA7 output Note: 255FBGA is currently under development. Table 1.3.1 Description of the 32170 Pin Function (6/6) Type Pin Name Signal Name Input/OutputFunction Input/ output port OVERVIEW

1-19 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW shows a pin layout diagram of the 32170/32174 in 255FBGA package. Table 1.4.1 lists pin assignments of the 240QFP. Table 1.4.2 lists pin assignments of the 255FBGA. Figure 1.4.1 Pin Layout Diagram of the 240QFP (Top View) Package: 240P6Y-A (0.5 mm pitch) Note: Use caution when using these pins because they have a debug event function. M32170F3VFP M32170F4VFP M32170F6VFP M32174F4VFP M32174F3VFP 2 43 44435 6 7 8 9 353637383940222324252627282930313233341112131415161718192021 4142101 6059515253545556454647484950 5758 103 102 101 112 111 110 109 108 107 106 105 104 120 119 118 117 116 115 114 113 100 124132 130129 127 121137146145144143142141140139138155154153152151150149148147156159158157 133136135134 123122131 128 126125166165164163162161175174173172171170169168167176179178177 160180 195 185 184 183 182 181 186 189 188 187 194 193 192 191 190 196 199 198 197 205 204 203 202 201 200 206 209 208 207 215 214 213 212 211 210 216 239 217 219 218 225 224 223 222 221 220 226 227 229 228 230 235 234 233 232 231 236 237 238 240 P41/BLW/BLE P157/TIN7 P156/TIN6 P155/TIN5 P154/TIN4 P153/TIN3 P152/TIN2 P151/TIN1 P150/TIN0 P147/TIN15 P146/TIN14 P145/TIN13 P144/TIN12 P143/TIN11 P142/TIN10 P141/TIN9 P140/TIN8 VSS VCCE P137/TIN23 P136/TIN22 P135/TIN21 P134/TIN20 P133/TIN19 P132/TIN18 P131/TIN17 P130/TIN16 VSS VCCI P42/BHW/BHE P127/TCLK3 P126/TCLK2 P125/TCLK1 P124/TCLK0 P107/TO15 P106/TO14 P105/TO13 P104/TO12 VSSVCCI P103/TO11 VSS VCCI P43/RDP44/CS0P45/CS1 P14/DB12P37/A22P36/A21P33/A18P31/A16P30/A15 P35/A20P34/A19P32/A17 VCCE P27/A30P25/A28P26/A29P24/A27 P07/DB7P02/DB2P01/DB1P00/DB0P23/A26P22/A25P20/A23 P10/DB8P11/DB9 VSS P15/DB13P13/DB11P12/DB10P06/DB6P04/DB4P03/DB3P47/A14 P21/A24P46/A13 VCCEVSS P16/DB14P17/DB15 P82/TXD0 VSS VCCE P172/TIN24 P173/TIN25 P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 P160/TO21 P161/TO22 P162/TO23 P163/TO24 P164/TO25 P165/TO26 P166/TO27 P167/TO28 VSS VCCI VREF0 AVCC0 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AVSS0 P181/TO30 P182/TO31 P183/TO32 P184/TO33 P180/TO29 VSS VCCE P186/TO35 P187/TO36 P190/TIN26 P185/TO34 P194/TIN30 P195/TIN31 P196/TIN32 P197/TIN33 P191/TIN27 P192/TIN28 P193/TIN29 RESET P84/SCLKI0/SCLKO0 P83/RXD0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1VSSVCCE VCCIP62VSSFP P67/ADTRGP66/SCLKI5/SCLKO5P65/SCLKI4/SCLKO4P94/TO17 P74/RTDTXDP75/RTDRXDP76/RTDACKP77/RTDCLK P61P63P114/TO4P115/TO5P116/TO6P117/TO7 VSSVCCEMOD1P100/TO8P101/TO9P102/TO10 P110/TO0P111/TO1P112/TO2P113/TO3 P95/TO18P96/TO19P97/TO20 P70/BCLK/WRP71/WAITP72/ HREQ P64/SBIMOD0 P93/TO16 P73/ HACK VCCI VSSVDD FVCC P201/RXD4P202/TXD5P203/RXD5P200/TXD4 AD1IN5 AD1IN4 AD1IN3 AD1IN2 AD1IN1 AD1IN0 VREF1 AD1IN15AD1IN14AD1IN13AD1IN12 AVSS1 AD1IN6 JTDO JTRST JTCK JTMS JTDI P212/TO39P213/TO40P214/TO41P215/TO42P211/TO38P210/TO37P216/TO43P217/TO44 VCNT OSC-VCC XOUT XIN OSC-VSSP221/CRXP220/CTX VSSVSS P05/DB5 AD1IN11 AD1IN10 AD1IN9 AD1IN8 AD1IN7 P222P223 (Note) P224/A11(Note) P225/A12 VSS AVCC1

1-20 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW Table 1.4.1 Pin Assignments of the 240QFP (1/2) No. Pin Name No. Pin Name No. Pin Name No. Pin Name

1 AD1IN12 41 P26 / A29 81 VSS 121 P87 / SCLKI1 / SCLKO1

2 AD1IN13 42 P27 / A30 82 P180 / TO29 122 P200 / TXD4

3 AD1IN14 43 P00 / DB0 83 P181 / TO30 123 P201 / RXD4

4 AD1IN15 44 P01 / DB1 84 P182 / TO31 124 P202 / TXD5

5 AVSS1 45 P02 / DB2 85 P183 / TO32 125 P203 / RXD5

P43 / RD 46 P03 / DB3 86 P184 / TO33 126 VCCI ___ P44 / CS0 47 P04 / DB4 87 P185 / TO34 127 VSS ___ P45 / CS1 48 P05 / DB5 88 P186 / TO35 128 FVCC

9 P46 / A13 49 P06 / DB6 89 P187 / TO36 129 VSS

10 P47 / A14 50 P07 / DB7 90 P190 / TIN26 130 P61

11 P220 / CTX 51 VCCE 91 P191 / TIN27 131 P62

12 P221 / CRX 52 VSS 92 P192 / TIN28 132 P63

13 P222 53 P10 / DB8 93 P193 / TIN29 133

___ P64 / SBI

14 P223 54 P11 / DB9 94 P194 / TIN30 134 P65 / SCLKI4 / SCLKO4

15 P224 / A11 55 P12 / DB10 95 P195 / TIN31 135 P66 / SCLKI5 / SCLKO5

16 P225 / A12 56 P13 / DB11 96 P196 / TIN32 136

17 VSS 57 P14 / DB12 97 P197 / TIN33 137 VCCI

18 OSC-VSS 58 P15 / DB13 98 VCCI 138 VSS

19 XIN 59 P16 / DB14 99 VSS 139 VCCE

20 XOUT 60 P17 / DB15 100 P160 / TO21 140

___ P70 / BCLK / WR

21 OSC-VCC 61 VREF0 101 P161 / TO22 141

____ P71 / WAIT

22 VSS 62 AVCC0 102 P162 / TO23 142

____ P72 / HREQ

23 VCNT 63 AD0IN0 103 P163 / TO24 143

____ P73 / HACK

24 VSS 64 AD0IN1 104 P164 / TO25 144 P74 / RTDTXD

25 P30 / A15 65 AD0IN2 105 P165 / TO26 145 P75 / RTDRXD

26 P31 / A16 66 AD0IN3 106 P166 / TO27 146 P76 / RTDACK

27 P32 / A17 67 AD0IN4 107 P167 / TO28 147 P77 / RTDCLK

28 P33 / A18 68 AD0IN5 108 P172 / TIN24 148 P93 / TO16

29 P34 / A19 69 AD0IN6 109 P173 / TIN25 149 P94 / TO17

30 P35 / A20 70 AD0IN7 110 P174 / TXD2 150 P95 / TO18

31 P36 / A21 71 AD0IN8 111 P175 / RXD2 151 P96 / TO19

32 P37 / A22 72 AD0IN9 112 P176 / TXD3 152 P97 / TO20

33 P20 / A23 73 AD0IN10 113 P177 / RXD3 153

34 P21 / A24 74 AD0IN11 114 VCCE 154 MOD0

35 P22 / A25 75 AD0IN12 115 VSS 155 MOD1

36 P23 / A26 76 AD0IN13 116 P82 / TXD0 156 FP

37 VCCE 77 AD0IN14 117 P83 / RXD0 157 VCCE

38 VSS 78 AD0IN15 118

P84 / SCLKI0 / SCLKO0 158 VSS

39 P24 / A27 79 AVSS0 119 P85 / TXD1 159 P110 / TO0

40 P25 / A28 80 VCCE 120 P86 / RXD1 160 P111 / TO1

1-21 32170/32174 Group User's Manual (Rev. 2.1) OVERVIEW Table 1.4.1 Pin Assignments of the 240QFP (2/2) No. Pin Name No. Pin Name No. Pin Name No. Pin Name

161 P112 / TO2 181 JTMS 201 P134 / TIN20 221 P156 / TIN6

162 P113 / TO3 182 JTCK 202 P135 / TIN21 222 P157 / TIN7

163 P114 / TO4 183 JTRST 203 P136 / TIN22 223

164 P115 / TO5 184 JTDO 204 P137 / TIN23 224

165 P116 / TO6 185 JTDI 205 VCCE 225 VCCI

166 P117 / TO7 186 P103 / TO11 206 VSS 226 VSS

167 P100 / TO8 187 P104 / TO12 207 P140 / TIN8 227 VREF1

168 P101 / TO9 188 P105 / TO13 208 P141 / TIN9 228 AVCC1

169 P102 / TO10 189 P106 / TO14 209 P142 / TIN10 229 AD1IN0

170 VDD 190 P107 / TO15 210 P143 / TIN11 230 AD1IN1

171 VCCI 191 P124 / TCLK0 211 P144 / TIN12 231 AD1IN2

172 VSS 192 P125 / TCLK1 212 P145 / TIN13 232 AD1IN3

173 P210 / TO37 193 P126 / TCLK2 213 P146 / TIN14 233 AD1IN4

174 P211 / TO38 194 P127 / TCLK3 214 P147 / TIN15 234 AD1IN5

175 P212 / TO39 195 VCCI 215 P150 / TIN0 235 AD1IN6

176 P213 / TO40 196 VSS 216 P151 / TIN1 236 AD1IN7

177 P214 / TO41 197 P130 / TIN16 217 P152 / TIN2 237 AD1IN8

178 P215 / TO42 198 P131 / TIN17 218 P153 / TIN3 238 AD1IN9

179 P216 / TO43 199 P132 / TIN18 219 P154 / TIN4 239 AD1IN10

180 P217 / TO44 200 P133 / TIN19 220 P155 / TIN5 240 AD1IN11

1-22 32170/32174 Group User's Manual (Rev. 2.1) Package: 255F7F (0.8 mm pitch) Note 1:NC pins (W19, Y1) are not internally connected. Leave them open. Note 2:Use caution when using P224/A11 and P225/A12 because they have a debug event function. Note 3:255FBGA is currently under development. Figure 1.4.2 Pin Layout Diagram of the 255FBGA (Top View) ABCDE FGH JKL MNPRT UVW Y AD1IN12 AD1IN13 AD1IN14 AD1IN15 AVSS1 P43 /RD P44 /CS0 P45 /CS1 P46 /A13 P47 /A14 P220 /CTX P221 /CRX P222 P223 P224 /A11 P225 /A12 VSS OSC- VSS XIN XOUT OSC- VCC VSS VCNT VSS P30 /A15 P31 /A16 P32 /A17 P33 /A18 P34 /A19 P35 /A20 TRCLK TRSYNC P36 /A21 P37 /A22 P20 /A23 P21 /A24 P23 /A26 P22 /A25 VCCE VSS P24 /A27 P25 /A28 P26 /A29 P27 /A30 P00 /DB0 P01 /DB1 P02 /DB2 P03 /DB3 P04 /DB4 P05 /DB5 P06 /DB6 P07 /DB7 VCCE VSS P10 /DB8 P11 /DB9 P12 /DB10 P13 /DB11 P14 /DB12 P15 /DB13 P16 /DB14 P17 /DB15 VREF0 AVCC0 AD0IN0AD0IN1 AD0IN2 AD0IN3 AD0IN4AD0IN5 AD0IN6 AD0IN7 AD0IN8AD0IN9 AD0IN10 AD0IN11 AD0IN12AD0IN13 AD0IN14 AD0IN15 A VSS0VCCE VSS P180 /TO29 P181 /TO30 P182 /TO31 P183 /TO32 P184 /TO33 P185 /TO34 P186 /TO35 P187 /TO36 P190 /TIN26 P191 /TIN27 P192 /TIN28 P193 /TIN29 P194 /TIN30 P196 /TIN32 P195 /TIN31 P197 /TIN33 VCCI VSSP160 /TO21 P161 /TO22 P162 /TO23 P163 /TO24 P164 /TO25 P165 /TO26 P166 /TO27 P167 /TO28 P172 /TIN24 P173 /TIN25 P174 /TXD2 P175 /RXD2 P176 /TXD3 P177 /RXD3 VCCE VSS P82 /TXD0 P87 /SCLK1 P84 /SCLK0 P85 /TXD1 P86 /RXD1 TRDATA TRDATA TRDATA TRDATA P200 /TXD4 P201 /RXD4 P202 /TXD5 P203 /RXD5 VCCI VSS P83 /RXD0 VSS P61 P62 FVCC P64 /SBI P65 /SCLK4 P66 /SCLK5 P63 VCCI VSS VCCE P67 /ADTRG P71 /WAIT P72 /HREQ P73 /HACK P74/ RTDTXD P75/ RTDRXD P76/ RTDACK P77/ RTDCLK P93 /TO16 P94 /TO17 P95 /TO18 P96 /TO19 P97 /TO20 RESET MOD0 MOD1 FP VCCE VSS P110 /TO0 P111 /TO1 P112 /TO2 P113 /TO3 TRDATA TRDATA TRDATA TRDATA P114 /TO4 P115 /TO5 P116 /TO6 P117 /TO7 P100 /TO8 P101 /TO9 P102 /TO10 VDD VCCI VSS P210 /TO37 P211 /TO38 P212 /TO39 P214 /TO41 P215 /TO42 P213 /TO40 P216 /TO43 P217 /TO44 JDBI JTCK JEVENT JTRSTJEVENT

1 JTDO

/TO11 P104 /TO12 P105 /TO13 P106 /TO14 P107 /TO15 P124 /TCLK0 P125 /TCLK1 P126 /TCLK2 P127 /TCLK3VCCI VSS P130 /TIN16 P131 /TIN17 P132 /TIN18 P133 /TIN19 P134 /TIN20 P135 /TIN21 P136 /TIN22 P137 /TIN23 VCCEVSSP140 /TIN8 P141 /TIN9 P142 /TIN10 P143 /TIN11 P144 /TIN12 P145 /TIN13 P146 /TIN14 P147 /TIN15 P150 /TIN0 P151 /TIN1 P152 /TIN2 P153 /TIN3 P154 /TIN4 P155 /TIN5 P156 /TIN6 P157 /TIN7 P41 /BLW P42 /BHW VCCIVSSVREF1 AVCC1 AD1IN0AD1IN1AD1IN2 AD1IN3 AD1IN4 AD1IN5AD1IN6 AD1IN7 AD1IN8 AD1IN10 AD1IN9 AD1IN11 M32170F3VWG M32170F4VWG M32170F6VWG M32174F4VWG M32174F3VWG P70 /BCLK JTMS N.C. N.C. OVERVIEW

1-23 32170/32174 Group User's Manual (Rev. 2.1) Table 1.4.2 Pin Assignments of the 255FBGA (1/2) No. Pin Name No. Pin Name No. Pin Name No. Pin Name A1 — C1 AD1IN14 E1 P220 / CTX H1 VCNT A2 AD1IN9 C2 AD1IN13 E2 P47 / A14 H2 VSS A3 AD1IN8 C3 AD1IN4 E3 ___ P46 / A13 H3 OSC-VCC A4 AD1IN6 C4 AD1IN5 E4 ___ P45 / CS1 H4 XOUT A5 AD1IN2 C5 AD1IN1 E17 P101 / TO9 H17 P111 / TO1 A6 VREF1 C6 VSS E18 VCCI H18 TRDATA4 P41 / BLW C7 P157 / TIN7 E19 VDD H19 P113 / TO3 A8 P154 / TIN4 C8 P153 / TIN3 E20 P102 / TO10 H20 P112 / TO2 A9 P150 / TIN0 C9 P147 / TIN15 F1 P224 / A11 J1 P32 / A17 A10 P144 / TIN12 C10 P143 / TIN11 F2 P223 J2 P31 / A16 A11 P140 / TIN8 C11 P141 / TIN9 F3 P222 J3 P30 / A15 A12 P136 / TIN22 C12 P137 / TIN23 F4 P221 / CRX J4 VSS A13 P132 / TIN18 C13 P133 / TIN19 F17 P115 / TO5 J17 FP A14 VCCI C14 VSS F18 P100 / TO8 J18 P110 / TO0 A15 P124 / TCLK0 C15 P125 / TCLK1 F19 P117 / TO7 J19 VSS A16 P104 / TO12 C16 P105 / TO13 F20 P116 / TO6 J20 VCCE A17 JEVENT1 C17 JTDO G1 XIN K1 TRCLK A18 JEVENT0 C18 P213 / TO40 G2 OSC-VSS K2 P35 / A20 A19 JTCK C19 P215 / TO42 G3 VSS K3 P34 / A19 A20 JTMS C20 P214 / TO41 G4 P225 / A12 K4 P33 / A18 B1 AD1IN12 D1 P44 / CS0 G17 TRDATA5 K17 P97 / TO20 B2 AD1IN11 D2 P43 / RD G18 P114 / TO4 K18 MOD1 B3 AD1IN10 D3 AVSS1 G19 TRDATA7 K19 MOD0 B4 AD1IN7 D4 AD1IN15 G20 TRDATA6 K20 RESET B5 AD1IN3 D5 AD1IN0 B6 AVCC1 D6 VCCI P42 / BHW D7 P156 / TIN6 B8 P155 / TIN5 D8 P152 / TIN2 B9 P151 / TIN1 D9 P146 / TIN14 B10 P145 / TIN13 D10 P142 / TIN10 B11 VSS D11 VCCE B12 P135 / TIN21 D12 P134 / TIN20 B13 P131 / TIN17 D13 P130 / TIN16 B14 P127 / TCLK3 D14 P126 / TCLK2 B15 P107 / TO15 D15 P106 / TO14 B16 P103 / TO11 D16 JTDI B17 JTRST D17 VSS B18 JDBI D18 P212 / TO39 B19 P217 / TO44 D19 P211 / TO38 B20 P216 / TO43 D20 P210 / TO37 OVERVIEW

1-24 32170/32174 Group User's Manual (Rev. 2.1) Table 1.4.2 Pin Assignments of the 255FBGA (2/2) No. Pin Name No. Pin Name No. Pin Name No. Pin Name L1 P36 / A21 P1 P00 / DB0 U1 P12 / DB10 W1 P16 / DB14 L2 P37 / A22 P2 P01 / DB1 U2 P13 / DB11 W2 VREF0 L3 P20 / A23 P3 P02 / DB2 U3 P14 / DB12 W3 AD0IN0 L4 TRSYNC P4 P27 / A30 U4 P11 / DB9 W4 AD0IN3 L17 P93 / TO16 P17 P67 / ADTRG U5 AD0IN6 W5 AD0IN7 L18 P94 / TO17 P18 VCCI U6 AD0IN10 W6 AD0IN11 L19 P95 / TO18 P19 VSS U7 AD0IN14 W7 AD0IN15 L20 P96 / TO19 P20 VCCE U8 VSS W8 P180 / TO29 M1 P22 / A25 R1 P04 / DB4 U9 P183 / TO32 W9 P184 / TO33 M2 P23 / A26 R2 P05 / DB5 U10 P187 / TO36 W10 P190 / TIN26 M3 VCCE R3 P06 / DB6 U11 P193 / TIN29 W11 P196 / TIN32 M4 P21 / A24 R4 P03 / DB3 U12 P197 / TIN33 W12 P160 / TO21 M17 P74 / RTDTXD R17 P63 U13 P161 / TO22 W13 P164 / TO25 M18 P75 / RTDRXD R18 ___ P64 / SBI U14 P165 / TO26 W14 P172 / TIN24 M19 P76 / RTDACK R19 P65 / SCLK4 U15 P173 / TIN25 W15 P176 / TXD3 M20 P77 / RTDCLK R20 P66 / SCLK5 U16 P177 / RXD3 W16 P82 / TXD0 N1 P24 / A27 T1 VCCE U17 P83 / RXD0 W17 P86 / RXD1 N2 P25 / A28 T2 VSS U18 P203 / RXD5 W18 TRDATA2 N3 P26 / A29 T3 P10 / DB8 U19 VCCI W19 N.C. N4 VSS T4 P07 / DB7 U20 VSS W20 P201 / RXD4 N17 P70 / BCLK T17 FVCC V1 P15 / DB13 Y1 N.C. N18 P71 / WAIT T18 VSS V2 P17 / DB15 Y2 AVCC0 N19 P72 / HREQ T19 P61 V3 AD0IN1 Y3 AD0IN2 N20 P73 / HACK T20 P62 V4 AD0IN5 Y4 AD0IN4 V5 AD0IN9 Y5 AD0IN8 V6 AD0IN13 Y6 AD0IN12 V7 VCCE Y7 AVSS0 V8 P182 / TO31 Y8 P181 / TO30 V9 P186 / TO35 Y9 P185 / TO34 V10 P192 / TIN28 Y10 P191 / TIN27 V11 P194 / TIN30 Y11 P195 / TIN31 V12 VCCI Y12 VSS V13 P162 / TO23 Y13 P163 / TO24 V14 P166 / TO27 Y14 P167 / TO28 V15 P174 / TXD2 Y15 P175 / RXD2 V16 VCCE Y16 VSS V17 P84 / SCLK0 Y17 P85 / TXD1 V18 P87 / SCLK1 Y18 TRDATA0 V19 P200 / TXD4 Y19 TRDATA1 V20 P202 / TXD5 Y20 TRDATA3 OVERVIEW

2.1 CPU Registers

2.2 General-purpose Registers

2.3 Control Registers

2.4 Accumulator

2.5 Program Counter

2.6 Data Formats

2.7 Precautions on CPU

2-2 32170/32174 Group User's Manual (Rev. 2.1) CPU The M32R has sixteen general-purpose registers, five control registers, an accumulator, and a program counter. The accumulator is a 56-bit configuration, and all other registers are a 32-bit configuration. General-purpose registers are 32 bits in width and there are sixteen of them (R0 to R15), which are used to hold data and base addresses. Especially, R14 is used as a link register, and R15 is used as a stack pointer. The link register is used to store the return address when executing a subroutine call instruction. The stack pointer is switched between an interrupt stack pointer (SPI) and a user stack pointer (SPU) depending on the value of the Processor Status Word register (PSW)'s stack mode (SM) bit. 31 3100 R10 R11 R12 R13 R14 (Link register) R15 (Stack pointer) (Note) Note: The stack pointer is switched between an interrupt stack pointer (SPI) and a user stack pointer (SPU) depending on the value of the PSW's SM bit. Figure 2.2.1 General-purpose Registers

2-3 32170/32174 Group User's Manual (Rev. 2.1) CPU There are five control registers-Processor Status Word Register (PSW), Condition Bit Register (CBR), Interrupt Stack Pointer (SPI), User Stack Pointer (SPU), and Backup PC (BPC). Dedicated "MVTC" and "MVFC" instructions are used to set and read these control registers. Figure 2.3.1 Control Registers Control Registers CR0 CR1 CR2 CR3 0 31 PSW CBR SPI SPU Processor status Word Register Condition Bit Register Interrupt Stack Pointer User Stack Pointer BPCCR6 Backup PC CRn Note 1: CRn (n = 0-3, 6) denotes control register numbers. Note 2: Dedicated "MVTC" and "MVFC" instructions are used to set and read the control registers.

2-4 32170/32174 Group User's Manual (Rev. 2.1) CPU

2.3.1 Processor Status Word Register: PSW (CR0)

The Processor Status Word Register (PSW) is used to indicate the status of the M32R. It consists of a regularly used PSW field and a special BPSW field which is used to save the PSW field when an EIT occurs. The PSW field consists of several bits labeled Stack Mode (SM), Interrupt Enable (IE), and Condition bit (C). The BPSW field consists of backup bits of the foregoing, i.e., Backup SM bit (BSM), Backup IE bit (BIE), and Backup C bit (BC). D Bit Name Function Initial R W

16 BSM (Backup SM) Holds the value of SM bit when EIT Indeterminate

is accepted.

17 BIE (Backup IE) Holds the value of IE bit when EIT Indeterminate

is accepted.

23 BC (Backup C) Holds the value of C bit when EIT Indeterminate

is accepted. 24 SM (Stack Mode) 0: Interrupt stack pointer is used. 0 1: User stack pointer is used. 25 IE (Interrupt Enable) 0: No interrupt is accepted. 0 1: Interrupt is accepted.

31 C (Condition bit) Depending on instruction execution, it indicates0

whether operation resulted in a carry, borrow, or overflow. Note 1: "Initial" shows the state immediately after reset, R = O means the register is readable, W = O means the register is writable. Note 2: For changes of the state of each bit when an EIT event occurs, refer to Chapter 4, "EIT.” (Note 1) 16 17 23 24 25 31(LSB)15870(MSB) SM IE CBCBSM BIE 00000000000000000000000000PSW BPSW field PSW field

2-5 32170/32174 Group User's Manual (Rev. 2.1) CPU

2.3.2 Condition Bit Register: CBR (CR1)

The Condition Bit Register (CBR) is created as a separate register from the PSW by extracting the Condition bit (C) from it. The value written to the PSW C bit is reflected in this register. This register is a read-only register (writes to this register by "MVTC" instruction are ignored).

2.3.3 Interrupt Stack Pointer: SPI (CR2)

User Stack Pointer: SPU (CR3) The Interrupt Stack Pointer (SPI) and User Stack Pointer (SPU) hold the current address of the stack pointer. These registers can be accessed as general-purpose register R15. In this case, whether R15 is used as SPI or as SPU depends on the PSW's Stack Mode (SM) bit.

2.3.4 Backup PC: BPC (CR6)

The Backup PC (BPC) is a register used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31 is fixed to 0. When an EIT occurs, the value held in the PC immediately before the EIT occurred or the value of the next instruction is set in this register. When the "RTE" instruction is executed, the saved value is returned from the BPC to the PC. However, the two low-order bits of the PC when thus returned are always fixed to "00" (control always returns to word boundaries.) SPI SPI SPU SPU 0(MSB) 0(MSB) 31(LSB) 31(LSB) CBR 0(MSB) 31(LSB) 00 00 00 00 00 0 00 0000 0000 0 0 0 00 000 0 0 C BPC BPC 0 31(LSB)0(MSB)

2-6 32170/32174 Group User's Manual (Rev. 2.1) The accumulator (ACC) is a 56-bit register used by DSP function instructions. When read out or written to, it is handled as a 64-bit register. When reading, the value of bit 8 is sign-extended. When writing, bits 0--7 are ignored. Also, the accumulator is used by the multiplication instruction "MUL." Note that when executing this instruction, the value of the accumulator is destroyed. The "MVTACHI" and "MVTACLO" instructions are used to write to the accumulator. The "MVTACHI" instruction writes data to the 32 high-order bits (bits 0-31), and the "MVTACLO" instruction writes data to the 32 low-order bits (bits 32-63). The "MVFACHI," "MVFACLO," and "MVFACMI" instructions are used to read data from the accumulator. The "MVFACHI" instruction reads data from the 32 high-order bits (bits 0-31), the "MVFACLO" instruction reads data from the 32 low-order bits (bits 32-63), and the "MVFACHI" instruction reads data from the 32 middle bits (bits 16-47). CPU Note: Bits 0-7 always show the sign-extended value of bit 8. Writes to this bit field are ignored. PC PC 0 31(LSB)0(MSB) The Program Counter (PC) is a 32-bit counter used to hold the address of the currently executed instruction. Because M32R instructions each start from an even address, the LSB (bit 31) is always 32 48 63(LSB)3116150(MSB) 4778 Range of bits read by MVFACMI instruction Range of bits read/written to by MVFACHI/MVTACHI instructions Range of bits read/written to by MVFACLO/MVTACLO instructions ACC (Note)

2-7 32170/32174 Group User's Manual (Rev. 2.1)

2.6.1 Data Types

There are several data types that can be handled by the M32R's instruction set. These include signed and unsigned 8, 16, and 32-bit integers. Values of signed integers are represented by 2's complements. Figure 2.6.1 Data Types CPU Signed byte (8-bit) integer Unsigned byte (8-bit) integer Signed halfword (16-bit) integer Unsigned halfword (16-bit) integer Signed word (32-bit) integer Unsigned word (32-bit) integer 0(MSB) 0(MSB) 0(MSB) 0(MSB) 0(MSB) 0(MSB) 7(LSB) 7(LSB) 15(LSB) 15(LSB) 31(LSB) 31(LSB) S S S S : Sign bit

2-8 32170/32174 Group User's Manual (Rev. 2.1) CPU

2.6.2 Data Formats

(1) Data formats in register Data sizes in M32R registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign- extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) into word (32-bit) data before being stored in the register. When storing data from M32R register into memory, the register data is stored in memory in different sizes depending on the instructions used. The ST instruction stores the entire 32-bit data of the register, the STH instruction stores the least significant 16-bit data, and the STB instruction stores the least significant 8-bit data. Figure 2.6.2 Data Formats in Register Rn 0(MSB) 31(LSB) <When loading> Byte Rn 0(MSB) 31(LSB) Halfword Rn 0(MSB) 31(LSB) Word Sign-extended (LDB instruction) or zero-extended (LDUB instruction) From memory (LDB, LDUB instructions) <When storing> Rn 0(MSB) 31(LSB) Byte Rn 0(MSB) 31(LSB) Halfword Rn 0(MSB) 31(LSB) Word To memory (STB instruction) To memory (STH instruction) To memory (ST instruction) From memory (LDH, LDUH instructions) From memory (LD instructions) Sign-extended (LDH instruction) or zero-extended (LDUH instruction)

2-9 32170/32174 Group User's Manual (Rev. 2.1) (2) Data formats in memory Data sizes in memory are either byte (8 bits), halfword (16 bits), or word (32 bits). Byte data can be located at any address. However, halfword data must be located at halfword boundaries (where the LSB address bit = "0"), and word data must be located at word boundaries (where two LSB address bits = "00"). If an attempt is made to access memory data across these halfword or word boundaries, an address exception is generated. Figure 2.6.3 Data Formats in Memory CPU + 0 address + 1 address + 2 address + 3 address 03 1 Byte 7 8 15 16 23 24 (MSB) (LSB) (MSB) (LSB) Byte Byte Byte Halfword Halfword Word

2-10 32170/32174 Group User's Manual (Rev. 2.1) CPU (3) Endian The following shows the generally used endian methods and the M32R family endian. Figure 2.6.4 Endian Methods Figure 2.6.5 M32R Family Endian Bit endian Byte endian Big endian Little endian Note: Even for bit big endian, H'01 is not B'10000000. MSB LSB HH HL LH LL H'01 H'23 H'45 H'67 MSB LSB LL LH HL HH H'67 H'45 H'23 H'01 MSB LSB B'0000001 D0 D7 MSB LSB B'0000001 D7 D0 Little/Little LL LH HL HH Big/Big HH HL LH LL Little/Big HH HL LH LL Endian (Bit/Byte) Data arrangement MPU name 7700 family M16C family Competition M32R family M16 family 7-031-24 15-823-16 0-7 24-31 8-15 16-23Bit number MSB LSB MSB LSB MSB LSB Ex:0x01234567 .byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67 Note: The M32R's endian method is big endian for both bit and byte. 7-031-24 15-823-16

2-11 32170/32174 Group User's Manual (Rev. 2.1) (4) Transfer instructions Figure 2.6.6 Transfer instructions CPU

• Constant transfer LD24 Rdest, #imm24 LDI Rdest, #imm16 LDI Rdest, #imm8 SETH Rdest, #imm16 230 Rdest imm24 310 LD24 Rdest, #imm24 150 Rdest imm16 310 SETH Rdest, #imm16 00 00
• Register to register transfer MV Rdest, Rsrc
• Control register transfer MVFC Rdest, CRsrc MVTC Rsrc, CRdest Note: For the MVTC instruction, the condition bit C does not change unless CRdest is CR0 (PSW). Rsrc 310 Rdest 310 Rsrc 310 CRdest 310 MVTC Rsrc, CRdest MV Rdest, Rsrc

2-12 32170/32174 Group User's Manual (Rev. 2.1) (5) Memory (signed) to register transfer Figure 2.6.7 Memory (signed) to register transfer (6) Memory (unsigned) to register transfer Figure 2.6.8 Memory (unsigned) to register transfer

• Signed 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc
• Signed 16 bits LD24 Rsrc, #label LDH Rdest, @Rsrc
• Signed 8 bits LD24 Rsrc, #label LDB Rdest, @Rsrc label Rdest 310+0 +1 +2 +3 Rdestlabel 00 00 FF FF Check the MSB 0 = positive 1 = negative 310 +0 +1 +2 +3 Rdestlabel 00 00 00 FF FF FF 310 +0 +1 +2 +3 Memory Register Check the MSB 0 = positive 1 = negative
• Unsigned 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc
• Unsigned 16 bits LD24 Rsrc, #label LDUB Rdest, @Rsrc
• Unsigned 8 bits LD24 Rsrc, #label LDUH Rdest, @Rsrc Rdest 00 00 310 label +0 +1 +2 +3 label +0 +1 +2 +3 Rdest 310 label +0 +1 +2 +3 Rdest 00 00 00 310 Memory Register CPU

2-13 32170/32174 Group User's Manual (Rev. 2.1) (7) Things to be noted for data transfer Note that in data transfer, data arrangements in registers and those in memory are different. Figure 2.6.9 Difference in Data Arrangements Data in memoryData in register Word data (32 bits) +0 +1 +2 +3 D0 D31 HH HL LH LL D0 D31 HH HL LH LL Half-word data (16 bits) +0 +1 +2 +3 D0 D31 H L D0 D15 H L Byte data (8 bits) +0 +1 +2 +3 D0 D31 D0 D7 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB (R0-R15) (R0-R15) (R0-R15) CPU

2-14 32170/32174 Group User's Manual (Rev. 2.1) CPU

• Usage Notes for 0 Division Instruction Problem and Conditions Inaccurate calculations for the instructions listed in (2) will result from execution of the 0 division instruction under the conditions described in (1). (1) If 0 division calculation is executed when the divisor = 0 for instructions DIV, DIVU, REM and REMU, (2) the result will be inaccurate calculations for any of the following instructions that are executed immediately after 0 division: ADDV, ADDX, ADD, ADDI, ADDV3, ADD3, CMP, CMPU, CMPI, CMPUI, SUBV, SUBX, SUB, DIV, DIVU, REM, REMU. Countermeasure Assuming that the 0 division occurrence itself is not expected by the system and therefore is the cause of miscalculations, before executing division or remainder instructions, do a 0 check on the divisor to make sure 0 division does not occur.

3.1 Outline of Address Space

3.2 Operation Modes

3.3 Internal ROM Area and Extended

3.4 Internal RAM Area and SFR

3.5 EIT Vector Entry

3.6 ICU Vector Table

3.7 Notes on Address Space

3-2 32170/32174 Group User's Manual (Rev. 2.1) The M32R's logical addresses are always handled in 32 bits, providing 4 Gbytes of linear ad- dress space. The M32R/ECU's address space consists of the following: (1) User space

• Internal ROM area
• Extended external area
• Internal RAM area
• Special Function Register (SFR) area (2) Boot program space (3) System space (areas not open to the user) (1) User space A 2 Gbytes of address space from H'0000 0000 to H'7FFF FFFF is the user space. Located in this space are the internal ROM area, extended external area, internal RAM area, and Spe- cial Function Register (SFR) area, an area containing a group of internal peripheral I/O regis- ters. Of these, the internal ROM and extended external areas are located differently depend- ing on mode settings which will be described later. (2) Boot program space A 1 Gbyte of address space from H'8000 0000 to H'BFFF FFFF is the boot program space. This space stores a program (boot program) which enables on-board programming when the internal flash area is blank. (3) System space A 1 Gbyte of address space from H'C000 0000 to H'FFFF FFFF is the system space. This space is reserved for use by development tools such as an in-circuit emulator or a debug monitor, and cannot be used by the user. ADDRESS SPACE

3-3 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.1.1 Address Space of the M32170F6 Note 1: This location varies with chip mode settings. Note 2: The boot program space can read out only when FP = 1, MOD0 = 1, and MOD1 = 0. BOOT ROM area (8 Kbytes) H'0000 0000 H'FFFF FFFF <Logical address space of M32170F6> H'7FFF FFFF H'8000 0000 User space EIT vector entry Logical address H'BFFF FFFF H'C000 0000 Boot program space System space (16 Mbytes) H'0000 0000 H'00FF FFFF H'007F FFFF H'0080 0000SFR area (16 Kbytes) H'0080 3FFF H'0080 4000 H'001F FFFF H'0020 0000 H'003F FFFF H'0040 0000 Internal ROM area (768 Kbytes) (Note 1) Extended external area (4 Mbytes) Ghost area in units of 128 Kbytes

1 Gbyte

2 Gbytes

16 Mbytes

4 Mbytes

(40 Kbytes) H'0080 DFFF H'8000 0000 H'8000 1FFF Ghost area in units of (8 Kbytes) Reserved area (72 Kbytes) H'0081 FFFF H'0082 0000 H'0080 E000 H'8000 3FFF H'8000 2000 H'8000 4000 H'BFFF FFFF H'000B FFFF H'0010 0000 CS1 area CS0 area Reserved area (256 Kbytes) H'000F FFFF

3-4 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.1.2 Address Space of the M32170F4 BOOT ROM area (8 Kbytes) H'0000 0000 H'FFFF FFFF <Logical address space of M32170F4> H'7FFF FFFF H'8000 0000 User space EIT vector entry Logical address H'BFFF FFFF H'C000 0000 Boot program space System space (16 Mbytes) H'0000 0000 H'00FF FFFF H'007F FFFF H'0080 0000SFR area (16 Kbytes) H'0080 3FFF H'0080 4000 H'001F FFFF H'0020 0000 H'003F FFFF H'0040 0000 Internal ROM area (512 Kbytes) (Note 1) Extended external area (4 Mbytes) Ghost area in units of 128 Kbytes (32 Kbytes) H'0080 BFFF H'8000 0000 H'8000 1FFF Ghost area in units of (8 Kbytes) Reserved area (80 Kbytes) H'0081 FFFF H'0082 0000 H'0080 C000 H'8000 3FFF H'8000 2000 H'8000 4000 H'BFFF FFFF H'0007 FFFF H'0010 0000 CS1 area CS0 area Reserved area (512 Kbytes) H'000F FFFF Note 1: This location varies with chip mode settings. Note 2: The boot program space can read out only when FP = 1, MOD0 = 1, and MOD1 = 0.

3-5 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.1.3 Address Space of the M32170F3 BOOT ROM area (8 Kbytes) H'0000 0000 H'FFFF FFFF <Logical address space of M32170F3> H'7FFF FFFF H'8000 0000 User space EIT vector entry Logical address H'BFFF FFFF H'C000 0000 Boot program space System space (16 Mbytes) H'0000 0000 H'00FF FFFF H'007F FFFF H'0080 0000SFR area (16 Kbytes) H'0080 3FFF H'0080 4000 H'001F FFFF H'0020 0000 H'003F FFFF H'0040 0000 Internal ROM area (384 Kbytes) (Note 1) Extended external area (4 Mbytes) Ghost area in units of 128 Kbytes (32 Kbytes) H'0080 BFFF H'8000 0000 H'8000 1FFF Ghost area in units of (8 Kbytes) Reserved area (80 Kbytes) H'0081 FFFF H'0082 0000 H'0080 C000 H'8000 3FFF H'8000 2000 H'8000 4000 H'BFFF FFFF H'0005 FFFF H'0010 0000 CS1 area CS0 area Reserved area (640 Kbytes) H'000F FFFF Note 1: This location varies with chip mode settings. Note 2: The boot program space can read out only when FP = 1, MOD0 = 1, and MOD1 = 0.

3-6 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.1.4 Address Space of the M32174F4 Note 1: This location varies with chip mode settings. Note 2: The boot program space can read out only when FP = 1, MOD0 = 1, and MOD1 = 0. BOOT ROM area (8 Kbytes) H ’0000 0000 H ’FFFF FFFF <Logical address space of M32174F4> H ’7FFF FFFF H ’8000 0000 User space EIT vector entry Logical address H ’BFFF FFFF H ’C000 0000 Boot program space System space (16 Mbytes) H ’0000 0000 H ’00FF FFFF H ’007F FFFF H ’0080 0000SFR area (16 Kbytes) H ’0080 3FFF H ’0080 4000 H ’001F FFFF H ’0020 0000 H ’003F FFFF H ’0040 0000 Internal ROM area (512 Kbytes) (Note 1) Extended external area (4 Mbytes) Ghost area in units of 128 Kbytes (40 Kbytes) H ’0080 BFFF H ’8000 0000 H ’8000 1FFF Ghost area in units of (8 Kbytes) Reserved area (72 Kbytes) H ’0081 FFFF H ’0082 0000 H ’0080 C000 H ’8000 3FFF H ’8000 2000 H ’8000 4000 H ’BFFF FFFF H ’0007 FFFF H ’0010 0000 CS1 area CS0 area Reserved area (512 Kbytes) H ’000F FFFF

3-7 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.1.5 Address Space of the M32174F3 Note 1: This location varies with chip mode settings. Note 2: The boot program space can read out only when FP = 1, MOD0 = 1, and MOD1 = 0. BOOT ROM area (8 Kbytes) H ’0000 0000 H ’FFFF FFFF <Logical address space of M32174F3> H ’7FFF FFFF H ’8000 0000 User space EIT vector entry Logical address H ’BFFF FFFF H ’C000 0000 Boot program space System space (16 Mbytes) H ’0000 0000 H ’00FF FFFF H ’007F FFFF H ’0080 0000SFR area (16 Kbytes) H ’0080 3FFF H ’0080 4000 H ’001F FFFF H ’0020 0000 H ’003F FFFF H ’0040 0000 Internal ROM area (384 Kbytes) (Note 1) Extended external area (4 Mbytes) Ghost area in units of 128 Kbytes (40 Kbytes) H ’0080 BFFF H ’8000 0000 H ’8000 1FFF Ghost area in units of (8 Kbytes) Reserved area (72 Kbytes) H ’0081 FFFF H ’0082 0000 H ’0080 C000 H ’8000 3FFF H ’8000 2000 H ’8000 4000 H ’BFFF FFFF H ’0005 FFFF H ’0010 0000 CS1 area CS0 area Reserved area (640 Kbytes) H ’000F FFFF

3-8 32170/32174 Group User's Manual (Rev. 2.1) This microcomputer is placed in one of the following modes by setting its operation mode (using MOD0 and MOD1 pins). For details about the mode used to rewrite the internal flash memory, refer to Section 6.5, "Programming of Internal Flash Memory." Table 3.2.1 Setting Operation Modes MOD0 MOD1 (Note 1) Operation Mode (Note 2) VSS VSS Single-chip mode VSS VCCE Extended external mode VCCE VSS Processor mode (FP = VSS) VCCE VCCE Reserved (cannot be used) Note 1: VCCE connects to +5 V or 3.3V, and VSS connects to GND. Note 2: For flash rewrite mode (FP = VCCE) not listed in the above table, refer to Section 6.5, "Programming of Internal Flash Memory." The internal ROM and extended external areas are located differently depending on this microcomputer's operation mode. (All other areas in address space are located the same way.) The address maps of internal ROM and extended external areas in each mode are shown below. (For details about internal flash memory rewrite mode, refer to Section 6.5, "Programming of Internal Flash Memory.") ADDRESS SPACE Figure 3.2.1 M32170F6 Operation Mode and Internal ROM/Extended External Areas H'0000 0000 H'000B FFFF H'000C 0000 H'003F FFFF Non-CS0 area <Single-chip mode> <Processor mode> CS1 area (2 Mbytes) CS0 area (2 Mbytes) CS1 area (2 Mbytes) <Extended external mode> Internal ROM area (768 Kbytes) Extended external area Extended external area Internal ROM area (768 Kbytes) H'000F FFFF H'0010 0000 H'001F FFFF H'0020 0000 CS0 area (1 Mbyte) Reserved area (256 Kbytes)

3-9 32170/32174 Group User's Manual (Rev. 2.1) Figure 3.2.2 M32170F4 and M32174F4 Operation Mode and Internal ROM/Extended External Areas Figure 3.2.3 M32170F3 and M32174F3 Operation Mode and Internal ROM/Extended External Areas H'0000 0000 H'0007 FFFF H'0008 0000 H'003F FFFF Non-CS0 area <Single-chip mode> <Processor mode> CS1 area (2 Mbytes) CS0 area (2 Mbytes) CS1 area (2 Mbytes) <Extended external mode> Internal ROM area (512 Kbytes) Extended external area Extended external area Internal ROM area (512 Kbytes) H'000F FFFF H'0010 0000 H'001F FFFF H'0020 0000 CS0 area (1 Mbyte) Reserved area (512 Kbytes) H'0000 0000 H'0005 FFFF H'0006 0000 H'003F FFFF Non-CS0 area <Single-chip mode> <Processor mode> CS1 area (2 Mbytes) CS0 area (2 Mbytes) CS1 area (2 Mbytes) <Extended external mode> Internal ROM area (384 Kbytes) Extended external area Extended external area Internal ROM area (384 Kbytes) H'000F FFFF H'0010 0000 H'001F FFFF H'0020 0000 CS0 area (1 Mbyte) Reserved area (640 Kbytes) ADDRESS SPACE

3-10 32170/32174 Group User's Manual (Rev. 2.1)

3.3 Internal ROM Area and Extended External Area

The 8 Mbyte area at addresses H'0000 0000 to H'007F FFFF in the user space accommodates the internal ROM and extended external areas. Of this, a 4 Mbytes of address space from H'0000 0000 to H'0003 FFFF is the area that the user can actually use. All other areas here comprise a 4 Mbytes of ghost area. (When programming, do not use this ghost area intentionally.) For details on how the internal ROM and extended external areas are located differently depending on this microcomputer's operation modes set, refer to Section 3.2, "Operation Modes."

3.3.1 Internal ROM Area

The internal ROM is located in the area shown below. Also, this area has an EIT vector entry (and ICU vector table) located in it at the beginning. Table 3.3.1 Addresses at Which the Internal ROM is Located Type Name Size Located address MF32170F6 768 Kbytes H'0000 0000 - H'000B FFFF MF32170F4, M32174F4 512 Kbytes H'0000 0000 - H'0007 FFFF MF32170F3, M32174F3 384 Kbytes H'0000 0000 - H'0005 FFFF

3.3.2 Extended External Area

An extended external area is provided only when extended external mode or processor mode has been selected when setting this microcomputer's operation mode. For access to this extended external area, this microcomputer outputs the control signals necessary to access external devices. This microcomputer's CS0 and CS1 signals are output corresponding to the address mapping of the extended external area. The CS0 signal is output for the CS0 area, and the CS1 signal is output for the CS1 area. Table 3.3.2 Address Mapping of the Extended External Area in Each Operation Mode Operation Mode Address mapping of the extended external area Single-chip mode None Extended external mode Addresses H'0010 0000 to H'001F FFFF (CS0 area: 1 Mbytes) Addresses H'0020 0000 to H'003F FFFF (CS1 area: 2 Mbytes) Processor mode Addresses H'0000 0000 to H'001F FFFF (CS0 area: 2 Mbytes) Addresses H'0020 0000 to H'003F FFFF (CS1 area: 2 Mbytes) ADDRESS SPACE

3.3 Internal ROM/Extended External Area

3-11 32170/32174 Group User's Manual (Rev. 2.1)

3.4 Internal RAM Area and SFR Area

The 8 Mbyte area at addresses H'0080 0000 to H'00FF FFFF in the user space accommodates the internal RAM area and Special Function Register (SFR) area. Of this, a 128 Kbytes of address space from H'0080 0000 to H'0081 FFFF is the area that the user can actually use. All other areas here comprise a ghost area in units of 128 Kbytes. (When programming, do not use this ghost area intentionally.)

3.4.1 Internal RAM Area

The internal RAM is located in the area shown below. Table 3.4.1 Addresses at Which the Internal ROM is Located Type Name Size Located address M32170F6 40 Kbytes H'0080 4000 - H'0080 DFFF M32174F4 M32174F3 M32170F4 32 Kbytes H'0080 4000 - H'0080 BFFF M32170F3

3.4.2 Special Function Register (SFR) Area

Addresses H'0080 0000 to H'0080 3FFFF are the Special Function Register (SFR) area. This area has registers for internal peripheral I/O located in it. ADDRESS SPACE

3.4 Internal ROM/SFR Area

Figure 3.4.1 Internal RAM Area and Special Function Register (SFR) Area of the M32170F6 H’0080 0000 H’0080 DFFF SFR area (16 Kbytes) Internal RAM (40 Kbytes) H’0080 3FFF H’0080 4000 Virtual-flash emulation areas separated in units of

8 Kbytes or 4 Kbytes can

be allocated here. For details, refer to Section 6.7.

3-12 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.2 Internal RAM Area and Special Function Register (SFR) Area of the M32170F4 and M32170F3 H’0080 0000 H’0080 BFFF SFR area (16 Kbytes) Internal RAM (32 Kbytes) H’0080 3FFF H’0080 4000 Virtual-flash emulation areas separated in units of be allocated here. For details, refer to Section 6.7. Figure 3.4.3 Internal RAM Area and Special Function Register (SFR) Area of the M32174F4 and M32174F3 H’0080 0000 H’0080 DFFF SFR area (16 Kbytes) Internal RAM (32 Kbytes) H’0080 3FFF H’0080 4000 H’0080 BFFF The low-order 8 Kbytes cannot be used for virtual-flash emulation. Virtual-flash emulation areas separated in units of be allocated here. For details, refer to Section 6.7.

3-13 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.4 Outline Address Mapping of the SFR Area H ’0080 0000 H ’0080 007E H ’0080 0180 Interrupt controller (ICU) H ’0080 0080 A-D0 converter H ’0080 00EE Serial I/O0-3 H ’0080 0100 H ’0080 0146 Wait controller MJT (common part) MJT (TOP) MJT (TIO) MJT (TMS) H ’0080 0200 H ’0080 0240 H ’0080 0300 H ’0080 03C0 H ’0080 03E0 H ’0080 03FE Note: The Real-time Debugger (RTD) is designed to be an independent module operated from an external source, and is transparent to the CPU. 0 7 8 15 H ’0080 0A00 +0 address +1 address 0 7 8 15 Multijunction timer (MJT) Flash control H ’0080 07E0 H ’0080 07F2 H ’0080 023E H ’0080 02FE MJT (TOD0) H ’0080 078C H ’0080 07DE MJT (TID0) H ’0080 0790 H ’0080 078E Multijunction timer (MJT) Serial I/O4, 5 H ’0080 0A26 H ’0080 0A80 A-D1 converter H ’0080 0AEE MJT (TOD1) MJT (TOM0) H ’0080 0BDE H ’0080 0C8C H ’0080 0CDE MJT (TML1) H ’0080 0FE0 H ’0080 0FFE H ’0080 0400 DMAC H ’0080 0478 CAN0 H ’0080 1000 H ’0080 11FE H ’0080 0700 Input/output port H ’0080 0756 H ’0080 03BE H ’0080 03D8 MJT (TML0) H ’0080 0B8C MJT (TID1)H ’0080 0B8E H ’0080 0B90 H ’0080 0C8E H ’0080 0C90 MJT (TID2) H ’0080 0760 H ’0080 3FFE +0 address +1 address Multijunction timer (MJT)

3-14 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.5 Register Mapping of the SFR Area (1) H ’0080 0000 H ’0080 0002 H ’0080 0004 H ’0080 0006 H ’0080 006C H ’0080 006E H ’0080 0070 H ’0080 0072 H ’0080 0074 H ’0080 0076 H ’0080 0078 H ’0080 007A H ’0080 007C H ’0080 007E H ’0080 0080 H ’0080 0082 H ’0080 0084 H ’0080 0086 H ’0080 0088 H ’0080 008A H ’0080 0090 +0 Address +1 Address Interrupt Vector Register (IVECT) D0 D7 D8 D15 Interrupt Mask Register (IMASK) SBI Control Register (SBICR) A-D0 Conversion Interrupt Control Register (IAD0CCR)SIO0 Transmit Interrupt Control Register (ISIO0TXCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) SIO1 Receive Interrupt Control Register (ISIO1RXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) DMA0-4 Interrupt Control Register (IDMA04CR) MJT Output Interrupt Control Register 0 (IMJTOCR0) MJT Output Interrupt Control Register 2 (IMJTOCR2) MJT Output Interrupt Control Register 4 (IMJTOCR4) MJT Output Interrupt Control Register 6 (IMJTOCR6) MJT Input Interrupt Control Register 0 (IMJTICR0) MJT Output Interrupt Control Register 1 (IMJTOCR1) MJT Output Interrupt Control Register 3 (IMJTOCR3) MJT Output Interrupt Control Register 5 (IMJTOCR5) MJT Output Interrupt Control Register 7 (IMJTOCR7) MJT Input Interrupt Control Register 1 (IMJTICR1) MJT Input Interrupt Control Register 2 (IMJTICR2) MJT Input Interrupt Control Register 3 (IMJTICR3) MJT Input Interrupt Control Register 4 (IMJTICR4) A-D0 Single Mode Register 0 (AD0SIM0) A-D0 Single Mode Register 1 (AD0SIM1) A-D0 Scan Mode Register 0 (AD0SCM0) A-D0 Scan Mode Register 1 (AD0SCM1) A-D0 Successive Approximation Register (AD0SAR) A-D0 Comparate Data Register (AD0CMP)H ’0080 008C H ’0080 0092 H ’0080 0094 10-bit A-D0 Data Register 0 (AD0DT0) 10-bit A-D0 Data Register 1 (AD0DT1) 10-bit A-D0 Data Register 2 (AD0DT2) 10-bit A-D0 Data Register 3 (AD0DT3) 10-bit A-D0 Data Register 4 (AD0DT4) 10-bit A-D0 Data Register 5 (AD0DT5) 10-bit A-D0 Data Register 6 (AD0DT6) 10-bit A-D0 Data Register 7 (AD0DT7) 10-bit A-D0 Data Register 8 (AD0DT8) 10-bit A-D0 Data Register 9 (AD0DT9) 10-bit A-D0 Data Register 10 (AD0DT10) 10-bit A-D0 Data Register 11 (AD0DT11) 10-bit A-D0 Data Register 12 (AD0DT12) 10-bit A-D0 Data Register 13 (AD0DT13) 10-bit A-D0 Data Register 14 (AD0DT14) 10-bit A-D0 Data Register 15 (AD0DT15) H ’0080 0096 H ’0080 0098 H ’0080 009A H ’0080 009C H ’0080 009E H ’0080 00A0 H ’0080 00A2 H ’0080 00A4 H ’0080 00A6 H ’0080 00A8 H ’0080 00AA H ’0080 00AC H ’0080 00AE H ’0080 00D0 Address H ’0080 0066 H ’0080 0068 H ’0080 006A RTD Interrupt Control Register (IRTDCR) SIO2,3 Transmit/Receive Interrupt Control Register (ISO23CR) DMA5-9 Interrupt Control Register (IDMA59CR) TOD0 Output Interrupt Control Register (ITOD0CR) TID0 Output Interrupt Control Register (ITID0CR) 8-bit A-D0 Data Register 0 (AD08DT0) H ’0080 0064 H ’0080 0062 H ’0080 0060 CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) TID2 Output Interrupt Control Register (ITID2CR) TML1 Input Interrupt Control Register (ITML1CR) A-D1 Conversion Interrupt Control Register (IAD1CCR) SIO4,5 Transmit/Receive Interrupt Control Register (ISIO45CR)TOD1-TOM0 Output Interrupt Control Register (ITOM0CR) TID1 Output Interrupt Control Register (ITID1CR) Blank addresses are reserved areas

3-15 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.6 Register Mapping of the SFR Area (2) H ’0080 00DA H ’0080 00DC H ’0080 00DE H ’0080 00E0 H ’0080 00E4 H ’0080 00E6 H ’0080 00E8 H ’0080 00EA H ’0080 00EC H ’0080 00EE H ’0080 0100 H ’0080 0102 H ’0080 0110 H ’0080 0112 H ’0080 0114 H ’0080 0116 H ’0080 0120 H ’0080 0126 +0 Address +1 Address D0 D7 D8 D15 H ’0080 0122 H ’0080 0130 SIO1 Baud Rate Register (S1BAUR) SIO0 Transmit Buffer Register (S0TXB) SIO0 Receive Buffer Register (S0RXB) SIO23 Interrupt Status Register (SI23STAT) 8-bit A-D0 Data Register 5 (AD08DT5) 8-bit A-D0 Data Register 6 (AD08DT6) 8-bit A-D0 Data Register 7 (AD08DT7) 8-bit A-D0 Data Register 8 (AD08DT8) 8-bit A-D0 Data Register 9 (AD08DT9) 8-bit A-D0 Data Register 10 (AD08DT10) 8-bit A-D0 Data Register 11 (AD08DT11) 8-bit A-D0 Data Register 12 (AD08DT12) 8-bit A-D0 Data Register 13 (AD08DT13) 8-bit A-D0 Data Register 14 (AD08DT14) 8-bit A-D0 Data Register 15 (AD08DT15) H ’0080 0132 H ’0080 0134 H ’0080 0136 H ’0080 0140 H ’0080 0142 H ’0080 0144 H ’0080 0146 H ’0080 0180 H ’0080 0200 H ’0080 0202 H ’0080 0210 H ’0080 0212 H ’0080 0214 Address H ’0080 00E2 SIO03 Interrupt Mask Register (SI03MASK) SIO03 Receive Interrupt Cause Select Register (SI03SEL) SIO0 Transmit Control Register (S0TCNT) SIO0 Transmit/Receive Mode Register (S0MOD) SIO0 Receive Control Register (S0RCNT) H ’0080 0124 SIO1 Baud Rate Register (S1BAUR) SIO1 Transmit Buffer Register (S1TXB) SIO1 Receive Buffer Register (S1RXB) SIO1 Transmit Control Register (S1TCNT) SIO0 Transmit/Receive Mode Register (S1MOD) SIO1 Receive Control Register (S1RCNT) SIO2 Baud Rate Register (S2BAUR) SIO2 Transmit Buffer Register (S2TXB) SIO2 Receive Buffer Register (S2RXB) SIO2 Transmit Control Register (S2TCNT) SIO2 Transmit/Receive Mode Register (S2MOD) SIO2 Receive Control Register (S2RCNT) SIO3 Baud Rate Register (S3BAUR) SIO3 Transmit Buffer Register (S3TXB) SIO3 Receive Buffer Register (S3RXB) SIO3 Transmit Control Register (S3TCNT) SIO3 Transmit/Receive Mode Register (S3MOD) SIO3 Receive Control Register (S3RCNT) Wait Cycles Control Register (WTCCR) H ’0080 0204 Clock Bus & Input Event Bus Control Register (CKIEBCR) Prescaler Register 0 (PRS0) Output Event Bus Control Register (OEBCR) Prescaler Register 1 (PRS1) Prescaler Register 2 (PRS2) TCLK Input Processing Control Register (TCLKCR) TIN Input Processing Control Register 0 (TINCR0) TIN Input Processing Control Register 1 (TINCR1) H ’0080 00D2 H ’0080 00D4 H ’0080 00D6 H ’0080 00D8 8-bit A-D0 Data Register 1 (AD08DT1) 8-bit A-D0 Data Register 2 (AD08DT2) 8-bit A-D0 Data Register 3 (AD08DT3) 8-bit A-D0 Data Register 4 (AD08DT4) Blank addresses are reserved areas.

3-16 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.7 Register Mapping of the SFR Area (3) +0 Address +1 Address D0 D7 D8 D15 H ’0080 021E F/F Source Select Register 0 (FFS0) F/F Source Select Register 1 (FFS1) F/F Protect Register 0 (FFP0) F/F Data Register 0 (FFD0) H ’0080 0220 H ’0080 0222 H ’0080 0224 H ’0080 0226 H ’0080 0228 H ’0080 022A F/F Protect Register 1 (FFP1) F/F Data Register 1 (FFD1) H ’0080 0230 H ’0080 0232 H ’0080 0234 H ’0080 0236 H ’0080 0238 H ’0080 023A H ’0080 023C H ’0080 023E H ’0080 0240 H ’0080 0242 H ’0080 0244 H ’0080 0246 H ’0080 0250 TOP Interrupt Control Register 0 (TOPIR0) TOP Interrupt Control Register 1 (TOPIR1) TOP Interrupt Control Register 2 (TOPIR2) TIO Interrupt Control Register 0 (TIOIR0) TIO Interrupt Control Register 2 (TIOIR2) TOP Interrupt Control Register 3 (TOPIR3) TIO Interrupt Control Register 1 (TIOIR1) TMS Interrupt Control Register (TMSIR) TIN Interrupt Control Register 0 (TINIR0) TIN Interrupt Control Register 2 (TINIR2) TIN Interrupt Control Register 4 (TINIR4) TIN Interrupt Control Register 6 (TINIR6) TIN Interrupt Control Register 1 (TINIR1) TIN Interrupt Control Register 3 (TINIR3) TIN Interrupt Control Register 5 (TINIR5) TOP0 Counter (TOP0CT) TOP0 Reload Register (TOP0RL) TOP0 Correction Register (TOP0CC) TOP1 Counter (TOP1CT) Address H ’0080 0252 H ’0080 0254 H ’0080 0260 H ’0080 0262 H ’0080 0264 H ’0080 0266 TOP1 Reload Register (TOP1RL) TOP1 Correction Register (TOP1CC)H ’0080 0256 TOP2 Counter (TOP2CT) TOP2 Reload Register (TOP2RL) TOP2 Correction Register (TOP2CC) TOP3 Counter (TOP3CT) TOP3 Reload Register (TOP3RL) TOP3 Correction Register (TOP3CC) H ’0080 0270 H ’0080 0272 H ’0080 0274 H ’0080 0276 H ’0080 0280 H ’0080 0282 H ’0080 0284 H ’0080 0286 TOP4 Counter (TOP4CT) TOP4 Reload Register (TOP4RL) TOP4 Correction Register (TOP4CC) TOP5 Counter (TOP5CT) TOP5 Reload Register (TOP5RL) H ’0080 0290 H ’0080 0292 H ’0080 0294 H ’0080 0216 H ’0080 021C H ’0080 0218 H ’0080 021A TIN Input Processing Control Register 2 (TINCR2) TIN Input Processing Control Register 3 (TINCR3) TIN Input Processing Control Register 4 (TINCR4) TIN Interrupt Control Register 7 (TINIR7) Blank addresses are reserved areas.

3-17 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.8 Register Mapping of the SFR Area (4) TOP5 Correction Register (TOP5CC) +0 Address +1 Address D0 D7 D8 D15 H ’0080 029E H ’0080 02A0 H ’0080 02A2 H ’0080 02A4 H ’0080 02A6 TOP6 Counter (TOP6CT) TOP6 Reload Register (TOP6RL) TOP6 Correction Register (TOP6CC) H ’0080 02B0 H ’0080 02B2 H ’0080 02B4 TOP7 Counter (TOP7CT) TOP7 Reload Register (TOP7RL) TOP7 Correction Register (TOP7CC) H ’0080 02C0 H ’0080 02C2 H ’0080 02C4 H ’0080 02C6 TOP8Counter (TOP8CT) TOP8 Reload Register (TOP8RL) TOP8 Correction Register (TOP8CC) H ’0080 02B6 H ’0080 02A8 H ’0080 02AA TOP6, 7 Control Register (TOP67CR) Address H ’0080 02D0 H ’0080 02D2 H ’0080 02D4 H ’0080 02D6 TOP9 Counter (TOP9CT) TOP9 Reload Register (TOP9RL) TOP9 Correction Register (TOP9CC) TOP10 Counter (TOP10CT) TOP10 Reload Register (TOP10RL) TOP10 Correction Register (TOP10CC) H ’0080 02E0 H ’0080 02E2 H ’0080 02E4 H ’0080 02E6 H ’0080 02E8 H ’0080 02EA TOP8-10 Control Register (TOP810CR) TOP0-10 External Enable Register (TOPEEN) TOP0-10 Enable Protect Register (TOPPRO) TOP0-10 Count Enable Register (TOPCEN) H ’0080 02FA H ’0080 02FC H ’0080 02FE H ’0080 0300 TIO0 Counter (TIO0CT) TIO0 Reload 1 Register (TIO0RL) TIO0 Reload 0/Measure Register (TIO0RL0) TIO1 Counter (TIO1CT) TIO1 Reload 1 Register (TIO1RL) TIO1 Reload 0/Measure Register (TIO1RL0) TIO0-3 Control Register 0 (TIO03CR0) H ’0080 0302 H ’0080 0304 H ’0080 0306 H ’0080 0310 H ’0080 0312 H ’0080 0314 H ’0080 0316 H ’0080 0318 H ’0080 031A TOP0-5 Control Register 0 (TOP05CR0) TOP0-5 Control Register 1 (TOP05CR1) H ’0080 0296 H ’0080 0298 H ’0080 029A H ’0080 029C Blank addresses are reserved areas.

3-18 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.9 Register Mapping of the SFR Area (5) +0 Address +1 Address D0 D7 D8 D15 H ’0080 0324 H ’0080 0326 TIO2 Reload 1 Register (TIO2RL1) TIO2 Reload 0/Measure Register (TIO2RL0) H ’0080 0330 H ’0080 0332 H ’0080 0334 H ’0080 0336 TIO3 Counter (TIO3CT) TIO3 Reload 1 Register (TIO3RL1) TIO3 Reload 0/Measure Register (TIO3RL0) H ’0080 0340 H ’0080 0342 H ’0080 0344 Address TIO4 Counter (TIO4CT) TIO4 Reload 1 Register (TIO4RL1) TIO4 Reload 0/Measure Register (TIO4RL0) TIO4 Control Register (TIO4CR) TIO5 Control Register (TIO5CR) TIO5 Counter (TIO5CT) TIO5 Reload 1 Register (TIO5RL1) TIO5 Reload 0/Measure Register (TIO5RL0) H ’0080 0346 H ’0080 0348 H ’0080 034A H ’0080 0350 H ’0080 0352 H ’0080 0354 H ’0080 0356 TIO6 Counter (TIO6CT) TIO6 Reload 1 Register (TIO6RL1) TIO6 Reload 0/Measure Register (TIO6RL0) TIO6 Control Register (TIO6CR) TIO7 Control Register (TIO7CR) H ’0080 0360 H ’0080 0362 H ’0080 0364 H ’0080 0366 H ’0080 0368 H ’0080 036A H ’0080 0370 H ’0080 0372 H ’0080 0374 H ’0080 0376 TIO7 Counter (TIO7CT) TIO7 Reload 1 Register (TIO7RL1) TIO7 Reload 0/Measure Register (TIO7RL0) H ’0080 0380 H ’0080 0382 H ’0080 0384 H ’0080 0386 H ’0080 0388 H ’0080 038A TIO8 Counter (TIO8CT) TIO8 Reload 1 Register (TIO8RL1) TIO8 Reload 0/Measure Register (TIO8RL0) TIO8 Control Register (TIO8CR) TIO9 Control Register (TIO9CR) H ’0080 0390 H ’0080 0392 H ’0080 0394 H ’0080 0396 TIO9 Counter (TIO9CT) TIO9 Reload 1 Register (TIO9RL1) TIO9 Reload 0/Measure Register (TIO9RL0) TIO0-3 Control Register 1 (TIO03CR1) TIO2 Counter (TIO2CT) H ’0080 031C H ’0080 0320 H ’0080 0322 Blank addresses are reserved areas.

3-19 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.10 Register Mapping of the SFR Area (6) D0 D7 D8 D15 TMS0 Counter (TMS0CT) TMS0 Measure 3 Register (TMS0MR3) TMS0 Measure 2 Register (TMS0MR2) TMS0 Measure 1 Register (TMS0MR1) H ’0080 03C0 H ’0080 03C2 H ’0080 03C4 H ’0080 03C6 TMS0 Measure 0 Register (TMS0MR0) TMS0 Control Register (TMS0CR) TMS1 Control Register (TMS1CR) TMS1 Counter (TMS1CT) TMS1 Measure 3 Register (TMS1MR3) TMS1 Measure 2 Register (TMS1MR2) TMS1 Measure 1 Register (TMS1MR1) TMS1 Measure 0 Register (TMS1MR0) H ’0080 03C8 H ’0080 03CA H ’0080 03D0 H ’0080 03D2 H ’0080 03D4 H ’0080 03D6 H ’0080 03D8 H ’0080 03E0 H ’0080 03E2 H ’0080 03EA H ’0080 03F0 H ’0080 03F2 H ’0080 03F4 H ’0080 03F6 H ’0080 03F8 H ’0080 03FA H ’0080 03FC TML0 Counter, High (TML0CTH) TML0 Counter, Low (TML0CTL) TML0 Measure 3 Register, High (TML0MR3H) TML0 Measure 3 Register, Low (TML0MR3L) TML0 Measure 2 Register, High (TML0MR2H) TML0 Measure 2 Register, Low (TML0MR2L) TML0 Measure 1 Register, High (TML0MR1H) TML0 Measure 1 Register, Low (TML0MR1L) TML0 Measure 0 Register, High (TML0MR0H) TML0 Control Register (TML0CR) H ’0080 03FE TML0 Measure 0 Register, Low (TML0MR0L) DMA0-4 Interrupt Mask Register (DM04ITMK) DMA0 Channel Control Register (DM0CNT) DMA0 Transfer Count Register (DM0TCT) DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA1 Channel Control Register (DM1CNT) DMA1 Transfer Count Register (DM1TCT) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) H ’0080 0412 H ’0080 0414 H ’0080 0416 H ’0080 0418 H ’0080 041A H ’0080 041C H ’0080 0410 H ’0080 041E H ’0080 0422 H ’0080 0424 H ’0080 0426 H ’0080 0428 H ’0080 0420 DMA0-4 Interrupt Request Status Register (DM04ITST)H ’0080 0400 H ’0080 0408 DMA5-9 Interrupt Mask Register (DM59ITMK)DMA5-9 Interrupt Request Status Register (DM59ITST) DMA5 Channel Control Register (DM5CNT) DMA5 Transfer Count Register (DM5TCT) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA6 Channel Control Register (DM6CNT) DMA6 Transfer Count Register (DM6TCT) H ’0080 03BE TIO0-9 Count Enable Register (TIOCEN) H ’0080 042A H ’0080 042C H ’0080 042E DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) H ’0080 03BC TIO0-9 Enable Protect Register (TIOPRO) +0 Address +1 AddressAddress Blank addresses are reserved areas.

3-20 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.11 Register Mapping of the SFR Area (7) D0 D7 D8 D15 DMA2 Channel Control Register (DM2CNT) DMA2 Transfer Count Register (DM2TCT)H ’0080 0430 H ’0080 0432 H ’0080 0434 H ’0080 0436 H ’0080 0438 H ’0080 043A H ’0080 043C H ’0080 043E H ’0080 0442 H ’0080 0444 H ’0080 0446 H ’0080 0448 H ’0080 044A H ’0080 044C H ’0080 0440 H ’0080 044E H ’0080 0450 H ’0080 0452 H ’0080 0454 H ’0080 0456 H ’0080 0458 H ’0080 045A H ’0080 045C H ’0080 045E H ’0080 0460 H ’0080 0464 H ’0080 0466 H ’0080 0462 DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA3 Channel Control Register (DM3CNT) DMA3 Transfer Count Register (DM3TCT) DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA4 Channel Control Register (DM4CNT) DMA4 Transfer Count Register (DM4TCT) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA7 Channel Control Register (DM7CNT) DMA7 Transfer Count Register (DM7TCT) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) DMA8 Channel Control Register (DM8CNT) DMA8 Transfer Count Register (DM8TCT) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA9 Channel Control Register (DM9CNT) DMA9 Transfer Count Register (DM9TCT) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA4 Software Request Generation Register (DM4SRI) DMA5 Software Request Generation Register (DM5SRI) DMA6 Software Request Generation Register (DM6SRI) DMA7 Software Request Generation Register (DM7SRI) DMA8 Software Request Generation Register (DM8SRI) DMA9 Software Request Generation Register (DM9SRI) H ’0080 0468 H ’0080 0470 H ’0080 0474 H ’0080 0476 H ’0080 0472 H ’0080 0478 H ’0080 0700 P0 Data Register (P0DATA) P1 Data Register (P1DATA) P2 Data Register (P2DATA) P3 Data Register (P3DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P7 Data Register (P7DATA) H ’0080 0702 H ’0080 0704 H ’0080 0706 H ’0080 0708 H ’0080 070A H ’0080 070C P8 Data Register (P8DATA) P10 Data Register (P10DATA) P12 Data Register (P12DATA) P9 Data Register (P9DATA) P11Data Register (P11DATA) P13 Data Register (P13DATA) P20 Data Register (P20DATA) P18 Data Register (P18DATA) P16 Data Register (P16DATA) P14 Data Register (P14DATA)H ’0080 070E H ’0080 0710 H ’0080 0712 H ’0080 0714 P15 Data Register (P15DATA) P17 Data Register (P17DATA) P19 Data Register (P19DATA) P21 Data Register (P21DATA) Blank addresses are reserved areas. +0 Address +1 AddressAddress

3-21 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.12 Register Mapping of the SFR Area (8) +0 Address +1 Address D0 D7 D8 D15 P2 Direction Register (P2DIR) P3 Direction Register (P3DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P7 Direction Register (P7DIR) P8 Direction Register (P8DIR) P9 Direction Register (P9DIR) P10 Direction Register (P10DIR) P11 Direction Register (P11DIR) P12 Direction Register (P12DIR) P13 Direction Register (P13DIR) P14 Direction Register (P14DIR) P15 Direction Register (P15DIR) H ’0080 0724 H ’0080 0722 H ’0080 0728 H ’0080 0726 H ’0080 072C H ’0080 072A H ’0080 0730 H ’0080 072E Address H ’0080 0746 H ’0080 074A H ’0080 0748 H ’0080 074E H ’0080 074C P6 Operation Mode Register (P6MOD) P7 Operation Mode Register (P7MOD) P8 Operation Mode Register (P8MOD) P9 Operation Mode Register (P9MOD) P10 Operation Mode Register (P10MOD) P11 Operation Mode Register (P11MOD) P12 Operation Mode Register (P12MOD) P13 Operation Mode Register (P13MOD) P14 Operation Mode Register (P14MOD) P15 Operation Mode Register (P15MOD) P16 Direction Register (P16DIR) P17 Direction Register (P17DIR) H ’0080 0750 P16 Operation Mode Register (P16MOD) P17 Operation Mode Register (P17MOD) H ’0080 078C TID0 Counter (TID0CT) TID0 Reload Register (TID0RL)H ’0080 078E H ’0080 0790 TOD0_0 Counter (TOD00CT) TOD0_0 Reload 1 Register (TOD00RL1) TOD0_0 Reload 0 Register (TOD00RL0) TOD0_1 Counter (TOD01CT) TOD0_1 Reload 1 Register (TOD01RL1) TOD0_0 Reload 0 Register (TOD01RL0) TOD0_2 Counter (TOD02CT) TOD0_2 Reload 1 Register (TOD02RL1) H ’0080 0794 H ’0080 0792 H ’0080 0798 H ’0080 0796 H ’0080 079C H ’0080 079A H ’0080 07A0 H ’0080 079E H ’0080 07A4 H ’0080 07A2 H ’0080 0744 Port Input Function Enable Register (PIEN) P22 Data Register (P22DATA)H ’0080 0716 H ’0080 0720 H ’0080 0732 H ’0080 0734 H ’0080 0736 P18 Direction Register (P18DIR) P20 Direction Register (P20DIR) P22 Direction Register (P22DIR) P19 Direction Register (P19DIR) P21 Direction Register (P21DIR) H ’0080 0752 H ’0080 0754 H ’0080 0756 P18 Operation Mode Register (P18MOD) P20 Operation Mode Register (P20MOD) P22 Operation Mode Register (P22MOD) P19 Operation Mode Register (P19MOD) P21 Operation Mode Register (P21MOD) Bus Mode Control Register (BUSMODC) P0 Direction Register (P0DIR) P1 Direction Register (P1DIR) H ’0080 077E H ’0080 07A6 H ’0080 07A8 H ’0080 07AA TOD0_2 Reload 0 Register (TOD02RL0) TOD0_3 Counter (TOD03CT) TOD0_3 Reload 1 Register (TOD03RL1) TOD0_3 Reload 0 Register (TOD03RL0) H ’0080 07AC H ’0080 07AE Blank addresses are reserved areas.

3-22 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.13 Register Mapping of the SFR Area (9) D0 D7 D8 D15 TOD0_7 Reload 1 Register (TOD07RL1)H ’0080 07CC H ’0080 07CA H ’0080 07D0 H ’0080 07CE H ’0080 07D4 H ’0080 07D2 H ’0080 07D8 H ’0080 07D6 H ’0080 07DE H ’0080 07E2 H ’0080 07E0 H ’0080 07E8 Flash Mode Register (FMOD) Flash Control Register 1 (FCNT1) H ’0080 07DC H ’0080 07DA TOD0_7 Reload 0 Register (TOD07RL0) Prescaler Register 3 (PRS3) TID0 Control & Prescaler 3 Enable Register (TID0PRES3EN) TOD0 Interrupt Mask Register (TOD0IMA) TOD0 Interrupt Status Register (TOD0IST) F/F Protect Register 2 (FFP2) F/F Data Register 2 (FFD2) TOD0 Control Register (TOD0CR) TOD0 Enable Protect Register (TOD0PRO) TOD0 Count Enable Register (TOD0CEN) H ’0080 07E4 Flash Status Register 1 (FSTAT1) Flash Control Register 2 (FCNT2) Flash Control Register 3 (FCNT3) Flash Control Register 4 (FCNT4) TOD0_4 Counter (TOD04CT) TOD0_4 Reload 1 Register (TOD04RL1) TOD0_4 Reload 0 Register (TOD04RL0) TOD0_5 Counter (TOD05CT) TOD0_5 Reload 1 Register (TOD05RL1) TOD0_5 Reload 0 Register (TOD05RL0) TOD0_6 Counter (TOD06CT) TOD0_6 Reload 1 Register (TOD06RL1) TOD0_6 Reload 0 Register (TOD06RL0) TOD0_7 Counter (TOD07CT) H ’0080 07B0 H ’0080 07B4 H ’0080 07B8 H ’0080 07B6 H ’0080 07BC H ’0080 07BA H ’0080 07BE H ’0080 07B2 H ’0080 07C0 H ’0080 07C4 H ’0080 07C8 H ’0080 07C6 H ’0080 07C2 Pseudo-flash L Bank Register 0 (FELBANK0) H ’0080 07EA H ’0080 0A00 H ’0080 0A02 H ’0080 0A10 H ’0080 0A12 H ’0080 0A14 H ’0080 0A16 H ’0080 0A20 H ’0080 0A22 H ’0080 0A24 Pseudo-flash L Bank Register 1 (FELBANK1) SIO45 Interrupt Status Register (SI45STAT) SIO45 Receive Interrupt Cause Select Register (SI45SEL) SIO45 Interrupt Mask Register (SI45MASK) SIO4 Transmit Control Register (S4TCNT) SIO4 Receive Control Register (S4RCNT) SIO4 Transmit Buffer Register (S4TXB) SIO4 Receive Buffer Register (S4RXB) SIO4 Transmit/Receive Mode Register (S4MOD) SIO4 Baud Rate Register (S4BAUR) SIO5 Transmit Control Register (S5RCNT) SIO5 Transmit/Receive Mode Register (S5MOD) SIO5 Transmit Buffer Register (S5TXB) SIO5 Receive Buffer Register (S5RXB) H ’0080 07EC Pseudo-flash L Bank Register 2 (FELBANK2) Pseudo-flash L Bank Register 3 (FELBANK3) H ’0080 0A26 SIO5 Receive Control Register (S5RCNT) SIO5 Baud Rate Register (S5BAUR) H ’0080 07EE Pseudo-flash S Bank Register 0 (FESBANK0) Pseudo-flash S Bank Register 1 (FESBANK1) H ’0080 07F0 H ’0080 07F2 H ’0080 07E6 Blank addresses are reserved areas. +0 Address +1 AddressAddress

3-23 32170/32174 Group User's Manual (Rev. 2.1) Figure 3.4.14 Register Mapping of the SFR Area (10) ADDRESS SPACE 10-bit A-D1 Data Register 9 (AD1DT9)H ’0080 0AA2 H ’0080 0AA0 H ’0080 0AA6 H ’0080 0AA4 H ’0080 0AAA H ’0080 0AA8 H ’0080 0AAE H ’0080 0AAC H ’0080 0AD2 H ’0080 0AD6 H ’0080 0AD4 H ’0080 0ADC H ’0080 0AD0 10-bit A-D1 Data Register 10 (AD1DT10) 8-bit A-D1 Data Register 0 (AD18DT0) 8-bit A-D1 Data Register 1 (AD18DT1) H ’0080 0AD8 8-bit A-D1 Data Register 2 (AD18DT2) A-D1 Successive Approximation Register (AD1SAR) A-D1 Comparate Data Register (AD1CMP) 10-bit A-D1 Data Register 1 (AD1DT1) 10-bit A-D1 Data Register 2 (AD1DT2) 10-bit A-D1 Data Register 3 (AD1DT3) 10-bit A-D1 Data Register 5 (AD1DT5) 10-bit A-D1 Data Register 6 (AD1DT6) 10-bit A-D1 Data Register 7 (AD1DT7) H ’0080 0A82 H ’0080 0A80 H ’0080 0A84 H ’0080 0A86 H ’0080 0A8A H ’0080 0A8C H ’0080 0A92 H ’0080 0A90 H ’0080 0A94 H ’0080 0A88 H ’0080 0A96 H ’0080 0A9A H ’0080 0A9E H ’0080 0A9C H ’0080 0A98 H ’0080 0ADE H ’0080 0AE2 H ’0080 0AE4 H ’0080 0AE8 H ’0080 0AEA H ’0080 0AEC H ’0080 0AEE H ’0080 0B8C H ’0080 0B8E H ’0080 0B90 TID1 Reload Register (TID1RL) TOD1_0 Counter (TOD10CT) A-D1 Single Mode Register 0 (AD1SIM0) A-D1 Single Mode Register 1 (AD1SIM1) A-D1 Scan Mode Register 0 (AD1SCM0) A-D1 Scan Mode Register 1 (AD1SCM1) 10-bit A-D1 Data Register 0 (AD1DT0) 10-bit A-D1 Data Register 4 (AD1DT4) 10-bit A-D1 Data Register 8 (AD1DT8) 10-bit A-D1 Data Register 11 (AD1DT11) 10-bit A-D1 Data Register 12 (AD1DT12) 10-bit A-D1 Data Register 13 (AD1DT13) 10-bit A-D1 Data Register 14 (AD1DT14) 10-bit A-D1 Data Register 15 (AD1DT15) H ’0080 0ADA H ’0080 0AE0 H ’0080 0AE6 8-bit A-D1 Data Register 3 (AD18DT3) 8-bit A-D1 Data Register 4 (AD18DT4) 8-bit A-D1 Data Register 5 (AD18DT5) 8-bit A-D1 Data Register 6 (AD18DT6) 8-bit A-D1 Data Register 7 (AD18DT7) 8-bit A-D1 Data Register 8 (AD18DT8) 8-bit A-D1 Data Register 9 (AD18DT9) 8-bit A-D1 Data Register 10 (AD18DT10) 8-bit A-D1 Data Register 11 (AD18DT11) 8-bit A-D1 Data Register 12 (AD18DT12) 8-bit A-D1 Data Register 13 (AD18DT13) 8-bit A-D1 Data Register 14 (AD18DT14) 8-bit A-D1 Data Register 15 (AD18DT15) TID1 Counter (TID1CT)TOD1_0 Reload 1 Register (TOD10RL1) H ’0080 0B92 H ’0080 0B94 Blank addresses are reserved areas. +0 Address +1 AddressAddress

3-24 32170/32174 Group User's Manual (Rev. 2.1) Figure 3.4.15 Register Mapping of the SFR Area (11) ADDRESS SPACE +0 Address +1 Address D0 D7 D8 D15 TOD1_5 Counter (TOD15CT)H ’0080 0BB8 H ’0080 0BB6 H ’0080 0BBC H ’0080 0BBA H ’0080 0BC0 H ’0080 0BBE H ’0080 0BC4 H ’0080 0BC2 H ’0080 0BCA Address H ’0080 0BCE H ’0080 0BCC H ’0080 0BD4 H ’0080 0BC8 H ’0080 0BD0 TOD1_1 Reload 0 Register (TOD11RL0) TOD1_3 Counter (TOD13CT) TOD1_3 Reload 1 Register (TOD13RL1) TOD1_4 Counter (TOD14CT) TOD1_4 Reload 1 Register (TOD14RL1) H ’0080 0B98 H ’0080 0B96 H ’0080 0B9A H ’0080 0B9C H ’0080 0BA0 H ’0080 0BA2 H ’0080 0BA8 H ’0080 0BA6 H ’0080 0BAA H ’0080 0B9E H ’0080 0BAC H ’0080 0BB0 H ’0080 0BB4 H ’0080 0BB2 H ’0080 0BAE H ’0080 0BD6 H ’0080 0BDA H ’0080 0BDC H ’0080 0C8C H ’0080 0C8E H ’0080 0C90 H ’0080 0C94 H ’0080 0C96 H ’0080 0C98 TOM0_0 Reload 0 Register (TOM00RL0) TOM0_1 Counter (TOM01CT) TOD1_2 Reload 0 Register (TOD12RL0) TOD1_3 Reload 0 Register (TOD13RL0) TOD1_4 Reload 0 Register (TOD14RL0) TOD1_5 Reload 1 Register (TOD15RL1) TOD1_5 Reload 0 Register (TOD15RL0) TOD1_6 Counter (TOD16CT) TOD1_6 Reload 1 Register (TOD16RL1) H ’0080 0BD2 H ’0080 0BD8 H ’0080 0BDE TOD1 Interrupt Status Register (TOD1IST) F/F Protect Register 3 (FFP3) F/F Data Register 3 (FFD3) TOD1 Enable Protect Register (TOD1PRO) TOD1 Count Enable Register (TOD1CEN) TOM0_0 Reload 1 Register (TOM00RL1) H ’0080 0BA4 H ’0080 0BC6 H ’0080 0C92 TOD1_0 Reload 0 Register (TOD10RL0) TOD1_1 Counter (TOD11CT) TOD1_1 Reload 1 Register (TOD11RL1) TOD1_2 Counter (TOD12CT) TOD1_2 Reload 1 Register (TOD12RL1) TOD1_6 Reload 0 Register (TOD16RL0) TOD1_7 Counter (TOD17CT) TOD1_7 Reload 1 Register (TOD17RL1) TOD1_7 Reload 0 Register (TOD17RL0) TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN)Prescaler Register 4 (PRS4) TOD1 Interrupt Mask Register (TOD1IMA) TOD1 Control Register (TOD1CR) TID2 Counter (TID2CT) TID2 Reload Register (TID2RL) TOM0_0 Counter (TOM00CT) H ’0080 0C9A H ’0080 0C9C TOM0_1 Reload 1 Register (TOM01RL1) Blank addresses are reserved areas.

3-25 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.16 Register Mapping of the SFR Area (12) D0 D7 D8 D15 TOM0_6 Counter (TOM06CT)H ’0080 0CC0 H ’0080 0CBE H ’0080 0CC4 H ’0080 0CC2 H ’0080 0CC8 H ’0080 0CC6 H ’0080 0CCC H ’0080 0CCA H ’0080 0CD2 H ’0080 0CD6 H ’0080 0CD4 H ’0080 0CDC H ’0080 0CD0 H ’0080 0CD8 TOM0_2 Reload 0 Register (TOM02RL0) TOM0_4 Counter (TOM04CT) TOM0_4 Reload 1 Register (TOM04RL1) TOM0_5 Counter (TOM05CT) TOM0_5 Reload 1 Register (TOM05RL1) H ’0080 0CA0 H ’0080 0C9E H ’0080 0CA2 H ’0080 0CA4 H ’0080 0CA8 H ’0080 0CAA H ’0080 0CB0 H ’0080 0CAE H ’0080 0CB2 H ’0080 0CA6 H ’0080 0CB4 H ’0080 0CB8 H ’0080 0CBC H ’0080 0CBA H ’0080 0CB6 H ’0080 0CDE H ’0080 0FE0 H ’0080 0FE2 H ’0080 0FF0 H ’0080 0FF2 H ’0080 0FF6 H ’0080 0FF8 H ’0080 0FFA TML1 Measure 1 Register, High (TML1MR1H) TML1 Measure 1 Register, Low (TML1MR1L) TOM0_3 Reload 0 Register (TOM03RL0) TOM0_4 Reload 0 Register (TOM04RL0) TOM0_5 Reload 0 Register (TOM05RL0) TOM0_6 Reload 1 Register (TOM06RL1) TOM0_6 Reload 0 Register (TOM06RL0) TOM0_7 Counter (TOM07CT) TOM0_7 Reload 1 Register (TOM07RL1) H ’0080 0CDA TOM0 Interrupt Status Register (TOM0IST) F/F Protect Register 4 (FFP4) F/F Data Register 4 (FFD4) TOM0 Count Enable Register (TOM0CEN) TOM0 Enable Protect Register (TOM0PRO) TML1 Measure 2 Register, Low (TML1MR2L) H ’0080 0CAC H ’0080 0CCE H ’0080 0FF4 TOM0_1 Reload 0 Register (TOM01RL0) TOM0_2 Counter (TOM02CT) TOM0_2 Reload 1 Register (TOM02RL1) TOM0_3 Counter (TOM03CT) TOM0_3 Reload 1 Register (TOM03RL1) TOM0_7 Reload 0 Register (TOM07RL0) TID2 Control & Prescaler 5 Enable Register (TID2PRS5EN)Prescaler Register 5 (PRS5) TOM0 Interrupt Mask Register (TOM0IMA) TOM0 Control Register (TOM0CR) TML1 Measure 3 Register, High (TML1MR3H) TML1 Counter, High (TML1CTH) TML1 Counter, Low (TML1CTL) H ’0080 0FEA TML1 Control Register (TML1CR) TML1 Measure 2 Register, High (TML1MR2H) H ’0080 0FFC H ’0080 0FFE TML1 Measure 0 Register, High (TML1MR0H) TML1 Measure 0 Register, Low (TML1MR0L) Blank addresses are reserved areas. +0 Address +1 AddressAddress TML1 Measure 3 Register, Low (TML1MR3L)

3-26 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.17 Register Mapping of the SFR Area (13) D0 D7 D8 D15 H ’0080 1034 H ’0080 1032 H ’0080 1038 H ’0080 1036 H ’0080 103C H ’0080 103A H ’0080 1054 H ’0080 1058 H ’0080 1056 H ’0080 1052 H ’0080 105A CAN0 Configuration Register (CAN0CONF) CAN0 Global Mask Register Standard ID0 (C0GMSKS0) CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0) H ’0080 1000 H ’0080 1002 H ’0080 1004 H ’0080 1008 H ’0080 100A H ’0080 1010 H ’0080 100E H ’0080 1006 H ’0080 1028 H ’0080 102C H ’0080 1030 H ’0080 102E H ’0080 102A H ’0080 105C H ’0080 100C H ’0080 1050 CAN0 Control Register (CAN0CNT) CAN0 extended ID Register (CAN0EXTID) CAN0 Time Stamp Count Register (CAN0TSTMP) CAN0 Slot Interrupt Status Register (CAN0SLIST) CAN0 Message Slot 3 Control Register (C0MSL3CNT)CAN0 Message Slot 2 Control Register (C0MSL2CNT) CAN0 Message Slot 4 Control Register (C0MSL4CNT) CAN0 Status Register (CAN0STAT) CAN0 Receive Error Count Register (CAN0REC) CAN0 Transmit Error Count Register (CAN0TEC) CAN0 Message Slot 0 Control Register (C0MSL0CNT) CAN0 Message Slot 1 Control Register (C0MSL1CNT) CAN0 Message Slot 5 Control Register (C0MSL5CNT) CAN0 Message Slot 7 Control Register (C0MSL7CNT) CAN0 Message Slot 9 Control Register (C0MSL9CNT) CAN0 Message Slot 11 Control Register (C0MSL11CNT) CAN0 Message Slot 13 Control Register (C0MSL13CNT) CAN0 Message Slot 15 Control Register (C0MSL15CNT) CAN0 Message Slot 6 Control Register (C0MSL6CNT) CAN0 Message Slot 8 Control Register (C0MSL8CNT) CAN0 Message Slot 10 Control Register (C0MSL10CNT) CAN0 Message Slot 12 Control Register (C0MSL12CNT) CAN0 Message Slot 14 Control Register (C0MSL14CNT) H ’0080 1012 CAN0 Error Interrupt Status Register (CAN0ERIST) CAN0 Error Interrupt Mask Register (CAN0ERIMK)H ’0080 1014 H ’0080 1016 CAN0 Baud Rate Prescaler (CAN0BRP) H ’0080 105E CAN0 Global Mask Register Standard ID1 (C0GMSKS1) CAN0 Global Mask Register Extended ID0 (C0GMSKE0) CAN0 Global Mask Register Extended ID1 (C0GMSKE1) CAN0 Global Mask Register Extended ID2 (C0GMSKE2) CAN0 Local Mask Register A Standard ID1 (C0LMSKAS1) CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0) CAN0 Local Mask Register A Extended ID1 (C0LMSKAE1) CAN0 Local Mask Register A Extended ID2 (C0LMSKAE2) CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0) CAN0 Local Mask Register B Standard ID0 (C0LMSKBS1) CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) CAN0 Local Mask Register B Extended ID0 (C0LMSKBE1) CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) Blank addresses are reserved areas. +0 Address +1 AddressAddress CAN0 Slot Interrupt Mask Register (CAN0SLIMK)

3-27 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.18 Register Mapping of the SFR Area (14) D0 D7 D8 D15 H'0080 1102 H'0080 1104 H'0080 110C H'0080 110E H'0080 1112 H'0080 1114 H'0080 1116 H'0080 1110 H'0080 1108 H'0080 1106 H'0080 110A CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) CAN0 Message Slot 0 Data 0 (C0MSL0DT0) CAN0 Message Slot 0 Data 2 (C0MSL0DT2) CAN0 Message Slot 0 Data 4 (C0MSL0DT4) CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) CAN0 Message Slot 0 Data 1 (C0MSL0DT1) CAN0 Message Slot 0 Data 3 (C0MSL0DT3) CAN0 Message Slot 0 Data 5 (C0MSL0DT5) CAN0 Message Slot 0 Data 6 (C0MSL0DT6) CAN0 Message Slot 0 Data 7 (C0MSL0DT7) CAN0 Message Slot 0 Time Stamp (C0MSL0TSP) CAN0 Message Slot 1 Standard ID0 (C0MSL1SID0) CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0) CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2) CAN0 Message Slot 1 Data 0 (C0MSL1DT0) CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1) CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1) CAN0 Message Slot 1 Data Length Register (C0MSL1DLC) CAN0 Message Slot 1 Data 1 (C0MSL1DT1) CAN0 Message Slot 1 Data 3 (C0MSL1DT3) CAN0 Message Slot 1 Data 5 (C0MSL1DT5) CAN0 Message Slot 1 Data 2 (C0MSL1DT2) CAN0 Message Slot 1 Data 4 (C0MSL1DT4) H'0080 1118 H'0080 111A H'0080 111E H'0080 1120 H'0080 1122 H'0080 1126 H'0080 1128 H'0080 112E H'0080 112C H'0080 1124 H'0080 112A CAN0 Message Slot 2 Data 6 (C0MSL2DT6) CAN0 Message Slot 2 Time Stamp (C0MSL2TSP) CAN0 Message Slot 2 Data 7 (C0MSL2DT7) H'0080 111C CAN0 Message Slot 2 Data 4 (C0MSL2DT4) CAN0 Message Slot 2 Data 2 (C0MSL2DT2) CAN0 Message Slot 2 Data 0 (C0MSL2DT0) CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2) CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0) CAN0 Message Slot 2 Standard ID0 (C0MSL2SID0) CAN0 Message Slot 1 Time Stamp (C0MSL1TSP) CAN0 Message Slot 1 Data 6 (C0MSL1DT6) CAN0 Message Slot 2 Data 5 (C0MSL2DT5) CAN0 Message Slot 2 Data 3 (C0MSL2DT3) CAN0 Message Slot 2 Data 1 (C0MSL2DT1) CAN0 Message Slot 2 Data Length Register (C0MSL2DLC) CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1) CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1) CAN0 Message Slot 1 Data 7 (C0MSL1DT7) H'0080 1130 H'0080 1132 H'0080 1136 H'0080 1138 H'0080 113E H'0080 113C H'0080 1134 H'0080 113A CAN0 Message Slot 3 Data 6 (C0MSL3DT6) CAN0 Message Slot 3 Time Stamp (C0MSL3TSP) CAN0 Message Slot 3 Data 7 (C0MSL3DT7) CAN0 Message Slot 3 Data 4 (C0MSL3DT4) CAN0 Message Slot 3 Data 2 (C0MSL3DT2) CAN0 Message Slot 3 Data 0 (C0MSL3DT0) CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2) CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0) CAN0 Message Slot 3 Standard ID0 (C0MSL3SID0) CAN0 Message Slot 3 Data 5 (C0MSL3DT5) CAN0 Message Slot 3 Data 3 (C0MSL3DT3) CAN0 Message Slot 3 Data 1 (C0MSL3DT1) CAN0 Message Slot 3 Data Length Register (C0MSL3DLC) CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1) CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1) H'0080 1140 H'0080 1142 H'0080 1146 H'0080 1148 H'0080 114E H'0080 114C H'0080 1144 H'0080 114A CAN0 Message Slot 4 Data 6 (C0MSL4DT6) CAN0 Message Slot 4 Time Stamp (C0MSL4TSP) CAN0 Message Slot 4 Data 7 (C0MSL4DT7) CAN0 Message Slot 4 Data 4 (C0MSL4DT4) CAN0 Message Slot 4 Data 2 (C0MSL4DT2) CAN0 Message Slot 4 Data 0 (C0MSL4DT0) CAN0 Message Slot 4 Extended ID2 (C0MSL4EID2) CAN0 Message Slot 4 Extended ID0 (C0MSL4EID0) CAN0 Message Slot 4 Standard ID0 (C0MSL4SID0) CAN0 Message Slot 4 Data 5 (C0MSL4DT5) CAN0 Message Slot 4 Data 3 (C0MSL4DT3) CAN0 Message Slot 4 Data 1 (C0MSL4DT1) CAN0 Message Slot 4 Data Length Register (C0MSL4DLC) CAN0 Message Slot 4 Extended ID1 (C0MSL4EID1) CAN0 Message Slot 4 Standard ID1 (C0MSL4SID1) H'0080 1150 H'0080 1152 CAN0 Message Slot 5 Extended ID0 (C0MSL5EID0) CAN0 Message Slot 5 Standard ID0 (C0MSL5SID0) CAN0 Message Slot 5 Extended ID1 (C0MSL5EID1) CAN0 Message Slot 5 Standard ID1 (C0MSL5SID1) H'0080 1100 CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1)CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) Blank addresses are reserved areas. +0 Address +1 AddressAddress

3-28 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.4.19 Register Mapping of the SFR Area (15) D0 D7 D8 D15 H'0080 1156 H'0080 1158 H'0080 115E H'0080 115C H'0080 1154 H'0080 115A H'0080 1160 H'0080 1162 H'0080 1166 H'0080 1168 H'0080 116E H'0080 116C H'0080 1164 H'0080 116A H'0080 1170 H'0080 1172 H'0080 1176 H'0080 1174 CAN0 Message Slot 5 Data 6 (C0MSL5DT6) CAN0 Message Slot 5 Time Stamp (C0MSL5TSP) CAN0 Message Slot 5 Data 7 (C0MSL5DT7) CAN0 Message Slot 5 Data 4 (C0MSL5DT4) CAN0 Message Slot 5 Data 2 (C0MSL5DT2) CAN0 Message Slot 5 Data 0 (C0MSL5DT0) CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) CAN0 Message Slot 5 Data 5 (C0MSL5DT5) CAN0 Message Slot 5 Data 3 (C0MSL5DT3) CAN0 Message Slot 5 Data 1 (C0MSL5DT1) CAN0 Message Slot 5 Data Length Register (C0MSL5DLC) CAN0 Message Slot 6 Data 6 (C0MSL6DT6) CAN0 Message Slot 6 Time Stamp (C0MSL6TSP) CAN0 Message Slot 6 Data 7 (C0MSL6DT7) CAN0 Message Slot 6 Data 4 (C0MSL6DT4) CAN0 Message Slot 6 Data 2 (C0MSL6DT2) CAN0 Message Slot 6 Data 0 (C0MSL6DT0) CAN0 Message Slot 6 Extended ID2 (C0MSL6EID2) CAN0 Message Slot 6 Extended ID0 (C0MSL6EID0) CAN0 Message Slot 6 Standard ID0 (C0MSL6SID0) CAN0 Message Slot 6 Data 5 (C0MSL6DT5) CAN0 Message Slot 6 Data 3 (C0MSL6DT3) CAN0 Message Slot 6 Data 1 (C0MSL6DT1) CAN0 Message Slot 6 Data Length Register (C0MSL6DLC) CAN0 Message Slot 6 Extended ID1 (C0MSL6EID1) CAN0 Message Slot 6 Standard ID1 (C0MSL6SID1) CAN0 Message Slot 7 Data 0 (C0MSL7DT0) CAN0 Message Slot 7 Extended ID2 (C0MSL7EID2) CAN0 Message Slot 7 Extended ID0 (C0MSL7EID0) CAN0 Message Slot 7 Standard ID0 (C0MSL7SID0) CAN0 Message Slot 7 Data 1 (C0MSL7DT1) CAN0 Message Slot 7 Data Length Register (C0MSL7DLC) CAN0 Message Slot 7 Extended ID1 (C0MSL7EID1) CAN0 Message Slot 7 Standard ID1 (C0MSL7SID1) H'0080 117A H'0080 117C H'0080 117E H'0080 1182 H'0080 1184 H'0080 118A H'0080 1188 H'0080 1180 H'0080 1186 H'0080 1178 H'0080 118C H'0080 118E H'0080 1192 H'0080 1194 H'0080 119A H'0080 1198 H'0080 1190 H'0080 1196 H'0080 119C H'0080 119E CAN0 Message Slot 8 Data 6 (C0MSL8DT6) CAN0 Message Slot 8 Time Stamp (C0MSL8TSP) CAN0 Message Slot 8 Data 7 (C0MSL8DT7) CAN0 Message Slot 8 Data 4 (C0MSL8DT4) CAN0 Message Slot 8 Data 2 (C0MSL8DT2) CAN0 Message Slot 8 Data 0 (C0MSL8DT0) CAN0 Message Slot 8 Extended ID2 (C0MSL8EID2) CAN0 Message Slot 8 Extended ID0 (C0MSL8EID0) CAN0 Message Slot 8 Standard ID0 (C0MSL8SID0) CAN0 Message Slot 8 Data 5 (C0MSL8DT5) CAN0 Message Slot 8 Data 3 (C0MSL8DT3) CAN0 Message Slot 8 Data 1 (C0MSL8DT1) CAN0 Message Slot 8 Data Length Register (C0MSL8DLC) CAN0 Message Slot 8 Extended ID1 (C0MSL8 EID1) CAN0 Message Slot 8 Standard ID1 (C0MSL8SID1) CAN0 Message Slot 7 Data 6 (C0MSL7DT6) CAN0 Message Slot 7 Time Stamp (C0MSL7TSP) CAN0 Message Slot 7 Data 7 (C0MSL7DT7) CAN0 Message Slot 7 Data 4 (C0MSL7DT4) CAN0 Message Slot 7 Data 2 (C0MSL7DT2) CAN0 Message Slot 7 Data 5 (C0MSL7DT5) CAN0 Message Slot 7 Data 3 (C0MSL7DT3) CAN0 Message Slot 9 Data 6 (C0MSL9DT6) CAN0 Message Slot 9 Time Stamp (C0MSL9TSP) CAN0 Message Slot 9 Data 7 (C0MSL9DT7) CAN0 Message Slot 9 Data 4 (C0MSL9DT4) CAN0 Message Slot 9 Data 2 (C0MSL9DT2) CAN0 Message Slot 9 Data 0 (C0MSL9DT0) CAN0 Message Slot 9 Extended ID2 (C0MSL9EID2) CAN0 Message Slot 9 Extended ID0 (C0MSL9EID0) CAN0 Message Slot 9 Standard ID0 (C0MSL9SID0) CAN0 Message Slot 9 Data 5 (C0MSL9DT5) CAN0 Message Slot 9 Data 3 (C0MSL9DT3) CAN0 Message Slot 9 Data 1 (C0MSL9DT1) CAN0 Message Slot 9 Data Length Register (C0MSL9DLC) CAN0 Message Slot 9 Extended ID1 (C0MSL9EID1) CAN0 Message Slot 9 Standard ID1 (C0MSL9SID1) H'0080 11A2 H'0080 11A4 H'0080 11A0 CAN0 Message Slot 10 Extended ID2 (C0MSL10EID2) CAN0 Message Slot 10 Extended ID0 (C0MSL10EID0) CAN0 Message Slot 10 Standard ID0 (C0MSL10SID0) CAN0 Message Slot 10 Data Length Register (C0MSL10DLC) CAN0 Message Slot 10 Extended ID1 (C0MSL10EID1) CAN0 Message Slot 10 Standard ID1 (C0MSL10SID1) H'0080 11A6 CAN0 Message Slot 10 Data 0 (C0MSL10DT0) CAN0 Message Slot 10 Data 1 (C0MSL10DT1) Blank addresses are reserved areas. +0 Address +1 AddressAddress

3-29 32170/32174 Group User's Manual (Rev. 2.1) Figure 3.4.20 Register Mapping of the SFR Area (16) ADDRESS SPACE H ’0080 11AA H ’0080 11A8 H ’0080 11AC H ’0080 11AE H ’0080 11B2 H ’0080 11BC H ’0080 11BA H ’0080 11B8 H ’0080 11B0 H ’0080 11B6 H ’0080 11BE H ’0080 11C2 H ’0080 11C4 H ’0080 11CA H ’0080 11C8 H ’0080 11C0 H ’0080 11C6 H ’0080 11CE H ’0080 11D2 H ’0080 11D0 CAN0 Message Slot 10 Data 6 (C0MSL10DT6) CAN0 Message Slot 10 Time Stamp (C0MSL10TSP) CAN0 Message Slot 10 Data 7 (C0MSL10DT7) CAN0 Message Slot 10 Data 4 (C0MSL10DT4) CAN0 Message Slot 10 Data 2 (C0MSL10DT2) CAN0 Message Slot 10 Data 5 (C0MSL10DT5) CAN0 Message Slot 10 Data 3 (C0MSL10DT3) CAN0 Message Slot 11 Data 6 (C0MSL11DT6) CAN0 Message Slot 11 Time Stamp (C0MSL11TSP) CAN0 Message Slot 11 Data 7 (C0MSL11DT7) CAN0 Message Slot 11 Data 4 (C0MSL11DT4) CAN0 Message Slot 11 Data 2 (C0MSL11DT2) CAN0 Message Slot 11 Data 0 (C0MSL11DT0) CAN0 Message Slot 11 Extended ID2 (C0MSL11EID2) CAN0 Message Slot 11 Extended ID0 (C0MSL11EID0) CAN0 Message Slot 11 Standard ID0 (C0MSL11SID0) CAN0 Message Slot 11 Data 5 (C0MSL11DT5) CAN0 Message Slot 11 Data 3 (C0MSL11DT3) CAN0 Message Slot 11 Data 1 (C0MSL11DT1) CAN0 Message Slot 11 Data Length Register (C0MSL11DLC) CAN0 Message Slot 11 Extended ID1 (C0MSL11EID1) CAN0 Message Slot 11 Standard ID1 (C0MSL11SID1) CAN0 Message Slot 12 Data 6 (C0MSL12DT6) CAN0 Message Slot 12 Time Stamp (C0MSL12TSP) CAN0 Message Slot 12 Data 7 (C0MSL12DT7) CAN0 Message Slot 12 Data 4 (C0MSL12DT4) CAN0 Message Slot 12 Data 2 (C0MSL12DT2) CAN0 Message Slot 12 Data 0 (C0MSL12DT0) CAN0 Message Slot 12 Extended ID2 (C0MSL12EID2) CAN0 Message Slot 12 Extended ID0 (C0MSL12EID0) CAN0 Message Slot 12 Standard ID0 (C0MSL12SID0) CAN0 Message Slot 12 Data 5 (C0MSL12DT5) CAN0 Message Slot 12 Data 3 (C0MSL12DT3) CAN0 Message Slot 12 Data 1 (C0MSL12DT1) CAN0 Message Slot 12 Data Length Register (C0MSL12DLC) CAN0 Message Slot 12 Extended ID1 (C0MSL12EID1) CAN0 Message Slot 12 Standard ID1 (C0MSL12SID1) CAN0 Message Slot 13 Extended ID0 (C0MSL13EID0) CAN0 Message Slot 13 Standard ID0 (C0MSL13SID0) CAN0 Message Slot 13 Extended ID1 (C0MSL13EID1) CAN0 Message Slot 13 Standard ID1 (C0MSL13SID1) H ’0080 11D6 H ’0080 11D8 H ’0080 11DA H ’0080 11DE H ’0080 11E0 H ’0080 11E6 H ’0080 11E4 H ’0080 11DC H ’0080 11E2 H ’0080 11D4 H ’0080 11E8 H ’0080 11EA H ’0080 11EE H ’0080 11F0 H ’0080 11F6 H ’0080 11F4 H ’0080 11EC H ’0080 11F2 H ’0080 11F8 H ’0080 11FA H ’0080 11FE H ’0080 3FFE H ’0080 11FC CAN0 Message Slot 14 Data 6 (C0MSL14DT6) CAN0 Message Slot 14 Time Stamp (C0MSL14TSP) CAN0 Message Slot 14 Data 7 (C0MSL14DT7) CAN0 Message Slot 14 Data 4 (C0MSL14DT4) CAN0 Message Slot 14 Data 2 (C0MSL14DT2) CAN0 Message Slot 14 Data 0 (C0MSL14DT0) CAN0 Message Slot 14 Extended ID2 (C0MSL14EID2) CAN0 Message Slot 14 Extended ID0 (C0MSL14EID0) CAN0 Message Slot 14 Standard ID0 (C0MSL14SID0) CAN0 Message Slot 14 Data 5 (C0MSL14DT5) CAN0 Message Slot 14 Data 3 (C0MSL14DT3) CAN0 Message Slot 14 Data 1 (C0MSL14DT1) CAN0 Message Slot 14 Data Length Register (C0MSL14DLC) CAN0 Message Slot 14 Extended ID1 (C0MSL14EID1) CAN0 Message Slot 14 Standard ID1 (C0MSL14SID1) CAN0 Message Slot 13 Data 6 (C0MSL13DT6) CAN0 Message Slot 13 Time Stamp (C0MSL13TSP) CAN0 Message Slot 13 Data 7 (C0MSL13DT7) CAN0 Message Slot 13 Data 4 (C0MSL13DT4) CAN0 Message Slot 13 Data 2 (C0MSL13DT2) CAN0 Message Slot 13 Data 0 (C0MSL13DT0) CAN0 Message Slot 13 Extended ID2 (C0MSL13EID2) CAN0 Message Slot 13 Data 5 (C0MSL13DT5) CAN0 Message Slot 13 Data 3 (C0MSL13DT3) CAN0 Message Slot 13 Data 1 (C0MSL13DT1) CAN0 Message Slot 15 Data 6 (C0MSL15DT6) CAN0 Message Slot 15 Time Stamp (C0MSL11TSP) CAN0 Message Slot 15 Data 7 (C0MSL15DT7) CAN0 Message Slot 15 Data 4 (C0MSL15DT4) CAN0 Message Slot 15 Data 2 (C0MSL15DT2) CAN0 Message Slot 15 Data 0 (C0MSL15DT0) CAN0 Message Slot 15 Extended ID2 (C0MSL15EID2) CAN0 Message Slot 15 Extended ID0 (C0MSL15EID0) CAN0 Message Slot 15 Standard ID0 (C0MSL15SID0) CAN0 Message Slot 15 Data 5 (C0MSL15DT5) CAN0 Message Slot 15 Data 3 (C0MSL15DT3) CAN0 Message Slot 15 Data 1 (C0MSL15DT1) CAN0 Message Slot 15 Data Length Register (C0MSL15DLC) CAN0 Message Slot 15 Extended ID1 (C0MSL15EID1) CAN0 Message Slot 15 Standard ID1 (C0MSL15SID1) CAN0 Message Slot 13 Data Length Register (C0MSL13DLC) H ’0080 11CC H ’0080 11B4 Blank addresses are reserved areas. +0 Address +1 AddressAddress

3-30 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE The EIT vector entry is located at the beginning of the internal ROM/extended external areas. Instructions for branching to the start addresses of respective EIT event handlers are written here. Note that it is branch instructions and not the jump addresses that are written here. For details, refer to Chapter 4, "EIT." Figure 3.5.1 EIT Vector Entry Note: When flash entry bit = 1 (i.e., flash enable mode), the EI vector entry is at H'0080 4000. H’0000 0040 TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 AE (Address Exception) EI (External Interrupt) (Note) H’0000 0044 H’0000 0048 H’0000 004C H’0000 0050 H’0000 0054 H’0000 0058 H’0000 005C H’0000 0060 H’0000 0064 H’0000 0068 H’0000 006C H’0000 0070 H’0000 0074 H’0000 0078 H’0000 007C H’0000 0080 RI (Reset Interrupt) SBI (System Break Interrupt) RIE (Reserved Instruction Exception) H’0000 0030 H’0000 0020 H’0000 0010 H’0000 0000 03 1 H’0000 0034 H’0000 0038 H’0000 003C H’0000 0024 H’0000 0028 H’0000 002C H’0000 0004 H’0000 0008 H’0000 000C H’0000 0014 H’0000 0018 H’0000 001C

3-31 32170/32174 Group User's Manual (Rev. 2.1) The ICU vector table is used by the internal interrupt controller. The start addresses of interrupt handlers for the interrupt requests from respective internal peripheral I/Os are set at the ad- dresses shown below. For details, refer to Chapter 5, "Interrupt Controller." ADDRESS SPACE Figure 3.6.1 ICU Vector Table (1/2) H’0000 0094 Address D0 D7 +0 Address +1 Address D8 D15 H’0000 0096 MJT Input Interrupt 4 Handler Start Address (A0-A15) MJT Input Interrupt 4 Handler Start Address (A16-A31) H’0000 0098 H’0000 009A H’0000 009C H’0000 009E H’0000 00A0 H’0000 00A2 H’0000 00A4 H’0000 00A6 H’0000 00A8 H’0000 00AA H’0000 00AC H’0000 00AE H’0000 00B0 H’0000 00B2 H’0000 00B4 H’0000 00B6 H’0000 00B8 H’0000 00BA H’0000 00BC H’0000 00BE H’0000 00C0 H’0000 00C2 H’0000 00C4 H’0000 00C6 MJT Output Interrupt 7 Handler Start Address (A0-A15) MJT Output Interrupt 7 Handler Start Address (A16-A31) MJT Input Interrupt 3 Handler Start Address (A0-A15) MJT Input Interrupt 3 Handler Start Address (A16-A31) MJT Input Interrupt 2 Handler Start Address (A0-A15) MJT Input Interrupt 2 Handler Start Address (A16-A31) MJT Input Interrupt 1 Handler Start Address (A0-A15) MJT Input Interrupt 1 Handler Start Address (A16-A31) MJT Input Interrupt 0 Handler Start Address (A0-A15) MJT Input Interrupt 0 Handler Start Address (A16-A31) MJT Output Interrupt 6 Handler Start Address (A0-A15) MJT Output Interrupt 6 Handler Start Address (A16-A31) MJT Output Interrupt 5 Handler Start Address (A0-A15) MJT Output Interrupt 5 Handler Start Address (A16-A31) MJT Output Interrupt 4 Handler Start Address (A0-A15) MJT Output Interrupt 4 Handler Start Address (A16-A31) MJT Output Interrupt 3 Handler Start Address (A0-A15) MJT Output Interrupt 3 Handler Start Address (A16-A31) MJT Output Interrupt 2 Handler Start Address (A0-A15) MJT Output Interrupt 2 Handler Start Address (A16-A31) MJT Output Interrupt 1 Handler Start Address (A0-A15) MJT Output Interrupt 1 Handler Start Address (A16-A31) MJT Output Interrupt 0 Handler Start Address (A0-A15) MJT Output Interrupt 0 Handler Start Address (A16-A31)

3-32 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE Figure 3.6.2 ICU Vector Table (2/2) H'0000 00C8 Address D0 D7 +0 Address +1 Address D8 D15 H'0000 00CA DMA0-4 Interrupt Handler Start Address (A0-A15) DMA0-4 Interrupt Handler Start Address (A16-A31) H'0000 00CC H'0000 00CE H'0000 00D0 H'0000 00D2 H'0000 00D4 H'0000 00D6 H'0000 00D8 H'0000 00DA H'0000 00DC H'0000 00DE SIO1 Receive Interrupt Handler Start Address (A0-A15) SIO1 Receive Interrupt Handler Start Address (A16-A31) SIO1 Transmit Interrupt Handler Start Address (A0-A15) SIO1 Transmit Interrupt Handler Start Address (A16-A31) A-D0 Conversion Interrupt Handler Start Address (A0-A15) A-D0 Conversion Interrupt Handler Start Address (A16-A31) H'0000 00E0 H'0000 00E2 H'0000 00E4 H'0000 00E6 H'0000 00E8 H'0000 00EA H'0000 00EC H'0000 00EE TID0 Output Interrupt Handler Start Address (A0-A15) TID0 Output Transmit Interrupt Handler Start Address (A16-A31) TOD0 Output Interrupt Handler Start Address (A0-A15) TOD0 Output Interrupt Handler Start Address (A16-A31) DMA5-9 Interrupt Handler Start Address (A0-A15) DMA5-9 Interrupt Handler Start Address (A16-A31) SIO2,3 Transmit/Receive Interrupt Handler Start Address (A0-A15) SIO2,3 Transmit/Receive Interrupt Handler Start Address (A16-A31) H'0000 00F0 H'0000 00F2 RTD Interrupt Handler Start Address (A0-A15) RTD Interrupt Handler Start Address (A16-A31) H'0000 00F4 H'0000 00F6 TID1 Output Interrupt Handler Start Address (A0-A15) TID1 Output Interrupt Handler Start Address (A16-A31) H'0000 00F8 H'0000 00FA TOD1+TOM0 Output Interrupt Handler Start Address (A0-A15) TOD1+TOM0 Output Interrupt Handler Start Address (A16-A31) H'0000 00FC H'0000 00FE SIO4,5 Transmit/Receive Interrupt Handler Start Address (A0-A15) SIO4,5 Transmit/Receive Interrupt Handler Start Address (A16-A31) H'0000 0100 H'0000 0102 A-D1 Conversion Interrupt Handler Start Address (A0-A15) A-D1 Conversion Interrupt Handler Start Address (A16-A31) H'0000 0104 H'0000 0106 TID2 Output Interrupt Handler Start Address (A0-A15) TID2 Output Interrupt Handler Start Address (A16-A31) H'0000 0108 H'0000 010A TML1 Input Interrupt Handler Start Address (A0-A15) TML1 Input Interrupt Handler Start Address (A16-A31) H'0000 010C H'0000 010E CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A0-A15) CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A16-A31) SIO0 Receive Interrupt Handler Start Address (A0-A15) SIO0 Receive Interrupt Handler Start Address (A16-A31) SIO0 Transmit Interrupt Handler Start Address (A0-A15) SIO0 Transmit Interrupt Handler Start Address (A16-A31)

3-33 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE

• Virtual-flash emulation function The 32170 and 32174 have a function for mapping 8-Kbyte blocks (up to four blocks for the M32170F6 or up to three blocks for the M32170F4, M32170F3, M32174F4, and M32174F3) of the internal RAM beginning with its start address into the internal flash memory areas divided in units of

8 Kbytes (L banks), as well as mapping 4-Kbyte blocks (up to two blocks) of the internal RAM

beginning with address H’0080 C000 for the M32170F6 or H’0080 A000 for the M32170F4, M32170F3, M32174F4, and M32174F3 into the internal flash memory areas divided in units of 4 Kbytes (S banks). This is referred to as the virtual-flash emulation function. For details about this function, refer to Section 6.7, “Virtual-flash Emulation Function.”

3-34 32170/32174 Group User's Manual (Rev. 2.1) ADDRESS SPACE ❊ This is a blank page. ❊

4.1 Outline of EIT

4.2 EIT Event

4.3 EIT Processing Procedure

4.4 EIT Processing Mechanism

4.5 Acceptance of EIT Events

4.6 Saving and Restoring the PC

4.7 EIT Vector Entry

4.8 Exception Processing

4.9 Interrupt Processing

4.10 Trap Processing

4.11 EIT Priority Levels

4.12 Example of EIT Processing

4.13 Precautions on EIT

4-2 32170/32174 Group User's Manual (Rev. 2.1) EIT If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. Events like this one are referred to by a generic name as EIT (Exception, Interrupt, and Trap). (1) Exception This is an event related to the context being executed. It is generated by an error or violation during instruction execution. In the M32R/ECU, this type of event includes Address Exception (AE) and Reserved Instruction Exception (RIE). (2) Interrupt This is an event generated irrespective of the context being executed. It is generated in hardware by a signal from an external source. In the M32R/ECU, this type of event includes External Interrupt (EI), System Break Interrupt (SBI), and Reset Interrupt (RI). (3) Trap This refers to a software interrupt generated by executing a TRAP instruction. This type of event is intentionally generated in a program as in the OS's system call by the programmer. EIT Exception Reserved Instruction Exception (RIE) Address Exception (AE) Interrupt Reset Interrupt (RI) System Break Interrupt (SBI) External Interrupt (EI) Trap TRAP Figure 4.1.1 Classification of EITs

4-3 32170/32174 Group User's Manual (Rev. 2.1) EIT

4.2.1 Exception

(1) Reserved Instruction Exception (RIE) Reserved Instruction Exception (RIE) is generated when execution of a reserved instruction (unimplemented instruction) is detected. (2) Address Exception (AE) Address Exception (AE) is generated when an attempt is made to access a misaligned address in Load or Store instructions.

4.2.2 Interrupt

(1) Reset Interrupt (RI) Reset Interrupt (RI) is always accepted by entering the RESET signal. The reset interrupt is assigned the highest priority. (2) System Break Interrupt (SBI) System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. This interrupt can only be used in cases when after interrupt processing, control will not return to the program that was being executed when the interrupt occurred. (3) External Interrupt (EI) External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt controller. The internal interrupt controller manages these interrupts by assigning each one of eight priority levels including an interrupt-disabled state.

4.2.3 Trap

Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector addresses are provided corresponding to TRAP instruction operands 0-15.

4-4 32170/32174 Group User's Manual (Rev. 2.1) EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except for a rest interrupt, is shown below. Figure 4.3.1 Outline of EIT Processing Procedure Instruction A Instruction B Instruction C PC BPC PSW (B)PSW EIT vector entry EIT handlers except for SBI RTE instruc- tion Instruction C Instruction D •••• Program suspended EIT request accepted Instruction processing- canceled type (RIE, AE) Instruction processing -completed type (EI, TRAP) Program execution restarted EIT request generated Hardware preprocessing BPC, (B)PSW, and general-purpose registers saved to stack Branch instruc -tion General-purpose registers, (B)PSW, and BPC restored from stack SBI (System Break Interrupt processing) Hardware postprocessing (SBI) Program terminated or system is reset User-created EIT handler (B)PSW PSW BPC PC Processing by handler Note: (B)PSW denotes the BPSW field of the PSW register. EIT

4-5 32170/32174 Group User's Manual (Rev. 2.1) When an EIT is accepted, the M32R/ECU saves the PC and PSW (as will be described later) and branches to the EIT vector. The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction (note that these are not branch address) for the EIT handler is written. In the M32R/ECU's hardware preprocessing, only the contents of the PC and PSW registers are transferred to the backup registers (BPC register and the BPSW field of the PSW register), and no other operations are performed. Therefore, please make sure the BPC register, the PSW register (including the BPSW field), and the general-purpose registers to be used in the EIT handler are saved to the stack by the EIT handler you write. (Remember that these registers must be saved to the stack in a program by the user.) When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute the "RTE" instruction. Control is thereby returned from EIT processing to the program that was being executed when the EIT occurred. (This does not apply to the System Break Interrupt, however.) In the M32R/ECU's hardware postprocessing, the contents of the backup registers (BPC register and the BPSW field of the PSW register) are moved back to the PC and PSW registers. EIT

4-6 32170/32174 Group User's Manual (Rev. 2.1) The M32R/ECU's EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/Os. It also has the backup registers for the PC and PSW (BPC register and the BPSW field of the PSW register). The M32R/ECU's internal EIT processing mechanism is shown below. Figure 4.4.1 The M32R/ECU's EIT Processing Mechanism Interrupt controller (ICU) SBI EIInternal peripheral I/O RESET RI AE, RIE, TRAP IE flag (PSW) M32R CPU core SBI Low High Priority SBI EI RI M32R/ECU PSW register PSWBPSW BPC register PC register EIT

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4.5 Acceptance of EIT Event

When an EIT event occurs, the M32R/ECU suspends the program it has hitherto been executing and branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are accepted are shown below. Table 4.5.1 Acceptance of EIT Events EIT Event Type of Processing Acceptance Timing Values Set in BPC Register Reserved Instruction Instruction processing- During instruction PC value of the instruction Exception (RIE) canceled type execution which generated RIE Address Exception (AE) Instruction processing- During instruction PC value of the instruction canceled type execution which generated AE Reset Interrupt (RI) Instruction processing- Each machine cycle Indeterminate value aborted type System Break Instruction processing- Break in instructions PC value of the next instruction Interrupt (SBI) completed type (only word boundaries) External Interrupt (EI) Instruction processing- Break in instructions PC value of the next instruction completed type (only word boundaries) Trap (TRAP) Instruction processing- Break in instructions PC value of TRAP completed type instruction + 4 EIT

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4.6 Saving and Restoring the PC and PSW

The following describes operation of the M32R at the time when it accepts an EIT and when it executes the "RTE" instruction. (1) Hardware preprocessing when an EIT is accepted (a) Save the SM, IE, and C bits of the PSW register BSM ← SM BIE ← IE BC ← C (b) Update the SM, IE, and C bits of the PSW register SM ← Remains unchanged (RIE, AE, TRAP) or set to 0 (SBI, EI, RI) IE ← Set to 0 C ← Set to 0 (c) Save the PC register BPC ← PC (d) Set the vector address in the PC register Branches to the EIT vector and executes the branch instruction ("BRA" instruction) written in it, thereby transferring control to the user-created EIT handler. (2) Hardware postprocessing when the "RTE" instruction is executed (e) Restore the SM, IE, and C bits of the PSW register from their backup bits. SM ← BSM IE ← BIE C ← BC (f) Restore the value of the PC register from the BPC register PC ← BPC Note:The value of the BPC register and those of the BSM, BIE, and BC bits of the PSW register after execution of the "RTE" instruction are indeterminate. EIT

4-9 32170/32174 Group User's Manual (Rev. 2.1) Figure 4.6.1 Saving and Restoring the PC and PSW 16 17 23 24 25 31(LSB)15870(MSB) SM IE CBCBSM BIE 00000000000000000000000000PSW BPSW field PSW field EIT (b) (d) (a) Save the SM, IE, and C bits (b) Update the SM, IE, and C bits SM Unchanged/0 (c) Save the PC (d) Set the vector address in the PC PC Vector address (f) Restore the BPC value into the PC After executing the RTE instruction, the value of the BPC is indeterminate. (e) Restore the BSM, BIE, and BC bits After executing the RTE instruction, the values of the BSM, BIE, and BC bits are indeterminate. BSM BIE BC SM IE C IE C BPC PC SM IE C BSM BIE BC (C)(a) (f)(e)

4-10 32170/32174 Group User's Manual (Rev. 2.1) The EIT vector entry is located in the user space starting from address H'0000 0000. The table below lists the EIT vector entry. Table 4.7.1 EIT Vector Entry Note 1: During boot mode, this vector address is moved to the beginning of the boot ROM (address H'8000 0000). For details, refer to Section 6.5, "Programming of Internal Flash Memory." Note 2: During flash E/W enable mode, this vector address is moved to the beginning of the internal RAM (address H'0080 4000). For details, refer to Section 6.5, "Programming of Internal Flash Memory." Name AbbreviationVector Address SM IE BPC Reset Interrupt RI H'0000 0000 (Note 1) 0 0 Indeterminate System Break Interrupt SBI H'0000 0010 0 0 PC of the next instruction Reserved Instruction RIE H'0000 0020 Indeterminate 0 PC of the instruction that Exception generated EIT Address Exception AE H'0000 0030 Indeterminate 0 PC of the instruction that generated RIE Trap TRAP0 H'0000 0040 Indeterminate 0 PC of TRAP instruction + 4 TRAP1 H'0000 0044 Indeterminate 0 PC of TRAP instruction + 4 TRAP2 H'0000 0048 Indeterminate 0 PC of TRAP instruction + 4 TRAP3 H'0000 004C Indeterminate 0 PC of TRAP instruction + 4 TRAP4 H'0000 0050 Indeterminate 0 PC of TRAP instruction + 4 TRAP5 H'0000 0054 Indeterminate 0 PC of TRAP instruction + 4 TRAP6 H'0000 0058 Indeterminate 0 PC of TRAP instruction + 4 TRAP7 H'0000 005C Indeterminate 0 PC of TRAP instruction + 4 TRAP8 H'0000 0060 Indeterminate 0 PC of TRAP instruction + 4 TRAP9 H'0000 0064 Indeterminate 0 PC of TRAP instruction + 4 TRAP10 H'0000 0068 Indeterminate 0 PC of TRAP instruction + 4 TRAP11 H'0000 006C Indeterminate 0 PC of TRAP instruction + 4 TRAP12 H'0000 0070 Indeterminate 0 PC of TRAP instruction + 4 TRAP13 H'0000 0074 Indeterminate 0 PC of TRAP instruction + 4 TRAP14 H'0000 0078 Indeterminate 0 PC of TRAP instruction + 4 TRAP15 H'0000 007C Indeterminate 0 PC of TRAP instruction + 4 External Interrupt EI H'0000 0080 (Note 2) 0 0 PC of the next instruction EIT

4-11 32170/32174 Group User's Manual (Rev. 2.1)

4.8.1 Reserved Instruction Exception (RIE)

[Occurrence Conditions] Reserved Instruction Exception (RIE) is generated when execution of a reserved instruction (unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a reserved instruction exception occurs, the instruction which generated it is not executed. If an external interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved instruction exception that is accepted. [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits – the BSM, BIE, and BC bits. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below. SM ← Unchanged BIE ← 0 BC ← 0 (3) Saving PC The PC value of the instruction that generated the reserved instruction exception is set in the BPC register. For example, if the instruction that generated the reserved instruction exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC[30] = 0) or not on a word boundary (BPC[30] = 1). However, in either case of the above, the address to which the "RTE" instruction returns after completion of processing by the EIT handler is address 4. (This is because the two low-order bits are cleared to "00" when returning to the PC.) EIT

4-12 32170/32174 Group User's Manual (Rev. 2.1) Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE) (4) Branching to the EIT vector entry Control branches to the address H'0000 0020 in the user space. This is the last operation performed in hardware preprocessing by the M32R/ECU. (5) Jumping from the EIT vector entry to the user-created handler The M32R/ECU executes the "BRA" instruction written at address H'0000 0020 of the EIT vector entry by the user to jump to the start address of the user-created handler. At the beginning of the EIT handler you created, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and then execute the "RTE" instruction. As you execute the "RTE" instruction, hardware postprocessing is automatically performed by the M32R/ECU. H’00 Address RIE occurredH’04 H’08 H’0C +0 +1 +2 +3 H’00 Address RIE occurredH’04 H’08 H’0C +0 +1 +2 +3 Return address Return address BPC H’06BPC H’04 EIT

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4.8.2 Address Exception (AE)

[Occurrence Conditions] Address Exception (AE) is generated when an attempt is made to access a misaligned address in Load or Store instructions. The following lists the combination of instructions and accessed addresses that may cause address exceptions to occur:

• When the LDH, LDUH, or STH instruction accesssed an address whose two low-order bits are "01" or "11"
• When the LD, ST, LOCK, or UNLOCK instruction accessed an address whose two low-order When an address exception occurs, memory access by the instruction that generated the exception is not performed. If an external interrupt is requested at the same time an address exception is detected, it is the address exception that is accepted. [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits – the BSM, BIE, and BC bits. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving PC The PC value of the instruction that generated the address exception is set in the BPC register. For example, if the instruction that generated the address exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the address exception resides on a word boundary (BPC[30] = 0) or not on a word boundary (BPC[30] = 1). However, in either case of the above, the address to which the "RTE" instruction returns after completion of processing by the EIT handler is address 4. (This is because the two low-order bits are cleared to "00" when returning to the PC.) EIT

4-14 32170/32174 Group User's Manual (Rev. 2.1) Figure 4.8.2 Example of a Return Address for Address Exception (AE) (4) Branching to the EIT vector entry Control branches to the address H'0000 0030 in the user space. This is the last operation performed in hardware preprocessing by the M32R/ECU. (5) Jumping from the EIT vector entry to the user-created handler The M32R/ECU executes the "BRA" instruction written at address H'0000 0030 of the EIT vector entry by the user to jump to the start address of the user-created handler. At the beginning of the EIT handler you created, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and then execute the "RTE" instruction. As you execute the "RTE" instruction, hardware postprocessing is automatically performed by the M32R/ECU. H ’00 Address AE occurredH ’04 H ’08 H ’0C +0 +1 +2 +3 H ’00 Address AE occurredH ’04 H ’08 H ’0C +0 +1 +2 +3 Return address Return address BPC H ’06BPC H ’04 EIT

4-15 32170/32174 Group User's Manual (Rev. 2.1)

4.9.1 Reset Interrupt (RI)

[Occurrence Conditions] Reset Interrupt (RI) is unconditionally accepted in any machine cycle by pulling the RESET input signal low. The reset interrupt is assigned the highest priority among all EITs. [EIT Processing] (1) Initializing SM, IE, and C bits The SM, IE, and C bits of the PSW register are initialized in the manner shown below. For the reset interrupt, the values of BSM, BIE, and BC bits are indeterminate. SM ← 0 IE ← 0 C ← 0 (2) Branching to the EIT vector entry Control branches to the address H'0000 0000 in the user space. However, when operating in boot mode, control goes to the beginning of the boot ROM (address H'8000 0000). For details, refer to Section 6.5, "Programming of Internal Flash Memory." (3) Jumping from the EIT vector entry to the user program The M32R/ECU executes the instruction written at address H'0000 0000 of the EIT vector entry by the user. In the reset vector entry, be sure to initialize the PSW and SPI registers before jumping to the start address of the program you created. EIT

4-16 32170/32174 Group User's Manual (Rev. 2.1)

4.9.2 System Break Interrupt (SBI)

System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt cannot be masked by the PSW register IE bit. Therefore, the system break interrupt can only be used when some fatal event has already occurred to the system when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred. [Occurrence Conditions] A system break interrupt is accepted by a falling edge on SBI input pin. (The system break interrupt cannot be masked by the PSW register IE bit.) In no case will a system break interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt may be accepted immediately after branching.) Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted 16-bit instruction Order in which instructions are executed Address 1000 Interrupt may be accepted Interrupt cannot be accepted Address 1002 Address 1004 Address 1008 16-bit instruction 32-bit instruction Interrupt may be accepted Interrupt may be accepted EIT

4-17 32170/32174 Group User's Manual (Rev. 2.1) [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits-the BSM, BIE, and BC bits. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving PC The content (always word boundary) of the PC register is saved to the BPC register. (4) Branching to the EIT vector entry Control branches to the address H'0000 0010 in the user space. This is the last operation performed in hardware preprocessing by the M32R/ECU. (5) Jumping from the EIT vector entry to the user-created handler The M32R/ECU executes the "BRA" instruction written at address H'0000 0010 of the EIT vector entry by the user to jump to the start address of the user-created handler. The system break interrupt can only be used when some fatal event has occurred to the system. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred. EIT

4-18 32170/32174 Group User's Manual (Rev. 2.1)

4.9.3 External Interrupt (EI)

An external interrupt is generated upon an interrupt request which is output by the internal interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority levels. For details, refer to Chapter 5, "Interrupt Controller." For details about the interrupt sources, refer to each section in which the relevant internal peripheral I/O is described. [Occurrence Conditions] External interrupts are managed based on interrupt requests from each internal peripheral I/O by the internal interrupt controller. These interrupt requests are notified to the M32R CPU by the interrupt controller. The M32R/ECU checks these interrupt requests at a break in instructions residing on word boundaries, and when an interrupt request is detected and the PSW register IE flag = 1, accepts it as an external interrupt. In no case will an external interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt may be accepted immediately after branching.) Figure 4.9.2 Timing at Which External Interrupt (EI) is Accepted 16-bit instruction Order in which instructions are executed Address 1000 Interrupt may be accepted Interrupt cannot be accepted Address 1002 Address 1004 Address 1008 16-bit instruction 32-bit instruction Interrupt may be accepted Interrupt may be accepted EIT

4-19 32170/32174 Group User's Manual (Rev. 2.1) [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits – the BSM, BIE, and BC bits. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving PC The content (always word boundary) of the PC register is saved to the BPC register. (4) Branching to the EIT vector entry Control branches to the address H'0000 0080 in the user space. However, when operating in flash E/W enable mode, control goes to the beginning of the internal RAM (address H'0080 4000). (For details, refer to Section 6.5, "Programming of Internal Flash Memory.") This is the last operation performed in hardware preprocessing by the M32R/ECU. (5) Jumping from the EIT vector entry to the user-created handler The M32R/ECU executes the "BRA" instruction written at address H'0000 0080 of the EIT vector entry by the user to jump to the start address of the user-created handler. At the beginning of the EIT handler you created, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and then execute the "RTE" instruction. As you execute the "RTE" instruction, hardware postprocessing is automatically performed by the M32R/ECU. EIT

4-20 32170/32174 Group User's Manual (Rev. 2.1)

4.10.1 Trap (TRAP)

[Occurrence Conditions] Traps refer to software interrupts which are generated by executing the "TRAP" instruction. Sixteen distinct traps are generated, each corresponding to one of "TRAP" instruction operands 0-15. Accordingly, sixteen vector entries are provided. [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits – the BSM, BIE, and BC bits. BSM ← SM BIE ← IE BC ← C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below. Unchanged SM ← 0 IE ← 0 C ← 0 (3) Saving PC When the trap instruction is executed, the "PC value of the TRAP instruction + 4" is set in the BPC register. For example, if the "TRAP" instruction is located at address 4, the value H'08 is set in the BPC register. Similarly, if the instruction is located at address 6, the value H'0A is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the trap instruction resides on a word boundary (BPC[30] = 0) or not on a word boundary (BPC[30] = 1). However, in either case of the above, the address to which the "RTE" instruction returns after completion of processing by the EIT handler is address 8. (This is because the two low-order bits are cleared to "00" when returning to the PC.) Normally, when the program has been written in assembler, the halfword that immediately follows the "TRAP" instruction placed at a word boundary has the "NOP" instruction automatically inserted by the assembler. EIT

4-21 32170/32174 Group User's Manual (Rev. 2.1) Figure 4.10.1 Example of a Return Address for Trap (TRAP) (4) Branching to the EIT vector entry Control branches to the addresses H'0000 0040 through H'0000 007C in the user space. This is the last operation performed in hardware preprocessing by the M32R/ECU. (5) Jumping from the EIT vector entry to the user-created handler The M32R/ECU executes the "BRA" instruction written at addresses H'0000 0040 through H'0000 007C of the EIT vector entry by the user to jump to the start address of the user- created handler. At the beginning of the EIT handler you created, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and then execute the "RTE" instruction. As you execute the "RTE" instruction, hardware postprocessing is automatically performed by the M32R/ECU. H ’00 H ’04 H ’08 H ’0C +0 +1 +2 +3 H ’00 H ’04 H ’08 H ’0C +0 +1 +2 +3 BPC H ’0ABPC H ’08 Address TRAP occurredReturn addressReturn address Address TRAP occurred EIT

4-22 32170/32174 Group User's Manual (Rev. 2.1) The table below lists the priority levels of EIT events. When multiple EITs occur simultaneously, the event with the highest priority is accepted first. Table 4.11.1 Priority of EIT Events and How Returned from EIT Note that for External Interrupt (EI), the priority levels of interrupt requests from each peripheral I/O are set by the internal interrupt controller. For details, refer to Chapter 5, "Interrupt Controller." PriorityEIT Event Type of Processing Values Set in BPC Register 1(Highest) Reset Interrupt (RI) Instruction processing Indeterminate -aborted type Address Exception (AE) Instruction processing- PC of the instruction that canceled type generated AE Reserved Instruction Instruction processing- PC of the instruction that Exception (RIE) canceled type generated AE Trap (TRAP) Instruction processing- TRAP instruction + 4 completed type

3 System Break Instruction processing- PC of the next instruction

Interrupt (SBI) completed type

4 External Interrupt (EI) Instruction processing- PC of the next instruction

4-23 32170/32174 Group User's Manual (Rev. 2.1) (1) When RIE, AE, SBI, EI, or TRAP occurs singly Figure 4.12.1 Processing of Events When RIE, AE, SBI, EI, or TRAP Occurs Singly (2) When RIE, AE, or TRAP and EI occurs simultaneously Figure 4.12.2 Processing of Events when RIE, AE, or TRAP and EI Occurs Simultaneously RTE instruction IE=0 IE=1 BPC register = Return address A IE=1 RIE, AE, SBI, EI, or TRAP occurrs Singly Return address A: If IE = 0, no events but reset and SBI are accepted :EIT handler RIE, AE, or TRAP is accepted first BPC register = Return address A RIE, AE, or TRAP and EI occurs simultaneously EI is accepted next BPC register = Return address A RTE instruction IE=0 IE=1 IE=1 Return address A: :EIT handler IE=0 IE=1 RTE instruction EIT

4-24 32170/32174 Group User's Manual (Rev. 2.1) BRA instruction RTE EIT handler EIT vector entry Program being executed Save BPC to stack Save PSW to stack Save general-purpose registers to stack Processing by EIT handler Restore general- purpose registers Restore PSW Restore BPC EIT event occurs (SBI) System Break Interrupt processing Program terminated or system reset (Any event other than SBI) PC BPC PSW (B)PSWHardware preprocessing Hardware postprocessing (B)PSW PSW BPC PC EIT Figure 4.12.3 Example of EIT Processing

4-25 32170/32174 Group User's Manual (Rev. 2.1) Address Exception requires caution because when an address exception occurs pursuant to execution of an instruction (one of the following three) that uses the “register indirect + register update” addressing mode, the value of the automatically updated register (Rsrc or Rsrc2) becomes indeterminate. Except that the values of Rsrc and Rsrc2 are indeterminate, the behavior is the same as when using other addressing modes.  Applicable instructions LD Rdest, @Rsrc+ ST Rsrc1, @-Rsrc2 ST Rsrc1, @+Rsrc2 If the above applies, because the register value becomes indeterminate as explained, consideration must be taken before continuing with system processing. (If an address exception occurs, it means that some fatal fault already occurred in the system at that point in time. Therefore, use EIT on condition that after processing by the address exception handler, the CPU will not return to the program it was executing when the exception occurred.) EIT

4-26 32170/32174 Group User's Manual (Rev. 2.1) ❊ This is a blank page. ❊ EIT

CONTROLLER (ICU)

5.1 Outline of Interrupt Controller

(ICU)

5.2 Interrupt Sources of Internal

5.3 ICU-Related Registers

5.4 ICU Vector Table

5.5 Description of Interrupt Operation

5.6 Description of System Break

Interrupt (SBI) Operation

5-2 32170/32174 Group User's Manual (Rev. 2.1) INTERRUPT CONTROLLER (ICU)

5.1 Outline of the Interrupt Controller (ICU)

5.1 Outline of Interrupt Controller (ICU)

The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are notified to the M32R CPU as external interrupts (EI). There are a total of 31 interrupt sources for the maskable interrupts from internal peripheral I/Os, which are managed by assigning them one of eight priority levels including an interrupt-disabled state. When multiple interrupt requests of the same priority level occur simultaneously, their priorities are resolved by predetermined hardware priority. The source of an interrupt request generated in internal peripheral I/Os is identified by reading the relevant interrupt status register provided for internal peripheral I/Os. On the other hand, the system break interrupt (SBI) is recognized when a low-going transition occurs on the SBI signal input pin. This interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer, so that it is always accepted irrespective of the PSW register IE bit status. When the ICU has finished servicing an SBI, terminate or reset the system without returning to the program that was being executed when the interrupt occurred. Specifications of the interrupt controller are outlined in the table below. Table 5.1.1 Outline of Interrupt Controller (ICU) Item Specification Interrupt source Maskable interrupt from internal peripheral I/O : 31 sources System break interrupt ___ : 1 source (entered from SBI pin) Level management Eight levels including an interrupt-disabled state (However, interrupts of the same level have their priorities resolved by fixed hardware priority.)

5-3 32170/32174 Group User's Manual (Rev. 2.1) INTERRUPT CONTROLLER (ICU) Figure 5.1.1 Block Diagram of the Interrupt Controller Interrupt Vector Register( IVECT) Interrupt Mask Register (IMASK) NEW_IMASK Maskable interrupt request generated Priority resolution by fixed hardware priority IMASK Compar- ed ILEVEL Priority resolution by interrupt priority levels set System Break Interrupt request generated SBI EI SBI Interrupt controller Interrupt Control Register SBI Control Register (SBICR) SBIREQ IREQ IREQ IREQ IREQ IREQ IREQ Peripheral circuits Edge- recognized Interrupt control circuit Level- recognized Interrupt request Interrupt request Interrupt request To the CPU core Edge- recognized Edge- recognized Level- recognized Level- recognized Interrupt control circuit Interrupt control circuit To the CPU core

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5.2 Interrupt Sources of Internal Peripheral I/Os

The interrupt controller receives as its inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O, A-D converter, RTD, and CAN. For details about these interrupts, refer to each section in which the relevant internal peripheral I/O is described. Table 5.2.1 Interrupt Sources of Internal Peripheral I/Os (1/2) Interrupt Cause Contents Number of Input ICU Type of Input Sources Source(Note) A-D0 conversion interrupt 1 Edge-recognized A-D1 conversion interrupt 1 Edge-recognized SIO0 transmit interrupt 1 Edge-recognized SIO0 receive interrupt 1 Edge-recognized SIO1transmit interrupt 1 Edge-recognized SIO1 receive interrupt 1 Edge-recognized SIO2,3 transmit/receive 4 Level-recognized interrupt SIO4,5 transmit/receive 4 Level-recognized interrupt TID0 output interrupt 1 Edge-recognized TID1 output interrupt 1 Edge-recognized TID2 output interrupt 1 Edge-recognized TOD0 output interrupt 8 Level-recognized TOD1 + TOM0 output 16 Level-recognized interrupt TML1 input interrupt 4 Level-recognized RTD interrupt 1 Edge-recognized DMA transfer interrupt 0 5 Level-recognized DMA transfer interrupt 1 5 Level-recognized CAN0 transmit/receive 5 Level-recognized & error interrupt Note: ICU type of input source

• Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal applied to the ICU.
• Level-recognized: Interrupt requests are generated when the interrupt signal applied to the ICU is held low. For these level-recognized interrupts, the ICU's Interrupt Control Register IRQ bit cannot be set or cleared in software. Single-shot conversion in A-D0 converter scan mode completed, single mode completed, or comparator mode completed Single-shot conversion in A-D1 converter scan mode completed, single mode completed, or comparator mode completed SIO0 transmit buffer empty interrupt SIO0 reception completed or receive error interrupt SIO1 transmit buffer empty interrupt SIO1 reception completed or receive error interrupt SIO2, 3 reception completed or receive error interrupt Transmit buffer empty interrupt SIO4, 5 reception completed or receive error interrupt Transmit buffer empty interrupt TID0 output TID1 output TID2 output TOD0_0 to TOD0_7 output TOD1_0 to TOD1_7 output + TOM0_0 to TOM0_7 output TML1 input (TIN30 to TIN33 input) RTD interrupt generation command DMA0-4 transfer completed DMA5-9 transfer completed CAN0 transmission completed, CAN0 reception completed, CAN0 error passive, CAN0 error bus-off, CAN0 bus error INTERRUPT CONTROLLER (ICU)

5-5 32170/32174 Group User's Manual (Rev. 2.1) Table 5.2.2 Interrupt Sources of Internal Peripheral I/Os (2/2) Interrupt Source Content Number of Input ICU Type of Input Sources Source (Note) MJT output interrupt 7 MJT output interrupt group 7 (TMS0, TMS1 output)2 Level-recognized MJT output interrupt 6 MJT output interrupt group 6 (TOP8, TOP9 output)2 Level-recognized MJT output interrupt 5 MJT output interrupt group 5 (TOP10 output) 1 Edge-recognized MJT output interrupt 4 MJT output interrupt group 4 (TIO4 - TIO7 output)4 Level-recognized MJT output interrupt 3 MJT output interrupt group 3 (TIO8, TIO9 output)2 Level-recognized MJT output interrupt 2 MJT output interrupt group 2 (TOP0 - TOP5 output)6 Level-recognized MJT output interrupt 1 MJT output interrupt group 1 (TOP6, TOP7 output)2 Level-recognized MJT output interrupt 0 MJT output interrupt group 0 (TIO0 - TIO3 output)4 Level-recognized MJT input interrupt 4 MJT input interrupt group 4 (TIN3-TIN6 input)4 Level-recognized MJT input interrupt 3 MJT input interrupt group 3 (TIN20-TIN23 input)4 Level-recognized MJT input interrupt 2 MJT input interrupt group 2 (TIN12-TIN19 input)8 Level-recognized MJT input interrupt 1 MJT input interrupt group 1 (TIN0-TIN2 input)3 Level-recognized MJT input interrupt 0 MJT input interrupt group 0 (TIN7-TIN11 input)5 Level-recognized Note: ICU type of input source

• Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal applied to the ICU.
• Level-recognized: Interrupt requests are generated when the interrupt signal applied to the ICU is held low. For these level-recognized interrupts, the ICU's Interrupt Control Register IRQ bit cannot be set or cleared in software. INTERRUPT CONTROLLER (ICU)

5-6 32170/32174 Group User's Manual (Rev. 2.1) The diagram below shows a map of the Interrupt Controller (ICU)'s related registers. Figure 5.3.1 Interrupt Controller (ICU) Related Register Map INTERRUPT CONTROLLER (ICU) H’0080 0000 Address D0 D7 +0 Address +1 AddressD8 D15 H’0080 0004 H’0080 0006 H’0080 0066 H’0080 0068 Interrupt Mask Register (IMASK) SBI Control Register (SBICR) H’0080 006A H’0080 006C H’0080 006E H’0080 0070 H’0080 0072 H’0080 0074 H’0080 0076 H’0080 0078 H’0080 0002 H’0080 007A H’0080 007C H’0080 007E A-D0 Conversion Interrupt Control Register (IAD0CCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) SIO1 Receive Interrupt Control Register (ISIO1RXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) SIO0 Transmit Interrupt Control Register (ISIO0TXCR) DMA0-4 Interrupt Control Register (IDMA04CR) MJT Output Interrupt Control Register 0 (IMJTOCR0) MJT Output Interrupt Control Register 2 (IMJTOCR2) MJT Output Interrupt Control Register 4 (IMJTOCR4) MJT Output Interrupt Control Register (IMJTOCR6) MJT Output Interrupt Control Register (IMJTOCR1) MJT Output Interrupt Control Register 3 (IMJTOCR3) MJT Output Interrupt Control Register5 (IMJTOCR5) MJT Output Interrupt Control Register7 (IMJTOCR7) MJT Input Interrupt Control Register 0 (IMJTICR0) MJT Input Interrupt Control Register 1 (IMJTICR1) MJT Input Interrupt Control Register 2 (IMJTICR2) MJT Input Interrupt Control Register 3 (IMJTICR3) MJT Input Interrupt Control Register 4 (IMJTICR4) TID1 Output Interrupt Control Register (ITID1CR) SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) RTD Interrupt Control Register (IRTDCR) DMA5-9 Interrupt Control Register (IDMA59CR) TOD0 Output Interrupt Control Register (ITOD0CR) TID0 Output Interrupt Control Register (ITID0CR) Interrupt Vector Register (IVECT) Note: The registers in the thick frames must always be accessed in halfwords. H’0080 0060CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) TML1 Input Interrupt Control Register (ITML1CR) H’0080 0062TID2 Output Interrupt Control Register (ITID2CR) A-D1 Conversion Interrupt Control Register (IAD1CCR) H’0080 0064SIO4,5 Transmit/Receive Interrupt Control Register (ISIO45CR) TOD1+TOM0 Output Interrupt Control Register (ITOM0CR) Blank addresses are reserved for future use.

5-7 32170/32174 Group User's Manual (Rev. 2.1)

5.3.1 Interrupt Vector Register

I Interrupt Vector Register (IVECT) <Address:H'0080 0000> <When reset: Indeterminate> D Bit Name Function R W 0 – 15 IVECT (16 low-order When an interrupt is accepted, the 16 low-order bits– bits of ICU vector in ICU vector table address for the accepted table address) interrupt source is stored in this register. Note: This register must always be accessed in halfwords. The Interrupt Vector Register (IVECT) is used when an interrupt is accepted to store the 16 low- order bits of ICU vector table address for the accepted interrupt source. Before this function can work, the ICU vector table (addresses H'0000 0094 through H'0000 010F) must have set in it the start addresses of interrupt handlers for each internal peripheral I/O. When an interrupt is accepted, the 16 low-order bits of ICU vector table address for the accepted interrupt source is stored in this IVECT register. The EIT handler reads out the content of the IVECT register by the "LDH" instruction to acquire the ICU vector table address. When the IVECT register is read out, operations (1) to (4) below are automatically performed in hardware: (1) The accepted new IMASK (NEW_IMASK) is set in the IMASK register. (2) The accepted interrupt request is cleared (not cleared for level-recognized interrupt sources). (3) The interrupt request (EI) to the CPU core is cleared. (4) The ICU's internal sequencer is activated to start internal processing (interrupt priority resolution). Do not read the Interrupt Vector Register (IVECT) unless the PSW Register IE bit is disabled in the EIT handler. Also, make sure that in the EIT handler, the Interrupt Mask Register (IMASK) is read out before reading out the IVECT register. CAUTION D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 IVECT INTERRUPT CONTROLLER (ICU)

5-8 32170/32174 Group User's Manual (Rev. 2.1)

5.3.2 Interrupt Mask Register

I Interrupt Mask Register (IMASK) <Address:H'0080 0004> The Interrupt Mask Register (IMASK) is used to finally determine whether an interrupt request can be accepted after comparing its priority with the priority levels that have been set for each interrupt source (by setting the Interrupt Control Register ILEVEL bits). When the Interrupt Vector Register (IVECT) described above is read out, a new mask value (NEW_IMASK) is set in this IMASK register. When any value is written to the IMASK register, operations (1) to (2) below are automatically performed in hardware: (1) The interrupt request (EI) to the CPU core is cleared. (2) The ICU's internal sequencer is activated to start internal processing (interrupt priority resolution). Do not write to the Interrupt Mask Register (IMASK) unless the PSW Register IE bit is disabled in the EIT handler. <When reset: H''07> D Bit Name Function R W 0 – 4 No functions assigned 0 – 5– 7 IMASK (Interrupt mask) 000 : Maskable interrupts are disabled 001 : Level 0 interrupts can be accepted 010 : Level 0-1 interrupts can be accepted 011 : Level 0-2 interrupts can be accepted 100 : Level 0-3 interrupts can be accepted 101 : Level 0-4 interrupts can be accepted 110 : Level 0-5 interrupts can be accepted 111 : Level 0-6 interrupts can be accepted D 0 123456 D 7 IMASK INTERRUPT CONTROLLER (ICU)

5-9 32170/32174 Group User's Manual (Rev. 2.1)

5.3.3 SBI (System Break Interrupt) Control Register

I SBI (System Break Interrupt) Control Register <Address:H'0080 0006> W = : Writable for only clearing operation (see the description below) The SBI (System Break Interrupt) is an interrupt generated by a falling edge on SBI signal input pin. When an SBI occurs, the SBI Control Register's SBIREQ (SBI request) bit is set to 1. The SBIREQ bit cannot be set in software. To clear the SBIREQ bit after being set, perform the operation described below. (Be careful not to clear this bit when no SBI request has been generated.)

• Write a 1 and then a 0 to SBIREQ. <When reset: H''00> D Bit Name Function R W 0 – 6 No functions assigned 0 –

7 SBI REQ (SBI request) 0 : SBI is not requested

1 : SBI is requested D 0 123456 D 7 SBIREQ INTERRUPT CONTROLLER (ICU)

5-10 32170/32174 Group User's Manual (Rev. 2.1)

5.3.4 Interrupt Control Registers

I CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR)<Address:H'0080 0060> I TML1 Interrupt Control Register (ITML1CR) <Address:H'0080 0061> I TID2 Output Interrupt Control Register (ITID2CR) <Address:H'0080 0062> I A-D1 Converter Interrupt Control Register (IAD1CCR) <Address:H'0080 0063> I SIO4,5 Transmit/Receive Interrupt Control Register (ISIO45CR) <Address:H'0080 0064> I TOD1+TOM0 Output Interrupt Control Register (ITOM0CR) <Address:H'0080 0065> I TID1 Output Interrupt Control Register (ITID1CR) <Address:H'0080 0066> I RTD Interrupt Control Register (IRTDCR) <Address:H'0080 0067> I SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) <Address:H'0080 0068> I DMA5-9 Interrupt Control Register (IDMA59CR) <Address:H'0080 0069> I TOD0 Output Interrupt Control Register (ITOD0CR) <Address:H'0080 006A> I TID0 Output Interrupt Control Register (ITID0CR) <Address:H'0080 006B> I A-D0 Converter Interrupt Control Register (IAD0CCR) <Address:H'0080 006C> I SIO0 Transmit Interrupt Control Register (ISIO0TXCR) <Address:H'0080 006D> I SIO0 Receive Interrupt Control Register (ISIO0RXCR) <Address:H'0080 006E> I SIO1 Transmit Interrupt Control Register (ISIO1TXCR) <Address:H'0080 006F> I SIO1 Receive Interrupt Control Register (ISIO1RXCR) <Address:H'0080 0070> I DMA0-4 Interrupt Control Register (IDMA04CR) <Address:H'0080 0071> I MJT Output Interrupt Control Register 0 (IMJTOCR0) <Address:H'0080 0072> I MJT Output Interrupt Control Register 1 (IMJTOCR1) <Address:H'0080 0073> I MJT Output Interrupt Control Register 2 (IMJTOCR2) <Address:H'0080 0074> I MJT Output Interrupt Control Register 3 (IMJTOCR3) <Address:H'0080 0075> I MJT Output Interrupt Control Register 4 (IMJTOCR4) <Address:H'0080 0076> I MJT Output Interrupt Control Register 5 (IMJTOCR5) <Address:H'0080 0077> I MJT Output Interrupt Control Register 6 (IMJTOCR6) <Address:H'0080 0078> I MJT Output Interrupt Control Register 7 (IMJTOCR7) <Address:H'0080 0079> I MJT Input Interrupt Control Register 0 (IMJTICR0) <Address:H'0080 007A> I MJT Input Interrupt Control Register 1 (IMJTICR1) <Address:H'0080 007B> I MJT Input Interrupt Control Register 2 (IMJTICR2) <Address:H'0080 007C> I MJT Input Interrupt Control Register 3 (IMJTICR3) <Address:H'0080 007D> I MJT Input Interrupt Control Register 4 (IMJTICR4) <Address:H'0080 007E> INTERRUPT CONTROLLER (ICU)

5-11 32170/32174 Group User's Manual (Rev. 2.1) W= : Can be set and cleared only when the type of input source is "Edge-recognized" type (with only one interrupt source being input). (1) IREQ (Interrupt Request) bit (D3 or D11) When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Request) bit is set to 1. This bit can be set and cleared in software for only edge-recognized interrupt sources (and not for level-recognized interrupt sources). Also, when the IREQ bit is set by an interrupt request generated by an edge-recognized interrupt source, it is automatically cleared to 0 by reading out the Interrupt Vector Register (IVECT) (not cleared in the case of level-recognized interrupt sources). If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in software has priority. Also, if the IREQ bit is cleared by reading out the IVECT register at the same time it is set by an interrupt request generated, clearing by a read of IVECT has priority. <When reset: H''07> D Bit Name Function R W 0 – 2 No functions assigned 0 – (8-10)

3 IREQ (Interrupt request) 0 : Interrupt is not requested

(11) 1 : Interrupt is requested

4 No functions assigned 0 –

(12) 5-7 ILEVEL (Interrupt priority level)000 : Interrupt priority level 0 (13-15) 001 : Interrupt priority level 1 010 : Interrupt priority level 2 011 : Interrupt priority level 3 100 : Interrupt priority level 4 101 : Interrupt priority level 5 110 : Interrupt priority level 6 111 : Interrupt priority level 7 (Interrupt-disabled state) D 0 123456 D 7 (D8 9 10 11 12 13 14 D15) IREQ ILEVEL INTERRUPT CONTROLLER (ICU)

5-12 32170/32174 Group User's Manual (Rev. 2.1) Figure 5.3.2 Interrupt Control Register Configuration (Edge-recognized Type) Figure 5.3.3 Interrupt Control Register Configuration (Level-recognized Type) INTERRUPT CONTROLLER (ICU) (Levels 0-7) D3,11Data bus D5-7,13-15 3 F/F set set/clear IREQ D3,11 D5-7,13-15 RD IREQ Group interrupt Interrupt priority resolving circuit Group Interrupt request from each peripheral function Interrupt enabled ILEVEL (Levels 0-7) Data bus Read-only circuit

5-13 32170/32174 Group User's Manual (Rev. 2.1) (2) ILEVEL (Interrupt Priority Level) (D5-D7 or D13-D15) These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set priority level 7 to disable interrupts from some internal peripheral I/O or priority levels 0-6 to enable interrupts. When an interrupt occurs, the interrupt controller resolves priority between this interrupt and other interrupt sources based on ILEVEL settings and finally compares its priority with the IMASK value to determine whether to forward an EI request to the CPU or keep it pending. The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts are accepted. Table 5.3.1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 (ILEVEL="000") Accepted when IMASK is 1-7 1 (ILEVEL="001") Accepted when IMASK is 2-7 2 (ILEVEL="010") Accepted when IMASK is 3-7 3 (ILEVEL="011") Accepted when IMASK is 4-7 4 (ILEVEL="100") Accepted when IMASK is 5-7 5 (ILEVEL="101") Accepted when IMASK is 6-7 6 (ILEVEL="110") Accepted when IMASK is 7 7 (ILEVEL="111") Not accepted (interrupts disabled) INTERRUPT CONTROLLER (ICU)

5-14 32170/32174 Group User's Manual (Rev. 2.1) The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The 31-source interrupts are assigned the following addresses: Table 5.4.1 ICU Vector Table Addresses Interrupt Source ICU Vector Table Address MJT Input Interrupt 4 H'0000 0094-H'0000 0097 MJT Input Interrupt 3 H'0000 0098-H'0000 009B MJT Input Interrupt 2 H'0000 009C-H'0000 009F MJT Input Interrupt 1 H'0000 00A0-H'0000 00A3 MJT Input Interrupt 0 H'0000 00A4-H'0000 00A7 MJT Output Interrupt 7 H'0000 00A8-H'0000 00AB MJT Output Interrupt 6 H'0000 00AC-H'0000 00AF MJT Output Interrupt 5 H'0000 00B0-H'0000 00B3 MJT Output Interrupt 4 H'0000 00B4-H'0000 00B7 MJT Output Interrupt 3 H'0000 00B8-H'0000 00BB MJT Output Interrupt 2 H'0000 00BC-H'0000 00BF MJT Output Interrupt 1 H'0000 00C0-H'0000 00C3 MJT Output Interrupt 0 H'0000 00C4-H'0000 00C7 DMA0-4 Interrupt H'0000 00C8-H'0000 00CB SIO1 Receive Interruptt H'0000 00CC-H'0000 00CF SIO1 Transmit Interruptt H'0000 00D0-H'0000 00D3 SIO0 Receive Interruptt H'0000 00D4-H'0000 00D7 SIO0 Transmit Interruptt H'0000 00D8-H'0000 00DB A-D0 Converter Interruptt H'0000 00DC-H'0000 00DF TID0 Output Interruptt H'0000 00E0-H'0000 00E3 TOD0 Output Interruptt H'0000 00E4-H'0000 00E7 DMA5-9 Interruptt H'0000 00E8-H'0000 00EB SIO2,3 Transmit/Receive Interrupt t H'0000 00EC-H'0000 00EF RTD Interruptt H'0000 00F0-H'0000 00F3 TID1 Output Interrupt H'0000 00F4-H'0000 00F7 TOD1+TOM0 Output Interrupt H'0000 00F8-H'0000 00FB SIO4,5 Transmit/Receive Interrupt H'0000 00FC-H'0000 00FF A-D1 Converter Interrupt H'0000 0100-H'0000 0103 TID2 Output Interrupt H'0000 0104-H'0000 0107 TML1 Input Interrupt H'0000 0108-H'0000 010B CAN0 Transmit/Receive & Error Interrupt H'0000 010C-H'0000 010F INTERRUPT CONTROLLER (ICU)

5-15 32170/32174 Group User's Manual (Rev. 2.1) Figure 5.4.1 ICU Vector Table Memory Map (1/2) H'0000 0094 Address D0 D7 +0 Address +1 AddressD8 D15 H'0000 0096 MJT Input Interrupt 4 Handler Start Address (A0-A15) MJT Input Interrupt 4 Handler Start Address (A16-A31) H'0000 0098 H'0000 009A MJT Input Interrupt 3 Handler Start Address (A0-A15) MJT Input Interrupt 3 Handler Start Address (A16-A31) H'0000 009C H'0000 009E MJT Input Interrupt 2 Handler Start Address (A0-A15) MJT Input Interrupt 2 Handler Start Address (A16-A31) H'0000 00A0 H'0000 00A2 MJT Input Interrupt 1 Handler Start Address (A0-A15) MJT Input Interrupt 1 Handler Start Address (A16-A31) H'0000 00A4 H'0000 00A6 H'0000 00A8 H'0000 00AA H'0000 00AC H'0000 00AE H'0000 00B0 H'0000 00B2 H'0000 00B4 H'0000 00B6 H'0000 00B8 H'0000 00BA H'0000 00BC H'0000 00BE H'0000 00C0 H'0000 00C2 H'0000 00C4 H'0000 00C6 MJT Output Interrupt 7 Handler Start Address (A0-A15) MJT Output Interrupt 7 Handler Start Address (A16-A31) MJT Output Interrupt 6 Handler Start Address (A0-A15) MJT Output Interrupt 6 Handler Start Address (A16-A31) MJT Output Interrupt 5 Handler Start Address (A0-A15) MJT Output Interrupt 5 Handler Start Address (A16-A31) MJT Output Interrupt 4 Handler Start Address (A0-A15) MJT Output Interrupt 4 Handler Start Address (A16-A31) MJT Output Interrupt 3 Handler Start Address (A0-A15) MJT Output Interrupt 3 Handler Start Address (A16-A31) MJT Output Interrupt 2 Handler Start Address (A0-A15) MJT Output Interrupt 2 Handler Start Address (A16-A31) MJT Output Interrupt 1 Handler Start Address (A0-A15) MJT Output Interrupt 1 Handler Start Address (A16-A31) MJT Output Interrupt 0 Handler Start Address (A0-A15) MJT Output Interrupt 0 Handler Start Address (A16-A31) MJT Input Interrupt 0 Handler Start Address (A0-A15) MJT Input Interrupt 0 Handler Start Address (A16-A31) INTERRUPT CONTROLLER (ICU)

5-16 32170/32174 Group User's Manual (Rev. 2.1) Figure 5.4.2 ICU Vector Table Memory Map (2/2) H'0000 00C8 Address D0 D7 +0 Address +1 Address D8 D15 H'0000 00CA DMA0-4 Interrupt Handler Start Address (A0-A15) DMA0-4 Interrupt Handler Start Address (A16-A31) H'0000 00CC H'0000 00CE H'0000 00D0 H'0000 00D2 H'0000 00D4 H'0000 00D6 H'0000 00D8 H'0000 00DA H'0000 00DC H'0000 00DE SIO1 Receive Interrupt Handler Start Address (A0-A15) SIO1 Receive Interrupt Handler Start Address (A16-A31) SIO1 Transmit Interrupt Handler Start Address (A0-A15) SIO1 Transmit Interrupt Handler Start Address (A16-A31) SIO0 Receive Interrupt Handler Start Address (A0-A15) SIO0 Receive Interrupt Handler Start Address (A16-A31) SIO0 Transmit Interrupt Handler Start Address (A0-A15) SIO0 Transmit Interrupt Handler Start Address (A16-A31) A-D0 Converter Interrupt Handler Start Address (A0-A15) A-D0 Converter Interrupt Handler Start Address (A16-A31) H'0000 00E0 H'0000 00E2 H'0000 00E4 H'0000 00E6 H'0000 00E8 H'0000 00EA H'0000 00EC H'0000 00EE TID0 Input Interrupt Handler Start Address (A0-A15) TID0 Input Interrupt Handler Start Address (A16-A31) TOD0 Output Interrupt Handler Start Address (A0-A15) TOD0 Output Interrupt Handler Start Address (A16-A31) DMA5-9 Interrupt Handler Start Address (A0-A15) DMA5-9 Interrupt Handler Start Address (A16-A31) SIO2,3 Transmit/Receive Interrupt Handler Start Address (A0-A15) SIO2,3 Transmit/Receive Interrupt Handler Start Address (A16-A31) H'0000 00F0 H'0000 00F2 RTD Interrupt Handler Start Address (A0-A15) RTD Interrupt Handler Start Address (A16-A31) H'0000 00F4 H'0000 00F6 TID1 Input Interrupt Handler Start Address (A0-A15) TID1 Input Interrupt Handler Start Address (A16-A31) H'0000 00F8 H'0000 00FA TOD1+TOM0 Output Interrupt Handler Start Address (A0-A15) TOD1+TOM0 Output Interrupt Handler Start Address (A16-A31) H'0000 00FC H'0000 00FE SIO4,5 Transmit/Receive Interrupt Handler Start Address (A0-A15) SIO4,5 Transmit/Receive Interrupt Handler Start Address (A16-A31) H'0000 0100 H'0000 0102 A-D1 Converter Interrupt Handler Start Address (A0-A15) A-D1 Converter Interrupt Handler Start Address (A16-A31) H'0000 0104 H'0000 0106 TID2 Input Interrupt Handler Start Address (A00-A15) TID2 Input Interrupt Handler Start Address (A16-A31) H'0000 0108 H'0000 010A TML1 Input Interrupt Handler Start Address (A00-A15) TML1 Input Interrupt Handler Start Address (A16-A31) H'0000 010C H'0000 010E CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A0-A15) CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A16-A31) INTERRUPT CONTROLLER (ICU)

5-17 32170/32174 Group User's Manual (Rev. 2.1)

5.5.1 Acceptance of Internal Peripheral I/O Interrupts

An interrupt from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set by the Interrupt Control Register and the IMASK value of the Interrupt Mask Register. If its priority is higher than the IMASK value, the interrupt is accepted. However, when multiple interrupt requests occur simultaneously, the interrupt controller resolves priority between these interrupt requests following the procedure described below. (a) The ILEVEL values set by the Interrupt Control Register for each interrupt peripheral I/O are compared with each other. (b) If the ILEVEL values are the same, they are resolved according to the predetermined hardware priority. (c) The ILEVEL value is compared with IMASK value. When multiple interrupt requests occur simultaneously, the interrupt controller first compares their priority levels set by each Interrupt Control Register's ILEVEL bit to select an interrupt request which has the highest priority. If the interrupt requests have the same LEVEL value, they are resolved according to the hardware-fixed priority. The interrupt request thus selected has its ILEVEL value compared with IMASK value and if its priority is higher than the IMASK value, the interrupt controller sends an EI request to the CPU. Interrupt requests may be masked by setting the Interrupt Mask Register and the Interrupt Control Register's ILEVEL bit (level 7 = disabled) provided for each internal peripheral I/O and the PSW register IE bit. Figure 5.5.1 Example of Priority Resolution When Accepting Interrupt (c)(b)(a) Interrupt requested or not Resolve priority according to interrupt priority levels (ILEVEL) Resolve priority according to hardware priority Compare with IMASK value MJT Output Interrupt 4 MJT Output Interrupt 3 MJT Output Interrupt 2 MJT Output Interrupt 1 DMA0-4 Interrupt A-D0 Converter Interrupt (ILEVEL settings) Level 3 Level 4 Level 5 Level 3 Level 1 Level 3 Not requested Requested Requested Requested Requested Requested Hardware-fixed priority Accept interrupt if PSW register IE bit = 1 Level 3 Level 3 Level 3 Can be accepted when IMASK = 4-7 INTERRUPT CONTROLLER (ICU)

5-18 32170/32174 Group User's Manual (Rev. 2.1) Table 5.5.1 Hardware-fixed Priority Levels Priority Interrupt Source ICU Vector Table Address Type of Input Source High MJT Input Interrupt 4 (IRQ12) H'0000 0094-H'0000 0097 Level-recognized MJT Input Interrupt 3 (IRQ11) H'0000 0098-H'0000 009B Level-recognized MJT Input Interrupt 2 (IRQ10) H'0000 009C-H'0000 009F Level-recognized MJT Input Interrupt 1 (IRQ9) H'0000 00A0-H'0000 00A3 Level-recognized MJT Input Interrupt 0 (IRQ8) H'0000 00A4-H'0000 00A7 Level-recognized MJT Output Interrupt 7 (IRQ7) H'0000 00A8-H'0000 00AB Level-recognized MJT Output Interrupt 6 (IRQ6) H'0000 00AC-H'0000 00AF Level-recognized MJT Output Interrupt 5 (IRQ5) H'0000 00B0-H'0000 00B3 Edge-recognized MJT Output Interrupt 4 (IRQ4) H'0000 00B4-H'0000 00B7 Level-recognized MJT Output Interrupt 3 (IRQ3) H'0000 00B8-H'0000 00BB Level-recognized MJT Output Interrupt 2 (IRQ2) H'0000 00BC-H'0000 00BF Level-recognized MJT Output Interrupt 1 (IRQ1) H'0000 00C0-H'0000 00C3 Level-recognized MJT Output Interrupt 0 (IRQ0) H'0000 00C4-H'0000 00C7 Level-recognized DMA0-4 Interrupt H'0000 00C8-H'0000 00CB Level-recognized SIO1 Receive Interrupt H'0000 00CC-H'0000 00CF Edge-recognized SIO1 Transmit Interrupt H'0000 00D0-H'0000 00D3 Edge-recognized SIO0 Receive Interrupt H'0000 00D4-H'0000 00D7 Edge-recognized SIO0 Transmit Interrupt H'0000 00D8-H'0000 00DB Edge-recognized A-D0 Converter Interrupt H'0000 00DC-H'0000 00DF Edge-recognized TID0 Output Interrupt H'0000 00E0-H'0000 00E3 Edge-recognized TOD0 Output Interrupt H'0000 00E4-H'0000 00E7 Level-recognized DMA5-9 Interrupt H'0000 00E8-H'0000 00EB Level-recognized SIO2,3 Transmit/Receive Interrupt H'0000 00EC-H'0000 00EF Level-recognized RTD Interrupt H'0000 00F0-H'0000 00F3 Edge-recognized TID1 Output Interrupt H'0000 00F4-H'0000 00F7 Edge-recognized TOD1+TOM0 Output Interrupt H'0000 00F8-H'0000 00FB Level-recognized SIO4,5 Transmit/Receive Interrupt H'0000 00FC-H'0000 00FF Level-recognized A-D1 Converter Interrupt H'0000 0100-H'0000 0103 Edge-recognized TID2 Output Interrupt H'0000 0104-H'0000 0107 Edge-recognized TML1 Input Interrupt H'0000 0108-H'0000 010B Level-recognized Low CAN0 Transmit/Receive & Error InterruptH'0000 010C-H'0000 010F Level-recognized INTERRUPT CONTROLLER (ICU)

5-19 32170/32174 Group User's Manual (Rev. 2.1) Table 5.5.2 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 (ILEVEL="000") Accepted when IMASK is 1-7 1 (ILEVEL="001") Accepted when IMASK is 2-7 2 (ILEVEL="010") Accepted when IMASK is 3-7 3 (ILEVEL="011") Accepted when IMASK is 4-7 4 (ILEVEL="100") Accepted when IMASK is 5-7 5 (ILEVEL="101") Accepted when IMASK is 6-7 6 (ILEVEL="110") Accepted when IMASK is 7 7 (ILEVEL="111") Not accepted (interrupts disabled) INTERRUPT CONTROLLER (ICU)

5-20 32170/32174 Group User's Manual (Rev. 2.1)

5.5.2 Processing by Internal Peripheral I/O Interrupt by Handlers

(1) Branching to the interrupt handler Upon accepting an interrupt request, the CPU branches to the EIT vector entry after performing the hardware preprocessing as described in Section 4.3, "EIT Processing Procedure." The EIT vector entry for External Interrupt (EI) is located at the address H'0000 0080. This address is where the instruction (not the jump address itself) for branching to the beginning of the interrupt handler routine for external interrupt requests is written. (2) Processing in the External Interrupt (EI) handler A typical operation of the External Interrupt (EI) handler (for interrupts from internal peripheral I/ O) is shown in Figure 5.5.2. [1] Saving each register to the stack Save the BPC, PSW and general-purpose registers to the stack. Also, save the accumulator and FPSR register to the stack as necessary. [2] Reading the Interrupt Request Mask Register (IMASK) and saving to the stack Read the Interrupt Request Mask Register and save its content to the stack. [3] Reading the Interrupt Vector Register (IVECT) Read the Interrupt Vector Register. This register holds the 16 low-order address bits of the ICU vector table for the accepted interrupt request source that was stored in it when accepting an interrupt request. When the Interrupt Vector Register is read, the following processing is automatically performed in hardware:

• The interrupt priority level of the accepted interrupt request (ILEVEL) is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.)
• The accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources).
• The interrupt request (EI) to the CPU core is dropped.
• The ICU's internal sequencer is activated to start internal processing (interrupt priority resolution). [4] Reading and overwriting the Interrupt Request Mask Register (IMASK) Read the Interrupt Request Mask Register and overwrite it with the read value. This write to the IMASK register causes the following processing to be automatically performed in hardware:
• The interrupt request (EI) to the CPU core is dropped.
• The ICU's internal sequencer is activated to start internal processing (interrupt priority resolution). Note: • Processing in [4] here is unnecessary when multiple interrupts are to be enabled in [6] below. INTERRUPT CONTROLLER (ICU)

5-21 32170/32174 Group User's Manual (Rev. 2.1) INTERRUPT CONTROLLER (ICU) [5] Reading the ICU vector table Read the ICU vector table for the accepted interrupt request source. The relevant ICU vector table address can be obtained by zero-extending the content of the Interrupt Vector Register that was read in [3] (i.e., the 16 low-order address bits of the ICU vector table for the accepted interrupt request source). The ICU vector table must have set in it the start address of the interrupt handler for the interrupt request source concerned.) [6] Enabling multiple interrupts To enable another higher priority interrupt while processing the accepted interrupt (i.e., enabling multiple interrupts), set the PSW register IE bit to "1". [7] Branching to the internal peripheral I/O interrupt handler Branch to the start address of the interrupt handler that was read out in [5]. [8] Processing in the internal peripheral I/O interrupt handler [9] Disabling interrupts Clear the PSW register IE bit to "0" to disable interrupts. [10] Restoring the Interrupt Request Mask Register (IMASK) Restore the Interrupt Request Mask Register that was saved to the stack in [2]. [11] Restoring registers from the stack Restore the registers that were saved to the stack in [1]. [12] Completion of external interrupt processing Execute the RTE instruction to complete the external interrupt processing. The program returns to the state in which it was before the currently processed interrupt request was accepted. (3) Identifying the source of the interrupt request generated If any internal peripheral I/O has two or more interrupt request sources, check the Interrupt Request Status Register provided for each internal peripheral I/O to identify the source of the interrupt request generated. (4) Enabling multiple interrupts To enable multiple interrupts in the interrupt handler, set the PSW register IE (Interrupt Enable) bit to enable interrupt requests to be accepted. However, before writing "1" to the IE bit, be sure to save each register (BPC, PSW, general-purpose registers and IMASK) to the stack. Note: • Before enabling multiple interrupts, read the Interrupt Vector Register (IVECT) and then the ICU vector table, as shown in Figure 5.5.2, "Typical Handler Operation for Interrupts from Internal Peripheral I/O."

5-22 32170/32174 Group User's Manual (Rev. 2.1) Note 1: For operations at EIT acceptance and return from EIT, also see Section 4.3, "EIT Processing Procedure." Note 2: Do not read the Interrupt Vector Register (IVECT) or write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts are disabled (PSW register IE bit = 0). Note 3: When multiple interrupts are disabled, execute processing in [4]. Processing in [4] is unnecessary if multiple interrupts are enabled by executing processing in [6] and [9]. Note 4: To enable multiple interrupts, execute processing in [6] and [9]. Note 5: To reenable interrupts (by setting the IE bit to 1) after reading the Interrupt Vector Register (IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts. In the example here, there is no need to add a dummy access because the ICU vector table is read after reading the IVECT register. Similarly, to reenable interrupts (by setting the IE bit to 1) after writing to the Interrupt Request Mask Register (IMASK), perform a dummy access to the internal memory, etc. before reenabling interrupts. H'0000 0080 BRA instruction Read Interrupt Vector Register (IVECT) Read ICU vector table Branch to the interrupt handler for each internal peripheral I/O RTE H'0080 0004 H'0000 0094 H'0000 0113 Interrupt handler EI (External Interrupt) handler EI (External Interrupt) vector entry Interrupt handler start address Program being executed Interrupt generated IVECT Save BPC to the stack Save PSW to the stack Save general-purpose registers to the stack Restore BPC from the stack Restore PSW from the stack Restore general-purpose registers from the stack Read and save Interrupt Request Mask Register (IMASK) to the stack IMASK H'0080 0000 Set PSW register IE bit to 1 Clear PSW register IE bit to 0 Restore Interrupt Request Mask Register (IMASK) from the stack [1] [2] [3] [5] [7] [8] [9] [6] [10] [11] ICU vector table (Note 1) (Note 1) Hardware preprocessing when EIT is accepted Hardware postprocessing when RTE instruction is executed Read and overwrite Interrupt Request Mask Register (IMASK) [4] [12] (Note 2) (Note 2) (Note 3) (Note 4) (Note 5) (Note 4) (Note 2) Interrupt handler [1] to [12]: Processing of EI by interrupt handler Figure 5.5.2 Typical Operation for Interrupts from Internal Peripheral I/O INTERRUPT CONTROLLER (ICU)

5-23 32170/32174 Group User's Manual (Rev. 2.1) H’0000 0010 BRA instruction SBI (System Break Interrupt) handler SBI (System Break Interrupt) vector entry Program being executed SBI generated Processing to terminate the system Note: Do not return to the program that was being executed when the interrupt occurred. Terminate or reset the system INTERRUPT CONTROLLER (ICU)

5.6 Description of System Break Interrupt (SBI) Operation

5.6.1 Acceptance of SBI

System Break Interrupt (SBI) is an emergency interrupt which is used when power failure is detected or a fault condition is notified by an external watchdog timer. The system break interrupt is accepted anytime upon detection of a falling edge on the SBI signal regardless of how the PSW register IE bit is set, and cannot be masked.

5.6.2 SBI Processing by Handler

When the system break interrupt generated has been serviced, always be sure to terminate or reset the system without returning to the program that was being executed when the interrupt occurred. Figure 5.6.1 Typical SBI Operation

5-24 32170/32174 Group User's Manual (Rev. 2.1) INTERRUPT CONTROLLER (ICU) ❊ This is a blank page. ❊

6.1 Outline of the Internal Memory

6.2 Internal RAM

6.3 Internal Flash Memory

6.4 Registers Associated with the

6.5 Programming of the Internal

6.6 Boot ROM

6.7 Virtual Flash Emulation

6.8 Connecting to A Serial

6.9 Precautions to Be Taken

When Rewriting Flash Memory

6-2 32170/32174 Group User's Manual (Rev. 2.1) This microcomputer internally contains the following types of memory:

• 40 Kbyte or 32 Kbyte RAM
• 768 Kbyte, 512 Kbyte, or 384 Kbyte flash memory

Specifications of the internal RAM are shown below. Table 6.2.1 Specifications of the Internal RAM Item Specification Capacity M32170F6, M32174F4, M32174F3 : 40 Kbytes M32170F4, M32170F3 : 32Kbytes Location address M32170F6, M32174F4, M32174F3 : H'0080 4000 - H'0080 DFFF M32170F4, M32170F3 : H'0080 4000 - H'0080 BFFF Wait insertion Operates with no wait states (when using 40 MHz CPU clock) Internal bus connection Connected by 32-bit bus Dual port By using the Real-Time Debugger (RTD), data can be read (monitored) or written to any area of the internal RAM via serial communication from external devices independently of the CPU. (Refer to Chapter 14, "Real-Time Debugger.") INTERNAL MEMORY

6-3 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Specifications of the internal flash memory are shown below. Table 6.3.1 Specifications of the Internal Flash Memory Item Specification Capacity M32170F6 : 768 Kbytes M32170F4, M32174F4 : 512Kbytes M32170F3, M32174F3 : 384Kbytes Location address M32170F6 : H'0000 0000 - H'000B FFFF M32170F4, M32174F4 : H'0000 0000 - H'0007 FFFF M32170F3, M32174F3 : H'0000 0000 - H'0005 FFFF Wait insertion Operates with no wait states (when using 40 MHz CPU clock) Durability Can be rewritten 100 times Internal bus connection Connected by 32-bit bus Other Virtual flash emulation function is included. (Refer to Section 6.7, "Virtual Flash Emulation Function.")

6-4 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY

6.4 Registers Associated with the Internal Flash Memory

Figure 6.4.1 Register Map Associated with the Internal Flash Memory H’0080 07E0 H’0080 07E2 Address D0 D7 +0 Address +1 Address D8 D15 H’0080 07E4 H’0080 07E6 H’0080 07E8 H’0080 07EA H’0080 07EC H’0080 07EE H’0080 07F0 H’0080 07F2 Blank addresses are reserved for future use. (Note) Note: The M32170F4 and M32170F3 do not have the FELBANK3 register. Flash Mode Register (FMOD) Flash Controle Register 1 (FCNT1) Flash Controle Register 3 (FCNT3) Flash Status Register 1 (FSTAT1) Flash Controle Register 2 (FCNT2) Flash Controle Register 4 (FCNT4) Virtual Flash L Bank Register 0 (FELBANK0) Virtual Flash L Bank Register 1 (FELBANK1) Virtual Flash L Bank Register 2 (FELBANK2) Virtual Flash L Bank Register 3 (FELBANK3) Virtual Flash S Bank Register 0 (FESBANK0) Virtual Flash S Bank Register 1 (FESBANK1) The diagram below shows a register map associated with the internal flash memory.

6-5 32170/32174 Group User's Manual (Rev. 2.1) D 0 123456 D 7 FPMOD <When reset : H'0?> D Bit Name Function R W 0 - 6 No functions assigned 0 —

7 FPMOD 0 : FP pin = low —

(External FP pin status) 1 : FP pin = high The Flash Mode Register (FMOD) is a read-only status register, with its FPMOD bit indicating the status of the FP (Flash Protect) pin. Write to the flash memory is enabled only when FPMOD = 1. Writing to the flash memory when FPMOD = 0 has no effect.

6.4.1 Flash Mode Register

I Flash Mode Register (FMOD) <Address: H'0080 07E0> INTERNAL MEMORY

6-6 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY

6.4.2 Flash Status Registers

The 32170 has two registers to indicate the flash memory status, one of which is Flash Status Register 1 (FSTAT1) located in the SFR area (address: H'0080 07E1), and the other is Flash Status Register 2 (FSTAT2) included in the flash memory itself. When programming or erasing the flash memory, use these two status registers (FSTAT1, FSTAT2) to control the program/erase operations. I Flash Status Register 1 (FSTAT1) <Address: H'0080 07E1> D 8 9 1 01 11 21 31 4 D 1 5 FSTAT <When reset : H'01> D Bit Name Function R W 8 - 14 No functions assigned 0 —

15 FSTAT 0 : Busy —

(Ready/Busy status) 1 : Ready The Flash Status Register 1 (FSTAT1) is a read-only status register used to know the execution status of whether the flash memory is being programmed or erased. When the FSTAT bit = 0, it means that the flash memory is being programmed or erased, during which time any operation to program the flash memory area is disabled.

6-7 32170/32174 Group User's Manual (Rev. 2.1) I Flash Status Register 2 (FSTAT2) D 8 9 1 01 11 21 31 4 D 1 5 FBUSY ERASE WRERR1 WRERR2 <When reset : H'80> D Bit Name Function R W

8 FBUSY 0 : Program or erase under way —

(Flash busy) 1 : Ready state

9 No functions assigned 0 —

10 ERASE 0 : Erase normally operating/terminated —

(Auto Erase operating condition) 1 : Erase error occurred

11 WRERR1 0 : Program normally operating/terminated —

(Program operating condition) 1 : Program error occurred

12 WRERR2 0 : Program normally operating/terminated —

(Program operating condition) 1 : Over-programming occurred 13 - 15 No functions assigned 0 — The Flash Status Register 2 (FSTAT2) consists of the following four read-only status bits which indicate the operating condition of the flash memory. (1) FBUSY (Flash Busy) bit (D8) The FBUSY bit is used to determine whether the operation is terminated when programming or erasing the flash memory. When FBUSY = 0, it means the program or erase operation is being executed; when FBUSY = 1, the operation is terminated. (2) ERASE (Auto Erase operating condition) bit (D10) The ERASE bit is used to determine whether execution of the flash memory erase operation has resulted in an error. When ERASE = 0, it means the erase operation terminated normally; when ERASE = 1, the operation terminated in an error. (3) WRERR1 (Program operating condition) bit (D11) The WRERR1 bit is used to determine after completion of execution whether the flash memory program operation resulted in an error. When WRERR1 = 0, it means the program operation terminated normally; when WRERR1 = 1, the operation terminated in an error. The condition under which WRERR1 is set to 1 is when any bit other than those that must be 0 is found to be a 0 by comparison between the write data and the data in the flash memory. INTERNAL MEMORY

6-8 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY (4) WRERR2 (Program operating condition) bit (D12) The WRERR2 bit is used to determine after execution whether the flash memory program operation resulted in an error. When WRERR2 = 0, it means the program operation terminated normally; when WRERR2 = 1, the operation terminated in an error. The condition under which WRERR2 is set to 1 is when the flash memory could not be written to by repeating the write operation a specified number of times. Note: This status register is included in the internal flash memory itself, and can be read out by writing the Read Status Command (H'7070) to any address of the flash memory. For details, refer to Section 6.5, "Programming of Internal Flash Memory."

6-9 32170/32174 Group User's Manual (Rev. 2.1) D 0 123456 D 7 FENTRY FEMMOD <When reset : H'00> D Bit Name Function R W 0 - 2 No functions assigned 0 —

3 FENTRY 0 : Normal read

(Flash mode entry) 1 : Erase/program enable 4 - 6 No functions assigned 0 —

7 FEMMOD 0 : Normal mode

(Virtual flash emulation mode) 1 : Virtual Flash emulation mode The Flash Control Register 1 (FCNT1) consists of the following two bits to control the internal flash memory. (1) FENTRY (Flash Mode Entry) bit (D3) The FENTRY bit controls entry to flash E/W enable mode. Flash E/W enable mode can be entered only when FENTRY = 1. To set the FENTRY bit to 1, write a 0 and then a 1 to the FENTRY bit in succession while the FP pin = high. The FENTRY bit is cleared in the following cases:

• When the device is reset
• When a 0 is written to the FENTRY bit
• When the FP pin changes state from high to low

6.4.3 Flash Control Registers

I Flash Control Register 1 (FCNT1) <Address: H'0080 07E2> INTERNAL MEMORY

6-10 32170/32174 Group User's Manual (Rev. 2.1) When using a program in the flash memory while the FENTRY bit = 0, the EI vector entry is located at address H'0000 0080 of the flash memory. When running a flash rewrite program in RAM while the FENTRY bit = 1, the EI vector entry is located at address H'0080 4000 of the RAM, allowing for flash rewrite operation to be controlled using interrupts. Table 6.4.1 Changes of EI Vector Entry by FENTRY FENTRY EI Vector Entry Address

0 Flash memory area H'0000 0080

1 Internal RAM area H'0080 4000

(2) FEMMOD (Virtual Flash Emulation Mode) bit (D7) The FEMMOD bit controls entry to Virtual flash emulation mode. Virtual flash emulation mode is entered by setting the FEMMOD bit to 1 while the FENTRY bit = 0. (For details, refer to Section 6.7, "Virtual Flash Emulation Function.") INTERNAL MEMORY

6-11 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY I Flash Control Register 2 (FCNT2) <Address: H'0080 07E3> D 8 9 1 01 11 21 31 4 D 1 5 FPROT <When reset : H'00> D Bit Name Function R W 8 - 14 No functions assigned 0 —

15 FPROT 0 : Protection by lock bit effective

(Unlock) 1 : Protection by lock bit not effective The Flash Control Register 2 (FCNT2) controls invalidation of the internal flash memory protection by a lock bit (to disable erasing or programming of the flash memory). The flash memory protection becomes invalid (unlocked) by setting the FPROT bit to 1, so that any blocks protected by the lock bit can be erased or programmed. To set the FPROT bit to 1, write a 0 and then a 1 to the FPROT bit in succession while the FENTRY bit = 1. The FPROT bit is cleared to 0 by writing a 0 to the FPROT bit and setting the FP pin low or the FENTRY bit to 0 immediately after reset. Figure 6.4.2 Protection Unlocking Flow FPROT=0 YES NO FENTRY=1 FPROT=1 FPROT is not set to 1 if write cycle to any other area occurs during this time FPR OT=0 FPR OT=1 FENTRY=1

6-12 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY I Flash Control Register 3 (FCNT3) <Address: H'0080 07E4> D 0 123456 D 7 FELEVEL <When reset : H'00> D Bit Name Function R W 0 - 6 No functions assigned 0 —

7 FELEVEL 0 : Normal level

(Raise erase margin) 1 : Raise erase margin The Flash Control Register 3 (FCNT3) controls the depth of erase levels when erasing the internal flash memory with one of erase commands. By setting the FELEVEL bit to 1, the flash memory erase level can be deepened, which will result in an increased reliability margin.

6-13 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY I Flash Control Register 4 (FCNT4) <Address: H'0080 07E5> D 8 9 1 01 11 21 31 4 D 1 5 FRESET <When reset : H'00> D Bit Name Function R W 8 - 14 No functions assigned 0 —

15 FRESET 0 : No operation performed

(Reset flash) 1 : Reset the flash memory The Flash Control Register 4 (FCNT4) controls canceling program/erase operation in the middle and initializing each status bit of Flash Status Register 2 (FSTAT2). When the FRESET bit is set to 1, program/erase operation is canceled in the middle and each status bit of FSTAT2 is initialized (H'80). The FRESET bit is effective only when the FENTRY bit = 1. Information on FRESET bit is ignored unless the FENTRY bit = 1. Make sure that when programming or erasing the flash memory, the FRESET bit remains 0.

6-14 32170/32174 Group User's Manual (Rev. 2.1) Figure 6.4.3 Example for Using the FCNT4 Register INTERNAL MEMORY FRESET=1 YES NO FENTRY=1 Program/erase flash memory Error found Program/erase terminated normally FRESET=0 Program/erase flash memory FENTRY=0

6-15 32170/32174 Group User's Manual (Rev. 2.1)

6.4.4 Virtual Flash L Bank Registers

I Virtual Flash L Bank Register 0 (FELBANK0) <Address: H'0080 07E8> I Virtual Flash L Bank Register 1 (FELBANK1) <Address: H'0080 07EA> I Virtual Flash L Bank Register 2 (FELBANK2) <Address: H'0080 07EC> I Virtual Flash L Bank Register 3 (FELBANK3) <Address: H'0080 07EE> INTERNAL MEMORY D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 <When reset : H'0000> D Bit Name Function R W

0 MODENL 0 : Disable virtual flash function

(Virtual flash emulation enable) 1 : Enable virtual flash function 1 - 7 No functions assigned 0 — 8 - 14 LBANKAD A12 - A18 of start address of the L bank (L bank address) to be selected

15 No functions assigned 0 —

Note: This register must always be accessed in halfword. (1) MODENL (Virtual Flash Emulation Enable) bit (D0) The MODENL bit can be set to 1 after entering virtual flash emulation mode (by setting the FEMMOD bit to 1 while the FENTRY bit = 0). This causes the virtual flash emulation function to become effective for the L bank area selected by the LBANKAD bits. (2) LBANKAD (L Bank Address) bits (D8-D14) The LBANKAD bits are provided for selecting one L bank from a total of 96 L banks separated every 8 KB. Use these LBANKAD bits to set the seven bits, A12-A18, of the 32-bit start address of the L bank you want to select. (For details, refer to Section 6.7, "Virtual Flash Emulation Function.") Note: The M32170F4, M32170F3, M32174F4, and M32174F3 do not have Virtual Flash L Bank Register 3 (FELBANK3). MOD ENL

6-16 32170/32174 Group User's Manual (Rev. 2.1)

6.4.5 Virtual Flash S Bank Registers

I Virtual Flash S Bank Register 0 (FESBANK0) <Address: H'0080 07F0> I Virtual Flash S Bank Register 1 (FESBANK1) <Address: H'0080 07F2> INTERNAL MEMORY D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 <When reset : H'0000> D Bit Name Function R W

0 MODENS 0 : Disable virtual flash function

(Virtual flash emulation enable) 1 : Enable virtual flash function 1 - 7 No functions assigned 0 — 8 - 15 SBANKAD A12 - A19 of start address of the S bank (S bank address) to be selected Note: This register must always be accessed in halfword. (1) MODENS (Virtual Flash Emulation Enable) bit (D0) The MODENS bit can be set to 1 after entering virtual flash emulation mode (by setting the FEMMOD bit to 1 while the FENTRY bit = 0). This causes the virtual flash emulation function to become effective for the S bank area selected by the SBANKAD bits. (2) SBANKAD (S Bank Address) bits (D8-D15) The SBANKAD bits are provided for selecting one S bank from a total of 192 S banks separated every 4 KB. Use these SBANKAD bits to set the eight bits, A12-A19, of the 32-bit start address of the S bank you want to select. (For details, refer to Section 6.7, "Virtual Flash Emulation Function.") MOD ENS

6-17 32170/32174 Group User's Manual (Rev. 2.1)

6.5 Programming of the Internal Flash Memory

6.5.1 Outline of Programming Flash Memory

When writing to the internal flash memory, there are following two methods to use depending on situation: (1) When the write program does not exist in the internal flash memory (2) When the write program already exists in the internal flash memory For (1), set the FP pin = high, MOD0 = high, and MOD1 = low to enter boot flash E/W enable mode. In this case, the reset vector entry is located at the beginning of the boot program area (H'8000 0000). (Normally, the reset vector entry is located at the start address of the internal flash memory.) Transfer the "flash write program" from the boot area into the internal RAM using a boot program. After this transfer, jump to the RAM and set the Flash Control Register 1 FENTRY bit to 1 to make the flash memory ready for write. You now can write to the internal flash memory using the "flash write program" that has been transferred into the internal RAM. For (2), set the FP pin = high, MOD0 = low, and MOD1 = low to enter flash E/W enable mode in single-chip mode. Transfer the "flash write program" from the internal flash memory in which it has been prepared beforehand into the internal RAM. After this transfer, jump to the RAM and set the Flash Control Register 1 (FCNT1) FENTRY bit to 1 using a program in the RAM to make the flash memory ready for write. You now can write to the internal flash memory using the "flash write program" that has been transferred into the internal RAM. Or you can set the FP pin = high, MOD0 = low, and MOD1 = high to enter flash E/W enable mode in extended external mode. When in flash E/W enable mode (FP pin = 1, FENTRY bit = 1), the EIT vector entry for External Interrupt (EI) is moved to the beginning of the internal RAM (H'0080 4000). During normal mode, the EIT vector entry exists in the flash area (H'0000 0080). INTERNAL MEMORY

6-18 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.5.1 EI Vector Entry When in Flash E/W Enable Mode EI vector entry Internal ROM area Internal RAM (H'0000 0080) H'0000 0000 H'00FF FFFF H'0080 4000 Internal ROM area Internal RAM H'0080 3FFF Flash E/W enable mode (FENTRY=1) Normal mode (FENTRY=0) H'0000 0000 H'0080 3FFF EI vector entry (H'0080 4000)H'0080 4000 H'00FF FFFF

6-19 32170/32174 Group User's Manual (Rev. 2.1) (1) When the write program does not exist in the internal flash memory Use a program in the boot ROM located on memory map to write to the flash memory. To transfer the write data, use serial I/O1 in clock-synchronized serial mode. Use this serial transfer when writing to the flash memory using a flash programmer. INTERNAL MEMORY Figure 6.5.2 Procedure for Writing to Internal Flash Memory (when the write program does not exist in the flash memory) SIO1 CPU SIO1 CPU Flash write program MOD1= L SIO1 CPU RAM Flash memory FP=L or H RAM RAM <Step 1> Initial state (where the write program does not exist in the flash memory. <Step 2> Set the FP pin high, the MOD0 pin high, and the MOD1 pin low to place the device in boot mode + flash E/W enable mode. Deassert reset and start up using the boot program. Transfer the flash write program from boot ROM to RAM. Jump to the flash write program in RAM. <Step 3> Using the flash write program in RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1. Write data to the internal flash memory using the flash write program. When you finished writing, reset MOD0 low and jump to the flash memory or apply reset to enter normal mode. M32R/ECU M32R/ECU M32R/ECU External device External device Flash memory Flash write data Flash memory MOD0=L Boot ROM Boot ROM Boot ROM MOD1= LFP=H MOD0=H MOD1= LFP=H MOD0=H RESET=L RESET=H RESET=H Flash write program Write data Write data External device Write data

6-20 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.5.3 Internal Flash Memory Write Timings (when the write program does not exist in the flash memory) RESET MOD0 FENTRY FP MOD1 POWER ON Mode selected Reset deasserted (Boot program starts) Mode selected Reset deasserted Writes to flash memory by boot program Settings by boot program

6-21 32170/32174 Group User's Manual (Rev. 2.1) (2) When the write program already exists in the internal flash memory Use the flash write program already stored in the internal flash memory to write to the flash memory. For write to the flash memory, use the internal peripheral circuits according to your programming system. (The data bus, serial I/O, and ports can be used.) The following shows an example for writing to the flash memory by using serial I/O0 in single-chip mode. INTERNAL MEMORY Figure 6.5.4 Procedure for Writing to Internal Flash Memory (when the write program already exists in the flash memory) SIO0 CPU SIO0 CPU Flash write program MOD1= L SIO0 CPU RAM Flash write program FP=L or H RAM RAM <Step 1> Initial state (where the write program already exists in the flash memory) Ordinary program in the flash memory is being executed. <Step 2> Set the FP pin high, the MOD1 pin low, and the MOD0 pin low to place the device in single-chip + flash E/W enable mode. After determining the FP pin and MOD1 pin levels, transfer the flash write program from the flash memory area into RAM. Jump to the flash write program in RAM. <Step 3> Using the flash write program in RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1. Write data to the internal flash memory using the flash write program in RAM. When you finished writing, jump to the program in the flash memory or apply reset to enter normal mode. M32R/ECU M32R/ECU M32R/ECU External device External device Flash memory Flash write data Flash memory Boot ROM Boot ROM Boot ROM MOD1= LFP=H MOD1= LFP=H MOD0=L MOD0=L MOD0=L Flash write program Write data Write data External device Write data

6-22 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.5.5 Internal Flash Memory Write Timings (when the write program already exists in the flash memory) RESET MOD0 FENTRY FP "H" or "L" "H" or "L" (Single-chip or extended external)MOD1 "L" "H" or "L" Write to flash memory by flash rewrite program Flash rewrite starts Flash mode turned off Flash rewrite program transferred to RAM Flash mode turned on

6-23 32170/32174 Group User's Manual (Rev. 2.1)

6.5.2 Controlling Operation Mode during Programming Flash

The device's operation modes are set by MOD0, MOD1, and Flash Control Register 1 (FCNT1) FENTRY bit. The table below lists operation modes that may be set during flash write. Table 6.5.1 Operation Modes Set during Flash Write FP MOD0 MOD1 FENTRY (Note) Operation Mode Reset Vector Entry EI Vector Entry 00 0 — Single-chip mode Start address of Flash area 1 0 0 0 flash memory (H'0000 0080) (H'0000 0000) 01 0 — Processor mode Start address of External area external area (H'0000 0080) (H'0000 0000) 00 1 — Extended external modeStart address of Flash area 1 0 1 0 flash memory (H'0000 0080) (H'0000 0000) 1 0 0 1 Single-chip mode Start address of Beginning of + flash E/W enable flash memory internal RAM (H'0000 0000) (H'0080 4000) 1 1 0 0 Boot mode Start address of Flash area boot program area (H'0000 0080) (H'8000 0000) 1 1 0 1 Boot mode Start address of Beginning of + flash E/W enable boot program area internal RAM (H'8000 0000) (H'0080 4000) 10 1 1 Extended external modeStart address of Beginning of + flash E/W enable flash memory internal RAM (H'0000 0000) (H'0080 4000) — 11 — reserved — — Note: Indicates the FENTRY bit status of Flash Control Register 1 (FCNT1). The bar "— " denotes "Don't Care." (1) Flash E/W enable mode Flash E/W enable mode is a mode in which the internal flash memory can be programmed or erased. In flash E/W enable mode, no programs can be executed in the internal flash memory. Therefore, before entering flash E/W enable mode, you need to transfer the necessary program into the internal RAM and run the program in RAM. INTERNAL MEMORY

6-24 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY (2) Entering flash E/W enable mode Flash E/W enable mode can be entered only when the device is operating in single-chip mode or extended external mode. Namely, you can enter flash E/W enable mode only when the FP pin = high and the Flash Control Register 1 (FCNT1) FENTRY bit = 1. You cannot enter flash E/W enable mode when the device is operating in processor mode or the FP pin = low. (3) Detecting the MOD0 and MOD1 pin levels The MOD0 and MOD1 pin levels (high or low) can be verified using the P8 Data Register (Port Data Register, H'00800 0708) MOD0DT and MOD1DT bits. I P8 Data Register (P8DATA) <Address: H'0080 0708> D 0 123456 D 7 MOD0DT MOD1DT P82DT P83DT P84DT P85DT P86DT P87DT <When reset : Indeterminate> D Bit Name Function R W

0 MOD0DT 0 : MOD0 pin = low —

(MOD0 data) 1 : MOD0 pin = high

1 MOD1DT 0 : MOD1 pin = low —

(MOD1 data) 1 : MOD1 pin = high

2 P82DT Depending on how the Port Direction Register is set

(Port P82 data) • When direction bit = 0 (input mode)

3 P83DT 0: Port input pin = low

(Port P83 data) 1: Port input pin = high

4 P84DT • When direction bit = 1 (output mode)

(Port P84 data) 0: Port output latch = low

5 P85DT 1: Port output latch = high

(Port P85 data)

6 P86DT

(Port P86 data)

7 P87DT

(Port P87 data)

6-25 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.5.6 Procedure for Entering Flash E/W Enable Mode Note: For details about each command, refer to Section 6.5.3, "Programming Procedure to Internal Flash Memory." END START Enter one of the following modes:

• Single-chip mode + flash E/W enable mode
• Boot mode + flash E/W enable mode
• Extended external mode + flash E/W enable mode Transfer E/W program to internal RAM in each mode Set Flash Control Register in SFR area (FCNT1, H'0080 07E2) flash entry (FENTRY) bit to 0 Set Flash Control Register in SFR area (FCNT1, H'0080 07E2) flash entry (FENTRY) bit to 1 Execute flash E/W command and various read commands (Note) Switched to flash E/W program 1 µs wait (by hardware timer or software timer) Jump to flash memory or apply reset Switched to normal mode MOD0, 1 FP pin levels checked OK NO END FMOD(H'0080 07E0) FPMOD P8DATA(H'0080 0708) D0=MOD0DT D1=MOD1DT

6-26 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY

6.5.3 Programming Procedure to the Internal Flash Memory

To write to the internal flash memory, set the device's operation mode to enter flash E/W enable mode first and then use the flash write program that has already been transferred from the flash memory into the internal RAM. In flash E/W enable mode, no data can be read out from the internal flash memory as in normal mode, so you cannot execute a program that exists in the internal flash memory. Therefore, the flash write program must be prepared in the internal RAM before entering flash E/W enable mode. (Once you've entered flash E/W enable mode, you cannot use any command except flash commands to access the flash memory.) To access the internal flash memory in flash memory E/W enable mode, issue commands for the internal flash memory address to be operated on. The table below lists the commands that can be issued in flash memory E/W enable mode. Note : During flash E/W enable mode, the flash memory cannot be accessed for read or write wordwise. Table 6.5.2 Commands in Flash Memory E/W Enable Mode Command Name Issued Command Data Read Array command H'FFFF Page Program command H'4141 Lock Bit Program command H'7777 Block Erase command H'2020 Erase All Unlock Block command H'A7A7 Read Status Register command H'7070 Clear Status Register command H'5050 Read Lock Bit Status command H'7171 Verify command (Note) H'D0D0 Note: This command is used in conjunction with Lock Bit Program, Block Erase, and Erase All Unlock Block operations. (1) Read Array command Read mode is entered by writing command data H'FFFF to any address of the internal flash memory. Then read the flash memory address you want to read out, and the content of that address will be read out. Before exiting flash E/W enable mode, always be sure to execute the Read Array command.

6-27 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY (2) Page Program command Flash memory is programmed one page at a time, each page consisting of 256 bytes (lower addresses H'00 to H'FF). To write data to the flash memory (i.e., to program the flash memory), write the program command H'4141 to any address of the internal flash memory and then the program data to the address to which you want to write. With the Page Program command, you cannot write to the protected blocks. Page Program is automatically performed by the internal control circuit, and the completion of programming can be verified by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (Refer to Section 6.4.2, "Flash Status Registers.") While the FSTAT bit = 0, the next programming can not be performed. (3) Lock Bit Program command Flash memory can be protected against program/erase one block at a time. The Lock Bit Program command is provided for protecting memory blocks. Write the Lock Bit Program command data H'7777 to any address of the internal flash memory. Next, write the Verify command data H'D0D0 to the last even address of the block you want to protect, and this memory block is protected against program/erase. To remove protection, disable lock bit-effectuated protection using the Flash Control Register 2 (FCNT2) FPROT bit (see Section 6.4.3, "Flash Control Registers") and erase the block whose protection you want to remove. (The content of this memory block is also erased.) The table below lists the target blocks and their specified addresses when writing the Verify command data.

6-28 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Table 6.5.3 M32170F6 Target Blocks and Specified Addresses Target Block Specified Address

0 H'0000 3FFE

1 H'0000 5FFE

2 H'0000 7FFE

3 H'0000 FFFE

4 H'0001 FFFE

5 H'0002 FFFE

6 H'0003 FFFE

7 H'0004 FFFE

8 H'0005 FFFE

9 H'0006 FFFE

10 H'0007 FFFE

11 H'0008 FFFE

12 H'0009 FFFE

13 H'000A FFFE

14 H'000B FFFE

Table 6.5.4 M32170F4 and M32174F4 Target Blocks and Specified Addresses Target Block Specified Address

6-29 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Table 6.5.5 M32170F3 and M32174F3 Target Blocks and Specified Addresses Target Block Specified Address

6-30 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.5.7 Block Configuration of the M32170F6 Flash Memory M32170F6 ’s Internal Flash Memory Area (768KB) H ’0002 0000 8KB 16KB 8KB 32KB 64KB H ’0000 0000 H ’0000 7FFF H ’0000 8000 H ’0001 FFFF H ’0000 3FFF H ’0000 4000 H ’0000 FFFF H ’0001 0000 H ’0000 5FFF H ’0000 6000 64KB H ’0002 FFFF 64KB H ’0009 FFFF H ’0009 0000 64KB H ’000A FFFF H ’000A 0000 64KB H ’000B FFFF H ’000B 0000 64KB Block 0 64KB 64KB 64KB 64KB 64KB H ’0003 0000 H ’0003 FFFF H ’0004 0000 H ’0004 FFFF H ’0005 0000 H ’0005 FFFF H ’0006 0000 H ’0006 FFFF H ’0007 0000 H ’0007 FFFF H ’0008 0000 H ’0008 FFFF Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8 Uneven blocks Even blocks Block 9 Block 10 Block 11 Block 12 Block 13 Block 14

6-31 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.5.8 Block Configuration of the M32170F4 and M32174F4 Flash Memory M32170F4 ’s and M32174F4’s Internal Flash Memory Area (512KB) H ’0002 0000 8KB 16KB 8KB 32KB 64KB H ’0000 0000 H ’0000 7FFF H ’0000 8000 H ’0001 FFFF H ’0000 3FFF H ’0000 4000 H ’0000 FFFF H ’0001 0000 H ’0000 5FFF H ’0000 6000 64KB H ’0002 FFFF 64KB 64KB 64KB Block 0 64KB 64KB H ’0003 0000 H ’0003 FFFF H ’0004 0000 H ’0004 FFFF H ’0005 0000 H ’0005 FFFF H ’0006 0000 H ’0006 FFFF H ’0007 0000 H ’0007 FFFF Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8 Uneven blocks Even blocks Block 9 Block 10

6-32 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.5.9 Block Configuration of the M32170F3 and M32174F3 Flash Memory M32170F3 ’s and M32174F3’s Internal Flash Memory Area (384KB) H ’0002 0000 8KB 16KB 8KB 32KB 64KB H ’0000 0000 H ’0000 7FFF H ’0000 8000 H ’0001 FFFF H ’0000 3FFF H ’0000 4000 H ’0000 FFFF H ’0001 0000 H ’0000 5FFF H ’0000 6000 64KB H ’0002 FFFF 64KB 64KB 64KB Block 0 H ’0003 0000 H ’0003 FFFF H ’0004 0000 H ’0004 FFFF H ’0005 0000 H ’0005 FFFF Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8 Uneven blocks Even blocks

6-33 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY (4) Block Erase command The Block Erase command erases the contents of internal flash memory one block at a time. For Block Erase, write the command data H'2020 to any address of the internal flash memory. Next, write the Verify command data H'D0D0 to the last even address of the memory block you want to The content of this memory block is erased. With the Block Erase command, you cannot erase the protected blocks. Block Erase is automatically performed by the internal control circuit, and the completion of Block Erase can be verified by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (Refer to Section 6.4.2, "Flash Status Registers.") While the FSTAT bit = 0, you cannot erase the next block. (5) Erase All Unlock Block command The Erase All Unlock Block command erases all memory blocks that are not protected. To erase all unlock blocks, write the command data H'A7A7 to any address of the internal flash memory. Next, write the command data H'D0D0 to any address of the internal flash memory, and all of unprotected memory blocks are erased. (6) Read Status Register command The Read Status Register command reads out the content of Flash Status Register 2 (FSTAT2) that indicates whether flash memory write or erase operation has terminated normally or not. To read Flash Status Register 2, write the command data H'7070 to any address of the internal flash memory. Next, read any address of the internal flash memory, and the content of Flash Status Register 2 (FSTAT2) is read out. (7) Clear Status Register command The Clear Status Register command clears the Flash Status Register 2 (FSTAT2) D10, D11, and D12 bits to 0. Write the command data H'5050 to any address of the internal flash memory, and Flash Status Register 2 is cleared to 0. If an error occurs when programming or erasing the flash memory and the Flash Status Register 2 (FSTAT2) ERASE (Auto Erase operating condition) or WRERR2 (Program operating condition 2) bit is set to 1, you cannot perform the next program or erase operation unless WRERR1 (Program operating condition 1) or WRERR2 (Program operating condition 2) is cleared to 0.

6-34 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 <When reset : Indeterminate> D Bit Name Function R W 0 No functions assigned ? —

1 FLBST0 0 : Protected —

(Lock bit 0) 1 : Not protected 2 - 8 No functions assigned ? —

9 FLBST1 0 : Protected —

(Lock bit 1) 1 : Not protected (Same content as FLBST0 is output.) 10 - 15 No functions assigned ? — The Lock Bit Status Register is a read-only register, which contains said lock bits independently for each block. (8) Read Lock Bit Status command The Read Lock Bit Status command allows you to check whether or not a memory block is protected against program/erase. Write the command data H'7171 to any address of the internal flash memory. Next, read the last even address of the block you want to check (see Table 6.5.3, Table 6.5.4, and Table 6.5.5, "Target Blocks and Specified Addresses"), and the data you read shows whether or not the target block is protected. If the FLBST0 (lock bit 0) bit and FLBST1 (lock bit 1) bit of the data you read are 0s, it means that the target memory block is protected. If the FLBST0 (lock bit 0) bit and FLBST1 (lock bit 1) bit are 1s, it means that the target memory block is not protected. I Lock Bit Status Register (FLBST)

6-35 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Follow the procedure described below to write to the lock bits. a) Setting the lock bit to 0 (protect the block) Issue the Lock Bit Program command (H'7777) to the memory block you want to protect. b) Setting the lock bit to 1 (unprotect the block) After setting the Flash Control Register 2 FPROT bit to invalidate lock bit-effectuated protection, use the Block Erase command (H'2020) or Erase All Unprotect Block command (H'A7A7) to erase the memory block you want to unprotect. This is the only way to unprotect a memory block. You cannot set the lock bit alone to 1. c) Status when the lock bit is reset The lock bit is unaffected by a reset or power outage because it is a nonvolatile bit. (9) Execution flow of each command The diagrams below show an execution flow of each command. Figure 6.5.10 Read Array START Write Read Array command (H'FFFF) to any address of internal flash memory Read the internal flash memory address you want to read END

6-36 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.5.11 Page Program Note 1: Start writing from the beginning of a 256-byte boundary of the flash memory (lower address H'00). Note 2: When Program operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 3: Examine the Flash Status Register 2 ERESE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for program error. END Write data to the internal flash memory address to which you want to write. (Note 1) Increment the previous write address by 2 and write the next data to the new address. Write Page Program command (H'4141) to any address of internal flash memory. Written to the internal flash memory by Page Program (Note 2) Programmed for one page ? NO YES 1 µs wait (by hardware timer or software timer) FSTAT bit = 1 YES NO Go to next page START Read any address of internal flash memory to check for program error. (Note 3) Last address ? YES NO TIME OUT ? 0.5s YES NO Forcibly terminated

6-37 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.5.12 Lock Bit Program Note 1: When Program operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 2: Examine the Flash Status Register 2 ERESE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for program error. END Write Verify command (H'D0D0) to the last even address of the block you want to protect. Written to the lock bit by program (Note 1) Write Lock Bit Program command (H'7777) to any address of internal flash memory. 1 µs wait (by hardware timer or software timer) FSTAT bit = 1 YES NO START Read any address of internal flash memory to check for program error. (Note 2) TIME OUT ? 0.5s YES NO Forcibly terminated

6-38 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.5.13 Block Erase Note 1: When Erase operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 2: Examine the Flash Status Register 2 ERESE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for erase error. END Write Verify command (H'D0D0) to the last even address of the block you want to erase. Flash memory contents erased by Erase program (Note 1) Write Erase command (H'2020) to any address of internal flash memory. 1 µs wait (by hardware timer or software timer) FSTAT bit = 1 YES NO START Read any address of internal flash memory to check for erase error. (Note 2) TIME OUT ? YES NO Forcibly terminated

6-39 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.5.14 Erase All Unlock Block Note 1: When Erase operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 2: Examine the Flash Status Register 2 ERESE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for erase error. END Write Verify command (H'D0D0) to any address in memory blocks you want to erase. Flash memory contents erased by Erase program (Note 1) Write Erase All Unlock Block command (H'A7A7) to any address of internal flash memory. 1 µs wait (by hardware timer or software timer) FSTAT bit = 1 YES NO START Read any address of internal flash memory to check for erase error. (Note 2) TIME OUT ? 10s YES NO Forcibly terminated

6-40 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.5.15 Read Status Register Figure 6.5.17 Read Lock Bit Status Register Figure 6.5.16 Clear Status Register Write Read Status command (H'7070) to any address of internal flash memory. START Read any address of internal flash memory. END Write Clear Status command (H'5050) to any address of internal flash memory. START END Write Read Lock Bit Status command (H'7171) to any address of internal flash memory. START Read the last even address of the block whose status you want to read. END

6-41 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY

6.5.4 Flash Write Time (for Reference)

The time required for writing to the internal flash memory is shown below for your reference. (1) M32170F6 (a) Transfer time by SIO (for a transfer data size of 768 KB) 1/57600 bps × 1 (frame) × 11 (number of transfer bits) × 768 KB 150.2 [s] (b) Flash write time 768 KB/256-byte block × 8 ms 24.6 [s] (c) Erase time (entire area) 50 ms × number of blocks = 750 [ms] (d) Total flash write time (entire 768 KB area)

• When communicating at 57600 bps using UART, the flash write time can be ignored because it is very short compared to the serial communication time. Therefore, the flash write time can be calculated using the equation below: (a) + (c) 151 [s] When writing data to flash memory at high speed by speeding up the serial communication or by other means, the fastest write time possible is as follows: (b) + (c) 25 [s] (2) M32170F4 and M32174F4 (a) Transfer time by SIO (for a transfer data size of 512 KB) 1/57600 bps × 1 (frame) × 11 (number of transfer bits) × 512 KB 100.2 [s] (b) Flash write time 512 KB/256-byte block × 8 ms 16.4 [s] (c) Erase time (entire area) 50 ms × number of blocks = 550 [ms] (d) Total flash write time (entire 512 KB area)
• When communicating at 57600 bps using UART, the flash write time can be ignored because it is very short compared to the serial communication time. Therefore, the flash write time can be calculated using the equation below: (a) + (c) 101 [s] When writing data to flash memory at high speed by speeding up the serial communication or by other means, the fastest write time possible is as follows: (b) + (c) 17 [s] .= . .= . .= . .= . .= . .= . .= . .= .

6-42 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY (3) M32170F3 and M32174F3 (a) Transfer time by SIO (for a transfer data size of 384 KB) 1/57600 bps × 1 (frame) × 11 (number of transfer bits) × 384 KB 75.1 [s] (b) Flash write time 384 KB/256-byte block × 8 ms 12.3 [s] (c) Erase time (entire area) 50 ms × number of blocks = 450 [ms] (d) Total flash write time (entire 384 KB area)

• When communicating at 57600 bps using UART, the flash write time can be ignored because it is very short compared to the serial communication time. Therefore, the flash write time can be calculated using the equation below: (a) + (c) 76 [s] When writing data to flash memory at high speed by speeding up the serial communication or by other means, the fastest write time possible is as follows: (b) + (c) 13 [s] .= . .= . .= . .= .

6-43 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY The table below shows boot memory specifications of the 32170 and 32174. Table 6.6.1 Boot Memory Specifications Item Specification Capacity 8 Kbytes Location address H'8000 0000 - H'8000 1FFF Wait insertion Operates with no wait states (with 40 MHz internal CPU memory clock) Internal bus connection Connected by 32-bit bus Read Can only be read when FP = 1, MOD0 = 1, and MOD1 = 0. When read in other modes,indeterminate values are read out. Cannot be accessed for write. Other Because the boot ROM area is a reserved area that can only be used in boot mode, the program cannot be modified.

6-44 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY

6.7 Virtual Flash Emulation Function

This microcomputer has a special function, called the "Virtual Flash Emulation Function," which allows the internal RAM to be mapped in blocks of 8 Kbytes from the beginning (up to four blocks for the M32170F6, up to three blocks for the M32170F4, M32170F3, M32174F4, and M32174F3) into the internal flash memory area divided in units of 8 Kbytes (L banks). Similarly, this function allows the internal RAM to be mapped in blocks of 4 Kbytes, for the M32170F6 (up to two blocks) starting from the RAM address H'0080 C000, for the M32170F4, M32170F3, M32174F4, and M32174F3 (up to two blocks) starting from the RAM address H'0080 A000 into the internal flash memory area divided in units of 4 Kbytes (S banks). When this function is used, the data placed in 8 Kbyte or 4 Kbyte blocks of internal RAM can be moved to or from the L or S banks in the flash memory that are specified by the Virtual Flash Bank Register. For applications that require modifying data during program operation, this enables dynamic modification of data using 8 Kbytes or 4 Kbytes of RAM areas. The RAM blocks allocated for virtual flash emulation can be read or written to from both internal RAM and internal flash memory areas. This function, when used in combination with the Real-Time Debugger (RTD), permits you to look up or rewrite from outside the data tables created in the internal flash memory, thus facilitating data table tuning from an external device. Before accessing the internal flash memory for programming, be sure to terminate this virtual flash emulation mode. Figure 6.7.1 Internal RAM Bank Configuration of the M32170F6 RAM bank L block 0 (FELBANK0)

8 Kbytes

H ’0080 4000 H ’0080 6000 H ’0080 8000 H ’0080 A000 H ’0080 C000 H ’0080 D000 RAM bank L block 1 (FELBANK1) (FELBANK2) (FELBANK3) (FESBANK0)

4 Kbytes

(FESBANK1)

6-45 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.7.2 Internal RAM Bank Configuration of the M32170F4 and M3170F3 H ’0080 4000 H ’0080 6000 H ’0080 8000 H ’0080 A000 H ’0080 B000 RAM bank L block 0 (FELBANK0) (FELBANK1) (FELBANK2) (FESBANK0) (FESBANK1) Figure 6.7.3 Internal RAM Bank Configuration of the M32174F4 and M32174F3 RAM bank L block 0 (FELBANK0) H'0080 4000 H'0080 6000 H'0080 8000 H'0080 A000 H'0080 B000 RAM bank L block 1 (FELBANK1) (FELBANK2) (FESBANK0) 4K bytes RAM bank S block 1 (FESBANK1) H'0080 C000 H'0080 DFFF Areas usable for virtual-flash emulation Note: The 8-Kbyte area from H'0080 C000 to H'0080 DFFF cannot be used as a virtual-flash emulation area.

6-46 32170/32174 Group User's Manual (Rev. 2.1)

6.7.1 Virtual-Flash Emulation Areas

The following shows the areas in which the virtual-flash emulation function is effective. Using the Virtual-Flash L Bank Registers (FELBANK0–FELBANK3 for the M32170F6 or FELBANK0 –FELBANK2 for the M32170F4, M32170F3, M32174F4, and M32174F3), select an arbitrary L bank area from 8-Kbyte L banks in the flash memory area (by setting the seven start address bits A12–A18 of the desired L bank in the Virtual-Flash L Bank Register LBANKAD bits). Then set the Virtual-Flash L Bank Register MODENL0–3 bits (for the M32170F6) or MODENL0–2 bits (for the M32170F4, M32170F3, M32174F4, and M32174F3) to 1. The selected L bank areas can be replaced with 8-Kbyte blocks of the internal RAM beginning with its start address, up to four blocks for the M32170F6 or up to three blocks for the M32170F4, M32170F3, M32174F4, and M32174F3. Similarly, using the Virtual-Flash S Bank Registers (FESBANK0, FESBANK1), select an arbitrary S bank area from 4-Kbyte S banks in the flash memory (by setting the eight start address bits A12– A19 of each desired S bank in the Virtual-Flash S Bank Register SBANKAD bits). Then set the Virtual-Flash S Bank Register MODENS0 and MODENS1 bits to 1. The selected S bank areas can be replaced with up to two 4-Kbyte blocks of the internal RAM beginning with address H’0080 C000 for the M32170F6 or H’0080 A000 for the M32170F4, M32170F3, M32174F4, and M32174F3. In this way, the M32170F6 can have four 8-Kbyte blocks or L banks and two 4-Kbyte blocks or S banks selected, for a total of up to six banks. For the M32170F4, M32170F3, M32174F4, and M32174F3, three 8-Kbyte blocks or L banks and two 4-Kbyte blocks or S banks can be selected, for a total of up to five banks. Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbyte) to be replaced with is selected according to the priority of Virtual-Flash Bank Registers as follows:

• M32170F6 FELBANK0 > FELBANK1 > FELBANK2 > FELBANK3 > FESBANK0 > FESBANK1
• M32170F4, M32170F3, M32174F4, and M32174F3 FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1 Note 2: During virtual-flash emulation mode, the RAM can be accessed for read and write from the internal RAM area and the area that has been set as a virtual-flash area. Note 3: The internal RAM area from H’0080 C000 to H’0080 DFFF of the M32174F4 and M32174F3 cannot be used as a virtual-flash emulation area. Note 4: When performing virtual-flash read after setting Flash Control Register 1’s Virtual-Flash Emulation Mode bit to 1, be sure to wait for three CPU clock periods or more before performing virtual-flash read after setting the said bit to 1. Note 5: When performing virtual-flash read after setting the Virtual-Flash Bank Register (L Bank or S Bank Register)’s Virtual-Flash Emulation Enable bit and bank address bits, be sure to wait for three CPU clock periods or more before performing virtual-flash read after setting the Virtual-Flash Bank Register. INTERNAL MEMORY

6-47 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.7.4 The M32170F6's Virtual Flash Emulation Area Divided in Units of 8 Kbytes Figure 6.7.5 The M32170F6's Virtual Flash Emulation Area Divided in Units of 4 Kbytes Note 1: If after setting the same bank area in multiple Virtual Flash Bank Registers, you enable the Virtual Flash Emulation Enable bit, the internal RAM area selected in order of priority FELBANK0 > FELBANK1 > FELBANK2 > FELBANK3 > FESBANK0 > FESBANK1 is assigned. Note 2: When you access an 8-Kbyte area (L bank) specified by Virtual Flash L Bank Registers 0-3, its corresponding internal RAM area is accessed. During Virtual Flash Emulation mode, RAM can be read or written to from both internal RAM area and virtual flash setup area. Note 1: If after setting the same bank area in multiple Virtual Flash Bank Registers, you enable the Virtual Flash Emulation Enable bit, the internal RAM area selected in order of priority FELBANK0 > FELBANK1 > FELBANK2 > FELBANK3 > FESBANK0 > FESBANK1 is assigned. Note 2: When you access an 4-Kbyte area (S bank) specified by Virtual Flash S Bank Registers 0,1, its corresponding internal RAM area is accessed. During Virtual Flash Emulation mode, RAM can be read or written to from both internal RAM area and virtual flash setup area. H ’0000 0000 H ’0000 2000 H ’0006 6000 <Internal flash> <Internal RAM> H ’0080 4000 H ’0080 6000 L bank 0 (8 Kbytes) H ’0000 4000 H ’0006 4000 H ’000B E000 H ’000B C000 H ’0080 8000 H ’0080 A000 L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) L bank 50 (8 Kbytes) L bank 51 (8 Kbytes) L bank 94 (8 Kbytes) L bank 95 (8 Kbytes) H'0000 0000 H'0000 1000 <Internal flash> <Internal RAM> H'0080 4000 H'0000 2000 H'000B F000 H'000B E000 H'0080 C000 H'0080 D000 S bank 0 (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes) S bank 190 (4 Kbytes) S bank 191 (4 Kbytes)

6-48 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.7.6 The M32170F4's Virtual Flash Emulation Area Divided in Units of 8 Kbytes Figure 6.7.7 The M32170F4's Virtual Flash Emulation Area Divided in Units of 4 Kbytes Note 1: If after setting the same bank area in multiple Virtual Flash Bank Registers, you enable the Virtual Flash Emulation Enable bit, the internal RAM area selected in order of priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1 is assigned. Note 2: When you access an 8-Kbyte area (L bank) specified by Virtual Flash L Bank Registers 0-2, its corresponding internal RAM area is accessed. During Virtual Flash Emulation mode, RAM can be read or written to from both internal RAM area and virtual flash setup area. Note 1: If after setting the same bank area in multiple Virtual Flash Bank Registers, you enable the Virtual Flash Emulation Enable bit, the internal RAM area selected in order of priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1 is assigned. Note 2: When you access an 4-Kbyte area (S bank) specified by Virtual Flash S Bank Registers 0,1, its corresponding internal RAM area is accessed. During Virtual Flash Emulation mode, RAM can be read or written to from both internal RAM area and virtual flash setup area. H ’0000 0000 H ’0000 2000 <Internal flash> <Internal RAM> H ’0080 4000 H ’0080 6000 L bank 0 (8 Kbytes) H ’0000 4000 H ’0007 E000 H ’0007 C000 H ’0080 8000 L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) L bank 62 (8 Kbytes) L bank 63 (8 Kbytes) H'0000 0000 H'0000 1000 H'0080 4000 H'0000 2000 H'0007 F000 H'0007 E000 H'0080 A000 H'0080 B000 <Internal flash> S bank 0 (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes) S bank 126 (4 Kbytes) S bank 127 (4 Kbytes) <Internal RAM>

6-49 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.7.8 The M32170F3's Virtual Flash Emulation Area Divided in Units of 8 Kbytes Figure 6.7.9 The M32170F3's Virtual Flash Emulation Area Divided in Units of 4 Kbytes Note 1: If after setting the same bank area in multiple Virtual Flash Bank Registers, you enable the Virtual Flash Emulation Enable bit, the internal RAM area selected in order of priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1 is assigned. Note 2: When you access an 8-Kbyte area (L bank) specified by Virtual Flash L Bank Registers 0-2, its corresponding internal RAM area is accessed. During Virtual Flash Emulation mode, RAM can be read or written to from both internal RAM area and virtual flash setup area. Note 1: If after setting the same bank area in multiple Virtual Flash Bank Registers, you enable the Virtual Flash Emulation Enable bit, the internal RAM area selected in order of priority FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1 is assigned. Note 2: When you access an 4-Kbyte area (S bank) specified by Virtual Flash S Bank Registers 0,1, its corresponding internal RAM area is accessed. During Virtual Flash Emulation mode, RAM can be read or written to from both internal RAM area and virtual flash setup area. H’0000 0000 H’0000 2000 <Internal flash> <Internal RAM> H’0080 4000 H’0080 6000 L bank 0 (8 Kbytes) H’0000 4000 H’0005 E000 H’0005 C000 H’0080 8000 L bank 1 (8 Kbytes) L bank 2 (8 Kbytes) L bank 46 (8 Kbytes) L bank 47 (8 Kbytes) H'0000 0000 H'0000 1000 H'0080 4000 H'0000 2000 H'0005 F000 H'0005 E000 H'0080 A000 H'0080 B000 <Internal flash> S bank 0 (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes) S bank 94 (4 Kbytes) S bank 95 (4 Kbytes) <Internal RAM>

6-50 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.7.10 The M32174F4's Virtual Flash Emulation Area Divided in Units of 8 Kbytes Figure 6.7.11 The M32174F4's Virtual Flash Emulation Area Divided in Units of 4 Kbytes Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area to be replaced with is selected by priority: FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) selected by one of Virtual-Flash L Bank Registers 0–2, what actually is accessed is the internal RAM area. During virtual-flash emulation mode, it is possible to read and write to RAM from both the internal RAM area and the area that has been set as a virtual-flash area. Note 3: The internal RAM area from H’0080 C000 to H’0080 DFFF cannot be used as a virtual-flash emulation area. Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area to be replaced with is selected by priority: FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 4-Kbyte area (S bank) selected by Virtual-Flash S Bank Register 0 or 1, what actually is accessed is the internal RAM area. During virtual-flash emulation mode, it is possible to read and write to RAM from both the internal RAM area and the area that has been set as a virtual-flash area. Note 3: The internal RAM area from H’0080 C000 to H’0080 DFFF cannot be used as a virtual-flash emulation area. H'0000 0000 H'0000 2000 <Internal flash> L Bank 1 (8 Kbytes) L Bank 0 (8 Kbytes) H'0000 4000 L Bank 2 (8 Kbytes) L Bank 63 (8 Kbytes) L Bank 62 (8 Kbytes) H'0007 E000 H'0007 C000 <Internal RAM> H'0080 4000 H'0080 6000 H'0080 8000 H'0080 C000 H'0080 DFFF H'0000 0000 H'0000 1000 <Internal flash> <Internal RAM> S Bank 1 (4 Kbytes) H'0080 4000 S Bank 0 (4 Kbytes) H'0000 2000 S Bank 2 (4 Kbytes) (4 Kbytes) S Bank 126 (4 Kbytes) H'0007 F000 H'0007 E000 H'0080 A000 H'0080 B000 H'0080 C000 H'0080 DFFF

6-51 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.7.12 The M32174F3's Virtual Flash Emulation Area Divided in Units of 8 Kbytes Figure 6.7.13 The M32174F3's Virtual Flash Emulation Area Divided in Units of 4 Kbytes Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area to be replaced with is selected by priority: FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) selected by one of Virtual-Flash L Bank Registers 0–2, what actually is accessed is the internal RAM area. During virtual-flash emulation mode, it is possible to read and write to RAM from both the internal RAM area and the area that has been set as a virtual-flash area. Note 3: The internal RAM area from H’0080 C000 to H’0080 DFFF cannot be used as a virtual-flash emulation area. Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area to be replaced with is selected by priority: FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 4-Kbyte area (S bank) selected by Virtual-Flash S Bank Register 0 or 1, what actually is accessed is the internal RAM area. During virtual-flash emulation mode, it is possible to read and write to RAM from both the internal RAM area and the area that has been set as a virtual-flash area. Note 3: The internal RAM area from H’0080 C000 to H’0080 DFFF cannot be used as a virtual-flash emulation area. H'0000 0000 H'0000 2000 <Internal flash> L Bank 1 (8 Kbytes) L Bank 0 (8 Kbytes) H'0000 4000 L Bank 2 (8 Kbytes) L Bank 47 (8 Kbytes) L Bank 46 (8 Kbytes) H'0005 E000 H'0005 C000 <Internal RAM> H'0080 4000 H'0080 6000 H'0080 8000 H'0080 C000 H'0080 DFFF H'0000 0000 H'0000 1000 <Internal flash> <Internal RAM> S Bank 1 (4 Kbytes) H'0080 4000 S Bank 0 (4 Kbytes) H'0000 2000 S Bank 2 (4 Kbytes) (4 Kbytes) S Bank 94 (4 Kbytes) H'0005 F000 H'0005 E000 H'0080 A000 H'0080 C000 H'0080 DFFF H'0080 B000

6-52 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.7.14 Values Set in the M32170F6's Virtual Flash Bank Register when Divided in Units of 8 Kbytes Figure 6.7.15 Values Set in the M32170F6's Virtual Flash Bank Register when Divided in Units of 4 Kbytes Note: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Note: Set the eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. H ’0000 0000 L bank Start address of bank in flash memory L bank address (LBANKAD) bit set value H ’0000 2000 H ’0000 4000 H ’000B C000 H ’000B E000 H ’00 H ’02 H ’04 H ’BC H ’BE (Note) L bank 0 L bank 1 L bank 2 L bank 94 L bank 95 H ’0000 0000 S bank Start address of bank in flash memory S bank address (SBANKAD) bit set value H ’0000 1000 H ’0000 2000 H ’000B E000 H ’000B F000 H ’00 H ’01 H ’02 H ’BE H ’BF (Note) S bank 0 S bank 1 S bank 2 S bank 190 S bank 191

6-53 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.7.16 Values Set in the M32170F4's and the M32174F4's Virtual Flash Bank Register when Divided in Units of 8 Kbytes Figure 6.7.17 Values Set in the M32170F4's and the M32174F4's Virtual Flash Bank Register when Divided in Units of 4 Kbytes Note: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Note: Set the eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. H ’0000 0000 L bank Start address of bank in flash memory L bank address (LBANKAD) bit set value H ’0000 2000 H ’0000 4000 H ’0007 C000 H ’0007 E000 H ’00 H ’02 H ’04 H ’7C H ’7E (Note) L bank 0 L bank 1 L bank 2 L bank 62 L bank 63 H ’0000 0000 S bank Start address of bank in flash memory S bank address (SBANKAD) bit set value H ’0000 1000 H ’0000 2000 H ’0007 E000 H ’0007 F000 H ’00 H ’01 H ’02 H ’7E H ’7F (Note) S bank 0 S bank 1 S bank 2 S bank 126 S bank 127

6-54 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.7.18 Values Set in the M32170F3's and the M32174F3's Virtual Flash Bank Register when Divided in Units of 8 Kbytes Figure 6.7.19 Values Set in the M32170F3's and the M32174F3's Virtual Flash Bank Register when Divided in Units of 4 Kbytes Note: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Note: Set the eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. H ’0000 0000 L bank Start address of bank in flash memory L bank address (LBANKAD) bit set value H ’0000 2000 H ’0000 4000 H ’0005 C000 H ’0005 E000 H ’00 H ’02 H ’04 H ’5C H ’5E (Note) L bank 0 L bank 1 L bank 2 L bank 46 L bank 47 H ’0000 0000 S bank Start address of bank in flash memory S bank address (SBANKAD) bit set value H ’0000 1000 H ’0000 2000 H ’0005 E000 H ’0005 F000 H ’00 H ’01 H ’02 H ’5E H ’5F (Note) S bank 0 S bank 1 S bank 2 S bank 94 S bank 95

6-55 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY

6.7.2 Entering Virtual Flash Emulation Mode

To enter Virtual Flash Emulation Mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit to 1. After entering Virtual Flash Emulation Mode, set the Virtual Flash Bank Register MODEN bit to 1 to enable the Virtual Flash Emulation Function. Even during virtual-flash emulation mode, the internal RAM area (H’0080 4000 to H’0080 DFFF for the M32170F6, H’0080 4000 to H’0080 BFFF for the M32170F4 and M32170F3, or H’0080 4000 to H ’0080 DFFF for the M32174F4 and M32174F3) can be accessed as internal RAM. Figure 6.7.20 Virtual Flash Emulation Mode Sequence Set RAM location address in Virtual Flash Bank Register LBANKADn ← Address A12-A18 SBANKADn ← Address A12-A19 Write flash data to RAM Enable Virtual Flash Emulation Function MODENLn ← 1 MODENSn ← 1 Settings completed Go to Virtual Flash Emulation Mode FEMMOD ← 1 Settings completed

6-56 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY

6.7.3 Application Example of Virtual Flash Emulation Mode

By locating two RAM areas in the same virtual flash area using the Virtual Flash Emulation Function, you can rewrite data in the flash memory successively. Figure 6.7.21 Application Example of Virtual Flash Emulation (1/2) Replace area Flash RAM block 0 Data write to RAM0 (1) Operation when reset (2) Program operation using RAM block 0 Initial value (3) Program operation changed from RAM block 0 to RAM block 1 Bank xx Bank xx specified RAM block 0 RAM block 1 Replace Flash RAM block 0 Data write to RAM1 Initial value Bank xx RAM block 1 Bank xx specified RAM block 0 Replace Flash RAM block 0 Initial value Bank xx RAM block 1 RAM block 1 Bank xx specified (settings invalid)

6-57 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY Figure 6.7.22 Application Example of Virtual Flash Emulation (2/2) (6) Go to item (2) Note : valid area (4) Program operation using RAM block 1 Bank xx specified RAM block 1 Replace Flash RAM block 0 Data write to RAM0 Initial value Bank xx RAM block 1 (5) Program operation changed from RAM block 1 to RAM block 0 Bank xx specified RAM block 0 Replace Flash RAM block 0 Initial value Bank xx RAM block 1 RAM block 1 Bank xx specified (settings invalid)

6-58 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY

6.8 Connecting to A Serial Programmer

When you rewrite the internal flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode, you need to process the pins on the 32170 and 32174 shown below to make them suitable for the serial programmer. Table 6.8.1 Processing the 32170 Pins when Using a Serial Programmer Pin Name Pin Number Function Remark FP MOD0 RESET SCLKI1 RXD1 TXD1 P84 VCCE VCCI VSS 156 154 153 121 120 119 118 205 98,126,137,171,195,225 115,127,129,138,158, 172,196,206,226 OSC-VCC 21 XOUT 20 XIN 19 OSC-VSS 18 VREF0 VREF1 227 AVCC0 AVCC1 228 AVSS0 AVSS1 FVCC 128 VDD 170 Transfer clock input Serial data input (receive data) Serial data output (transmit data) Transmit/receive enable output Flash memory protect Operation mode 1 Reset Clock input Clock output PLL circuit power supply PLL circuit ground PLL circuit control inputVCNT 23 A-D converter reference voltage input Analog power supply Analog ground Flash memory power supply RAM backup power supply

5 V power supply

Connect to 3.3 V power supply Connect to 5 V power supply Note: All other pins do not need to be processed. P83 117 Transmit/receive control Need to be pulled high Need to be pulled high Need to be pulled high Connect to ground Connect to ground Connect to 5 V power supply Connect to 3.3 V power supply Connect to 3.3 V power supply

3.3 V power supply

6-59 32170/32174 Group User's Manual (Rev. 2.1) INTERNAL MEMORY The diagram below shows an example of user system configuration which has had a serial programmer connected. After the user system is powered on, the serial programmer writes to the flash memory in clock-synchronized serial mode. No communication problems associated with the oscillation frequency may occur. If the system uses any 32170/32174 pins which will connect to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the addresses H'0000 0084 through H'0000 0093 as an area to check ID for flash memory protection. Figure 6.8.1 Pin Connection Diagram Note 1 : Turn on the power to the user system before you write to the flash memory. Note 2 : If the system circuit uses P83-P87, consideration must be taken for connection of a serial programmer. Note 3 : P83 must have a high-level signal applied to it. Note 4 : P64/SBI must be fixed high or low to ensure that interrupts will not be generated. Note 5 : The pullup resistances of P83, P84, P86, and P87 must be set to suit system design conditions. Note 6 : The typical pullup resistances of P83, P84, P86, and P87 are 4.7 to 10 kΩ . Note 7 : All other ports, whether high or low, do not affect flash memory programming. VREF0, VREF1 32170 32174 VDD VCCI AVCC0, AVCC1 OSC-VCC VCCE Connects to 5 V power supply P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P84/SCLKI0/SCLKO0 Connector Various signals on flash programmer MOD0 FP RESET VSS Set microcomputer operating conditions XIN XOUT VCNT AVSS0, AVSS1 OSCVSS To system circuit P83/RXD0 RxD (Input) TxD (Output) SCLKO(Output) BUSY (Input) MOD0 (Output) FP (Output) RESET(Output) GND (Output) 5V (Input) User system circuit board FVCC MOD1 Connects to 3.3 V power supply

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6.9 Precautions to Be Taken When Rewriting Flash Memory

The following describes precautions to be taken when you rewrite the flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode.

• When you use the pins with the system that are used by a serial programmer, take measures not to affect the system when connecting a serial programmer.
• If the flash memory needs to be protected, set an appropriate ID in the flash memory protect ID verification area (H'0000 0084 through H'0000 0093).
• If the flash memory does not require protection, fill the entire flash memory protect ID verification area (H'0000 0084 through H'0000 0093) with H'FF.
• Do not use wait function when entering the flash E/W mode because it may validate wait state if a low-level signal is applied to the WAIT# pin. INTERNAL MEMORY

7.1 Outline of Reset

7.2 Reset Operation

7.3 Internal State Immediately

7.4 Things To Be Considered after

7-2 32170/32174 Group User's Manual (Rev. 2.1) The device is reset by applying a low-level signal to the RESET input pin. The device is gotten out of a reset state by releasing the RESET input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the program starts executing from the reset vector entry.

7.2.1 Reset at Power-on

When powering on the device, hold the RESET input low until its internal multiply-by-4 clock generator becomes oscillating stably.

7.2.2 Reset during Operation

To reset the device during operation, hold the RESET input low for more than four clock periods of XIN signal.

7.2.3 Reset Vector Relocation during Flash Rewrite

When placed in boot mode, the reset vector entry address is moved to the start address of the boot program space (address H'8000 0000). For details, refer to Section 6.5, "Programming of Internal Flash Memory." RESET

7-3 32170/32174 Group User's Manual (Rev. 2.1) RESET

7.3 Internal State Immediately after Reset Release

The table below lists the register state of the device immediately after it has gotten out of reset. For details about the initial register state of each internal peripheral I/O, refer to each section in this manual where the relevant internal peripheral I/O is described. Table 7.3.1 Internal State Immediately after Reset Register State after Reset Release PSW (CR0) B'0000 0000 0000 0000 ??00 000? 0000 0000 (BSM, BIE, BC bits = indeterminate) CBR (CR1) H'0000 0000 (C bit = 0) SPI (CR2) Indeterminate SPU (CR3) Indeterminate BPC (CR6) Indeterminate PC H'0000 0000 (Executed beginning with address H'0000 0000) (Note) ACC (accumulator) Indeterminate Note: When in boot mode, this changes to the start address of the boot program space (H'8000 0000).

7-4 32170/32174 Group User's Manual (Rev. 2.1) RESET Pin name Single chip External extension Microprocessor Boot Reset, MOD0, MOD1, and FP Input Input Input Input Port Input Input Input Input Hi-Z P00 - P07, P10 - P17, P61 - P67, P70 - P77, P82 - P87, P93 - P97, P100 - P107, P110 - P117, P124 - P127, P130 - P137, P140 - P147, P150 - P157, P160 - P167, P172 - P177, P180 - P187, P190 - P197, P200 - P203, P210 - P217, P220 - P225 AD0IN0 - 7 AD1IN0 - 7 Input Input Input Input Input Input Input JTAG JTDO Input Input Input Input Indeterminate Indeterminate Indeterminate Indeterminate JTDI, JTMS, JTCK, JTRST Mode P20 - P27, P30 - P37, P41 - P47 A-D converter XIN XOUT VCNT (Note 1) Input Input Input Input Output Output Output Output —— —— DBI EVENT[0:1] TRCLK TRSYNC (Note 4) TRDATA[0:7] (Note 3) (Note 4) (Note 4) (Note 4) (Note 4) Indeterminate Indeterminate Indeterminate Indeterminate High output High output High output High output Low-level output Low-level output Low-level output Low-level output Low-level output Low-level output Low-level output Low-level output High-level output High-level output High-level output High-level output (Note 2) Table 7.3.2 Pin Status When Reset Note 1: The VCNT pin is used to control the PLL circuit. Note 2: The JTAG pin is not initialized by a reset. It can be reset by pulling JTRST low. Note 3: The DBI pin is pulled high internally. Note 4: This applies only when using 255FBAG (not available when using 240QFP).

7-5 32170/32174 Group User's Manual (Rev. 2.1) RESET

7.4 Things To Be Considered after Reset Release

• Input/output ports After reset release, the 32170's and 32174's input/output ports are disabled against input in order to prevent current from flowing through the port. To use any ports in input mode, enable them for input using the Port Input Function Enable Register (PIEN) PIEN0 bit. For details, refer to Section 8.3, "Input/Output Port Related Registers."

7-6 32170/32174 Group User's Manual (Rev. 2.1) RESET ❊ This is a blank page. ❊

8.1 Outline of Input/Output Ports

8.2 Selecting Pin Functions

8.3 Input/Output Port Related

8.4 Port Peripheral Circuits

8.5 Precautions on Input/output Ports

8-2 32170/32174 Group User's Manual (Rev. 2.1) This microcomputer has a total of 157 input/output ports from P0 to P22 (of which P5 is reserved for future use, however). These input/output ports can be set for input or output mode by a direction register. Each input/output port serves as a dual-function or triple-function pin, sharing the pin with other internal peripheral I/O or extended external bus signal line. Pin functions are selected depending on the device's operation mode you choose or by setting the input/output port's Operation Mode Register. (If any internal peripheral I/O has still another function, you need to set the register provided for that peripheral I/O.) As a new function, the 32170 internally contains a Port Input Function Enable bit that can be used to prevent current from flowing into the input ports. This helps to simplify the software and hardware processing to be performed immediately after reset or during flash rewrite. To use any ports in input mode, you need to set the Port Input Function Enable bit accordingly. The input/output ports are outlined in the next pages. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-3 32170/32174 Group User's Manual (Rev. 2.1) P3 : P30 - P37 (8 lines) P4 : P41 - P47 (7 lines) P6 : P61 - P67 (7 lines) P7 : P70 - P77 (8 lines) P8 : P82 - P87 (6 lines) P9 : P93 - P97 (5 lines) P10 : P100 - P107 (8 lines) P11 : P110 - P117 (8 lines) P12 : P124 - P127 (4 lines) P13 : P130 - P137 (8 lines) P14 : P140 - P147 (8 lines) P15 : P150 - P157 (8 lines) P16 : P160 - P167 (8 lines) P17 : P172 - P177 (6 lines) P18 : P180 - P187 (8 lines) P19 : P190 - P197 (8 lines) P20 : P200 - P203 (4 lines) P21 : P210 - P217 (8 lines) P22 : P220 - P225 (6 lines) Port function The input/output ports can individually be set for input or output mode using the ___ Direction Control Register provided for each input/output port. (However, P64 is an SBI input-only port and P221 is a CAN input-only port.) Pin function Shared with peripheral I/O or extended external signals to serve dual functions (or with two or more peripheral I/O functions to serve multiple functions) Pin function switchover P0 - P4, P224, P225 : Depends on CPU operation mode (determined by setting MOD0 and MOD1 pins) P6 - P22 : As set by each input/output port's Operation Mode Register (However, peripheral I/O pin functions are selected by peripheral I/O registers.) INPUT/OUTPUT PORTS AND PIN FUNCTIONS Table 8.1.1 Outline of Input/Output Ports Item Specification Number of ports Total 157 lines P0 : P00 - P07 (8 lines) P1 : P10 - P17 (8 lines) P2 : P20 - P27 (8 lines)

8-4 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS Each input/output port serves dual functions sharing the pin with other internal peripheral I/O or extended external bus signal line (or triple functions sharing the pin with two or more peripheral I/O functions). Pin functions are selected depending on the device's operation mode you choose or by setting the input/output port's Operation Mode Register. P0-P4, P224, and P225, when the CPU is set to operate in extended external mode or processor mode, all are switched to serve as signal pins for external access. The CPU operation mode is determined by setting the MOD0 and MOD1 pins (see the table below). Table 8.2.1 CPU Operation Mode and Pin Functions of P0-P4, P224, and P225 MOD0 MOD1 Operation Mode Pin Functions of P0-P4, P224, and P225 VSS VSS Single-chip mode input/output port pin VSS VCCE Extended external mode Extended external signal pin VCCE VSS Processor mode VCCE VCCE Reserved (Use inhibited) — Note: VCCE and VSS are connected to +5 V and GND, respectively. P6-P22 (except P64, P221, P224, and P225) have their pin functions switched between input/ output port pins and internal peripheral I/O pins by setting each port's Operation Mode Register. If any internal peripheral I/O has multiple pin functions, you need to set the register provided for that peripheral I/O to select the desired pin function. Note that settings of FP pin and MOD1 pin during internal flash memory write operation do not affect the pin functions.

8-5 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS Figure 8.2.1 Input/Output Ports and Pin Function Assignments Note 1: Pin functions are switched over by setting MOD0 and MOD1 pins. Note 2: Pin functions are switched over by setting MOD0 and MOD1 pins. Also, use of this pin requires caution because it has a debug event function. P10 P11 P12 P13 P14 P15 DB0 01234567 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 A23 A24 A25 A26 A27 A28 A29 A30 A15 A16 A17 A18 A19 A20 A21 A22 BLW/ BLE BHW/ BHE RD CS0 CS1 A13 A14 (P61) (P62) (P63) SBI SCLKI4/ SCLKO4 ADTRG BCLK/ WR WAIT HREQ HACK RTDTXD RTDRXD RTDACK RTDCLK TXD0 RXD0 SCLKI0/ SCLKO0 TXD1 RXD1 SCLKI1/ SCLKO1 TO16 TO17 TO18 TO19 TO20 TO11 TO12 TO13 TO14 TO15TO10TO9TO8 TO3 TO4 TO5 TO6 TO7TO2TO1TO0 TCLK0 TCLK1 TCLK2 TCLK3 TIN16 TIN17 TIN18 TIN19 TIN20 TIN21 TIN22 TIN23 TIN8 TIN9 TIN10 TIN11 TIN12 TIN13 TIN14 TIN15 TIN0 TIN1 TIN2 TIN3 TIN4 TIN5 TIN6 TIN7 Settings of CPU operation mode (Note 1) (Reserved) Settings of input/ output port Operation Mode Register P16 TO21 TO22 TO23 TO24 TO25 TO26 TO27 TO28 P17 TIN24 TIN25 TXD2 RXD2 TXD3 RXD3 P18 P19 TO29 TO30 TO31 TO32 TO33 TO34 TO35 TO36 P20 TXD4 RXD4 RXD5 P21 TO37 TO38 TO39 TO40 TO41 TO42 TO43 TO44 P22 CTX CRX (P222) (P223) A11 (Note 2) A12 (Note 2) TIN26 TIN27 TIN28 TIN29 TIN30 TIN31 TIN32 TIN33 TXD5 SCLKI5/ SCLKO5

8-6 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8.3 Input/Output Port Related Registers

Included in the 32170 as input/output port related registers are the Port Data Registers, Port Direction Registers, and Port Operation Mode Registers. Of these, the Port Operation Mode Registers are provided for only P6-P22. Ports P0-P4, P224, and P225 have their pin functions determined by setting the CPU operation mode (FP, MOD0, and MOD1 pins). Port P5 is reserved for future use. The tables below show an input/output port related register map. Figure 8.3.1 Input/Output Port Related Register Map (1/2) Address D0 D7+0 Address D8 D15 Blank addresses are reserved. P1 Data Register (P1DATA) P3 Data Register (P3DATA) P7 Data Register (P7DATA) P9 Data Register (P9DATA) P11 Data Register (P11DATA) P13 Data Register (P13DATA) P15 Data Register (P15DATA) P1 Direction Register (P1DIR) P3 Direction Register (P3DIR) P7 Direction Register (P7DIR) P9 Direction Register (P9DIR) P11 Direction Register (P11DIR) P17 Data Register (P17DATA) P19 Data Register (P19DATA) P21 Data Register (P21DATA) P13 Direction Register (P13DIR) P15 Direction Register (P15DIR) P17 Direction Register (P17DIR) P19 Direction Register (P19DIR) P21 Direction Register (P21DIR) H'0080 0700 H'0080 0702 H'0080 0704 H'0080 0706 H'0080 0708 H'0080 070A H'0080 070C H'0080 070E H'0080 0720 H'0080 0722 H'0080 0724 H'0080 0726 H'0080 0728 H'0080 072A H'0080 072C H'0080 072E H'0080 0710 H'0080 0730 H'0080 0712 H'0080 0714 H'0080 0716 H'0080 0732 H'0080 0734 H'0080 0736 P0 Data Register (P0DATA) P2 Data Register (P2DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P8 Data Register (P8DATA) P10 Data Register (P10DATA) P12 Data Register (P12DATA) P14 Data Register (P14DATA) P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P8 Direction Register (P8DIR) P10 Direction Register (P10DIR) P16 Data Register (P16DATA) P18 Data Register (P18DATA) P20 Data Register (P20DATA) P22 Data Register (P22DATA) P12 Direction Register (P12DIR) P14 Direction Register (P14DIR) P16 Direction Register (P16DIR) P18 Direction Register (P18DIR) P20 Direction Register (P20DIR) P22 Direction Register (P22DIR) +1 Address

8-7 32170/32174 Group User's Manual (Rev. 2.1)

8.3.2 Input/Output Port Related Register Map (2/2)

INPUT/OUTPUT PORTS AND PIN FUNCTIONS P7 Operation Mode Register (P7MOD) P9 Operation Mode Register (P9MOD) P11 Operation Mode Register (P11MOD) P13 Operation Mode Register (P13MOD) P15 Operation Mode Register (P15MOD) P17 Operation Mode Register (P17MOD) Port Input Function Enable Register (PIEN) P19 Operation Mode Register (P19MOD) P21 Operation Mode Register (P21MOD) P6 Operation Mode Register (P6MOD) P8 Operation Mode Register (P8MOD) P10 Operation Mode Register (P10MOD) P12 Operation Mode Register (P12MOD) P14 Operation Mode Register (P14MOD) P16 Operation Mode Register (P16MOD) P18 Operation Mode Register (P18MOD) P20 Operation Mode Register (P20MOD) P22 Operation Mode Register (P22MOD) H'0080 0746 H'0080 0748 H'0080 074A H'0080 074C H'0080 074E H'0080 0750 H'0080 0744 H'0080 0752 H'0080 0754 H'0080 0756 Blank addresses are reserved. Address D0 D7+0 Address D8 D15 +1 Address

8-8 32170/32174 Group User's Manual (Rev. 2.1)

8.3.1 Port Data Registers

I P0 Data Register (P0DATA) <Address: H'0080 0700> I P1 Data Register (P1DATA) <Address: H'0080 0701> I P2 Data Register (P2DATA) <Address: H'0080 0702> I P3 Data Register (P3DATA) <Address: H'0080 0703> I P4 Data Register (P4DATA) <Address: H'0080 0704> I P6 Data Register (P6DATA) <Address: H'0080 0706> I P7 Data Register (P7DATA) <Address: H'0080 0707> I P8 Data Register (P8DATA) <Address: H'0080 0708> I P9 Data Register (P9DATA) <Address: H'0080 0709> I P10 Data Register (P10DATA) <Address: H'0080 070A> I P11 Data Register (P11DATA) <Address: H'0080 070B> I P12 Data Register (P12DATA) <Address: H'0080 070C> I P13 Data Register (P13DATA) <Address: H'0080 070D> I P14 Data Register (P14DATA) <Address: H'0080 070E> I P15 Data Register (P15DATA) <Address: H'0080 070F> I P16 Data Register (P16DATA) <Address: H'0080 0710> I P17 Data Register (P17DATA) <Address: H'0080 0711> I P18 Data Register (P18DATA) <Address: H'0080 0712> I P19 Data Register (P19DATA) <Address: H'0080 0713> I P20 Data Register (P20DATA) <Address: H'0080 0714> I P21 Data Register (P21DATA) <Address: H'0080 0715> I P22 Data Register (P22DATA) <Address: H'0080 0716> INPUT/OUTPUT PORTS AND PIN FUNCTIONS ( D8 9 10 11 12 13 14 D15 ) Pn0DT Pn1DT Pn2DT Pn3DT Pn4DT Pn5DT Pn6DT Pn7DT Note: n = 0 to 22 (except for P5)

8-9 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS <When reset : Indeterminate> D Bit Name Function R W

0 Pn0DT (Port Pn0 data) Depending on how the Port Direction Register is set

1 Pn1DT (Port Pn1 data) • When direction bit = 0 (input mode)

2 Pn2DT (Port Pn2 data) 0: Port input pin = low

3 Pn3DT (Port Pn3 data) 1: Port input pin = high

4 Pn4DT (Port Pn4 data) • When direction bit = 1 (output mode)

5 Pn5DT (Port Pn5 data) 0: Port output latch = low

6 Pn6DT (Port Pn6 data) 1: Port output latch = high

7 Pn7DT (Port Pn7 data)

Note 1: The following bits have no functions assigned (when read, the bit = 0; writing to the bit has no effect). P40, P60, P90-P92, P120-P123, P170, P171, P204-P207, P226, P227 Note 2: Port P64 is input mode-only. Writing to the P64DT bit has no effect. Note 3: Port P221 is input mode-only. Writing to the P221DT bit has no effect. Note 4: Ports P80 and P81 are input mode-only. Writing to the P80DT and P81DT bits has no effect. When read out, P80 shows the MOD0 pin level and P81 shows the MOD1 pin level. The P80DT and P81DT bits are write-protected.

8-10 32170/32174 Group User's Manual (Rev. 2.1)

8.3.2 Port Direction Registers

I P0 Direction Register (P0DIR) <Address: H'0080 0720> I P1 Direction Register (P1DIR) <Address: H'0080 0721> I P2 Direction Register (P2DIR) <Address: H'0080 0722> I P3 Direction Register (P3DIR) <Address: H'0080 0723> I P4 Direction Register (P4DIR) <Address: H'0080 0724> I P6 Direction Register (P6DIR) <Address: H'0080 0726> I P7 Direction Register (P7DIR) <Address: H'0080 0727> I P8 Direction Register (P8DIR) <Address: H'0080 0728> I P9 Direction Register (P9DIR) <Address: H'0080 0729> I P10 Direction Register (P10DIR) <Address: H'0080 072A> I P11 Direction Register (P11DIR) <Address: H'0080 072B> I P12 Direction Register (P12DIR) <Address: H'0080 072C> I P13 Direction Register (P13DIR) <Address: H'0080 072D> I P14 Direction Register (P14DIR) <Address: H'0080 072E> I P15 Direction Register (P15DIR) <Address: H'0080 072F> I P16 Direction Register (P16DIR) <Address: H'0080 0730> I P17 Direction Register (P17DIR) <Address: H'0080 0731> I P18 Direction Register (P18DIR) <Address: H'0080 0732> I P19 Direction Register (P19DIR) <Address: H'0080 0733> I P20 Direction Register (P20DIR) <Address: H'0080 0734> I P21 Direction Register (P21DIR) <Address: H'0080 0735> I P22 Direction Register (P22DIR) <Address: H'0080 0736> INPUT/OUTPUT PORTS AND PIN FUNCTIONS ( D8 9 10 11 12 13 14 D15 ) Pn0DIR Pn1DIR Pn2DIR Pn3DIR Pn4DIR Pn5DIR Pn6DIR Pn7DIR Note: n = 0 to 22 (except for P5)

8-11 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS <When reset : H'00> D Bit Name Function R W

0 Pn0DIR (Port Pn0 direction bit) 0: Input mode (when reset)

1 Pn1DIR (Port Pn1 direction bit) 1: Output mode

2 Pn2DIR (Port Pn2 direction bit)

3 Pn3DIR (Port Pn3 direction bit)

4 Pn4DIR (Port Pn4 direction bit)

5 Pn5DIR (Port Pn5 direction bit)

6 Pn6DIR (Port Pn6 direction bit)

7 Pn7DIR (Port Pn7 direction bit)

Note 1: The following bits have no functions assigned (when read, the bit = 0; writing to the bit has no effect). P40, P60, P64, P80, P81, P90-P92, P120-P123, P170, P171, P204-P207, P221, P226, P227 Note 2: When reset, all ports are placed in input mode. Note 3: Port P64 is input mode-only. The register does not have a P64DIR bit. Note 4: Ports P80 and P81 are input mode-only. The register does not have P80DIR and P81DIR bits. Note 5: Port P221 is input mode-only. The register does not have a P221DIR bit.

8-12 32170/32174 Group User's Manual (Rev. 2.1)

8.3.3 Port Operation Mode Registers

I P6 Operation Mode Register (P6MOD) <Address: H'0080 0746> INPUT/OUTPUT PORTS AND PIN FUNCTIONS <When reset : H'00> D Bit Name Function R W 0 - 4 No functions assigned 0 —

5 P65MOD 0 : P65

(Port P65 operation mode) 1 : SCLKI4 / SCLKO4

6 P66MOD 0 : P66

(Port P66 operation mode) 1 : SCLKI5 / SCLKO5

7 P67MOD 0 : P67

(Port P67 operation mode) 1 : ADTRG Note 1: Port 60 is not accommodated. Note 2: Ports P61-P63 are always input/output ports (single-function pins). ___ Note 3: Port P64 is an SBI input-only pin. The pin level can be verified by reading the P64 Data Register.

8-13 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P7 Operation Mode Register (P7MOD) <Address: H'0080 0747> D 8 9 1 01 11 21 31 4 D 1 5 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD <When reset : H'00> D Bit Name Function R W

8 P70MOD 0 : P70

(Port P70 operation mode) 1 : BCLK / WR

9 P71MOD 0 : P71

(Port P71 operation mode) ____ 1 : WAIT

10 P72MOD 0 : P72

(Port P72 operation mode) ____ 1 : HREQ

11 P73MOD 0 : P73

(Port P73 operation mode) ____ 1 : HACK

12 P74MOD 0 : P74

(Port P74 operation mode) 1 : RTDTXD

13 P75MOD 0 : P75

(Port P75 operation mode) 1 : RTDRXD

14 P76MOD 0 : P76

(Port P76 operation mode) 1 : RTDACK

15 P77MOD 0 : P77

(Port P77 operation mode) 1 : RTDCLK

8-14 32170/32174 Group User's Manual (Rev. 2.1) I P8 Operation Mode Register (P8MOD) <Address: H'0080 0748> INPUT/OUTPUT PORTS AND PIN FUNCTIONS P82MOD P83MOD P84MOD P85MOD P86MOD P87MOD <When reset : H'00> D Bit Name Function R W 0, 1 No functions assigned 0 —

2 P82MOD 0 : P82

(Port P82 operation mode) 1 : TXD0

3 P83MOD 0 : P83

(Port P83 operation mode) 1 : RXD0

4 P84MOD 0 : P84

(Port P84 operation mode) 1 : SCLKI0 / SCLKO0

5 P85MOD 0 : P85

(Port P85 operation mode) 1 : TXD1

6 P86MOD 0 : P86

(Port P86 operation mode) 1 : RXD1

7 P87MOD 0 : P87

(Port P87 operation mode) 1 : SCLKI1 / SCLKO1 Note : Ports P80 and P81 are not accommodated.

8-15 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P9 Operation Mode Register (P9MOD) <Address: H'0080 0749> D 8 9 1 01 11 21 31 4 D 1 5 P93MOD P94MOD P95MOD P96MOD P97MOD <When reset : H'00> D Bit Name Function R W 8 - 10 No functions assigned 0 —

11 P93MOD 0 : P93

(Port P93 operation mode) 1 : TO16

12 P94MOD 0 : P94

(Port P94 operation mode) 1 : TO17

13 P95MOD 0 : P95

(Port P95 operation mode) 1 : TO18

14 P96MOD 0 : P96

(Port P96 operation mode) 1 : TO19

15 P97MOD 0 : P97

(Port P97 operation mode) 1 : TO20 Note : Ports P90 - P92 are not accommodated.

8-16 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P10 Operation Mode Register (P10MOD) <Address: H'0080 074A> D 0 123456 D 7 P100MOD P101MOD P102MOD P103MOD P104MOD P105MOD P106MOD P107MOD <When reset : H'00> D Bit Name Function R W

0 P100MOD 0 : P100

(Port P100 operation mode) 1 : TO8

1 P101MOD 0 : P101

(Port P101 operation mode) 1 : TO9

2 P102MOD 0 : P102

(Port P102 operation mode) 1 : TO10

3 P103MOD 0 : P103

(Port P103 operation mode) 1 : TO11

4 P104MOD 0 : P104

(Port P104 operation mode) 1 : TO12

5 P105MOD 0 : P105

(Port P105 operation mode) 1 : TO13

6 P106MOD 0 : P106

(Port P106 operation mode) 1 : TO14

7 P107MOD 0 : P107

(Port P107 operation mode) 1 : TO15

8-17 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P11 Operation Mode Register (P11MOD) <Address: H'0080 074B> D 8 9 1 01 11 21 31 4 D 1 5 P110MOD P111MOD P112MOD P113MOD P114MOD P115MOD P116MOD P117MOD <When reset : H'00> D Bit Name Function R W

8 P110MOD 0 : P110

(Port P110 operation mode) 1 : TO0

9 P111MOD 0 : P111

(Port P111 operation mode) 1 : TO1

10 P112MOD 0 : P112

(Port P112 operation mode) 1 : TO2

11 P113MOD 0 : P113

(Port P113 operation mode) 1 : TO3

12 P114MOD 0 : P114

(Port P114 operation mode) 1 : TO4

13 P115MOD 0 : P115

(Port P115 operation mode) 1 : TO5

14 P116MOD 0 : P116

(Port P116 operation mode) 1 : TO6

15 P117MOD 0 : P117

(Port P117 operation mode) 1 : TO7

8-18 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P12 Operation Mode Register (P12MOD) <Address: H'0080 074C> D 0 123456 D 7 P124MOD P125MOD P126MOD P127MOD <When reset : H'00> D Bit Name Function R W 0 - 3 No functions assigned 0 —

4 P124MOD 0 : P124

(Port P124 operation mode) 1 : TCLK0

5 P125MOD 0 : P125

(Port P125 operation mode) 1 : TCLK1

6 P126MOD 0 : P126

(Port P126 operation mode) 1 : TCLK2

7 P127MOD 0 : P127

(Port P127 operation mode) 1 : TCLK3 Note : Ports P120 - P123 are not accommodated.

8-19 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P13 Operation Mode Register (P13MOD) <Address: H'0080 074D> D 8 9 1 01 11 21 31 4 D 1 5 P130MOD P131MOD P132MOD P133MOD P134MOD P135MOD P136MOD P137MOD <When reset : H'00> D Bit Name Function R W

8 P130MOD 0 : P130

(Port P130 operation mode) 1 : TIN16

9 P131MOD 0 : P131

(Port P131 operation mode) 1 : TIN17

10 P132MOD 0 : P132

(Port P132 operation mode) 1 : TIN18

11 P133MOD 0 : P133

(Port P133 operation mode) 1 : TIN19

12 P134MOD 0 : P134

(Port P134 operation mode) 1 : TIN20

13 P135MOD 0 : P135

(Port P135 operation mode) 1 : TIN21

14 P136MOD 0 : P136

(Port P136 operation mode) 1 : TIN22

15 P137MOD 0 : P137

(Port P137 operation mode) 1 : TIN23

8-20 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P14 Operation Mode Register (P14MOD) <Address: H'0080 074E> D 0 123456 D 7 P140MOD P141MOD P142MOD P143MOD P144MOD P145MOD P146MOD P147MOD <When reset : H'00> D Bit Name Function R W

0 P140MOD 0 : P140

(Port P140 operation mode) 1 : TIN8

1 P141MOD 0 : P141

(Port P141 operation mode) 1 : TIN9

2 P142MOD 0 : P142

(Port P142 operation mode) 1 : TIN10

3 P143MOD 0 : P143

(Port P143 operation mode) 1 : TIN11

4 P144MOD 0 : P144

(Port P144 operation mode) 1 : TIN12

5 P145MOD 0 : P145

(Port P145 operation mode) 1 : TTIN13

6 P146MOD 0 : P146

(Port P146 operation mode) 1 : TIN14

7 P147MOD 0 : P147

(Port P147 operation mode) 1 : TIN15

8-21 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P15 Operation Mode Register (P15MOD) <Address: H'0080 074F> D 8 9 1 01 11 21 31 4 D 1 5 P150MOD P151MOD P152MOD P153MOD P154MOD P155MOD P156MOD P157MOD <When reset : H'00> D Bit Name Function R W

8 P150MOD 0 : P150

(Port P150 operation mode) 1 : TIN0

9 P151MOD 0 : P151

(Port P151 operation mode) 1 : TIN1

10 P152MOD 0 : P152

(Port P152 operation mode) 1 : TIN2

11 P153MOD 0 : P153

(Port P153 operation mode) 1 : TIN3

12 P154MOD 0 : P154

(Port P154 operation mode) 1 : TIN4

13 P155MOD 0 : P155

(Port P155 operation mode) 1 : TIN5

14 P156MOD 0 : P156

(Port P156 operation mode) 1 : TIN6

15 P157MOD 0 : P157

(Port P157 operation mode) 1 : TIN7

8-22 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P16 Operation Mode Register (P16MOD) <Address: H'0080 0750> D 0 123456 D 7 P160MOD P161MOD P162MOD P163MOD P164MOD P165MOD P166MOD P167MOD <When reset : H'00> D Bit Name Function R W

0 P160MOD 0 : P160

(Port P160 operation mode) 1 : TO21

1 P161MOD 0 : P161

(Port P161 operation mode) 1 : TO22

2 P162MOD 0 : P162

(Port P162 operation mode) 1 : TO23

3 P163MOD 0 : P163

(Port P163 operation mode) 1 : TO24

4 P164MOD 0 : P164

(Port P164 operation mode) 1 : TO25

5 P165MOD 0 : P165

(Port P165 operation mode) 1 : TO26

6 P166MOD 0 : P166

(Port P166 operation mode) 1 : TO27

7 P167MOD 0 : P167

(Port P167 operation mode) 1 : TO28

8-23 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P17 Operation Mode Register (P17MOD) <Address: H'0080 0751> D 8 9 1 01 11 21 31 4 D 1 5 P172MOD P173MOD P174MOD P175MOD P176MOD P177MOD <When reset : H'00> D Bit Name Function R W 8, 9 No functions assigned 0 —

10 P172MOD 0 : P172

(Port P172 operation mode) 1 : TIN24

11 P173MOD 0 : P173

(Port P173 operation mode) 1 : TIN25

12 P174MOD 0 : P174

(Port P174 operation mode) 1 : TXD2

13 P175MOD 0 : P175

(Port P175 operation mode) 1 : RXD2

14 P176MOD 0 : P176

(Port P176 operation mode) 1 : TXD3

15 P177MOD 0 : P177

(Port P177 operation mode) 1 : RXD3 Note : Ports P170 and P171 are not accommodated.

8-24 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P18 Operation Mode Register (P18MOD) <Address: H'0080 0752> D 0 123456 D 7 P180MOD P181MOD P182MOD P183MOD P184MOD P185MOD P186MOD P187MOD <When reset : H'00> D Bit Name Function R W

0 P180MOD 0 : P180

(Port P180 operation mode) 1 : TO29

1 P181MOD 0 : P181

(Port P181 operation mode) 1 : TO30

2 P182MOD 0 : P182

(Port P182 operation mode) 1 : TO31

3 P183MOD 0 : P183

(Port P183 operation mode) 1 : TO32

4 P184MOD 0 : P184

(Port P184 operation mode) 1 : TO33

5 P185MOD 0 : P185

(Port P185 operation mode) 1 : TO34

6 P186MOD 0 : P186

(Port P186 operation mode) 1 : TO35

7 P187MOD 0 : P187

(Port P187 operation mode) 1 : TO36

8-25 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P19 Operation Mode Register (P19MOD) <Address: H'0080 0753> D 8 9 1 01 11 21 31 4 D 1 5 P190MOD P191MOD P192MOD P193MOD P194MOD P195MOD P196MOD P197MOD <When reset : H'00> D Bit Name Function R W

8 P190MOD 0 : P190

(Port P190 operation mode) 1 : TIN26

9 P191MOD 0 : P191

(Port P191 operation mode) 1 : TIN27

10 P192MOD 0 : P192

(Port P192 operation mode) 1 : TIN28

11 P193MOD 0 : P193

(Port P193 operation mode) 1 : TIN29

12 P194MOD 0 : P194

(Port P194 operation mode) 1 : TIN30

13 P195MOD 0 : P195

(Port P195 operation mode) 1 : TIN31

14 P196MOD 0 : P196

(Port P196 operation mode) 1 : TIN32

15 P197MOD 0 : P197

(Port P197 operation mode) 1 : TIN33

8-26 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P20 Operation Mode Register (P20MOD) <Address: H'0080 0754> D 0 123456 D 7 P200MOD P201MOD P202MOD P203MOD <When reset : H'00> D Bit Name Function R W

0 P200MOD 0 : P200

(Port P200 operation mode) 1 :TXD4

1 P201MOD 0 : P201

(Port P201 operation mode) 1 : RXD4

2 P202MOD 0 : P202

(Port P202 operation mode) 1 : TXD5

3 P203MOD 0 : P203

(Port P203 operation mode) 1 : RXD5 4 - 7 No functions assigned 0 — Note : Ports P204 - P207 are not accommodated.

8-27 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P21 Operation Mode Register (P21MOD) <Address: H'0080 0755> D 8 9 1 01 11 21 31 4 D 1 5 P210MOD P211MOD P212MOD P213MOD P214MOD P215MOD P216MOD P217MOD <When reset : H'00> D Bit Name Function R W

8 P210MOD 0 : P210

(Port P210 operation mode) 1 : TO37

9 P211MOD 0 : P211

(Port P211 operation mode) 1 : TO38

10 P212MOD 0 : P212

(Port P212 operation mode) 1 : TO39

11 P213MOD 0 : P213

(Port P213 operation mode) 1 : TO40

12 P214MOD 0 : P214

(Port P214 operation mode) 1 : TO41

13 P215MOD 0 : P215

(Port P215 operation mode) 1 : TO42

14 P216MOD 0 : P216

(Port P216 operation mode) 1 : TO43

15 P217MOD 0 : P217

(Port P217 operation mode) 1 : TO44

8-28 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I P22 Operation Mode Register (P22MOD) <Address: H'0080 0756> D 0 123456 D 7 P220MOD P224MOD P225MOD <When reset : H'00> D Bit Name Function R W

0 P220MOD 0 : P220

(Port P220 operation mode) 1 : CTX 1 - 3 No functions assigned 0 —

4 P224MOD 0 : P224

(Port P224 operation mode) 1 : Use inhibited

5 P225MOD 0 : P225

(Port P225 operation mode) 1 : Use inhibited 6 - 7 No functions assigned 0 — Note 1: P221 is a CAN input-only pin. Note 2: P222-P223 are always input/output ports (single-function pins). Note 3: P224 and P225 have their pin functions changed depending on how the MOD0 and MOD1 pins are set. Also, use of these ports requires caution because they have a debug event function. Note 4: P226 and P227 are not accommodated.

8-29 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS I Port Input Function Enable Register (PIEN) <Address: H'0080 0745> D 8 9 1 01 11 21 31 4 D 1 5 PIEN0 <When reset : H'00> D Bit Name Function R W 8 - 14 No functions assigned 0 —

15 PIEN0 0 : Disables input (to prevent current from flowing in)

(Port input function enable bit) 1 : Enables input This register is provided to prevent current from flowing into the port input pin. Because after reset this register is set to disable input, it must be set to 1 before input can be processed. During boot mode, all pins shared with serial I/O function are enabled for input, so that when rewriting the flash memory via serial communication, you can set this register to 0 to prevent current from flowing in from any pins other than serial I/O function. The next page lists the pins that can be controlled by the Port Input Function Enable Register in each mode.

8-30 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS Mode Name Controllable Pins Noncontrollable Pins P00 - P07, P10 - P17, P20 - P27 P64, P221, FP P30 -P37 , P41 - P47, P61 - P63 Single chip P65 - P67, P70 - P77, P82 - P87 P93 - P97, P100 - P107, P110 - P117 P124 - P127, P130 - P137, P140 - P147 P150 - P157, P160 - P167, P172 - P177 P180 - P187, P190 - P197, P200 - P203 P210 - P217, P220, P222 - P225 P61 - P63, P65 - P67, P70 - P77 P00 - P07, P10 - P17 P82 - P87, P93 -P97, P100 - P107 P20 - P27, P30 - P37 Extended external P110 - P117, P124 - P127, P130 - P137 P41 - P47, P64, P221, P224 Microprocessor P140 - P147, P150 - P157, P160 - P167 P225, FP P172 - P177, P180 - P187, P190 - P197 P200 - P203, P210 - P217, P220 P222 - P223 P00 - P07, P10 - P17, P20 - P27 P64, P65, P66, P82 - P87 P30 -P37 , P41 - P47, P61 - P63 P174 - P177, P200 - P203 Boot (single chip) P67, P70 - P77, P93 - P97 P221, FP P100 - P107, P110 - P117, P124 - P127 P130 - P137, P140 - P147, P150 - P157 P160 - P167, P172 - P173, P180 - P187 P190 - P197, P210 - P217, P220 P222 - P225

8-31 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS Figures 8.4.1 through 8.4.4 show the peripheral circuit diagrams of the input/output ports described in the preceding pages. Figure 8.4.1 Port Peripheral Circuit Diagram (1) Note 2: denotes pins. Note 3: indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. Note 4: The input capacitance of each pin is approximately 10 pF. Note 1: Ports P00-P07, P10-P17, P20-P27, P30-P37, P41-P47, and P224-P225 when operating in extended external mode or processor mode, function as external bus interface control signals, but their functional description in this block diagram is omitted. P00 - P07 (DB0-DB7) P10 - P17 (DB8-DB15) P20 - P27 (A23-A30) P30 - P37 (A15-A22) P41 (BLW / BLE) P42 (BHW / BHE) P43 (RD) ___ P44 (CS0) ___ P45 (CS1) P46 - P47 (A13-A14) P61 - P63 P224 - P225 (A11-A12) P222 - P223 P67 (ADTRG) P75 (RTDRXD) P77 (RTDCLK) P83 (RXD0) P86 (RXD1) P124 - P127 (TCLK0-TCLK3) P130 - P137 (TIN16-TIN23) P140 - P147 (TIN8-TIN15) P150 - P157 (TIN0-TIN7) P172, P173 (TIN24, TIN25) P175 (RXD2) P177 (RXD3) P190 - P197 (TIN26-TIN33) P201 (RXD4) P203 (RXD5) Data bus (DB0 - DB15) Operation mode register Port output latch Direction register Input function enable Peripheral function input Data bus (DB0 - DB15) Port output latch Direction register Input function enable

8-32 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS Figure 8.4.2 Port Peripheral Circuit Diagram (2) Note 1: denotes pins. Note 2: indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. Note 3: The input capacitance of each pin is approximately 10 pF. ___ P64 (SBI) P221 / CRX ____ P72 (HREQ) SBI Operation mode register HREQ Data bus (DB0 - DB15) Port output latch Direction register Input function enable Data bus (DB0 - DB15)

8-33 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS Figure 8.4.3 Port Peripheral Circuit Diagram (3) Note 1: denotes pins. Note 2: indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. Note 3: The input capacitance of each pin is approximately 10 pF. ____ P71 (WAIT) P70 (BCLK / WR) ____ P73 (HACK) P74 (RTDTXD) P76 (RTDACK) P82 (TXD0) P85 (TXD1) P93 - P97 (TO16-TO20) P100 - P107 (TO8-TO15) P110 - P117 (TO0-TO7) P160 - P167 (TO21-TO28) P174 (TXD2) P176 (TXD3) P180 - P187 (TO29-TO36) P200 (TXD4) P202 (TXD5) P210 - P217 (TO37-TO44) P220 (CTX) WAIT Data bus (DB0 - DB15) Operation mode register Port output latch Direction register Input function enable Peripheral function input Data bus (DB0 - DB15) Port output latch Direction register Input function enable Operation mode register

8-34 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS Figure 8.4.4 Port Peripheral Circuit Diagram (4) Note 1: denotes pins. Note 2: indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. P84(SCLKI0,SCLKO0) P87(SCLKI1,SCLKO1) P65(SCLKI4,SCLKO4) P66(SCLKI5,SCLKO5) Operation mode register Direction register Port output latch Data bus (DB0 - DB15) SCLKIi input UART/CSIO function select bit Internal/external clock select bit SCLKOi output OSC-VCC VCCI VCCE VDD OSC-VCC, VCCI, VCCE, VDD Input function enable MOD0 MOD1 MOD0, MOD1 FP FP JTDI JTCK JTMS JTDI, JTCK, JTMS JTDO JTDO RESET XIN JTRST RESET, XIN, JTRST

8-35 32170/32174 Group User's Manual (Rev. 2.1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS

• When using the ports in output mode Because the Port Data Register values immediately after a reset are indeterminate, it is necessary that the initial value be written to the Port Data Register before setting the Port Direction Register for output. Conversely, if the Port Direction Register is set for output before writing to the Port Data Register, indeterminate values will be output for a while until the initial value is set in the Port Data Register.

8-36 32170/32174 Group User's Manual (Rev. 2.1) ❊ This is a blank page. ❊ INPUT/OUTPUT PORTS AND PIN FUNCTIONS

9.1 Outline of the DMAC

9.2 DMAC Related Registers

9.3 Functional Description of the

9.4 Precautions about the DMAC

9-2 32170/32174 Group User's Manual (Rev. 2.1) This microcomputer contains a 10 channel-DMA (Direct Memory Access) Controller. It allows you to transfer data at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs, as requested by a software trigger or from an internal peripheral I/O. Table 9.1.1 Outline of the DMAC Item Description Number of channel 10 channels Transfer request • Software trigger

• Request from internal peripheral I/Os: A-D converter,multijunction timer, serial I/O (reception completed, transmit buffer empty)
• Transfer operation can be cascaded between DMA channels (Note) Maximum number 256 times of times transferred Transferable • 64 Kbytes (address space from H'0080 0000 to H'0080 FFFF) address space • Transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, between internal RAMs are supported Transfer data size 16 or 8 bits Transfer method Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual-address transfer Transfer mode Single transfer mode Direction of transfer One of three modes can be selected for the source and destination:
• Address fixed
• Address incremental
• Ring buffered Channel priority Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 >channel 7 > channel 8 > channel 9 (Priority is fixed) Maximum transfer rate13.3 Mbytes per second (with 20 MHz internal peripheral clock) Interrupt request Group interrupt request can be generated when each transfer count register underflows. Transfer area 64 Kbytes from H'0080 0000 to H'0080 FFFF (Transferable in the entire internal RAM/SFR area) Note: Transfer operation can be cascaded between DMA channels as shown below. Completion of one transfer in channel 0 starts DMA transfer in channel 1 Completion of one transfer in channel 1 starts DMA transfer in channel 2 Completion of one transfer in channel 2 starts DMA transfer in channel 0 Completion of one transfer in channel 3 starts DMA transfer in channel 4 Completion of one transfer in channel 5 starts DMA transfer in channel 6 Completion of one transfer in channel 6 starts DMA transfer in channel 7 Completion of one transfer in channel 7 starts DMA transfer in channel 5 Completion of one transfer in channel 8 starts DMA transfer in channel 9 Completion of all DMA transfers in channel 0 (transfer count register underflow) starts DMA transfer in channel 5 DMAC

9-3 32170/32174 Group User's Manual (Rev. 2.1) DMAC Figure 9.1.1 Block Diagram of the DMAC DMA request selector A-D0 conversion completed DMA channel 0 Software start MJT (TIN13 input signal) One DMA0 transfer completed Internal bus Software start Software start Serial I/O0 (reception completed) One DMA2 transfer completed One DMA3 transfer completed MJT (TIO8_udf) MJT (input event bus 2) MJT (output event bus 0) MJT (TIN19 input signal) Software start MJT (TIN18 input signal) One DMA1 transfer completed MJT (output event bus 1) Software start Serial I/O0 (transmit buffer empty) Serial I/O1 (reception completed) Source address register Destination address register Determination block DMA start MJT (TIN0 input signal) All DMA0 transfers completed (udf) Software start MJT (TIN1 input signal) One DMA5 transfer completed Software start One DMA7 transfer completed Serial I/O2 (reception completed) MJT (TIN20 input signal) Serial I/O1 (transmit buffer empty) Software start MJT (TIN2 input signal) One DMA6 transfer completed Serial I/O2 (transmit buffer empty) Software start MJT (input event bus 0) Serial I/O3 (reception completed) MJT (TIN7 input signal) Source Destination Transfer count Interrupt request Internal bus arbitration Software start MJT (TIN8 input signal) One DMA8 transfer completed Serial I/O3 (transmit buffer empty) Transfer count register udf DMA request selector DMA channel 1 udf Source Destination Transfer count DMA request selector DMA channel 2 udf Source Destination Transfer count DMA request selector DMA channel 3 udf Source Destination Transfer count DMA request selector DMA channel 4 udf Source Destination Transfer count DMA request selector DMA channel 5 udf Source Destination Transfer count DMA request selector DMA channel 6 udf Source Destination Transfer count DMA request selector DMA channel 7 udf Source Destination Transfer count DMA request selector DMA channel 8 udf Source Destination Transfer count DMA request selector DMA channel 9 udf Determination block DMA start Internal bus arbitration Interrupt request

9-4 32170/32174 Group User's Manual (Rev. 2.1) DMAC The diagram below shows a memory map of DMAC related registers. Figure 9.2.1 DMAC Related Register Map (1/2) Address D0 D7 +0 Address +1 Address D8 D15 Note: The registers enclosed in thick frames can only be accessed in halfwords. DMA0-4 Interrupt Request Status Register (DM04ITST)H'0080 0400 H'0080 0414 H'0080 0416 H'0080 0418 H'0080 0410 H'0080 0412 H'0080 0422 H'0080 0424 H'0080 0426 H'0080 0428 H'0080 042A H'0080 0420 H'0080 0432 H'0080 0434 H'0080 0436 H'0080 0438 H'0080 043A H'0080 0430 H'0080 0408 H'0080 042C H'0080 042E H'0080 043C H'0080 043E H'0080 041A H'0080 041C H'0080 041E Blank addresses are reserved. DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA0-4 Interrupt Mask Register (DM04ITMK) DMA5-9 Interrupt Request Status Register (DM59ITST) DMA5-9 Interrupt Mask Register (DM59ITMK) DMA0 Channel Control Register (DM0CNT) DMA0 Transfer Count Register (DM0TCT) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA5 Channel Control Register (DM5CNT) DMA5 Transfer Count Register (DM5TCT) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) DMA1 Channel Control Register (DM1CNT) DMA1 Transfer Count Register (DM1TCT) DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) DMA6 Channel Control Register (DM6CNT) DMA6 Transfer Count Register (DM6TCT) DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA2 Channel Control Register (DM2CNT) DMA2 Transfer Count Register (DM2TCT) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) DMA7 Channel Control Register (DM7CNT) DMA7 Transfer Count Register (DM7TCT)

9-5 32170/32174 Group User's Manual (Rev. 2.1) DMAC Figure 9.2.2 DMAC Related Register Map (2/2) Address D0 D7 +0 Address +1 Address D8 D15 Note: The registers enclosed in thick frames can only be accessed in halfwords. H'0080 0440 H'0080 044C H'0080 044E H'0080 0450 H'0080 0448 H'0080 044A H'0080 045A H'0080 045C H'0080 045E H'0080 0460 H'0080 0462 H'0080 0458 H'0080 0470 H'0080 0472 H'0080 0474 H'0080 0476 H'0080 0468 H'0080 0444 H'0080 0464 H'0080 0466 H'0080 0478 H'0080 0452 H'0080 0454 H'0080 0456 Blank addresses are reserved. DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA3 Channel Control Register (DM3CNT) DMA3 Transfer Count Register (DM3TCT) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA8 Channel Control Register (DM8CNT) DMA8 Transfer Count Register (DM8TCT) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA4 Channel Control Register (DM4CNT) DMA4 Transfer Count Register (DM4TCT) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA9 Channel Control Register (DM9CNT) DMA9 Transfer Count Register (DM9TCT) DMA0 Software Request Generation Register (DM0SRI) H'0080 0442 H'0080 0446 DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 Software Request Generation Register (DM4SRI) DMA5 Software Request Generation Register (DM5SRI) DMA6 Software Request Generation Register (DM6SRI) DMA7 Software Request Generation Register (DM7SRI) DMA8 Software Request Generation Register (DM8SRI) DMA9 Software Request Generation Register (DM9SRI)

9-6 32170/32174 Group User's Manual (Rev. 2.1) DMAC

9.2.1 DMA Channel Control Register

I DMA0 Channel Control Register (DM0CNT) <Address: H'0080 0410> D 0 123456 D 7 MDSEL0 TREQF0 REQSL0 TENL0 TSZSL0 SADSL0 DADSL0 <When reset : H'00> D Bit Name Function R W

0 MDSEL0 0 : Normal mode

(Selects DMA0 transfer mode) 1 : Ring buffer mode

1 TREQF0 0 : Not requested

(DMA0 transfer request flag) 1 : Requested 2, 3 REQSL0 00 : Software start or one DMA2 transfer completed (Selects cause of DMA0 request) 01 : A-D0 conversion completed 10 : MJT (TIO8_udf) 11 : MJT (input event bus 2)

4 TENL0 0 : Disables transfer

(Enables DMA0 transfer) 1 : Enables transfer

5 TSZSL0 0 : 16 bits

(Selects DMA0 transfer size) 1 : 8 bits

6 SADSL0 0 : Fixed

(Selects DMA0 source address direction)1 : Incremental

7 DADSL0 0 : Fixed

(Selects DMA0 destination 1 : Incremental address direction) W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

9-7 32170/32174 Group User's Manual (Rev. 2.1) DMAC I DMA1 Channel Control Register (DM1CNT) <Address: H'0080 0420> D 0 123456 D 7 MDSEL1 TREQF1 REQSL1 TENL1 TSZSL1 SADSL1 DADSL1 <When reset : H'00> D Bit Name Function R W

0 MDSEL1 0 : Normal mode

(Selects DMA1 transfer mode) 1 : Ring buffer mode

1 TREQF1 0 : Not requested

(DMA1 transfer request flag) 1 : Requested 2, 3 REQSL1 00 : Software start (Selects cause of DMA1 request) 01 : MJT (output event bus 0) 10 : MJT (TIN13 input signal) 11 : One DMA0 transfer completed

4 TENL1 0 : Disables transfer

(Enables DMA1 transfer) 1 : Enables transfer

5 TSZSL1 0 : 16 bits

(Selects DMA1 transfer size) 1 : 8 bits

6 SADSL1 0 : Fixed

(Selects DMA1 source address direction)1 : Incremental

7 DADSL1 0 : Fixed

(Selects DMA1 destination 1 : Incremental address direction) W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

9-8 32170/32174 Group User's Manual (Rev. 2.1) DMAC I DMA2 Channel Control Register (DM2CNT) <Address: H'0080 0430> D 0 123456 D 7 MDSEL2 TREQF2 REQSL2 TENL2 TSZSL2 SADSL2 DADSL2 <When reset : H'00> D Bit Name Function R W

0 MDSEL2 0 : Normal mode

(Selects DMA2 transfer mode) 1 : Ring buffer mode

1 TREQF2 0 : Not requested

(DMA2 transfer request flag) 1 : Requested 2, 3 REQSL2 00 : Software start (Selects cause of DMA2 request) 01 : MJT (output event bus 1) 10 : MJT (TIN18 input signal) 11 : One DMA1 transfer completed

4 TENL2 0 : Disables transfer

(Enables DMA2 transfer) 1 : Enables transfer

5 TSZSL2 0 : 16 bits

(Selects DMA2 transfer size) 1 : 8 bits

6 SADSL2 0 : Fixed

(Selects DMA2 source address direction)1 : Incremental

7 DADSL2 0 : Fixed

(Selects DMA2 destination 1 : Incremental address direction) W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

9-9 32170/32174 Group User's Manual (Rev. 2.1) DMAC I DMA3 Channel Control Register (DM3CNT) <Address: H'0080 0440> D 0 123456 D 7 MDSEL3 TREQF3 REQSL3 TENL3 TSZSL3 SADSL3 DADSL3 <When reset : H'00> D Bit Name Function R W

0 MDSEL3 0 : Normal mode

(Selects DMA3 transfer mode) 1 : Ring buffer mode

1 TREQF3 0 : Not requested

(DMA3 transfer request flag) 1 : Requested 2, 3 REQSL3 00 : Software start (Selects cause of DMA3 request) 01 : Serial I/O0 (transmit buffer empty) 10 : Serial I/O1 (reception completed) 11 : MJT (TIN0 input signal)

4 TENL3 0 : Disables transfer

(Enables DMA3 transfer) 1 : Enables transfer

5 TSZSL3 0 : 16 bits

(Selects DMA3 transfer size) 1 : 8 bits

6 SADSL3 0 : Fixed

(Selects DMA3 source address direction)1 : Incremental

7 DADSL3 0 : Fixed

(Selects DMA3 destination 1 : Incremental address direction) W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

9-10 32170/32174 Group User's Manual (Rev. 2.1) DMAC I DMA4 Channel Control Register (DM4CNT) <Address: H'0080 0450> D 0 123456 D 7 MDSEL4 TREQF4 REQSL4 TENL4 TSZSL4 SADSL4 DADSL4 <When reset : H'00> D Bit Name Function R W

0 MDSEL4 0 : Normal mode

(Selects DMA4 transfer mode) 1 : Ring buffer mode

1 TREQF4 0 : Not requested

(DMA4 transfer request flag) 1 : Requested 2, 3 REQSL4 00 : Software start (Selects cause of DMA4 request) 01 : One DMA3 transfer completed 10 : Serial I/O0 (reception completed) 11 : MJT (TIN19 input signal)

4 TENL4 0 : Disables transfer

(Enables DMA4 transfer) 1 : Enables transfer

5 TSZSL4 0 : 16 bits

(Selects DMA4 transfer size) 1 : 8 bits

6 SADSL4 0 : Fixed

(Selects DMA4 source address direction)1 : Incremental

7 DADSL4 0 : Fixed

(Selects DMA4 destination 1 : Incremental address direction) W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

9-11 32170/32174 Group User's Manual (Rev. 2.1) DMAC I DMA5 Channel Control Register (DM5CNT) <Address: H'0080 0418> D 0 123456 D 7 MDSEL5 TREQF5 REQSL5 TENL5 TSZSL5 SADSL5 DADSL5 <When reset : H'00> D Bit Name Function R W

0 MDSEL5 0 : Normal mode

(Selects DMA5 transfer mode) 1 : Ring buffer mode

1 TREQF5 0 : Not requested

(DMA5 transfer request flag) 1 : Requested 2, 3 REQSL5 00 : Software start or one DMA7 transfer completed (Selects cause of DMA5 request) 01 : All DMA0 transfers completed 10 : Serial I/O2 (reception completed) 11 : MJT (TIN20 input signal)

4 TENL5 0 : Disables transfer

(Enables DMA5 transfer) 1 : Enables transfer

5 TSZSL5 0 : 16 bits

(Selects DMA5 transfer size) 1 : 8 bits

6 SADSL5 0 : Fixed

(Selects DMA5 source address direction)1 : Incremental

7 DADSL5 0 : Fixed

(Selects DMA5 destination 1 : Incremental address direction) W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

9-12 32170/32174 Group User's Manual (Rev. 2.1) DMAC I DMA6 Channel Control Register (DM6CNT) <Address: H'0080 0428> D 0 123456 D 7 MDSEL6 TREQF6 REQSL6 TENL6 TSZSL6 SADSL6 DADSL6 <When reset : H'00> D Bit Name Function R W

0 MDSEL6 0 : Normal mode

(Selects DMA6 transfer mode) 1 : Ring buffer mode

1 TREQF6 0 : Not requested

(DMA6 transfer request flag) 1 : Requested 2, 3 REQSL6 00 : Software start (Selects cause of DMA6 request) 01 : Serial I/O1 (transmit buffer empty) 10 : MJT (TIN1 input signal) 11 : One DMA5 transfer completed

4 TENL6 0 : Disables transfer

(Enables DMA6 transfer) 1 : Enables transfer

5 TSZSL6 0 : 16 bits

(Selects DMA6 transfer size) 1 : 8 bits

6 SADSL6 0 : Fixed

(Selects DMA6 source address direction)1 : Incremental

7 DADSL6 0 : Fixed

(Selects DMA6 destination 1 : Incremental address direction) W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

9-13 32170/32174 Group User's Manual (Rev. 2.1) DMAC I DMA7 Channel Control Register (DM7CNT) <Address: H'0080 0438> D 0 123456 D 7 MDSEL7 TREQF7 REQSL7 TENL7 TSZSL7 SADSL7 DADSL7 <When reset : H'00> D Bit Name Function R W

0 MDSEL7 0 : Normal mode

(Selects DMA7 transfer mode) 1 : Ring buffer mode

1 TREQF7 0 : Not requested

(DMA7 transfer request flag) 1 : Requested 2, 3 REQSL7 00 : Software start (Selects cause of DMA7 request) 01 : Serial I/O2 (transmit buffer empty) 10 : MJT (TIN2 input signal) 11 : One DMA6 transfer completed

4 TENL7 0 : Disables transfer

(Enables DMA7 transfer) 1 : Enables transfer

5 TSZSL7 0 : 16 bits

(Selects DMA7 transfer size) 1 : 8 bits

6 SADSL7 0 : Fixed

(Selects DMA7 source address direction)1 : Incremental

7 DADSL7 0 : Fixed

(Selects DMA7 destination 1 : Incremental address direction) W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

9-14 32170/32174 Group User's Manual (Rev. 2.1) DMAC I DMA8 Channel Control Register (DM8CNT) <Address: H'0080 0448> D 0 123456 D 7 MDSEL8 TREQF8 REQSL8 TENL8 TSZSL8 SADSL8 DADSL8 <When reset : H'00> D Bit Name Function R W

0 MDSEL8 0 : Normal mode

(Selects DMA8 transfer mode) 1 : Ring buffer mode

1 TREQF8 0 : Not requested

(DMA8 transfer request flag) 1 : Requested 2, 3 REQSL8 00 : Software start (Selects cause of DMA8 request) 01 : MJT (input event bus 0) 10 : Serial I/O3 (reception completed) 11 : MJT (TIN7 input signal)

4 TENL8 0 : Disables transfer

(Enables DMA8 transfer) 1 : Enables transfer

5 TSZSL8 0 : 16 bits

(Selects DMA8 transfer size) 1 : 8 bits

6 SADSL8 0 : Fixed

(Selects DMA8 source address direction)1 : Incremental

7 DADSL8 0 : Fixed

(Selects DMA8 destination 1 : Incremental address direction) W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

9-15 32170/32174 Group User's Manual (Rev. 2.1) DMAC I DMA9 Channel Control Register (DM9CNT) <Address: H'0080 0458> D 0 123456 D 7 MDSEL9 TREQF9 REQSL9 TENL9 TSZSL9 SADSL9 DADSL9 <When reset : H'00> D Bit Name Function R W

0 MDSEL9 0 : Normal mode

(Selects DMA9 transfer mode) 1 : Ring buffer mode

1 TREQF9 0 : Not requested

(DMA9 transfer request flag) 1 : Requested 2, 3 REQSL9 00 : Software start (Selects cause of DMA9 request) 01 : Serial I/O3 (transmit buffer empty) 10 : MJT (TIN8 input signal) 11 : One DMA8 transfer completed

4 TENL9 0 : Disables transfer

(Enables DMA9 transfer) 1 : Enables transfer

5 TSZSL9 0 : 16 bits

(Selects DMA9 transfer size) 1 : 8 bits

6 SADSL9 0 : Fixed

(Selects DMA9 source address direction)1 : Incremental

7 DADSL9 0 : Fixed

(Selects DMA9 destination 1 : Incremental address direction) W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

9-16 32170/32174 Group User's Manual (Rev. 2.1) DMAC The DMA Channel Control Register consists of bits to select DMA transfer mode in each channel, set DMA transfer request flag, and the bits to select the cause of DMA request, enable DMA transfer, and set the transfer size and the source/destination address directions. (1) MDSELn (DMAn transfer mode select) bit (D0) This bit when in single transfer mode selects normal mode or ring buffer mode. Normal mode is selected by setting this bit to 0 or ring buffer mode is selected by setting it to 1. In ring buffer mode, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. In this case, the Transfer Count Register counts in free-run mode during which time transfer operation is continued until the transfer enable bit is reset to 0 (to disable transfer). No interrupt is generated at completion of DMA transfer. (2) TREQFn (DMAn transfer request flag) bit (D1) This flag is set to 1 when a DMA transfer request occurs. Reading this flag helps to know DMA transfer requests in each channel. The generated DMA request is cleared by writing a 0 to this bit. If you write a 1, the value you wrote is ignored and the bit retains its previous value. If a new DMA transfer request is generated for a channel whose DMA transfer request flag has already been set to 1, the next DMA transfer request is not accepted until the transfer under way in that channel is completed. (3) REQSLn (cause of DMAn request select) bits (D2, D3) These bits select the cause of DMA request in each DMA channel. (4) TENLn (DMAn transfer enable) bit (D4) Transfer is enabled by setting this bit to 1, so that the channel is ready for DMA transfer. Conversely, transfer is disabled by setting this bit to 0. However, if a transfer request has already been accepted, transfer in that channel is not disabled until after the requested transfer is completed. (5) TSZSLn (DMAn transfer size select) bit (D5) This bit selects the number of bits to be transferred in one DMA transfer operation (unit of one transfer). The unit of one transfer is 16 bits when TSZSL = 0 or 8 bits when TSZSL = 1. (6) SADSLn (DMAn source address direction select) bit (D6) This bit selects the direction in which the source address changes as transfer proceeds. This mode can be selected from two choices: address fixed or address incremental. (7) DADSLn (DAMn destination address direction select) bit (D7) This bit selects the direction in which the destination address changes as transfer proceeds. This mode can be selected from two choices: address fixed or address incremental.

9-17 32170/32174 Group User's Manual (Rev. 2.1) DMAC

9.2.2 DMA Software Request Generation Registers

I DMA0 Software Request Generation Register (DM0SRI)<Address: H'0080 0460> I DMA1 Software Request Generation Register (DM1SRI)<Address: H'0080 0462> I DMA2 Software Request Generation Register (DM2SRI)<Address: H'0080 0464> I DMA3 Software Request Generation Register (DM3SRI)<Address: H'0080 0466> I DMA4 Software Request Generation Register (DM4SRI)<Address: H'0080 0468> I DMA5 Software Request Generation Register (DM5SRI)<Address: H'0080 0470> I DMA6 Software Request Generation Register (DM6SRI)<Address: H'0080 0472> I DMA7 Software Request Generation Register (DM7SRI)<Address: H'0080 0474> I DMA8 Software Request Generation Register (DM8SRI)<Address: H'0080 0476> I DMA9 Software Request Generation Register (DM9SRI)<Address: H'0080 0478> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 DM0SRI - DM9SRI <When reset : Indeterminate> D Bit Name Function R W 0 - 15 DM0SRI - DM9SRI DMA transfer request is generated ? (Generates DMA software request) by writing any data Note: This register can be accessed in either bytes or halfwords. The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA transfer request can be generated by writing any data to this register when "Software start" has been selected for the cause of DMA request. DM0SRI - DM9SRI (DMA software request generate) bit A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in byte (8 bits) beginning with an even or odd address when "Software" is selected as the cause of DMA transfer request (by setting the DMA Channel Control Register D2, D3 bits to "00").

9-18 32170/32174 Group User's Manual (Rev. 2.1) DMAC

9.2.3 DMA Source Address Registers

I DMA0 Source Address Register (DM0SA) <Address: H'0080 0412> I DMA1 Source Address Register (DM1SA) <Address: H'0080 0422> I DMA2 Source Address Register (DM2SA) <Address: H'0080 0432> I DMA3 Source Address Register (DM3SA) <Address: H'0080 0442> I DMA4 Source Address Register (DM4SA) <Address: H'0080 0452> I DMA5 Source Address Register (DM5SA) <Address: H'0080 041A> I DMA6 Source Address Register (DM6SA) <Address: H'0080 042A> I DMA7 Source Address Register (DM7SA) <Address: H'0080 043A> I DMA8 Source Address Register (DM8SA) <Address: H'0080 044A> I DMA9 Source Address Register (DM9SA) <Address: H'0080 045A> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 DM0SA - DM9SA <When reset : Indeterminate> D Bit Name Function R W 0 - 15 DM0SA - DM9SA A16-A31 of the source address (A0-A15 are fixed to H'0080) Note: This register must always be accessed in halfwords. The DMA Source Address Register is used to set the source address of DMA transfer in such a way that D0 corresponds to A16, and D15 corresponds to A31. Because this register is comprised of a current register, the value you get by reading this register is always the current value. When DMA transfer finishes (at which the Transfer Count Register underflows), the value in this register if "Address fixed" is selected, is the same source address that was set in it before DMA transfer began; if "Address incremental" is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). Make sure the DMA Source Address Register is always accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value read from this register is indeterminate. DM0SA-DM9SA (A16-A31 of the source address) By setting this register, specify the source address of DMA transfer in internal I/O space ranging from H'0080 0000 to H'0080 FFFF or in the RAM space. The 16 high-order bits of the source address (A0-A15) are always fixed to H'0080. Use this register to set the 16 low-order bits of the source address (with D0 corresponding to A16, and D15 corresponding to A31).

9-19 32170/32174 Group User's Manual (Rev. 2.1) DMAC

9.2.4 DMA Destination Address Registers

I DMA0 Destination Address Register (DM0DA) <Address: H'0080 0414> I DMA1 Destination Address Register (DM1DA) <Address: H'0080 0424> I DMA2 Destination Address Register (DM2DA) <Address: H'0080 0434> I DMA3 Destination Address Register (DM3DA) <Address: H'0080 0444> I DMA4 Destination Address Register (DM4DA) <Address: H'0080 0454> I DMA5 Destination Address Register (DM5DA) <Address: H'0080 041C> I DMA6 Destination Address Register (DM6DA) <Address: H'0080 042C> I DMA7 Destination Address Register (DM7DA) <Address: H'0080 043C> I DMA8 Destination Address Register (DM8DA) <Address: H'0080 044C> I DMA9 Destination Address Register (DM9DA) <Address: H'0080 045C> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 DM0DA - DM9DA <When reset : Indeterminate> D Bit Name Function R W 0 - 15 DM0DA - DM9DA A16-A31 of the destination address (A0-A15 are fixed to H'0080) Note: This register must always be accessed in halfwords. The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that D0 corresponds to A16, and D15 corresponds to A31. Because access to this register is comprised of a current register, the value you get by reading this register is always the current value. When DMA transfer finishes (at which the Transfer Count Register underflows), the value in this register if "Address fixed" is selected, is the same destination address that was set in it before DMA transfer began; if "Address incremental" is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). Make sure the DMA Destination Address Register is always accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value read from this register is indeterminate. DM0DA-DM9DA (A16-A31 of the destination address) By setting this register, specify the destination address of DMA transfer in internal I/O space ranging from H'0080 0000 to H'0080 FFFF or in the RAM space. The 16 high-order bits of the destination address (A0-A15) are always fixed to H'0080. Use this register to set the 16 low-order bits of the destination address (with D0 corresponding to A16, and D15 corresponding to A31).

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9.2.5 DMA Transfer Count Registers

I DMA0 Transfer Count Register (DM0TCT) <Address: H'0080 0411> I DMA1 Transfer Count Register (DM1TCT) <Address: H'0080 0421> I DMA2 Transfer Count Register (DM2TCT) <Address: H'0080 0431> I DMA3 Transfer Count Register (DM3TCT) <Address: H'0080 0441> I DMA4 Transfer Count Register (DM4TCT) <Address: H'0080 0451> I DMA5 Transfer Count Register (DM5TCT) <Address: H'0080 0419> I DMA6 Transfer Count Register (DM6TCT) <Address: H'0080 0429> I DMA7 Transfer Count Register (DM7TCT) <Address: H'0080 0439> I DMA8 Transfer Count Register (DM8TCT) <Address: H'0080 0449> I DMA9 Transfer Count Register (DM9TCT) <Address: H'0080 0459> D 8 9 1 01 11 21 31 4 D 1 5 DM0TCT - DM9TCT <When reset : Indeterminate> D Bit Name Function R W 8 - 15 DM0TCT - DM9TCT DMA transfer count (ignored during 32-channel ring buffer mode) The DMA Transfer Count Register is used to set the number of times data is transferred in each channel. However, the value in this register is ignored during ring buffer mode. The transfer count is the (value set in the transfer count register + 1). Because the DMA Transfer Count Register is comprised of a current register, the value you get by reading this register is always the current value. (However, if you read this register in a cycle immediately after transfer, the value you get is the value that was in the count register before the transfer began.) When transfer finishes, this count register underflows, so that the read value you get is H'FF. If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all transfers are completed (at which the transfer count register underflows), transfer in the cascaded channel starts.

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9.2.6 DMA Interrupt Request Status Registers

I DMA0-4 Interrupt Request Status Register (DM04ITST)<Address: H'0080 0410> D 0 123456 D 7 DMITST4 DMITST3 DMITST2 DMITST1 DMITST0 <When reset : H'00> D Bit Name Function R W 0 - 2 No functions assigned 0 —

3 DMITST4 (DMA4 interrupt request status) 0 : No interrupt request

4 DMITST3 (DMA3 interrupt request status) 1 : Interrupt requested

5 DMITST2 (DMA2 interrupt request status)

6 DMITST1 (DMA1 interrupt request status)

7 DMITST0 (DMA0 interrupt request status)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. The DMA0-4 Interrupt Request Status Register lets you know the status of interrupt requests in channels 0-4. If the DMAn interrupt request status bit (n = 0 to 4) is set to 1, it means that a DMAn interrupt request in the corresponding channel has been generated. DMITSTn (DMAn interrupt request status) bit (n = 0 to 4) [Setting the DMAn interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing a 0 in software. Note: The DMAn interrupt request status bit cannot be cleared by writing a 0 to the "Interrupt cause bit" of the DMA Interrupt Control Register that the interrupt controller has. When writing to the DMA0-4 Interrupt Request Status Register, be sure to set the bits you want to clear to 0 and all other bits to 1. The bits which are thus set to 1 are unaffected by writing in software, and retain the value they had before you wrote. DMAC

9-22 32170/32174 Group User's Manual (Rev. 2.1) DMAC I DMA5-9 Interrupt Request Status Register (DM59ITST)<Address: H'0080 0408> D 0 123456 D 7 DMITST9 DMITST8 DMITST7 DMITST6 DMITST5 <When reset : H'00> D Bit Name Function R W 0 - 2 No functions assigned 0 —

3 DMITST9 (DMA9 interrupt request status) 0 : No interrupt request

4 DMITST8 (DMA8 interrupt request status) 1 : Interrupt requested

5 DMITST7 (DMA7 interrupt request status)

6 DMITST6 (DMA6 interrupt request status)

7 DMITST5 (DMA5 interrupt request status)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. The DMA5-9 Interrupt Request Status Register lets you know the status of interrupt requests in channels 5-9. If the DMAn interrupt request status bit (n = 5 to 9) is set to 1, it means that a DMAn interrupt request in the corresponding channel has been generated. DMITSTn (DMAn interrupt request status) bit (n = 5 to 9) [Setting the DMAn interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing a 0 in software. Note: The DMAn interrupt request status bit cannot be cleared by writing a 0 to the "Interrupt cause bit" of the DMA Interrupt Control Register that the interrupt controller has. When writing to the DMA5-9 Interrupt Request Status Register, be sure to set the bits you want to clear to 0 and all other bits to 1. The bits which are thus set to 1 are unaffected by writing in software, and retain the value they had before you wrote.

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9.2.7 DMA Interrupt Mask Registers

I DMA0-4 Interrupt Mask Register (DM04ITMK) <Address: H'0080 0401> D 8 9 1 01 11 21 31 4 D 1 5 DMITMK4 DMITMK3 DMITMK2 DMITMK1 DMITMK0 <When reset : H'00> D Bit Name Function R W 8 - 10 No functions assigned 0 —

11 DMITMK4 (DMA4 interrupt request mask) 0 : Enables interrupt request

12 DMITMK3 (DMA3 interrupt request mask) 1 : Masks (disables) interrupt request

13 DMITMK2 (DMA2 interrupt request mask)

14 DMITMK1 (DMA1 interrupt request mask)

15 DMITMK0 (DMA0 interrupt request mask)

The DMA0-4 Interrupt Mask Register is used to mask interrupt requests in DMA channels 0-4. DMITMKn (DMAn interrupt request mask) bit (n = 0 to 4) DMAn interrupt request is masked by setting the DMAn interrupt request mask bit to 1. However, when an interrupt request is generated, the DMAn interrupt request status bit is always set to 1 irrespective of the contents of this register.

9-24 32170/32174 Group User's Manual (Rev. 2.1) DMAC I DMA5-9 Interrupt Mask Register (DM59ITMK) <Address: H'0080 0409> D 8 9 1 01 11 21 31 4 D 1 5 DMITMK9 DMITMK8 DMITMK7 DMITMK6 DMITMK5 <When reset : H'00> D Bit Name Function R W 8 - 10 No functions assigned 0 —

11 DMITMK9 (DMA9 interrupt request mask) 0 : Enables interrupt request

12 DMITMK8 (DMA8 interrupt request mask) 1 : Masks (disables) interrupt request

13 DMITMK7 (DMA7 interrupt request mask)

14 DMITMK6 (DMA6 interrupt request mask)

15 DMITMK5 (DMA5 interrupt request mask)

The DMA5-9 Interrupt Mask Register is used to mask interrupt requests in DMA channels 5-9. DMITMKn (DMAn interrupt request mask) bit (n = 5 to 9) DMAn interrupt request is masked by setting the DMAn interrupt request mask bit to 1. However, when an interrupt request is generated, the DMAn interrupt request status bit is always set to 1 irrespective of the contents of this register.

9-25 32170/32174 Group User's Manual (Rev. 2.1) DMAC Figure 9.2.3 Block Diagram of DMA Transfer Interrupt 0 DMITST4 F/F DMITMK4 F/Fb11 DMITST3 F/F DMITMK3 F/Fb12 DMITST2 F/F DMITMK2 F/Fb13 DMITST1 F/F DMITMK1 F/Fb14 DMITST0 F/F DMITMK0 F/Fb15 DM04ITST <H'0080 0400> DM04ITMK <H'0080 0401> DMA4UDF DMA3UDF DMA2UDF DMA1UDF DMA0UDF Data bus DMA transfer interrupt 0(Level) 5-source inputs

9-26 32170/32174 Group User's Manual (Rev. 2.1) DMAC Figure 9.2.4 Block Diagram of DMA Transfer Interrupt 1 DMITST9 F/F DMITMK9 F/Fb11 DMITST8 F/F DMITMK8 F/Fb12 DMITST7 F/F DMITMK7 F/Fb13 DMITST6 F/F DMITMK6 F/Fb14 DMITST5 F/F DMITMK5 F/Fb15 DM59ITST <H'0080 0408> DM59ITMK <H'0080 0409> DMA9UDF DMA8UDF DMA7UDF DMA6UDF DMA5UDF Data bus DMA transfer interrupt 1(Level) 5-source inputs

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9.3 Functional Description of the DMAC

9.3.1 Cause of DMA Request

For each DMA channel (channels 0 to 9), DMA transfer can be requested from multiple sources. There are various causes (or sources) of DMA transfer, so that DMA transfer can be started by a request from internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all transfers in a DMA channel (cascade mode). The cause of DMA request is selected using the cause of request select bit provided for each channel, REQSLn (DMAn Channel Control Register bits D2, D3). The table below lists the causes of DMA requests in each channel. Table 9.3.1 Causes of DMA Requests in DMA0 and Generation Timings REQSL0 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA0 Software Request or one DMA2 transfer completed Generation Register (software start) or one DMA2 transfer is completed (cascade mode) 0 1 A-D0 conversion completed When A-D0 conversion is completed 1 0 MJT (TIO8_udf) When MJT TIO8 underflow occurs 1 1 MJT (input event bus 2) When MJT's input event bus 2 signal is generated Table 9.3.2 Causes of DMA Requests in DMA1 and Generation Timings REQSL1 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA1 Software Request Generation Register 0 1 MJT (output event bus 0) When MJT's output event bus 0 signal is generated 1 0 MJT (TIN13 input signal) When MJT's TIN13 input signal is generated 1 1 One DMA0 transfer completed When one DMA0 transfer is completed (cascade mode)

9-28 32170/32174 Group User's Manual (Rev. 2.1) DMAC Table 9.3.3 Causes of DMA Requests in DMA2 and Generation Timings REQSL2 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA2 Software Request Generation Register 0 1 MJT (output event bus 1) When MJT's output event bus 1 signal is generated 1 0 MJT (TIN18 input signal) When MJT's TIN18 input signal is generated 1 1 One DMA1 transfer completed When one DMA1 transfer is completed (cascade mode) Table 9.3.4 Causes of DMA Requests in DMA3 and Generation Timings REQSL3 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA3 Software Request Generation Register 0 1 Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is emptied 1 0 Serial I/O1 (reception completed) When serial I/O1 reception is completed 1 1 MJT (TIN0 input signal) When MJT's TIN0 input signal is generated Table 9.3.5 Causes of DMA Requests in DMA4 and Generation Timings REQSL4 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA4 Software Request Generation Register 0 1 One DMA3 transfer completed When one DMA3 transfer is completed (cascade mode) 1 0 Serial I/O0 (reception completed) When serial I/O0 reception is completed 1 1 MJT (TIN19 input signal) When MJT's TIN19 input signal is generated

9-29 32170/32174 Group User's Manual (Rev. 2.1) DMAC Table 9.3.6 Causes of DMA Requests in DMA5 and Generation Timings REQSL5 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA5 Software Request or one DMA7 transfer completed Generation Register or one DMA7 transfer is completed (cascade mode) 0 1 All DMA0 transfers completed When all DMA0 transfers are completed (cascade mode) 1 0 Serial I/O2 (reception completed) When serial I/O2 reception is completed 1 1 MJT (TIN20 input signal) When MJT's TIN20 input signal is generated Table 9.3.7 Causes of DMA Requests in DMA6 and Generation Timings REQSL6 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA6 Software Request Generation Register 0 1 Serial I/O1 (transmit buffer empty) When serial I/O1 transmit buffer is emptied 1 0 MJT (TIN1 input signal) When MJT's TIN1 input signal is generated 1 1 One DMA5 transfer completed When one DMA5 transfer is completed (cascade mode) Table 9.3.8 Causes of DMA Requests in DMA7 and Generation Timings REQSL7 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA7 Software Request Generation Register 0 1 Serial I/O2 (transmit buffer empty) When serial I/O2 transmit buffer is emptied 1 0 MJT (TIN2 input signal) When MJT's TIN2 input signal is generated 1 1 One DMA6 transfer completed When one DMA6 transfer is completed (cascade mode)

9-30 32170/32174 Group User's Manual (Rev. 2.1) DMAC Table 9.3.9 Causes of DMA Requests in DMA8 and Generation Timings REQSL8 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA8 Software Request Generation Register 0 1 MJT (input event bus 0) When MJT's input event bus 0 signal is generated 1 0 Serial I/O3 (reception completed) When serial I/O3 reception is completed 1 1 MJT (TIN7 input signal) When MJT's TIN7 input signal is generated Table 9.3.10 Causes of DMA Requests in DMA9 and Generation Timings REQSL9 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA9 Software Request Generation Register 0 1 Serial I/O3 (transmit buffer empty) When serial I/O3 transmit buffer is emptied 1 0 MJT (TIN8 input signal) When MJT's TIN8 input signal is generated 1 1 One DMA8 transfer completed When one DMA8 transfer is completed (cascade mode)

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9.3.2 DMA Transfer Processing Procedure

Shown below is an example of how to control DMA transfer in cases when performing transfer in DMA channel 0. Figure 9.3.1 Example of a DMA Transfer Processing Procedure DMA transfer starts as requested by internal peripheral I/O DMA transfer processing starts Transfer count register underflows Interrupt request generated Set DMA0 Channel Control Register Set DMA0-4 Interrupt Request Status Register Set DMA0 Channel Control Register Set DMA0 Source Address Register Set DMA0 Destination Address Register Set DMA0 Count Register Setting DMAC related registers Starting DMA transfer DMA transfer completed

• Transfers disabled
• Clears interrupt request status bit Set DMA0-4 Interrupt Mask Register
• Source address of transfer
• Address
• Number of times DMA transfer performed
• Transfer mode, cause of request, transfer size, address direction, and transfer enable DMA operation completed
• Enables interrupt request Set the interrupt controller's DMA0-4 Interrupt Control Register • Interrupt priority level Setting interrupt controller related registers

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9.3.3 Starting DMA

Use the REQSL (cause of DMA request select) bit to set the cause of DMA request. To enable DMA, set the TENL (DMA transfer enable) bit to 1. DMA transfer begins when the specified cause of DMA request becomes effective after setting the TENL (DMA transfer enable) bit to 1. Note: If the requesting source selected with the REQSL (DMA request source select) bit is MJT (TIN input signal), it takes at least three cycles (e.g., 150 ns when the internal peripheral clock is operating with 20 MHz) before DMA transfer begins after detecting the rising or falling edge or both edges of the TIN input signal. Or, depending on the bus usage condition before or after that, up to six cycles (e.g., 300 ns when the internal peripheral clock is operating with 20 MHz) may be needed. (Note, however, that this applies to the case where external bus, HOLD, and LOCK instruction are unused.) To ensure that changes of the TIN input signal are detected correctly, apply a TIN input signal in pulse width of 7 tc (BCLK)/2 or more. (For details, see Section 21.5, “AC Characteristics.”)

9.3.4 Channel Priority

Channel 0 has the highest priority. The priority of this and other channels is shown below. Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 This order of priority is fixed and cannot be changed. Among channels for which DMA transfers are requested, the channel that has the highest priority is selected. Channel selection is made every transfer cycle (one DMA bus cycle consisting of three machine cycles).

9-33 32170/32174 Group User's Manual (Rev. 2.1) Figure 9.3.2 Gaining and Releasing Control of the Internal Bus One DMA transfer DMAC CPU Internal bus arbitration (control requested by DMAC) Internal bus R: Read W: Write RW RW RW Requested Gained Released Requested Gained Requested Gained Released Released One DMA transfer One DMA transfer

9.3.5 Gaining and Releasing Control of the Internal Bus

For any channel, control of the internal bus is gained and released in "single transfer DMA" mode. In single transfer DMA, the DMA gains control of the internal bus when DMA transfer request is accepted and after executing one DMA transfer (consisting of one read cycle + one write cycle of internal peripheral clock), returns bus control to the CPU. The diagram below shows DMA operation in single transfer DMA.

9.3.6 Transfer Units

Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one DMA transfer.

9.3.7 Transfer Counts

Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be performed up to 256 times. The value of the DMA Transfer Count Register is decremented by one each time one transfer unit is transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-run mode, with the value set in it ignored. DMAC

9-34 32170/32174 Group User's Manual (Rev. 2.1) (4) Address count direction and address changes The direction in which the source and destination addresses are counted as transfer proceeds ("Address fixed" or "Address incremental") is set for each channel using the SADSL (source address direction select) and DADSL (destination address select) bits. When the transfer size is 16 bits, the address is incremented by two for each DMA transfer performed; when the transfer size is 8 bits, the address is incremented by one. Table 9.3.11 Address Count Direction and Address Changes Address Count Direction Transfer Unit Address Change for One DMA Address fixed 8 bits 0 16 bits 0 Address incremental 8 bits +1 16 bits +2 DMAC

9.3.8 Address Space

The address space in which data can be transferred by DMA is the internal peripheral I/O or 64 Kbytes of RAM space (H'0080 0000 through H'0080 FFFF) for either source or destination. To set the source and destination addresses in each channel, use the DMA Source Address Register and DMA Destination Address Register.

9.3.9 Transfer Operation

(1) Dual-address transfer Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and one for destination write access. (The transfer data is temporarily taken into the DMA's internal temporary register.) (2) Bus protocol and bus timing Because the bus interface is shared with the CPU, the same applies to both bus protocol and bus timing as in peripheral module access from the CPU. (3) Transfer rate The maximum transfer rate is calculated using the equation below: Maximum transfer rate [bytes/second] = 2 bytes × 1 / f (BCLK) × 3 cycles

9-35 32170/32174 Group User's Manual (Rev. 2.1) DMAC (5) Transfer count value The transfer count value is decremented by one at a time irrespective of the size of transfer unit (8 or 16 bits). (6) Transfer byte positions When the transfer unit = 8 bits, the LSB of the address register is effective for both source and destination. (Therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address, or from odd address to even address.) When the transfer unit = 8 bits, the LSB of the address register (D15 of the address register) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus. The diagram below shows the valid transfer byte positions. Figure 9.3.3 Transfer Byte Positions D0 D7 D8 D15 8 bits Source Destination <When transfer unit = 8 bits> 16 bits D0 D7 D8 D15 <When transfer unit = 16 bits> 8 bits 8 bits 8 bits 16 bits

9-36 32170/32174 Group User's Manual (Rev. 2.1) DMAC Figure 9.3.4 Example of Address Increment Operation in 32-Channel Ring Buffer Mode (7) Ring buffer mode When ring buffer mode is selected, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. In this case, however, the five low-order bits of the ring buffer start address must always be B'00000. The address increment operation in ring buffer mode is described below. (a) When the transfer unit = 8 bits The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented by one at a time. When as transfer proceeds the five low-order bits reach B'11111, they are recycled to B'00000 by the next increment operation, thus returning to the start address again. (b) When the transfer unit = 16 bits The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented by two at a time. When as transfer proceeds the six low-order bits reach B'111110, they are recycled to B'000000 by the next increment operation, thus returning to the start address again. When the source address has been set to be incremented, it is the source address that recycles to the start address; when the destination address has been set to be incremented, it is the destination address that recycles to the start address. If both source and destination addresses have been set to be incremented, both addresses recycle to the start address. However, the start address on either side must have their five low-order bits initially being B'00000. During ring buffer mode, the transfer count register is ignored. Also, once DMA operation starts, the counter operates in free-run mode, and the transfer continues until the transfer enable bit is cleared to (to disable transfer). <When transfer unit = 8 bits> Transfer count Transfer address

1 H'0080 1000

2 H'0080 1001

3 H'0080 1002

31 H'0080 101E

32 H'0080 101F

<When transfer unit = 16 bits> Transfer count Transfer address

2 H'0080 1002

3 H'0080 1004

31 H'0080 103C

32 H'0080 103E

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9.3.10 End of DMA and Interrupt

In normal mode, DMA transfer is terminated when the transfer count register underflows. When transfer finishes, the transfer enable bit is cleared to 0 and transfers are thereby disabled. Also, an interrupt request is generated at completion of transfer. However, this interrupt is not generated for channels where interrupt requests have been masked by the DMA Interrupt Mask Register. During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the transfer enable bit is cleared to 0 (to disable transfer). In this case, therefore, the DMA transfer-completed interrupt request is not generated. Nor is this interrupt request generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit.

9.3.11 Status of Each Register after Completion of DMA Transfer

When DMA transfer is completed, the status of the source address and destination address registers becomes as follows: (1) Address fixed

• The value set in the address register before DMA transfer started remains intact (fixed). (2) Address incremental
• For 8-bit transfer, the value of the address register is the last transfer address + 1.
• For 16-bit transfer, the value of the address register is the last transfer address + 2. The transfer count register when DMA transfer completed is in an underflow state (H'FF). Therefore, to perform another DMA transfer, set the transfer count register newly again, except when you are performing transfers 256 times (H'FF).

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• About writing to DMAC related registers Because DMA transfer involves exchanging data via the internal bus, basically you only can write to the DMAC related registers immediately after reset or when transfer is disabled (transfer enable bit = 0). When transfer is enabled, do not write to the DMAC related registers because write operation to those registers, except the DMA transfer enable bit, transfer request flag, and the DMA Transfer Count Register which is protected in hardware, is instable. The table below shows the registers that can or cannot be accessed for write. Table 9.4.1 DMAC Related Registers That Can or Cannot Be Accessed for Write Status Transfer enable bit Transfer request flagOther DMAC related registers When transfer is enabled ✕ When transfer is disabled : Can be accessed ; ✕ : Cannot be accessed For even registers that can exceptionally be written to while transfer is enabled, the following requirements must be met. (a) DMA Channel Control Register's transfer enable bit and transfer request flag For all other bits of the channel control register, be sure to write the same data that those bits had before you wrote to the transfer enable bit or transfer request flag. Note that you only can write a 0 to the transfer request flag as valid data. (b) DMA Transfer Count Register When transfer is enabled, this register is protected in hardware, so that any data you write to this register is ignored. (c) Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer In this case, you are writing to the DMAC related registers while DMA is enabled, but this practically does not present any problem. However, you cannot DMA-transfer to the DMAC related registers on the local channel itself in which you are currently operating.

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• Manipulating DMAC related registers by DMA transfer When manipulating DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related registers' initial values by DMA transfer), do not write to the DMAC related registers on the local channel itself through that channel. (If this precaution is neglected, device operation cannot be guaranteed.) Only if residing on other channels, you can write to the DMAC related registers by means of DMA transfer. (For example, you can rewrite the DMAn Source Address and DMAn Destination Address Registers on channel 1 by DMA transfer through channel 0.)
• About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register, be sure to write 1s to all bits but the one you want to clear. The bits to which you wrote 1s retain the previous data they had before the write.
• About the stable operation of DMA transfer To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except the DMA Channel Control Register's transfer enable bit, unless transfer is disabled. One exception is that even when transfer is enabled, you can rewrite the DMA Source Address and DMA Destination Address Registers by DMA transfer from one channel to another.

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• This is a blank page.*

10.1 Outline of Multijunction Timers

10.2 Common Units of Multijunction

10.3 TOP (Output-related 16-bit

Timer)

10.4 TIO (Input/Output-related 16-

bit Timer)

10.5 TMS (Input-related 16-bit Timer)

10.6 TML (Input-related 32-bit Timer)

10.7 TID (Input-related 16-bit Timer)

10.8 TOD (Output-related 16-bit

Timer)

10.9 TOM (Output-related 16-bit

Timer)

10-2 32170/32174 Group User's Manual (Rev. 2.1) The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to being used as a single unit, the timers can be internally connected to each other. This capability allows for highly flexible timer configuration, making it possible to meet various application needs. It is because the timers are connected to the internal event bus at multiple points that they are called the "multijunction" timers. This microcomputer has seven types of multijunction timers as listed in the table below, providing a total of 64 channels of timers. Table 10.1.1 Outline of Multijunction Timers (1/2) Name Type Number of ChannelsDescription TOP Output-related 11 One of three output modes can be selected by software. (Timer Output) 16-bit timer <With correction function> (down-counter) • Single-shot output mode

• Delayed single-shot output mode <Without correction function>
• Continuous output mode TIO Input/output-related 10 One of three input modes or four output modes can be (Timer 16-bit timer selected by software. Input Output) (down-counter) <Input modes>
• Measure clear input mode
• Measure free-run input mode
• Noise processing input mode <Output mode without correction function>
• PWM output mode
• Single-shot output mode
• Delayed single-shot output mode
• Continuous output mode TMS Input-related 8 16-bit input measure timer (Timer 16-bit timer Measure Small) (up-counter) TML Input-related 8 32-bit input measure timer (Timer 32-bit timer Measure Large) (up-counter) MULTIJUNCTION TIMERS

10-3 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Table 10.1.1 Outline of Multijunction Timers (2/2) Name Type Number of Channels Description TID Input-related 3 One of three input modes can be selected by software. (Timer Input 16-bit timer • Fixed period mode Derivation) (up/down-counter) • Event count mode

• Multiply-by-4 event count mode TOD Output-related 16 One of four output modes can be selected by software. (Timer Output 16-bit timer <Without correction function> Derivation) (down-counter) • PWM output mode
• Single-shot output mode
• Delayed single-shot output mode
• Continuous output mode TOM Output-related 8 One of four output modes can be selected by software. (Timer Output 16-bit timer <Without correction function> Modification) (down-counter) • PWM output mode
• Single-shot PWM output mode
• Single-shot output mode
• Continuous output mode Table 10.1.2 MJT Interrupt Generation Functions of the M32170 Signal Name Source of MJT Interrupt RequestedInterrupt Controller (ICU) InputICU Cause Input IRQ18 TIN30 - TIN33 input TML1 input interrupt 4 IRQ17 TID2 output TID2 output interrupt 1 IRQ16 TOD1_0 - TOD1_7 output, TOD1+TOM0 output interrupt 16 TOM0_0 - TOM0_7 output IRQ15 TID1 output TID1 output interrupt 1 IRQ14 TID0 output TID0 output interrupt 1 IRQ13 TOD0_0 - TOD0_7 output TOD0 output interrupt 8 IRQ12 TIN3 - TIN6 input MJT input interrupt 4 4 IRQ11 TIN20 - TIN23 input MJT input interrupt 3 4 IRQ10 TIN12 - TIN19 input MJT input interrupt 2 8 IRQ9 TIN0 - TIN2 input MJT input interrupt 1 3 IRQ8 TIN7 - TIN11 input MJT input interrupt 0 5 IRQ7 TMS0, TMS1 output MJT output interrupt 7 2 IRQ6 TOP8, TOP9 output MJT output interrupt 6 2 IRQ5 TOP10 output MJT output interrupt 5 1 IRQ4 TIO4 - 7 output MJT output interrupt 4 4 IRQ3 TIO8, TIO9 output MJT output interrupt 3 2 IRQ2 TOP0 - 5 output MJT output interrupt 2 6 IRQ1 TOP6, TOP7 output MJT output interrupt 1 2 IRQ0 TIO0 - 3 output MJT output interrupt 0 4

10-4 32170/32174 Group User's Manual (Rev. 2.1) Table 10.1.3 DMA Transfer Request Generation by MJT Signal Name Source of DMA Request Generated DMAC Input Channel DRQ0 TIO8 underflow Channel 0 DRQ1 Input event bus 2 Channel 0 DRQ2 Output event bus 0 Channel 1 DRQ3 TIN13 input Channel 1 DRQ4 Output event bus 1 Channel 2 DRQ5 TIN18 input Channel 2 DRQ6 TIN19 input Channel 4 DRQ7 TIN0 input Channel 3 DRQ8 TIN1 input Channel 6 DRQ9 TIN2 input Channel 7 DRQ10 TIN7 input Channel 8 DRQ11 TIN8 input Channel 9 DRQ12 TIN20 input Channel 5 DRQ13 Input event bus 0 Channel 8 Table 10.1.4 A-D Conversion Start Request by MJT Signal Name Source of A-D Conversion Start RequestedA-D Converter AD0TRG Output event bus 3 Can be input to A-D0 conversion start trigger AD1TRG TID1 overflow/underflow Can be input to A-D1 conversion start trigger MULTIJUNCTION TIMERS

10-5 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.1.1 Block Diagram of MJT (1/4) Note 1: IRQ0-18 denote interrupt signals, of which the same number indicates the same group of interrupts. (See Table denote trigger signals to A-D0 and A-D1 converters, respectively. Note 2: Indicates timer input pin edge selection output. Note 3: Indicates input signals from peripheral circuits (AD and SIO). IRQ2 IRQ12 IRQ12 IRQ12 clk en udfTOP 0 Clock bus Input event bus clk en udfTOP 1 clk en udfTOP 2 clk en udfTOP 3 Output event bus TCLK0S TO 0 IRQ9 1/2 internal peripheral clock IRQ8 clk en udfTOP 4 clk en udfTOP 5 TCLK0 TIN0 TIN7 TCLK1 S STIN0S clk en udfTOP 6 clk en udfTOP 7 S S S IRQ9 TIN1 IRQ9 TIN2 S S clk en udfTOP 8 clk en udfTOP 9 clk en udfTOP 10 clk en/cap udfTIO 0 clk en/cap udfTIO 1 clk en/cap udfTIO 2 clk en/cap udfTIO 3 clk en/cap udfTIO 4 S STIN3 S S TIN4 TIN5 S SIRQ12 TIN6 PRS1 PRS0 clk en/cap udfTIO 5S S IRQ8 TIN8 TCLK2 clk en/cap udfTIO 6S S IRQ8 TIN9 clk en/cap udfTIO 7S S IRQ8 TIN10 S S clk en/cap udfTIO 8 clk en/cap udfTIO 9IRQ8 TIN11 S S F/F0 F/F1 F/F2 F/F3 F/F4 F/F5 F/F6 F/F7 F/F8 F/F9 F/F10 F/F11 F/F12 F/F13 F/F14 F/F15 S F/F16 F/F17 F/F18 F/F19 F/F20 S : SelectorF/F : Output flip-flopPRS0 - 5 : Prescaler S S S S S S S S S S S S S S IRQ2 IRQ2 IRQ2 IRQ2 IRQ2 TO 1 TO 2 TO 3 TO 4 TO 5 TO 6 TO 7 TO 8 TO 9 TO 10 TO 11 TO 12 TO 13 TO 14 TO 15 IRQ1 IRQ1 IRQ6 IRQ6 IRQ5 IRQ0 IRQ0 IRQ0 IRQ0 IRQ4 TO 16 TO 17 TO 18 TO 19 TO 20 IRQ4 DRQ0 IRQ3 IRQ3 PRS2 IRQ4 IRQ4 TIN1S TIN2S TIN3S TIN4S TIN5S TIN6S TCLK1S TCLK2S TIN7S TIN8S TIN9S TIN10S TIN11S DRQ7 DRQ8 DRQ9 DRQ10 DRQ11 AD0TRG (To A-D0 converter) 32 10 32 10 (Note 1) 32 10 32 10 0123 01 23

10-6 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.1.2 Block Diagram of MJT (2/4) clk TMS 0S ovfcap3 cap2 cap1 cap0 S S S S TCLK3 TCLK3S DRQ3 IRQ10 TIN12 TIN13 TIN14 TIN15 clk TMS 1 ovfcap3 cap2 cap1 cap0 S S S S S DRQ5 TIN16 TIN17 TIN18 TIN19 DRQ6 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 clk TML0 cap3 cap2 cap1 cap0 S S S S TIN20 TIN21 TIN22 TIN23 IRQ11 IRQ11 IRQ11 IRQ11 IRQ7 IRQ7 TIN12S TIN13S TIN14S TIN15S TIN16S TIN17S TIN18S TIN19S TIN20S TIN21S TIN22S TIN23S SDRQ12 clk TML1 cap3 cap2 cap1 cap0 S S S S TIN30 TIN31 TIN32 TIN33 TIN30S TIN31S TIN32S TIN33S S IRQ18 IRQ18 IRQ18 IRQ18 S : Selector 32 10 32 10 0 1 2 3 Clock bus Input event bus Output event bus 32 10 32 10 01 23 1/2 internal peripheral clock 1/2 internal peripheral clock

10-7 32170/32174 Group User's Manual (Rev. 2.1) Figure 10.1.3 Block Diagram of MJT (3/4) MULTIJUNCTION TIMERS clk TOD0_0 udf F/F21 clk TOD0_1 udf F/F22 TO21 TO22 clk TOD0_2 udf F/F23 clk TOD0_3 udf F/F24 TO23 TO24 clk TOD0_4 udf F/F25 clk TOD0_5 udf F/F26 TO25 TO26 clk TOD0_6 udf F/F27 clk TOD0_7 udf F/F28 TO27 TO28 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 IRQ13 CLK1 CLK2 PRS3 clk TID1 TIN26 TIN27 IRQ15 clk TOD1_0 udf F/F29 clk TOD1_1 udf F/F30 TO29 TO30 clk TOD1_2 udf F/F31 clk TOD1_3 udf F/F32 TO31 TO32 clk TOD1_4 udf F/F33 clk TOD1_5 udf F/F34 TO33 TO34 clk TOD1_6 udf F/F35 clk TOD1_7 udf F/F36 TO35 TO36 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 CLK1 CLK2 PRS4 clk TID2 TIN28 TIN29 clk TOM0_0 udf F/F37 clk TOM0_1 udf F/F38 TO37 TO38 clk TOM0_2 udf F/F39 clk TOM0_3 udf F/F40 TO39 TO40 clk TOM0_4 udf F/F41 clk TOM0_5 udf F/F42 TO41 TO42 clk TOM0_6 udf F/F43 clk TOM0_7 udf F/F44 TO43 TO44 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 IRQ16 CLK1 CLK2 PRS5 ovf udf ovf udf (Note) IRQ17 en Clock busInput event bus Output event bus 3210 32 10 01 23 1/2 internal peripheral clock 1/2 internal peripheral clock 1/2 internal peripheral clock 32 10 3210 S : Selector 0123 AD1TRG (To A-D1 converter) en en en en en en en en en en en en en en en

10-8 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.1.4 Block Diagram of MJT (4/4) AD0 completed TIO8-udf S DMA0 udf end DMAIRQ0 S DMAIRQ0TIN13 TIN18 S DMAIRQ0 S DMAIRQ0 TIN19 SIO0-TXD SIO1-RXD SIO0-RXD S DMAIRQ1 DMAIRQ1 SIO2-RXD SIO1-TXD DMAIRQ1 DMAIRQ1 SIO2-TXD SIO3-RXD DMAIRQ1SIO3-TXD TIN2 TIN7 TIN8 TIN20 TIN1 TIN0 S DMAIRQ0 S S S S Clock bus Input event bus Output event bus 3210 32 10 32 10 01 23 0123 (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) DMA1 udf end DMA2 udf end DMA3 udf end DMA4 udf (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) DMA5 udf end DMA7 udf end DMA6 udf end (Note 3) (Note 3) DMA8 udf end DMA9 udf 32 10

10-9 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS

10.2 Common Units of Multijunction Timer

The common units of the multijunction timer include the following:

• Prescaler unit
• Clock bus/input-output event bus control unit
• Input processing control unit
• Output flip-flop control unit
• Interrupt control unit

10.2.1 Timer Common Register Map

The diagrams in the next pages show a map of registers in the common units of the multijunction timer.

10-10 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.2.1 Timer Common Register Map (1/2) Address D0 D7 +0 Address +1 AddressD8 D15 Note: The registers included in thick frames must always be accessed in halfwords. H’0080 0200 H’0080 0214 H’0080 0216 H’0080 0218 H’0080 0210 H’0080 0212 H’0080 0224 H’0080 0226 H’0080 0228 H’0080 022A H’0080 0222 H’0080 0236 H’0080 0238 H’0080 023A H’0080 023C H’0080 023E H’0080 0234 H’0080 0204 H’0080 0230 H’0080 0232 H’0080 07D0 H’0080 021A H’0080 0220 Blank addresses are reserved. TIN Input Processing Control Register 0 (TINCR0) TIN Input Processing Control Register 1 (TINCR1) Clock Bus & Input Event Bus Control Register (CKIEBCR) Prescaler Register 2 (PRS2) Output Event Bus Control Register (OEBCR) TIN Input Processing Control Register 4 (TINCR4) F/F Protect Register 0 (FFP0) F/F Data Register 0 (FFD0) F/F Source Select Register 1 (FFS1) F/F Data Register 1 (FFD1) TIO Interrupt Control Register 0 (TIOIR0) TIO Interrupt Control Register 1 (TIOIR1) TOD0 Control Register (TOD0CR) Prescaler Register 0 (PRS0) Prescaler Register 1 (PRS1) TCLK Input Processing Control Register (TCLKCR) H’0080 0202 TIN Input Processing Control Register 2 (TINCR2) TIN Input Processing Control Register 3 (TINCR3) F/F Source Select Register 0 (FFS0) F/F Protect Register 1 (FFP1) TOP Interrupt Control Register 2 (TOPIR2) TOP Interrupt Control Register 3 (TOPIR3) TOP Interrupt Control Register 0 (TOPIR0) TOP Interrupt Control Register 1 (TOPIR1) TIO Interrupt Control Register 2 (TIOIR2) TMS Interrupt Control Register (TMSIR) TIN Interrupt Control Register 0 (TINIR0) TIN Interrupt Control Register 1 (TINIR1) TIN Interrupt Control Register 2 (TINIR2) TIN Interrupt Control Register 3 (TINIR3) TIN Interrupt Control Register 4 (TINIR4) TIN Interrupt Control Register 5 (TINIR5) TIN Interrupt Control Register 6 (TINIR6) TIN Interrupt Control Register 7 (TINIR7) Prescaler Register 3 (PRS3) TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) H’0080 07D2TOD0 Interrupt Mask Register (TOD0IMA) TOD0 Interrupt Status Register (TOD0IST) H’0080 07D4 F/F Protect Register 2 (FFP2) H’0080 07D6 F/F Data Register 2 (FFD2) H’0080 07D8 H’0080 07DA H’0080 07DC TOD0 Enable Protect Register (TOD0PRO) H’0080 07DE TOD0 Count Enable Register (TOD0CEN) TIN Input Processing Control Register 3 (TINCR3)

10-11 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS +0 Address +1 Address D8 D15 Note: The registers included in thick frames must always be accessed in halfwords. H’0080 0BD0 Blank addresses are reserved. Prescaler Register 4 (PRS4) TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) H’0080 0BD2TOD1 Interrupt Mask Register (TOD1IMA) TOD1 Interrupt Status Register (TOD1IST) H’0080 0BD4 F/F Protect Register 3 (FFP3) H’0080 0BD6 F/F Data Register 3 (FFD3) H’0080 0CD0Prescaler Register 5 (PRS5) TID2 Control & Prescaler 5 Enable Register (TID2PRS5EN) H’0080 0CD2TOM0 Interrupt Mask Register (TOM0IMA) TOM0 Interrupt Status Register (TOM0IST) H’0080 0CD4 F/F Protect Register 4 (FFP4) H’0080 0CD6 F/F Data Register 4 (FFD4) Figure 10.2.2 Timer Common Register Map (2/2)

10-12 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS

10.2.2 Prescaler Unit

The prescalers PRS0-5 are an 8-bit counter, which generates clocks supplied to each timer (TOP, TIO, TMS, TML, TID, TOD, and TOM) from the divide-by-2 frequency of the internal peripheral clock (10.0 MHz when the internal peripheral clock = 20 MHz). The values of prescaler registers are initialized to H'00 when reset. Also, when you rewrite the set value of any prescaler register, the device starts operating with the new value simultaneously when the prescaler underflows. Values H'00 to H'FF can be set in the counter registers of prescalers. The prescalers' divide-by ratios are given by the equation below. Prescaler divide-by ratio = ——— —— Prescaler set value + 1 I Prescaler Register 0 (PRS0) <Address: H'0080 0202> I Prescaler Register 1 (PRS1) <Address: H'0080 0203> I Prescaler Register 2 (PRS2) <Address: H'0080 0204> I Prescaler Register 3 (PRS3) <Address: H'0080 07D0> I Prescaler Register 4 (PRS4) <Address: H'0080 0BD0> I Prescaler Register 5 (PRS5) <Address: H'0080 0CD0> D 0 123456 D 7 ( D8 9 10 11 12 13 14 D15 ) PRS0 - PRS5 <When reset : H'00> D Bit Name Function R W 0 - 7 PRS0, 2 - 5 Sets the prescaler's divide-by value 8 - 15 PRS1 Prescaler Registers 0-2 start counting after reset removal. Prescaler Registers 3-5 each are activated by setting the TID0 Control & Prescaler 3 Enable Register, TID1 Control & Prescaler 4 Enable Register, and TID2 Control & Prescaler 5 Enable Register to 1 (= count start), upon which they reload the prescaler register value and start counting. For details, refer to Section 10.7, "TID (Input-related 16-bit Timer)."

10-13 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS

10.2.3 Clock Bus/Input-Output Event Bus Control Unit

(1) Clock bus The clock bus is provided for supplying clock to each timer, and is comprised of four lines of clock bus 0-3. Each timer can use this clock bus signal as clock input signal. The table below lists the signals that can be fed to the clock bus. Table 10.2.1 Signals That Can Be Fed to Each Clock Bus Line Clock Bus Acceptable Signal

3 TCLK0 input

2 Internal prescaler (PRS2) or TCLK3 input

1 Internal prescaler (PRS1)

0 Internal prescaler (PRS0)

(2) Input event bus The input event bus is provided for supplying a count enable signal or measure capture signal to each timer, and is comprised of four lines of input event bus 0-3. Each timer can use this input event bus signal as enable (or capture) signal input. The table below lists the signals that can be fed to the input event bus. Table 10.2.2 Signals That Can Be Fed to Each Input Event Bus Line Input Event Bus Acceptable Signal

3 TIN3 input, output event bus 2 or TIO7 underflow signal

2 TIN0 input, TIN2 input or TIN4 input

1 TIN5 input or TIO6 underflow signal

0 TIN6 input or TIO5 underflow signal

10-14 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (3) Output event bus The output event bus has the underflow signal from each timer connected to it, and is comprised of four lines of output event bus 0-3. Output event bus signals are connected to output flip-flops, and can also be connected to other peripheral circuits-output event bus 3 to A-D0 converter, output event bus 0 to DMA channel 1, and output event bus 1 to DMA channel 2. Furthermore, output event bus 2 can be connected to input event bus 3. The table below lists the signals that can be connected to the output event bus. Table 10.2.3 Signals That Can Be Connected (Fed) to Each Output Event Bus Line Output Event Bus Connectable (Acceptable) Signal (Note)

3 TOP8, TIO3, TIO4, or TIO8 underflow signal

2 TOP9 or TIO2 underflow signal

1 TOP7 or TIO1 underflow signal

0 TOP6 or TIO0 underflow signal

Note: For details about the output destinations of output event bus signals, refer to Figure 10.1.1, "Block Diagram of MJT." Timings at which signals are generated to the output event bus by each timer (and those generated to the input event bus by TIO5, 6) are shown below. (Note that they are generated at different timings than those forwarded to output flip-flops by timers.) Table 10.2.4 Timings at Which Signals Are Generated to the Output Event Bus by Each Timer (1/2) Timer Mode Timings at which signals are generated to the output event bus TOP Single-shot output mode When the counter underflows Delayed single-shot output mode When the counter underflows Continuous output mode When the counter underflows TIO (Note) Measure clear input mode When the counter underflows Measure free-run input mode When the counter underflows Noise processing input mode When the counter underflows PWM output mode When the counter underflows Single-shot output mode When the counter underflows Delayed single-shot output mode When the counter underflows Continuous output mode When the counter underflows TMS (16-bit measure input) No signal generation function TML (32-bit measure input) No signal generation function TID Fixed period mode No signal generation function Event count mode No signal generation function Multiply-by-4 event count mode No signal generation function TOD PWM output mode No signal generation function Single-shot output mode No signal generation function Delayed single-shot output mode No signal generation function Continuous output mode No signal generation function Note: TIO5, 6 output underflow signals to the input event bus.

10-15 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Table 10.2.4 Timings at Which Signals Are Generated to the Output Event Bus by Each Timer (2/2) Timer Mode Timings at which signals are generated to the output event bus TOM PWM output mode No signal generation function Single-shot PWM output mode No signal generation function Single-shot output mode No signal generation function Continuous output mode No signal generation function Figure 10.2.3 Conceptual Diagram of the Clock Bus and Input/Output Event Bus TCLK0STCLK0 TIN0 TIN2 TIN3 TIN4 TIN5 TIN6 PRS1 PRS0 PRS2 TCLK3 udfTIO 5 udfTIO 6 S udfTIO 7 udfTOP 6 udfTOP 7 udfTOP 8 udfTOP 9 udfTIO 0 udfTIO 1 udfTIO 2 udfTIO 3 udfTIO 4 udfTIO 8 TCLK3S TIN0S TIN2S TIN3S TIN4S TIN5S TIN6S Clock bus Input event bus Output event bus S : SelectorPRS0 - 2 : Prescaler 32 10 32 10 32 10 32 10 01 23 01 23 1/2 internal peripheral clock

10-16 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS The clock bus/input-output bus control unit has the following registers:

• Clock Bus & Input Event Bus Control Register (CKIEBCR)
• Output Event Bus Control Register (OEBCR) I Clock Bus & Input Event Bus Control Register (CKIEBCR) <Address: H'0080 0201> D 8 9 1 01 11 21 31 4 D 1 5 IEB3S IEB2S IEB1S IEB0S CKB2S <When reset : H'00> D Bit Name Function R W 8, 9 IEB3S 0X : Selects external input 3 (TIN3) (input event bus 3 input selection) 10 : Selects output event bus 2 11 : Selects TIO7 output 10, 11 IEB2S 00 : Selects external input 0 (TIN0) (input event bus 2 input selection) 01 : Selects external input 2 (TIN2) 1X : Selects external input 4 (TIN4)

12 IEB1S 0 : Selects external input 5 (TIN5)

(input event bus 1 input selection) 1 : Selects TIO6 output

13 IEB0S 0 : Selects external input 6 (TIN6)

(input event bus 0 input selection) 1 : Selects TIO5 output

14 No functions assigned 0 —

15 CKB2S 0 : Selects prescaler 2

(Clock Bus 2 input selection) 1 : Selects external clock 3 (TCLK3) The register CKIEBCR is used to select the clock source (external input or prescaler) supplied to the clock bus and the count enable/capture signal (external input or output event bus) supplied to the input event bus.

10-17 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I Output Event Bus Control Register (OEBCR) <Address: H'0080 0205> D 8 9 1 01 11 21 31 4 D 1 5 OEB3S OEB2S OEB1S OEB0S <When reset : H'00> D Bit Name Function R W 8, 9 OEB3S 00 : Selects TOP8 output (output event bus 3 input selection)01 : Selects TIO3 output 10 : Selects TIO4 output 11 : Selects TIO8 output

10 No functions assigned 0 —

11 OEB2S 0 : Selects TOP9 output

(output event bus 2 input selection)1 : Selects TIO2 output

12 No functions assigned 0 —

13 OEB1S 0 : Selects TOP7 output

(output event bus 1 input selection)1 : Selects TIO1 output

15 OEB0S 0 : Selects TOP6 output

(output event bus 0 input selection)1 : Selects TIO0 output The register OEBCR is used to select the timer (TOP or TIO) whose underflow signal is supplied to the output event bus.

10-18 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS

10.2.4 Input Processing Control Unit

The input processing control unit processes the TCLK and TIN signals fed into the MJT. In the TCLK input processing unit, selection is made of the source of TCLK signal, or for external input, the active edge (rising or falling or both) or level (high or low) of the signal, with or at which to generate the clock signal fed to the clock bus. In the TIN input processing unit, selection is made of the active edge (rising or falling or both) or level (high or low) of the signal at which to generate the enable, measure or count source signal for each timer or the signal fed to each event bus. Following input processing control registers are included:

• TCLK Input Processing Control Register (TCLKCR)
• TIN Input Processing Control Register 0 (TINCR0)
• TIN Input Processing Control Register 1 (TINCR1)
• TIN Input Processing Control Register 2 (TINCR2)
• TIN Input Processing Control Register 3 (TINCR3)
• TIN Input Processing Control Register 4 (TINCR4)

10-19 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (1) Functions of TCLK input processing control registers Item Function 1/2 internal peripheral clock Rising clock edge Falling clock edge Both edges Low level High level Count clock 1/2 internal peripheral clock TCLK Count clock TCLK Count clock TCLK Count clock TCLK Count clock 1/2 internal peripheral clock TCLK Count clock 1/2 internal peripheral clock

10-20 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (2) Functions of TIN input processing control registers Item Function Rising edge Falling edge Both edges Low level High level TIN Internal edge signal TIN Internal edge signal TIN Internal edge signal TIN Internal edge signal PRS × clock width or TCLK × input TIN Internal edge signal PRS × clock width or TCLK × input

10-21 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TCLK3S TCLK2S TCLK1S TCLK0S <When reset : H'0000> D Bit Name Function R W 0, 1 No functions assigned 0 — 2, 3 TCLK3S 00 : 1/2 internal peripheral clock (TCLK3 input 01 : Rising edge processing selection) 10 : Falling edge 11 : Both edges

4 No functions assigned 0 —

5 - 7 TCLK2S 000 : Invalidates input (TCLK2 input 001 : Rising edge processing selection) 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level

8 No functions assigned 0 —

9 - 11 TCLK1S 000 : Invalidates input (TCLK1 input 001 : Rising edge processing selection) 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 12, 13 No functions assigned 0 — 14, 15 TCLK0S 00 : 1/2 internal peripheral clock (TCLK0 input 01 : Rising edge processing selection) 10 : Falling edge 11 : Both edges Note: This register must always be accessed in halfwords. I TLCK Input Processing Control Register (TCLKCR) <Address: H'0080 0210>

10-22 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TIN4S TIN3S TIN2S TIN1S TIN0S <When reset : H'0000> D Bit Name Function R W

0 No functions assigned 0 —

1 - 3 TIN4S 000 : Invalidates input (TIN4 input 001 : Rising edge processing selection) 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 5 - 7 TIN3S 000 : Invalidates input (TIN3 input 001 : Rising edge processing selection) 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 8, 9 No functions assigned 0 — 10, 11 TIN2S 00 : Invalidates input (TIN2 input 01 : Rising edge processing selection) 10 : Falling edge 11 : Both edges 12, 13 TIN1S 00 : Invalidates input (TIN1 input 01 : Rising edge processing selection) 10 : Falling edge 11 : Both edges 14, 15 TIN0S 00 : Invalidates input (TIN0 input 01 : Rising edge processing selection) 10 : Falling edge 11 : Both edges Note: This register must always be accessed in halfwords. I TIN Input Processing Control Register 0 (TINCR0) <Address: H'0080 0212>

10-23 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TIN8S TIN7S TIN6S TIN5S <When reset : H'0000> D Bit Name Function R W 1 - 3 TIN8S 000 : Invalidates input (TIN8 input 001 : Rising edge processing selection) 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 5 - 7 TIN7S 000 : Invalidates input (TIN7 input 001 : Rising edge processing selection) 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 9 - 11 TIN6S 000 : Invalidates input (TIN6 input 001 : Rising edge processing selection) 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 13 - 15 TIN5S 000 : Invalidates input (TIN5 input 001 : Rising edge processing selection) 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level Note: This register must always be accessed in halfwords. I TIN Input Processing Control Register 1 (TINCR1) <Address: H'0080 0214>

10-24 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TIN11S TIN10S TIN9S <When reset : H'0000> D Bit Name Function R W 0 - 4 No functions assigned 0 — 5 - 7 TIN11S 000 : Invalidates input (TIN11 input 001 : Rising edge processing selection) 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 9 - 11 TIN10S 000 : Invalidates input (TIN10 input 001 : Rising edge processing selection) 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level 13 - 15 TIN9S 000 : Invalidates input (TIN9 input 001 : Rising edge processing selection) 010 : Falling edge 011 : Both edges 10X : Low level 11X : High level Note: This register must always be accessed in halfwords. I TIN Input Processing Control Register 2 (TINCR2) <Address: H'0080 0216>

10-25 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TIN19S TIN18S TIN17S TIN16S TIN15S TIN14S TIN13S TIN12S <When reset : H'0000> D Bit Name Function R W 0, 1 TIN19S (TIN19 input processing selection) 00 : Invalidates input 2, 3 TIN18S (TIN18 input processing selection) 01 : Rising edge 4, 5 TIN17S (TIN17 input processing selection) 10 : Falling edge 6, 7 TIN16S (TIN16 input processing selection) 11 : Both edges 8, 9 TIN15S (TIN15 input processing selection) 10, 11 TIN14S (TIN14 input processing selection) 12, 13 TIN13S (TIN13 input processing selection) 14, 15 TIN12S (TIN12 input processing selection) Note: This register must always be accessed in halfwords. I TIN Input Processing Control Register 4 (TINCR4) <Address: H'0080 021A> I TIN Input Processing Control Register 3 (TINCR3) <Address: H'0080 0218> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TIN33S TIN32S TIN31S TIN30S TIN23S TIN22S TIN21S TIN20S <When reset : H'0000> D Bit Name Function R W 0, 1 TIN33S (TIN33 input processing selection) 00 : Invalidates input 2, 3 TIN32S (TIN32 input processing selection) 01 : Rising edge 4, 5 TIN31S (TIN31 input processing selection) 10 : Falling edge 6, 7 TIN30S (TIN30 input processing selection) 11 : Both edges 8, 9 TIN23S (TIN23 input processing selection) 10, 11 TIN22S (TIN22 input processing selection) 12, 13 TIN21S (TIN21 input processing selection) 14, 15 TIN20S (TIN20 input processing selection) Note: This register must always be accessed in halfwords.

10-26 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS

10.2.5 Output Flip-Flop Control Unit

The output flip-flop control unit controls the flip-flop (F/F) provided for each timer output. Following flip-flop control registers are included:

• F/F Source Select Register 0 (FFS0)
• F/F Source Select Register 1 (FFS1)
• F/F Protect Register 0 (FFP0)
• F/F Protect Register 1 (FFP1)
• F/F Protect Register 2 (FFP2)
• F/F Protect Register 3 (FFP3)
• F/F Protect Register 4 (FFP4)
• F/F Data Register 0 (FFD0)
• F/F Data Register 1 (FFD1)
• F/F Data Register 2 (FFD2)
• F/F Data Register 3 (FFD3)
• F/F Data Register 4 (FFD4) Timings at which signals are generated to the output flip-flop by each timer are shown in Table 10.2.5 below. (Note that signals are generated at different timings than those fed to the output event bus.)

10-27 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Table 10.2.5 Timings at Which Signals Are Generated to the Output Flip-Flop by Each Timer Timer Mode Timings at which signals are generated to the output flip-flop TOP Single-shot output mode When counter is enabled and when underflows Delayed single-shot output mode When counter underflows Continuous output mode When counter is enabled and when underflows TIO Measure clear input mode When counter underflows Measure free-run input mode When counter underflows Noise processing input mode When counter underflows PWM output mode When counter is enabled and when underflows Single-shot output mode When counter is enabled and when underflows Delayed single-shot output mode When counter underflows Continuous output mode When counter is enabled and when underflows TMS (16-bit measure input) No signal generation function TML (32-bit measure input) No signal generation function TID Fixed period count mode No signal generation function Event count mode No signal generation function Multiply-by-4 event count mode No signal generation function TOD PWM output mode When counter is enabled and when underflows Single-shot output mode When counter is enabled and when underflows Delayed single-shot output mode When counter underflows Continuous output mode When counter is enabled and when underflows TOM PWM output mode When counter is enabled and when underflows Single-shot PWM output mode When counter underflows Single-shot output mode When counter is enabled and when underflows Continuous output mode When counter is enabled and when underflows

10-28 32170/32174 Group User's Manual (Rev. 2.1) Figure 10.2.4 Configuration of the F/F Output Circuit MULTIJUNCTION TIMERS F/F protect (FPn) WR Dn Output control (ON/OFF) TOn Internal edge signal Port operation mode register(PnMOD) F/Fn output data (FDn) TOP TIO TOD TOM udf F/F source selection (FFn) Output event bus 1 Output event bus 2 Output event bus 3 Note: Dn denotes the data bus. F/F F/F F/F

10-29 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 FF15 FF14 FF13 FF12 FF11 FF10 FF9 FF8 FF7 FF6 <When reset : H'0000> D Bit Name Function R W 0 - 2 No functions assigned 0 —

3 FF15 (F/F15 source selection) 0 : TIO4 output

1 : Output event bus 0

4 FF14 (F/F14 source selection) 0 : TIO3 output

1 : Output event bus 0

5 FF13 (F/F13 source selection) 0 : TIO2 output

1 : Output event bus 3

6 FF12 (F/F12 source selection) 0 : TIO1 output

1 : Output event bus 2

7 FF11 (F/F11 source selection) 0 : TIO0 output

1 : Output event bus 1 8, 9 FF10 (F/F10 source selection) 0X : TOP10 output 10 : Output event bus 0 11 : Output event bus 1 10, 11 FF9 (F/F9 source selection) 0X : TOP9 output 10 : Output event bus 0 11 : Output event bus 1 12, 13 FF8 (F/F8 source selection) 00 : TOP8 output 01 : Output event bus 0 10 : Output event bus 1 11 : Output event bus 2

14 FF7 (F/F7 source selection) 0 : TOP7 output

1 : Output event bus 0

15 FF6 (F/F6 source selection) 0 : TOP6 output

1 : Output event bus 1 Note: This register must always be accessed in halfwords. I F/F Source Select Register 0 (FFS0) <Address: H'0080 0220>

10-30 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I F/F Source Select Register 1 (FFS1) <Address: H'0080 0223> D 8 9 1 01 11 21 31 4 D 1 5 FF19 FF18 FF17 FF16 <When reset : H'00> D Bit Name Function R W 8, 9 FF19 (F/F19 source selection) 0X : TIO8 output 10 : Output event bus 0 11 : Output event bus 1 10, 11 FF18 (F/F18 source selection) 0X : TIO7 output 10 : Output event bus 0 11 : Output event bus 1 12, 13 FF17 (F/F17 source selection) 0X : TIO6 output 10 : Output event bus 0 11 : Output event bus 1 14, 15 FF16 (F/F16 source selection) 00 : TIO5 output 01 : Output event bus 0 10 : Output event bus 1 11 : Output event bus 3 The registers FFS0 and FFS1 are used to select the signal sources fed to each output F/F (flip- flop). For these signal sources, you can choose signals from the internal output bus or underflow output from each timer.

10-31 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 FP15 FP14 FP13 FP12 FP11 FP10 FP9 FP8 FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 <When reset : H'0000> D Bit Name Function R W

0 FP15 (F/F15 protect) 0 : Enables write to F/F output bit

1 FP14 (F/F14 protect) 1 : Disables write to F/F output bit

2 FP13 (F/F13 protect)

3 FP12 (F/F12 protect)

4 FP11 (F/F11 protect)

5 FP10 (F/F10 protect)

6 FP9 (F/F9 protect)

7 FP8 (F/F8 protect)

8 FP7 (F/F7 protect)

9 FP6 (F/F6 protect)

10 FP5 (F/F5 protect)

11 FP4 (F/F4 protect)

12 FP3 (F/F3 protect)

13 FP2 (F/F2 protect)

14 FP1 (F/F1 protect)

15 FP0 (F/F0 protect)

Note: This register must always be accessed in halfwords. This register controls write to each output F/F (flip-flop) by enabling or disabling it. When this register is set to disable write to any output F/F, writing to the F/F Data Register has no effect. I F/F Protect Register 0 (FFP0) <Address: H'0080 0224>

10-32 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 8 9 1 01 11 21 31 4 D 1 5 FP20 FP19 FP18 FP17 FP16 <When reset : H'00> D Bit Name Function R W 8 - 10 No functions assigned 0 —

11 FP20 (F/F20 protect) 0 : Enables write to F/F output bit

12 FP19 (F/F19 protect) 1 : Disables write to F/F output bit

13 FP18 (F/F18 protect)

14 FP17 (F/F17 protect)

15 FP16 (F/F16 protect)

I F/F Protect Register 2 (FFP2) <Address: H'0080 07D5> I F/F Protect Register 1 (FFP1) <Address: H'0080 0229> D 8 9 1 01 11 21 31 4 D 1 5 FP21 FP22 FP23 FP24 FP25 FP26 FP27 FP28 <When reset : H'00> D Bit Name Function R W

8 FP21 (F/F21 protect) 0 : Enables write to F/F output bit

9 FP22 (F/F22 protect) 1 : Disables write to F/F output bit

10 FP23 (F/F23 protect)

11 FP24 (F/F24 protect)

12 FP25 (F/F25 protect)

13 FP26 (F/F26 protect)

14 FP27 (F/F27 protect)

15 FP28 (F/F28 protect)

This register controls write to each output F/F (flip-flop) by enabling or disabling it. When this register is set to disable write to any output F/F, writing to the F/F Data Register has no effect.

10-33 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 8 9 1 01 11 21 31 4 D 1 5 FP29 FP30 FP31 FP32 FP33 FP34 FP35 FP36 <When reset : H'00> D Bit Name Function R W

8 FP29 (F/F29 protect) 0 : Enables write to F/F output bit

9 FP30 (F/F30 protect) 1 : Disables write to F/F output bit

10 FP31 (F/F31 protect)

11 FP32 (F/F32 protect)

12 FP33 (F/F33 protect)

13 FP34 (F/F34 protect)

14 FP35 (F/F35 protect)

15 FP36 (F/F36 protect)

I F/F Protect Register 4 (FFP4) <Address: H'0080 0CD5> I F/F Protect Register 3 (FFP3) <Address: H'0080 0BD5> D 8 9 1 01 11 21 31 4 D 1 5 FP37 FP38 FP39 FP40 FP41 FP42 FP43 FP44 <When reset : H'00> D Bit Name Function R W

8 FP37 (F/F37 protect) 0 : Enables write to F/F output bit

9 FP38 (F/F38 protect) 1 : Disables write to F/F output bit

10 FP39 (F/F39 protect)

11 FP40 (F/F40 protect)

12 FP41 (F/F41 protect)

13 FP42 (F/F42 protect)

14 FP43 (F/F43 protect)

15 FP44 (F/F44 protect)

This register controls write to each output F/F (flip-flop) by enabling or disabling it. When this register is set to disable write to any output F/F, writing to the F/F Data Register has no effect.

10-34 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 FD15 FD14 FD13 FD12 FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 <When reset : H'0000> D Bit Name Function R W

0 FD15 (F/F15 output data) 0 : F/F output data = 0

1 FD14 (F/F14 output data) 1 : F/F output data = 1

2 FD13 (F/F13 output data)

3 FD12 (F/F12 output data)

4 FD11 (F/F11 output data)

5 FD10 (F/F10 output data)

6 FD9 (F/F9 output data)

7 FD8 (F/F8 output data)

8 FD7 (F/F7 output data)

9 FD6 (F/F6 output data)

10 FD5 (F/F5 output data)

11 FD4 (F/F4 output data)

12 FD3 (F/F3 output data)

13 FD2 (F/F2 output data)

14 FD1 (F/F1 output data)

15 FD0 (F/F0 output data)

Note: This register must always be accessed in halfwords. This register is used to set data in each output F/F (flip-flop). Normally, the data output from F/F changes with timer output, but by setting data 0 or 1 in this register you can produce the desired output from any F/F. The F/F Data Register can only be accessed for write when the F/F Protect Register described above is enabled for write. I F/F Data Register 0 (FFD0) <Address: H'0080 0226>

10-35 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 8 9 1 01 11 21 31 4 D 1 5 FD20 FD19 FD18 FD17 FD16 <When reset : H'00> D Bit Name Function R W 8 - 10 No functions assigned 0 —

11 FD20 (F/F20 output data) 0 : F/F output data = 0

12 FD19 (F/F19 output data) 1 : F/F output data = 1

13 FD18 (F/F18 output data)

14 FD17 (F/F17 output data)

15 FD16 (F/F16 output data)

I F/F Data Register 2 (FFD2) <Address: H'0080 07D7> I F/F Data Register 1 (FFD1) <Address: H'0080 022B> D 8 9 1 01 11 21 31 4 D 1 5 FD21 FD22 FD23 FD24 FD25 FD26 FD27 FD28 <When reset : H'00> D Bit Name Function R W

8 FD21 (F/F21 output data) 0 : F/F output data = 0

9 FD22 (F/F22 output data) 1 : F/F output data = 1

10 FD23 (F/F23 output data)

11 FD24 (F/F24 output data)

12 FD25 (F/F25 output data)

13 FD26 (F/F26 output data)

14 FD27 (F/F27 output data)

15 FD28 (F/F28 output data)

This register is used to set data in each output F/F (flip-flop). Normally, the data output from F/F changes with timer output, but by setting data 0 or 1 in this register you can produce the desired output from any F/F. The F/F Data Register can only be accessed for write when the F/F Protect Register described above is enabled for write.

10-36 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 8 9 1 01 11 21 31 4 D 1 5 FD29 FD30 FD31 FD32 FD33 FD34 FD35 FD36 <When reset : H'00> D Bit Name Function R W

8 FD29 (F/F29 output data) 0 : F/F output data = 0

9 FD30 (F/F30 output data) 1 : F/F output data = 1

10 FD31 (F/F31 output data)

11 FD32 (F/F32 output data)

12 FD33 (F/F33 output data)

13 FD34 (F/F34 output data)

14 FD35 (F/F35 output data)

15 FD36 (F/F36 output data)

I F/F Data Register 4 (FFD4) <Address: H'0080 0CD7> I F/F Data Register 3 (FFD3) <Address: H'0080 0BD7> D 8 9 1 01 11 21 31 4 D 1 5 FD37 FD38 FD39 FD40 FD41 FD42 FD43 FD44 <When reset : H'00> D Bit Name Function R W

8 FD37 (F/F37 output data) 0 : F/F output data = 0

9 FD38 (F/F38 output data) 1 : F/F output data = 1

10 FD39 (F/F39 output data)

11 FD40 (F/F40 output data)

12 FD41 (F/F41 output data)

13 FD42 (F/F42 output data)

14 FD43 (F/F43 output data)

15 FD44 (F/F44 output data)

This register is used to set data in each output F/F (flip-flop). Normally, the data output from F/F changes with timer output, but by setting data 0 or 1 in this register you can produce the desired output from any F/F. The F/F Data Register can only be accessed for write when the F/F Protect Register described above is enabled for write.

10-37 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS

10.2.6 Interrupt Control Unit

The interrupt control unit controls the interrupt signals sent to the interrupt controller by each timer. Following 22 timer interrupt control registers are provided for each timer.

• TOP Interrupt Control Register 0 (TOPIR0)
• TOP Interrupt Control Register 1 (TOPIR1)
• TOP Interrupt Control Register 2 (TOPIR2)
• TOP Interrupt Control Register 3 (TOPIR3)
• TIO Interrupt Control Register 0 (TIOIR0)
• TIO Interrupt Control Register 1 (TIOIR1)
• TIO Interrupt Control Register 2 (TIOIR2)
• TMS Interrupt Control Register (TMSIR)
• TIN Interrupt Control Register 0 (TINIR0)
• TIN Interrupt Control Register 1 (TINIR1)
• TIN Interrupt Control Register 2 (TINIR2)
• TIN Interrupt Control Register 3 (TINIR3)
• TIN Interrupt Control Register 4 (TINIR4)
• TIN Interrupt Control Register 5 (TINIR5)
• TIN Interrupt Control Register 6 (TINIR6)
• TIN Interrupt Control Register 7 (TINIR7)
• TOD0 Interrupt Mask Register (TOD0IMA)
• TOD0 Interrupt Status Register (TOD0IST)
• TOD1 Interrupt Mask Register (TOD1IMA)
• TOD1 Interrupt Status Register (TOD1IST)
• TOM0 Interrupt Mask Register (TOM0IMA)
• TOM0 Interrupt Status Register (TOM0IST) For interrupts which have only one source of interrupt in one interrupt table, no interrupt control registers are provided in the timer, and the interrupt status flags are automatically managed within the interrupt controller. For details, refer to Chapter 14, "Interrupt Controller."
• TOP10 MJT Output Interrupt 5 (IRQ5)
• TID0 TID0 Output Interrupt (IRQ14)
• TID1 TID1 Output Interrupt (IRQ15)
• TID2 TID2 Output Interrupt (IRQ17)

10-38 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS For interrupts which have two or more sources of interrupt in one interrupt table, interrupt control registers are provided, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in the interrupt controller function only as a bit to show whether an interrupt-enabled interrupt request occurred and cannot be written to. (1) Interrupt request status bit This status bit shows whether an interrupt request occurred. When an interrupt request is generated, this bit is set in hardware (but cannot be set in software). The status bit is cleared by writing a 0, but not affected by writing a 1, in which case the bit holds the status intact. Because the status bit is unaffected by interrupt mask bits, it can also be used to check the operation of peripheral function. In interrupt processing, make sure that among grouped interrupt flags, only the flag for the serviced interrupt is cleared. Clearing flags for unserviced interrupts results in the pending interrupt requests also being cleared. (2) Interrupt mask bit This bit is used to disable unnecessary interrupts among grouped interrupt requests. Set this bit to 0 to enable interrupts or 1 to disable interrupts. Figure 10.2.5 Interrupt Status Register and Mask Register Interrupt controller Each timer or TIN input interrupt request Interrupt status Data bus Set Group interrupt Interrupt enable clear F/F F/F Data = 0

10-39 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.2.6 Example for Clearing the Interrupt Status b4 5 6 b7 Interrupt status flag Initial state b6 event occurred Interrupt request b4 event occurred Only b6 cleared b4 data retained b4 5 6 b7 1101 Write to the interrupt status Example for clearing the interrupt status 000 0 001 0 011 0 010 0

10-40 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS The table below shows the relationship between the interrupt signals generated by multijunction timers and the interrupt sources input to the interrupt controller. Table 10.2.6 Interrupt Signals Generated by MJT Signal Name Source of Interrupt Generated Interrupt Sources Input to ICU (Note 1) Number of Input Sources IRQ0 TIO0, TIO1, TIO2, TIO3 MJT output interrupt 0 4 IRQ1 TOP6, TOP7 MJT output interrupt 1 2 IRQ2 TOP0, TOP1, TOP2, TOP3, TOP4, TOP5 MJT output interrupt 2 6 IRQ3 TIO8, TIO9 MJT output interrupt 3 2 IRQ4 TIO4, TIO5, TIO6, TIO7 MJT output interrupt 4 4 IRQ6 TOP8, TOP9 MJT output interrupt 6 2 IRQ7 TMS0, TMS1 MJT output interrupt 7 2 IRQ8 TIN7, TIN8, TIN9, TIN10, TIN11 MJT input interrupt 0 5 IRQ9 TIN0, TIN1, TIN2 MJT input interrupt 1 3 IRQ10 TIN12, TIN13, TIN14, TIN15, TIN16, MJT input interrupt 2 8 TIN17, TIN18, TIN19 IRQ11 TIN20, TIN21, TIN22, TIN23 MJT input interrupt 3 4 IRQ12 TIN3, TIN4, TIN5, TIN6 MJT input interrupt 4 4 IRQ13 TOD0_0, TOD0_1, TOD0_2, TOD0_3, TOD0 output interrupt 8 TOD0_4, TOD0_5, TOD0_6, TOD0_7 IRQ16 TOD1_0, TOD1_1, TOD1_2, TOD1_3, TOD1 + TOM0 output interrupt 16 TOD1_4, TOD1_5, TOD1_6, TOD1_7, TOM0_0, TOM0_1, TOM0_2, TOM0_3, TOM0_4, TOM0_5, TOM0_6, TOM0_7 IRQ18 TIN30, TIN31, TIN32, TIN33 TML1 input interrupt 4 Note 1: Refer to Chapter 5, "Interrupt Controller (ICU)." Note 2: For TOP10 and TID0-2, there are no interrupt status and mask bits in MJT interrupt control registers because they only have one source of interrupt in the group. (They are controlled directly by the interrupt controller.)

10-41 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS TOPIS5 TOPIS4 TOPIS3 TOPIS2 TOPIS1 TOPIS0 <When reset : H'00> D Bit Name Function R W 0, 1 No functions assigned 0 —

2 TOPIS5 (TOP5 interrupt status) 0 : No interrupt request

3 TOPIS4 (TOP4 interrupt status) 1 : Interrupt request generated

4 TOPIS3 (TOP3 interrupt status)

5 TOPIS2 (TOP2 interrupt status)

6 TOPIS1 (TOP1 interrupt status)

7 TOPIS0 (TOP0 interrupt status)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. I TOP Interrupt Control Register 1 (TOPIR1) <Address: H'0080 0231> I TOP Interrupt Control Register 0 (TOPIR0) <Address: H'0080 0230> D 8 9 1 01 11 21 31 4 D 1 5 TOPIM5 TOPIM4 TOPIM3 TOPIM2 TOPIM1 TOPIM0 <When reset : H'00> D Bit Name Function R W 8, 9 No functions assigned 0 —

10 TOPIM5 (TOP5 interrupt mask) 0 : Enables interrupt request

11 TOPIM4 (TOP4 interrupt mask) 1 : Masks (disables) interrupt request

12 TOPIM3 (TOP3 interrupt mask)

13 TOPIM2 (TOP2 interrupt mask)

14 TOPIM1 (TOP1 interrupt mask)

15 TOPIM0 (TOP0 interrupt mask)

10-42 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.2.7 Block Diagram of MJT Output Interrupt 2 MJT output interrupt 2 IRQ2 Data bus TOPIS5 F/F TOPIM5 F/Fb10 TOPIS4 F/F TOPIM4 F/Fb11 TOPIS3 F/F TOPIM3 F/Fb12 TOPIS2 F/F TOPIM2 F/Fb13 TOPIS1 F/F TOPIM1 F/Fb14 TOPIS0 F/F TOPIM0 F/Fb15 (Level) 6-source inputs TOPIR0 <H'0080 0230> TOPIR1 <H'0080 0231> TOP5udf TOP4udf TOP3udf TOP2udf TOP1udf TOP0udf

10-43 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS TOPIS7 TOPIS6 TOPIM7 TOPIM6 <When reset : H'00> D Bit Name Function R W 0, 1 No functions assigned 0 —

2 TOPIS7 (TOP7 interrupt status) 0 : No interrupt request

3 TOPIS6 (TOP6 interrupt status) 1 : Interrupt request generated

4, 5 No functions assigned 0 —

6 TOPIM7 (TOP7 interrupt mask) 0 : Enables interrupt request

7 TOPIM6 (TOP6 interrupt mask) 1 : Masks (disables) interrupt request

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. I TOP Interrupt Control Register 2 (TOPIR2) <Address: H'0080 0232> Figure 10.2.8 Block Diagram of MJT Output Interrupt 1 TOPIS7 F/F TOPIM7 F/Fb6 TOPIS6 F/F TOPIM6 F/Fb7 TOPIR2 <H'0080 0232> TOP7udf TOP6udf Data bus MJT output interrupt 1 IRQ1(Level) 2-source inputs

10-44 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 8 9 1 01 11 21 31 4 D 1 5 TOPIS9 TOPIS8 TOPIM9 TOPIM8 <When reset : H'00> D Bit Name Function R W 8, 9 No functions assigned 0 —

10 TOPIS9 (TOP9 interrupt status) 0 : No interrupt request

11 TOPIS8 (TOP8 interrupt status) 1 : Interrupt request generated

12, 13 No functions assigned 0 —

14 TOPIM9 (TOP9 interrupt mask) 0 : Enables interrupt request

15 TOPIM8 (TOP8 interrupt mask) 1 : Masks (disables) interrupt request

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. Note: For TOP10, there are no interrupt status and mask bits in MJT interrupt control registers because it only has one source of interrupt in the group. (It is controlled directly by the interrupt controller.) I TOP Interrupt Control Register 3 (TOPIR3) <Address: H'0080 0233> Figure 10.2.9 Block Diagram of MJT Output Interrupt 6 b10 TOPIS9 F/F TOPIM9 F/Fb14 b11 TOPIS8 F/F TOPIM8 F/Fb15 TOPIR3 <H'0080 0233> TOP9udf TOP8udf Data bus MJT output interrupt 6 IRQ6(Level) 2-source inputs

10-45 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS TIOIS3 TIOIS2 TIOIS1 TIOIS0 TIOIM3 TIOIM2 TIOIM1 TIOIM0 <When reset : H'00> D Bit Name Function R W

0 TIOIS3 (TIO3 interrupt status) 0 : No interrupt request

1 TIOIS2 (TIO2 interrupt status) 1 : Interrupt request generated

2 TIOIS1 (TIO1 interrupt status)

3 TIOIS0 (TIO0 interrupt status)

4 TIOIM3 (TIO3 interrupt mask) 0 : Enables interrupt request

5 TIOIM2 (TIO2 interrupt mask) 1 : Masks (disables) interrupt request

6 TIOIM1 (TIO1 interrupt mask)

7 TIOIM0 (TIO0 interrupt mask)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. I TIO Interrupt Control Register 0 (TIOIR0) <Address: H'0080 0234> Figure 10.2.10 Block Diagram of MJT Output Interrupt 0 TIOIS3 F/F TIOIM3 F/Fb4 TIOIS2 F/F TIOIM2 F/Fb5 TIOIS1 F/F TIOIM1 F/Fb6 TIOIS0 F/F TIOIM0 F/Fb7 TIOIR0 <H'0080 0234> TIO3udf TIO2udf TIO1udf TIO0udf Data bus MJT output interrupt 0 IRQ0(Level) 4-source inputs

10-46 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 8 9 1 01 11 21 31 4 D 1 5 TIOIS7 TIOIS6 TIOIS5 TIOIS4 TIOIM7 TIOIM6 TIOIM5 TIOIM4 <When reset : H'00> D Bit Name Function R W

8 TIOIS7 (TIO7 interrupt status) 0 : No interrupt request

9 TIOIS6 (TIO6 interrupt status) 1 : Interrupt request generated

10 TIOIS5 (TIO5 interrupt status)

11 TIOIS4 (TIO4 interrupt status)

12 TIOIM7 (TIO7 interrupt mask) 0 : Enables interrupt request

13 TIOIM6 (TIO6 interrupt mask) 1 : Masks (disables) interrupt request

14 TIOIM5 (TIO5 interrupt mask)

15 TIOIM4 (TIO4 interrupt mask)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. I TIO Interrupt Control Register 1 (TIOIR1) <Address: H'0080 0235> Figure 10.2.11 Block Diagram of MJT Output Interrupt 4 TIOIS7 F/F TIOIM7 F/Fb12 TIOIS6 F/F TIOIM6 F/Fb13 b10 TIOIS5 F/F TIOIM5 F/Fb14 b11 TIOIS4 F/F TIOIM4 F/Fb15 TIOIR1 <H’0080 0235> TIO7udf TIO6udf TIO5udf TIO4udf Data bus MJT output interrupt 4 IRQ4(Level) 4-source inputs

10-47 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS TIOIS9 TIOIS8 TIOIM9 TIOIM8 <When reset : H'00> D Bit Name Function R W 0, 1 No functions assigned 0 —

2 TIOIS9 (TIO9 interrupt status) 0 : No interrupt request

3 TIOIS8 (TIO8 interrupt status) 1 : Interrupt request generated

4, 5 No functions assigned 0 —

6 TIOIM9 (TIO9 interrupt mask) 0 : Enables interrupt request

7 TIOIM8 (TIO8 interrupt mask) 1 : Masks (disables) interrupt request

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. I TIO Interrupt Control Register 2 (TIOIR2) <Address: H'0080 0236> Figure 10.2.12 Block Diagram of MJT Output Interrupt 3 TIOIS9 F/F TIOIM9 F/Fb6 TIOIS8 F/F TIOIM8 F/Fb7 TIOIR2 <H'0080 0236> TIO9udf TIO8udf Data bus MJT output interrupt 3 IRQ3(Level) 2-source inputs

10-48 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 8 9 1 01 11 21 31 4 D 1 5 TMSIS1 TMSIS0 TMSIM1 TMSIM0 <When reset : H'00> D Bit Name Function R W 8, 9 No functions assigned 0 —

10 TMSIS1 (TMS1 interrupt status) 0 : No interrupt request

11 TMSIS0 (TMS0 interrupt status) 1 : Interrupt request generated

12, 13 No functions assigned 0 —

14 TMSIM1 (TMS1 interrupt mask) 0 : Enables interrupt request

15 TMSIM0 (TMS0 interrupt mask) 1 : Masks (disables) interrupt request

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. I TMS Interrupt Control Register (TMSIR) <Address: H'0080 0237> Figure 10.2.13 Block Diagram of MJT Output Interrupt 7 b10 TMSIS1 F/F TMSIM1 F/Fb14 b11 TMSIS0 F/F TMSIM0 F/Fb15 TMSIR <H'0080 0237> TMS1ovf TMS0ovf Data bus MJT output interrupt 7 IRQ7(Level) 2-source inputs

10-49 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS TINIS2 TINIS1 TINIS0 TINIM2 TINIM1 TINIM0 <When reset : H'00> D Bit Name Function R W

1 TINIS2 (TIN2 interrupt status) 0 : No interrupt request

2 TINIS1 (TIN1 interrupt status) 1 : Interrupt request generated

3 TINIS0 (TIN0 interrupt status)

5 TINIM2 (TIN2 interrupt mask) 0 : Enables interrupt request

6 TINIM1 (TIN1 interrupt mask) 1 : Masks (disables) interrupt request

7 TINIM0 (TIN0 interrupt mask)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. I TIN Interrupt Control Register 0 (TINIR0) <Address: H'0080 0238> Figure 10.2.14 Block Diagram of MJT Input Interrupt 1 TINIS2 F/F TINIM2 F/Fb5 TINIS1 F/F TINIM1 F/Fb6 TINIS0 F/F TINIM0 F/Fb7 TINIR0 <H'0080 0238> TIN2edge TIN1edge TIN0edge Data bus MJT input interrupt 1 IRQ9(Level) 3-source inputs

10-50 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 8 9 1 01 11 21 31 4 D 1 5 TINIS6 TINIS5 TINIS4 TINIS3 TINIM6 TINIM5 TINIM4 TINIM3 <When reset : H'00> D Bit Name Function R W

8 TINIS6 (TIN6 interrupt status) 0 : No interrupt request

9 TINIS5 (TIN5 interrupt status) 1 : Interrupt request generated

10 TINIS4 (TIN4 interrupt status)

11 TINIS3 (TIN3 interrupt status)

12 TINIM6 (TIN6 interrupt mask) 0 : Enables interrupt request

13 TINIM5 (TIN5 interrupt mask) 1 : Masks (disables) interrupt request

14 TINIM4 (TIN4 interrupt mask)

15 TINIM3 (TIN3 interrupt mask)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. I TIN Interrupt Control Register 1 (TINIR1) <Address: H'0080 0239> Figure 10.2.15 Block Diagram of MJT Input Interrupt 4 TINIS6 F/F TINIM6 F/Fb12 TINIS5 F/F TINIM5 F/Fb13 b10 TINIS4 F/F TINIM4 F/Fb14 TINIR1 <H'0080 0239> TIN6edge TIN5edge TIN4edge b11 TINIS3 F/F TINIM3 F/Fb15 TIN3edge Data bus MJT input interrupt 4 IRQ2(Level) 4-source inputs

10-51 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS TINIS11 TINIS10 TINIS9 TINIS8 TINIS7 <When reset : H'00> D Bit Name Function R W 0,1,2 No functions assigned 0 —

3 TINIS11 (TIN11 interrupt status) 0 : No interrupt request

4 TINIS10 (TIN10 interrupt status) 1 : Interrupt request generated

5 TINIS9 (TIN9 interrupt status)

6 TINIS8 (TIN8 interrupt status)

7 TINIS7 (TIN7 interrupt status)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. I TIN Interrupt Control Register 3 (TINIR3) <Address: H'0080 023B> I TIN Interrupt Control Register 2 (TINIR2) <Address: H'0080 023A> D 8 9 1 01 11 21 31 4 D 1 5 TINIM11 TINIM10 TINIM9 TINIM8 TINIM7 <When reset : H'00> D Bit Name Function R W 8,9,10 No functions assigned 0 —

11 TINIM11 (TIN11 interrupt mask) 0 : Enables interrupt request

12 TINIM10 (TIN10 interrupt mask) 1 : Masks (disables) interrupt request

13 TINIM9 (TIN9 interrupt mask)

14 TINIM8 (TIN8 interrupt mask)

15 TINIM7 (TIN7 interrupt mask)

10-52 32170/32174 Group User's Manual (Rev. 2.1) Figure 10.2.16 Block Diagram of MJT Input Interrupt 0 MULTIJUNCTION TIMERS TINIR2 <H’0080 023A> TINIR3 <H’0080 023B> TIN11edge TIN10edge TIN9edge TIN8edge TIN7edge Data bus MJT input interrupt 0 IRQ8(Level) 5-source inputs

10-53 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS TINIS19 TINIS18 TINIS17 TINIS16 TINIS15 TINIS14 TINIS13 TINIS12 <When reset : H'00> D Bit Name Function R W

0 TINIS19 (TIN19 interrupt status) 0 : No interrupt request

1 TINIS18 (TIN18 interrupt status) 1 : Interrupt request generated

2 TINIS17 (TIN17 interrupt status)

3 TINIS16 (TIN16 interrupt status)

4 TINIS15 (TIN15 interrupt status)

5 TINIS14 (TIN14 interrupt status)

6 TINIS13 (TIN13 interrupt status)

7 TINIS12 (TIN12 interrupt status)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. I TIN Interrupt Control Register 5 (TINIR5) <Address: H'0080 023D> I TIN Interrupt Control Register 4 (TINIR4) <Address: H'0080 023C> D 8 9 1 01 11 21 31 4 D 1 5 TINIM19 TINIM18 TINIM17 TINIM16 TINIM15 TINIM14 TINIM13 TINIM12 <When reset : H'00> D Bit Name Function R W

8 TINIM19 (TIN19 interrupt mask) 0 : Enables interrupt request

9 TINIM18 (TIN18 interrupt mask) 1 : Masks (disables) interrupt request

10 TINIM17 (TIN17 interrupt mask)

11 TINIM16 (TIN16 interrupt mask)

12 TINIM15 (TIN15 interrupt mask)

13 TINIM14 (TIN14 interrupt mask)

14 TINIM13 (TIN13 interrupt mask)

15 TINIM12 (TIN12 interrupt mask)

10-54 32170/32174 Group User's Manual (Rev. 2.1) Figure 10.2.17 Block Diagram of MJT Input Interrupt 2 MULTIJUNCTION TIMERS TINIR4 <H'0080 023C> TINIR5 <H'0080 023D> TIN19edge TIN18edge TIN17edge TIN16edge TIN15edge TINIS14 F/F TINIM14 F/Fb13 TINIS13 F/F TINIM13 F/Fb14 TINIS12 F/F TINIM12 F/Fb15 TIN14edge TIN13edge TIN12edge Data bus MJT input interrupt 2 IRQ10(Level) 8-source inputs

10-55 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS TINIS23 TINIS22 TINIS21 TINIS20 TINIM23 TINIM22 TINIM21 TINIM20 <When reset : H'00> D Bit Name Function R W

0 TINIS23 (TIN23 interrupt status) 0 : No interrupt request

1 TINIS22 (TIN22 interrupt status) 1 : Interrupt request generated

2 TINIS21 (TIN21 interrupt status)

3 TINIS20 (TIN20 interrupt status)

4 TINIM23 (TIN23 interrupt mask) 0 : Enables interrupt request

5 TINIM22 (TIN22 interrupt mask) 1 : Masks (disables) interrupt request

6 TINIM21 (TIN21 interrupt mask)

7 TINIM20 (TIN20 interrupt mask)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. Figure 10.2.18 Block Diagram of MJT Input Interrupt 3 I TIN Interrupt Control Register 6 (TINIR6) <Address: H'0080 023E> TINIS23 F/F TINIM23 F/Fb4 TINIS22 F/F TINIM22 F/Fb5 TINIS21 F/F TINIM21 F/Fb6 TINIS20 F/F TINIM20 F/Fb7 TINIR6 <H'0080 023E> TIN23edge TIN22edge TIN21edge TIN20edge Data bus MJT input interrupt 3 IRQ11(Level) 4-source inputs

10-56 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 8 9 1 01 11 21 31 4 D 1 5 TINIS33 TINIS32 TINIS31 TINIS30 TINIM33 TINIM32 TINIM31 TINIM30 <When reset : H'00> D Bit Name Function R W

8 TINIS33 (TIN33 interrupt status) 0 : No interrupt request

9 TINIS32 (TIN32 interrupt status) 1 : Interrupt request generated

10 TINIS31 (TIN31 interrupt status)

11 TINIS30 (TIN30 interrupt status)

12 TINIM33 (TIN33 interrupt mask) 0 : Enables interrupt request

13 TINIM32 (TIN32 interrupt mask) 1 : Masks (disables) interrupt request

14 TINIM31 (TIN31 interrupt mask)

15 TINIM30 (TIN30 interrupt mask)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. Note : For TIN24-TIN29, there are no interrupt status and mask bits in MJT interrupt control registers because they do not have interrupt functions. I TIN Interrupt Control Register 7 (TINIR7) <Address: H'0080 023F> Figure 10.2.19 Block Diagram of TML1 Input Interrupt TINIS33 F/F TINIM33 F/Fb12 TINIS32 F/F TINIM32 F/Fb13 b10 TINIS31 F/F TINIM31 F/Fb14 b11 TINIS30 F/F TINIM30 F/Fb15 TINIR7 <H'0080 023F> TIN33edge TIN32edge TIN31edge TIN30edge Data bus TML1 input interrupt IRQ18(Level) 4-source inputs

10-57 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS TOD07IMA TOD06IMA TOD05IMA TOD04IMA TOD03IMA TOD02IMA TOD01IMA TOD00IMA <When reset : H'00> D Bit Name Function R W

0 TOD07IMA (TOD0_7 interrupt mask) 0 : Enables interrupt request

1 TOD06IMA (TOD0_6 interrupt mask) 1 : Masks (disables) interrupt request

2 TOD05IMA (TOD0_5 interrupt mask)

3 TOD04IMA (TOD0_4 interrupt mask)

4 TOD03IMA (TOD0_3 interrupt mask)

5 TOD02IMA (TOD0_2 interrupt mask)

6 TOD01IMA (TOD0_1 interrupt mask)

7 TOD00IMA (TOD0_0 interrupt mask)

I TOD0 Interrupt Status Register (TOD0IST) <Address: H'0080 07D3> I TOD0 Interrupt Mask Register (TOD0IMA) <Address: H'0080 07D2> D 8 9 1 01 11 21 31 4 D 1 5 TOD07IST TOD06IST TOD05IST TOD04IST TOD03IST TOD02IST TOD01IST TOD00IST <When reset : H'00> D Bit Name Function R W

8 TOD07IST (TOD0_7 interrupt status) 0 : No interrupt request

9 TOD06IST (TOD0_6 interrupt status) 1 : Interrupt request generated

10 TOD05IST (TOD0_5 interrupt status)

11 TOD04IST (TOD0_4 interrupt status)

12 TOD03IST (TOD0_3 interrupt status)

13 TOD02IST (TOD0_2 interrupt status)

14 TOD01IST (TOD0_1 interrupt status)

15 TOD00IST (TOD0_0 interrupt status)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

10-58 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.2.20 Block Diagram of TOD0 Output Interrupt TOD07IST F/F TOD07IMA F/Fb0 TOD06IST F/F TOD06IMA F/Fb1 b10 TOD05IST F/F TOD05IMA F/Fb2 b11 TOD04IST F/F TOD04IMA F/Fb3 b12 TOD03IST F/F TOD03IMA F/Fb4 TOD0IMA <H'0080 07D2> TOD0IST <H'0080 07D3> TOD07udf TOD06udf TOD05udf TOD04udf TOD03udf b13 TOD02IST F/F TOD02IMA F/Fb5 b14 TOD01IST F/F TOD01IMA F/Fb6 b15 TOD00IST F/F TOD00IMA F/Fb7 TOD02udf TOD01udf TOD00udf Data bus TOD0 output interrupt 2 IRQ13(Level) 8-source inputs

10-59 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS TOD17IMA TOD16IMA TOD15IMA TOD14IMA TOD13IMA TOD12IMA TOD11IMA TOD10IMA <When reset : H'00> D Bit Name Function R W

0 TOD17IMA (TOD1_7 interrupt mask) 0 : Enables interrupt request

1 TOD16IMA (TOD1_6 interrupt mask) 1 : Masks (disables) interrupt request

2 TOD15IMA (TOD1_5 interrupt mask)

3 TOD14IMA (TOD1_4 interrupt mask)

4 TOD13IMA (TOD1_3 interrupt mask)

5 TOD12IMA (TOD1_2 interrupt mask)

6 TOD11IMA (TOD1_1 interrupt mask)

7 TOD10IMA (TOD1_0 interrupt mask)

I TOD1 Interrupt Status Register (TOD1IST) <Address: H'0080 0BD3> I TOD1 Interrupt Mask Register (TOD1IMA) <Address: H'0080 0BD2> D 8 9 1 01 11 21 31 4 D 1 5 TOD17IST TOD16IST TOD15IST TOD14IST TOD13IST TOD12IST TOD11IST TOD10IST <When reset : H'00> D Bit Name Function R W

8 TOD17IST (TOD1_7 interrupt status) 0 : No interrupt request

9 TOD16IST (TOD1_6 interrupt status) 1 : Interrupt request generated

10 TOD15IST (TOD1_5 interrupt status)

11 TOD14IST (TOD1_4 interrupt status)

12 TOD13IST (TOD1_3 interrupt status)

13 TOD12IST (TOD1_2 interrupt status)

14 TOD11IST (TOD1_1 interrupt status)

15 TOD10IST (TOD1_0 interrupt status)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

10-60 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS TOM07IMA TOM06IMA TOM05IMA TOM04IMA TOM03IMA TOM02IMA TOM01IMA TOM00IMA <When reset : H'00> D Bit Name Function R W

0 TOM07IMA (TOM0_7 interrupt mask) 0 : Enables interrupt request

1 TOM06IMA (TOM0_6 interrupt mask) 1 : Masks (disables) interrupt request

2 TOM05IMA (TOM0_5 interrupt mask)

3 TOM04IMA (TOM0_4 interrupt mask)

4 TOM03IMA (TOM0_3 interrupt mask)

5 TOM02IMA (TOM0_2 interrupt mask)

6 TOM01IMA (TOM0_1 interrupt mask)

7 TOM00IMA (TOM0_0 interrupt mask)

I TOM0 Interrupt Status Register (TOM0IST) <Address: H'0080 0CD3> I TOM0 Interrupt Mask Register (TOM0IMA) <Address: H'0080 0CD2> D 8 9 1 01 11 21 31 4 D 1 5 TOM07IST TOM06IST TOM05IST TOM04IST TOM03IST TOM02IST TOM01IST TOM00IST <When reset : H'00> D Bit Name Function R W

8 TOM07IST (TOM0_7 interrupt status) 0 : No interrupt request

9 TOM06IST (TOM0_6 interrupt status) 1 : Interrupt request generated

10 TOM05IST (TOM0_5 interrupt status)

11 TOM04IST (TOM0_4 interrupt status)

12 TOM03IST (TOM0_3 interrupt status)

13 TOM02IST (TOM0_2 interrupt status)

14 TOM01IST (TOM0_1 interrupt status)

15 TOM00IST (TOM0_0 interrupt status)

W = : Only writing a 0 is effective; when you write a 1, the previous value is retained.

10-61 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.2.21 Block Diagram of TOD1 + TOM0 Output Interrupt (1/2) TOD17IST F/F TOD17IMA F/Fb0 TOD16IST F/F TOD16IMA F/Fb1 b10 TOD15IST F/F TOD15IMA F/Fb2 b11 TOD14IST F/F TOD14IMA F/Fb3 b12 TOD13IST F/F TOD13IMA F/Fb4 TOD1IMA <H'0080 0BD2> TOD1IST <H'0080 0BD3> TOD17udf TOD16udf TOD15udf TOD14udf TOD13udf b13 TOD12IST F/F TOD12IMA F/Fb5 b14 TOD11IST F/F TOD11IMA F/Fb6 b15 TOD10IST F/F To 8 input sources in the next page F/Fb7 TOD12udf TOD11udf TOD10udf TOD10IMA Data bus TOD1 + TOM0 output interrupt IRQ16(Level) 16-source inputs

10-62 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.2.22 Block Diagram of TOD1 + TOM0 Output Interrupt (2/2) TOM07IST F/F TOM07IMA F/Fb0 TOM06IST F/F TOM06IMA F/Fb1 b10 TOM05IST F/F TOM05IMA F/Fb2 b11 TOM04IST F/F TOM04IMA F/Fb3 b12 TOM03IST F/F TOM03IMA F/F TOM0IMA <H'0080 0CD2> TOM0IST <H'0080 0CD3> TOM07udf TOM06udf TOM05udf TOM04udf TOM03udf b13 TOM02IST F/F TOM02IMA F/F b14 TOM01IST F/F TOM01IMA F/F b15 TOM00IST F/F F/F TOM02udf TOM01udf TOM00udf TOM00IMA To the preceding page Data bus

10-63 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS

10.3 TOP (Output-related 16-bit Timer)

10.3.1 Outline of TOP

TOP (Timer Output) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software:

• Single-shot output mode
• Delayed single-shot output mode
• Continuous output mode The table below shows specifications of TOP. The diagram in the next page shows a block diagram of TOP. Table 10.3.1 Specifications of TOP (Output-related 16-bit Timer) Item Specification Number of channels 11 channels Counter 16-bit down-counter Reload register 16-bit reload register Correction register 16-bit correction register Timer startup Started by writing to enable bit in software or by enabling with external input (rising or falling edge or both) Mode selection <With correction function>
• Single-shot output mode
• Delayed single-shot output mode <Without correction function>
• Continuous output mode Interrupt generation Can be generated by a counter underflow

10-64 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.3.1 Block Diagram of TOP (Output-related 16-bit Timer) IRQ2clk en udf TOP 0 Clock bus Input event bus clk en udfTOP 1 clk en udfTOP 2 clk en udfTOP 3 Output event bus TCLK0S TO 0 IRQ9 3 2 1 0 clk en udfTOP 4 clk en udfTOP 5 TCLK0 TIN0 S STIN0S clk en udfTOP 6 clk en udfTOP 7 S S S IRQ9 TIN1 IRQ9 TIN2 S S clk en udfTOP 8 clk en udfTOP 9 clk en udfTOP 10 F/F0 F/F1 F/F2 F/F3 F/F4 F/F5 F/F6 F/F7 F/F8 F/F9 F/F10 S : SelectorF/F : Output flip-flop S S S S S IRQ2 IRQ2 IRQ2 IRQ2 IRQ2 TO 1 TO 2 TO 3 TO 4 TO 5 TO 6 TO 7 TO 8 TO 9 TO 10 IRQ1 IRQ1 IRQ6 IRQ6 IRQ5 3 2 1 0 0 1 2 3 TIN1S TIN2S Reload register Down-counter Correction register 3 2 1 0 3 2 1 0 0 1 2 3 (16 bits) DRQ7 DRQ8 DRQ9

10-65 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS

10.3.2 Outline of Each Mode of TOP

Each mode of TOP is outlined below. For each TOP channel, only one of the following modes can be selected. (1) Single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once and then stops without performing any operation. When after setting the reload register, the timer is enabled (by writing to the enable bit in software or by external input), the content of the reload register is loaded into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of (reload register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. (2) Delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. When after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1) . Also, an interrupt can be generated when the counter underflows first time and next. (3) Continuous output mode In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload register set value + 1).

10-66 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS When after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of the reload register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows.

10-67 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS

10.3.3 TOP Related Register Map

The diagram below shows a TOP-related register map. Figure 10.3.2 TOP Related Register Map (1/3) H’0080 0240 Address D0 D7 +0 Address +1 AddressD8 D15 H’0080 0242 H’0080 0244 H’0080 0246 H’0080 0250 H’0080 0252 H’0080 0254 H’0080 0256 H’0080 0260 H’0080 0262 H’0080 0264 H’0080 0266 H’0080 0270 H’0080 0272 H’0080 0274 H’0080 0276 TOP0 Counter (TOP0CT) TOP0 Reload Register (TOP0RL) TOP0 Correction Register (TOP0CC) Note: The registers enclosed in thick frames must always be accessed in halfwords.. Blank addresses are reserved. TOP1 Counter (TOP1CT) TOP1 Reload Register (TOP1RL) TOP1 Correction Register (TOP1CC) TOP2 Counter (TOP2CT) TOP2 Reload Register (TOP2RL) TOP2 Correction Register (TOP2CC) TOP3 Counter (TOP3CT) TOP3 Reload Register (TOP3RL) TOP3 Correction Register (TOP3CC)

10-68 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.3.3 TOP Related Register Map (2/3) H’0080 0280 D0 D7 D8 D15 H’0080 0282 H’0080 0284 H’0080 0286 H’0080 0290 H’0080 0292 H’0080 0294 H’0080 0296 H’0080 02A0 H’0080 02A2 H’0080 02A4 H’0080 02A6 H’0080 02B0 H’0080 02B2 H’0080 02B4 H’0080 02B6 H’0080 0298 H’0080 029A H’0080 029C TOP0-5 Control Register 0 (TOP05CR0) TOP0-5 Control Register 1 (TOP05CR1) H’0080 02AA H’0080 02A8 Address +0 Address +1 Address TOP4 Counter (TOP4CT) TOP4 Reload Register (TOP4RL) TOP4 Correction Register (TOP4CC) TOP5 Counter (TOP5CT) TOP5 Reload Register (TOP5RL) TOP5 Correction Register (TOP5CC) TOP6,7 Control Register (TOP67CR) TOP6 Counter (TOP6CT) TOP6 Reload Register (TOP6RL) TOP6 Correction Register (TOP6CC) TOP7 Counter (TOP7CT) TOP7 Reload Register (TOP7RL) TOP7 Correction Register (TOP7CC) Note: The registers enclosed in thick frames must always be accesse d in halfwords. Blank addresses are reserved.

10-69 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.3.4 TOP Related Register Map (3/3) H’0080 02C0 D0 D7 D8 D15 H’0080 02C2 H’0080 02C4 H’0080 02C6 H’0080 02D0 H’0080 02D2 H’0080 02D4 H’0080 02D6 H’0080 02E0 H’0080 02E2 H’0080 02E4 H’0080 02E6 H’0080 02FA H’0080 02FC H’0080 02FE TOP0-10 External Enable Enable Register (TOPEEN) H’0080 02EA TOP8-10 Control Register (TOP810CR) H’0080 02E8 TOP0-10 Enable Protect Register (TOPPRO) TOP0-10 Count Enable Register (TOPCEN) Address +0 Address +1 Address TOP8 Counter (TOP8CT) TOP8 Reload Register (TOP8RL) TOP8 Correction Register (TOP8CC) Note: The registers enclosed in thick frames must always be accesse d in halfwords. Blank addresses are reserved. TOP9 Counter (TOP9CT) TOP9 Reload Register (TOP9RL) TOP9 Correction Register (TOP9CC) TOP9 Counter (TOP9CT) TOP9 Reload Register (TOP9RL) TOP9 Correction Register (TOP9CC) TOP10 Counter (TOP10CT) TOP10 Reload Register (TOP10RL) TOP10 Correction Register (TOP10CC)

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10.3.4 TOP Control Registers

The TOP control registers are used to select operation modes of TOP0-10 (single-shot, delayed single-shot, or continuous mode), as well as select the counter enable and counter clock sources. Following four TOP control registers are provided for each timer group.

• TOP0-5 Control Register 0 (TOP05CR0)
• TOP0-5 Control Register 1 (TOP05CR1)
• TOP6, 7 Control Register (TOP67CR)
• TOP8-10 Control Register (TOP810CR)

10-71 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TOP0-5 Control Register 0 (TOP05CR0) <Address:H'0080 029A> Note 1: This register must always be accessed in halfwords. Note 2: Always make sure the counter has stopped and is idle before setting or changing operation modes. <When reset:H'0000> D Bit Name Function R W 0,1 TOP3M (TOP3 operation mode selection) 00: Single-shot output mode 2,3 TOP2M (TOP2 operation mode selection) 01: Delayed single-shot output mode 4,5 TOP1M (TOP1 operation mode selection) 1X: Continuous output mode 6,7 TOP0M (TOP0 operation mode selection)

8 No functions assigned 0 –

9-10 TOP05ENS 0XX: External TIN0 input (TOP0-5 enable source selection) 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12,13 No functions assigned 0 – 14,15 TOP05CKS 00: Clock bus 0 (TOP0-5 clock source selection) 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOP3M TOP2M TOP1M TOP0M TOP05ENS TOP05CKS

10-72 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TOP0-5 Control Register 1 (TOP05CR1) <Address:H'0080 029D> D 8 9 1 01 11 21 31 4 D 1 5 TOP5M TOP4M Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. Figure 10.3.5 Outline Diagram of TOP0-5 Clock/Enable Inputs <When reset:H'00> D Bit Name Function R W 8-11 No functions assigned 0 – 12,13 TOP5M (TOP5 operation mode selection) 00: Single-shot output mode 14,15 TOP4M (TOP4 operation mode selection) 01: Delayed single-shot output mode 1X: Continuous output mode clk en TOP 0 Clock bus Input event bus clk en TOP 1 clk en TOP 2 clk en TOP 3 3 2 1 0 clk en TOP 4 clk en TOP 5 S S : Selector TIN0 S TIN0S 3 2 1 0 Note: This diagram is shown for the explanation of TOP control registers, and is partly omitted .

10-73 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOP7M TOP6M TOP67ENS TOP67CKSTOP7 ENS I TOP6,7 Control Register (TOP67CR) <Address:H'0080 02AA> Note 1: This register must always be accessed in halfwords. Note 2: Always make sure the counter has stopped and is idle before setting or changing operation modes. <When reset:H'0000> D Bit Name Function R W

0 No functions assigned 0 –

1 TOP7ENS 0: Result selected by TOP67ENS bit

(TOP7 enable source selection) 1: TOP6 output 2,3 TOP7M (TOP7 operation mode selection) 00: Single-shot output mode 01: Delayed single-shot output mode 1X: Continuous output mode 4,5 No functions assigned 0 – 6,7 TOP6M (TOP6 operation mode selection) 00: Single-shot output mode 01: Delayed single-shot output mode 1X: Continuous output mode 9-11 TOP67ENS 0XX: External TIN1 input (TOP6, TOP7 enable source selection) 100: Input event bus 0 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 12,13 No functions assigned 0 – 14,15 TOP67CKS 00: Clock bus 0 (TOP6, TOP7 clock source selection) 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3

10-74 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.3.6 Outline Diagram of TOP6, TOP7 Clock/Enable Inputs 3 2 1 0 clk en udfTOP 6 clk en udfTOP 7 S S TIN1STIN1 S 3 2 1 0 S Clock bus Input event bus : Selector Note: This diagram is shown for the explanation of TOP control registers, and is partly omitted.

10-75 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TOP8-10 Control Register (TOP810CR) <Address:H'0080 02EA> Note 1: This register must always be accessed in halfwords. Note 2: Always make sure the counter has stopped and is idle before setting or changing operation modes. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOP10M TOP9M TOP8M TOP810CKS TOP 810 ENS <When reset:H'0000> D Bit Name Function R W 0,1 No functions assigned 0 – 2,3 TOP10M (TOP10 operation mode selection) 00: Single-shot output mode 4,5 TOP9M (TOP9 operation mode selection) 01: Delayed single-shot output mode 6,7 TOP8M (TOP8 operation mode selection) 1X: Continuous output mode 8-10 No functions assigned 0 –

11 TOP810ENS 0: External TIN2 input

(TOP8-10 enable source selection) 1: Input event bus 3 12,13 No functions assigned 0 – 14,15 TOP810CKS 00: Clock bus 0 (TOP8-10 clock source selection) 01: Clock bus 1 10: Clock bus 2 01: Clock bus 3

10-76 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.3.7 Outline Diagram of TOP8-10 Clock/Enable Inputs 3 2 1 0 TIN2 TIN2S S S clk en TOP 8 clk en TOP 9 clk en TOP 10 S 3 2 1 0 Clock bus Input event bus : Selector Note: This diagram is shown for the explanation of TOP control registers, and is partly omitted.

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10.3.5 TOP Counters (TOP0CT-TOP10CT)

I TOP0 Counter (TOP0CT) <Address:H'0080 0240> I TOP1 Counter (TOP1CT) <Address:H'0080 0250> I TOP2 Counter (TOP2CT) <Address:H'0080 0260> I TOP3 Counter (TOP3CT) <Address:H'0080 0270> I TOP4 Counter (TOP4CT) <Address:H'0080 0280> I TOP5 Counter (TOP5CT) <Address:H'0080 0290> I TOP6 Counter (TOP6CT) <Address:H'0080 02A0> I TOP7 Counter (TOP7CT) <Address:H'0080 02B0> I TOP8 Counter (TOP8CT) <Address:H'0080 02C0> I TOP9 Counter (TOP9CT) <Address:H'0080 02D0> I TOP10 Counter (TOP10CT) <Address:H'0080 02E0> Note: This register must always be accessed in halfwords. The TOP counters are a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by external input), the counter starts counting synchronously with the count clock. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOP0CT-TOP10CT <When reset: Indeterminate> D Bit Name Function R W 0-15 TOP0CT-TOP10CT 16-bit counter value

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10.3.6 TOP Reload Registers (TOP0RL-TOP10RL)

I TOP0 Reload Register (TOP0RL) <Address:H'0080 0242> I TOP1 Reload Register (TOP1RL) <Address:H'0080 0252> I TOP2 Reload Register (TOP2RL) <Address:H'0080 0262> I TOP3 Reload Register (TOP3RL) <Address:H'0080 0272> I TOP4 Reload Register (TOP4RL) <Address:H'0080 0282> I TOP5 Reload Register (TOP5RL) <Address:H'0080 0292> I TOP6 Reload Register (TOP6RL) <Address:H'0080 02A2> I TOP7 Reload Register (TOP7RL) <Address:H'0080 02B2> I TOP8 Reload Register (TOP8RL) <Address:H'0080 02C2> I TOP9 Reload Register (TOP9RL) <Address:H'0080 02D2> I TOP10 Reload Register (TOP10RL) <Address:H'0080 02E2> Note: This register must always be accessed in halfwords. The TOP reload registers are used to load data into the TOP counter registers (TOP0CT- TOP10CT). It is in the following cases that the content of the reload register is loaded in the counter:

• When the counter is enabled in single-shot mode
• When the counter underflowed in delayed single-shot or continuous mode Writing data to the reload register does not mean that the data is loaded into the counter simultaneously. Note that data reloading after an underflow is performed synchronously with the clock period in which the counter underflowed. <When reset: Indeterminate> D Bit Name Function R W 0-15 TOP0RL-TOP10RL 16-bit reload register value D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOP0RL-TOP10RL

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10.3.7 TOP Correction Registers (TOP0CC-TOP10CC)

I TOP0 Correction Register (TOP0CC) <Address:H'0080 0246> I TOP1 Correction Register (TOP1CC) <Address:H'0080 0256> I TOP2 Correction Register (TOP2CC) <Address:H'0080 0266> I TOP3 Correction Register (TOP3CC) <Address:H'0080 0276> I TOP4 Correction Register (TOP4CC) <Address:H'0080 0286> I TOP5 Correction Register (TOP5CC) <Address:H'0080 0296> I TOP6 Correction Register (TOP6CC) <Address:H'0080 02A6> I TOP7 Correction Register (TOP7CC) <Address:H'0080 02B6> I TOP8 Correction Register (TOP8CC) <Address:H'0080 02C6> I TOP9 Correction Register (TOP9CC) <Address:H'0080 02D6> I TOP10 Correction Register (TOP10CC) <Address:H'0080 02E6> <When reset: Indeterminate> D Bit Name Function R W 0-15 TOP0CC-TOP10CC 16-bit correction register value D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOP0CC-TOP10CC (Acceptable set values +32767- –32768) Note: This register must always be accessed in halfwords. The TOP correction registers are used to correct the TOP counter value by adding or subtracting it in the middle of operation. To increase or reduce the counter value, write a value to this correction register, the value by which you want to be increased or reduced from the initial count set in the counter. To add, write the value you want to add to the correction register directly as is; to subtract, write the two's complement of the value you want to subtract to the correction register. Correction of the counter is performed synchronously with a clock period next to the one in which the correction value was written to the TOP correction register. In this case, one down-count in the clock period during which the correction was performed is canceled. Therefore, note that the counter value actually is corrected by (correction register value + 1). For example, if the initial counter value is 10 and you write a value 3 to the correction register when the counter has counted down to 5, then the counter underflows after a total of 15 counts.

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10.3.8 TOP Enable Control Register

I TOP0-10 External Enable Permit Register (TOPEEN)<Address:H'0080 02FA> Note: This register must always be accessed in halfwords. The TOP0-10 External Enable Permit Register controls enable operation from sources external to the TOP counter by enabling or disabling it. D Bit Name Function R W 0-4 No functions assigned 0 –

5 TOP10EEN (TOP10 external enable permit) 0: Disables external enable

6 TOP9EEN (TOP9 external enable permit) 1: Enables external enable

7 TOP8EEN (TOP8 external enable permit)

8 TOP7EEN (TOP7 external enable permit)

9 TOP6EEN (TOP6 external enable permit)

10 TOP5EEN (TOP5 external enable permit)

11 TOP4EEN (TOP4 external enable permit)

12 TOP3EEN (TOP3 external enable permit)

13 TOP2EEN (TOP2 external enable permit)

14 TOP1EEN (TOP1 external enable permit)

15 TOP0EEN (TOP0 external enable permit)

D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 EEN EEN EEN EEN EEN EEN EEN EEN EEN EEN EEN

10-81 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TOP0-10 Enable Protect Register (TOPPRO) <Address:H'0080 02FC> Note: This register must always be accessed in halfwords. The TOP0-10 Enable Protect Register controls rewriting of the TOP0-10 count enable bits shown in the next page by enabling or disabling rewrite. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO <When reset:H'0000> D Bit Name Function R W 0-4 No functions assigned 0 –

5 TOP10PRO (TOP10 enable protect) 0: Enables rewrite

6 TOP9PRO (TOP9 enable protect) 1: Disables rewrite

7 TOP8PRO (TOP8 enable protect)

8 TOP7PRO (TOP7 enable protect)

9 TOP6PRO (TOP6 enable protect)

10 TOP5PRO (TOP5 enable protect)

11 TOP4PRO (TOP4 enable protect)

12 TOP3PRO (TOP3 enable protect)

13 TOP2PRO (TOP2 enable protect)

14 TOP1PRO (TOP1 enable protect)

15 TOP0PRO (TOP0 enable protect)

10-82 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TOP0-10 Count Enable Register (TOPCEN) <Address:H'0080 02FE> Note: This register must always be accessed in halfwords. The TOP0-10 Count Enable Register controls the operation of TOP counter. To enable the counter in software, enable the relevant TOP0-10 Enable Protect Register for write and set the count enable bit by writing a 1. To stop the counter, enable the TOP0-10 Enable Protect Register for write and reset the count enable bit by writing a 0. In all but continuous mode, when the counter stops due to an occurrence of underflow, the count enable bit is automatically reset to 0. Therefore, what you get by reading the TOP0-10 Count Enable Register is the status that indicates the counter's operating status (active or idle). <When reset:H'0000> D Bit Name Function R W 0-4 No functions assigned 0 –

5 TOP10CEN (TOP10 count enable) 0: Stops count

6 TOP9CEN (TOP9 count enable) 1: Enables count

7 TOP8CEN (TOP8 count enable)

8 TOP7CEN (TOP7 count enable)

9 TOP6CEN (TOP6 count enable)

10 TOP5CEN (TOP5 count enable)

11 TOP4CEN (TOP4 count enable)

12 TOP3CEN (TOP3 count enable)

13 TOP2CEN (TOP2 count enable)

14 TOP1CEN (TOP1 count enable)

15 TOP0CEN (TOP0 count enable)

D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 CEN CEN CEN CEN CEN CEN CEN CEN CEN CEN CEN

10-83 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.3.8 Configuration of the TOP Enable Circuit WR Dn TOPm enable protect (TOPmPRO) WR EN-ON TOPm external enable (TOPmEEN) TINnS TOPm enable (TOPmCEN) TOP enable control Edge selection F/F F/F F/F Event bus

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10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function)

(1) Outline of TOP single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload register value + 1) only once and stops without performing any operation. When after setting the reload register, the timer is enabled (by writing to the enable bit in software or by external input), it loads the content of the reload register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. The count value is (reload register set value + 1). In the case shown below, for example, if the reload register value = 7, then the count value = 8. Because all internal circuits operate synchronously with the count clock, a finite time equal to a prescaler delay is included before F/F output changes state after the timer is enabled. Figure 10.3.9 Example of Counting in TOP Single-shot Output Mode Enable Reload register (7) 6 5 4 3 12345678 H ’FFFF7 Counter Interrupt Underflow Count value =8 (Note 1) Note 1: What you actually see in the cycle immediately after reload is the previous counter value, and not 7. Note 2: This diagram does not show detail timing information . 2 1 0 F/F output * A finite time equal to a prescaler delay is included before F/F output changes state after the timer is enabled. Count clock

10-85 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS In the example below, the reload register has the initial value H'A000 set in it. (The initial value of the counter can be indeterminate, and does not have to be specific.) When the timer starts, the reload register value is loaded into the counter causing it to start counting. Thereafter, it continues counting down clock pulses until it underflows after reaching the minimum count. Figure 10.3.10 Typical Operation in TOP Single-shot Output Mode Count clock Correction register H ’FFFF H ’0000 Enabled (by writing to enable bit or by external input) F/F output Disabled (by underflow) (Not used) TOP interrupt due to underflow Enable bit Starts counting down from the reload register set value Note: This diagram does not show detail timing information. Reload register H ’A000 Data inverted by enable Counter H ’A000 Data inverted by underflow H ’FFFF

10-86 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (2) Correction function of TOP single-shot output mode If you want to change the counter value during operation, write a value to the TOP correction register, the value by which you want to be increased or reduced from the initial count set in the counter. To add, write the value you want to add to the correction register directly as is; to subtract, write the two's complement of the value you want to subtract to the correction register. Correction of the counter is performed synchronously with a clock period next to the one in which the correction value was written to the TOP correction register. In this case, one down-count in the clock period during which the correction was performed is canceled. Therefore, note that the counter value actually is corrected by (correction register value + 1). For example, if the initial counter value is 7 and you write a value 3 to the correction register when the counter has counted down to 3, then the counter underflows after a total of 12 counts. Figure 10.3.11Example of Counting in TOP Single-shot Output Mode When Count is Corrected Enable Reload register (7) 6 5 4 3 2 1 0 123456789 1 0 1 1 1 2 6 5 4 3 H ’FFFF7 Counter 3Correction register Interrupt Underflow Count value =(7+1)+(3+1)=12 (Note 1) Note 1: What you actually see in the cycle immediately after reload is th e previous counter value, and not 7. Note 2: This diagram does not show detail timing information. Prescaler delay Count clock

10-87 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS When writing to the correction register, be careful not to cause the counter to overflow. Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. In the example below, the reload register has the initial value H'8000 set in it. When the timer starts, the reload register value is loaded into the counter causing it to start counting down. In the example diagram here, H'4000 is written to the correction register when the counter has counted down to H'5000. As a result of this correction, the count has been increased to H'9000, so that the counter stops after counting a total of (H'8000 + 1 + H'4000 + 1) counts.

10-88 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.3.12 Example of Counting in TOP Single-shot Output Mode When Count is Corrected H ’FFFF H ’0000 Indeterminate H ’8000 Write to correction register H ’4000 H ’5000 H ’5000+H ’4000 H ’8000 H ’FFFF Count clock Correction register Enabled (by writing to enable bit or by external input) F/F output Disabled (by underflow) TOP interrupt due to underflow Enable bit Note: This diagram does not show detail timing information. Reload register Data inverted by enable Counter Data inverted by underflow

10-89 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (3) Precautions to be observed when using TOP single-shot output mode The following describes precautions to be observed when using TOP single-shot output mode.

• If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops).
• If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled).
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled).
• Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. Figure 10.3.13 Prescaler Delay
• When writing to the correction register, be careful not to cause the counter to overflow. Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. When the counter underflows in the subsequent down-count after overflow, a false underflow interrupt is generated due to overcounting. In the example below, the reload register has the initial value H'FFF8 set in it. When the timer starts, the reload register value is loaded into the counter causing it to start counting down. In the example diagram here, H'0014 is written to the correction register when the counter has counted down to H'FFF0. As a result of this correction, the count overflows to H'0004 and fails to count correctly. Also, an interrupt is generated for an erroneous overcount. Internal clock Count clock Enable F/F operation Prescaler cycle Delay till prescaler cycle Write to enable bit

10-90 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.3.14 Example of Operation in TOP Single-shot Output Mode Where Count Overflows due to Correction H ’FFFF H ’0000 Indeterminate Indeterminate H ’FFF8 Write to correction register H ’(FFF0+0014) H ’0004 H ’FFF0 H ’0014 Overflow occurs Actual count after overflow H ’FFF8 H ’FFFF Count clock Correction register Enabled (by writing to enable bit or by external input) F/F output Disabled (by underflow) TOP interrupt due to underflow Enable bit Note: This diagram does not show detail timing information. Reload register Data inverted by enable Counter Data inverted by underflow

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10.3.10 Operation in TOP Delayed Single-shot Output Mode (With Correction Function)

(1) Outline of TOP delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. When after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an interrupt can be generated when the counter underflows first time and next. The valid count values are the (counter set value + 1) and (reload register set value + 1). The diagram below shows timer operation as an example when the initial counter value = 4 and the initial reload register value = 5. Figure 10.3.15 Example of Counting in TOP Delayed Single-shot Output Mode Enable Reload register (4) 3 2 1 12345678 H ’FFFF Counter Interrupt Underflow Count value =(4+1)+(5+1)=11 (Note 1) F/F output 3 2 1 0 4(5) (Note 2) H ’FFFF Underflow Prescaler delay Count clock Note 1: What you actually see in the cycle immediately after enable is the previous counter value, and not 4. Note 2: What you actually see in the cycle immediately after reload is H'FFFF (underflow value), and not 5. Note 3: This diagram does not show detail timing information.

10-92 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS In the example below, the counter has the initial value H'A000 set in it and the reload register has the initial value H'F000 set in it. When the timer starts, the counter starts counting down clock pulses and when it underflows after reaching the minimum count, the counter is reloaded with the content of the reload register. Then when the counter underflows next time while continuing down- count, it stops. Figure 10.3.16 Typical Operation in TOP Delayed Single-shot Output Correction register H ’FFFF H ’0000 Underflow (first time) Down-count starting from counter’s set value H ’A000 Underflow (second time) H ’F000 Down-count starting from reload register’s set value H ’(F000-1) Data inverted by underflow (Not used) H ’FFFF H ’F000 Count clock Enabled (by writing to enable bit or by external input) F/F output TOP interrupt due to underflow Enable bit Note: This diagram does not show detail timing information . Reload register Counter Data inverted by underflow

10-93 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (2) Correction function of TOP delayed single-shot output mode If you want to change the counter value during operation, write a value to the TOP correction register, the value by which you want to be increased or reduced from the initial count set in the counter. To add, write the value you want to add to the correction register directly as is; to subtract, write the two's complement of the value you want to subtract to the correction register. Correction of the counter is performed synchronously with a clock period next to the one in which the correction value was written to the TOP correction register. In this case, one down-count in the clock period during which the correction was performed is canceled. Therefore, note that the counter value actually is corrected by (correction register value + 1). For example, if the initial counter value is 7 and you write a value 3 to the correction register when the counter has counted down to 3, then the counter underflows after a total of 12 counts after reload. Figure 10.3.17 Example of Counting in TOP Delayed Single-shot Output Mode When Count is Corrected When writing to the correction register, be careful not to cause the counter to overflow. Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. Enable = "H" Reload register (7) 6 5 4 3 2 1 0 123456789 1 0 1 1 1 2 6 5 4 3 H ’FF Counter 3Correction register Interrupt Underflow Count value after reload =(7+1)+(3+1)=12 (Note 1) Count clock Note 1: What you actually see in the cycle immediately after reload is the previous counter valu and not 7. Note 2: This diagram does not show detail timing information.

10-94 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.3.18 Typical Operation in TOP Delayed Single-shot Output Mode when Correction Applied H ’FFFF H ’0000 Underflow (first time) Indeterminate Counter corrected H ’F000 H ’A000 Underflow (second time) H ’F000 H ’(F000+0008+1) H ’0008 Write to correction register Correction register Data inverted by underflow Count clock F/F output TOP interrupt due to underflow Enable bit Reload register Counter Data inverted by underflow Note: This diagram does not show detail timing information.

10-95 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (3) Precautions to be observed when using TOP delayed single-shot output mode The following describes precautions to be observed when using TOP delayed single-shot output mode.

• If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops).
• If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled).
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled).
• Even when the counter overflows due to correction of counts, no interrupt is generated for the occurrence of overflow. When the counter underflows in the subsequent down-count after overflow, a false underflow interrupt is generated due to overcounting.
• When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge. Figure 10.3.19 Counter Value Immediately after Underflow Count clock Enable bit "H" H ’0001 H ’0000 H ’FFFF H ’AAA9 H ’AAA8Counter value H ’AAAAReload register Reload due to underflow H ’(AAAA-1) H ’(AAAA-2) During reload cycle, you always see H’FFFF, and not the reload register value (in this case, H ’AAAA). Down-count starting from reloaded register value Reload cycle

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10.3.11 Operation in TOP Continuous Output Mode (Without Correction Function)

(1) Outline of TOP continuous output mode In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload register set value + 1). When after setting the counter and reload register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of the reload register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows.

10-97 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS The valid count values are the (counter set value + 1) and (reload register set value + 1). The diagram below shows timer operation as an example when the initial counter value = 4 and the initial reload register value = 5. Note 1: What you actually see in the cycle immediately after enable is the previous counter value, and not 4. Note 2: What you actually see in the cycle immediately after reload is H'FFFF (underflow value), and not 5. Note 3: This diagram does not show detail timing information. Figure 10.3.20 Example of Counting in TOP Continuous Output Mode (4) 3 2 1 12345 H ’FFFF Count value =5 3 2 1 0 4(5) 3 2 1 0 (5) (5)4 123456 Count value =6 Count value =6 123456 Enable Reload register Counter Interrupt (Note 1) F/F output Underflow Prescaler delay Count clock (Note 2) (Note 2) (Note 2) Underflow Underflow

10-98 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS In the example below, the counter has the initial value H'A000 set in it and the reload register has the initial value H'E000 set in it. When the timer starts, the counter starts counting down clock pulses and when it underflows after reaching the minimum count, the counter is reloaded with the content of the reload register and continues counting down. Figure 10.3.21 Typical Operation in TOP Continuous Output Mode H ’FFFF H ’0000 H ’E000 H ’A000 Data inverted by enable H ’(E000-1) H ’FFFF H ’FFFF Correction register Underflow (first time) Down-count starting from counter’s set value Underflow (second time) Down-count starting from reload register set value Data inverted by underflow (Not used) Count clock Enabled (by writing to enable bit or by external input) F/F output TOP interrupt due to underflow Enable bit Note: This diagram does not show detail timing information. Reload register Counter Down-count starting from reload register set value Data inverted by underflow

10-99 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (2) Precautions to be observed when using TOP continuous output mode The following describes precautions to be observed when using TOP continuous output mode.

• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled).
• When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge.
• Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled. Figure 10.3.22 Prescaler Delay Internal clock Count clock Enable F/F operation Prescaler cycle Delay till prescaler cycle Write to enable bit

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10.4 TIO (Input/Output-related 16-bit Timer)

10.4.1 Outline of TIO

TIO (Timer Input/Output) is an input/output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software: <Input mode>

• Measure clear input mode
• Measure free-run input mode
• Nose processing input mode <Output mode without correction function>
• PWM output mode
• Single-shot output mode
• Delayed single-shot output mode
• Continuous output mode The table below shows specifications of TIO. The diagram in the next page shows a block diagram of TIO. Table 10.4.1 Specifications of TIO (Input/Output-related 16-bit Timer) Item Specification Number of channels 10 channels Counter 16-bit down-counter Reload register 16-bit reload register Measure register 16-bit capture register Timer startup Started by writing to enable bit in software or by enabling with external input (rising/falling edge or both or high/low level) Mode selection <Input mode>
• Measure clear input mode
• Measure free-run input mode
• Nose processing input mode <Output mode without correction function>
• PWM output mode
• Single-shot output mode
• Delayed single-shot output mode
• Continuous output mode Interrupt generation Can be generated by a counter underflow

10-101 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.4.1 Block Diagram of TIO (Input/Output-related 16-bit Timer) IRQ12 IRQ12 IRQ12 3 2 1 0 internal clock IRQ8 TIN7 TCLK1 clk en/cap udf TIO 0 clk en/cap udfTIO 1 clk en/cap udfTIO 2 clk en/cap udfTIO 3 clk en/cap udfTIO 4 S STIN3STIN3 S S TIN4STIN4 TIN5STIN5 S SIRQ12 TIN6STIN6 PRS1 PRS0 clk en/cap udfTIO 5STCLK1S STIN7S IRQ8 TIN8 TCLK2 clk en/cap udfTIO 6STCLK2S STIN8S IRQ8 TIN9 clk en/cap udfTIO 7S STIN9S IRQ8 TIN10 S STIN10S clk en/cap udfTIO 8 clk en/cap udfTIO 9 IRQ8 TIN11 S STIN11S F/F11 F/F12 F/F13 F/F14 F/F15 S F/F16 F/F17 F/F18 F/F19 SF/FPRS0 2 : Prescaler S S S S S S S S S TO 11 TO 12 TO 13 TO 14 TO 15 IRQ0 IRQ0 IRQ0 IRQ0 IRQ4 TO 16 TO 17 TO 18 TO 19 TO 20 IRQ4 IRQ4 IRQ4 DRQ0 IRQ3 3 2 1 0 0 1 2 3 0 1 2 33 2 1 0 3 2 1 0 PRS2 IRQ3 Note: Reload 1 Register is used in only PWM output mode. F/F20 DRQ10 DRQ11 Clock bus Input event bus O utput event bus Reload 0/measure register Down-counter Reload 1 register (note) (16 bits) : Selector: Output flip-flop~

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10.4.2 Outline of Each Mode of TIO

Each mode of TIO is outlined below. For each TIO channel, only one of the following modes can be selected. (1) Measure clear/free-run input modes In measure clear/free-run input modes, the timer measures a duration of time from when it starts counting till when an external capture signal is entered. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchronously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written to a register called the "measure register." Especially in measure clear input mode, the counter value is initialized to H'FFFF upon capture, from which the counter starts counting down again. In measure free-run mode, the counter continues counting down even after capture and upon underflow, recycles to H'FFFF, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software. Note that an interrupt can be generated by a counter underflow or execution of measure operation. (2) Noise processing input mode In noise processing input mode, the timer detects the status of an input signal that it remained in the same state for over a predetermined time. In noise processing input mode, the counter is started by entering a high or low-level signal from an external device and if the signal remains in the same state for over a predetermined time before the counter underflows, the counter stops after generating an interrupt. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and when a valid-level signal is entered again, it is reloaded with the initial count and restarts counting. The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. An interrupt can be generated by a counter underflow. (3) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle.

10-103 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by external input), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The F/F output waveform in PWM output mode is inverted at count startup and upon each underflow. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). An interrupt can be generated when the counter underflows every other time (second time, fourth time, and so on) after being enabled. (4) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. (5) Delayed single-shot output mode (without correction function) In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload 0 register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an interrupt can be generated when the counter underflows first time and next.

10-104 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (6) Continuous output mode (without correction function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows.

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10.4.3 TIO Related Register Map

The diagram below shows a TIO related register map. Figure 10.4.2 TIO Related Register Map (1/3) H’0080 0300 D0 D7 +0 Address +1 AddressD8 D15 H’0080 0302 H’0080 0304 H’0080 0306 H’0080 0310 H’0080 0312 H’0080 0314 H’0080 0316 H’0080 0320 H’0080 0322 H’0080 0324 H’0080 0326 H’0080 0330 H’0080 0332 H’0080 0334 H’0080 0336 TIO0 Reload 0/ Measure Register (TIO0RL0) H’0080 0318 H’0080 031A H’0080 031C TIO0-3 Control Register 0 (TIO03CR0) TIO0-3 Control Register 1 (TIO03CR1) Address TIO0 Counter (TIO0CT) TIO0 Reload 1 Register (TIO0RL) Note: The registers enclosed in thick frames must always be accessed in halfwords. Blank addresses are reserved. TIO1 Reload 0/ Measure Register (TIO1RL0) TIO1 Counter (TIO1CT) TIO1 Reload 1 Register (TIO1RL1) TIO2 Reload 0/ Measure Register (TIO2RL0) TIO2 Counter (TIO2CT) TIO2 Reload 1 Register (TIO2RL1) TIO3 Reload 0/ Measure Register (TIO3RL0) TIO3 Counter (TIO3CT) TIO3 Reload 1 Register (TIO3RL1)

10-106 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.4.3 TIO Related Register Map (2/3) H’0080 0340 D0 D7 D8 D15 H’0080 0342 H’0080 0344 H’0080 0346 H’0080 0350 H’0080 0352 H’0080 0354 H’0080 0356 H’0080 0360 H’0080 0362 H’0080 0364 H’0080 0366 H’0080 0370 H’0080 0372 H’0080 0374 H’0080 0376 H’0080 034A H’0080 0348 TIO4 Control Register (TIO4CR) H’0080 036A H’0080 0368 +0 Address +1 Address TIO4 Reload 0/ Measure Register (TIO4RL0) TIO5 Control Register (TIO5CR) Address TIO4 Counter (TIO4CT) TIO4 Reload 1 Register (TIO4RL1) Blank addresses are reserved. TIO5 Reload 0/ Measure Register (TIO5RL0) TIO5 Counter (TIO5CT) TIO5 Reload 1 Register (TIO5RL1) TIO6 Reload 0/ Measure Register (TIO6RL0) TIO6 Counter (TIO6CT) TIO6 Reload 1 Register (TIO6RL1) TIO6 Control Register (TIO6CR) TIO7 Control Register (TIO7CR) TIO7 Reload 0/ Measure Register (TIO7RL0) TIO7 Counter (TIO7CT) TIO7 Reload 1 Register (TIO7RL1) Note: The registers enclosed in thick frames must always be accessed in halfwords.

10-107 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.4.4 TIO Related Register Map (3/3) H’0080 0380 D0 D7 D8 D15 H’0080 0382 H’0080 0384 H’0080 0386 H’0080 0390 H’0080 0392 H’0080 0394 H’0080 0396 H’0080 03BC H’0080 03BE H’0080 038A H’0080 0388 +0 Address +1 Address TIO8 Reload 0/ Measure Register (TIO8RL0) TIO9 Control Register (TIO9CR) Address TIO8 Counter (TIO8CT) TIO8 Reload 1 Register (TIO8RL1) Note: The registers enclosed in thick frames must always be accessed in halfwords. Blank addresses are reserved. TIO8 Control Register (TIO8CR) TIO9 Reload 0/ Measure Register (TIO9RL0) TIO9 Counter (TIO9CT) TIO9 Reload 1 Register (TIO9RL1) TIO0-9 Enable Protect Register (TIOPRO) TIO0-9 Count Enable Register (TIOCEN)

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10.4.4 TIO Control Registers

The TIO control registers are used to select TIO0-9 operation modes (measure input, noise processing input, PWM output, single-shot output, delayed single-shot output, or continuous output mode), as well as select the counter enable and counter clock sources. Following eight TIO control registers are provided for each timer group.

• TIO0-3 Control Register 0 (TIO03CR0)
• TIO0-3 Control Register 1 (TIO03CR1)
• TIO4 Control Register (TIO4CR)
• TIO5 Control Register (TIO5CR)
• TIO6 Control Register (TIO6CR)
• TIO7 Control Register (TIO7CR)
• TIO8 Control Register (TIO8CR)
• TIO9 Control Register (TIO9CR)

10-109 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS <When reset:H'0000> D Bit Name Function R W

0 TIO3EEN (TIO3 external input enable) 0: Disables external input

(Note 2) 1: Enables external input 1-3 TIO3M (TIO3 operation mode selection) 000: Single-shot output mode 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode

4 TIO2ENS (TIO2 enable/ 0: No selection

measure input source selection) 1: External input TIN5 5-7 TIO2M 000: Single-shot output mode (TIO2 operation mode selection) 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode

8 TIO1ENS (TIO1 enable/ 0: No selection

measure input source selection) 1: External input TIN4 I TIO0-3 Control Register 0 (TIO3CR0) <Address:H'0080 031A> Note 1:To select the TIO3 enable/measure input source, use the TIO4 Control Register's TIO34ENS (TIO3, TIO4 enable/measure input source selection) bit. Note 2:During measure free-run/clear input mode, even if this bit is set to 0 (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written to the measure register. However, because in measure clear input mode, if this bit = 0 (external input disabled), the counter value is not initialized (H'FFFF) upon capture, we recommend that this bit be set to 1 (external input enabled) when using measure clear input mode. Note 3:This register must always be accessed in halfwords. Note 4:Always make sure the counter has stopped and is idle before setting or changing operation modes. TIO3 TIO2 TIO1 TIO0 EEN ENS ENS ENS D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TIO3M TIO2M TIO1M TIO0M (Continues to the next page)

10-110 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (Continued from the preceding page) Note 1: This register must always be accessed in halfwords. Note 2: Always make sure the counter has stopped and is idle before setting or changing operation modes. Figure 10.4.5 Outline Diagram of TIO0-4 Clock/Enable Inputs D Bit Name Function R W 9-11 TIO1M 000: Single-shot output mode (TIO1 operation mode selection) 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode

12 TIO0ENS (TIO0 enable/ 0: No selection

measure input source selection) 1: External input TIN3 13-15 TIO0M 000: Single-shot output mode (TIO0 operation mode selection) 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode Clock bus Input event bus 3 2 1 0 clk en/cap TIO 0 clk en/cap TIO 1 clk en/cap TIO 2 clk en/cap TIO 3 clk en/cap TIO 4 S STIN3STIN3 S S TIN4STIN4 TIN5STIN5 S S TIN6STIN6 S : Selector 3 2 1 0 3 2 1 0 3 2 1 0 Note: This diagram is shown for the explanation of TIO control registers, and is partly omitted .

10-111 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TIO0-3 Control Register 1 (TIO03CR1) <Address:H'0080 031D> <When reset:H'00> D Bit Name Function R W 8-13 No functions assigned 0 – 14,15 TIO03CKS 00: Clock bus 0 (TIO0-3 clock source selection) 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 D 8 9 1 01 11 21 31 4 D 1 5 TIO03CKS

10-112 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TIO4 Control Register (TIO4CR) <Address:H'0080 034A> Note 1:During measure free-run/clear input mode, even if this bit is set to 0 (external input disabled), when a capture signal is entered from an external device, the counter value at that point in time is written to the measure register. However, because in measure clear input mode, if this bit = 0 (external input disabled), the counter value is not initialized (H'FFFF) upon capture, we recommend that this bit be set to 1 (external input enabled) when using measure clear input mode. Note 2:Always make sure the counter has stopped and is idle before setting or changing operation modes. D 0 123456 D 7 TIO4CKS TIO4EEN TIO34ENS TIO4M <When reset:H'00> D Bit Name Function R W 0, 1 TIO4CKS 00: Clock bus 0 (TIO4 clock source selection) 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3

2 TIO4EEN (Note 1) 0: Disables external input

(TIO4 external input enable) 1: Enables external input 3,4 TIO34ENS 0X: External input TIN6 (TIO3,4 enable/measure 10: Input event bus 2 input source selection) 11: Input event bus 3 5-7 TIO4M 000: Single-shot output mode (TIO4 operation mode selection) 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode

10-113 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.4.6 Outline Diagram of TIO5-9 Clock/Enable Inputs clk en/capS TCLK2S STIN8S 3 2 1 0 TIN7 TCLK1 clk en/cap TIO 5S TCLK1S STIN7S TIN8 TCLK2 TIO 6 TIN9 clk en/cap TIO 7S STIN9S TIN10 S STIN10S clk en/cap TIO 8 clk en/cap TIO 9 TIN11 S STIN11S S 3 2 1 0 3 2 1 0 3 2 1 0 Clock bus Input event bus : Selector Note: This is an outline diagram shown for the explanation of TIO Control Register

10-114 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TIO5 Control Register (TIO5CR) <Address:H'0080 034B> Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. <When reset:H'00> D Bit Name Function R W 8-10 TIO5CKS 0XX: External input TCLK1 (TIO5 clock source selection) 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 11,12 TIO5ENS 0X: No selection (TIO5 enable/measure 10: External input TIN7 input source selection) 11: Input event bus 3 13-15 TIO5M 000: Single-shot output mode (TIO5 operation mode selection) 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode D 8 9 1 01 11 21 31 4 D 1 5 TIO5CKS TIO5ENS TIO5M

10-115 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TIO6 Control Register (TIO6CR) <Address:H'0080 036A> Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. D 0 123456 D 7 TIO6CKS TIO6ENS TIO6M <When reset:H'00> D Bit Name Function R W 0-2 TIO6CKS 0XX: External input TCLK2 (TIO6 clock source selection) 100: Clock bus 0 101: Clock bus 1 110: Clock bus 2 111: Clock bus 3 3,4 TIO6ENS 00: No selection (TIO6 enable/measure 01: External input TIN8 input source selection) 10: Input event bus 2 11: Input event bus 3 5-7 TIO6M 000: Single-shot output mode (TIO6 operation mode selection) 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode

10-116 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TIO7 Control Register (TIO7CR) <Address:H'0080 036B> Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. <When reset:H'00> D Bit Name Function R W 9,10 TIO7CKS 00: Clock bus 0 (TIO7 clock source selection) 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11,12 TIO7ENS 00: No selection (TIO7 enable/measure 01: External input TIN9 input source selection) 10: Input event bus 0 11: Input event bus 3 13-15 TIO7M 000: Single-shot output mode (TIO7 operation mode selection) 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode D 8 9 1 01 11 21 31 4 D 1 5 TIO7CKS TIO7ENS TIO7M

10-117 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TIO8 Control Register (TIO8CR) <Address:H'0080 038A> Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. <When reset:H'00> D Bit Name Function R W 0,1 TIO8CKS 00: Clock bus 0 (TIO8 clock source selection) 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 2-4 TIO8ENS 0XX: No selection (TIO8 enable/measure 100: External input TIN10 input source selection) 101: Input event bus 1 110: Input event bus 2 111: Input event bus 3 5-7 TIO8M 000: Single-shot output mode (TIO8 operation mode selection) 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode D 0 123456 D 7 TIO8CKS TIO8ENS TIO8M

10-118 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TIO9 Control Register (TIO9CR) <Address:H'0080 038B> Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. <When reset:H'00> D Bit Name Function R W 9,10 TIO9CKS 00: Clock bus 0 (TIO9 clock source selection) 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 11,12 TIO9ENS 00: No selection (TIO9 enable/measure 01: External input TIN1 input source selection) 10: Input event bus 1 11: Input event bus 3 13-15 TIO9M 000: Single-shot output mode (TIO9 operation mode selection) 001: Delayed single-shot output mode 010: Continuous output mode 011: PWM output mode 100: Measure clear input mode 101: Measure free-run input mode 11X: Noise processing input mode D 8 9 1 01 11 21 31 4 D 1 5 TIO9CKS TIO9ENS TIO9M

10-119 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS <When reset: Indeterminate> D Bit Name Function R W 0-15 TIO0CT-TIO9CT 16-bit counter value

10.4.5 TIO Counter (TIO0CT-TIO9CT)

I TIO0 Counter (TIO0CT) <Address:H'0080 0300> I TIO1 Counter (TIO1CT) <Address:H'0080 0310> I TIO2 Counter (TIO2CT) <Address:H'0080 0320> I TIO3 Counter (TIO3CT) <Address:H'0080 0330> I TIO4 Counter (TIO4CT) <Address:H'0080 0340> I TIO5 Counter (TIO5CT) <Address:H'0080 0350> I TIO6 Counter (TIO6CT) <Address:H'0080 0360> I TIO7 Counter (TIO7CT) <Address:H'0080 0370> I TIO8 Counter (TIO8CT) <Address:H'0080 0380> I TIO9 Counter (TIO9CT) <Address:H'0080 0390> W= : Write to this register is not accepted is disabled in PWM output mode. Note: This register must always be accessed in halfwords. The TIO Counters are a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by external input), the counter starts counting synchronously with the count clock. The counter cannot be written to during PWM output mode. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TIO0CT-TIO9CT

10-120 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS <When reset: Indeterminate> D Bit Name Function R W 0-15 TIO0RL0-TIO9RL0 16-bit reload register value

10.4.6 TIO Reload 0/ Measure Register (TIO0RL0-TIO9RL0)

I TIO0 Reload 0/ Measure Register (TIO0RL0) <Address:H'0080 0306> I TIO1 Reload 0/ Measure Register (TIO1RL0) <Address:H'0080 0316> I TIO2 Reload 0/ Measure Register (TIO2RL0) <Address:H'0080 0326> I TIO3 Reload 0/ Measure Register (TIO3RL0) <Address:H'0080 0336> I TIO4 Reload 0/ Measure Register (TIO4RL0) <Address:H'0080 0346> I TIO5 Reload 0/ Measure Register (TIO5RL0) <Address:H'0080 0356> I TIO6 Reload 0/ Measure Register (TIO6RL0) <Address:H'0080 0366> I TIO7 Reload 0/ Measure Register (TIO7RL0) <Address:H'0080 0376> I TIO8 Reload 0/ Measure Register (TIO8RL0) <Address:H'0080 0386> I TIO9 Reload 0/ Measure Register (TIO9RL0) <Address:H'0080 0396> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TIO0RL0-TIO9RL0 W= : Write to this register is not accepted is disabled in PWM output mode. Note: This register must always be accessed in halfwords. The TIO Reload 0/ Measure Registers serve dual purposes as a register for reloading TIO Count Registers (TIO0CT-TIO9CT) with data, and as a measure register during measure input mode. These registers are disabled against write during measure input mode. It is in the following cases that the content of reload 0 register is loaded into the counter:

• When after the counter started counting in noise processing input mode, the input signal is inverted and a valid-level signal is entered again before the counter underflows
• When the counter is enabled in single-shot mode
• When the counter underflowed in delayed single-shot or continuous mode
• When the counter is enabled in PWM mode and when the counter value set by reload 1 register underflowed Writing data to the reload 0 register does not mean that the data is loaded into the counter simultaneously. When used as a measure register, the counter value is latched into the measure register by an event input.

10-121 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS <When reset: Indeterminate> D Bit Name Function R W 0-15 TIO0RL1-TIO9RL1 16-bit reload register value

10.4.7 TIO Reload 1 Registers (TIO0RL1-TIO9RL1)

I TIO0 Reload 1 Register (TIO0RL1) <Address:H'0080 0304> I TIO1 Reload 1 Register (TIO1RL1) <Address:H'0080 0314> I TIO2 Reload 1 Register (TIO2RL1) <Address:H'0080 0324> I TIO3 Reload 1 Register (TIO3RL1) <Address:H'0080 0334> I TIO4 Reload 1 Register (TIO4RL1) <Address:H'0080 0344> I TIO5 Reload 1 Register (TIO5RL1) <Address:H'0080 0354> I TIO6 Reload 1 Register (TIO6RL1) <Address:H'0080 0364> I TIO7 Reload 1 Register (TIO7RL1) <Address:H'0080 0374> I TIO8 Reload 1 Register (TIO8RL1) <Address:H'0080 0384> I TIO9 Reload 1 Register (TIO9RL1) <Address:H'0080 0394> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TIO0RL1-TIO9RL1 Note: This register must always be accessed in halfwords. The TIO Reload 1 Registers are used to reload the TIO Counter Registers (TIO0CT-TIO9CT) with data. It is in the following cases that the content of reload 1 register is loaded into the counter:

• When the count value set by reload 0 register underflowed in PWM output mode Writing data to the reload 1 register does not mean that the data is loaded into the counter simultaneously.

10-122 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS <When reset:H'0000> D Bit Name Function R W 0-5 No functions assigned 0 –

6 TIO9PRO (TIO9 Enable Protect) 0: Enables rewrite

7 TIO8PRO (TIO8 Enable Protect) 1: Disables rewrite

8 TIO7PRO (TIO7 Enable Protect)

9 TIO6PRO (TIO6 Enable Protect)

10 TIO5PRO (TIO5 Enable Protect)

11 TIO4PRO (TIO4 Enable Protect)

12 TIO3PRO (TIO3 Enable Protect)

13 TIO2PRO (TIO2 Enable Protect)

14 TIO1PRO (TIO1 Enable Protect)

15 TIO0PRO (TIO0 Enable Protect)

10.4.8 TIO Enable Control Registers

I TIO0-9 Enable Protect Register (TIOPRO) <Address:H'0080 03BC> Note: This register must always be accessed in halfwords. The TIO0-9 Enable Protect Register controls rewriting of the TIO count enable bit described in the next page by enabling or disabling rewrite. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TIO9 TIO8 TIO7 TIO6 TIO5 TIO4 TIO3 TIO2 TIO1 TIO0 PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO

10-123 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS <When reset:H'0000> D Bit Name Function R W 0-5 No functions assigned 0 –

6 TIO9CEN (TIO9 count enable) 0: Stops count

7 TIO8CEN (TIO8 count enable) 1: Enables count

8 TIO7CEN (TIO7 count enable)

9 TIO6CEN (TIO6 count enable)

10 TIO5CEN (TIO5 count enable)

11 TIO4CEN (TIO4 count enable)

12 TIO3CEN (TIO3 count enable)

13 TIO2CEN (TIO2 count enable)

14 TIO1CEN (TIO1 count enable)

15 TIO0CEN (TIO0 count enable)

I TIO0-9 Count Enable Register (TIOCEN) <Address:H'0080 03BE> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TIO9 TIO8 TIO7 TIO6 TIO5 TIO4 TIO3 TIO2 TIO1 TIO0 CEN CEN CEN CEN CEN CEN CEN CEN CEN CEN Note: This register must always be accessed in halfwords. The TIO0-9 Count Enable Register controls operation of TIO counters. To enable the counter in software, enable the relevant TIO0-9 Enable Protect Register for write and set the count enable bit by writing a 1. To stop the counter, enable the TIO0-9 Enable Protect Register for write and reset the count enable bit by writing a 0. In all but continuous mode, when the counter stops due to an occurrence of underflow, the count enable bit is automatically reset to 0. Therefore, what you get by reading the TIO0-9 Count Enable Register is the status that indicates the counter's operating status (active or idle).

10-124 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.4.7 Configuration of the TIO Enable Circuit WR Dn TIOm enable protect (TIOmPRO) WR EN-ON TIOm external enable (TIOmEEN or TIOmENS) TINnS TIOm enable (TIOmCEN) TIO enable control Edge selection F/F F/F F/F Event bus

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10.4.9 Operation in TIO Measure Free-run/Clear Input Modes

(1) Outline of TIO measure free-run/clear input modes In TIO measure free-run/clear input modes, the timer measures a duration of time from when it starts counting till when an external capture signal is entered. An interrupt can be generated by a counter underflow or execution of measure operation. After the timer is enabled (by writing to the enable bit in software), the counter starts counting down synchronously with the count clock. When a capture signal is entered from an external device, the counter value at that point in time is written to the measure register. Especially in measure clear input mode, the counter value is initialized to H'FFFF upon capture, from which the counter starts counting down again. When the counter underflows after reaching the minimum count, it starts counting down from H'FFFF again. In measure free-run input mode, the counter continues counting down even after capture and upon underflow, recycles to H'FFFF, from which it starts counting down again. To stop the counter, disable count by writing to the enable bit in software.

10-126 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.4.8 Typical Operation in Measure Free-run Input Mode Count clock Counter H ’FFFF H ’0000 Enabled (by writing to enable bit) TIO interrupt Measure event (capture) occurs Indeterminate Enable bit Note: This diagram does not show detail timing information . Measure register H ’7000 TIN interrupt by external event input TIO interrupt by underflow H ’9000 H ’7000 H ’9000 Measure event (capture) occurs TIN interrupt by external event input TIN interrupt

10-127 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.4.9 Typical Operation in Measure Clear Input Mode H ’FFFF H ’0000 H ’7000 H ’7000 Count clock Counter Enabled (by writing to enable bit) TIO interrupt Measure event (capture) occurs Indeterminate Enable bit Note: This diagram does not show detail timing information. Measure register TIN interrupt by external event input TIO interrupt by underflow TIN interrupt

10-128 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (2) Precautions to be observed when using TIO measure free-run/clear input modes The following describes precautions to be observed when using TIO measure free-run/clear input modes.

• If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter while at the same time latched into the measure register.

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10.4.10 Operation in TIO Noise Processing Input Mode

In noise processing input mode, the timer detects the status of an input signal that it remained in the same state for over a predetermined time. In noise processing input mode, the counter is started by entering a high or low-level signal from an external device and if the signal remains in the same state for over a predetermined time before the counter underflows, the counter stops after generating an interrupt. If the valid-level signal being applied turns to an invalid level before the counter underflows, the counter temporarily stops counting and when a valid-level signal is entered again, it is reloaded with the initial count and restarts counting. The valid count value is (reload 0 register set value + 1). The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit. An interrupt can be generated by a counter underflow. Figure 10.4.10 Typical Operation in Noise Processing Input Mode H ’FFFF H ’0000 Enabled (by writing to enable bit or by external input) Reload 0 registerH ’A000 External input (noise processing) H ’A000 Valid signal widthInvalidInvalid Disabled by underflow Count clock Counter TIO interrupt Enable bit Note: This diagram does not show detail timing information . TIO interrupt by underflow

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10.4.11 Operation in TIO PWM Output Mode

(1) Outline of TIO PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by external input), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The valid count values are (reload 0 register set value + 1) and (reload 1 register set value + 1). The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output levels change from low to high, or vice versa) at count startup and upon each underflow. An interrupt can be generated when the counter underflows every other time (second time, fourth time, and so on) after being enabled. Note that TIO's PWM output mode does not have the correction function.

10-131 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.4.11 Typical Operation in PWM Output Mode H ’FFFF H ’0000 F/F output Underflow (first time) TIO interrupt by underflow H ’A000 Underflow (second time) Down-count starting from reload 1 register set value H ’(C000-1) Data inverted by underflow Data inverted by enable H ’(A000-1) Reload 1 register H ’C000 Down-count starting from reload 0 register set value Down-count starting from reload 0 register set value H ’A000 PWM output period H ’C000 H ’A000 Enabled (by writing to enable bit or by external input) Reload 0 register Count clock Counter Enable bit Note: This diagram does not show detail timing information . Data inverted by underflow

10-132 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (2) Reload register updates in TIO PWM output mode In PWM output mode, when the timer remains idle, reload 0 and reload 1 registers are updated at the same time data are written to the registers. But when the timer is active, reload 1 register is updated by updating reload 0 register. However, when you read reload 0 and reload 1 registers, the values you get are always the data written to the registers. Figure 10.4.12 PWM Circuit Diagram If you want to rewrite reload 0 and reload 1 registers while the timer is operating, rewrite reload 1 register first and then reload 0 register. In this way, reload 0 and reload 1 registers both are updated synchronously with PWM periods, from which the timer starts operating again. This operation can normally be performed collectively by accessing register addresses wordwise (in 32 bits) beginning with that of reload 1 register. (Data are automatically written to reload 1 and then reload 0 registers in succession.) If you update the reload registers in reverse by updating reload 0 register first and then reload 1 register, only reload 0 register is updated. when you read reload 0 and reload 1 registers, the values you get are always the data written to the registers, and not the reload values being actually used. Note that when updating the PWM period, if the PWM period is terminated before you finished writing to reload 0, the PWM period is not updated in the current period and what you've set is reflected in the next period. Internal bus TIOnRL1 Reload 1 Reload1WR Reload0WR Buffer 16-bit counterPrescaler output F/F TO TIOnRL0 Reload 1 PWM mode control

10-133 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.4.13 Reload 0 and Reload 1 Register Updates in PWM Output Mode (a) When reload register updates take effect in the current period (reflected in the next period) Note: This diagram does not show detail timing information. Count clock Reload 0 register Reload 1 register H ’0001 H ’FFFF H ’1000 H ’7FFF H ’2000 H ’8000 H ’9000 Counter Interrupt by underflow Timing at which reload 1 and reload 0 registers are updated New PWM output period Operation by new reload value written Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (reload 1 data latched) H ’1000 H ’2000 H ’8000 H ’9000 Enlarged view New PWM output periodOld PWM output period F/F output H ’7FFEH ’0000 PWM period latched Reload 1 buffer H ’2000 H ’9000 H ’000 H ’ FFFF H ’1000 H ’0FFF H ’2000 H ’800 H ’9000 (b) When reload register updates take effect in the next period (reflected one period later) H ’1000 H ’2000 H ’8000 H ’9000 H ’0FFEH ’000 H ’2000 H ’9000 Note: This diagram does not show detail timing information. Count clock Reload 0 register Reload 1 register Counter Interrupt by underflow Timing at which reload 1 and reload 0 registers are updated Old PWM output period Operation by old reload value Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (reload 1 data latched) Enlarged view Old PWM output periodOld PWM output period F/F output PWM period latched Reload 1 buffer

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10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function)

(1) Outline of TIO single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. The count value is (reload 0 register set value + 1). (For details about count operation, also refer to Section 10.3.9, "Operation in TOP Single-shot Output Mode (with Correction Function)." (2) Precautions to be observed when using TIO single-shot output mode The following describes precautions to be observed when using TIO single-shot output mode.

• If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops).
• If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled).
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled).
• Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled.

10-135 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.4.14 Typical Operation in TIO Single-shot Output Mode (without Correction Function) H ’FFFF H ’0000 Disabled (by underflow) (Not used) Counts down starting from reload 0 register set value H ’A000 H ’A000 F/F output TIO interrupt by underflow Data inverted by underflow Data inverted by enable Reload 1 register Enabled (by writing to enable bit or by external input) Reload 0 register Count clock Counter Enable bit Note: This diagram does not show detail timing information .

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10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction

Function) (1) Outline of TIO delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload 0 register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an interrupt can be generated when the counter underflows first time and next. The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For details about count operation, also see Section 10.3.10, "Operation in TOP Delayed Single-shot Output Mode (With Correction Function)." (2) Precautions to be observed when using TIO delayed single-shot output mode The following describes precautions to be observed when using TIO delayed single-shot output mode.

• If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops).
• If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled).
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled).
• When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge.

10-137 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.4.15Typical Operation in TIO Deleted Single-shot Output Mode (without Correction Function) H ’FFFF H ’0000 Underflow (first time) Down-count starting from counter set value H ’F000 H ’A000 Underflow (second time) H ’F000 Down-count starting from reload 0 register set value H ’EFFF (Not used) F/F output TIO interrupt by underflow Data inverted by underflow Reload 1 register Enabled (by writing to enable bit or by external input) Reload 0 register Count clock Counter Enable bit Note: This diagram does not show detail timing information . Data inverted by underflow

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10.4.14 Operation in TIO Continuous Output Mode (Without Correction Function)

(1) Outline of TIO continuous output mode In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by external input), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows. The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For details about count operation, also see Section 10.3.11, "Operation in TOP Continuous Output M10.4 TIO (Input/Output-related 16-bit Timer) (2) Precautions to be observed when using TIO continuous output mode The following describes precautions to be observed when using TIO continuous output mode.

• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled).
• When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge.
• Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled.

10-139 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS H ’FFFF H ’0000 H ’E000 H ’A000 H ’E000 H ’DFFF Data inverted by enable H ’DFFF Underflow (first time) Down-count starting from counter set value Underflow (second time) Down-count starting from reload 0 register set value (Not used) F/F output TIO interrupt by underflow Data inverted by underflow Reload 1 register Enabled (by writing to enable bit or by external input) Reload 0 register Count clock Counter Enable bit Note: This diagram does not show detail timing information. Down-count starting from reload 0 register set value Figure 10.4.16Typical Operation in TIO Continuous Output Mode (without Correction Function)

10-140 32170/32174 Group User's Manual (Rev. 2.1)

10.5.1 Outline of TMS

TMS (Timer Measure Small) is an input-related 16-bit timer capable of measuring input pulses in two circuit blocks comprising a total eight channels. The table below shows specifications of TMS. The diagram in the next page shows a block diagram of TMS. Table 10.5.1 Specifications of TMS (Input-related 16-bit Timer)

10.5.2 Outline of TMS Operation

In TMS, when the timer is started by writing to the enable bit in software, the counter starts operating. The counter is a 16-bit up-counter, where when a measure signal is entered from an external device, the counter value is latched into each measure register. The counter stops counting at the same time count is disabled by writing to the enable bit in software. A TIN interrupt can be generated by entering an external measure signal. Also, a TMS interrupt can be generated by a counter overflow. Item Specification Number of channels 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) Counter 16-bit up-counter × 2 Measure register 16-bit measure register × 8 Timer startup Started by writing to enable bit in software Interrupt generation Can be generated by a counter overflow MULTIJUNCTION TIMERS

10-141 32170/32174 Group User's Manual (Rev. 2.1) Figure 10.5.1 Block Diagram of TMS (Input-related 16-bit Timer) MULTIJUNCTION TIMERS S ovf cap3 cap2 cap1 cap0 S S S S TCLK3 TCLK3S TIN12S DRQ3 TIN13S IRQ10 TIN12 TIN13 TIN14STIN14 TIN15STIN15 clk TMS 1 ovf cap3 cap2 cap1 cap0 S S S S S TIN16S DRQ5 TIN17S TIN16 TIN17 TIN18STIN18 TIN19STIN19 DRQ6 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 IRQ10 0 1 2 3 IRQ7 IRQ7 S 3 2 1 0 3 2 1 0 0 1 2 3 Measure register 3 Measure register 2 Measure register 1 Measure register 0 Counter (16 bits) Clock bus Input event bus Output event bus : Selector

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10.5.3 TMS Related Register Map

The diagram below shows a TMS related register map. Figure 10.5.2 TMS Related Register Map H’0080 03C0 D0 D7 D8 D15 H’0080 03C2 H’0080 03C4 H’0080 03C6 TMS0 Measure 2 Register (TMS0MR2) TMS0 Measure 1 Register (TMS0MR1) H’0080 03CA TMS1 Control Register (TMS1CR) H’0080 03C8 TMS0 Control Register (TMS0CR) TMS0 Measure 3 Register (TMS0MR3) TMS0 Measure 0 Register (TMS0MR0) H’0080 03D0 H’0080 03D2 H’0080 03D4 H’0080 03D6 H’0080 03D8 +0 Address +1 AddressAddress TMS Counter (TMS0CT) Note: The registers enclosed in thick frames must always be accessed in halfwords. Blank addresses are reserved. TMS1 Measure 2 Register (TMS1MR2) TMS1 Measure 1 Register (TMS1MR1) TMS1 Measure 3 Register (TMS1MR3) TMS1 Measure 0 Register (TMS1MR0) TMS1 Counter (TMS1CT) MULTIJUNCTION TIMERS

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10.5.4 TMS Control Registers

The TMS control registers are used to select TMS0/1 input events and the counter clock source, as well as control counter startup. Following two TMS control registers are included:

• TMS0 Control Register (TMS0CR)
• TMS1 Control Register (TMS1CR) I TMS0 Control Register (TMS0CR) <Address: H'0080 03CA> <When reset:H'00> D Bit Name Function R W

0 TMS0SS0 0: External input TIN15

(TMS0 measure 0 source selection) 1: Input event bus 0

1 TMS0SS1 0: External input TIN14

(TMS0 measure 1 source selection) 1: Input event bus 1

2 TMS0SS2 0: External input TIN13

(TMS0 measure 2 source selection) 1: Input event bus 2

3 TMS0SS3 0: External input TIN12

(TMS0 measure 3 source selection) 1: Input event bus 3 4,5 TMS0CKS 00: External input TCLK3 (TMS0 clock source selection) 01: Clock bus 0 10: Clock bus 1 11: Clock bus 3

6 No functions assigned 0 –

7 TMS0CEN 0: Count stops

(TMS0 count enable) 1: Count starts TMS0 TMS0 TMS0 TMS0 SS0 SS1 SS2 SS3 MULTIJUNCTION TIMERS

10-144 32170/32174 Group User's Manual (Rev. 2.1) I TMS1 Control Register (TMS1CR) <Address: H'0080 03CB> <When reset:H'00> D Bit Name Function R W

8 TMS1SS0 0: External input TIN19

(TMS1measure 0 source selection) 1: Input event bus 0

9 TMS1SS1 0: External input TIN18

(TMS1 measure 1 source selection) 1: Input event bus 1

10 TMS1SS2 0: External input TIN17

(TMS1 measure 2 source selection) 1: Input event bus 2

11 TMS1SS3 0: External input TIN16

(TMS1 measure 3 source selection) 1: Input event bus 3

12 No functions assigned 0 –

13 TMS1CKS 0: Clock bus 0

(TMS1 clock source selection) 1: Clock bus 3

14 No functions assigned 0 –

15 TMS1CEN 0: Count stops

(TMS1 count enable) 1: Count starts D 8 9 1 01 11 21 31 4 D 1 5 TMS1CKS TMS1CENTMS1 TMS1 TMS1 TMS1 SS0 SS1 SS2 SS3 MULTIJUNCTION TIMERS

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10.5.5 TMS Counter (TMS0CT, TMS1CT)

I TMS0 Counter (TMS0CT) <Address: H'0080 03C0> I TMS1 Counter (TMS1CT) <Address: H'0080 03D0> <When reset: Indeterminate> D Bit Name Function R W 0-15 TMS0CT, TMS1CT 16-bit counter value Note: This register must always be accessed in halfwords. The TMS counters are a 16-bit up-counter, which starts counting when the timer is enabled (by writing to the enable bit in software). The counter can be read on-the-fly. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TMS0CT, TMS1CT MULTIJUNCTION TIMERS

10-146 32170/32174 Group User's Manual (Rev. 2.1)

10.5.6 TMS Measure Registers (TMS0MR3-0, TMS1MR3-0)

I TMS0 Measure 3 Register (TMS0MR3) <Address: H'0080 03C2> I TMS0 Measure 2 Register (TMS0MR2) <Address: H'0080 03C4> I TMS0 Measure 1 Register (TMS0MR1) <Address: H'0080 03C6> I TMS0 Measure 0 Register (TMS0MR0) <Address: H'0080 03C8> I TMS1 Measure 3 Register (TMS1MR3) <Address: H'0080 03D2> I TMS1 Measure 2 Register (TMS1MR2) <Address: H'0080 03D4> I TMS1 Measure 1 Register (TMS1MR1) <Address: H'0080 03D6> I TMS1 Measure 0 Register (TMS1MR0) <Address: H'0080 03D8> Note 1: This register is a read-only register. Note 2: This register can be accessed in either byte or halfword. The TMS measure registers are used to latch counter contents upon event input. The TMS measure registers are a read-only register. <When reset: Indeterminate> D Bit Name Function R W 0-15 TMS0MR3-TMS0MR0 16-bit reload register value – TMS1MR3-TMS1MR0 D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TMS0MR3-0, TMS1MR3-0 MULTIJUNCTION TIMERS

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10.5.7 Operation of TMS Measure Input

(1) Outline of TMS measure input In TMS measure input, the counter starts counting up clock pulses when the timer is actuated by writing to the enable bit in software. When event input is entered to TMS while the timer is operating, the counter value is latched into measure registers 0-3. The timer stops at the same time count is disabled by writing to the enable bit. A TIN interrupt can be generated by entering a measure signal from an external device. Also, when the counter overflows, a TMS interrupt can be generated. Figure 10.5.3 Typical Operation in TMS Measure Input Count clock Counter H ’FFFF H ’0000 Enabled (by writing to enable bit) Measure event 1 occurs Initial value (indeterminate) Enable bit Note: This diagram does not show detail timing information. Measure 0 register H ’8000 Overflow occurs TIN15 interrupt H ’C000 Measure event 0 occurs TMS interrupt by overflow H ’C000 H ’6000 H ’D000 H ’6000 H ’D000 H ’8000 Indeterminate value Measure event 1 occurs Measure event 0 occurs Initial value (indeterminate)Measure 1 register TIN14 interrupt MULTIJUNCTION TIMERS

10-148 32170/32174 Group User's Manual (Rev. 2.1) (2) Precautions to be observed when using TMS measure input The following describes precautions to be observed when using TMS measure input.

• If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter while at the same time latched to the measure register. MULTIJUNCTION TIMERS

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10.6.1 Outline of TML

TML (Timer Measure Large) is an input-related 32-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table below shows specifications of TML. The diagram in the next page shows a block diagram of TML. Table 10.6.1 Specifications of TML (Input-related 32-bit Timer) Item Specification Number of channels 8 channels (2 circuit blocks consisting of 4 channels each, 8 channels in total) Input clock Divided-by-2 frequency of the internal peripheral operating clock (e.g., 10.0 MHz when using 20 MHz internal peripheral operating clock) or clock bus 1 input Counter 32-bit up-counter × 2 Measure register 32-bit measure register × 8 Timer startup Starts counting after leaving reset MULTIJUNCTION TIMERS

10-150 32170/32174 Group User's Manual (Rev. 2.1) Figure 10.6.1 Block Diagram of TML (Input-related 32-bit Timer)

10.6.2 Outline of TML Operation

In TML, the counter starts counting upon deassertion of reset. The counter is a 32-bit up-counter, where when a measure event signal is entered from an external device, the counter value at that point in time is stored in each 32-bit measure register. When reset input is deasserted, the counter starts operating with a divided-by-2 frequency of the internal peripheral clock, and cannot be stopped once it has started. The counter is idle only when the device remains reset. A TIN interrupt can be generated by entering an external measure signal. However, no TML counter overflow interrupts are available. MULTIJUNCTION TIMERS S S S S TIN20S TIN21S TIN20 TIN21 TIN22STIN22 TIN23STIN23 IRQ11 IRQ11 IRQ11 IRQ11 1/2 internal peripheral clock 0 1 2 3 S 3 2 1 0 3 2 1 0 0 1 2 3 clk TML0 cap3 cap2 cap1 cap0 S S S S S TIN30S TIN31S TIN30 TIN31 TIN32STIN32 TIN33STIN33 IRQ18 IRQ18 IRQ18 IRQ18 clk TML1 cap3 cap2 cap1 cap0 S Measure register 3 Measure register 2 Measure register 1 Measure register 0 Counter (32 bits) Clock bus Input event bus Output event bus : Selector Measure register 3 Measure register 2 Measure register 1 Measure register 0 Counter (32 bits)

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10.6.3 TML Related Register Map

The diagram below shows a TML related register map. Figure 10.6.2 TML Related Register Map MULTIJUNCTION TIMERS H’0080 03E0 D0 D7 D8 D15 H’0080 03E2 TML0 Counter, High (TML0CTH) H’0080 03EA TML0 Counter, Low (TML0CTL) H’0080 03F0 H’0080 03F2 H’0080 03F4 H’0080 03F6 TML0 Measure 3 Register, Low (TML0MR3L) H’0080 03F8 H’0080 03FA H’0080 03FC H’0080 03FE TML0 Measure 3 Register, High (TML0MR3H) H’0080 0FE0 H’0080 0FE2 H’0080 0FEA H’0080 0FF0 H’0080 0FF2 H’0080 0FF4 H’0080 0FF6 H’0080 0FF8 H’0080 0FFA H’0080 0FFC H’0080 0FFE TML0 Control Register (TML0CR) +0 Address +1 AddressAddress Note: The registers enclosed in thick frames must always be accessed in halfwords. Blank addresses are reserved. TML0 Measure 2 Register, Low (TML0MR2L) TML0 Measure 2 Register, High (TML0MR2H) TML0 Measure 1 Register, Low (TML0MR1L) TML0 Measure 1 Register, High (TML0MR1H) TML0 Measure 0 Register, Low (TML0MR0L) TML0 Measure 0 Register, High (TML0MR0H) TML1 Counter, High (TML1CTH) TML1 Counter, Low (TML1CTL) TML1 Measure 3 Register, Low (TML1MR3L) TML1 Measure 3 Register, High (TML1MR3H) TML1 Control Register (TML1CR) TML1 Measure 2 Register, Low (TML1MR2L) TML1 Measure 2 Register, High (TML1MR2H) TML1 Measure 1 Register, Low (TML1MR1L) TML1 Measure 1 Register, High (TML1MR1H) TML1 Measure 0 Register, Low (TML1MR0L) TML1 Measure 0 Register, High (TML1MR0H)

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10.6.4 TML Control Registers

I TML0 Control Register (TML0CR) <Address: H'0080 03EB> The TML0 Control Register is used to select TML0 input event and the counter clock source. Note: The counter can be written to normally only when the selected clock source is a 1/2 internal peripheral clock. When using any other clock source, you cannot write to the counter normally. Under this condition, do not write to the counter. <When reset:H'00> D Bit Name Function R W

8 TML0SS0 0: External input TIN23

(TML0 measure 0 source selection) 1: Input event bus 0

9 TML0SS1 0: External input TIN22

(TML0 measure 1 source selection) 1: Input event bus 1

10 TML0SS2 0: External input TIN21

(TML0 measure 2 source selection) 1: Input event bus 2

11 TML0SS3 0: External input TIN20

(TML0 measure 3 source selection) 1: Input event bus 3 12-14 No functions assigned 0 –

15 TML0CKS 0: 1/2 internal peripheral clock

(TML0 clock source selection) 1: Clock bus 1 D 8 9 1 01 11 21 31 4 D 1 5 TML0SS0 TML0SS1 TML0SS2 TML0SS3 TML0CKS MULTIJUNCTION TIMERS

10-153 32170/32174 Group User's Manual (Rev. 2.1) I TML1 Control Register (TML1CR) <Address: H'0080 0FEB> D 8 9 1 01 11 21 31 4 D 1 5 TML1SS0 TML1SS1 TML1SS2 TML1SS3 TML1CKS <When reset:H'00> D Bit Name Function R W

8 TML1SS0 0: External input TIN33

(TML1 measure 0 source selection) 1: Input event bus 0

9 TML1SS1 0: External input TIN32

(TML1 measure 1 source selection) 1: Input event bus 1

10 TML1SS2 0: External input TIN31

(TML1 measure 2 source selection) 1: Input event bus 2

11 TML1SS3 0: External input TIN30

(TML1 measure 3 source selection) 1: Input event bus 3 12-14 No functions assigned 0 –

15 TML1CKS 0: 1/2 internal peripheral clock

(TML1 clock source selection) 1: Clock bus 1 The TML1 Control Register is used to select TML1 input event and the counter clock source. Note: The counter can be written to normally only when the selected clock source is a 1/2 internal peripheral clock. When using any other clock source, you cannot write to the counter normally. Under this condition, do not write to the counter. MULTIJUNCTION TIMERS

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10.6.5 TML Counters

I TML0 Counter, High (TML0CTH) <Address: H'0080 03E0> I TML0 Counter, Low (TML0CTL) <Address: H'0080 03E2> Note: This register must always be accessed in words (32 bits) beginning with the address of TML0CTH. The TML0 Counter is a 32-bit up-counter, which starts counting upon deassertion of reset. The TML0CTH register accommodates the 16 high-order bits, and the TML0CTL register accommodates the 16 low-order bits of the 32-bit counter. The counter can be read on-the-fly. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML0CTH (16 high-order bits) D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML0CTL (16 low-order bits) <When reset: Indeterminate> D Bit Name Function R W 0-15 TML0CTH 32-bit counter value (16 high-order bits) TML0CTL 32-bit counter value (16 low-order bits) MULTIJUNCTION TIMERS

10-155 32170/32174 Group User's Manual (Rev. 2.1) I TML1 Counter, High (TML1CTH) <Address: H'0080 0FE0> I TML1 Counter, Low (TML1CTL) <Address: H'0080 0FE2> Note: This register must always be accessed in words (32 bits) beginning with the address of TML1CTH. The TML1 Counter is a 32-bit up-counter, which starts counting upon deassertion of reset. The TML1CTH register accommodates the 16 high-order bits, and the TML1CTL register accommodates the 16 low-order bits of the 32-bit counter. The counter can be read on-the-fly. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML1CTH (16 high-order bits) D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML1CTL (16 low-order bits) <When reset: Indeterminate> D Bit Name Function R W 0-15 TML1CTH 32-bit counter value (16 high-order bits) TML1CTL 32-bit counter value (16 low-order bits) MULTIJUNCTION TIMERS

10-156 32170/32174 Group User's Manual (Rev. 2.1)

10.6.6 TML Measure Registers

I TML0 Measure 3 Register (TML0MR3H) <Address: H'0080 03F0> I TML0 Measure 3 Register (TML0MR3L) <Address: H'0080 03F2> I TML0 Measure 2 Register (TML0MR2H) <Address: H'0080 03F4> I TML0 Measure 2 Register (TML0MR2L) <Address: H'0080 03F6> I TML0 Measure 1 Register (TML0MR1H) <Address: H'0080 03F8> I TML0 Measure 1 Register (TML0MR1L) <Address: H'0080 03FA> I TML0 Measure 0 Register (TML0MR0H) <Address: H'0080 03FC> I TML0 Measure 0 Register (TML0MR0L) <Address: H'0080 03FE> Note 1: These registers are a read-only register. Note 2: These registers must always be accessed in words (32 bits) beginning with a word boundary. The TML0 Measure Registers are used to latch counter contents upon event input. The TML0 Measure Registers are configured with 32 bits, the TML0MR3H-0H accommodating the 16 high- order bits, and the TML0MR3L-0L accommodating the 16 low-order bits. The TML0 Measure Registers are a read-only register. These registers must always be accessed in words (32 bits) beginning with a word boundary. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML0MR3H-TML0MR0H (16 high-order bits) D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML0MR3L-TML0MR0L (16 low-order bits) <When reset: Indeterminate> D Bit Name Function R W 0-15 TML0MR3H-0H 32-bit counter value (16 high-order bits) – TML0MR3L-0L 32-bit counter value (16 low-order bits) MULTIJUNCTION TIMERS

10-157 32170/32174 Group User's Manual (Rev. 2.1) I TML1 Measure 3 Register (TML1MR3H) <Address: H'0080 0FF0> I TML1 Measure 3 Register (TML1MR3L) <Address: H'0080 0FF2> I TML1 Measure 2 Register (TML1MR2H) <Address: H'0080 0FF4> I TML1 Measure 2 Register (TML1MR2L) <Address: H'0080 0FF6> I TML1 Measure 1 Register (TML1MR1H) <Address: H'0080 0FF8> I TML1 Measure 1 Register (TML1MR1L) <Address: H'0080 0FFA> I TML1 Measure 0 Register (TML1MR0H) <Address: H'0080 0FFC> I TML1 Measure 0 Register (TML1MR0L) <Address: H'0080 0FFE> Note 1: These registers are a read-only register. Note 2: These registers must always be accessed in words (32 bits) beginning with a word boundary. The TML1 Measure Registers are used to latch counter contents upon event input. The TML1 Measure Registers are configured with 32 bits, the TML1MR3H-0H accommodating the 16 high- order bits, and the TML1MR3L-0L accommodating the 16 low-order bits. The TML1 Measure Registers are a read-only register. These registers must always be accessed in words (32 bits) beginning with a word boundary. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML1MR3H-TML1MR0H (16 high-order bits) D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML1MR3L-TML1MR0L (16 low-order bits) <When reset: Indeterminate> D Bit Name Function R W 0-15 TML1MR3H-0H 32-bit counter value (16 high-order bits) – TML1MR3L-0L 32-bit counter value (16 low-order bits) MULTIJUNCTION TIMERS

10-158 32170/32174 Group User's Manual (Rev. 2.1) Counter (32 bits) H ’FFFF FFFF H ’0000 0000 Reset H ’8000 0000 H ’C000 0000 H ’8000 0000 H ’C000 0000 H ’6000 0000 H ’D000 0000 H ’6000 0000 H ’D000 0000 Count clock Enabled (by deassertion of reset) Measure event 1 occurs Initial value (indeterminate) Note: This diagram does not show detail timing information. Measure 0 register Overflow occurs TIN23 interrupt Measure event 0 occurs Indeterminate value Measure event 1 occurs Measure event 0 occurs Measure 1 register TIN22 interrupt Initial value (indeterminate)

10.6.7 Operation of TML Measure Input

(1) Outline of TML measure input In TML measure input, the counter starts counting up clock pulses upon deassertion of reset. When event input is entered to measure registers 0-3, the counter value is latched into the measure registers. A TIN interrupt can be generated by entering an external measure signal. (No TML counter overflow interrupts are available.) Figure 10.6.3 Typical Operation in TML Measure Input MULTIJUNCTION TIMERS

10-159 32170/32174 Group User's Manual (Rev. 2.1) (2) Precautions to be observed when using TML measure input The following describes precautions to be observed when using TML measure input.

• If measure event input and write to the counter occur simultaneously in the same clock period, the write value is set in the counter, whereas the up-count value (before being rewritten) is latched to the measure register.
• If the timer operates with any clock other than the 1/2 internal peripheral clock while clock bus 1 is selected for the count clock, the counter cannot be written to normally. Therefore, when operating with any clock other than the 1/2 internal peripheral clock, do not write to the counter.
• If the timer operates with any clock other than the 1/2 internal peripheral clock while clock bus 1 is selected for the count clock, the captured value is one that leads the actual counter value by one clock period. However, during the 1/2 internal peripheral clock interval from the count clock, this problem does not occur and the counter value is captured at exact timing. The diagram below shows the relationship between counter operation and the valid data that can be captured. MULTIJUNCTION TIMERS

When 1/2 internal peripheral clock is selected 1/2 internal peripheral clock Capture Counter BA C When clock bus 1 is selected 1/2 internal peripheral clock Count clock Capture BC D F Figure 10.6.4 Mistimed Counter Value and Captured Value

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10.7.1 Outline of TID

TID (Timer Input Derivation) is an input-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software:

• Fixed period count mode
• Event count mode
• Multiply-by-4 event count mode The table below shows specifications of TID. The diagram in the next page shows a block diagram of TID. Table 10.7.1 Specifications of TID (Input-related 16-bit Timer) Item Specification Number of channels 3 channels Counter 16-bit up/down-counter Reload register 16-bit reload register Timer startup Started by writing to enable bit in software Mode selection <Input mode>
• Fixed period count mode
• Event count mode
• Multiply-by-4 event count mode Interrupt generation Can be generated by a counter underflow and overflow MULTIJUNCTION TIMERS

10-161 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.7.1 Block Diagram of TID (Input-related 16-bit Timer) Up/down-counter TID0 IRQ14 PRS3 TIN24 TIN25 S 1/2 internal peripheral clock Built-in edge control circuitCLK1 CLK2 TOD0_0 - 7 Reload register clk TID1 AD1TRG (To A-D1 converter) PRS4 TIN26 TIN27 S CLK1 CLK2 TOD1_0 - 7 clk TOD1_0 - TOD1_7 Enable signal IRQ15 PRS5 TOM0_0 - TOM0_7 Enable signal IRQ17 PRS3 - 5 : Prescaler 1/2 internal peripheral clock Up/down-counter Built-in edge control circuit Reload register TID2 S CLK1 CLK2 TOM0_0 - 7 clk Up/down-counter Built-in edge control circuit Reload register TIN28 TIN29 1/2 internal peripheral clock

10-162 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.7.2 TID Related Register Map

10.7.2 TID Related Register Map

The diagram below shows a TID related register map. Address D0 D7 +0 Address +1 Address D8 D15 Note: The registers enclosed in thick frames must always be accessed in halfwords. H’0080 078C H’0080 0B8E H’0080 0BD0 H’0080 0B8C H’0080 0CD0 H’0080 0C8C H’0080 0C8E Blank addresses are reserved. TID0 Counter (TID0CT) TID0 Reload Register (TID0RL) Prescaler Register 3 (PRS3) TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) H’0080 078E H’0080 07D0 TID1 Counter (TID1CT) TID1 Reload Register (TID1RL) Prescaler Register 4 (PRS4) TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) TID2 Counter (TID2CT) TID2 Reload Register (TID2RL) Prescaler Register 5 (PRS5) TID2 Control & Prescaler 5 Enable Register (TID2PRS5EN)

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10.7.3 TID Control &Prescaler Enable Registers

I TID0 Control &Prescaler 3 Enable Register (TID0PRS3EN) <Address: H'0080 07D1> D 8 9 1 01 11 21 31 4 D 1 5 TID0M TID0CEN PRS3EN <When reset : H'00> D Bit Name Function R W 9, 10 TID0M 0X : Fixed period count mode (TID0 operation mode selection) 10 : Multiply-by-4 event count mode 11 : Event count mode

11 TID0CEN 0 : Count stops

(TID0 count enable) 1 : Count starts 12 - 14 No functions assigned 0 —

15 PRS3EN 0 : Count stops

(Prescaler 3 enable) 1 : Count starts Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. The TID0 Control & Prescaler 3 Enable Register selects TID0 operation mode (Fixed period count mode, Event count mode, or Multiply-by-4 event count mode) and controls prescaler 3 startup.

10-164 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TID1 Control &Prescaler 4 Enable Register (TID1PRS4EN) <Address: H'0080 0BD1> D 8 9 1 01 11 21 31 4 D 1 5 TID1M TID1CEN TID1ENO PRS4EN <When reset : H'00> D Bit Name Function R W 9, 10 TID1M 0X : Fixed period count mode (TID1 operation mode selection) 10 : Multiply-by-4 event count mode 11 : Event count mode

11 TID1CEN 0 : Count stops

(TID1 count enable) 1 : Count starts

13 TID1ENO 0 : Disables enable output to TOD1_0-7

(TID1 enable output enable) 1 : Enables enable output to TOD1_0-7

15 PRS4EN 0 : Count stops

(Prescaler 4 enable) 1 : Count starts Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. The TID1 Control & Prescaler 4 Enable Register selects TID1 operation mode (Fixed period count mode, Event count mode, or Multiply-by-4 event count mode) and controls prescaler 4 startup.

10-165 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TID2 Control &Prescaler 5 Enable Register (TID2PRS5EN) <Address: H'0080 0CD1> D 8 9 1 01 11 21 31 4 D 1 5 TID2M TID2CEN TID2ENO PRS5EN <When reset : H'00> D Bit Name Function R W 9, 10 TID2M 0X : Fixed period count mode (TID2 operation mode selection) 10 : Multiply-by-4 event count mode 11 : Event count mode

11 TID2CEN 0 : Count stops

(TID2 count enable) 1 : Count starts

13 TID2ENO 0 : Disables enable output to TOM0_0-7

(TID2 enable output enable) 1 : Enables enable output to TOM0_0-7

15 PRS5EN 0 : Count stops

(Prescaler 5 enable) 1 : Count starts Note: Always make sure the counter has stopped and is idle before setting or changing operation modes. The TID2 Control & Prescaler 5 Enable Register selects TID2 operation mode (Fixed period count mode, Event count mode, or Multiply-by-4 event count mode) and controls prescaler 5 startup.

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10.7.4 TID Counters (TID0CT, TID1CT, TID2CT)

I TID0 Counter (TID0CT) <Address: H'0080 078C> I TID1 Counter (TID1CT) <Address: H'0080 0B8C> I TID2 Counter (TID2CT) <Address: H'0080 0C8C> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TID0CT, TID1CT, TID2CT <When reset : Indeterminate> D Bit Name Function R W 0 - 15 TID0CT, TID1CT, TID2CT 16-bit counter value Note: This register must always be accessed in halfwords. The TID counters are a 16-bit up/down-counter. After the timer is enabled (by writing to the enable bit in software), the counter starts counting synchronously with the count clock.

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10.7.5 TID Reload Registers (TID0RL, TID1RL, TID2RL)

I TID0 Reload Register (TID0RL) <Address: H'0080 078E> I TID1 Reload Register (TID1RL) <Address: H'0080 0B8E> I TID2 Reload Register (TID2RL) <Address: H'0080 0C8E> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TID0RL, TID1RL, TID2RL <When reset : Indeterminate> D Bit Name Function R W 0 - 15 TID0RL, TID1RL, TID2RL 16-bit reload register value Note: This register must always be accessed in halfwords. The TID reload registers are used to reload the TID counter registers (TID0CT, TID1CT, or TID2CT) with data. It is in the following cases that the content of the reload register is loaded into the counter:

• When the counter underflowed in fixed period count mode
• When the counter is enabled in fixed period count mode Writing data to the reload register does not mean that the data is loaded into the counter simultaneously.

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10.7.6 Outline of Each Mode of TID

Each mode of TID is outlined below. TID modes can be selected from the following, only one at a time: (1) Fixed period count mode In fixed period count mode, the timer uses a reload register to generate an interrupt at intervals of (reload register set value + 1). When after setting the reload register (initial value being indeterminate), the timer is enabled (by writing to the enable bit in software), it loads the content of the reload register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clockpulses and when it underflows after reaching the minimum count, the counter is reloaded with the content of the reload register again and continues counting. To stop the counter, disable count by writing to the enable bit. Also, an interrupt can be generated each time the counter underflows. The valid count value is the (reload register set value + 1). Figure 10.7.3 Typical Operation in TID Fixed Period Count Mode MULTIJUNCTION TIMERS H ’FFFF H ’0000 H ’E000 H ’E000 H ’DFFF H ’DFFF Enable- synchronized write H ’E000 Underflow (first time) TID0 interrupt by underflow Underflow (second time) Down-count starting from reload register set value Enabled (by writing to enable bit) Reload register Count clock Counter Enable bit Note: This diagram does not show detail timing information . Down-count starting from reload register set value Down-count starting from reload register set value

10-169 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (2) Event count mode In event count mode, the timer uses an external input signal (TIN24, TIN26, or TIN28) as the clock source with which to operate the counter. Note: TIN25, TIN27, and TIN29 cannot be used as the clock source. By detecting rising and falling edges of the external input signal (TIN24, TIN26, or TIN28), the timer generates clock pulses synchronized to the internal clock. When after setting the counter, the timer is enabled (by writing to the enable bit in software), the counter starts counting up from the set count value synchronously with the generated clock. An interrupt can be generated by a counter overflow. To stop the counter, disable count by writing to the enable bit in software or fix the external input signal high or low. Figure 10.7.4 Typical Operation in TID Event Count Mode (Basic Operation) Figure 10.7.5 Typical Operation in TID Event Count Mode (when Overflow Occurs) TIN24 Counter value7FFF 8000 8001 8002 8003 8004 TIN24 FFFE FFFF 0000 0001 0002 0003 TID interrupt by overflow FFFDCounter value

10-170 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (3) Multiply-by-4 event count mode In multiply-by-4 event count mode, the timer uses two external input signals in pairs (TIN24 and TIN25, TIN26 and TIN27, or TIN28 and TIN29) as the clock sources with which to operate the counter. The count direction is switched between up-count and down-count depending on the status of the two input signals. The two externally sourced signals both are sampled to detect rising and falling edges as the timer generates clock pulses synchronized to the internal clock. When after setting the counter, the timer is enabled (by writing to the enable bit in software), the counter starts counting up synchronously with the generated clock. For details on whether the counter counts up or counts down, see Table 10.7.2 below. An interrupt can be generated by a counter overflow and/or underflow. To stop the counter, disable count by writing to the enable bit in software or fix the external input signals high or low. Table 10.7.2 Count Direction during Multiply-by-4 Event Count Mode TIN24 (TIN26, TIN28) TIN25 (TIN27, TIN29) Input H H L L H L L H Up-count Down-count Count Direction

10-171 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.7.6 Up/Down Count Operation (Switchover Timing) Figure 10.7.7 Up/Down Count Operation (Count Enabled and Disabled) TIN24 TIN25 Up-count Down-count 8000 8001 8002 8001 8000 8003 7FFE 8003Counter value Counter 80027FFF7FFE 7FFF 7FFE Switched over 8000 8001 80007FFF7FFE Timer enable Count disabled Count enabled 7FFF Enable TIN24 TIN25 8001 7FFE Counter value Counter Switched over Up-count Down-count Count disabled Count disabled Count enabled

10-172 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.7.8 Up/Down Count Operation (Interrupt Timing) TID Interrupt FFFF 0000 0001 0000 FFFF00020001FFFEFFFD FFFE FFFD TIN24 TIN25 Up-count Down-count FFFF 0000 Counter value Counter Switched over

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10.8 TOD (Output-related 16-bit Timer)

10.8.1 Outline of TOD

TOD (Timer Output Derivation) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software. This timer is a variation of TIO, with TIO input modes removed. <Output modes without correction function>

• PWM output mode
• Single-shot output mode
• Delayed single-shot output mode
• Continuous output mode The table below shows specifications of TOD. The diagram in the next page shows a block diagram of TOD. Table 10.8.1 Specifications of TOD (Output-related 16-bit Timer) Item Specification Number of channels 16 channels (two circuit blocks consisting of 8 channels each, 16 channels in total) Counter 16-bit down-counter × 2 Reload register 16-bit reload register × 2 Timer startup TOD0 : Started by writing to enable bit in software TOD1 : Started by writing to enable bit in software or by TID1 timer underflow/overflow signal Mode selection <Output modes without correction function>
• PWM output mode
• Single-shot output mode
• Delayed single-shot output mode
• Continuous output mode Interrupt generation Can be generated by a counter underflow

10-174 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.8.1 Block Diagram of TOD (Output-related 16-bit Timer) clk udfTOD0_0 clk udfTOD0_1 clk udfTOD0_2 clk udfTOD0_3 clk udfTOD0_4 clk udfTOD0_5 clk udfTOD0_6 clk udfTOD0_7 F/F21 F/F22 F/F23 F/F24 F/F25 F/F26 F/F27 F/F28 F/FPRS3, 4 IRQ13 TO 21 TO 22 TO 23 TO 24 TO 25 TO 26 TO 27 TO 28 PRS3 clk udfTOD1_0 clk udfTOD1_1 clk udfTOD1_2 clk udfTOD1_3 clk udfTOD1_4 clk udfTOD1_5 clk udfTOD1_6 clk udfTOD1_7 F/F29 F/F30 F/F31 F/F32 F/F33 F/F34 F/F35 F/F36 IRQ16 TO 29 TO 30 TO 31 TO 32 TO 33 TO 34 TO 35 TO 36 PRS4 en en en en en en en en clk udfTID1 ovf IRQ15 AD1TRG (To A-D1 converter)CLK1 CLK2 TIN26 TIN27 : Prescaler : Output flip-flop 1/2 internal peripheral clock 1/2 internal peripheral clock clk udfTID0 ovf IRQ14CLK1 CLK2 TIN24 TIN25

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10.8.2 Outline of Each Mode of TOD

Each mode of TOD is outlined below. For each TOD channel, only one of the following modes can be selected. (1) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock, letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The F/F output waveform in PWM output mode is inverted at count startup and upon each underflow. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). An interrupt can be generated when the counter underflows every other time (second time, fourth time, and so on) after being enabled. (2) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt can be generated when the counter underflows.

10-176 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (3) Delayed single-shot output mode (without correction function) In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload 0 register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (first set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an interrupt can be generated when the counter underflows first time and next. (4) Continuous output mode (without correction function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows.

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10.8.3 TOD Related Register Map

The diagram below shows a TOD related register map. Figure 10.8.2 TOD Related Register Map (1/3) Address D0 D7 +0 Address +1 Address D8 D15 Note: The registers enclosed in thick frames must always be accessed in halfwords. H’0080 0790 H’0080 0798 H’0080 07A0 H’0080 0794 H’0080 07AA H’0080 07A4 H’0080 07A6 Blank addresses are reserved. TOD0_0 Counter (TOD00CT) H’0080 0792 TID0_1 Counter (TOD01CT) TOD0_0 Reload 1 Register (TOD00RL1) H’0080 0796 TOD0_0 Reload 0 Register (TOD00RL0) H’0080 079C TID0_2 Counter (TOD02CT) TOD0_1 Reload 1 Register (TOD01RL1) H’0080 079E TOD0_1 Reload 0 Register (TOD01RL0) H’0080 079A H’0080 07A8 TID0_3 Counter (TOD03CT) TOD0_2 Reload 1 Register (TOD02RL1) TOD0_2 Reload 0 Register (TOD02RL0) H’0080 07A2 H’0080 07AC H’0080 07AE H’0080 07B0 H’0080 07B2 H’0080 07B4 H’0080 07B6 H’0080 07B8 H’0080 07BA H’0080 07BC H’0080 07BE TOD0_3 Reload 1 Register (TOD03RL1) TOD0_3 Reload 0 Register (TOD03RL0) TID0_4 Counter (TOD04CT) TOD0_4 Reload 1 Register (TOD04RL1) TOD0_4 Reload 0 Register (TOD04RL0) TID0_5 Counter (TOD05CT) TOD0_5 Reload 1 Register (TOD05RL1) TOD0_5 Reload 0 Register (TOD05RL0)

10-178 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.8.3 TOD Related Register Map (2/3) Address D0 D7 +0 Address +1 Address D8 D15 Note 1: Prescaler Register 3 is shared with TOD0_0-7 and TID0, and TID0 Control & Prescaler 3 Enable Register is used in TID0 control. Note 2: The registers enclosed in thick frames must always be accessed in halfwords. H’0080 07C0 H’0080 07C8 H’0080 07D0 H’0080 07C4 H’0080 07DA H’0080 07D4 H’0080 07D6 Blank addresses are reserved. TOD0_6 Counter (TOD06CT) H’0080 07C2 TID0_7 Counter (TOD07CT) Prescaler Register 3 (PRS3) TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) TOD0_6 Reload 1 Register (TOD06RL1) H’0080 07C6 TOD0_6 Reload 0 Register (TOD06RL0) H’0080 07CC TOD0_7 Reload 1 Register (TOD07RL1) H’0080 07CE TOD0_7 Reload 0 Register (TOD07RL0) H’0080 07CA H’0080 07D8 H’0080 07D2 H’0080 07DC H’0080 07DE H’0080 0B90 H’0080 0B92 H’0080 0B94 H’0080 0B96 H’0080 0B98 H’0080 0B9A H’0080 0B9C H’0080 0B9E H’0080 0BA0 H’0080 0BA2 H’0080 0BA4 H’0080 0BA6 (Note 1) TOD0 Interrupt Status Register (TOD0IST) TOD0 Interrupt Mask Register (TOD0IMA) F/F Protect Register 2 (FFP2) F/F Data Register 2 (FFD2) TOD0 Enable Protect Register (TOD0PRO) TOD0 Control Register (TOD0CR) TOD0 Count Enable Register (TOD0CEN) H’0080 0BA8 H’0080 0BAA H’0080 0BAC H’0080 0BAE TOD1_0 Counter (TOD10CT) TID1_1 Counter (TOD11CT) TOD1_0 Reload 1 Register (TOD10RL1) TOD1_0 Reload 0 Register (TOD10RL0) TOD1_1 Reload 1 Register (TOD11RL1) TOD1_1 Reload 0 Register (TOD11RL0) TOD1_2 Counter (TOD12CT) TID1_3 Counter (TOD13CT) TOD1_2 Reload 1 Register (TOD12RL1) TOD1_2 Reload 0 Register (TOD12RL0) TOD1_3 Reload 1 Register (TOD13RL1) TOD1_3 Reload 0 Register (TOD13RL0)

10-179 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.8.4 TOD Related Register Map (3/3) Address D0 D7 +0 Address +1 Address D8 D15 Note 1: Prescaler Register 3 is shared with TOD0_0-7 and TID0, and TID0 Control & Prescaler 3 Enable Register is used in TID0 control. Note 2: The registers enclosed in thick frames must always be accessed in halfwords. H’0080 0BB0 H’0080 0BB8 H’0080 0BC0 H’0080 0BB4 H’0080 0BCA H’0080 0BC4 H’0080 0BC6 Blank addresses are reserved. TOD1_4 Counter (TOD14CT) H’0080 0BB2 TOD1_5 Counter (TOD15CT) Prescaler Register 4 (PRS4) TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) TOD1_4 Reload 1 Register (TOD14RL1) H’0080 0BB6 TOD1_4 Reload 0 Register (TOD14RL0) H’0080 0BBC TOD1_6 Counter (TOD16CT) TOD1_5 Reload 1 Register (TOD15RL1) H’0080 0BBE TOD1_5 Reload 0 Register (TOD15RL0) H’0080 0BBA H’0080 0BC8 TOD1_7 Counter (TOD17CT) TOD1_6 Reload 1 Register (TOD16RL1) TOD1_6 Reload 0 Register (TOD16RL0) H’0080 0BC2 H’0080 0BCC H’0080 0BCE H’0080 0BD0 H’0080 0BD2 H’0080 0BD4 H’0080 0BD6 H’0080 0BD8 H’0080 0BDA H’0080 0BDC H’0080 0BDE TOD1_7 Reload 1 Register (TOD17RL1) TOD1_7 Reload 0 Register (TOD17RL0) (Note 1) TOD1 Interrupt Status Register (TOD1IST) TOD1 Interrupt Mask Register (TOD1IMA) F/F Protect Register 3 (FFP3) F/F Data Register 3 (FFD3) TOD1 Enable Protect Register (TOD1PRO) TOD1 Control Register (TOD1CR) TOD1 Count Enable Register (TOD1CEN)

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10.8.4 TOD Control Registers (TOD0CR)

I TOD0 Control Registers (TOD0CR) <Address: H'0080 07DA> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOD00M TOD01M TOD02M TOD03M TOD04M TOD05M TOD06M TOD07M <When reset : H'0000> D Bit Name Function R W 0, 1 TOD00M 00 : Single-shot output mode (TOD0_0 operation mode selection) 01 :Delayed single-shot output mode 2, 3 TOD01M 10 : Continuous output mode (TOD0_1 operation mode selection) 11 : PWM output mode 4, 5 TOD02M (TOD0_2 operation mode selection) 6, 7 TOD03M (TOD0_3 operation mode selection) 8, 9 TOD04M (TOD0_4 operation mode selection) 10, 11 TOD05M (TOD0_5 operation mode selection) 12, 13 TOD06M (TOD0_6 operation mode selection) 14, 15 TOD07M (TOD0_7 operation mode selection) The TOD0 Control Register is used to select TOD0_0-7 operation modes (PWM output, single-shot output, delayed single-shot output, or continuous output mode).

10-181 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TOD1 Control Registers (TOD1CR) <Address: H'0080 0BDA> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOD10M TOD11M TOD12M TOD13M TOD14M TOD15M TOD16M TOD17M <When reset : H'0000> D Bit Name Function R W 0, 1 TOD10M 00 : Single-shot output mode (TOD1_0 operation mode selection) 01 :Delayed single-shot output mode 2, 3 TOD11M 10 : Continuous output mode (TOD1_1 operation mode selection) 11 : PWM output mode 4, 5 TOD12M (TOD1_2 operation mode selection) 6, 7 TOD13M (TOD1_3 operation mode selection) 8, 9 TOD14M (TOD1_4 operation mode selection) 10, 11 TOD15M (TOD1_5 operation mode selection) 12, 13 TOD16M (TOD1_6 operation mode selection) 14, 15 TOD17M (TOD1_7 operation mode selection) The TOD1 Control Register is used to select TOD1_0-7 operation modes (PWM output, single-shot output, delayed single-shot output, or continuous output mode).

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10.8.5 TOD Counters

I TOD0_0 Counter (TOD00CT) <Address: H'0080 0790> I TOD0_1 Counter (TOD01CT) <Address: H'0080 0798> I TOD0_2 Counter (TOD02CT) <Address: H'0080 07A0> I TOD0_3 Counter (TOD03CT) <Address: H'0080 07A8> I TOD0_4 Counter (TOD04CT) <Address: H'0080 07B0> I TOD0_5 Counter (TOD05CT) <Address: H'0080 07B8> I TOD0_6 Counter (TOD06CT) <Address: H'0080 07C0> I TOD0_7 Counter (TOD07CT) <Address: H'0080 07C8> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOD00CT - TOD07CT <When reset : Indeterminate> D Bit Name Function R W 0 - 15 TOD00CT - TOD07CT 16-bit counter value W = : Write to this register is accepted in all but PWM output mode. Note: This register must always be accessed in halfwords. The TOD0 Counter is a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software), it starts counting synchronously with the count clock. During PWM output mode, this counter is disabled against write.

10-183 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TOD1_0 Counter (TOD10CT) <Address: H'0080 0B90> I TOD1_1 Counter (TOD11CT) <Address: H'0080 0B98> I TOD1_2 Counter (TOD12CT) <Address: H'0080 0BA0> I TOD1_3 Counter (TOD13CT) <Address: H'0080 0BA8> I TOD1_4 Counter (TOD14CT) <Address: H'0080 0BB0> I TOD1_5 Counter (TOD15CT) <Address: H'0080 0BB8> I TOD1_6 Counter (TOD16CT) <Address: H'0080 0BC0> I TOD1_7 Counter (TOD17CT) <Address: H'0080 0BC8> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOD10CT - TOD17CT <When reset : Indeterminate> D Bit Name Function R W 0 - 15 TOD10CT - TOD17CT 16-bit counter value W = : Write to this register is accepted in all but PWM output mode. Note: This register must always be accessed in halfwords. The TOD1 Counter is a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it starts counting synchronously with the count clock. During PWM output mode, this counter is disabled against write.

10-184 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (1) TOD timer counter write enable/disable conditions Whether TOD timer counter is enabled for or disabled against write is determined depending on a combination of TOD timers and a combination of their operation modes. These counter write enable/disable conditions are described below. Also, Figure 10.8.5 schematically shows a TOD0/TOD1 counter write circuit configuration. (a) Table 10.8.2 shows the relationship of each timer in cases where writing to the counter is enabled or disabled by a combination of timers. Whether writing to the counter in software is enabled or disabled depends on a combination of Table 10.8.2 Relationship of Each Timer Target timer Related timer TOD0-2 TOD0-1 TOD0-4 TOD0-2 TOD0-6 TOD0-3 TOD1-2 TOD1-1 TOD1-4 TOD1-2 TOD1-6 TOD1-3 Table 10.8.3 Behavior by a Combination of Timer Operation Modes Operation mode Operation mode Whether writing to the target timer’s of the target timer of a related timer counter in software is enabled or disabled PWM output Single-shot output Writing in software is enabled Delayed single-shot output Continuous output Single-shot output PWM output Writing in software is disabled Delayed single-shot output Continuous output

10-185 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (b) For cases other than the combinations in Tables 10.8.2 and 10.8.3, whether writing to the counter in software is enabled or disabled depends on operation mode of the target timer. Table 10.8.4 Writes to Counter Enabled/Disabled by Timer Operation Modes Operation mode of the target timer Whether writing to the target timer’s counter in software is enabled or disabled PWM output Writing in software is disabled Single-shot output Writing in software is enabled Delayed single-shot output Continuous output Timer mode select circuit Write control signal T O D n-1 write signal Write control signal: PWM output mode: Low Other modes: High T O D n-1 counterT O D n-2 counter T O D n-3 counter T O D n-4 counter T O D n-6 counter TODn-0 TODn-1 TODn-2 TO Dn-3 TODn-4 TODn-5 TODn-6 TODn-7 Write signal Write signal Write signal Write signal Write signal Note: TODn denotes TOD0 and TOD1. Timer mode select circuit Write control signal Timer mode select circuit Write control signal T O D n-2 write signal T O D n-3 write signal T O D n-4 write signal T O D n-6 write signal Figure 10.8.5 Configuration of TOD Timer Counter Write Circuit

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10.8.6 TOD Reload 0 Registers

I TOD0_0 Reload 0 Register (TOD00RL0) <Address: H'0080 0796> I TOD0_1 Reload 0 Register (TOD01RL0) <Address: H'0080 079E> I TOD0_2 Reload 0 Register (TOD02RL0) <Address: H'0080 07A6> I TOD0_3 Reload 0 Register (TOD03RL0) <Address: H'0080 07AE> I TOD0_4 Reload 0 Register (TOD04RL0) <Address: H'0080 07B6> I TOD0_5 Reload 0 Register (TOD05RL0) <Address: H'0080 07BE> I TOD0_6 Reload 0 Register (TOD06RL0) <Address: H'0080 07C6> I TOD0_7 Reload 0 Register (TOD07RL0) <Address: H'0080 07CE> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOD00RL0 - TOD07RL0 <When reset : Indeterminate> D Bit Name Function R W 0 - 15 TOD00RL0 - TOD07RL0 16-bit reload register value Note: This register must always be accessed in halfwords. The TOD0 Reload 0 Register is used to reload the TOD0 Counter Registers (TOD00CT-TOD07CT) with data. It is in the following cases that the content of reload 0 register is loaded into the counter:

• When the counter is enabled in single-shot output or PWM output mode
• When the counter underflowed in delayed single-shot output or continuous output mode
• When the count value set by reload 1 register underflowed in PWM output mode Writing data to the reload 0 register does not mean that the data is loaded into the counter simultaneously.

10-187 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TOD1_0 Reload 0 Register (TOD10RL0) <Address: H'0080 0B96> I TOD1_1 Reload 0 Register (TOD11RL0) <Address: H'0080 0B9E> I TOD1_2 Reload 0 Register (TOD12RL0) <Address: H'0080 0BA6> I TOD1_3 Reload 0 Register (TOD13RL0) <Address: H'0080 0BAE> I TOD1_4 Reload 0 Register (TOD14RL0) <Address: H'0080 0BB6> I TOD1_5 Reload 0 Register (TOD15RL0) <Address: H'0080 0BBE> I TOD1_6 Reload 0 Register (TOD16RL0) <Address: H'0080 0BC6> I TOD1_7 Reload 0 Register (TOD17RL0) <Address: H'0080 0BCE> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOD10RL0 - TOD17RL0 <When reset : Indeterminate> D Bit Name Function R W 0 - 15 TOD10RL0 - TOD17RL0 16-bit reload register value Note: This register must always be accessed in halfwords. The TOD1 Reload 0 Register is used to reload the TOD1 Counter Registers (TOD10CT-TOD17CT) with data. It is in the following cases that the content of reload 0 register is loaded into the counter:

• When the counter is enabled in single-shot output or PWM output mode
• When the counter underflowed in delayed single-shot output or continuous output mode
• When the count value set by reload 1 register underflowed in PWM output mode Writing data to the reload 0 register does not mean that the data is loaded into the counter simultaneously.

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10.8.7 TOD Reload 1 Registers

I TOD0_0 Reload 1 Register (TOD00RL1) <Address: H'0080 0794> I TOD0_1 Reload 1 Register (TOD01RL1) <Address: H'0080 079C> I TOD0_2 Reload 1 Register (TOD02RL1) <Address: H'0080 07A4> I TOD0_3 Reload 1 Register (TOD03RL1) <Address: H'0080 07AC> I TOD0_4 Reload 1 Register (TOD04RL1) <Address: H'0080 07B4> I TOD0_5 Reload 1 Register (TOD05RL1) <Address: H'0080 07BC> I TOD0_6 Reload 1 Register (TOD06RL1) <Address: H'0080 07C4> I TOD0_7 Reload 1 Register (TOD07RL1) <Address: H'0080 07CC> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOD00RL1 - TOD07RL1 <When reset : Indeterminate> D Bit Name Function R W 0 - 15 TOD00RL1 - TOD07RL1 16-bit reload register value Note: This register must always be accessed in halfwords. The TOD0 Reload 1 Register is used to reload the TOD0 Counter Registers (TOD00CT-TOD07CT) with data. It is in the following cases that the content of reload 1 register is loaded into the counter:

• When the count value set by reload 0 register underflowed in PWM output mode Writing data to the reload 1 register does not mean that the data is loaded into the counter simultaneously.

10-189 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TOD1_0 Reload 1 Register (TOD10RL1) <Address: H'0080 0B94> I TOD1_1 Reload 1 Register (TOD11RL1) <Address: H'0080 0B9C> I TOD1_2 Reload 1 Register (TOD12RL1) <Address: H'0080 0BA4> I TOD1_3 Reload 1 Register (TOD13RL1) <Address: H'0080 0BAC> I TOD1_4 Reload 1 Register (TOD14RL1) <Address: H'0080 0BB4> I TOD1_5 Reload 1 Register (TOD15RL1) <Address: H'0080 0BBC> I TOD1_6 Reload 1 Register (TOD16RL1) <Address: H'0080 0BC4> I TOD1_7 Reload 1 Register (TOD17RL1) <Address: H'0080 0BCC> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOD10RL1 - TOD17RL1 <When reset : Indeterminate> D Bit Name Function R W 0 - 15 TOD10RL1 - TOD17RL1 16-bit reload register value Note: This register must always be accessed in halfwords. The TOD1 Reload 1 Register is used to reload the TOD1 Counter Registers (TOD10CT-TOD17CT) with data. It is in the following cases that the content of reload 1 register is loaded into the counter:

• When the count value set by reload 0 register underflowed in PWM output mode Writing data to the reload 1 register does not mean that the data is loaded into the counter simultaneously.

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10.8.8 TOD Enable Protect Registers

I TOD0 Enable Protect Register (TOD0PRO) <Address: H'0080 07DD> D 8 9 1 01 11 21 31 4 D 1 5 TOD00PROTOD01PROTOD02PROTOD03PROTOD04PROTOD05PROTOD06PROTOD07PRO <When reset : H'00> D Bit Name Function R W

8 TOD00PRO 0 : Enables rewrite

(TOD0_0 enable protect) 1 :Disables rewrite

9 TOD01PRO

(TOD0_1 enable protect)

10 TOD02PRO

(TOD0_2 enable protect)

11 TOD03PRO

(TOD0_3 enable protect)

12 TOD04PRO

(TOD0_4 enable protect)

13 TOD05PRO

(TOD0_5 enable protect)

14 TOD06PRO

(TOD0_6 enable protect)

15 TOD07PRO

(TOD0_7 enable protect) The TOD0 Enable Protect Register controls rewriting of the TOD0 counter enable bit described in Section 10.8.9 by enabling or disabling rewrite.

10-191 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TOD1 Enable Protect Register (TOD1PRO) <Address: H'0080 0BDD> D 8 9 1 01 11 21 31 4 D 1 5 TOD10PROTOD11PROTOD12PROTOD13PROTOD14PROTOD15PROTOD16PROTOD17PRO <When reset : H'00> D Bit Name Function R W

8 TOD10PRO 0 : Enables rewrite

(TOD1_0 enable protect) 1 :Disables rewrite

9 TOD11PRO

(TOD1_1 enable protect)

10 TOD12PRO

(TOD1_2 enable protect)

11 TOD13PRO

(TOD1_3 enable protect)

12 TOD14PRO

(TOD1_4 enable protect)

13 TOD15PRO

(TOD1_5 enable protect)

14 TOD16PRO

(TOD1_6 enable protect)

15 TOD17PRO

(TOD1_7 enable protect) The TOD1 Enable Protect Register controls rewriting of the TOD1 counter enable bit described in Section 10.8.9 by enabling or disabling rewrite.

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10.8.9 TOD Cout Enable Registers

I TOD0 Count Enable Register (TOD0CEN) <Address: H'0080 07DF> D 8 9 1 01 11 21 31 4 D 1 5 TOD00CEN TOD01CEN TOD02CEN TOD03CEN TOD04CEN TOD05CEN TOD06CEN TOD07CEN <When reset : H'00> D Bit Name Function R W

8 TOD00CEN 0 : Stops count

(TOD0_0 count enable) 1 :Enables count

9 TOD01CEN

(TOD0_1 count enable)

10 TOD02CEN

(TOD0_2 count enable)

11 TOD03CEN

(TOD0_3 count enable)

12 TOD04CEN

(TOD0_4 count enable)

13 TOD05CEN

(TOD0_5 count enable)

14 TOD06CEN

(TOD0_6 count enable)

15 TOD07CEN

(TOD0_7 count enable) The TOD0 Count Enable Register controls operation of TOD0 counters. To enable the counter in software, enable the relevant TOD0 Enable Protect Register for write and set the count enable bit by writing a 1. To stop the counter, enable the TOD0 Enable Protect Register for write and reset the count enable bit by writing a 0. In single-shot output and delayed single-shot output modes, when the counter stops due to an occurrence of underflow, the count enable bit is automatically reset to 0. Therefore, what you get by reading the TOD0 Count Enable Register is the status that indicates the counter's operating status (active or idle).

10-193 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS I TOD1 Count Enable Register (TOD0CEN) <Address: H'0080 0BDF> D 8 9 1 01 11 21 31 4 D 1 5 TOD10CEN TOD11CEN TOD12CEN TOD13CEN TOD14CEN TOD15CEN TOD16CEN TOD17CEN <When reset : H'00> D Bit Name Function R W

8 TOD10CEN 0 : Stops count

(TOD1_0 count enable) 1 :Enables count

9 TOD11CEN

(TOD1_1 count enable)

10 TOD12CEN

(TOD1_2 count enable)

11 TOD13CEN

(TOD1_3 count enable)

12 TOD14CEN

(TOD1_4 count enable)

13 TOD15CEN

(TOD1_5 count enable)

14 TOD16CEN

(TOD1_6 count enable)

15 TOD17CEN

(TOD1_7 count enable) The TOD1 Count Enable Register controls operation of TOD1 counters. To enable the counter in software, enable the relevant TOD1 Enable Protect Register for write and set the count enable bit by writing a 1. To stop the counter, enable the TOD1 Enable Protect Register for write and reset the count enable bit by writing a 0. In single-shot output and delayed single-shot output modes, when the counter stops due to an occurrence of underflow, the count enable bit is automatically reset to 0. Therefore, what you get by reading the TOD1 Count Enable Register is the status that indicates the counter's operating status (active or idle).

10-194 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.8.6 Configuration of TOD0 Enable Circuit WR Dn WR F/F F/F TOD0m enable protect (TOD0mPRO) TOD0m enable (TOD0mCEN) TOD0m enable control Figure 10.8.7 Configuration of TOD1 Enable Circuit WR Dn WR EN-ON F/F F/F F/F TID1 enable output enable (TID1EN0) TID1 output TOD1m enable protect (TOD1mPRO) TOD1m enable (TOD1mCEN) TOD1m enable control

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10.8.10 Operation in TOD PWM Output Mode

(1) Outline of TOD PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The valid count values are (reload 0 register set value + 1) and (reload 1 register set value + 1). The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output levels change from low to high, or vice versa) at count startup and upon each underflow. An interrupt can be generated when the counter underflows every other time (second time, fourth time, and so on) after being enabled. Note that TOD's PWM output mode does not have the correction function.

10-196 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.8.8 Typical Operation in PWM Output Mode H ’FFFF H ’0000 H ’A000 H ’(C000-1) H ’(A000-1) H ’C000 H ’A000 H ’C000 H ’A000 F/F output Underflow (first time) TOD interrupt by underflow Underflow (second time) Down-count starting from reload 1 register set value Data inverted by underflow Data inverted by enable Reload 1 register Down-count starting from reload 0 register set value Down-count starting from reload 0 register set value PWM output period Enabled (by writing to enable bit or by external input) Reload 0 register Count clock Counter Enable bit Note: This diagram does not show detail timing information . Data inverted by underflow

10-197 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (2) Reload register updates in TOD PWM output mode In PWM output mode, when the timer remains idle, reload 0 and reload 1 registers are updated at the same time data are written to the registers. But when the timer is active, reload 1 register is updated by updating reload 0 register. However, when you read reload 0 and reload 1 registers, the values you get are always the data written to the registers. Figure 10.8.9 PWM Circuit Diagram If you want to rewrite reload 0 and reload 1 registers while the timer is operating, rewrite reload 1 register first and then reload 0 register. In this way, reload 0 and reload 1 registers both are updated synchronously with PWM periods, from which the timer starts operating again. This operation can normally be performed collectively by accessing register addresses wordwise (in 32 bits) beginning with that of reload 1 register. (Data are automatically written to reload 1 and then reload 0 registers in succession.) If you update the reload registers in reverse by updating reload 0 register first and then reload 1 register, only reload 0 register is updated. In this case when you read reload 0 and reload 1 registers, the values you get are always the data written to the registers, and not the reload values being actually used. Note that when updating the PWM period, if the PWM period is terminated before you finished writing to reload 0, the PWM period is not updated in the current period and what you've set is reflected in the next period. TODnRL1 Buffer F/F TO TODnRL0 Internal bus Reload 1 Reload1WR Reload0WR 16-bit counterPrescaler output Reload 0 PWM mode control

10-198 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.8.10 Reload 0 and Reload 1 Register Updates in PWM Output Mode H ’0001 H ’FFFF H ’1000 H ’7FFF H ’2000 H ’8000 H ’9000 H ’1000 H ’2000 H ’8000 H ’9000 H ’7FFEH ’0000 H ’2000 H ’9000 (a) When reload register updates take effect in the current period (reflected in the next period) Note: This diagram does not show detail timing information. Count clock Reload 0 register Reload 1 register Counter Interrupt by underflow Timing at which reload 1 and reload 0 registers are updated New PWM output period Operation by new reload value written Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (reload 1 data latched) Enlarged view New PWM output period Old PWM output period F/F output PWM period latched Reload 1 buffer H ’0001 H ’FFFF H ’1000 H ’0FFF H ’2000 H ’8000 H ’9000 H ’1000 H ’2000 H ’8000 H ’9000 H ’0FFEH ’0000 H ’2000 H ’9000 (b) When reload register updates take effect in the next period (reflected one period later) Note: This diagram does not show detail timing information . Count clock Reload 0 register Reload 1 register Counter Interrupt by underflow Timing at which reload 1 and reload 0 registers are updated Old PWM output period Operation by old reload value Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (reload 1 data latched) Enlarged view Old PWM output periodOld PWM output period F/F output PWM period latched Reload 1 buffer

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10.8.11 Operation in TOD Single-shot Output Mode (without Correction Function)

(1) Outline of TOD single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. The count value is (reload 0 register set value + 1). (For details about count operation, also refer to Section 10.3.11, "Operation in TOP Single-shot Output Mode (with Correction Function)." (2) Precautions to be observed when using TOD single-shot output mode The following describes precautions to be observed when using TOD single-shot output mode.

• If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops).
• If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that countis enabled).
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled).
• Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled.

10-200 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.8.11 Typical Operation in TOD Single-shot Output Mode (without Correction Function) H ’FFFF H ’0000 H ’A000 H ’A000 Disabled (by underflow) (Not used) Counts down starting from reload 0 register set value F/F output TOD interrupt by underflow Data inverted by underflow Data inverted by enable Reload 1 register Enabled (by writing to enable bit or by external input) Reload 0 register Count clock Counter Enable bit Note: This diagram does not show detail timing information.

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10.8.12 Operation in TOD Delayed Single-shot Output Mode (without Correction Function)

(1) Outline of TOD delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (counter set value + 1) and then stops without performing any operation. When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it starts counting down from the counter's set value synchronously with the count clock. The first time the counter underflows, the reload 0 register value is loaded into the counter causing it to continue counting down, and the counter stops when it underflows next time. The F/F output waveform in delayed single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) when the counter underflows first time and next, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once, with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an interrupt can be generated when the counter underflows first time and next. The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For details about count operation, also see Section 10.3.12, "Operation in TOP Delayed Single-shot Output Mode (With Correction Function)." (2) Precautions to be observed when using TOD delayed single-shot output mode The following describes precautions to be observed when using TOD delayed single-shot output mode.

• If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops).
• If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled).
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled).
• When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge.
• Because the internal circuit operation is synchronized to the prescaler output, a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled.

10-202 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.8.12 Typical Operation in TOD Delayed Single-shot Output Mode (without Correction Function) H ’FFFF H ’0000 H ’F000 H ’A000 H ’F000 H ’EFFF F/F output Underflow (first time) TOD interrupt by underflow Underflow (second time) Down-count starting from reload 0 register set value Data inverted by underflow Reload 1 register Down-count starting from counter set value Enabled (by writing to enable bit or by external input) Reload 0 register Count clock Counter Enable bit Note: This diagram does not show detail timing information. Data inverted by underflow (Not used)

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10.8.13 Operation in TOD Continuous Output Mode (Without Correction Function)

(1) Outline of TOD continuous output mode In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID1 underflow/overflow signal), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows. The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For details about count operation, also see Section 10.3.11, "Operation in TOP Continuous Output Mode (Without Correction Function)." (2) Precautions to be observed when using TOD continuous output mode The following describes precautions to be observed when using TOD continuous output mode.

• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled).
• When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge.
• Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled.

10-204 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.8.13 Typical Operation in TOD Continuous Output Mode (without Correction Function) H ’FFFF H ’0000 H ’E000 H ’A000 H ’E000 H ’DFFF H ’DFFF F/F output Underflow (first time) Underflow (second time) Data inverted by underflow Data inverted by enable Reload 1 register Down-count starting from reload 0 register set value Enabled (by writing to enable bit or by external input) Reload 0 register Count clock Counter Note: This diagram does not show detail timing information. Data inverted by underflow Down-count starting from counter set value Down-count starting from reload 0 register set value (Not used)

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10.9 TOM (Output-related 16-bit Timer)

10.9.1 Outline of TOM

TOM (Timer Output Modification) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software. <Output modes without correction function>

• PWM output mode
• Single-shot output mode
• Single-shot PWM output mode
• Continuous output mode The table below shows specifications of TOM. The diagram in the next page shows a block diagram of TOM. Table 10.9.1 Specifications of TOM (Output-related 16-bit Timer) Item Specification Number of channels 8 channels Counter 16-bit down-counter Reload register 16-bit reload register Timer startup Started by writing to enable bit in software or by TID2 timer underflow/overflow signal Mode selection <Output modes without correction function>
• PWM output mode
• Single-shot output mode
• Single-shot PWM output mode
• Continuous output mode Interrupt generation Can be generated by a counter underflow

10-206 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.9.1 TOM (Output-related 16-bit Timer) F/FPRS5 clk udfTOM0_0 clk udfTOM0_1 clk udfTOM0_2 clk udfTOM0_3 clk udfTOM0_4 clk udfTOM0_5 clk udfTOM0_6 clk udfTOM0_7 F/F37 F/F38 F/F39 F/F40 F/F41 F/F42 F/F43 F/F44 IRQ16 TO 37 TO 38 TO 39 TO 40 TO 41 TO 42 TO 43 TO 44 PRS5 en clk udfTID2 ovf IRQ17CLK1 CLK2 TIN28 TIN29 : Prescaler : Output flip-flop 1/2 internal peripheral clock en en en en en en en

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10.9.2 Outline of Each Mode of TOM

Each mode of TOM is outlined below. For each TOM channel, only one of the following modes can be selected. (1) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock, letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The F/F output waveform in PWM output mode is inverted at count startup and upon each underflow. The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). An interrupt can be generated when the counter underflows every other time (second time, fourth time, and so on) after being enabled. (2) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by using TID2 underflow/overflow signal), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt can be generated when the counter underflows.

10-208 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (3) Single-shot PWM output mode (without correction function) In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle only once. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock, letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Then when the counter underflows next time, it stops. The valid count values are the (reload 0 register set value + 1) and (reload 1 register set value + 1) each. To stop the timer in software, disable count by writing to the enable bit. The timer stops at the same time count is disabled (and not in synchronism with PWM output period). The F/F output waveform in single-shot PWM output mode is inverted (F/F output levels change from low to high, or vice versa) upon each underflow. (Unlike in PWM output mode, F/F output is not inverted at counter startup.) An interrupt can be generated when the counter underflows second time after being enabled. (4) Continuous output mode (without correction function) In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with the reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows.

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10.9.3 TOM Related Register Map

The diagram below shows a TOM related register map. Figure 10.9.2 TOM Related Register Map (1/2) H’0080 0C90 D0 D7 D8 D15 H’0080 0C92 H’0080 0C94 H’0080 0C96 H’0080 0CA0 H’0080 0CA2 H’0080 0CA4 H’0080 0CA6 H’0080 0CB0 H’0080 0CB2 H’0080 0CB4 H’0080 0CB6 H’0080 0CBA H’0080 0CBC H’0080 0CBE TOM0_1 Counter (TOM01CT) H’0080 0C9A H’0080 0C98 H’0080 0CB8 TOM0_0 Reload 0 Register (TOM00RL0) TOM0_0 Reload 1 Register (TOM00RL1) TOM0_0 Counter (TOM00CT) TOM0_5 Reload 0 Register (TOM05RL0) TOM0_5 Reload 1 Register (TOM05RL1) H’0080 0C9C H’0080 0C9E H’0080 0CA8 H’0080 0CAA H’0080 0CAC H’0080 0CAE +0 Address +1 AddressAddress Note: The registers enclosed in thick frames must always be accessed in halfwords. Blank addresses are reserved. TOM0_2 Counter (TOM02CT) TOM0_1 Reload 0 Register (TOM01RL0) TOM0_1 Reload 1 Register (TOM01RL1) TOM0_3 Counter (TOM03CT) TOM0_2 Reload 0 Register (TOM02RL0) TOM0_2 Reload 1 Register (TOM02RL1) TOM0_4 Counter (TOM04CT) TOM0_3 Reload 0 Register (TOM03RL0) TOM0_3 Reload 1 Register (TOM03RL1) TOM0_5 Counter (TOM05CT) TOM0_4 Reload 0 Register (TOM04RL0) TOM0_4 Reload 1 Register (TOM04RL1)

10-210 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.9.3 TOM Related Register Map (2/2) H’0080 0CC0 D0 D7 D8 D15 H’0080 0CC2 H’0080 0CC4 H’0080 0CC6 H’0080 0CD0 H’0080 0CD2 H’0080 0CD4 H’0080 0CD6 H’0080 0CCA H’0080 0CC8 TID2 Control & Prescaler 5 Enable Register (TID2PRS5EN) (Note 1) H’0080 0CCC H’0080 0CCE H’0080 0CD8 Prescaler Register 5 (PRS5) TOM0 Interrupt Mask Register (TOM0IMA) TOM0 Interrupt Status Register (TOM0IST) F/F Protect Register 4 (FFP4) F/F Data Register 4 (FFD4) Note 1: Prescaler Register 5 is shared with TOM0_0-7 and TID2, and TID2 Control & Prescaler 5 Enable Register is used in TID2 control. H’0080 0CDA H’0080 0CDC H’0080 0CDE TOM0 Control Register (TOM0CR) TOM0 Enable Protect Register (TOM0PRO) TOM0 Count Enable Register (TOM0CEN) Blank addresses are reserved. Note 2: The registers enclosed in thick frames must always be accessed in halfwords. TOM0_7 Counter (TOM07CT) TOM0_6 Reload 0 Register (TOM06RL0) TOM0_6 Reload 1 Register (TOM06RL1) +0 Address +1 AddressAddress TOM0_6 Counter (TOM06CT) TOM0_7 Reload 0 Register (TOM07RL0) TOM0_7 Reload 1 Register (TOM07RL1)

10-211 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS <When reset:H'0000> D Bit Name Function R W 0,1 TOM00M 00: Single-shot output mode (TOM0_0 operation mode selection) 01: Single-shot PWM output mode 2,3 TOM01M 10: Continuous output mode (TOM0_1 operation mode selection) 11: PWM output mode 4,5 TOM02M (TOM0_2 operation mode selection) 6,7 TOM03M (TOM0_3 operation mode selection) 8,9 TOM04M (TOM0_4 operation mode selection) 10,11 TOM05M (TOM0_5 operation mode selection) 12,13 TOM06M (TOM0_6 operation mode selection) 14,15 TOM07M (TOM0_7 operation mode selection)

10.9.4 TOM Control Registers

I TOM0 Control Register (TOM0CR) <Address: H'0080 0CDA> The TOM0 Control Register is used to select TOM0_0-7 operation modes (PWM output, single- shot output, single-shot PWM output, or continuous output mode). D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOM00M TOM01M TOM02M TOM03M TOM04M TOM05M TOM06M TOM07M

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10.9.5 TOM Counters

I TOM0_0 Counter (TOM00CT) <Address: H'0080 0C90> I TOM0_1 Counter (TOM01CT) <Address: H'0080 0C98> I TOM0_2 Counter (TOM02CT) <Address: H'0080 0CA0> I TOM0_3 Counter (TOM03CT) <Address: H'0080 0CA8> I TOM0_4 Counter (TOM04CT) <Address: H'0080 0CB0> I TOM0_5 Counter (TOM05CT) <Address: H'0080 0CB8> I TOM0_6 Counter (TOM06CT) <Address: H'0080 0CC0> I TOM0_7 Counter (TOM07CT) <Address: H'0080 0CC8> W= : Whether writing to the counter is enabled or disabled depends on a combination of timers and timer operation modes. For details, see (1) TOM timer counter write enable/disable conditions. Note: This register must always be accessed in halfwords. The TOM0 Counter is a 16-bit down-counter. After the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it starts counting synchronously with the count clock. During PWM output and single-shot PWM output modes, this counter is disabled against write. <When reset: Indeterminate> D Bit Name Function R W 0-15 TOM00CT-TOM07CT 16-bit counter value D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOM00CT-TOM07CT

10-213 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (1) TOM timer counter write enable/disable conditions Whether TOM timer counter is enabled for or disabled against write is determined depending on a combination of TOM timers and a combination of their operation modes. These counter write enable/disable conditions are described below. Also, Figure 10.9.4 schematically shows a configuration of the TOM timer counter write circuit. (a) Table 10.9.2 shows the relationship of each timer in cases where writing to the counter is enabled or disabled by a combination of timers. Whether writing to the counter in software is enabled or disabled depends on a combination Table 10.9.2 Relationship of Each Timer Target timer Related timer TOM0-2 TOM0-1 TOM0-4 TOM0-2 TOM0-6 TOM0-3 Table 10.9.3 Behavior by a Combination of Timer Operation Modes Operation mode Operation mode Whether writing to the target timer’s of the target timer of a related timer counter in software is enabled or disabled PWM output Single-shot output Writing in software is enabled Single-shot PWM output Continuous output Single-shot output PWM output Writing in software is disabled Continuous output Single-shot PWM output (b) For cases other than the combinations in Tables 10.9.2 and 10.9.3, whether writing to the counter in software is enabled or disabled depends on operation mode of the target timer. Table 10.9.4 Writes to Counter Enabled/Disabled by Timer Operation Modes Operation mode of the target timer Whether writing to the target timer’s counter in software is enabled or disabled PWM output Writing in software is disabled Single-shot PWM output Single-shot output Writing in software is enabled Continuous output

10-214 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Write control signal: PWM/single-shot PWM output mode: Low Other modes: High TOM 0 - 0 TOM 0 - 1 TOM 0 - 2 TOM 0 - 3 TOM 0 - 4 TOM 0 - 5 TOM 0 - 6 TOM 0 - 7 Write signal Write signal Write signal Write signal Write signal Timer mode select circuit Write control signal Timer mode select circuit Write control signal T O M 0-2 write signal T O M 0-3 write signal T O M 0-4 write signal T O M 0-6 write signal T O M 0-1 counter T O M 0-2 counter T O M 0-3 counter T O M 0-4 counter T O M 0-6 counter Figure 10.9.4 Configuration of TOM Timer Counter Write Circuit

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10.9.6 TOM Reload 0 Registers

I TOM0_0 Reload 0 Register (TOM00RL0) <Address: H'0080 0C96> I TOM0_1 Reload 0 Register (TOM01RL0) <Address: H'0080 0C9E> I TOM0_2 Reload 0 Register (TOM02RL0) <Address: H'0080 0CA6> I TOM0_3 Reload 0 Register (TOM03RL0) <Address: H'0080 0CAE> I TOM0_4 Reload 0 Register (TOM04RL0) <Address: H'0080 0CB6> I TOM0_5 Reload 0 Register (TOM05RL0) <Address: H'0080 0CBE> I TOM0_6 Reload 0 Register (TOM06RL0) <Address: H'0080 0CC6> I TOM0_7 Reload 0 Register (TOM07RL0) <Address: H'0080 0CCE> Note: This register must always be accessed in halfwords. The TOM0 Reload 0 Registers are used to reload the TOM0 Counter Registers (TOM00CT- TOM07CT) with data. It is in the following cases that the content of reload 0 register is loaded into the counter:

• When the counter is enabled in single-shot output, PWM output, or single-shot PWM output mode
• When the counter underflowed in continuous output mode
• When the count value set by reload 1 register underflowed in PWM output mode Writing data to the reload 0 register does not mean that the data is loaded into the counter simultaneously. <When reset: Indeterminate> D Bit Name Function R W 0-15 TOM00RL0-TOM07RL0 16-bit reload register value D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOM00RL0-TOM07RL0

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10.9.7 TOM Reload 1 Registers

I TOM0_0 Reload 1 Register (TOM00RL1) <Address: H'0080 0C94> I TOM0_1 Reload 1 Register (TOM01RL1) <Address: H'0080 0C9C> I TOM0_2 Reload 1 Register (TOM02RL1) <Address: H'0080 0CA4> I TOM0_3 Reload 1 Register (TOM03RL1) <Address: H'0080 0CAC> I TOM0_4 Reload 1 Register (TOM04RL1) <Address: H'0080 0CB4> I TOM0_5 Reload 1 Register (TOM05RL1) <Address: H'0080 0CBC> I TOM0_6 Reload 1 Register (TOM06RL1) <Address: H'0080 0CC4> I TOM0_7 Reload 1 Register (TOM07RL1) <Address: H'0080 0CCC> Note: This register must always be accessed in halfwords. The TOM0 Reload 1 Registers are used to reload the TOM0 Counter Registers (TOM00CT- TOM07CT) with data. It is in the following cases that the content of reload 1 register is loaded into the counter:

• When the count value set by reload 1 register underflowed in PWM output mode. Writing data to the reload 1 register does not mean that the data is loaded into the counter simultaneously. <When reset: Indeterminate> D Bit Name Function R W 0-15 TOM00RL1-TOM07RL1 16-bit reload register value D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOM00RL1-TOM07RL1

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10.9.8 TOM Enable Protect Registers

I TOM0 Enable Protect Register (TOM0PRO) <Address: H'0080 0CDD> The TOM0 Enable Protect Register controls rewriting of the TOM0 counter enable bit described in the next page by enabling or disabling rewrite. <When reset:H'00> D Bit Name Function R W

8 TOM00PRO 0: Enables rewrite

(TOM0_0 enable protect) 1: Disables rewrite

9 TOM01PRO

(TOM0_1 enable protect)

10 TOM02PRO

(TOM0_2 enable protect)

11 TOM03PRO

(TOM0_3 enable protect)

12 TOM04PRO

(TOM0_4 enable protect)

13 TOM05PRO

(TOM0_5 enable protect)

14 TOM06PRO

(TOM0_6 enable protect)

15 TOM07PRO

(TOM0_7 enable protect) D 8 9 1 01 11 21 31 4 D 1 5 TOM00PRO TOM01PRO TOM02PRO TOM03PRO TOM04PRO TOM05PRO TOM06PRO TOM07PRO

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10.9.9 TOM Count Enable Registers

I TOM0 Count Enable Register (TOM0CEN) <Address: H'0080 0CDF> D 8 9 1 01 11 21 31 4 D 1 5 TOM00CEN TOM01CEN TOM02CEN TOM03CEN TOM04CEN TOM05CEN TOM06CEN TOM07CEN <When reset:H'00> D Bit Name Function R W

8 TOM00CEN 0: Stops count

(TOM0_0 count enable) 1: Enables count

9 TOM01CEN

(TOM0_1 count enable)

10 TOM02CEN

(TOM0_2 count enable)

11 TOM03CEN

(TOM0_3 count enable)

12 TOM04CEN

(TOM0_4 count enable)

13 TOM05CEN

(TOM0_5 count enable)

14 TOM06CEN

(TOM0_6 count enable)

15 TOM07CEN

(TOM0_7 count enable) The TOM0 Count Enable Register controls operation of TOM0 counters. To enable the counter in software, enable the relevant TOM0 Enable Protect Register for write and set the count enable bit by writing a 1. To stop the counter, enable the TOM0 Enable Protect Register for write and reset the count enable bit by writing a 0. In single-shot output and single-shot PWM output modes, when the counter stops due to an occurrence of underflow, the count enable bit is automatically reset to 0. Therefore, what you get by reading the TOM0 Count Enable Register is the status that indicates the counter's operating status (active or idle).

10-219 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.9.5 Configuration of the TOM Enable Circuit WR Dn WR EN-ON TID2 enable output enable (TID2EN0) F/F F/F F/F TID2 output TOM0m enable protect (TOM0mPRO) TOM0m enable (TOM0mCEN) TOM0m enable control

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10.9.10 Operation in TOM PWM Output Mode

(1) Outline of TOM PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Thereafter, the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs. The valid count values are (reload 0 register set value + 1) and (reload 1 register set value + 1). The timer stops at the same time count is disabled by writing to the enable bit (and not in synchronism with PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output levels change from low to high, or vice versa) at count startup and upon each underflow. An interrupt can be generated when the counter underflows every other time (second time, fourth time, and so on) after being enabled. Note that TOM's PWM output mode does not have the correction function.

10-221 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.9.6 Typical Operation in PWM Output Mode H ’FFFF H ’0000 H ’A000 H ’(C000-1) H ’(A000-1) H ’C000 H ’A000 H ’C000 H ’A000 F/F output Underflow (first time) TOM interrupt by underflow Underflow (second time) Down-count starting from reload 1 register set value Data inverted by underflow Data inverted by enable Reload 1 register Down-count starting from reload 0 register set value PWM output period Enabled (by writing to enable bit or by external input) Reload 0 register Count clock Counter Enable bit Note: This diagram does not show detail timing information. Data inverted by underflow Down-count starting from reload 0 register set value

10-222 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS (2) Reload register updates in TOM PWM output mode In PWM output mode, when the timer remains idle, reload 0 and reload 1 registers are updated at the same time data are written to the registers. But when the timer is active, reload 1 register is updated by updating reload 0 register. However, when you read reload 0 and reload 1 registers, the values you get are always the data written to the registers. Figure 10.9.7 PWM Circuit Diagram If you want to rewrite reload 0 and reload 1 registers while the timer is operating, rewrite reload 1 register first and then reload 0 register. In this way, reload 0 and reload 1 registers both are updated synchronously with PWM periods, from which the timer starts operating again. This operation can normally be performed collectively by accessing register addresses wordwise (in 32 bits) beginning with that of reload 1 register. (Data are automatically written to reload 1 and then reload 0 registers in succession.) If you update the reload registers in reverse by updating reload 0 register first and then reload 1 register, only reload 0 register is updated. When you read reload 0 and reload 1 registers, the values you get are always the data written to the registers, and not the reload values being actually used. Note that when updating the PWM period, if the PWM period is terminated before you finished writing to reload 0, the PWM period is not updated in the current period and what you've set is reflected in the next period. TOM0nRL1 Buffer F/F TO TOM0nRL0 Internal bus Reload 1 Reload1WR Reload0WR 16-bit counterPrescaler output Reload 0 PWM mode control

10-223 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.9.8 Reload 0 and Reload 1 Register Updates in PWM Output Mode H ’0001 H ’FFFF H ’1000 H ’7FFF H ’2000 H ’8000 H ’9000 H ’1000 H ’2000 H ’8000 H ’9000 H ’7FFEH ’0000 H ’2000 H ’9000 (a) When reload register updates take effect in the current period (reflected in the next period) Note: This diagram does not show detail timing information . Count clock Reload 0 register Reload 1 register Counter Interrupt by underflow Timing at which reload 1 and reload 0 registers are updated New PWM output period Operation by new reload value written Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (reload 1 data latched) Enlarged view New PWM output periodOld PWM output period F/F output PWM period latched Reload 1 buffer H ’0001 H ’FFFF H ’1000 H ’0FFF H ’2000 H ’8000 H ’9000 H ’1000 H ’2000 H ’8000 H ’9000 H ’0FFEH ’0000 H ’2000 H ’9000 (b) When reload register updates take effect in the next period (reflected one period later) Note: This diagram does not show detail timing information. Count clock Reload 0 register Reload 1 register Counter Interrupt by underflow Timing at which reload 1 and reload 0 registers are updated Old PWM output period Operation by old reload value Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (reload 1 data latched) Enlarged view Old PWM output periodOld PWM output period F/F output PWM period latched Reload 1 buffer

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10.9.11 Operation in TOM Single-shot Output Mode (without Correction Function)

(1) Outline of TOM single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and stops without performing any operation. When after setting the reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the content of reload 0 register into the counter synchronously with the count clock, letting the counter start counting. The counter counts down clock pulses and stops when it underflows after reaching the minimum count. The F/F output waveform in single-shot output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once. Also, an interrupt can be generated when the counter underflows. The count value is (reload 0 register set value + 1). (For details about count operation, also refer to Section 10.3.11, "Operation in TOP Single-shot Output Mode (with Correction Function)." (2) Precautions to be observed when using TOM single-shot output mode The following describes precautions to be observed when using TOM single-shot output mode.

• If the counter stops due to underflow in the same clock period as the timer is enabled by external input, the former has priority (so that the counter stops).
• If the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit, the latter has priority (so that count is enabled).
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled).
• Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled.

10-225 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.9.9 Typical Operation in TOM Single-shot Output Mode (without Correction Function) H ’FFFF H ’0000 H ’A000 H ’A000 Disabled (by underflow) (Not used) Counts down starting from reload 0 register set value F/F output TOM interrupt by underflow Data inverted by underflow Data inverted by enable Reload 1 register Enabled (by writing to enable bit or by external input) Reload 0 register Count clock Counter Enable bit Note: This diagram does not show detail timing information.

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10.9.12 Operation in TOM Single-shot PWM Output Mode (without Correction Function)

(1) Outline of TOM single-shot PWM output mode In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle only once. When after setting the initial values in reload 0 and reload 1 registers, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it loads the reload 0 register value into the counter synchronously with the count clock, letting the counter start counting down. The first time the counter underflows, the reload 1 register value is loaded into the counter letting it continue counting. Then when the counter underflows next time, it stops. The valid count values are the (reload 0 register set value + 1) and (reload 1 register set value + 1) each. To stop the timer in software, disable count by writing to the enable bit. The timer stops at the same time count is disabled (and not in synchronism with PWM output period). The F/F output waveform in single-shot PWM output mode is inverted (F/F output levels change from low to high, or vice versa) upon each underflow. (Unlike in PWM output mode, F/F output is not inverted at counter startup.) An interrupt can be generated when the counter underflows second time after being enabled. Note that TOM's single-shot PWM output mode does not have the correction function.

10-227 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.9.10 Typical Operation in TOM Single-shot PWM Output Mode (without Correction Function) H ’FFFF H ’0000 H ’A000 H ’A000 H ’F000 H ’EFFF H ’F000 F/F output Underflow (first time) TOM interrupt by underflow Underflow (second time) Down-count starting from reload 1 register set value Data inverted by underflow Reload 1 register Down-count starting from reload 0 register set value PWM output period Enabled (by writing to enable bit or by external input) Reload 0 register Count clock Counter Enable bit Note: This diagram does not show detail timing information. Data inverted by underflow

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10.9.13 Operation in TOM Continuous Output Mode (Without Correction Function)

(1) Outline of TOM continuous output mode In continuous output mode, the timer counts down clock pulses starting from the set value of the counter and when the counter underflows, reloads it with reload 0 register value. Thereafter, this operation is repeated each time the counter underflows, thus generating consecutive pulses whose waveform is inverted in width of (reload 0 register set value + 1). When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable bit in software or by TID2 underflow/overflow signal), it starts counting down from the counter's set value synchronously with the count clock and when the minimum count is reached, generates an underflow. This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the counter, disable count by writing to the enable bit in software. The F/F output waveform in continuous output mode is inverted (F/F output levels change from low to high, or vice versa) at startup and upon underflow, generating consecutive pulses until the timer stops counting. Also, an interrupt can be generated each time the counter underflows. The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For details about count operation, also see Section 10.3.11, "Operation in TOP Continuous Output Mode (Without Correction Function)." (2) Precautions to be observed when using TOM continuous output mode The following describes precautions to be observed when using TOM continuous output mode.

• If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority (so that count is disabled).
• When you read the counter immediately after reloading it pursuant to underflow, the value you get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at the next clock edge.
• Because the internal circuit operation is synchronized to the count clock (prescaler output), a finite time equal to a prescaler delay is included before F/F starts operating after the timer is enabled.

10-229 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.9.11 Typical Operation in TOM Continuous Output Mode (Without Correction F unction) H ’FFFF H ’0000 H ’E000 H ’A000 H ’E000 H ’DFFF H ’DFFF (Not used) F/F output Underflow (first time) TOM interrupt by underflow Underflow (second time) Data inverted by underflow Data inverted by enable Reload 1 register Enabled (by writing to enable bit or by external input) Reload 0 register Count clock Counter Enable bit Note: This diagram does not show detail timing information. Data inverted by underflow Down-count starting from counter set value Down-count starting from reload 0 register set value Down-count starting from reload 0 register set value

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10.9.14 Example Application for Using the 32170 in Motor Control

The 16-bit timer TOM incorporated in the 32170 helps to reduce software burdens during motor control. The following shows an example application for using the 32170 in motor control. The three-phase motor control waveform is materialized by starting TOM in 20 kHz fixed cycles generated by TID2. The new single-shot PWM output function of TOM enables the output waveform to be configured easily by storing waveform data only when the data needs to be rewritten. Note that the high/low transistor shorting prevention time can be provided by changing the set time of TOM in software. Figure 10.9.12 System Configuration Diagram Figure 10.9.13 Timer Connections When Used for Three-phase Motor Control Circuit board M32R/E#4 Power-MOS MotorU V W TMS TMS TMS TOM TOM TOM TOM TOM TOM clk clk clk clk clk clk F/F37 F/F38 F/F39 F/F40 F/F41 F/F42 TOM(U) PSC5 EN EN EN EN EN EN clk TID2 Single-shot PWM TOM0_0 Fixed cycle udf udf udf udf udf udf udf TOM(/U) TOM(V) TOM(/V) TOM(W) TOM(/W) 20 kHz generated Startup Single-shot PWM TOM0_1 Single-shot PWM TOM0_2 Single-shot PWM TOM0_3 Single-shot PWM TOM0_4 Single-shot PWM TOM0_5

10-231 32170/32174 Group User's Manual (Rev. 2.1) MULTIJUNCTION TIMERS Figure 10.9.14 Diagram of Control Image Single-shot U V W 20KHzTOM start TOM(U) TOM(/U) TOM(V) TOM(/V) TOM(W) TOM(/W) Delay Delay Single-shot : Shorting prevention time

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11.1 Outline of A-D Converters

11.2 A-D Converter Related

11.3 Functional Description of A-D

11.4 Precautions on Using A-D

11-2 32170/32174 Group User's Manual (Rev. 2.1) A-D CONVERTERS

11.1 Outline of A-D Converter

The 32170 contains two 10-bit A-D converters of a successive approximation type (A-D0 and A-D1 converters). These converters have 32 analog input pins (channels) AD0IN0 to AD0IN15 and AD1IN0 to AD1IN 15. The A-D conversion results can be read out in either 8 bits or 10 bits. For A-D conversion, there are following conversion modes and operation modes: (1) Conversion mode

• A-D conversion mode: Ordinary mode in which analog input voltages are converted into digital quantities.
• Comparator mode (Note): A mode in which analog input voltage is compared with a preset comparison voltage to only find the relative magnitude of two quantities. (Single mode only) (2) Operation mode
• Single mode: Analog input voltage in one channel is A-D converted once or comparated(note) with a given quantity.
• Scan mode: Analog input voltages in multiple selected channels (4, 8, or 16 channels) are sequentially A-D converted. (3) Types of scan modes
• Single-shot scan mode: Scan operation is performed for one machine cycle.
• Continuous scan mode: Scan operation is performed repeatedly until stopped. (4) Special operation mode
• Forcible single mode execution during scan mode: Conversion is forcibly executed in single mode during scan operation.
• Scan mode start after single mode execution: Scan operation is started subsequently after executing conversion in single mode.
• Conversion restart: A-D conversion being executed in single or scan mode is restarted. The A-D conversion and comparate rates can be selected between normal and double rate. An A- D conversion interrupt request or a DMA transfer request (for the A-D0 converter only) can be generated at completion of A-D conversion, comparate operation, single-shot scan operation, or one cycle of continuous scan operation. Note: To discriminate between the comparison operation performed internally by the successive approximation-type A-D converter and the operation in comparator mode performed using the A-D converter as a comparator, the comparison operation in comparator mode in this manual is referred to as "comparate."

11-3 32170/32174 Group User's Manual (Rev. 2.1) and A-D1 converters, respectively. Table 11.1.1 Outline of A-D Converters Item Content Analog input 16 channels × 2 A-D conversion method Successive approximation method Resolution 10 bits (Conversion results can be read out in either 8 bits or 10 bits) Absolute accuracy (Note1) Normal mode ±2LSB (Conditions : Ta = -40 to 125°C, Double-speed mode ±2LSB AVCC0,1=VREF0,1=5.12V) Conversion mode A-D conversion mode, comparator mode Operation mode Single mode, scan mode Scan mode Single-shot scan mode, continuous scan mode Conversion start trigger Software start Started by setting A-D converter start bit to 1 Hardware start A-D0 converter started by MJT output event bus 3, A-D1 converter started by TID1 overflow or underflow (Note 2) Started by external ADTRG pin input Conversion rate During single mode Normal rate 299 × 1/f(BCLK) (Note 3) f(BCLK): (shortest time) Double rate 173 × 1/f(BCLK) Internal peripheral clock During comparator mode Normal rate 47 × 1/f(BCLK) operating frequency (shortest time) Double rate 29 × 1/f(BCLK) Interrupt request generation function Generated at completion of A-D conversion, comparate operation, single-shot scan operation, or one cycle of continuous scan operation DMA transfer request generation Generated at completion of A-D conversion, comparate operation, function (Note 4) single-shot scan operation, or one cycle of continuous scan operation Note 1: The rated value of conversion accuracy here is that of the microcomputer’s own as a single unit, which can only be obtained in an environment where the power supply wiring on the board is stable and the microcomputer is unaffected by noise. Note 2: Refer to Chapter 10, "Multijunction Timers." Note 3: When BCLK = 20 MHz, this is 1/f(BCLK) = 50 ns. Note 4: The DMA transfer request generation function is available for only the A-D0 converter. The A-D1 converter does not have this function. A-D CONVERTERS

11-4 32170/32174 Group User's Manual (Rev. 2.1) Figure 11.1.1 Block Diagram of A-D0 Converter A-D CONVERTERS (AD0SAR) 10-bit A-D0 Data Register 0 10-bit A-D0 Data Register 1 A-D0 Single Mode Register A-D Comparate Data Register A-D Control Circuit Mode selection Channel selection Conversion time selection Flag control Interrupt control10-bit A-D Converter Comparator AD0IN8 AD0IN9 AD0N10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 AD0CMP AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0DT12 AD0DT13 AD0DT14 AD0DT15 DMA transfer request Successive Approximation -type A-D Converter Unit Internal data bus A-D0 Scan Mode Register P67/ADTRG AD0SCM0,1 AD0SIM0,1 AVCC0 Output event bus 3 (multijunction timer) 10-bit readout 8-bit readout Shifter 10-bit A-D0 Data Register 2 10-bit A-D0 Data Register 3 10-bit A-D0 Data Register 4 10-bit A-D0 Data Register 5 10-bit A-D0 Data Register 6 10-bit A-D0 Data Register 7 10-bit A-D0 Data Register 8 10-bit A-D0 Data Register 9 10-bit A-D0 Data Register 10 10-bit A-D0 Data Register 11 10-bit A-D0 Data Register 12 10-bit A-D0 Data Register 13 10-bit A-D0 Data Register 14 10-bit A-D0 Data Register 15

11-5 32170/32174 Group User's Manual (Rev. 2.1) Figure 11.1.2 Block Diagram of A-D0 Converter A-D CONVERTERS AD1SCM0,1 AD1SIM0,1 AVCC1 TID1 underflow /overflow 10-bit A-D1 Data Register 0 10-bit A-D1 Data Register 1 A-D1 Single Mode Register A-D Comparate Data Register Internal data bus A-D1 Scan Mode Register 10-bit readout Shifter 10-bit A-D1 Data Register 2 10-bit A-D1 Data Register 3 10-bit A-D1 Data Register 4 10-bit A-D1 Data Register 5 10-bit A-D1 Data Register 6 10-bit A-D1 Data Register 7 10-bit A-D1 Data Register 8 10-bit A-D1 Data Register 9 10-bit A-D1 Data Register 10 10-bit A-D1 Data Register 11 10-bit A-D1 Data Register 12 10-bit A-D1 Data Register 13 10-bit A-D1 Data Register 14 10-bit A-D1 Data Register 15 Selector interrupt request 10-bit A-D Successive Approximation Register (AD1SAR) A-D Control Circuit Mode selection Channel selection Conversion time selection Flag control Interrupt control10-bit A-D Converter Comparator Successive Approximation -type A-D Converter Unit 8-bit readout

11-6 32170/32174 Group User's Manual (Rev. 2.1)

11.1.1 Conversion Modes

The A-D converters have two conversion modes: "A-D conversion mode" and "Comparator mode." (1) A-D conversion mode In A-D conversion mode, the analog input voltage in a specified channel is converted into digital quantity. In single mode, A-D conversion is performed on a channel selected by the Single Mode Register 1 analog input pin select bit. In scan mode, A-D conversion is performed on channels selected by Scan Mode Register 1 according to settings of Scan Mode Register 0. The conversion result is stored in each channel's corresponding 10-bit A-D Data Register. Also, 8-bit A-D conversion results can be read from each 8-bit A-D Data Register. An A-D conversion interrupt request or a DMA transfer request (for the A-D0 converter only) can be generated at completion of A-D conversion when in single mode, or when operating in scan mode, at completion of one cycle of scan loop. (2) Comparator mode In comparator mode, the analog input voltage in a specified channel is "comparated" (compared) with the Successive Approximation Register value, and the result (relative magnitude of two values) is returned to a flag. The channel to be comparated is selected using the Single Mode Register 1 analog input pin select bit. The result of comparate operation is flagged (1 or 0) by setting or resetting the A-D Comparate Data Register bit that corresponds to the selected channel. An A-D conversion interrupt request or a DMA transfer request (for the A-D0 converter only) can be generated at completion of comparate operation. A-D CONVERTERS

11-7 32170/32174 Group User's Manual (Rev. 2.1)

11.1.2 Operation Modes

The A-D converters operate in two modes: "Single mode" and "Scan mode." (1) Single mode In single mode, the analog input voltage in one selected channel is A-D converted once or comparated with a given quantity. An A-D conversion interrupt request or a DMA transfer request (for the A-D0 converter only) can be generated at completion of A-D conversion. Figure 11.1.3 Operation in Single Mode (A-D Conversion) Figure 11.1.4 Operation in Single Mode (Comparate) Note 1:A-D0 conversion start: Software trigger → Started by setting A-D0 conversion start bit to 1_____ Hardware trigger → Started by output event bus 3 or ADTRG signal input A-D1 conversion start: Software trigger → Started by setting A-D1 conversion start bit to 1_____ Hardware trigger → Started by TID1 overflow/underflow or ADTRG signal input Note 2:DMA transfer request: Can be generated for only the A-D0 converter. Note 1: Comparate start: Started by writing a comparison value to the successive approximation register (ADiSAR) Note 2: DMA transfer request: Can be generated for only the A-D0 converter. A-D CONVERTERS A-D conversion interrupt request or DMA transfer request (Note 2) ANiINn Completed ADiDTn 10-bit A-Di data register Conversion starts (Note 1) i=0,1 n=0-15 ADiINn ADiCMP A-Di comparate data register ADiSAR A-D successive approximation register Comparate result ADiCMP=0 (ANn>ADiSAR) ADiCMP=1 (ANn<ADiSAR) i=0,1 n=0-15 A-D conversion interrupt request or DMA transfer request (Note 2) CompletedConversion starts (Note 1)

11-8 32170/32174 Group User's Manual (Rev. 2.1) (2) Scan mode In scan mode, analog input voltages in multiple selected channels (4, 8, or 16 channels) are sequentially A-D converted. There are two types of scan modes: "Single-shot scan mode" in which A-D conversion is completed by performing one cycle of scan operation, and "Continuous scan mode" in which scan operation is continued until halted by setting the Scan Mode Register A-D conversion stop bit to 1. These types of scan modes are selected using Scan Mode Register 0. The channels to be scanned are selected using Scan Mode Register 1. The number of channels and the sequence to be scanned can be selected from three combinations available: 4, 8, or 16 channels. Channels ADiIN0 to ADiIN3 (i = 0, 1) are used for 4-channel scan. Similarly, channels ADiIN0 to ADiIN7 and channels ADiIN0 to ADiIN15 are used for 8-channel scan and 16-channel scan, respectively. An A-D conversion interrupt request or a DMA transfer request (for the A-D0 converter only) can be generated at completion of one cycle of scan operation. Figure 11.1.5 Operation of A-D Conversion in Scan Mode (for 4-channel Scan) Note 1:A-D0 conversion start: Software trigger → Started by setting A-D0 conversion start bit to 1_____ Hardware trigger → Started by output event bus 3 or ADTRG signal input A-D1 conversion start: Software trigger → Started by setting A-D1 conversion start bit to 1_____ Hardware trigger → Started by TID1 overflow/underflow or ADTRG signal input Note 2:DMA transfer request: Can be generated for only the A-D0 converter. A-D CONVERTERS ADiIN0 Completed here when operating in single-shot scan mode ADiDT010-bit A-Di data register ADiIN1 ADiIN2 ADiIN3 ADiDT1 ADiDT2 ADiDT3 During continuous scan mode <4-channel scan> i=0,1 A-D conversion interrupt request or DMA transfer request (Note 2) Conversion starts (Note 1)

11-9 32170/32174 Group User's Manual (Rev. 2.1) Figure 11.1.6 Operation of A-D Conversion in Scan Mode (for 8-channel/16-channel Scan) Note 1:A-D0 conversion start: Software trigger → Started by setting A-D0 conversion start bit to 1_____ Hardware trigger → Started by output event bus 3 or ADTRG signal input A-D1 conversion start: Software trigger → Started by setting A-D1 conversion start bit to 1_____ Hardware trigger → Started by TID1 overflow/underflow or ADTRG signal input Note 2:DMA transfer request: Can be generated for only the A-D0 converter. A-D CONVERTERS i=0,1 Completed here when operating in single-shot scan mode 10-bit A-Di data register During continuous scan mode <8-channel scan> A-D conversion interrupt request or DMA transfer request (Note 2) Conversion starts (Note 1) Completed here when operating in single-shot scan mode 10-bit A-Di data register During continuous scan mode <16-channel scan> Conversion starts (Note 1)

11-10 32170/32174 Group User's Manual (Rev. 2.1) Table 11.1.2 Registers in Which Scan Mode A-D Conversion Results Are Stored Scan loop Selected channels Selected channels A-D conversion result selection for single-shot scan for continue scan storage register 4-channel scan ADiIN0 ADiIN0 10-bit A-Di Data Register 0 ADiIN1 ADiIN1 10-bit A-Di Data Register 1 ADiIN2 ADiIN2 10-bit A-Di Data Register 2 ADiIN3 ADiIN3 10-bit A-Di Data Register 3 Completed ADiIN0 10-bit A-Di Data Register 0 (Repeated until forcibly halted) 8-channel scan ADiIN0 ADiIN0 10-bit A-Di Data Register 0 ADiIN1 ADiIN1 10-bit A-Di Data Register 1 ADiIN2 ADiIN2 10-bit A-Di Data Register 2 ADiIN3 ADiIN3 10-bit A-Di Data Register 3 ADiIN4 ADiIN4 10-bit A-Di Data Register 4 ADiIN5 ADiIN5 10-bit A-Di Data Register 5 ADiIN6 ADiIN6 10-bit A-Di Data Register 6 ADiIN7 ADiIN7 10-bit A-Di Data Register 7 Completed ADiIN0 10-bit A-Di Data Register 0 (Repeated until forcibly halted) 16-channel scan ADiIN0 ADiIN0 10-bit A-Di Data Register 0 ADiIN1 ADiIN1 10-bit A-Di Data Register 1 ADiIN2 ADiIN2 10-bit A-Di Data Register 2 ADiIN3 ADiIN3 10-bit A-Di Data Register 3 ADiIN4 ADiIN4 10-bit A-Di Data Register 4 ADiIN5 ADiIN5 10-bit A-Di Data Register 5 ADiIN6 ADiiN6 10-bit A-Di Data Register 6 ADiIN7 ADiIN7 10-bit A-Di Data Register 7 ADiIN8 ADiIN8 10-bit A-Di Data Register 8 ADiIN9 ADiIN9 10-bit A-Di Data Register 9 ADiIN10 ADiIN10 10-bit A-Di Data Register 10 ADiIN11 ADiIN11 10-bit A-Di Data Register 11 ADiIN12 ADiIN12 10-bit A-Di Data Register 12 ADiIN13 ADiIN13 10-bit A-Di Data Register 13 ADiIN14 ADiIN14 10-bit A-Di Data Register 14 ADiIN15 ADiIN15 10-bit A-Di Data Register 15 Completed ADiIN0 10-bit A-D Data Register 0 (Repeated until forcibly halted) (i=0, 1)

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11-11 32170/32174 Group User's Manual (Rev. 2.1)

11.1.3 Special Operation Modes

(1) Forcible single mode execution during scan mode This special operation mode forcibly executes single mode conversion (A-D conversion or comparate) in a specified channel during scan mode operation. For A-D conversion mode, the conversion result is stored in the 10-bit A-D Data Register corresponding to the specified channel. For comparate mode, the conversion result is stored in the 10-bit A-D Comparate Data Register. When the A-D conversion or comparate operation in the specified channel is completed, scan mode A-D conversion is restarted from where it was canceled during scan operation. To start single mode conversion during scan mode operation in software, choose a software trigger using the Single Mode Register 0 A-D conversion start trigger select bit. Then, for A-D conversion, set the said register's A-D conversion start bit to 1, or for comparate mode, write a comparison value to the A-D Successive Approximation Register (AD0SAR or AD1SAR) during scan mode operation. To start single mode conversion during scan mode operation in hardware, choose a hardware trigger using the Single Mode Register 0 A-D conversion start trigger select bit. Then enter the_____ hardware trigger selected with the said register (ADTRG signal or output event bus 3 for the A-D0_____ converter, or ADTRG signal or TID1 overflow/underflow for the A-D1 converter). An A-D conversion interrupt request or a DMA transfer request (for the A-D0 converter only) can be generated at completion of conversion in the specified channel, or at completion of one cycle of scan operation. Figure 11.1.7 Forcible Single Mode Execution during Scan Mode Note 1: The canceled convert operation in channel 2 is reexecuted from the beginning. Note 2: DMA transfer request: Can be generated for only the A-D0 converter. A-D CONVERTERS A-D conversion interrupt request or DMA transfer request (Note 2) ADiIN0 ADiDT010-bit A-Di data register Scan mode conversion starts ADiIN1 ADiDT1 ADiDT5 <To perform single mode conversion on ADiIN5 during ADiIN2 conversion in 4-channel single-shot scan mode> CompletedADiIN2 ADiIN3 ADiDT2 ADiDT3 ADiIN5 Forcible single mode execution starts (Note 1) ADiIN2 i=0,1

11-12 32170/32174 Group User's Manual (Rev. 2.1) (2) Scan mode start after single mode execution This special operation mode starts scan operation subsequently after executing conversion in single mode (A-D conversion or comparate). To start this mode in software, choose a software trigger using the Scan Mode Register 0 A-D conversion start trigger select bit. Then set the said register's A-D conversion start bit to 1 during single mode conversion operation. To start this mode in hardware, choose a hardware trigger using the Scan Mode Register 0 A-D conversion start trigger select bit. Then enter the hardware trigger selected with the said register (ADTRG signal or output event bus 3 for the A-D0 converter, or ADTRG signal or TID1 overflow/ underflow for the A-D1 converter). If after selecting a hardware trigger using the A-D conversion start trigger select bit in both Single Mode Register 0 and Scan Mode Register 0, you enter a hardware trigger (ADTRG signal or output event bus 3 for the A-D0 converter, or ADTRG signal or TID1 overflow/underflow for the A- D1 converter), the device first performs single mode conversion and then scan mode conversion subsequently after executing the single mode conversion. An A-D conversion interrupt request or a DMA transfer request (for the A-D0 converter only) can be generated at completion of single mode conversion in the specified channel, or at completion of one cycle of scan operation. Figure 11.1.8 Scan Mode Start after Single Mode Execution Note: DMA transfer request: Can be generated for only the A-D0 converter. A-D CONVERTERS <To start 4-channel single-shot scan mode subsequently after single mode conversion on ADiN5 > ADiIN2 ADiIN3 ADiDT2 ADiDT3 ADiIN5Single mode conversion starts i=0,1 A-D conversion interrupt request or DMA transfer request (Note) 10-bit A-Di data register Completed

11-13 32170/32174 Group User's Manual (Rev. 2.1) (3) Conversion restart This special operation mode stops operation being executed in single mode or scan mode and reexecutes the operation from the beginning. When in single mode, set the Single Mode Register 0 A-D conversion start bit to 1 again or enter a hardware trigger (ADTRG signal or output event bus 3 for the A-D0 converter, or ADTRG signal or TID1 overflow/underflow for the A-D1 converter) during scan or comparate operation, and the operation being executed is halted and reexecuted from the beginning. When in scan mode, set the Single Mode Register 0 A-D conversion start bit to 1 again or enter a hardware trigger (ADTRG signal or output event bus 3 for the A-D0 converter, or ADTRG signal or TID1 overflow/underflow for the A-D1 converter) during scan or comparate operation, and the channel being converted is canceled and A-D conversion is reexecuted beginning with channel Figure 11.1.9 Restarting Conversion during Single Mode Operation Figure 11.1.10 Restarting Conversion during Scan Operation Note: DMA transfer request: Can be generated for only the A-D0 converter. A-D CONVERTERS <To restart single mode ADiIN5 conversion> Single mode ADiIN5 conversion restarts ADiIN5 ADiIN5 i=0,1 A-D conversion interrupt request or DMA transfer request (Note) 10-bit A-Di data register Completed ADiIN0 ADiDT0 Scan mode conversion starts ADiIN1 ADiDT1 <To restart operation during ADiIN2 conversion in 4-channel single-shot scan mode > ADiIN2 ADiIN3 ADiDT2 ADiDT3 Scan mode restarts ADiIN2 ADiIN0 ADiDT0 ADiIN1 ADiDT1 i=0,1 A-D conversion interrupt request or DMA transfer request (Note) 10-bit A-Di data register Completed Note: DMA transfer request: Can be generated for only the A-D0 converter.

11-14 32170/32174 Group User's Manual (Rev. 2.1)

11.1.4 A-D Converter Interrupt and DMA Transfer Requests

The A-D converters can generate an A-D conversion interrupt request or a DMA transfer request (for the A-D0 converter only) each time A-D conversion, comparate operation, single-shot scan, or one cycle of continuous scan mode is completed. Single Mode Register 0 and Scan Mode Register 0 are used to select between an A-D conversion interrupt request and a DMA transfer request (for the A-D0 converter only). Note: For the A-D1 converter, this bit selects to enable or disable interrupt requests and cannot select DMA transfer requests. Figure 11.1.11 Selecting between Interrupt Request and DMA Transfer Request A-D CONVERTERS (when one cycle of scan completed) Single mode (when A-D conversion or comparate operation completed) A-D0 conversion interrupt request (To the interrupt controller) DMA transfer request (To the DMAC) A-D0 Scan Mode Register 0 interrupt request /DMA transfer request select bit (Note) A-D0 Single Mode Register 0 interrupt request /DMA transfer request select bit (Note)

11-15 32170/32174 Group User's Manual (Rev. 2.1)

11.2 A-D Converter Related Registers

The diagrams below show an A-D converter related register map. Figure 11.2.1 A-D Converter Related Register Map (1/4) A-D CONVERTERS H’0080 0084 H’0080 0086 H’0080 0088 H’0080 008A H’0080 008C H’0080 0080 H’0080 0082 A-D0 Single Mode Register 0 (AD0SIM0) Address D0 D7 +0 Address +1 Address D8 D15 10-bit A-D0 Data Register 0 (AD0DT0) A-D0 Scan Mode Register 0 (AD0SCM0) H’0080 0090 H’0080 0092 H’0080 0094 H’0080 0096 H’0080 0098 H’0080 009A H’0080 009C H’0080 009E H’0080 00A0 H’0080 00A2 H’0080 00A4 H’0080 00A6 H’0080 00A8 H’0080 00AA H’0080 00AC H’0080 00AE A-D0 Successive Approximation Register (AD0SAR) A-D0 Comparate Data Register (AD0CMP) Note: The registers enclosed in thick frames must always be accessed in halfwords. Blank addresses are reserved. A-D0 Single Mode Register 1 (AD0SIM1) A-D0 Scan Mode Register 1 (AD0SCM1) 10-bit A-D0 Data Register 1 (AD0DT1) 10-bit A-D0 Data Register 2 (AD0DT2) 10-bit A-D0 Data Register 3 (AD0DT3) 10-bit A-D0 Data Register 4 (AD0DT4) 10-bit A-D0 Data Register 5 (AD0DT5) 10-bit A-D0 Data Register 6 (AD0DT6) 10-bit A-D0 Data Register 7 (AD0DT7) 10-bit A-D0 Data Register 8 (AD0DT8) 10-bit A-D0 Data Register 9 (AD0DT9) 10-bit A-D0 Data Register 10 (AD0DT10) 10-bit A-D0 Data Register 11 (AD0DT11) 10-bit A-D0 Data Register 12 (AD0DT12) 10-bit A-D0 Data Register 13 (AD0DT13) 10-bit A-D0 Data Register 14 (AD0DT14) 10-bit A-D0 Data Register 15 (AD0DT15)

11-16 32170/32174 Group User's Manual (Rev. 2.1) Figure 11.2.2 A-D Converter Related Register Map (2/4) A-D CONVERTERS H’0080 00D2 H’0080 00D4 H’0080 00D6 H’0080 00D8 H’0080 00DA H’0080 00D0 Address D0 D7 +0 Address +1 Address D8 D15 H’0080 00DC H’0080 00DE H’0080 00E0 H’0080 00E2 H’0080 00E4 H’0080 00E6 H’0080 00E8 H’0080 00EA H’0080 00EC H’0080 00EE 8-bit A-D0 Data Register 15 (AD08DT15) Blank addresses are reserved. 8-bit A-D0 Data Register 14 (AD08DT14) 8-bit A-D0 Data Register 13 (AD08DT13) 8-bit A-D0 Data Register 12 (AD08DT12) 8-bit A-D0 Data Register 11 (AD08DT11) 8-bit A-D0 Data Register 10 (AD08DT10) 8-bit A-D0 Data Register 9 (AD08DT9) 8-bit A-D0 Data Register 8 (AD08DT8) 8-bit A-D0 Data Register 7 (AD08DT7) 8-bit A-D0 Data Register 6 (AD08DT6) 8-bit A-D0 Data Register 5 (AD08DT5) 8-bit A-D0 Data Register 4 (AD08DT4) 8-bit A-D0 Data Register 3 (AD08DT3) 8-bit A-D0 Data Register 2 (AD08DT2) 8-bit A-D0 Data Register 1 (AD08DT1) 8-bit A-D0 Data Register 0 (AD08DT0)

11-17 32170/32174 Group User's Manual (Rev. 2.1) Figure 11.2.3 A-D Converter Related Register Map (3/4) A-D CONVERTERS H’0080 0A84 H’0080 0A86 H’0080 0A88 H’0080 0A8A H’0080 0A8C H’0080 0A80 H’0080 0A82 D0 D7 D8 D15 H’0080 0A90 H’0080 0A92 H’0080 0A94 H’0080 0A96 H’0080 0A98 H’0080 0A9A H’0080 0A9C H’0080 0A9E H’0080 0AA0 H’0080 0AA2 H’0080 0AA4 H’0080 0AA6 H’0080 0AA8 H’0080 0AAA H’0080 0AAC H’0080 0AAE A-D1 Single Mode Register 0 (AD1SIM0) Address +0 Address +1 Address 10-bit A-D1 Data Register 0 (AD1DT0) A-D1 Scan Mode Register 0 (AD1SCM0) A-D1 Successive Approximation Register (AD1SAR) A-D1 Comparate Data Register (AD1CMP) Note: The registers enclosed in thick frames must always be accessed in halfwords. Blank addresses are reserved. A-D1 Single Mode Register 1 (AD1SIM1) A-D1 Scan Mode Register 1 (AD1SCM1) 10-bit A-D1 Data Register 1 (AD1DT1) 10-bit A-D1 Data Register 2 (AD1DT2) 10-bit A-D1 Data Register 3 (AD1DT3) 10-bit A-D1 Data Register 4 (AD1DT4) 10-bit A-D1 Data Register 5 (AD1DT5) 10-bit A-D1 Data Register 6 (AD1DT6) 10-bit A-D1 Data Register 7 (AD1DT7) 10-bit A-D1 Data Register 8 (AD1DT8) 10-bit A-D1 Data Register 9 (AD1DT9) 10-bit A-D1 Data Register 10 (AD1DT10) 10-bit A-D1 Data Register 11 (AD1DT11) 10-bit A-D1 Data Register 12 (AD1DT12) 10-bit A-D1 Data Register 13 (AD1DT13) 10-bit A-D1 Data Register 14 (AD1DT14) 10-bit A-D1 Data Register 15 (AD1DT15)

11-18 32170/32174 Group User's Manual (Rev. 2.1) Figure 11.2.4 A-D Converter Related Register Map (4/4) A-D CONVERTERS H’0080 0AD2 H’0080 0AD4 H’0080 0AD6 H’0080 0AD8 H’0080 0ADA H’0080 0AD0 D0 D7 D8 D15 H’0080 0ADC H’0080 0ADE H’0080 0AE0 H’0080 0AE2 H’0080 0AE4 H’0080 0AE6 H’0080 0AE8 H’0080 0AEA H’0080 0AEC H’0080 0AEE Address +0 Address +1 Address 8-bit A-D1 Data Register 15 (AD18DT15) Blank addresses are reserved. 8-bit A-D1 Data Register 14 (AD18DT14) 8-bit A-D1 Data Register 13 (AD18DT13) 8-bit A-D1 Data Register 12 (AD18DT12) 8-bit A-D1 Data Register 11 (AD18DT11) 8-bit A-D1 Data Register 10 (AD18DT10) 8-bit A-D1 Data Register 9 (AD18DT9) 8-bit A-D1 Data Register 8 (AD18DT8) 8-bit A-D1 Data Register 7 (AD18DT7) 8-bit A-D1 Data Register 6 (AD18DT6) 8-bit A-D1 Data Register 5 (AD18DT5) 8-bit A-D1 Data Register 4 (AD18DT4) 8-bit A-D1 Data Register 3 (AD18DT3) 8-bit A-D1 Data Register 2 (AD18DT2) 8-bit A-D1 Data Register 1 (AD18DT1) 8-bit A-D1 Data Register 0 (AD18DT0)

11-19 32170/32174 Group User's Manual (Rev. 2.1)

11.2.1 A-D Single Mode Register 0

I A-D0 Single Mode Register 0 (AD0SIM0) <Address: H'0080 0080> <When reset:H'04> D Bit Name Function R W 0,1 No functions assigned 0 –

2 AD0STRG

0: ADTRG signal input (A-D0 hardware trigger selection) 1: Output event bus 3

3 AD0SSEL 0: Software trigger

(A-D0 conversion start trigger selection) 1: Hardware trigger

4 AD0SREQ 0: A-D0 interrupt request

(Interrupt request/DMA transfer request selection)1: DMA transfer request

5 AD0SCMP 0: A-D0 conversion/comparate in progress –

(A-D0 conversion/comparate completed) 1: A-D0 conversion/comparate completed

6 AD0SSTP 0: Performs no operation 0

(A-D0 conversion stop) 1: Stops A-D0 conversion

7 AD0SSTT 0: Performs no operation 0

(A-D0 conversion start) 1: Starts A-D0 conversion A-D0 Single Mode Register 0 is used to control operation of the A-D0 converter during single mode (including special mode "Forcible single mode execution during scan mode"). D 0 123456 D 7 AD0STRG AD0SSEL AD0SREQ AD0SCMP AD0SSTP AD0SSTT A-D CONVERTERS

11-20 32170/32174 Group User's Manual (Rev. 2.1) I A-D1 Single Mode Register 0 (AD1SIM0) <Address: H'0080 0A80> A-D1 Single Mode Register 0 is used to control operation of the A-D1 converter during single mode (including special mode "Forcible single mode execution during scan mode"). <When reset:H'04> D Bit Name Function R W 0,1 No functions assigned 0 –

2 AD1STRG

0: ADTRG signal input (A-D1 hardware trigger selection) 1: TID1 overflow/underflow

3 AD1SSEL 0: Software trigger

(A-D1 conversion start trigger selection) 1: Hardware trigger

4 AD1SREQ 0: Enables A-D1 interrupt request

(Interrupt request) 1: Disables A-D1 interrupt request

5 AD1SCMP 0: A-D1 conversion/comparate in progress –

(A-D1 conversion/comparate completed) 1: A-D1 conversion/comparate completed

6 AD1SSTP 0: Performs no operation 0

(A-D1 conversion stop) 1: Stops A-D1 conversion

7 AD1SSTT 0: Performs no operation 0

(A-D1 conversion start) 1: Starts A-D1 conversion D 0 123456 D 7 AD1STRG AD1SSEL AD1SREQ AD1SCMP AD1SSTP AD1SSTT A-D CONVERTERS

11-21 32170/32174 Group User's Manual (Rev. 2.1) (1) ADnSTRG (A-Dn hardware trigger selection) bit (D2) When starting A-D conversion of the A-Dn converter in hardware, this bit selects whether to use_____ external ADTRG signal input or MJT output (output event bus 3 for A-D0, or TID1 overflow/ underflow for A-D1) to start the operation. The content of this bit is ignored when the ADnSSEL (A-Dn conversion start trigger selection) bit is set to choose a software trigger. When using the_____ _____ ADTRG pin for a start trigger, not that if A-D conversion is completed while the ADTRG pin input is held low, new A-D conversion is not started. (2) ADnSSEL (A-Dn conversion start trigger selection) bit (D3) This bit selects whether to use a software or hardware trigger to start A-Dn conversion during single mode. When you choose a software trigger, A-D conversion is started by setting the ADnSSTT (A-Dn conversion start) bit to 1. When you choose a hardware trigger, A-D conversion is started for the cause of start selected by the ADnSTRG (hardware trigger selection) bit. (3) ADnSREQ (A-Dn interrupt request/DMA transfer request selection) bit (D4) For the A-D0 converter (AD0SIM0), this bit selects whether to request an A-D0 conversion interrupt or DMA transfer when single mode operation (A-D conversion or comparate) is completed. For the A-D1 converter (AD1SIM0), this bit selects whether to enable or disable an A- D0 conversion interrupt when single mode operation (A-D conversion or comparate) is completed. (4) ADnSCMP (A-Dn conversion/comparate completion) bit (D5) This is a read-only bit, which when reset is 1. This bit is 0 when the A-Dn converter is performing single mode operation (A-D conversion or comparate) and set to 1 when the operation is completed. This bit also is set to 1 when A-D conversion or comparate operation is forcibly terminated by setting the ADnSSTT (A-Dn conversion stop) bit to 1 during A-D conversion or comparate operation. (5) ADnSSTP (A-Dn conversion stop) bit (D6) Single mode operation (A-D conversion or comparate) of the A-Dn converter can be halted by setting this bit to 1 while the operation is in progress. Manipulation of this bit is ignored when single mode is idle or when scan mode operation is under way. Operation is halted immediately by a write to this bit, and when you read the A-Dn Successive Approximation Register after being halted, the content you get is the value in the middle of conversion. (Not transferred to the A-Dn Data Register.) If the A-Dn conversion start bit and A-Dn conversion stop bit are set to 1 at the same time, the A- Dn conversion stop bit has priority. If this bit is set to 1 while operating in single mode during special mode "Forcible single mode execution during scan mode," only single mode conversion is halted and scan mode operation is restarted. A-D CONVERTERS

11-22 32170/32174 Group User's Manual (Rev. 2.1) (6) ADnSSTT (A-Dn conversion start) bit (D7) When this bit is set to 1 while a software trigger has been selected by the ADnSSEL (A-Dn conversion start trigger selection) bit, the A-Dn converter starts A-D conversion. If the A-Dn conversion start bit and A-Dn conversion stop bit are set to 1 at the same time, the A- Dn conversion stop bit has priority. If this bit is set to 1 again during single mode conversion, special operation mode "Forcible single mode execution during scan mode" is entered into, so that the channel being converted in scan mode is canceled and single mode conversion is performed. When the single mode conversion finishes, scan mode A-D conversion is restarted beginning with the canceled channel. A-D CONVERTERS

11-23 32170/32174 Group User's Manual (Rev. 2.1)

11.2.2 A-D Single Mode Register 1

I A-D0 Single Mode Register 1 (AD0SIM1) <Address: H'0080 0081> W= : Only writing a 0 is effective; when you write a 1, device operation cannot be guaranteed. A-D0 Single Mode Register 0 is used to control operation of the A-D0 converter during single mode (including special mode "Forcible single mode execution during scan mode"). <When reset:H'00> D Bit Name Function R W

8 AD0SMSL 0: A-D0 conversion mode

(A-D0 conversion mode selection) 1: Comparator mode

9 AD0SSPD 0: Normal rate

(A-D0 conversion rate selection) 1: Double rate 10,11 No functions assigned 0 12-15 AN0SEL 0000: Selects AD0IN0 (Analog input pin selection) 0001: Selects AD0IN1 0010: Selects AD0IN2 0011: Selects AD0IN3 0100: Selects AD0IN4 0101: Selects AD0IN5 0110: Selects AD0IN6 0111: Selects AD0IN7 1000: Selects AD0IN8 1001: Selects AD0IN9 1010: Selects AD0IN10 1011: Selects AD0IN11 1100: Selects AD0IN12 1101: Selects AD0IN13 1110: Selects AD0IN14 1111: Selects AD0IN15 D 8 9 1 01 11 21 31 4 D 1 5 AD0SMSL AD0SSPD AN0SEL A-D CONVERTERS

11-24 32170/32174 Group User's Manual (Rev. 2.1) I A-D1 Single Mode Register 1 (AD1SIM1) <Address: H'0080 0A81> W= : Only writing a 0 is effective; when you write a 1, device operation cannot be guaranteed. A-D1 Single Mode Register 0 is used to control operation of the A-D1 converter during single mode (including special mode "Forcible single mode execution during scan mode"). <When reset:H'00> D Bit Name Function R W

8 AD1SMSL 0: A-D1 conversion mode

(A-D1 conversion mode selection) 1: Comparator mode

9 AD1SSPD 0: Normal rate

(A-D1 conversion rate selection) 1: Double rate 10,11 No functions assigned 0 12-15 AN1SEL 0000: Selects AD1IN0 (Analog input pin selection) 0001: Selects AD1IN1 0010: Selects AD1IN2 0011: Selects AD1IN3 0100: Selects AD1IN4 0101: Selects AD1IN5 0110: Selects AD1IN6 0111: Selects AD1IN7 1000: Selects AD1IN8 1001: Selects AD1IN9 1010: Selects AD1IN10 1011: Selects AD1IN11 1100: Selects AD1IN12 1101: Selects AD1IN13 1110: Selects AD1IN14 1111: Selects AD1IN15 D 8 9 1 01 11 21 31 4 D 1 5 AD1SMSL AD1SSPD AN1SEL A-D CONVERTERS

11-25 32170/32174 Group User's Manual (Rev. 2.1) (1) ADnSMSL (A-Dn conversion mode selection) bit (D8) This bit selects A-D conversion mode for the A-Dn converter during single mode. Setting this bit to 0 selects A-D conversion mode, and setting this bit to 1 selects comparator mode. (2) ADnSSPD (A-Dn conversion rate selection) bit (D9) This bit selects an A-D conversion rate for the A-Dn converter during single mode. Setting this bit to 0 selects a normal speed, and setting this bit to 1 selects a x2 speed (two times normal speed). (3) ANnSEL (analog input pin selection) bits (D12-D15) These bits select analog input pins for the A-Dn converter during single mode. It is the channels selected by these bits that are operated on for A-D conversion or comparate operation. When you read these bits, they show the values written to them. A-D CONVERTERS

11-26 32170/32174 Group User's Manual (Rev. 2.1)

11.2.3 A-D Scan Mode Register 0

I A-D0 Scan Mode Register 0 (AD0SCM0) <Address: H'0080 0084> A-D0 Scan Mode Register 0 is used to control operation of the A-D0 converter during scan mode. <When reset:H'04> D Bit Name Function R W

1 AD0CMSL 0: Single-shot mode

(A-D0 scan mode selection) 1: Continuous mode

2 AD0CTRG

0: ADTRG signal input (A-D0 hardware trigger selection) 1: Output event bus 3

3 AD0CSEL 0: Software trigger

(A-D0 conversion start trigger selection) 1: Hardware trigger

4 AD0CREQ 0: Requests A-D0 interrupt

(Interrupt request/DMA request selection) 1: Requests DMA transfer

5 AD0CCMP 0: A-D0 conversion in progress –

(A-D0 conversion completed) 1: A-D0 conversion completed

6 AD0CSTP 0: Performs no operation 0

(A-D0 conversion stop) 1: Stops A-D0 conversion

7 AD0CSTT 0: Performs no operation 0

(A-D0 conversion start) 1: Starts A-D0 conversion D 0 123456 D 7 AD0CMSL AD0CTRG AD0CSEL AD0CREQAD0CCMP AD0CSTP AD0CSTT A-D CONVERTERS

11-27 32170/32174 Group User's Manual (Rev. 2.1) I A-D1 Scan Mode Register 0 (AD1SCM0) <Address: H'0080 0A84> <When reset:H'04> D Bit Name Function R W

1 AD1CMSL 0: Single-shot mode

(A-D1 scan mode selection) 1: Continuous mode

2 AD1CTRG

0: ADTRG signal input (A-D1 hardware trigger selection) 1: TID1 overflow/underflow

3 AD1CSEL 0: Software trigger

(A-D1 conversion start trigger selection) 1: Hardware trigger

4 AD1CREQ 0: Enables A-D1 interrupt request

(Interrupt request selection) 1: Disables A-D1 interrupt request

5 AD1CCMP 0: A-D1 conversion in progress –

(A-D1 conversion completed) 1: A-D1 conversion completed

6 AD1CSTP 0: Performs no operation 0

(A-D1 conversion stop) 1: Stops A-D1 conversion

7 AD1CSTT 0: Performs no operation 0

(A-D1 conversion start) 1: Starts A-D1 conversion A-D1 Scan Mode Register 0 is used to control operation of the A-D1 converter during scan mode. D 0 123456 D 7 AD1CMSL AD1CTRG AD1CSEL AD1CREQAD1CCMP AD1CSTP AD1CSTT A-D CONVERTERS

11-28 32170/32174 Group User's Manual (Rev. 2.1) (1) ADnCMSL (A-Dn scan mode selection) bit (D1) This bit selects scan mode of the A-Dn converter between single-shot scan and continuous scan. Setting this bit to 0 selects single-shot scan mode, so that the channels selected by the ANnSCAN (scan loop selection) bits are sequentially A-D converted and when A-D conversion in all selected channels are completed, the conversion operation stops. Setting this bit to 1 selects continuous scan mode, so that when operation in single-shot scan mode is completed, the selected channels are A-D converted beginning with the first channel again. This A-D conversion is continued until halted by setting the ADnCSTP (A-Dn conversion stop) bit to 1. (2) ADnCTRG (A-Dn hardware trigger selection) bit (D2) When starting A-D conversion of the A-Dn converter in hardware, this bit selects whether to use external ADTRG signal input or MJT output (output event bus 3 for A-D0, or TID1 overflow/ underflow for A-D1) to start the operation. The content of this bit is ignored when the ADnSSEL (A-Dn conversion start trigger selection) bit is set to choose a software trigger. When using the ADTRG pin for a start trigger, not that if A-D conversion is completed while the ADTRG pin input is held low, new A-D conversion is not started. (3) ADnCSEL (A-Dn conversion start trigger selection) bit (D3) This bit selects whether to use a software or hardware trigger to start A-D conversion of the A-Dn converter during scan mode. When you choose a software trigger, A-D conversion is started by setting the ADnCSTT (A-Dn conversion start) bit to 1. When you choose a hardware trigger, A-D conversion is started for the cause of start selected by the ADnCTRG (hardware trigger selection) bit. (4) ADnCREQ (A-Dn interrupt request/DMA transfer request selection) bit (D4) For the A-D0 converter (AD0SCM0), this bit selects whether to request an A-D0 conversion interrupt or DMA transfer when one cycle of scan operation is completed. For the A-D1 converter (AD1SCM0), this bit selects whether to enable or disable an A-D0 conversion interrupt when one cycle of scan operation is completed. (5) ADnCCMP (A-Dn conversion completion) bit (D5) This is a read-only bit, which when reset is 1. This bit is 0 when the A-Dn converter is performing scan mode A-D conversion and set to 1 when single-shot scan mode is completed, or when continuous scan mode is halted by setting ADnCSTT (A-Dn conversion stop) bit to 1. A-D CONVERTERS

11-29 32170/32174 Group User's Manual (Rev. 2.1) (6) ADnCSTP (A-Dn conversion stop) bit (D6) Scan mode A-D conversion of the A-Dn converter can be halted by setting this bit to 1 while the operation is in progress. This bit is effective only when operating in scan mode. If single mode and scan mode both are active in special operation mode, manipulation of this bit does not affect single mode operation. Scan mode operation is halted immediately by a write to this bit, and the A-D conversion being executed in a channel is aborted in the middle, without transfer to the A-D data register. If the A-Dn conversion start bit and A-Dn conversion stop bit are set to 1 at the same time, the A- Dn conversion stop bit has priority. (7) ADnCSTT (A-Dn conversion start) bit (D7) This bit is used to start scan mode operation of the A-Dn converter in software. This bit is effective only when a software trigger has been selected by the ADnCSEL (A-Dn conversion start trigger selection) bit, and starts A-D conversion when it is set to 1. If the A-Dn conversion start bit and A-Dn conversion stop bit are set to 1 at the same time, the A- Dn conversion stop bit has priority. If this bit is set to 1 again during scan mode conversion, special operation mode "Conversion restart" is entered into, so that scan operation is restarted according to the contents set by Scan Mode Register 0 and Scan Mode Register 1. If this bit is set to 1 again during single mode A-D conversion, special operation mode "Scan mode start after single mode execution" is entered into, so that scan mode operation is started subsequently after single mode is completed. A-D CONVERTERS

11-30 32170/32174 Group User's Manual (Rev. 2.1)

11.2.4 A-D Scan Mode Register 1

I A-D0 Scan Mode Register 1 (AD0SCM1) <Address: H'0080 0085> A-D0 Scan Mode Register 1 is used to control operation of the A-D0 converter during scan mode. <When reset:H'00> D Bit Name Function R W

9 AD0CSPD 0: Normal

(A-D0 conversion rate selection) 1: × 2 10,11 No functions assigned 0 – 12-15 AN0SCAN <When written to> (A-D0 scan loop selection) 01XX: 4-channel scan 10XX: 8-channel scan 11XX: 16-channel scan 00XX: 16-channel scan <When read during conversion> 0000: Converting AD0IN0 0001: Converting AD0IN1 0010: Converting AD0IN2 0011: Converting AD0IN3 0100: Converting AD0IN4 0101: Converting AD0IN5 0110: Converting AD0IN6 0111: Converting AD0IN7 1000: Converting AD0IN8 1001: Converting AD0IN9 1010: Converting AD0IN10 1011: Converting AD0IN11 1100: Converting AD0IN12 1101: Converting AD0IN13 1110: Converting AD0IN14 1111: Converting AD0IN15 D 8 9 1 01 11 21 31 4 D 1 5 AD0CSPD AN0SCAN A-D CONVERTERS

11-31 32170/32174 Group User's Manual (Rev. 2.1) D 8 9 1 01 11 21 31 4 D 1 5 AD1CSPD AN1SCAN I A-D1 Scan Mode Register 1 (AD1SCM1) <Address: H'0080 0A85> <When reset:H'00> D Bit Name Function R W

9 AD1CSPD 0: Normal

(A-D1 conversion rate selection) 1: × 2 10,11 No functions assigned 0 – 12-15 AN1SCAN <When written to> (A-D1 scan loop selection) 01XX: 4-channel scan 10XX: 8-channel scan 11XX: 16-channel scan 00XX: 16-channel scan <When read during conversion> 0000: Converting AD1IN0 0001: Converting AD1IN1 0010: Converting AD1IN2 0011: Converting AD1IN3 0100: Converting AD1IN4 0101: Converting AD1IN5 0110: Converting AD1IN6 0111: Converting AD1IN7 1000: Converting AD1IN8 1001: Converting AD1IN9 1010: Converting AD1IN10 1011: Converting AD1IN11 1100: Converting AD1IN12 1101: Converting AD1IN13 1110: Converting AD1IN14 1111: Converting AD1IN15 A-D1 Scan Mode Register 1 is used to control operation of the A-D1 converter during scan mode. A-D CONVERTERS

11-32 32170/32174 Group User's Manual (Rev. 2.1) (1) ADnCSPD (A-Dn conversion rate selection) bit (D9) This bit selects an A-D conversion rate for the A-Dn converter during scan mode. Setting this bit to 0 selects a normal speed, and setting this bit to 1 selects a x2 speed (two times normal speed). (2) ANnSCAN (A-Dn scan loop selection) bits (D12-D15) The ANnSCAN (A-Dn scan loop selection) bits set the channels to be scanned during scan mode of the A-Dn converter. In this case, writes to D14 and D15 have no effect. The ANnSCAN (A-Dn scan loop selection) bits when read during scan operation show the status of the A-Dn converter, indicating the channel it is converting. The value read from these bits during single mode are always "B'0000." If A-D conversion is halted by setting Scan Mode Register 0 ADnCSTP (A-Dn conversion stop) bit to 1 during scan mode execution, the bits when read at this time show the value of the channel in which the A-D conversion has been canceled. Also, if halted during single mode conversion in special operation mode "Forcible single mode execution during scan mode," the bits when read at this time show the value of the channel in which the A-D conversion has been canceled in the middle of scan. A-D CONVERTERS

11-33 32170/32174 Group User's Manual (Rev. 2.1)

11.2.5 A-D Successive Approximation Register

I A-D0 Successive Approximation Register (AD0SAR) <Address: H'0080 0088> Note: This register must always be accessed in halfwords. The A-D0 Successive Approximation Register (AD0SAR), when in A-D conversion mode, is used to read out the conversion result of the A-Dn converter, and when in comparator mode, it is used to write a comparison value. In A-D conversion mode, the successive approximation method is used to perform A-D conversion. With this method, the reference voltage VREF and analog input voltages are sequentially compared bitwise beginning with the high-order side, and the comparison result is set in the A-D0 Successive Approximation Register (AD0SAR) bits (D6-D15). After the A-D conversion is completed, the value of this register is transferred to the 10-bit A-D0 Data Register (AD0DTn) corresponding to the converted channel. When you read this register in the middle of A-D conversion, you see the result in the middle of conversion. In comparator mode, write a comparison value (the value to be compared in comparate operation) to this register. Simultaneously with a write to this register, comparate operation with the analog input pin that has been set by Single Mode Register 1 starts. After comparate operation, the result is stored in the A-D0 Comparate Data Register (AD0CMP). Use the calculation formula shown below to find the comparison value to be written to the A-D0 Successive Approximation Register (AD0SAR) during comparator mode. <When reset:Indeterminate> D Bit Name Function R W 0-5 No functions assigned 0 – 6-15 AD0SAR • A-D successive approximation value (A-D0 successive approximation (A-D conversion mode) value/comparison value) • Comparison value (comparator mode) Comparate comparison voltage [V] VREF0 input voltage [V]Comparison value = H'3FF × D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD0SAR A-D CONVERTERS

11-34 32170/32174 Group User's Manual (Rev. 2.1) I A-D1 Successive Approximation Register (AD1SAR) <Address: H'0080 0A88> Note: This register must always be accessed in halfwords. The A-D1 Successive Approximation Register (AD1SAR), when in A-D conversion mode, is used to read out the conversion result of the A-D1 converter, and when in comparator mode, it is used to write a comparison value. In A-D conversion mode, the successive approximation method is used to perform A-D conversion. With this method, the reference voltage VREF and analog input voltages are sequentially compared bitwise beginning with the high-order side, and the comparison result is set in the A- D1Successive Approximation Register (AD1SAR) bits (D6-D15). After the A-D conversion is completed, the value of this register is transferred to the 10-bit A-D1 Data Register (AD1DTn) corresponding to the converted channel. When you read this register in the middle of A-D conversion, you see the result in the middle of conversion. In comparator mode, write a comparison value (the value to be compared in comparate operation) to this register. Simultaneously with a write to this register, comparate operation with the analog input pin that has been set by Single Mode Register 1 starts. After comparate operation, the result is stored in the A-D1 Comparate Data Register (AD1CMP). Use the calculation formula shown below to find the comparison value to be written to the A- D1Successive Approximation Register (AD1SAR) during comparator mode. <When reset:Indeterminate> D Bit Name Function R W 0-5 No functions assigned 0 – 6-15 AD1SAR • A-D successive approximation value (A-D1 successive approximation (A-D conversion mode) value/comparison value) • Comparison value (comparator mode) Comparate comparison voltage [V] VREF1 input voltage [V]Comparison value = H'3FF × D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD1SAR A-D CONVERTERS

11-35 32170/32174 Group User's Manual (Rev. 2.1)

11.2.6 A-D0 Comparate Data Register

I A-D0 Comparate Data Register (AD0CMP) <Address: H'0080 008C> A-D CONVERTERS Note 1: This register must always be accessed in halfwords. Note 2: During comparator mode, each bit corresponds to channels 0 through 15. When comparator mode is selected by setting the A-D0 Single Mode Register 1 AD0SMSL (A-D0 conversion mode selection) bit, the selected analog input value is compared with the value written to the A-D0 Successive Approximation Register, with the result stored in the corresponding bit of this comparate data register. The bit is 0 when the analog input voltage > comparison voltage, and is 1 when the analog input voltage < comparison voltage. <When reset:Indeterminate> D Bit Name Function R W 0-15 AD0CMP0-AD0CMP15 (Note 2) 0: Analog input voltage > comparison voltage – (A-D0 comparate result flag) 1: Analog input voltage < comparison voltage D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD0 CMP12 AD0 CMP11 AD0 CMP9 AD0 CMP8 AD0 CMP7 AD0 CMP5 AD0 CMP4 AD0 CMP3 AD0 CMP2 AD0 CMP1 AD0 CMP0 AD0 CMP15 AD0 CMP14 AD0 CMP13 AD0 CMP10 AD0 CMP6

11-36 32170/32174 Group User's Manual (Rev. 2.1) I A-D1 Comparate Data Register (AD1CMP) <Address: H'0080 0A8C> Note 1: This register must always be accessed in halfwords. Note 2: During comparator mode, each bit corresponds to channels 0 through 15. When comparator mode is selected by setting the A-D1 Single Mode Register 1 AD1SMSL (A-D1 conversion mode selection) bit, the selected analog input value is compared with the value written to the A-D0 Successive Approximation Register, with the result stored in the corresponding bit of this comparate data register. The bit is 0 when the analog input voltage > comparison voltage, and is 1 when the analog input voltage < comparison voltage. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD1 CMP12 AD1 CMP11 AD1 CMP9 AD1 CMP8 AD1 CMP7 AD1 CMP5 AD1 CMP4 AD1 CMP3 AD1 CMP2 AD1 CMP1 AD1 CMP0 AD1 CMP15 AD1 CMP14 AD1 CMP13 AD1 CMP10 AD1 CMP6 <When reset:Indeterminate> D Bit Name Function R W 0-15 AD1CMP0-AD1CMP15 (Note 2) 0: Analog input voltage > comparison voltage – (A-D1 comparate result flag) 1: Analog input voltage < comparison voltage A-D CONVERTERS

11-37 32170/32174 Group User's Manual (Rev. 2.1) 11.2.7 10-bit A-D Data Registers I 10-bit A-D0 Data Register 0 (AD0DT0) <Address: H'0080 0090> I 10-bit A-D0 Data Register 1 (AD0DT1) <Address: H'0080 0092> I 10-bit A-D0 Data Register 2 (AD0DT2) <Address: H'0080 0094> I 10-bit A-D0 Data Register 3 (AD0DT3) <Address: H'0080 0096> I 10-bit A-D0 Data Register 4 (AD0DT4) <Address: H'0080 0098> I 10-bit A-D0 Data Register 5 (AD0DT5) <Address: H'0080 009A> I 10-bit A-D0 Data Register 6 (AD0DT6) <Address: H'0080 009C> I 10-bit A-D0 Data Register 7 (AD0DT7) <Address: H'0080 009E> I 10-bit A-D0 Data Register 8 (AD0DT8) <Address: H'0080 00A0> I 10-bit A-D0 Data Register 9 (AD0DT9) <Address: H'0080 00A2> I 10-bit A-D0 Data Register 10 (AD0DT10) <Address: H'0080 00A4> I 10-bit A-D0 Data Register 11 (AD0DT11) <Address: H'0080 00A6> I 10-bit A-D0 Data Register 12 (AD0DT12) <Address: H'0080 00A8> I 10-bit A-D0 Data Register 13 (AD0DT13) <Address: H'0080 00AA> I 10-bit A-D0 Data Register 14 (AD0DT14) <Address: H'0080 00AC> I 10-bit A-D0 Data Register 15 (AD0DT15) <Address: H'0080 00AE> Note: This register must always be accessed in halfwords. In single mode of the A-D0 converter, the result of A-D conversion is stored in the 10-bit A-D0 Data Register for each corresponding channel. In single-shot and continuous scan modes, the content of the A-D0 Successive Approximation Register is transferred to the 10-bit A-D Data Register for the corresponding channel every time the A-D conversion in each channel is completed. Each 10-bit A- D Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time. <When reset:Indeterminate> D Bit Name Function R W 0-5 No functions assigned 0 – 6-15 AD0DT0-AD0DT15 A-D conversion result – (A-D0 data) D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD0DT0-AD0DT15 A-D CONVERTERS

11-38 32170/32174 Group User's Manual (Rev. 2.1) I 10-bit A-D1 Data Register 0 (AD1DT0) <Address: H'0080 0A90> I 10-bit A-D1 Data Register 1 (AD1DT1) <Address: H'0080 0A92> I 10-bit A-D1 Data Register 2 (AD1DT2) <Address: H'0080 0A94> I 10-bit A-D1 Data Register 3 (AD1DT3) <Address: H'0080 0A96> I 10-bit A-D1 Data Register 4 (AD1DT4) <Address: H'0080 0A98> I 10-bit A-D1 Data Register 5 (AD1DT5) <Address: H'0080 0A9A> I 10-bit A-D1 Data Register 6 (AD1DT6) <Address: H'0080 0A9C> I 10-bit A-D1 Data Register 7 (AD1DT7) <Address: H'0080 0A9E> I 10-bit A-D1 Data Register 8 (AD1DT8) <Address: H'0080 0AA0> I 10-bit A-D1 Data Register 9 (AD1DT9) <Address: H'0080 0AA2> I 10-bit A-D1 Data Register 10 (AD1DT10) <Address: H'0080 0AA4> I 10-bit A-D1 Data Register 11 (AD1DT11) <Address: H'0080 0AA6> I 10-bit A-D1 Data Register 12 (AD1DT12) <Address: H'0080 0AA8> I 10-bit A-D1 Data Register 13 (AD1DT13) <Address: H'0080 0AAA> I 10-bit A-D1 Data Register 14 (AD1DT14) <Address: H'0080 0AAC> I 10-bit A-D1 Data Register 15 (AD1DT15) <Address: H'0080 0AAE> Note: This register must always be accessed in halfwords. In single mode of the A-D1 converter, the result of A-D conversion is stored in the 10-bit A-D1 Data Register for each corresponding channel. In single-shot and continuous scan modes, the content of the A-D1 Successive Approximation Register is transferred to the 10-bit A-D Data Register for the corresponding channel every time the A-D conversion in each channel is completed. Each 10-bit A- D Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time. <When reset:Indeterminate> D Bit Name Function R W 0-5 No functions assigned 0 – 6-15 AD1DT0-AD1DT15 A-D conversion result – (A-D1 data) D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD1DT0-AD1DT15 A-D CONVERTERS

11-39 32170/32174 Group User's Manual (Rev. 2.1) 11.2.8 8-bit A-D Data Registers I 8-bit A-D0 Data Register 0 (AD08DT0) <Address: H'0080 00D1> I 8-bit A-D0 Data Register 1 (AD08DT1) <Address: H'0080 00D3> I 8-bit A-D0 Data Register 2 (AD08DT2) <Address: H'0080 00D5> I 8-bit A-D0 Data Register 3 (AD08DT3) <Address: H'0080 00D7> I 8-bit A-D0 Data Register 4 (AD08DT4) <Address: H'0080 00D9> I 8-bit A-D0 Data Register 5 (AD08DT5) <Address: H'0080 00DB> I 8-bit A-D0 Data Register 6 (AD08DT6) <Address: H'0080 00DD> I 8-bit A-D0 Data Register 7 (AD08DT7) <Address: H'0080 00DF> I 8-bit A-D0 Data Register 8 (AD08DT8) <Address: H'0080 00E1> I 8-bit A-D0 Data Register 9 (AD08DT9) <Address: H'0080 00E3> I 8-bit A-D0 Data Register 10 (AD08DT10) <Address: H'0080 00E5> I 8-bit A-D0 Data Register 11 (AD08DT11) <Address: H'0080 00E7> I 8-bit A-D0 Data Register 12 (AD08DT12) <Address: H'0080 00E9> I 8-bit A-D0 Data Register 13 (AD08DT13) <Address: H'0080 00EB> I 8-bit A-D0 Data Register 14 (AD08DT14) <Address: H'0080 00ED> I 8-bit A-D0 Data Register 15 (AD08DT15) <Address: H'0080 00EF> This A-D data register stores the 8-bit conversion data from the A-D0 converter. In single mode of the A-D0 converter, the result of A-D conversion is stored in the 8-bit A-D0 Data Register for each corresponding channel. In single-shot and continuous scan modes, the content of the A-D0 Successive Approximation Register is transferred to the 8-bit A-D Data Register for the corresponding channel every time the A-D conversion in each channel is completed. Each 8-bit A- D Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time. <When reset:Indeterminate> D Bit Name Function R W 8-15 AD08DT0-AD08DT15 8-bit A-D conversion result – (8-bit A-D0 data) D 8 9 1 01 11 21 31 4 D 1 5 AD08DT0-AD08DT15 A-D CONVERTERS

11-40 32170/32174 Group User's Manual (Rev. 2.1) I 8-bit A-D1 Data Register 0 (AD18DT0) <Address: H'0080 0AD1> I 8-bit A-D1 Data Register 1 (AD18DT1) <Address: H'0080 0AD3> I 8-bit A-D1 Data Register 2 (AD18DT2) <Address: H'0080 0AD5> I 8-bit A-D1 Data Register 3 (AD18DT3) <Address: H'0080 0AD7> I 8-bit A-D1 Data Register 4 (AD18DT4) <Address: H'0080 0AD9> I 8-bit A-D1 Data Register 5 (AD18DT5) <Address: H'0080 0ADB> I 8-bit A-D1 Data Register 6 (AD18DT6) <Address: H'0080 0ADD> I 8-bit A-D1 Data Register 7 (AD18DT7) <Address: H'0080 0ADF> I 8-bit A-D1 Data Register 8 (AD18DT8) <Address: H'0080 0AE1> I 8-bit A-D1 Data Register 9 (AD18DT9) <Address: H'0080 0AE3> I 8-bit A-D1 Data Register 10 (AD18DT10) <Address: H'0080 0AE5> I 8-bit A-D1 Data Register 11 (AD18DT11) <Address: H'0080 0AE7> I 8-bit A-D1 Data Register 12 (AD18DT12) <Address: H'0080 0AE9> I 8-bit A-D1 Data Register 13 (AD18DT13) <Address: H'0080 0AEB> I 8-bit A-D1 Data Register 14 (AD18DT14) <Address: H'0080 0AED> I 8-bit A-D1 Data Register 15 (AD18DT15) <Address: H'0080 0AEF> This A-D data register stores the 8-bit conversion data from the A-D1 converter. In single mode of the A-D1 converter, the result of A-D conversion is stored in the 8-bit A-D1 Data Register for each corresponding channel. In single-shot and continuous scan modes, the content of the A-D1 Successive Approximation Register is transferred to the 8-bit A-D Data Register for the corresponding channel every time the A-D conversion in each channel is completed. Each 8-bit A- D Data Register retains the last conversion result until they receive the next conversion result transferred, allowing the content to be read out at any time. <When reset:Indeterminate> D Bit Name Function R W 8-15 AD18DT0-AD18DT15 8-bit A-D1 conversion result – (8-bit A-D1 data) D 8 9 1 01 11 21 31 4 D 1 5 AD18DT0-AD18DT15 A-D CONVERTERS

11-41 32170/32174 Group User's Manual (Rev. 2.1)

11.3 Functional Description of A-D Converters

11.3.1 How to Find Along Input Voltages

The A-D converters use a 10-bit successive approximation method, and find the actual analog input voltage from the value (digital quantity) obtained through execution of A-D conversion by performing the following calculation. The A-D converters are a 10-bit converter, providing a resolution of 1,024 discrete voltage levels. Because the reference voltage for the A-D converter is the voltage applied to the VREF pin, make sure an exact and stable constant-voltage power supply is connected to VREF. Also, make sure the analog circuit power supply and ground (AVCC, AVSS) are separated from those of the digital circuit, with sufficient noise prevention measures incorporated. For details about the conversion accuracy, refer to Section 11.3.5, "Accuracy of A-D Conversion." Analog input voltage [V] = Figure 11.3.1 Outline Block Diagram of the Successive Approximation-type A-D Converter Unit A-D conversion result × VREF input voltage [V] 1024 A-D CONVERTERS (ADiSAR) 10-bit A-Di data register A-Di comparate data register A-D control circuit 10-bit A-D converter Comparator ADiIN8 ADiIN9 ADiIN10 ADiIN11 ADiIN12 ADiIN13 ADiIN14 ADiIN15 ADiCMP ADiDT0-15 Successive approximation-type A-D converter unit AVCCi Vref VIN i=0, 1

11-42 32170/32174 Group User's Manual (Rev. 2.1)

11.3.2 A-D Conversion by Successive Approximation Method

The A-D converter has A-D convert operation started by an A-D conversion start trigger (in software or hardware). Once A-D conversion begins, the following operation is automatically executed. (a) During single mode, Single Mode Register 0's A-D conversion/comparate completion bit is cleared to 0. During scan mode, Can Mode Register 0's A-D conversion completion bit is cleared to 0. (b) The content of the A-D Successive Approximation Register is cleared to "H'0000." (c) The A-D Successive Approximation Register's most significant bit (D6) is set to 1. (d) The comparison voltage, Vref(note), is fed from the D-A converter into the comparator. (e) The comparison voltage, Vref, and the analog input voltage, VIN, are compared, with the comparison result stored in D6. If Vref < VIN, then D6 = 1 If Vref > VIN, then D6 = 0 (f) Operations in steps (c) through (e) above are executed for all other bits from D7 to D15. (g) The value stored in the A-D Successive Approximation Register at completion of the comparison of D15 is the final A-D conversion result. Figure 11.3.2 Changes of the A-D Successive Approximation Register during A-D Convert Operation Note: The comparison voltage, Vref (the voltage fed from the D-A converter into the comparator), is determined according to changes of the content of the A-D Successive Approximation Register. Shown below are the equations used to calculate the comparison voltage, Vref.

• When the content of the A-D Successive Approximation Register = 0 Vref [V] = 0
• When the content of the A-D Successive Approximation Register = 1 to 1,023 Vref [V] = (reference voltage VREF / 1,024) x (content of the A-D Successive Approximation Register - 0.5) A-D CONVERTERS

D6 7 8 9 10 11 12 13 14 D15 1000000000 n 9 100000000 n 9 n 8 10000000 n9 n8 n7 n6 n5 n4 n3 n2 n1 1 2nd comparison 3rd comparison 10th comparison Conversion completed n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 Result of 1st comparison Result of 2nd comparison Vref > VIN then nX=0 Vref < VIN then nX=1 A-D Successive Approximation Register (ADiSAR) i=0,1

11-43 32170/32174 Group User's Manual (Rev. 2.1) The comparison result finally is stored in the 10-bit A-D Data Register (AD0DTn, AD1DTn) corresponding to each converted channel. Also, the 8-bit A-D Data Register (AD08DTn, AD18DTn) contains the 8 high-order bits of the 10-bit A-D conversion result. The following shows the procedure for A-D conversion by successive approximation in each operation mode. (1) Single mode The convert operation stops when comparison of the A-D Successive Approximation Register's D15 bit is completed. The content (A-D conversion result) of the A-D Successive Approximation Register is transferred to the 10-bit A-D Data Registers 0-15 for the converted channel. (2) Single-shot scan mode When comparison of the A-D Successive Approximation Register's D15 bit in a specified channel is completed, the content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Registers 0-15, and convert operations in steps (b) to (g) above are reexecuted for the next channel to be converted. In single-shot scan mode, the convert operation stops when A-D conversion for one specified scan loop is completed. (3) Continuous scan mode When comparison of the A-D Successive Approximation Register's D15 bit in a specified channel is completed, the content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Registers 0-15, and convert operations in steps (b) to (g) above are reexecuted for the next channel to be converted. During continuous scan mode, the convert operation is executed continuously until scan operation is forcibly halted by setting the A-D conversion stop bit (Scan Mode Register 0's D6 bit) to 1. A-D CONVERTERS

11-44 32170/32174 Group User's Manual (Rev. 2.1)

11.3.3 Comparator Operation

When comparator mode (single mode only) is selected, the A-D converter functions as a comparator that compares analog input voltages with a preset comparison voltage. When a comparison value is written to the successive approximation register, the A-D converter starts 'comparating' the analog input voltage selected by the Single Mode Register 1 analog input selection bit with the value written to the successive approximation register. Once comparate begins, the following operation is automatically executed. (a) The Single Mode Register 0 or Scan Mode Register 0's A-D conversion/comparate completion flag is cleared to 0. (b) The comparison voltage, Vref(note), is fed from the D-A converter into the comparator. (c) The comparison voltage, Vref, and the analog input voltage, VIN, are compared, with the comparison result stored in the comparate result flag (A-D Comparate Data Register's D15). If Vref < VIN, then the comparate result flag = 0 If Vref > VIN, then the comparate result flag = 1 (d) The comparate operation stops after storing the comparison result. The comparison result is stored in the A-D Comparate Data Register (AD0CMP, AD1CMP)'s corresponding bit. Note: The comparison voltage, Vref (the voltage fed from the D-A converter into the comparator), is determined according to changes of the content of the A-D Successive Approximation Register. Shown below are the equations used to calculate the comparison voltage, Vref.

• When the content of the A-D Successive Approximation Register = 0 Vref [V] = 0
• When the content of the A-D Successive Approximation Register = 1 to 1,023 Vref [V] = (reference voltage VREF / 1,024) × (content of the A-D Successive Approximation Register - 0.5) A-D CONVERTERS

11-45 32170/32174 Group User's Manual (Rev. 2.1)

11.3.4 Calculation of the A-D Conversion Time

The A-D conversion time is expressed by the sum of dummy cycle time and the actual execution cycle time. The following shows each time factor necessary to calculate the conversion time. (a) Start dummy time A time from when the CPU executed the A-D conversion start instruction to when the A-D converter starts A-D conversion (b) A-D conversion execution cycle time (c) Comparate execution cycle time (d) End dummy time A time from when the A-D converter finished A-D conversion to when the CPU can stably read out this conversion result from the A-D data register (e) Scan to scan dummy time A time during single-shot or continuous scan mode from when the A-D converter finished A-D conversion in a channel to when it starts A-D conversion in the next channel The equation to calculate the A-D conversion time is as follows: A-D conversion time = Start dummy time + Execution cycle time (+ Scan to scan dummy time + Execution cycle time + Scan to scan dummy time + Execution cycle time + Scan to scan dummy time .... + Execution cycle time) + End dummy time Note: Shown in ( ) are the conversion time required for the second and subsequent channels to be converted in scan mode. A-D CONVERTERS

11-46 32170/32174 Group User's Manual (Rev. 2.1) Figure 11.3.3 Conceptual Diagram of A-D Conversion Time Table 11.3.1 List of Conversion Clock Periods Unit: BCLK Transfer Start dummy A-D conversion Comparate execu- End Scan to scan rate (Note 1) (Note 2) (Note 3) execution cycle tion cycle dummy dummy (Note 4) Normal rate 4 4 4 294 42 1 4 Double rate 4 4 4 168 24 1 4 Note 1:This applies to a software triggered case. Note 2:This applies to a hardware triggered case. Note 3:This applies to a comparator mode case where a value is written to the A-D Successive Approximation Register. Note 4:This applies to only scan mode, and is added to the execution time for each channel. A-D CONVERTERS Start dummy Execution cycle A-D conversion start trigger Convert operation begins Transferred to A-D data register <Scan mode> End dummy Start dummy Execution cycle Execution cycle <Single mode> Completed Scan to scan dummy Scan to scan dummy (Channel 0) (Channel 1) (Last channel)

11-47 32170/32174 Group User's Manual (Rev. 2.1) Table 11.3.2 Total A-D Conversion Time Conversion started by Conversion rate Conversion mode (Note 1) Conversion time [BCLK] Software trigger Normal Single mode 299 (Note 2) Single-shot scan 4-channel scan 1193 /Continuous 8-channel scan 2385 16-channel scan 4769 Comparator mode 47 ×2 Single mode 173 Single-shot scan 4-channel scan 689 /Continuous 8-channel scan 1377 16-channel scan 2753 Comparator mode 27 Hardware trigger Normal Single mode 299 (Note 3) Single-shot scan 4-channel scan 1193 /Continuous 8-channel scan 2385 16-channel scan 4769 Comparator mode 47 ×2 Single mode 173 Single-shot scan 4-channel scan 689 /Continuous 8-channel scan 1377 16-channel scan 2753 Comparator mode 27 Note 1: For single and comparator modes, this shows the time for A-D conversion in one channel or for comparate operation. For single-shot and continuous scan modes, this shows the time for A-D conversion in one scan loop. Note 2: This shows the time from when a write-to-register cycle is completed to when an A-D conversion interrupt request is generated. Note 3: This shows the time from when the ADTRG pin input is asserted low or output event bus 3 is actuated_____ (for the A-D0 converter) or from when the ADTRG pin input is asserted low or TID1 overflow/underflow occurs (for the A-D1 converter) to when an A-D conversion interrupt request is generated. A-D CONVERTERS

11-48 32170/32174 Group User's Manual (Rev. 2.1)

11.3.5 Definition of the A-D Conversion Accuracy

The accuracy of the A-D Converter is expressed by absolute accuracy. Absolute accuracy refers to the difference, expressed in terms of LSB, between the output code actually obtained by converting analog input voltages into digital quantities and the output code that can be expected from an A-D converter with ideal characteristics. The analog input voltages used during accuracy measurement are chosen to be the midpoint values of voltage width at which an A-D converter with ideal characteristics will produce the same output code. For example, when VREF0 = 5.12 V, the width of 1 LSB of a 10-bit A-D converter is 5 mV, so that the middle points of analog input voltages are chosen to be 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, 25 mV, and so on. If the absolute accuracy of an A-D converter is said to be ±2 LSB, it means that if the input voltage is 25 mV, for example, then the actual A-D conversion result is in the range of H’003 to H’007, whereas the output code that can be expected from an ideal A-D converter is H’005. Note that absolute accuracy includes a zero error and full-scale error. Although when actually using the A-D Converter, the analog input voltages are in the range of AVSS0 to VREF0, excessively lowering the VREF0 voltage requires caution because resolution may be degraded. Note also that output codes for analog input voltages from VREF0 to AVCC0 are always H’3FF. Figure 11.3.4Ideal A-D Conversion Characteristics Relative to the 10-bit A-D Converter's Analog Input Voltages A-D CONVERTERS H ’000 H ’001 H ’002 H ’003 H ’3FE H ’3FF A-D conversion result (hex Analog input voltage [V] VREF 1024 X1 Ideal A-D conversion characteristic A-D conversion characteristic with infinite resolution

0 VREF

1024 X2 VREF

1024 X1022

1024 X1023

1024 X1024

11-49 32170/32174 Group User's Manual (Rev. 2.1) Figure 11.3.5 Absolute Accuracy of an A-D Converter A-D CONVERTERS H ’000 H ’001 H ’002 H ’003 H ’004 H ’005 H ’006 Output code (hexadecimal) → Analog input voltage [mV] Ideal A-D conversion characteristic A-D conversion characteristic with infinite resolution 5 1 01 52 02 53 03 54 04 55 05 5 H ’007 H ’008 H ’009 H ’00A H ’00B +2 LSB -2 LSB

11-50 32170/32174 Group User's Manual (Rev. 2.1)

11.4 Precautions on Using A-D Converters

• Forcible termination during scan operation If A-D conversion is halted by setting the A-D conversion stop bit (AD0CSTP, AD1CSTP) to 1 during scan mode operation and you read the content of the A-D data register for the channel in which conversion was in progress, it shows the last conversion result that had been transferred to the A-D data register before the conversion was forcibly terminated.
• ADTRG signal and input/output port If you selected the ADTRG signal for an A-D conversion start trigger, do not use the ADTRG pin as an input/output port (P67).
• Modification of A-D converter related registers If you want to change the contents of the A-D Conversion Interrupt Control Register, each Single and Scan Mode Register, or A-D Successive Approximation Register, except for the A-D conversion stop bit, do your change while A-D conversion is inactive, or be sure to restart A-D conversion after you changed the register contents. If the contents of these registers are changed in the middle of A-D conversion, the conversion results cannot be guaranteed.
• Handling of analog input signals The A-D converters included in the 32170 do not have a sample-and-hold circuit. Therefore, make sure the analog input levels are fixed during A-D conversion.
• A-D conversion completion bit readout timing If you want to read the A-D conversion completion bit (Single Mode Register 0's D5 bit or Scan Mode Register 0's D5 bit) immediately after A-D conversion has started, be sure to adjust the timing one clock cycle by, for example, inserting a NOP instruction before you read.
• Regarding analog input pins Figure 11.4.1 shows an internal equivalent circuit of the analog input unit. For A-D conversions to be performed correctly, the microcomputer must finish charging the internal capacitor C2 within the designated time (i.e., the sampling time). Make sure the conditions shown below are met when determining the analog output device’s output impedance and the value of an external stabilizing capacitor. Condition 1: Sampling time ( ) > C1 × R1 Condition 2: The peak current of i2 be minimized. A-D CONVERTERS

10 × 4

11-51 32170/32174 Group User's Manual (Rev. 2.1) A-D CONVERTERS (ADiSAR) 10-bit DA converterVREF Cin : input pin capacitance (approx. 10 pF) R2 : parasitic resistance of selector, etc. (1 to 2 kΩ ) C2 : comparator capacitance (approx. 2.9 pF) Selector i ADIN n ADIN i E C1 : parasitic capacitance of board + stabilizing C R1 : resistance of analog output device Analog output device Cin

• Time needed to change C2 1-bit conversion time Sampling time Evaluation time For a 10-bit converter conversion time = 1-bit conversion time ×10
• Peak current of i2 i2(peak)= × (E-VREF) C2 C1 × R1 Note: Increasing the value C1 × R1 helps to reduce the peak current. Note: For A-D conversions to be performed correctly, the microcomputer must finish charging C2 within the sampling period. Refer to the equation below as an approximate guide. AD conversion time 10 × 4 > C1 × R1 E : input voltage Figure 11.4.1 Internal Equivalent Circuit of the Analog Input Unit

11-52 32170/32174 Group User's Manual (Rev. 2.1) A-D CONVERTERS

• This is a blank page. *

12.1 Outline of Serial I/O

12.2 Serial I/O Related Registers

12.3 Transmit Operation in CSIO

12.4 Receive Operation in CSIO

12.5 Precautions on Using CSIO

12.6 Transmit Operation in UART

12.7 Receive Operation in UART

12.8 Fixed Period Clock Output

12.9 Precautions on Using UART

12-2 32170/32174 Group User's Manual (Rev. 2.1) The 32170 contains a total of six channels of serial I/O-SIO0, SIO1, SIO2, SIO3, SIO4, and SIO5. SIO0, SIO1, SIO4, and SIO5 can be selected between CSIO mode (clock-synchronous serial I/O) and UART mode (asynchronous serial I/O). SIO2 and SIO3 are UART mode only.

• CSIO mode (clock-synchronous serial I/O) Communication is performed synchronously with transfer clock, using the same clock on both transmit and receive sides. The transfer data is 8 bits long (fixed).
• UART mode (asynchronous serial I/O) Communication is performed asynchronously. The transfer data length can be selected from 7 bits, 8 bits, and 9 bits. Serial I/O0-3 each have a transmit DMA transfer and a receive DMA transfer request. These transfer requests, when combined with the internal DMAC, allow serial communication to be performed at high speed, as well as reduce the CPU burdens imposed by data communication. Serial I/O is outlined in the pages to follow. SERIAL I/O

12-3 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Table 12.1.1 Outline of Serial I/O Item Content Number of channels CSIO/UART : 4 channels (SIO0, SIO1, SIO4, SIO5) UART only : 2 channels (SIO2, SIO3) Clock During CSIO mode : Internal clock or external clock as selected (Note 1) During UART mode : Internal clock only Transfer mode Transmit half-duplex, receive half-duplex, transmit/receive full-duplex BRG count source f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (when internal peripheral clock selected) (Note 2) f(BCLK) : Internal peripheral clock operating frequency Data format CSIO mode : Data length = 8 bits (fixed) Order of transfer = LSB first (fixed) UART mode : Start bit = 1 bit Character length = 7, 8, or 9 bits Parity bit = Added or not added (when added, selectable between odd and even parity) Stop bit = 1 or 2 bits Order of transfer = LSB first (fixed) Baud rate CSIO mode : 152 bits/sec to 2M bits/sec (at f(BCLK) = 20 MHz) UART mode : 19 bits/sec to 156K bits/sec (at f(BCLK) = 20 MHz) Error detection CSIO mode : Overrun error only UART mode : Overrun error, parity error, framing error (Occurrence of any of these errors is indicated by an error sum bit) Fixed period clock functionWhen using SIO0, SIO1, SIO4 and SIO5 as UART, this function outputs a divided- by-2 BRG clock from the SCLK pin. Note 1: The maximum input frequency of external clock during CSIO mode is 1/16 of f(BCLK). Note 2: When f(BCLK) is selected as the BRG count source, the BRG set value is subject to limitations.

12-4 32170/32174 Group User's Manual (Rev. 2.1) Table 12.1.2 Serial I/O Interrupt Request Generation Function Serial I/O Interrupt Request ICU Interrupt Cause SIO0 transmit buffer empty interrupt SIO0 transmit interrupt SIO0 receive-finished SIO0 receive interrupt or receive error interrupt (selectable) SIO1 transmit buffer empty interrupt SIO1 transmit interrupt SIO1 receive-finished SIO1 receive interrupt or receive error interrupt (selectable) SIO2 transmit buffer empty interrupt SIO2, 3 transmit/receive interrupt (group interrupt) SIO2 receive-finished SIO2, 3 transmit/receive interrupt (group interrupt) or receive error interrupt (selectable) SIO3 transmit buffer empty interrupt SIO2, 3 transmit/receive interrupt (group interrupt) SIO3 receive-finished SIO2, 3 transmit/receive interrupt (group interrupt) or receive error interrupt (selectable) SIO4 transmit buffer empty interrupt SIO4, 5 transmit/receive interrupt (group interrupt) SIO4 receive-finished SIO4, 5 transmit/receive interrupt (group interrupt) or receive error interrupt (selectable) SIO5 transmit buffer empty interrupt SIO4, 5 transmit/receive interrupt (group interrupt) SIO5 receive-finished SIO4, 5 transmit/receive interrupt (group interrupt) or receive error interrupt (selectable) Table 12.1.3 Serial I/O DMA Transfer Request Generation Function Serial I/O DMA Transfer Request DMAC Input Channel SIO0 transmit buffer empty Channel 3 SIO0 receive-finished Channel 4 SIO1 transmit buffer empty Channel 6 SIO1 receive-finished Channel 3 SIO2 transmit buffer empty Channel 7 SIO2 receive-finished Channel 5 SIO3 transmit buffer empty Channel 9 SIO3 receive-finished Channel 8 SERIAL I/O

12-5 32170/32174 Group User's Manual (Rev. 2.1) Figure 12.1.1 Block Diagram of SIO0-SIO5 Note 1 : When BCLK is selected, the BRG set value is subject to limitations. Note 2 : SIO2 and SIO3 do not have the SCLKI/SCLKO function. SCLKI0/ SCLKO0 BCLK, BCLK/8, BCLK/32, BCLK/256 Baud rate generator (BRG)BCLK (Set value + 1) Internal data bus CSIO mode When internal clock selected When UART mode selected CSIO mode UART mode When internal clock selected Clock divider RXD0 TXD0 Receive interrupt Transmit/receive control circuit SIO0 Transmit Buffer Register SIO0 Transmit Shift Register Receive DMA transfer request Transmit interrupt Transmit DMA transfer request To DMAC3SIO0 Receive Shift Register SIO0 Receive Buffer Register When external clock selected SIO0 SIO1 SIO2 SIO3 RXD1 TXD1 SIO1 Transmit Shift Register SIO1 Receive Shift Register RXD2 TXD2 RXD3 TXD3 To interrupt controller To DMAC4 SIO4 RXD4 TXD4 SIO5 RXD5 TXD5 SCLKI4 / SCLKO4 SCLKI5 / SCLKO5 Receive interruptTransmit/receive control circuit Receive DMA transfer request Transmit interrupt Transmit DMA transfer request SCLKI1/ SCLKO1 To DMAC6 To interrupt controller To DMAC3 SIO2 Transmit Shift Register SIO2 Receive Shift Register Receive interruptTransmit/receive control circuit Receive DMA transfer request Transmit interrupt Transmit DMA transfer request To DMAC7 To DMAC5 SIO3 Transmit Shift Register SIO3 Receive Shift Register Receive interrupt Transmit/receive control circuit Receive DMA transfer request Transmit interrupt Transmit DMA transfer request To DMAC9 To DMAC8 To interrupt controller SIO4 Transmit Shift Register SIO4 Receive Shift Register Receive interruptTransmit/receive control circuit Transmit interrupt SIO5 Transmit Shift Register SIO5 Receive Shift Register Receive interruptTransmit/receive control circuit Transmit interrupt To interrupt controller SERIAL I/O

12-6 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O The diagram below shows a serial I/O related register map. Figure 12.2.1 Serial I/O Related Register Map Address D0 D7 +0 Address +1 Address D8 D15 H’0080 0100 H’0080 0112 H’0080 0120 H’0080 0130 H’0080 0124 H’0080 0126 Blank addresses are reserved. H’0080 0102SIO03 Cause of Receive Interrupt Select Register (SI03SEL) H’0080 0110 H’0080 0116 SIO0 Transmit Buffer Register (S0TXB) H’0080 0114 H’0080 0122 H’0080 0132 H’0080 0134 H’0080 0136 H’0080 0140 H’0080 0142 H’0080 0144 H’0080 0146 H’0080 0A00 H’0080 0A02 H’0080 0A10 H’0080 0A12 H’0080 0A14 SIO23 Interrupt Status Register (SI23STAT) SIO03 Interrupt Mask Register (SI03MASK) H’0080 0A16 H’0080 0A20 H’0080 0A22 H’0080 0A24 H’0080 0A26 SIO0 Transmit Control Register (S0TCNT) SIO0 Transmit/Receive Mode Register (S0MOD) SIO0 Receive Buffer Register (S0RXB) SIO0 Receive Control Register (S0RCNT) SIO0 Baud Rate Register (S0BAUR) SIO1 Transmit Buffer Register (S1TXB) SIO1 Transmit Control Register (S1TCNT) SIO1 Receive Buffer Register (S1RXB) SIO1 Receive Control Register (S1RCNT) SIO1 Baud Rate Register (S1BAUR) SIO1 Transmit/Receive Mode Register (S1MOD) SIO2 Transmit Buffer Register (S2TXB) SIO2 Transmit Control Register (S2TCNT) SIO2 Receive Buffer Register (S2RXB) SIO2 Receive Control Register (S2RCNT) SIO2 Baud Rate Register (S2BAUR) SIO2 Transmit/Receive Mode Register (S2MOD) SIO3 Transmit Buffer Register (S3TXB) SIO3 Transmit Control Register (S3TCNT) SIO3 Receive Buffer Register (S3RXB) SIO3 Receive Control Register (S3RCNT) SIO3 Baud Rate Register (S3BAUR) SIO3 Transmit/Receive Mode Register (S3MOD) SIO4 Transmit Buffer Register (S4TXB) SIO4 Transmit Control Register (S4TCNT) SIO4 Receive Buffer Register (S4RXB) SIO4 Receive Control Register (S4RCNT) SIO4 Baud Rate Register (S4BAUR) SIO4 Transmit/Receive Mode Register (S4MOD) SIO45 Cause of Receive Interrupt Select Register (SI45SEL) SIO45 Interrupt Status Register (SI45STAT) SIO45 Interrupt Mask Register (SI45MASK) SIO5 Transmit Buffer Register (S5TXB) SIO5 Transmit Control Register (S5TCNT) SIO5 Receive Buffer Register (S5RXB) SIO5 Receive Control Register (S5RCNT) SIO5 Baud Rate Register (S5BAUR) SIO5 Transmit/Receive Mode Register (S5MOD)

12-7 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O

12.2.1 SIO Interrupt Related Registers

(1) Selecting the cause of interrupt Interrupt signals sent from each SIO to the ICU (Interrupt Controller) are broadly classified into transmit interrupts and receive interrupts. Transmit interrupts are generated when the transmit buffer is empty. Receive interrupts are either receive-finished interrupts or receive error interrupts as selected by the Cause of Receive Interrupt Select Register (SI03SEL, SI45SEL). Note 1: No interrupt signals are generated unless interrupts are enabled by the SIO Interrupt Mask Register after enabling the TEN (transmit enable) bit or REN (receive enable) bit for the corresponding SIO. Note 2: SIO2 and SIO3 together comprise one interrupt group, so do SIO4 and SIO5. (2) Precautions on using transmit interrupts Transmit interrupts are generated when the corresponding TEN (transmit enable) bit is enabled while the SIO Interrupt Mask Register is set to enable interrupts. (3) About DMA transfer requests from SIO Each SIO can generate a transmit DMA transfer and a receive-finished DMA transfer request. These DMA transfer requests can be generated by enabling each SIO's corresponding TEN (transmit enable) bit or REN (receive enable) bit. When using DMA transfers to communicate with external devices, be sure to set the DMAC before enabling the TEN or REN bits. When a receive error occurs, no receive-finished DMA transfer requests are generated.

• Transmit DMA transfer request Generated when the transmit buffer is empty and the TEN bit is enabled. Figure 12.2.2 Transmit DMA Transfer Request TEN (transmit enable bit) TBE (transmit buffer empty bit) Transmit DMA transfer request

12-8 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O

• Receive-finished DMA transfer request DMA transfer request is generated when the receive buffer is filled. Figure 12.2.3 Receive-finished DMA Transfer Request Receive DMA transfer request RFIN (receive-completed bit) Note: When a receive error occurs, no receive-finished DMA transfer requests are generated.

12-9 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O <When reset : H'00> D Bit Name Function R W 0 - 3 No functions assigned 0 —

4 IRQT2 (SIO2 transmit-finished 0 : Interrupt not requested

interrupt request status bit) 1 : Interrupt requested

5 IRQR2 (SIO2 receive interrupt 0 : Interrupt not requested

request status bit) 1 : Interrupt requested

6 IRQT3 (SIO3 transmit-finished 0 : Interrupt not requested

interrupt request status bit) 1 : Interrupt requested

7 IRQR3 (SIO3 receive interrupt 0 : Interrupt not requested

request status bit) 1 : Interrupt requested W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. Transmit/receive interrupt requests from SIO2 and SIO3 are described below. [Setting the interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the interrupt request status bit] This bit is cleared by writing a 0 in software. Note: If the status bit is set in hardware at the same time it is cleared in software, the former has priority and the status bit is set. When writing to the SIO Interrupt Status Register, make sure the bits you want to clear are set to 0 and all other bits are set to 1. The bits which are thus set to 1 are unaffected by writing in software and retain the value they had before you write.

12.2.2 SIO Interrupt Control Registers

I SIO23 Interrupt Status Register (SI23STAT) <Address: H'0080 0100>

12-10 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O <When reset : H'00> D Bit Name Function R W

0 IRQT4 (SIO4 transmit-finished 0 : Interrupt not requested

interrupt request status bit) 1 : Interrupt requested

1 IRQR4 (SIO4 receive interrupt 0 : Interrupt not requested

request status bit) 1 : Interrupt requested

2 IRQT5 (SIO5 transmit-finished 0 : Interrupt not requested

interrupt request status bit) 1 : Interrupt requested

3 IRQR5 (SIO5 receive interrupt 0 : Interrupt not requested

request status bit) 1 : Interrupt requested 4 - 7 No functions assigned 0 — W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. Transmit/receive interrupt requests from SIO4 and SIO5 are described below. [Setting the interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the interrupt request status bit] This bit is cleared by writing a 0 in software. Note: If the status bit is set in hardware at the same time it is cleared in software, the former has priority and the status bit is set. When writing to the SIO Interrupt Status Register, make sure the bits you want to clear are set to 0 and all other bits are set to 1. The bits which are thus set to 1 are unaffected by writing in software and retain the value they had before you write. I SIO45 Interrupt Status Register (SI45STAT) <Address: H'0080 0A00>

12-11 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O D 8 9 1 01 11 21 31 4 D 1 5 T0MASK R0MASK T1MASK R1MASK T2MASK R2MASK T3MASK R3MASK <When reset : H'00> D Bit Name Function R W

8 T0MASK (SIO0 transmit 0 : Masks (disables) interrupt request

interrupt mask bit) 1 : Enables interrupt request

9 R0MASK (SIO0 receive 0 : Masks (disables) interrupt request

interrupt mask bit) 1 : Enables interrupt request

10 T1MASK (SIO1 transmit 0 : Masks (disables) interrupt request

interrupt mask bit) 1 : Enables interrupt request

11 R1MASK (SIO1 receive 0 : Masks (disables) interrupt request

interrupt mask bit) 1 : Enables interrupt request

12 T2MASK (SIO2 transmit 0 : Masks (disables) interrupt request

interrupt mask bit) 1 : Enables interrupt request

13 R2MASK (SIO2 receive 0 : Masks (disables) interrupt request

interrupt mask bit) 1 : Enables interrupt request

14 T3MASK (SIO3 transmit 0 : Masks (disables) interrupt request

interrupt mask bit) 1 : Enables interrupt request

15 R3MASK (SIO3 receive 0 : Masks (disables) interrupt request

interrupt mask bit) 1 : Enables interrupt request This register enables or disables interrupt requests generated by each SIO. Interrupt requests from an SIO are enabled by setting its corresponding interrupt mask bit to 1. I SIO03 Interrupt Mask Register (SI03MASK) <Address: H'0080 0101>

12-12 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O D 8 9 1 01 11 21 31 4 D 1 5 T4MASK R4MASK T5MASK R5MASK <When reset : H'00> D Bit Name Function R W

8 T4MASK (SIO4 transmit 0 : Masks (disables) interrupt request

interrupt mask bit) 1 : Enables interrupt request

9 R4MASK (SIO4 receive 0 : Masks (disables) interrupt request

interrupt mask bit) 1 : Enables interrupt request

10 T5MASK (SIO5 transmit 0 : Masks (disables) interrupt request

interrupt mask bit) 1 : Enables interrupt request

11 R5MASK (SIO5 receive 0 : Masks (disables) interrupt request

interrupt mask bit) 1 : Enables interrupt request 12 - 15 No functions assigned 0 — This register enables or disables interrupt requests generated by each SIO. Interrupt requests from an SIO are enabled by setting its corresponding interrupt mask bit to 1. I SIO45 Interrupt Mask Register (SI45MASK) <Address: H'0080 0A01>

12-13 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O <When reset : H'00> D Bit Name Function R W 0 - 3 No functions assigned 0 —

4 ISR0 (SIO0 receive interrupt 0 : Receive-finished interrupt

cause select bit) 1 : Receive error interrupt

5 ISR1 (SIO1 receive interrupt 0 : Receive-finished interrupt

cause select bit) 1 : Receive error interrupt

6 ISR2 (SIO2 receive interrupt 0 : Receive-finished interrupt

cause select bit) 1 : Receive error interrupt

7 ISR3 (SIO3 receive interrupt 0 : Receive-finished interrupt

cause select bit) 1 : Receive error interrupt This register selects the cause of an interrupt generated at completion of receive operation. [When set to 0] Receive-finished interrupt (receive buffer full) is selected. Receive-finished interrupts occur for receive errors (except an overrun error), as well as for completion of receive operation. [When set to 1] Receive error interrupt is selected. The following lists the types of errors detected for reception errors.

• CSIO mode : Overrun error
• UART mode : Overrun error, parity error, and framing error I SIO03 Cause of Receive Interrupt Select Register (SI03SEL)<Address: H'0080 0102>

12-14 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O <When reset : H'00> D Bit Name Function R W 0 - 3 No functions assigned 0 —

4 ISR4 (SIO4 receive interrupt 0 : Receive-finished interrupt

cause select bit) 1 : Receive error interrupt

5 ISR5 (SIO5 receive interrupt 0 : Receive-finished interrupt

cause select bit) 1 : Receive error interrupt 6 - 7 No functions assigned 0 — This register selects the cause of an interrupt generated at completion of receive operation. [When set to 0] Receive-finished interrupt (receive buffer full) is selected. Receive-finished interrupts occur for receive errors (except an overrun error), as well as for completion of receive operation. [When set to 1] Receive error interrupt is selected. The following lists the types of errors detected for reception errors.

• CSIO mode : Overrun error
• UART mode : Overrun error, parity error, and framing error I SIO45 Cause of Receive Interrupt Select Register (SI45SEL) <Address: H'0080 0A02>

12-15 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.2.5 Block Diagram of SIO4,5 Transmit Interrupts Figure 12.2.4 Block Diagram of SIO2,3 Transmit Interrupts SIO2,3 transmit/receive interrupts Data bus IRQT2 F/F T2MASK F/Fb12 (Level) 4-source inputs <SI23STAT : H’0080 0100> TXD2 <SI03MASK : H’0080 0101> F/F ISR2 RXD2 receive-finished RXD2 receive error F/F ISR3 RXD3 receive-finished RXD3 receive error IRQR2 F/F R2MASK F/Fb13 IRQT3 F/F T2MASK F/Fb14 TXD3 IRQR3 F/F R2MASK F/Fb15 SIO4,5 transmit/receive interrupts Data bus IRQT4 F/F T4MASK F/Fb8 (Level) 4-source inputs <SI45STAT : H’0080 0A00> TXD4 <SI45MASK : H’0080 0A01> F/F ISR4 RXD4 receive-finished RXD4 receive error F/F ISR5 RXD5 receive-finished RXD5 receive error IRQR4 F/F R2MASK F/Fb9 IRQT5 F/F T2MASK F/Fb10 TXD5 IRQR5 F/F R2MASK F/Fb11

12-16 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O <When reset : H'12> D Bit Name Function R W 0 , 1 No functions assigned 0 — 2 , 3 CDIV D2 D3 (BRG count source select bit) 0 0 : Selects f(BCLK) 0 1 : Selects divided-by-8 f(BCLK) 1 0 : Selects divided-by-32 f(BCLK) 1 1 : Selects divided-by-256 f(BCLK)

5 TSTAT 0 : Transmit halted & no data —

(Transmit status bit) in transmit buffer register 1 : Transmit in progress or data exists in transmit buffer register

6 TBE 0 : Data exists in transmit buffer register —

(Transmit buffer empty bit) 1 : No data in transmit buffer register

7 TEN 0 : Disables transmit

(Transmit enable bit) 1 : Enables transmit

12.2.3 SIO Transmit Control Registers

I SIO0 Transmit Control Register (S0TCNT) <Address: H'0080 0110> I SIO1 Transmit Control Register (S1TCNT) <Address: H'0080 0120> I SIO2 Transmit Control Register (S2TCNT) <Address: H'0080 0130> I SIO3 Transmit Control Register (S3TCNT) <Address: H'0080 0140> I SIO4 Transmit Control Register (S4TCNT) <Address: H'0080 0A10> I SIO5 Transmit Control Register (S5TCNT) <Address: H'0080 0A20>

12-17 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O (1) CDIV (baud rate generator count source select) bits (D2, D3) These bits select the count source for the baud rate generator (BRG). Note: If f(BCLK) is selected as the count source for the BRG, make sure when you set BRG that the baud rate will not exceed the maximum transfer rate. For details, refer to the section of this manual where the BRG register is described. (2) TSTAT (transmit status) bit (D5) [Set condition] This bit is set to 1 by a write to the Transmit Buffer Register when transmit is enabled. [Clear condition] This bit is cleared to 0 when transmit is idle (no data in the Transmit Shift Register) and no data exists in the Transmit Buffer Register. This bit also is cleared by clearing the transmit enable bit. (3) TBE (transmit buffer empty) bit (D6) [Set condition] This bit is set to 1 when data is transferred from the Transmit Buffer Register to the Transmit Shift Register and the Transmit Buffer Register becomes empty. This bit also is set by clearing the transmit enable bit. [Clear condition] This bit is cleared to 0 by writing data to the lower byte of the Transmit Buffer Register when transmit is enabled (TEN = 1). (4) TEN (transmit enable) bit (D7) Transmit is enabled by setting this bit to 1 and disabled by clearing this bit to 0. If this bit is cleared to 0 while transmitting data, the transmit operation stops.

12-18 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O D 8 9 1 01 11 21 31 4 D 1 5 SMOD CKS STB PSEL PEN SEN <When reset : 00> D Bit Name Function R W 8 - 10 SMOD D8 D9 D10 (Serial I/O mode select bit) 0 0 0 : 7-bit UART (Note 1) 0 0 1 : 8-bit UART 0 1 X : 9-bit UART

1 X X : 8-bit clock-synchronized serial I/O

11 CKS 0 : Internal clock

(Internal/external clock select bit) 1 : External clock (Note 2)

12 STB (Stop bit length select bit, 0 : One stop bit

UART mode only) 1 : Two stop bits (Note 3)

13 PSEL (Parity odd/even select bit, 0 : Odd parity

UART mode only) 1 : Even parity (Note 3)

14 PEN (Parity enable bit, 0 : Disables parity

UART mode only) 1 : Enables parity (Note 3)

15 SEN (Sleep select bit, 0 : Disables sleep function

UART mode only) 1 : Enables sleep function (Note 3) Note 1: For SIO2 and 3, the D8 bit is fixed to 0 in hardware. You cannot set the D8 bit to 1 (to choose clock- synchronous serial I/O). Note 2: Has no effect when UART mode is selected. Note 3: D12 to D15 have no effect during clock-synchronous mode.

12.2.4 SIO Transmit/Receive Mode Registers

I SIO0 Mode Register (S0MOD) <Address: H'0080 0111> I SIO1 Mode Register (S1MOD) <Address: H'0080 0121> I SIO2 Mode Register (S2MOD) <Address: H'0080 0131> I SIO3 Mode Register (S3MOD) <Address: H'0080 0141> I SIO4 Mode Register (S4MOD) <Address: H'0080 0A11> I SIO5 Mode Register (S5MOD) <Address: H'0080 0A21>

12-19 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O The SIO Mode Register consists of bits to set the serial I/O operation mode, data format, and the functions used during communication. The SIO Transmit/Receive Mode Register must always be set before serial I/O starts operating. If you want to change settings of this register after the serial I/O started transmitting or receiving data, be sure to confirm that transmit and receive operations have been completed and disable transmit/ receive operations (by clearing the SIO Transmit Control Register transmit enable bit and SIO Receive Control Register receive enable bit to 0) before you change. (1) SMOD (serial I/O mode select) bits (D8 to D10) These bits select the operation mode of serial I/O. (2) CKS (internal/external clock select) bit (D11) This bit is effective when CSIO mode is selected. Setting this bit has no effect when UART mode is selected, in which case the serial I/O is clocked by an internal clock. (3) STB (stop bit length select) bit (D12) This bit is effective when UART mode is selected. Use this bit to select the stop bit length that indicates the end of data to transmit. Setting this bit to 0 selects one stop bit, and setting this bit to 1 selects two stop bits. During clock-synchronous mode, the content of this bit has no effect. (4) PSEL (parity odd/even select) bit (D13) This bit is effective during UART mode. When parity is enabled (D14 = 1), use this bit to select the parity attribute (whether odd or even). Setting this bit to 0 selects an odd parity, and setting this bit to 1 selects an even parity. When parity is disabled (D14 = 0) and during clock-synchronous mode, the content of this bit has no effect. (5) PEN (parity enable) bit (D14) This bit is effective during UART mode. When this bit is set to 1, a parity bit is added immediately after the data bits of transmit data, and for receive data, the parity in it is checked. The parity bit added to the transmit data is automatically determined to be a 1 or a 0 in such a way that the attribute (odd/even) of the sum of the number of 1's in data bits and the content of the parity bit agrees with one selected by the parity odd/even select bit (D13). Figure 12.2.4 shows an example of data format when parity is enabled. (6) SEN (sleep select) bit (D15) This bit is effective during UART mode. If the sleep function is enabled by setting this bit to 1, data is latched into the UART Receive Buffer Register only when the most significant bit (MSB) of the received data is 1.

12-20 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.2.4 Data Format when Parity is Enabled ST : Start bit PAR : Parity bit : One frame equivalent D : Data bit SP : Stop bit If the attribute (odd/even) of the number of 1’s included in data bits agrees with the selected parityattribute, a 0 is added as parity bit. If the attribute (odd/even) of the number of 1’s included in data bits does not agree with the selected parity attribute, a 1 is added as parity bit. D7 D6 D5 D4 D3 D2 D1 D0 PAR SPST Attribute of D7 + D6 + ... +D0 When it agrees with the selected parity attribute, PAR = 0 is added. LSB MSB If the result of D7 + D6 + ... D0 + PAR does not agree with the selected parity attribute, a parity error is assumed. Note 1: Shown above is an example of data format in 8-bit UART mode. Note 2: The data bit numbers (Dn) above indicate bit numbers in a data list, and not the register bit numbers (Dn). G 9-bit UART mode G 8-bit UART mode D6 D5 D4 D3 D2 D1 D0 PAR SPST Note 1 Note 2 G 7-bit UART mode D7 D6 D5 D4 D3 D2 D1G Clock-synchronous mode D0 Note 1: Whether or not to add a parity bit is selectable. Note 2: The stop bit can be one bit or two bits long as selected. Direction of transfer D6 D5 D4 D3 D2 D1 D0 PAR SPST Note 1 Note 2 D6 D5 D4 D3 D2 D1 D0 PAR SPST Note 1 Note 2 D7D8 G When transmitting Received data is checked to see if the number of 1’s included in its data bits and the parity bit agrees with the parity attribute (known as parity check). G When receiving When it agrees with the selected parity attribute, PAR = 0 is added. D7 D6 D5 D4 D3 D2 D1 D0 PAR SPST LSB MSB

12-21 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TDATA <When reset : Indeterminate> D Bit Name Function R W 0 - 6 No functions assigned ? 7 - 15 TDATA Sets transmit data. ? (Transmit data) R = ? : Indeterminate when read The SIOn Transmit Buffer Register is used to set transmit data. This register is a write-only register, so you cannot read out the content of this register. Set data LSB-aligned, and write transmit data to bits D9-D15 for 7-bit data (UART mode only), D8-D15 for 8-bit data, or D7-D15 for 9-bit data (UART mode only). Before you set data in this register, enable the Transmit Control Register TEN (transmit enable) bit by setting it to 1. Writing data to this register while the TEN bit is disabled (cleared to 0) has no effect. When data is written to the Transmit Buffer Register while transmit is enabled, the data is transferred from the SIO Transmit Buffer Register to the SIO Transmit Shift Register, upon which the serial I/O starts transmitting the data. Note: For 7-bit and 8-bit data, the register can be accessed bytewise.

12.2.5 SIO Transmit Buffer Registers

I SIO0 Transmit Buffer Register (S0TXB) <Address: H'0080 0112> I SIO1 Transmit Buffer Register (S1TXB) <Address: H'0080 0122> I SIO2 Transmit Buffer Register (S2TXB) <Address: H'0080 0132> I SIO3 Transmit Buffer Register (S3TXB) <Address: H'0080 0142> I SIO4 Transmit Buffer Register (S4TXB) <Address: H'0080 0A12> I SIO5 Transmit Buffer Register (S5TXB) <Address: H'0080 0A22>

12-22 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 RDATA <When reset : Indeterminate> D Bit Name Function R W 0 - 6 No functions assigned 0 — 8 - 15 RDATA Stores receive data. — (Receive data) The SIOn Receive Buffer Register is used to store the receive data. When the serial I/O finishes receiving data, the content of the SIO Receive Shift Register is transferred to the SIO Receive Buffer Register. This register is a read-only register. For 7-bit data (UART mode only), data is set in bits D9-D15, with D8 and D7 always set to 0. For 8- bit data, data is set in bits D8-D15, with D7 always set to 0. After reception is completed, you may read out the content of the SIO Receive Buffer Register, but if the serial I/O finishes receiving the next data before you read the previous data, an overrun error occurs. In this case, the data received thereafter is not transferred to the Receive Buffer Register. To restart reception normally, clear the Receive Control Register's REN (receive enable) bit to 0. Note: For 7-bit and 8-bit data, the register can be accessed bytewise.

12.2.6 SIO Receive Buffer Registers

I SIO0 Receive Buffer Register (S0RXB) <Address: H'0080 0114> I SIO1 Receive Buffer Register (S1RXB) <Address: H'0080 0124> I SIO2 Receive Buffer Register (S2RXB) <Address: H'0080 0134> I SIO3 Receive Buffer Register (S3RXB) <Address: H'0080 0144> I SIO4 Receive Buffer Register (S4RXB) <Address: H'0080 0A14> I SIO5 Receive Buffer Register (S5RXB) <Address: H'0080 0A24>

12-23 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O RSTAT RFIN REN OVR PTY FLM ERS <When reset : H'00> D Bit Name Function R W

1 RSTAT 0 : Reception stopped —

(Receive status bit) 1 : Reception in progress

2 RFIN 0 : No data in receive buffer register —

(Receive completed bit) 1 : Data exists in receive buffer register

3 REN 0 : Disables reception

(Receive enable bit) 1 : Enables reception

4 OVR 0 : No overrun error —

(Overrun error bit) 1 : Overrun error occurred

5 PTY 0 : No parity error —

(Parity error bit, UART mode only) 1 : Parity error occurred

6 FLM 0 : No framing error —

(Framing error bit, UART mode only)1 : Framing error occurred

7 ERS 0 : No error —

(Error sum bit) 1 : Error occurred

12.2.7 SIO Receive Control Registers

I SIO0 Receive Control Register (S0RCNT) <Address: H'0080 0116> I SIO1 Receive Control Register (S1RCNT) <Address: H'0080 0126> I SIO2 Receive Control Register (S2RCNT) <Address: H'0080 0136> I SIO3 Receive Control Register (S3RCNT) <Address: H'0080 0146> I SIO4 Receive Control Register (S4RCNT) <Address: H'0080 0A16> I SIO5 Receive Control Register (S5RCNT) <Address: H'0080 0A26>

12-24 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O (1) RSTAT (receive status) bit (D1) [Set condition] This bit is set to 1 by a start of receive operation. When this bit = 1, it means that the serial I/O is receiving data. [Clear condition] This bit is cleared to 0 upon completion of receive operation or by clearing the REN (receive enable) bit. (2) RFIN (receive completed) bit (D2) [Set condition] This bit is set to 1 when all data bits have been received in the Receive Shift Register and whose content is transferred to the Receive Buffer Register. [Clear condition] This bit is cleared to 0 by reading the lower byte from the Receive Buffer Register or by clearing the REN (receive enable) bit. However, if an overrun error occurs, this bit cannot be cleared by reading the lower byte from the Receive Buffer Register. In this case, clear the REN (receive enable) bit. (3) REN (receive enable) bit (D3) Receive is enabled by setting this bit to 1, and is disabled by clearing this bit to 0, at which time the receive unit is initialized. Accordingly, the receive status flag, receive-completed flag bit, overrun error flag, framing error flag, parity error flag, and error sum flag all are cleared. The receive operation stops when the receive enable bit is cleared to 0 while receiving data. (4) OVR (overrun error) bit (D4) [Set condition] This bit is set to 1 when all bits of the next receive data have been received in the Receive Shift Register while the Receive Buffer Register still contains the previous receive data. In this case, the receive data is not stored in the Receive Buffer Register. Although receive operation is continued when the overrun error flag = 1, the receive data is not stored in the Receive Buffer Register. To start reception normally, you need to clear this bit. [Clear condition] This bit is cleared to 0 by only clearing the REN (receive enable) bit.

12-25 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O (5) PTY (parity error) bit (D5) This bit is effective in only UART mode. During CSIO mode, this bit is fixed to 0. [Set condition] The PTY (parity error) bit is set to 1 when the SIO Transmit/Receive Mode Register's PEN (parity enable/disable) bit is enabled and the parity (even/odd) of the receive data does not agree with the value that has been set by the said register's PSEL bit (parity select) bit. [Clear condition] The PTY bit is cleared by reading the lower byte from the SIO Receive Buffer Register or by clearing the SIO Receive Control Register's REN (receive enable) bit. However, if an overrun error occurs, this bit cannot be cleared by reading the lower byte from the Receive Buffer Register. In this case, clear the REN (receive enable) bit. (6) FLM (framing error) bit (D6) This bit is effective in only UART mode. During CSIO mode, this bit is fixed to 0. [Set condition] The FLM (framing error) bit is set to 1 when the number of received bits does not agree with one that has been selected by the SIO Transmit/Receive Mode Register. However, if an overrun error occurs, this bit cannot be cleared by reading the lower byte from the Receive Buffer Register. In this case, clear the REN (receive enable) bit. [Clear condition] The FLM bit is cleared by reading the lower byte from the SIO Receive Buffer Register or by clearing the SIO Receive Control Register's REN (receive enable) bit (7) ERS (Error sum) bit (D7) [Set condition] This flag is set to 1 when any one of overrun, framing, or parity errors is detected at completion of reception. [Clear condition] If an overrun has occurred, this flag is cleared by clearing the REN (receive enable) bit. Otherwise, this flag is cleared by reading the lower byte from the Receive Buffer Register or clearing the SIO Receive Control Register's REN (receive enable) bit.

12-26 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O D 8 9 1 01 11 21 31 4 D 1 5 BRG <When reset : Indeterminate> D Bit Name Function R W 8 - 15 BRG Divides the baud rate count source selected (Baud rate divide value) by SIO Mode Register by (n + 1) according to the BRG set value 'n.' BRG (baud rate divide value) (D8-D15) The SIO Baud Rate Register divides the baud rate count source selected by SIO Mode Register by (BRG set value + 1) according to the BRG set value. In the initial state, the BRG value is indeterminate, so be sure to set the divide value before serial I/O starts operating. The value written to the BRG during transmit/receive operation takes effect in the next cycle after the BRG counter finished counting. When using the internal clock (to output the SCLKO signal) in CSIO mode, the serial I/O divides the internal BCLK using the clock divider. Next, it divides the resulting clock by (BRG set value + 1) according to the BRG set value and then by 2, which results in generating a transmit/receive shift clock. When using an external clock in CSIO mode, the serial I/O does not use the BRG. (Transmit/ receive operations are synchronized to the externally supplied clock.)

12.2.8 SIO Baud Rate Registers

I SIO0 Baud Rate Register (S0BAUR) <Address: H'0080 0117> I SIO1 Baud Rate Register (S1BAUR) <Address: H'0080 0127> I SIO2 Baud Rate Register (S2BAUR) <Address: H'0080 0137> I SIO3 Baud Rate Register (S3BAUR) <Address: H'0080 0147> I SIO4 Baud Rate Register (S4BAUR) <Address: H'0080 0A17> I SIO5 Baud Rate Register (S5BAUR) <Address: H'0080 0A27>

12-27 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O In UART mode, the serial I/O divides the internal BCLK using the clock divider. Next, it divides the resulting clock by (BRG set value + 1) according to the BRG set value and then by 16, which results in generating a transmit/receive shift clock. When using SIO0, SIO1, SIO4 or SIO5 in UART mode, you can choose the relevant port (P84, P87, P65 or P66) to function as the SCLKO pin, so that a divided-by-2 BRG output clock can be output from the SCLKO pin. When using the internal clock (internally clocked CSIO or UART mode), with f(BCLK) selected as the BRG count source, make sure that during CSIO mode, the transfer rate does not exceed 2 Mbits per second, and that during UART mode, BRG is equal to or greater than 7.

12-28 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O

12.3 Transmit Operation in CSIO Mode

12.3.1 Setting the CSIO Baud Rate

The baud rate (data transfer rate) in CSIO mode is determined by a transmit/receive shift clock. The clock source from which to generate the transmit/receive shift clock is selected from the internal clock f(BCLK) or external clock. The CKS (internal/external clock select) bit (SIO Transmit/Receive Mode Register D11 bit) is used to select the clock source. The equation by which to calculate the transmit/receive baud rate values differs with the selected clock source, whether internal or external. (1) When internal clock is selected in CSIO mode When the internal clock is selected, f(BCLK) is divided by the clock divider before being fed into the baud rate generator (BRG). The clock divider's divide-by value is selected from 1, 8, 32, or 256 by using the CDIV (baud rate generator count source select) bits (Transmit Control Register D2, D3 bits). The baud rate generator divides the clock divider output by (baud rate register set value + 1) and then by 2, which results in generating a transmit/receive shift clock. When the internal clock is selected in CSIO mode, the baud rate is calculated using the equation below. 1 (BCLK) [bps] Clock divider's divide-by value × (baud rate register set value + 1) × 2 Baud rate register set value = H'00 to H'FF (Note) Clock divider's divide-by value = 1, 8, 32, or 256 Note: If the divide-by value selected for the baud rate generator count source is "1" (i.e., f(BCLK) itself), make sure the baud rate register value you set does not exceed 2 Mbps. (2) When external clock is selected in CSIO mode In this case, the baud rate generator is not used; instead, the input clock from the SCLKI pin serves directly as CSIO transmit/receive shift clock. The maximum frequency of the SCLKI pin input clock is 1/16 of f(BCLK). Baud rate = SCLKI pin input clock [bps]

12-29 32170/32174 Group User's Manual (Rev. 2.1)

12.3.2 Initial Settings for CSIO Transmission

To transmit data in CSIO mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register

• Set the register to CSIO mode
• Select the internal or an external clock (2) Setting SIO Transmit Control Register
• Select the clock divider's divide-by ratio (when internal clock selected) (3) Setting SIO Baud Rate Register When the internal clock is selected, set a baud rate generator value. (Refer to Section 12.3.1, "Setting the CSIO Baud Rate.") (4) Setting SIO Interrupt Mask Register
• Enable or disable the transmit buffer empty interrupt (SIO Interrupt Mask Register) (5) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) When you use a transmit buffer empty interrupt during transmission, set its priority level. (6) Setting DMAC When you issue DMA transfer requests to the internal DMAC when the transmit buffer is empty, set the DMAC. (Refer to Chapter 9, "DMAC.") (7) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.") SERIAL I/O

12-30 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.3.1 Procedure for CSIO Transmit Initialization Note 1: This is necessary when you use the internal clock. Note 2: When you selected the internal clock and a divide-by ratio = 1, you are subject to limitations that the baud rate generator must be set not to exceed 2 Mbps. Set SIO Transmit/Receive Mode Register Initial settings for CSIO transmission Set register to CSIO mode Select internal or external clock (When using DMAC)Set DMAC (When using interrupt)Set the Interrupt Controller Enable/disable transmit buffer empty interrupt Set SIO Interrupt Mask Register Divide-by ratio H’00 to H’FF (Note 2) Set SIO Baud Rate Register Select clock divider’s divide-by ratio (Note 1) Set SIO Transmit Control Register Set input/output port Operation Mode Register Serial I/O related registers Initial settings for CSIO transmission finished

12-31 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O

12.3.3 Starting CSIO Transmission

When all of the following transmit conditions are met after you finished initialization, the serial I/O starts transmit operation. (1) Transmit conditions when CSIO mode internal clock is selected

• The SIO Control Register's transmit enable bit is set to 1.
• Transmit data (8 bits) is written to the lower byte of the SIO Transmit Buffer Register (transmit buffer empty bit = 0). (2) Transmit conditions when CSIO mode external clock is selected
• The SIO Control Register 0's transmit enable bit is set to 1.
• Transmit data is written to the lower byte of the SIO Transmit Buffer Register (transmit buffer empty bit = 0).
• A falling edge of transmit clock on the SCLKI pin is detected. Note 1: While the transmit enable bit is cleared to 0, writes to the transmit buffer register are ignored. Always be sure to set the transmit enable bit to 1 before you write to the transmit buffer register. Note 2: When the internal clock is selected, a write to the lower byte of the transmit buffer register in Note 1 above triggers a start of transmission. Note 3: The transmit status bit is set to 1 at the time data is set in the lower byte of the SIO Transmit Buffer Register. When transmission starts, the serial I/O transmits data following the procedure below.
• Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register.
• Set the transmit buffer empty bit to 1. (Note)
• Start sending data synchronously with the shift clock beginning with the LSB. Note : A transmit buffer empty interrupt request and/or a DMA transfer request can be generated when the transmit buffer is emptied.

12.3.4 Successive CSIO Transmission

Once data is transferred from the transmit buffer register to the transmit shift register, the next data can be written to the transmit buffer register even when transmission of the preceding data is not completed. When the next data is written to the transmit buffer before completion of the preceding data transmission, the preceding and the next data are successively transmitted. To see if data has been transferred from the transmit buffer register to the transmit shift register, check the SIO Status Register's transmit buffer empty flag.

12-32 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O

12.3.5 Processing at End of CSIO Transmission

When data transmission is completed, the following operation is automatically performed in hardware. (1) When not transmitting successively

• The transmit status bit is set to 0. (2) When transmitting successively
• When transmission of the last data in a consecutive data train is completed, the transmit status bit is set to 0.

12.3.6 Transmit Interrupt

If a transmit buffer empty interrupt has been enabled by the SIO Interrupt Mask Register, a transmit buffer empty interrupt is generated at the time data is transferred from the transmit buffer register to the transmit shift register. Also, a transmit buffer empty interrupt is generated when the TEN (transmit enable) bit is set to 1 (enabled after being disabled) while a transmit buffer empty interrupt has been enabled. You must set the Interrupt Controller (ICU) before you can use transmit interrupts.

12.3.7 Transmit DMA Transfer Request

When data has been transferred from the transmit buffer register to the transmit shift register, a transmit DMA transfer request for the corresponding SIO channel is ouput to the DMAC. This transfer request is also output when the TEN (transmit enable) bit is set to 1 (enabled after being disabled). You must set the Interrupt Controller (ICU) before you can transmit data using DMA transfers.

12-33 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.3.2 Transmit Operation during CSIO Mode (Hardware Processing) Note: This applies when transmit interrupt has been enabled by SIO Interrupt Mask Register. The following processing is automatically executed in hardware Transfer content of transmit buffer to transmit shift register Set transmit buffer empty bit to 1 Transmit data Y (Successive transmission) Transmit conditions met? Y N N Clear transmit status bit to 0 Transmit DMA transfer request Transmit interrupt request (Note) CSIO transmit operation starts CSIO transmit operation completed Transmit conditions met?

12-34 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.3.3 Example of CSIO Transmission (Transmitted Only Once, with Transmit Interrupt Used) Note 1: Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit Note 2: When transmit interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3: The Interrupt Controller IVECT register is read or "SIO Transmit Interrupt Control Register" interrupt request bit cleared Note 4: Transmit interrupt request is generated when transmission is enabled. Note 5: Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied.

12.3.8 Typical CSIO Transmit Operation

The following shows a typical transmit operation in CSIO mode. : Processing by software : Interrupt generation Internal clock selected External clock selected <CSIO on receive side> SCLKO TXD SCLKI RXD Transmit clock (SCLKO) Set Write to transmit buffer register Transmit buffer empty bit Transmit enable bit Cleared Transmit status bit D7 D6 D5 D4 D3 D2 D1 D0TXD SIO transmit interrupt (Note 1) Transmit interrupt (Note 4) Interrupt request accepted Content of transmit buffer register transferred to transmit shift register Cleared by completion of transmission Set by a write to transmit buffer (Note 2) (Note 3) <CSIO on transmit side> <CSIO on transmit side> Transmit interrupt (Note 5)

12-35 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.3.4 Example of CSIO Transmission (Successive Transmission, with Transmit Buffer Empty and Transmit Finished Interrupts Used) Note 1: Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit Note 2: When transmit interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3: Transmit interrupt request is generated when transmission is enabled. Note 4: Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. : Interrupt generation First data Next data (Note 2) (Note 3) (Note 2) Upon transmit buffer empty interrupt, next data is written (First data) (Next data) (Note 4) : Processing by software Internal clock selected External clock selected <CSIO on receive side> SCLKO TXD SCLKI RXD Transmit clock (SCLKO) Set Transmit buffer empty bit Transmit enable bit Cleared Transmit status bit D7 D6 D5 D0 D7 D6 D5 D0TXD SIO transmit interrupt (Note 1) <CSIO on transmit side> <CSIO on transmit side> Write to transmit buffer register Write to transmit buffer register

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12.4 Receive Operation in CSIO Mode

12.4.1 Initial Settings for CSIO Reception

To receive data in CSIO mode, initialize the serial I/O following the procedure described below. Note, however, that because the receive shift clock is derived from operation of the transmit circuit, you need to execute transmit operation even when you only want to receive data. (1) Setting SIO Transmit/Receive Mode Register

• Set the register to CSIO mode
• Select the internal or an external clock (2) Setting SIO Transmit Control Register
• Select the clock divider's divide-by ratio (when internal clock selected) (3) Setting SIO Baud Rate Register When the internal clock is selected, set a baud rate generator value. (Refer to Section 12.3.1, "Setting the CSIO Baud Rate.") (4) Setting SIO Interrupt Mask Register
• Enable or disable the transmit buffer empty interrupt (SIO Interrupt Mask Register)
• Select the cause of receive interrupt (receive finished/error) (Cause of Receive Interrupt Select Register) (5) Setting SIO Receive Control Register Set the receive enable bit (6) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) When you use a transmit interrupt or receive interrupt during transmission/reception, set its priority level. (7) Setting the DMAC When you generate a DMA transfer request to the internal DMAC when the transmit buffer is empty or transmission is completed, set the DMAC. (Refer to Chapter 9, "DMAC.")

12-37 32170/32174 Group User's Manual (Rev. 2.1) Figure 12.4.1 Procedure for CSIO Receive Initialization Note 1: This is necessary when you use the internal clock. Note 2: When you selected the internal clock and a divide-by ratio = 1, you are subject to limitations that the baud rate generator must be set not to exceed 2 Mbps. (8) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.") Set SIO Transmit/Receive Mode Register Initial settings for CSIO reception Set to CSIO mode Select internal or external clock (When using DMAC)Set DMAC (When using interrupt)Set the Interrupt Controller Enable/disable transmit buffer empty interrupt Set SIO Interrupt Mask Register Divide-by ratio H’00 to H’FF (Note 2) Set SIO Baud Rate Register Select clock divider’s divide-by ratio (Note 1) Set SIO Transmit Control Register Set input/output port Operation Mode Register Serial I/O related registers Initial settings for CSIO reception finished Set receive enable bitSet SIO Receive Control Register SERIAL I/O

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12.4.2 Starting CSIO Reception

When all of the following receive conditions are met after you finished initialization, the serial I/O starts receive operation. (1) Receive conditions when CSIO mode internal clock is selected

• The SIO Receive Control Register's receive enable bit is set to 1.
• Transmit conditions are met. (Refer to Section 12.3.3, "Starting CSIO Transmission.") (2) Receive conditions when CSIO mode external clock is selected
• The SIO Receive Control Register's receive enable bit is set to 1.
• Transmit conditions are met. (Refer to Section 12.3.3, "Starting CSIO Transmission.") Note : The receive status bit is set to 1 at the time dummy data is set in the lower byte of the SIO Transmit Buffer Register. When the above conditions are met, the serial I/O starts receiving 8-bit serial data (LSB first) synchronously with the receive shift clock.

12.4.3 Processing at End of CSIO Reception

When data reception is completed, the following operation is automatically performed in hardware. (1) When reception is completed normally The receive-finished (receive buffer full) bit is set to 1. Note 1 : If a receive-finished (receive buffer full) interrupt has been enabled, an interrupt request is generated. Note 2 : A DMA transfer request is generated. (2) When error occurs during reception When an error (only overrun error in CSIO mode) occurs during reception, the overrun error bit and receive sum bit are set to 1. Note 1: If a receive-finished interrupt has been selected (by SIO Cause of Receive Interrupt Select Register), neither a receive-finished interrupt request nor a DMA transfer request is generated. Note 2: If a receive error interrupt has been selected (by SIO Cause of Receive Interrupt Select Register), a receive error interrupt request is generated when interrupt requests are enabled. No DMA transfer requests are generated.

12-39 32170/32174 Group User's Manual (Rev. 2.1) Figure 12.4.2 Receive Operation during CSIO Mode (Hardware Processing) SERIAL I/O

12.4.4 About Successive Reception

When the following conditions are met at completion of data reception, data may be received successively.

• The receive enable bit is set to 1.
• Transmit conditions are met.
• No overrun error has occurred. Receive data Set SIO Receive Control Register’s receive-finished bit to 1 Store received data in Receive Buffer Register Set SIO Receive Control Register’s overrun error and receive sum error bits to 1 Overrun error? Receive conditions met? Y N CSIO receive operation starts N Y CSIO receive operation completed

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12.4.5 Flags Indicating the Status of CSIO Receive Operation

Following flags are available that indicate the status of receive operation in CSIO mode.

• SIO Receive Control Register receive status bit
• SIO Receive Control Register receive-finished bit
• SIO Receive Control Register receive error bit
• SIO Receive Control Register overrun error bit After reception is completed, you may read out the content of the SIO Receive Buffer Register, but if the serial I/O finishes receiving the next data before you read, an overrun error occurs. In this case, the data received thereafter is not transferred to the SIO Receive Buffer Register. To restart reception, temporarily clear the receive enable bit to 0 and initialize the receive control block before you restart. The said receive enable bit can be cleared, when there are no receive errors(note) encountered, by reading the lower byte from the SIO Receive Buffer Register or clearing the REN (receive enable) bit. If any receive error has occurred, it can only be cleared by clearing the REN (receive enable) bit, and cannot be cleared by reading the lower byte from the SIO Receive Buffer Register. Note: Overrun error is the only error that can be detected during reception in CSIO mode.

12-41 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.4.3 Example of CSIO Reception (When Received Normally) Note 1: Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit Note 2: When receive-finished interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3: The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register" interrupt request bit cleared

12.4.6 Typical CSIO Receive Operation

The following shows a typical receive operation in CSIO mode. SIO receive interrupt (Note 1) (When receive-finished interrupt is selected) Clock stopped Automatically cleared for each receive operation performed Receive-finished bit Read from receive buffer (When receive error interrupt is selected) Receive-finished interrupt (Note 2) Interrupt request accepted (Note 3) No interrupt request Internal clock selected External clock selected <CSIO on transmit side> SCLKO RXD SCLKI TXD Receive clock (SCLKI) Set Receive enable bit Cleared Receive status bit <CSIO on receive side> <CSIO on receive side> Set by a write to transmit buffer D7 D6 D5 D4 D3 D2 D1 D0RXD : Processing by software : Interrupt generation

12-42 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.4.4 Example of CSIO Reception (When Overrun Error Occurred) Note 1: Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit Note 2: When receive-finished interrupt is enabled Note 3: When receive error interrupt is enabled Note 4: Receive enable bit cleared Note 5: The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register" interrupt request bit cleared First data reception completed Overrun error bit Receive buffer not read during this interval Overrun error bit cleared (Note 4) Receive error interrupt (Note 3) Internal clock selected External clock selected <CSIO on transmit side> SCLKO RXD SCLKI TXD Transmit clock (SCLKO) Set Receive enable bit <CSIO on receive side> <CSIO on receive side> Cleared D7 D6 D0 D7 D6 D0RXD Set SIO receive interrupt (Note 1) (When receive-finished interrupt is selected) (When receive error interrupt is selected) Receive-finished interrupt (Note 2) Interrupt request accepted (Note 5) Interrupt request accepted (Note 5) : Processing by software : Interrupt generation Next data reception completed Receive-finished bit

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12.5 Precautions on Using CSIO Mode

• Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register's BRG count source select bit must always be set when not operating. When transmitting or receiving data, be sure to check that transmission and/or reception under way has been completed and clear the transmit and receive enable bits before you set the registers.
• Settings of Baud Rate (BRG) Register If you selected f(BCLK) with the BRG clock source select bit, make sure the BRG register value you set does not exceed 2 Mbps.
• About successive transmission To transmit multiple data successively, set the next transmit data in the SIO Transmit Buffer Register before transmission of the preceding data is completed.
• About reception Because during CSIO mode the receive shift clock is derived from operation of the transmit circuit, you need to execute transmit operation (by sending dummy data) even when you only want to receive data. In this case, note that if the port function is set for TXD pin (by setting the operation mode register to 1), dummy data is actually output from the pin.
• About successive reception To receive multiple data successively, set data (dummy data) in the SIO Transmit Buffer Register before the transmitter starts sending data.
• Transmit/receive operations using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before you start serial communication.
• About the receive-finished bit If a receive error (overrun error) occurs, the receive-finished bit cannot be cleared by reading out the receive buffer register. In this case, it can only be cleared by clearing the receive enable bit.

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• About overrun error If all bits of the next receive data are received in the SIO Receive Shift Register before you read out the SIO Receive Buffer Register (an overrun error occurs), the receive data is not stored in the Receive Buffer Register and the Receive Buffer Register retains the previously received data. Thereafter, although receive operation is continued, no receive data is stored in the Receive Buffer Register (the receive status bit = 1). To restart reception normally, you need to temporarily clear the receive enable bit before you restart. This is the only way you can clear the overrun error flag.
• About DMA transfer request generation during SIO transmission If the Transmit Buffer Register becomes empty (the transmit buffer empty flag = 1) while the transmit enable bit is set to 1 (transmit enabled), an SIO transmit buffer empty DMA transfer request is generated.
• About DMA transfer request generation during SIO reception When the receive-finished bit is set to 1 (the receive buffer register full), a receive-finished DMA transfer request is generated. However, if an overrun error has occurred, this DMA transfer request is not generated.

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12.6 Transmit Operation in UART Mode

12.6.1 Setting the UART Baud Rate

The baud rate (data transfer rate) during UART mode is determined by a transmit/receive shift clock. In UART mode, the source for this transmit/receive shift clock is always the internal clock regardless of how the internal/external clock select bit (SIO Transmit/Receive Mode Register bit D11) is set. (1) Calculating the UART mode baud rate After being divided by the clock divider, f(BCLK) is fed into the Baud Rate Generator (BRG), after which it is further divided by 16 to produce a transmit/receive shift clock. The clock divider's divide-by value is selected from 1, 8, 32, or 256(note) using the SIO Transmit Control Register's CDIV (baud rate generator count source select) bits (D2, D3). The Baud Rate Generator divides the clock it received from the clock divider by (baud rate register set value + 1) and further divides the resulting clock by 16 to produce a transmit/receive shift clock. During UART mode (in which the internal clock is always used), the baud rate is calculated using the equation below. 1 (BCLK) [bps] Clock divider's divide-by value × (baud rate register set value + 1) × 16 Baud rate register set value = H'00 to H'FF (Note) Clock divider's divide-by value = 1, 8, 32, or 256 Note : If the divide-by value selected for the baud rate generator count source is "1" (i.e., f(BCLK) itself), make sure the baud rate register value you set is equal to or greater than 7.

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12.6.2 UART Transmit/Receive Data Formats

The transmit/receive data format during UART mode is determined by setting the SIO Transmit/ Receive Mode Register. Shown below is the transmit/receive data format that can be used in UART mode. Figure 12.6.1 Example of Transmit/Receive Data Format in UART Mode Table 12.6.1 Transfer Data in UART Mode Bit Name Content ST (start bit) Indicates the beginning of data transmission. This is a low signal of a one bit duration, which is added immediately before the transmit data. D0-D8 (character bits) Transmit/receive data transferred via serial I/O. In UART mode, data in 7, 8, or 9 bits can be transmitted/received. PAR (parity bit) Added to the transmit/receive characters. When parity is enabled, parity is automatically set in such a way that the number of 1's in characters including the parity bit itself is always even or odd as selected by the even/odd parity select bit. SP (stop bit) Indicates the end of data transmission, and is added immediately after characters (or if parity enabled, immediately after the parity bit). The stop bit can be chosen to be one bit or two bits long. ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP SP LSB M SB ST Parity bitStop bitStart bit Data bits (8 bits) Transmit data Next data

12-47 32170/32174 Group User's Manual (Rev. 2.1) Figure 12.6.2 Selectable Data Formats during UART Mode Note 1: The high-order bits of the SIO Receive Buffer Register's selected character bits are fixed to 0. Note 2: The data bit numbers (Dn) above indicate bit numbers in a data list, and not the register bit numbers (Dn). SERIAL I/O ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP LSB MSB Start bit Character (data) bits Parity bit Stop bit D0 D7 D8 D15 SIO Transmit Buffer Register SIO Receive Buffer Register ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP LSB MSB ST D7 D6 D5 D4 D3 D2 D1 PAR SP SP ST D7 D6 D5 D4 D3 D2 D1 PAR SP ST D7 D6 D5 D4 D3 D2 D1 SP SP ST D7 D6 D5 D4 D3 D2 D1 SP LSB MSB 8-bit characters 7-bit characters ST : D0 - D7 : PAR : SP : 9-bit characters 8-bit characters 7-bit characters

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12.6.3 Initial Settings for UART Transmission

To transmit data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register

• Set the register to UART mode
• Set parity (when enabled, select odd/even)
• Set stop bit length
• Set character length Note : During UART mode, settings of the internal/external clock select bit have no effect (only the internal clock is useful). (2) Setting SIO Transmit Control Register
• Select the clock divider's divide-by ratio. (3) Setting SIO Baud Rate Register Set a baud rate generator value. (Refer to Section 12.6.1, "Setting the UART Baud Rate.") (4) Setting SIO Interrupt Mask Register
• Enable or disable SIO transmit interrupt. (5) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) When you use a transmit interrupt, set its priority level. (6) Setting DMAC When you issue DMA transfer requests to the internal DMAC when the transmit buffer is empty, set the DMAC. (Refer to Chapter 9, "DMAC.") (7) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.")

12-49 32170/32174 Group User's Manual (Rev. 2.1) Figure 12.6.3 Procedure for UART Transmit Initialization Note: When you selected f(BCLK) for the BRG count source (CDVI), you are subject to limitations that the baud rate register value you set must be equal to or greater than 7. SERIAL I/O Set SIO Transmit/Receive Mode Register Initial settings for UART transmission Set register to UART mode Set parity (when enabled, select odd/even) (When using DMAC)Set DMAC related registers (When using interrupt) Set the Interrupt Controller Enable/disable transmit interrupt Set SIO Interrupt Related Registers Divide-by ratio H’00 to H’FF (Note)Set SIO Baud Rate Register Select clock divider’s divide-by ratioSet SIO Transmit Control Register Set input/output port Operation Mode Register Serial I/O related registers Initial settings for UART transmission finished Set stop bit length Set character length

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12.6.4 Starting UART Transmission

When all of the following transmit conditions are met after you finished initialization, the serial I/O starts transmit operation.

• The SIO Transmit Control Register's TEN (transmit enable) bit is set to 1. (Note)
• Transmit data is written to the SIO Transmit Buffer Register (transmit buffer empty bit = 0). Note : While the transmit enable bit is cleared to 0, writes to the transmit buffer are ignored. Always be sure to set the transmit enable bit to 1 before you write to the transmit buffer register. When transmission starts, the serial I/O transmits data following the procedure below.
• Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register.
• Set the transmit buffer empty bit to 1. (Note)
• Start sending data synchronously with the shift clock beginning with the LSB. Note : A transmit buffer empty interrupt request and/or a DMA transfer request can be generated when the transmit buffer is emptied.

12.6.5 Successive UART Transmission

Once data is transferred from the transmit buffer register to the transmit shift register, the next data can be written to the transmit buffer register even when transmission of the preceding data is not completed. When the next data is written to the transmit buffer before completion of the preceding data transmission, the preceding and the next data are successively transmitted. To see if data has been transferred from the transmit buffer register to the transmit shift register, check the SIO Transmit Control Register's transmit buffer empty flag.

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12.6.6 Processing at End of UART Transmission

When data transmission is completed, the following operation is automatically performed in hardware. (1) When not transmitting successively

• The transmit status bit is set to 0. (2) When transmitting successively
• When transmission of the last data in a consecutive data train is completed, the transmit status bit is set to 0.

12.6.7 Transmit Interrupt

If a transmit buffer empty interrupt has been enabled by the SIO Interrupt Mask Register, a transmit buffer empty interrupt is generated at the time data is transferred from the transmit buffer register to the transmit shift register. Also, a transmit buffer empty interrupt is generated when the TEN (transmit enable) bit is set to 1 (enabled after being disabled) while a transmit buffer empty interrupt has been enabled. You must set the Interrupt Controller (ICU) before you can use transmit interrupts.

12.6.8 Transmit DMA Transfer Request

When data has been transferred from the transmit buffer register to the transmit shift register, a transmit DMA transfer request for the corresponding SIO channel is ouput to the DMAC. This transfer request is also output when the TEN (transmit enable) bit is set to 1 (enabled after being disabled). You must set the Interrupt Controller (ICU) before you can transmit data using DMA transfers.

12-52 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.6.4 Transmit Operation during UART Mode (Hardware Processing) Note: This applies when transmit interrupt has been enabled by SIO Interrupt Mask Register. The following processing is automatically executed in hardware Transfer content of transmit buffer to transmit shift register Set transmit buffer empty bit to 1 Transmit data Y (Successive transmission) Transmit conditions met? Y N N Clear transmit status bit to 0 Transmit DMA transfer request Transmit interrupt request (Note) UART transmit operation starts UART transmit operation completed Transmit conditions met?

12-53 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.6.5 Example of UART Transmission (Transmitted Only Once, with Transmit Interrupt Used) Note 1: Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit Note 2: When transmit-finished interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3: The Interrupt Controller IVECT register is read or "SIO Transmit Interrupt Control Register" interrupt request bit cleared Note 4: Transmit interrupt request is generated when transmission is enabled. Note 5: Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied.

12.6.9 Typical UART Transmit Operation

The following shows a typical transmit operation in CSIO mode. : Processing by software : Interrupt generation <UART on receive side> TXD RXD Set Write to transmit buffer register Transmit buffer empty bit Transmit enable bit Cleared Transmit status bit ST D7 D6 D0 PAR ST STTXD SIO transmit interrupt (Note 1) Transmit interrupt (Note 4) Interrupt request accepted Transferred from transmit buffer to transmit shift register (transmission starts) (Note 2) (Note 3) <UART on transmit side> <UART on transmit side> Transmit interrupt (Note 5) Cleared

12-54 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.6.6 Example of UART Transmission (Successive Transmission, with Transmit Interrupt Used) Note 1: Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3: The Interrupt Controller IVECT register is read or "SIO Transmit Interrupt Control Register" interrupt request bit cleared Note 4: Transmit interrupt request is generated when transmission is enabled. Note 5: Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. : Interrupt generation First data Next data (Note 2) (Note 4) (Note 2) Upon transmit interrupt, next data is written (First data) (Next data) (Note 5) : Processing by software <UART on receive side> TXD RXD Set Transmit buffer empty bit Transmit enable bit Cleared Transmit status bit D7ST D0 D7 SP D0TXD SIO transmit interrupt (Note 1) <UART on transmit side> <UART on transmit side> Write to transmit buffer register Write to transmit buffer register Transferred from transmit buffer to transmit shift register (transmission starts) Cleared when transmission of last data is completed SP ST Interrupt request accepted(Note 3)

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12.7 Receive Operation in UART Mode

12.7.1 Initial Settings for UART Reception

To receive data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register

• Set the register to UART mode
• Set parity (when enabled, select odd/even)
• Set stop bit length
• Set character length Note: During UART mode, settings of the internal/external clock select bit have no effect (only the internal clock is useful). (2) Setting SIO Transmit Control Register
• Select the clock divider's divide-by ratio. (3) Setting SIO Baud Rate Register Set a baud rate generator value. (Refer to Section 12.6.1, "Setting the UART Baud Rate.") (4) Setting SIO interrupt related registers
• Cause of Receive Interrupt Select Register Select the cause of receive interrupt (receive finished/receive error)
• Interrupt Mask Register Enable/disable receive interrupts (5) Setting the Interrupt Controller When you use interrupts during reception, set its priority level. (6) Setting DMAC When you issue DMA transfer requests to the internal DMAC when reception is completed, set the DMAC. (Refer to Chapter 9, "DMAC.") (7) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.")

12-56 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.7.1 Procedure for UART Receive Initialization Note: When you selected the clock divider's divide-by ratio = 1, you are subject to limitations that the baud rate register value you set must be equal to or greater than 7. Set SIO Transmit/Receive Mode Register Initial settings for UART reception Set register to UART mode Set parity (when enabled, select odd/even) (When using DMAC)Set DMAC related registers (When using interrupt)Set the interrupt controller SIO Receive Interrupt Control Register Set SIO Interrupt Related Registers Divide-by ratio H’00 to H’FF (Note)Set SIO Baud Rate Register Select clock divider’s divide-by ratioSet SIO Transmit Control Register Set input/output port Operation Mode Register Serial I/O related registers Initial settings for UART reception finished Set stop bit length Set character length Cause of Receive Interrupt Select Register (receive finished/receive error) Interrupt Mask Register (enable/disable receive interrupts)

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12.7.2 Starting UART Reception

When all of the following receive conditions are met after you finished initialization, the serial I/O starts receive operation.

• The SIO Receive Control Register's receive enable bit is set to 1
• Start bit (falling edge signal) is applied to the RXD pin When the above conditions are met, the serial I/O enters UART receive operation. However, if the start bit when checked again at the first rise of the internal receive shift clock is detected high for reason of noise, etc., the serial I/O stops receive operation and waits for the start bit again.

12.7.3 Processing at End of UART Reception

When data reception is completed, the following operation is automatically performed in hardware. (1) When reception is completed normally The receive-finished (receive buffer full) bit is set to 1. Note 1: If a receive-finished (receive buffer full) interrupt has been enabled, an interrupt request is generated. Note 2: A DMA transfer request is generated. (2) When error occurs during reception When an error occurs during reception, the corresponding error bit (OE, FE, or PE) and the receive sum bit are set to 1. Note 1: If a receive-finished interrupt has been selected (by SIO Cause of Receive Interrupt Select Register), a receive-finished interrupt request is generated when interrupt requests are enabled. However, if an overrun error has occurred, this interrupt is not generated. Note 2: If a receive error interrupt has been selected (by SIO Cause of Receive Interrupt Select Register), a receive error interrupt request is generated when interrupt requests are enabled. Note 3: No DMA transfer requests are generated.

12-58 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.7.2 Receive Operation during UART Mode (Hardware Processing) Receive data Y Transfer data from SIO Receive Shift Register to SIO Receive Buffer Register Set SIO Receive Control Register’s receive-finished bit to 1 Set receive status bit to 1 Overrun error? Parity error or framing error? Start bit detected normally? Set SIO Receive Control Register’s overrun error bit and error sum bit to 1 Set SIO Receive Control Register’s corresponding error bit and receive error sum bit to 1 N UART reception completed The following processing is automatically executed in hardware Transmit conditions met? Y N UART receive operation starts Y N N Y

12-59 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.7.3 Example of UART Reception (When Received Normally) Note 1: Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit Note 2: When receive-finished interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3: The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register" interrupt request bit cleared

12.7.4 Typical UART Receive Operation

The following shows a typical receive operation in UART mode. SIO receive interrupt (Note 1) (When receive-finished interrupt is selected) Automatically cleared for each receive operation performed Receive-finished bit Read from receive buffer (When receive error interrupt is selected) Receive-finished interrupt (Note 2) Interrupt request accepted (Note 3) No interrupt request Internal clock selected <UART on transmit side> RXD TXD Set Receive enable bit (SIO Receive Control Register) Cleared Receive status bit <UART on receive side> <UART on receive side> : Processing by software : Interrupt generation ST D7 D6 D0 PAR SP SPRXD

12-60 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.7.4 Example of UART Reception (When Overrun Error Occurred) Note 1: Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit Note 2: When receive-finished interrupt is enabled Note 3: When receive error interrupt is enabled Note 4: This is done by clearing the receive enable bit to 0. Note 5: The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register" interrupt request bit cleared First data reception completed Overrun error bit Receive buffer not read during this interval Overrun error bit cleared (Note 4) Receive error interrupt (Note 3) <UART on transmit side> RXD TXD Set <UART on receive side> <UART on receive side> ST D7 SP ST D7 SPRXD Set SIO receive interrupt (Note 1) (When receive-finished interrupt is selected) (When receive error interrupt is selected) Receive-finished interrupt (Note 2) Interrupt request accepted (Note 5) Interrupt request accepted (Note 5) : Processing by software : Interrupt generation Next data reception completed (Note 5) Receive enable bit (SIO Receive Control Register) Receive-finished bit

12-61 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O Figure 12.7.5 Timing at Which Data Are Latched during UART Reception BRG RXD SCLK (CASE1) SCLK (CASE2) 8CLK(BRG) 8CLK(BRG) Start bit LSB data Timing at which to latch the received data Maximum delay (equivalent to setting by BRG) T1bit/16 CASE1 CASE2 16CLK(BRG) BCLK (MHz) Clock divider Baud rate generator (BRG) Divided by 16 Shift clock (SCLK) Shift clock generator circuit BCLK BCLK/8 BCLK/32 BCLK/256 1/(set value +1) Set value = 00 to FF The time from when the start bit goes low to when the stop bit data at the K’th position is latched: K : number of bits in transmit data (including start, stop, and parity bits) SCLK : shift clock (BRG × 16) N ∆ T : error per bit (per SCLK) of the generator circuit (depends on the clock divider and the BRG set value) SCLK delay : drift in received data latch timing (equivalent to setting by BRG at maximum)Note 1: A timing error equivalent to setting by BRG at maximum occurs as the received data are latched by shift clock. Note 2: Errors of the oscillating clock are added (subtracted) every BCLK. (K – 1/2) × (SCLK ± N ∆ t) + (SCLK delay) Timing at which to latch the received data ST D7 D6 D5 D4 D3 D2 D0 D1 PER STRXD (For 11-bit data) The time from when the start bit goes low to when the stop bit data at the K’th position is latched is shown below.

12-62 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O

12.8 Fixed Period Clock Output Function

When using SIO0, SIO1, SIO4 or SIO5 in UART mode, you can choose the relevant port (P84, P87, P65 or P66) to function as the SCLKO0, SCLKO1, SCLKO4 or SCLKO5 pin. In this way, a clock derived from BRG output by dividing it by 2 can be output from the SCLKO pin. Note: This clock is output all the time, not just during data transfer. Figure 12.8.1 Example of Fixed Period Clock Output SCLKO TXD RXD Clock output to peripheral circuits UART transmit/receive ST SPData ST SPData 50% 50% BRG period Internal BRG output SCLKO output 1. Configuration when using BRG/2 clock 2. Operation timing

12-63 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O

12.9 Precautions on Using UART Mode

• Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register's BRG count source select bit must always be set when not operating. When transmitting or receiving data, be sure to check that transmission and/or reception under way has been completed and clear the transmit and receive enable bits before you set the registers.
• Settings of Baud Rate (BRG) Register If you selected f(BCLK) with the BRG clock source select bit, make sure the BRG register value you set is equal to or greater than 7. The value written to the SIO Baud Rate Register becomes effective beginning with the next period after the BRG counter finished counting. However, when transmit and receive operations are disabled, the register value can be changed at the same time you write to the register.
• Transmit/receive operations using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before you start serial communication.
• About overrun error If all bits of the next receive data are received in the SIO Receive Shift Register before you read out the SIO Receive Buffer Register (an overrun error occurs), the receive data is not stored in the Receive Buffer Register and the Receive Buffer Register retains the previously received data. Once an overrun error occurs, no receive data is stored in the Receive Buffer Register although receive operation is continued. To restart reception normally, you need to temporarily clear the receive enable bit before you restart. This is the only way you can clear the overrun error flag.

12-64 32170/32174 Group User's Manual (Rev. 2.1) SERIAL I/O

• Flags indicating the status of UART receive operation Following flags are available that indicate the status of receive operation during UART mode.
• SIO Receive Control Register receive status bit
• SIO Receive Control Register receive-finished bit
• SIO Receive Control Register receive error sum bit
• SIO Receive Control Register overrun error bit
• SIO Receive Control Register parity error bit
• SIO Receive Control Register framing error bit The manner in which the receive-finished bit and various error bit flags are cleared varies depending on whether an overrun error has occurred or not, as described below. [When no overrun error has occurred] Said bits can be cleared by reading the lower byte from the receive buffer register or clearing the receive enable bit to 0. [When an overrun error has occurred] Said bits can only be cleared by clearing the receive enable bit to 0.

13.1 Outline of the CAN Module

13.2 CAN Module Related

13.3 CAN Protocol

13.4 Initializing the CAN Module

13.5 Transmitting Data Frames

13.6 Receiving Data Frames

13.7 Transmitting Remote Frames

13.8 Receiving Remote Frames

13.9 Precautions about CAN Module

13-2 32170/32174 Group User's Manual (Rev. 2.1) CAN MODULE The M32R/ECU contains CAN (Controller Area Network) Specification 2.0B-compliant Full CAN module. This module has 16 message slots and three mask registers, effective use of which helps to reduce the CPU load for data processing. The following outlines the Full CAN module. Table 13.1.1 Outline of the CAN Module Item Content Protocol CAN Specification 2.0B Number of message slotsTotal 16 slots (14 global slots, two local slots) Polarity 0: Dominant 1: Recessive Acceptance filter One global mask Two local masks Baud rate 1 Time quantum (Tq) = (BRP + 1)/CPU clock (BRP: Baud rate prescaler set value) BRP :1-255 (0: Inhibited) Number of Tq's for one bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 + Progagation Segment : 1-8Tq Phase Segment 1 : 1-8Tq Phase Segment 2 : 2-8Tq (IPT = 2) Remote frame automatic A slot which received a remote frame automatically sends a data frame. response function Time stamp function Time stamp function implemented by a 16-bit counter. Using CAN bus bit period as the fundamental period, a count period can be set to 1/1 through 1/4 of it. BasicCAN mode BasicCAN function is materialized using two local slots. Transmit abort function Transmit request can be canceled. Loopback function The data transmitted by CAN module itself is received. Return bus off function Forcibly placed into error active mode after clearing error counter. Note: The maximum allowable error of oscillation depends on the system configuration (bus length, communication rate, CAN bus transceiver, sampling position, and bit configuration). Baud rate = 1 Tq period × number of Tq's for one bit

• ·· Max 1 Mibps

13-3 32170/32174 Group User's Manual (Rev. 2.1) Table 13.1.2 CAN Module Interrupt Generation Function CAN module interrupt source ICU interrupt source CAN0 transmit complete interrupt CAN0 group interrupt CAN0 receive complete interrupt CAN0 group interrupt CAN0 bus error interrupt CAN0 group interrupt CAN0 error passive interrupt CAN0 group interrupt CAN0 bus off interrupt CAN0 group interrupt CAN MODULE Figure 13.1.1 Block Diagram of the CAN Module CTX CRX Data bus CAN0 Status Register CAN0 REC Register CAN0 TEC Register CAN0 Message Slot 0-15 Control Register CAN0 Extended ID Register CAN0 Configuration Register CAN0 Control Register CAN0 Global Mask Register CAN0 Local Mask Register A CAN0 Local Mask Register B Message Memory (1) Message ID (2) Data length code (3) Message data (4) Time stamp CAN0 Slot Status Register CAN0 Slot Interrupt Control Register CAN0 Error Interrupt Control Register Interrupt Control Circuit CAN0 Interrupt Acceptance Filtering 16-bit Timer CAN0 Time Stamp Register CAN0 Protocol Controller Ver 2.0B

13-4 32170/32174 Group User's Manual (Rev. 2.1)

13.2 CAN Module Related Registers

The diagram below shows a CAN module related register map. CAN MODULE Figure 13.2.1 CAN Module Related Register Map (1/4) +0 Address +1 Address D0 D7 D8 D15 H ’0080 1034 H ’0080 1032 H ’0080 1038 H ’0080 1036 H ’0080 103C H ’0080 103A H ’0080 1054 Address H ’0080 1058 H ’0080 1056 H ’0080 1052 H ’0080 105A CAN0 Configuration Register (CAN0CONF) CAN0 Global Mask Register Standard ID0 (C0GMSKS0) CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0) H ’0080 1000 H ’0080 1002 H ’0080 1004 H ’0080 1008 H ’0080 100A H ’0080 1010 H ’0080 100E H ’0080 1006 H ’0080 1028 H ’0080 102C H ’0080 1030 H ’0080 102E H ’0080 102A H ’0080 105C H ’0080 100C H ’0080 1050 CAN0 Control Register (CAN0CNT) CAN0 Extended ID Register (CAN0EXTID) CAN0 Time Stamp Count Register (CAN0TSTMP) CAN0 Slot Interrupt Status Register (CAN0SLIST) CAN0 Status Register (CAN0STAT) CAN0 Receive Error Count Register (CAN0REC) CAN0 Transmit Error Count Register (CAN0TEC) CAN0 Message Slot 0 Control Register (C0MSL0CNT) H ’0080 1012 CAN0 Error Interrupt Status Register (CAN0ERIST) CAN0 Error Interrupt Mask Register (CAN0ERIMK)H ’0080 1014 H ’0080 1016 CAN0 Baud Rate Prescaler (CAN0BRP) H ’0080 105E CAN0 Global Mask Register Extended ID0 (C0GMSKE0) CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0) Blank addresses are reserved. CAN0 Slot Interrupt Mask Register (CAN0SLIMK) CAN0 Global Mask Register Standard ID1 (C0GMSKS1) CAN0 Global Mask Register Extended ID1 (C0GMSKE1) CAN0 Global Mask Register Extended ID2 (C0GMSKE2) CAN0 Local Mask Register A Standard ID1 (C0LMSKAS1) CAN0 Local Mask Register A Extended ID1 (C0LMSKAE1) CAN0 Local Mask Register A Extended ID2 (C0LMSKAE2) CAN0 Local Mask Register B Standard ID0 (C0LMSKAS0) CAN0 Local Mask Register B Extended ID0 (C0LMSKAE0) CAN0 Local Mask Register B Standard ID1 (C0LMSKAS1) CAN0 Local Mask Register B Extended ID1 (C0LMSKAE1) CAN0 Local Mask Register B Extended ID2 (C0LMSKAE2) CAN0 Message Slot 1 Control Register (C0MSL1CNT) CAN0 Message Slot 2 Control Register (C0MSL2CNT) CAN0 Message Slot 3 Control Register (C0MSL3CNT) CAN0 Message Slot 4 Control Register (C0MSL4CNT) CAN0 Message Slot 5 Control Register (C0MSL5CNT) CAN0 Message Slot 6 Control Register (C0MSL6CNT) CAN0 Message Slot 7 Control Register (C0MSL7CNT) CAN0 Message Slot 8 Control Register (C0MSL8CNT) CAN0 Message Slot 9 Control Register (C0MSL9CNT) CAN0 Message Slot 10 Control Register (C0MSL10CNT) CAN0 Message Slot 11 Control Register (C0MSL11CNT) CAN0 Message Slot 12 Control Register (C0MSL12CNT) CAN0 Message Slot 13 Control Register (C0MSL13CNT) CAN0 Message Slot 14 Control Register (C0MSL14CNT) CAN0 Message Slot 15 Control Register (C0MSL15CNT)

13-5 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.2.2 CAN Module Related Register Map (2/4) CAN MODULE H ’0080 1102 H ’0080 1104 H ’0080 110C H ’0080 110E H ’0080 1112 H ’0080 1114 H ’0080 1116 H ’0080 1110 H ’0080 1108 H ’0080 1106 H ’0080 110A CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) CAN0 Message Slot 0 Data 0 (C0MSL0DT0) CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) CAN0 Message Slot 0 Time Stamp (C0MSL0TSP) H ’0080 1118 H ’0080 111A H ’0080 111E H ’0080 1120 H ’0080 1122 H ’0080 1126 H ’0080 1128 H ’0080 112E H ’0080 112C H ’0080 1124 H ’0080 112A H ’0080 111C H ’0080 1130 H ’0080 1132 H ’0080 1136 H ’0080 1138 H ’0080 113E H ’0080 113C H ’0080 1134 H ’0080 113A H ’0080 1140 H ’0080 1142 H ’0080 1146 H ’0080 1148 H ’0080 114E H ’0080 114C H ’0080 1144 H ’0080 114A H ’0080 1150 H ’0080 1152 H ’0080 1100 CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) +0 Address +1 AddressAddress Blank addresses are reserved. CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) CAN0 Message Slot 0 Data 1 (C0MSL0DT1) CAN0 Message Slot 0 Data 2 (C0MSL0DT2) CAN0 Message Slot 0 Data 3 (C0MSL0DT3) CAN0 Message Slot 0 Data 4 (C0MSL0DT4) CAN0 Message Slot 0 Data 5 (C0MSL0DT5) CAN0 Message Slot 0 Data 6 (C0MSL0DT6) CAN0 Message Slot 0 Data 7 (C0MSL0DT7) CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0) CAN0 Message Slot 1 Data 0 (C0MSL1DT0) CAN0 Message Slot 1 Data Length Register (C0MSL1DLC) CAN0 Message Slot 1 Time Stamp (C0MSL1TSP) CAN0 Message Slot 1 Standard ID0 (C0MSL1SID0) CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1) CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2) CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1) CAN0 Message Slot 1 Data 1 (C0MSL1DT1) CAN0 Message Slot 1 Data 2 (C0MSL1DT2) CAN0 Message Slot 1 Data 3 (C0MSL1DT3) CAN0 Message Slot 1 Data 4 (C0MSL1DT4) CAN0 Message Slot 1 Data 5 (C0MSL1DT5) CAN0 Message Slot 1 Data 6 (C0MSL1DT6) CAN0 Message Slot 1 Data 7 (C0MSL1DT7) CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0) CAN0 Message Slot 2 Data 0 (C0MSL2DT0) CAN0 Message Slot 2 Data Length Register (C0MSL2DLC) CAN0 Message Slot 2 Time Stamp (C0MSL2TSP) CAN0 Message Slot 2 Standard ID0 (C0MSL2SID0) CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1) CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2) CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1) CAN0 Message Slot 2 Data 1 (C0MSL2DT1) CAN0 Message Slot 2 Data 2 (C0MSL2DT2) CAN0 Message Slot 2 Data 3 (C0MSL2DT3) CAN0 Message Slot 2 Data 4 (C0MSL2DT4) CAN0 Message Slot 2 Data 5 (C0MSL2DT5) CAN0 Message Slot 2 Data 6 (C0MSL2DT6) CAN0 Message Slot 2 Data 7 (C0MSL2DT7) CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0) CAN0 Message Slot 3 Data 0 (C0MSL3DT0) CAN0 Message Slot 3 Data Length Register (C0MSL3DLC) CAN0 Message Slot 3 Time Stamp (C0MSL3TSP) CAN0 Message Slot 3 Standard ID0 (C0MSL3SID0) CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1) CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2) CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1) CAN0 Message Slot 3 Data 1 (C0MSL3DT1) CAN0 Message Slot 3 Data 2 (C0MSL3DT2) CAN0 Message Slot 3 Data 3 (C0MSL3DT3) CAN0 Message Slot 3 Data 4 (C0MSL3DT4) CAN0 Message Slot 3 Data 5 (C0MSL3DT5) CAN0 Message Slot 3 Data 6 (C0MSL3DT6) CAN0 Message Slot 3 Data 7 (C0MSL3DT7) CAN0 Message Slot 4 Extended ID0 (C0MSL4EID0) CAN0 Message Slot 4 Data 0 (C0MSL4DT0) CAN0 Message Slot 4 Data Length Register (C0MSL4DLC) CAN0 Message Slot 4 Time Stamp (C0MSL4TSP) CAN0 Message Slot 4 Standard ID0 (C0MSL4SID0) CAN0 Message Slot 4 Standard ID1 (C0MSL4SID1) CAN0 Message Slot 4 Extended ID2 (C0MSL4EID2) CAN0 Message Slot 4 Extended ID1 (C0MSL4EID1) CAN0 Message Slot 4 Data 1 (C0MSL4DT1) CAN0 Message Slot 4 Data 2 (C0MSL4DT2) CAN0 Message Slot 4 Data 3 (C0MSL4DT3) CAN0 Message Slot 4 Data 4 (C0MSL4DT4) CAN0 Message Slot 4 Data 5 (C0MSL4DT5) CAN0 Message Slot 4 Data 6 (C0MSL4DT6) CAN0 Message Slot 4 Data 7 (C0MSL4DT7) CAN0 Message Slot 5 Extended ID0 (C0MSL5EID0) CAN0 Message Slot 5 Standard ID0 (C0MSL5SID0) CAN0 Message Slot 5 Standard ID1 (C0MSL5SID1) CAN0 Message Slot 5 Extended ID1 (C0MSL5EID1)

13-6 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.2.3 CAN Module Related Register Map (3/4) CAN MODULE H ’0080 1156 H ’0080 1158 H ’0080 115E H ’0080 115C H ’0080 1154 H ’0080 115A H ’0080 1160 H ’0080 1162 H ’0080 1166 H ’0080 1168 H ’0080 116E H ’0080 116C H ’0080 1164 H ’0080 116A H ’0080 1170 H ’0080 1172 H ’0080 1176 H ’0080 1174 H ’0080 117A H ’0080 117C H ’0080 117E H ’0080 1182 H ’0080 1184 H ’0080 118A H ’0080 1188 H ’0080 1180 H ’0080 1186 H ’0080 1178 H ’0080 118C H ’0080 118E H ’0080 1192 H ’0080 1194 H ’0080 119A H ’0080 1198 H ’0080 1190 H ’0080 1196 H ’0080 119C H ’0080 119E H ’0080 11A2 H ’0080 11A4 H ’0080 11A0 H ’0080 11A6 +0 Address +1 AddressAddress CAN0 Message Slot 6 Extended ID0 (C0MSL6EID0) CAN0 Message Slot 6 Data 0 (C0MSL6DT0) CAN0 Message Slot 6 Data Length Register (C0MSL6DLC) CAN0 Message Slot 6 Time Stamp (C0MSL6TSP) CAN0 Message Slot 6 Standard ID0 (C0MSL6SID0) CAN0 Message Slot 6 Standard ID1 (C0MSL6SID1) CAN0 Message Slot 6 Extended ID2 (C0MSL6EID2) CAN0 Message Slot 6 Extended ID1 (C0MSL6EID1) CAN0 Message Slot 6 Data 1 (C0MSL6DT1) CAN0 Message Slot 6 Data 2 (C0MSL6DT2) CAN0 Message Slot 6 Data 3 (C0MSL6DT3) CAN0 Message Slot 6 Data 4 (C0MSL6DT4) CAN0 Message Slot 6 Data 5 (C0MSL6DT5) CAN0 Message Slot 6 Data 6 (C0MSL6DT6) CAN0 Message Slot 6 Data 7 (C0MSL6DT7) Blank addresses are reserved. CAN0 Message Slot 5 Data 0 (C0MSL5DT0) CAN0 Message Slot 5 Data Length Register (C0MSL5DLC) CAN0 Message Slot 5 Time Stamp (C0MSL5TSP) CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) CAN0 Message Slot 5 Data 1 (C0MSL5DT1) CAN0 Message Slot 5 Data 2 (C0MSL5DT2) CAN0 Message Slot 5 Data 3 (C0MSL5DT3) CAN0 Message Slot 5 Data 4 (C0MSL5DT4) CAN0 Message Slot 5 Data 5 (C0MSL5DT5) CAN0 Message Slot 5 Data 6 (C0MSL5DT6) CAN0 Message Slot 5 Data 7 (C0MSL5DT7) CAN0 Message Slot 7 Extended ID0 (C0MSL7EID0) CAN0 Message Slot 7 Data 0 (C0MSL7DT0) CAN0 Message Slot 7 Data Length Register (C0MSL7DLC) CAN0 Message Slot 7 Time Stamp (C0MSL7TSP) CAN0 Message Slot 7 Standard ID0 (C0MSL7SID0) CAN0 Message Slot 7 Standard ID1 (C0MSL7SID1) CAN0 Message Slot 7 Extended ID2 (C0MSL7EID2) CAN0 Message Slot 7 Extended ID1 (C0MSL7EID1) CAN0 Message Slot 7 Data 1 (C0MSL7DT1) CAN0 Message Slot 7 Data 2 (C0MSL7DT2) CAN0 Message Slot 7 Data 3 (C0MSL7DT3) CAN0 Message Slot 7 Data 4 (C0MSL7DT4) CAN0 Message Slot 7 Data 5 (C0MSL7DT5) CAN0 Message Slot 7 Data 6 (C0MSL7DT6) CAN0 Message Slot 7 Data 7 (C0MSL7DT7) CAN0 Message Slot 8 Extended ID0 (C0MSL8EID0) CAN0 Message Slot 8 Data 0 (C0MSL8DT0) CAN0 Message Slot 8 Data Length Register (C0MSL8DLC) CAN0 Message Slot 8 Time Stamp (C0MSL8TSP) CAN0 Message Slot 8 Standard ID0 (C0MSL8SID0) CAN0 Message Slot 8 Standard ID1 (C0MSL8SID1) CAN0 Message Slot 8 Extended ID2 (C0MSL8EID2) CAN0 Message Slot 8 Extended ID1 (C0MSL8EID1) CAN0 Message Slot 8 Data 1 (C0MSL8DT1) CAN0 Message Slot 8 Data 2 (C0MSL8DT2) CAN0 Message Slot 8 Data 3 (C0MSL8DT3) CAN0 Message Slot 8 Data 4 (C0MSL8DT4) CAN0 Message Slot 8 Data 5 (C0MSL8DT5) CAN0 Message Slot 8 Data 6 (C0MSL8DT6) CAN0 Message Slot 8 Data 7 (C0MSL8DT7) CAN0 Message Slot 9 Extended ID0 (C0MSL9EID0) CAN0 Message Slot 9 Data 0 (C0MSL9DT0) CAN0 Message Slot 9 Data Length Register (C0MSL9DLC) CAN0 Message Slot 9 Time Stamp (C0MSL9TSP) CAN0 Message Slot 9 Standard ID0 (C0MSL9SID0) CAN0 Message Slot 9 Standard ID1 (C0MSL9SID1) CAN0 Message Slot 9 Extended ID2 (C0MSL9EID2) CAN0 Message Slot 9 Extended ID1 (C0MSL9EID1) CAN0 Message Slot 9 Data 1 (C0MSL9DT1) CAN0 Message Slot 9 Data 2 (C0MSL9DT2) CAN0 Message Slot 9 Data 3 (C0MSL9DT3) CAN0 Message Slot 9 Data 4 (C0MSL9DT4) CAN0 Message Slot 9 Data 5 (C0MSL9DT5) CAN0 Message Slot 9 Data 6 (C0MSL9DT6) CAN0 Message Slot 9 Data 7 (C0MSL9DT7) CAN0 Message Slot 10 Extended ID0 (C0MSL10EID0) CAN0 Message Slot 10 Data 0 (C0MSL10DT0) CAN0 Message Slot 10 Data Length Register (C0MSL10DLC) CAN0 Message Slot 10 Standard ID0 (C0MSL10SID0) CAN0 Message Slot 10 Standard ID1 (C0MSL10SID1) CAN0 Message Slot 10 Extended ID2 (C0MSL10EID2) CAN0 Message Slot 10 Extended ID1 (C0MSL10EID1) CAN0 Message Slot 10 Data 1 (C0MSL10DT1)

13-7 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.2.4 CAN Module Related Register Map (4/4) CAN MODULE H ’0080 11AA H ’0080 11A8 H ’0080 11AC H ’0080 11AE H ’0080 11B2 H ’0080 11BC H ’0080 11BA H ’0080 11B8 H ’0080 11B0 H ’0080 11B6 H ’0080 11BE H ’0080 11C2 H ’0080 11C4 H ’0080 11CA H ’0080 11C8 H ’0080 11C0 H ’0080 11C6 H ’0080 11CE H ’0080 11D2 H ’0080 11D0 H ’0080 11D6 H ’0080 11D8 H ’0080 11DA H ’0080 11DE H ’0080 11E0 H ’0080 11E6 H ’0080 11E4 H ’0080 11DC H ’0080 11E2 H ’0080 11D4 H ’0080 11E8 H ’0080 11EA H ’0080 11EE H ’0080 11F0 H ’0080 11F6 H ’0080 11F4 H ’0080 11EC H ’0080 11F2 H ’0080 11F8 H ’0080 11FA H ’0080 11FE H ’0080 3FFE H ’0080 11FC H ’0080 11CC H ’0080 11B4 CAN0 Message Slot 11 Extended ID0 (C0MSL11EID0) CAN0 Message Slot 11 Data 0 (C0MSL11DT0) CAN0 Message Slot 11 Data Length Register (C0MSL11DLC) CAN0 Message Slot 11 Time Stamp (C0MSL11TSP) CAN0 Message Slot 11 Standard ID0 (C0MSL11SID0) CAN0 Message Slot 11 Standard ID1 (C0MSL11SID1) CAN0 Message Slot 11 Extended ID2 (C0MSL11EID2) CAN0 Message Slot 11 Extended ID1 (C0MSL11EID1) CAN0 Message Slot 11 Data 1 (C0MSL11DT1) CAN0 Message Slot 11 Data 2 (C0MSL11DT2) CAN0 Message Slot 11 Data 3 (C0MSL11DT3) CAN0 Message Slot 11 Data 4 (C0MSL11DT4) CAN0 Message Slot 11 Data 5 (C0MSL11DT5) CAN0 Message Slot 11 Data 6 (C0MSL11DT6) CAN0 Message Slot 11 Data 7 (C0MSL11DT7) D0 D7 D8 D15 +0 Address +1 AddressAddress Blank addresses are reserved. CAN0 Message Slot 10 Time Stamp (C0MSL10TSP) CAN0 Message Slot 10 Data 2 (C0MSL10DT2) CAN0 Message Slot 10 Data 3 (C0MSL10DT3) CAN0 Message Slot 10 Data 4 (C0MSL10DT4) CAN0 Message Slot 10 Data 5 (C0MSL10DT5) CAN0 Message Slot 10 Data 6 (C0MSL10DT6) CAN0 Message Slot 10 Data 7 (C0MSL10DT7) CAN0 Message Slot 12 Extended ID0 (C0MSL12EID0) CAN0 Message Slot 12 Data 0 (C0MSL12DT0) CAN0 Message Slot 12 Data Length Register (C0MSL12DLC) CAN0 Message Slot 12 Time Stamp (C0MSL12TSP) CAN0 Message Slot 12 Standard ID0 (C0MSL12SID0) CAN0 Message Slot 12 Standard ID1 (C0MSL12SID1) CAN0 Message Slot 12 Extended ID2 (C0MSL12EID2) CAN0 Message Slot 12 Extended ID1 (C0MSL12EID1) CAN0 Message Slot 12 Data 1 (C0MSL12DT1) CAN0 Message Slot 12 Data 2 (C0MSL12DT2) CAN0 Message Slot 12 Data 3 (C0MSL12DT3) CAN0 Message Slot 12 Data 4 (C0MSL12DT4) CAN0 Message Slot 12 Data 5 (C0MSL12DT5) CAN0 Message Slot 12 Data 6 (C0MSL12DT6) CAN0 Message Slot 12 Data 7 (C0MSL12DT7) CAN0 Message Slot 13 Extended ID0 (C0MSL13EID0) CAN0 Message Slot 13 Data 0 (C0MSL13DT0) CAN0 Message Slot 13 Data Length Register (C0MSL13DLC) CAN0 Message Slot 13 Time Stamp (C0MSL13TSP) CAN0 Message Slot 13 Standard ID0 (C0MSL13SID0) CAN0 Message Slot 13 Standard ID1 (C0MSL13SID1) CAN0 Message Slot 13 Extended ID2 (C0MSL13EID2) CAN0 Message Slot 13 Extended ID1 (C0MSL13EID1) CAN0 Message Slot 13 Data 1 (C0MSL13DT1) CAN0 Message Slot 13 Data 2 (C0MSL13DT2) CAN0 Message Slot 13 Data 3 (C0MSL13DT3) CAN0 Message Slot 13 Data 4 (C0MSL13DT4) CAN0 Message Slot 13 Data 5 (C0MSL13DT5) CAN0 Message Slot 13 Data 6 (C0MSL13DT6) CAN0 Message Slot 13 Data 7 (C0MSL13DT7) CAN0 Message Slot 14 Extended ID0 (C0MSL14EID0) CAN0 Message Slot 14 Data 0 (C0MSL14DT0) CAN0 Message Slot 14 Data Length Register (C0MSL14DLC) CAN0 Message Slot 14 Standard ID0 (C0MSL14SID0) CAN0 Message Slot 14 Standard ID1 (C0MSL14SID1) CAN0 Message Slot 14 Extended ID2 (C0MSL14EID2) CAN0 Message Slot 14 Extended ID1 (C0MSL14EID1) CAN0 Message Slot 14 Data 1 (C0MSL14DT1) CAN0 Message Slot 14 Data 2 (C0MSL14DT2) CAN0 Message Slot 14 Data 3 (C0MSL14DT3) CAN0 Message Slot 14 Data 4 (C0MSL14DT4) CAN0 Message Slot 14 Data 5 (C0MSL14DT5) CAN0 Message Slot 14 Data 6 (C0MSL14DT6) CAN0 Message Slot 14 Data 7 (C0MSL14DT7) CAN0 Message Slot 14 Time Stamp (C0MSL14TSP) CAN0 Message Slot 15 Extended ID0 (C0MSL15EID0) CAN0 Message Slot 15 Data 0 (C0MSL15DT0) CAN0 Message Slot 15 Data Length Register (C0MSL15DLC) CAN0 Message Slot 15 Standard ID0 (C0MSL15SID0) CAN0 Message Slot 15 Standard ID1 (C0MSL15SID1) CAN0 Message Slot 15 Extended ID2 (C0MSL15EID2) CAN0 Message Slot 15 Extended ID1 (C0MSL15EID1) CAN0 Message Slot 15 Data 1 (C0MSL15DT1) CAN0 Message Slot 15 Data 2 (C0MSL15DT2) CAN0 Message Slot 15 Data 3 (C0MSL15DT3) CAN0 Message Slot 15 Data 4 (C0MSL15DT4) CAN0 Message Slot 15 Data 5 (C0MSL15DT5) CAN0 Message Slot 15 Data 6 (C0MSL15DT6) CAN0 Message Slot 15 Data 7 (C0MSL15DT7) CAN0 Message Slot 15 Time Stamp (C0MSL15TSP)

13-8 32170/32174 Group User's Manual (Rev. 2.1) W = : Only writing a 1 is effective. Automatically cleared to 0 in hardware.

13.2.1 CAN Control Register

I CAN0 Control Register (CAN0CNT) <Address:H'0080 1000> CAN MODULE <When reset:H'0011> D Bit Name Function R W 0-3 No functions assigned 0 –

4 RBO 0: Enables normal operation

(Return bus off) 1: Requests clearing of error counter

5 TSR 0: Enables count operation

(Time stamp Counter reset) 1: Initializes count (by setting H'0000) 6-7 TSP D6 D7 (Time stamp prescaler) 0 0 : Selects CAN bus bit clock 0 1 : Selects CAN bus bit clock divided by 2 1 0 : Selects CAN bus bit clock divided by 3 1 1 : Selects CAN bus bit clock divided by 4 8-9 No functions assigned 0 –

10 No functions assigned (Always set this bit to 0) 0 –

11 FRST 0: Negates rest

(Forcible reset) 1: Forcibly resets

12 BCM 0: Disables BasicCAN function

(BasicCAN mode) 1: BasicCAN mode

13 No functions assigned 0 –

14 LBM 0: Disables loopback function

(Loopback mode) 1: Enables loopback function

15 RST 0: Negates reset

(CAN reset) 1: Requests reset D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 RBO TSR TSP FRST BCM LBM RST

13-9 32170/32174 Group User's Manual (Rev. 2.1) CAN MODULE (1) RBO (Return Bus Off) bit (D4) Setting this bit to 1 clears the Receive Error Counter (CAN0REC) and Transmit Error Counter (CAN0TEC) and forcibly places the CAN module into an error active state. This bit is cleared when an error active state is entered. Note: After clearing the error counter, transmission becomes possible when 11 consecutive recessive bits are detected on the CAN bus. (2) TSR (Time Stamp Counter Reset) bit (D5) Setting this bit to 1 clears the value of the CAN Time Stamp Counter Register (CAN0TSTMP) to H'0000. This bit is cleared when the value of the CAN Time Stamp Counter Register (CAN0TSTMP) is cleared to H'0000. (3) TSP (Time Stamp Prescaler) bits (D6, D7) These bits select the count clock source for the time stamp counter. Note: Do not change settings of TSP bits while CAN is operating (CAN Status Register CRS bit = 0). (4) FRST (Forcible Reset) bit (D11) When the FRST bit is set to 1, the CAN module is separated from the CAN bus regardless of whether or not the CAN module is communicating and the protocol control unit is reset. Note 1:To restart CAN communication, the FRST and RST bits must be cleared to 0. Note 2:If the FRST bit is set to 1 during communication, the CTX pin output goes high immediately after that. Therefore, setting the FRST bit to 1 while transmitting CAN frame may cause a CAN bus error. Note 3: The CAN Message Slot Control Register’s transmit/receive requests are not cleared by setting the FRST or RST bit. (5) BCM (BasicCAN Mode) bit (D12) By setting this bit to 1, the CAN module can be operated in BasicCAN mode.

• Operation during BasicCAN mode In BasicCAN mode, two local slots-slots 14 and 15-are used as double buffers, and receive frames that are found matching to the ID by acceptance filtering are stored alternately in slots 14 and 15. Used for this acceptance filtering when slot 14 is active (next receive frame to be stored in slot 14) are the ID set for slot 14 and local mask A, and those used when slot 15 is active are the ID set for slot 15 and local mask B. Two types of frames-data frame and remote frame-can be received in this mode.

13-10 32170/32174 Group User's Manual (Rev. 2.1) By using the same ID and setting the same value in mask registers for the two slots, the possibility of a message-lost trouble when, for example, receiving frames which have many IDs can be reduced.

• Procedure for entering BasicCAN mode Follow the procedure below during initialization: (a) Set the IDs for slots 14 and 15 and local mask registers A and B. (We recommend setting the same value.) (b) Set the frame types handled by slots 14 and 15 (standard or extended) in the CAN Extended ID Register. (We recommend setting the same type.) (c) Set the Message Slot Control Register for slots 14 and 15 to for data frame reception. (d) Set the BCM bit to 1. Note 1:Do not change settings of BCM bit when CAN is operating (CAN Status Register CRS bit = 0). Note 2:The first slot that is active after clearing the RST bit is slot 14. Note 3:Even during BasicCAN mode, slots 0 to 13 can be used as in normal operation. (6) LBM (Loopback Mode) bit (D14) When the LBM bit is set to 1, if a receive slot exists whose ID matches that of the frame sent by the CAN module itself, then the frame can be received. Note 1:No ACK is returned for the transmit frame. Note 2:Do not change settings of LBM bit when CAN is operating (CAN Status Register CRS bit = 0). (7) RST (CAN Reset) bit (D15) When the RST bit is cleared to 0, the CAN module is connected to the CAN bus and becomes possible to communicate after detecting 11 consecutive recessive bits. Also, the CAN Time Stamp Count Register thereby starts counting. When the RST bit is set to 1, the CAN module is reset so that after sending a frame from the slot which has had a transmit request set, the protocol control unit is reset and the CAN module is disconnected from the CAN bus. Frames received during this time are processed normally. Note 1:It is inhibited to set a new transmit request for a while from when the CAN Status Register CRS bit is set to 1 after setting the RST bit to 1 till when the protocol control unit is reset. Note 2:When the protocol control unit is reset by setting the RST bit to 1, the CAN Time Stamp Count Register and CAN Transmit/Receive Error Count Registers are initialized to 0. Note 3:To restart CAN communication, the FRST and RST bits must be cleared to 0. CAN MODULE

13-11 32170/32174 Group User's Manual (Rev. 2.1)

13.2.2 CAN Status Register

I CAN0 Status Register (CAN0STAT) <Address:H'0080 1002> <When reset:H'0100> D Bit Name Function R W

1 BOS 0: Not Bus off –

(Bus off status) 1: Bus off state

2 EPS 0: Not error passive –

(Error passive status) 1: Error passive state

3 CBS 0: No error occurred –

(CAN bus error) 1: Error occurred

4 BCS 0: Normal mode –

(BasicCAN status) 1: BasicCAN mode

5 No functions assigned 0 –

6 LBS 0: Normal mode –

(Loopback status) 1: Loopback mode

7 CRS 0: Operating –

(CAN reset status) 1: Reset

8 RSB 0: Not receiving –

(Receive status) 1: Receiving

9 TSB 0: Not transmitting –

(Transmit status) 1: Transmitting

10 RSC 0: Reception not completed yet –

(Receive complete status) 1: Reception completed

11 TSC 0: Transmission not completed yet –

(Transmit complete status) 1: Transmission completed D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 BOS EPS CBS BCS 0 LBS CRS RSB TSB RSC TSC MSN CAN MODULE

13-12 32170/32174 Group User's Manual (Rev. 2.1) (1) BOS (Bus Off Status) bit (D1) When BOS bit = 1, it means that the CAN module is in a bus-off state. [Set condition] This bit is set to 1 when the transmit error counter value exceeded 255 and a bus-off state is entered. [Clear condition] This bit is cleared when restored from the bus-off state. (2) EPS (Error Passive Status) bit (D2) When EPS bit = 1, it means that the CAN module is in an error passive state. [Set condition] This bit is set to 1 when the transmit or receive error counter value exceeded 127 and an error passive state is entered. [Clear condition] This bit is cleared when restored from the error passive state. D Bit Name Function R W 12-15 MSN Number of message slot which has finished sending or receiving (Message slot number) 0000 : Slot0 – 0001 : Slot1 0010 : Slot2 0011 : Slot3 0100 : Slot4 0101 : Slot5 0110 : Slot6 0111 : Slot7 1000 : Slot8 1001 : Slot9 1010 : Slot10 1011 : Slot11 1100 : Slot12 1101 : Slot13 1110 : Slot14 1111 : Slot15 CAN MODULE

13-13 32170/32174 Group User's Manual (Rev. 2.1) (3) CBS (CAN Bus Error) bit (D3) [Set condition] This bit is set to 1 when an error on the CAN bus is detected. [Clear condition] This bit is cleared when normally transmitted or received. (4) BCS (BasicCAN Status) bit (D4) When BCS bit = 1, it means that the CAN module is operating in BasicCAN mode. [Set condition] This bit is set to 1 when operating in BasicCAN mode. Conditions for operating in BasicCAN mode

• The CAN Control Register BCM bit must be set to 1.
• Slots 14 and 15 both must be set for data frame reception. [Clear condition] This bit is cleared by clearing the BCM bit to 0. (5) LBS (Loopback Status) bit (D6) When LBS bit = 1, it means that the CAN module is operating in loopback mode. [Set condition] This bit is set to 1 by setting the CAN Control Register LBM (loopback mode) bit to 1. [Clear condition] This bit is cleared by clearing the LBM bit to 0. (6) CRS (CAN Reset Status) bit (D7) When CRS bit = 1, it means that the protocol control unit is in a reset state. [Set condition] This bit is set to 1 when the CAN module's protocol control unit is in a reset state. [Clear condition] This bit is cleared by clearing the CAN Control Register RST (CAN reset) bit to 0. CAN MODULE

13-14 32170/32174 Group User's Manual (Rev. 2.1) (7) RSB (Receive Status) bit (D8) [Set condition] This bit is set to 1 when the CAN module is operating as a receive node. [Clear condition] This bit is cleared when the CAN module started operating as a transmit node or entered a bus idle state. (8) TSB (Transmit Status) bit (D9) [Set condition] This bit is set to 1 when the CAN module is operating as a transmit node. [Clear condition] This bit is cleared when the CAN module started operating as a receive node or entered a bus idle state. (9) RSC (Receive Complete Status) bit (D10) [Set condition] This bit is set to 1 when the CAN module finished receiving normally (regardless of whether any slot exists that meets receive conditions). [Clear condition] This bit is cleared when the CAN module finished transmitting normally. (10) TSC (Transmit Complete Status) bit (D11) [Set condition] This bit is set to 1 when the CAN module finished transmitting normally. [Clear condition] This bit is cleared when the CAN module finished receiving normally. (11) MSN (Message Slot Number) bits (D12-D15) These bits show the relevant slot number when the CAN module finished transmitting or finished storing received data. This bit cannot be cleared to 0 in software. Note: If during loopback mode the CAN module receives the frame it itself transmitted, the MSN bit behaves as follows: The bit indicates the transmit slot number when the module finishes sending and is then cleared to 0 when the module stores the received data. CAN MODULE

13-15 32170/32174 Group User's Manual (Rev. 2.1)

13.2.3 CAN Extended ID Register

I CAN0 Extended ID Register (CAN0EXTID) <Address:H'0080 1004> This register selects the format of frames handled in message slots corresponding to each bit. The standard ID format is selected when a message slot's corresponding bit is set to 0, or the extended ID format is selected when the bit is set to 1. Note: Settings of each bit of this register can only be changed when the corresponding slot does not have transmit or receive requests set. <When reset:H'0000> D Bit Name Function R W

0 IDE0 (Extended ID0) 0: Standard ID format

1 IDE1 (Extended ID1) 1: Extended ID format

2 IDE2 (Extended ID2)

3 IDE3 (Extended ID3)

4 IDE4 (Extended ID4)

5 IDE5 (Extended ID5)

6 IDE6 (Extended ID6)

7 IDE7 (Extended ID7)

8 IDE8 (Extended ID8)

9 IDE9 (Extended ID9)

10 IDE10 (Extended ID10)

11 IDE11 (Extended ID11)

12 IDE12 (Extended ID12)

13 IDE13 (Extended ID13)

14 IDE14 (Extended ID14)

15 IDE15 (Extended ID15)

D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 IDE0 IDE1 IDE2 IDE3 IDE4 IDE5 IDE6 IDE7 IDE8 IDE9 IDE10 IDE11 IDE12 IDE13 IDE14 IDE15 CAN MODULE

13-16 32170/32174 Group User's Manual (Rev. 2.1)

13.2.4 CAN Configuration Register

I CAN0 Configuration Register (CAN0CONF) <Address:H'0080 1006> <When reset:H'0000> D Bit Name Function R W 0-1 SJW Sets reSynchronization Jump Width (reSynchronization Jump Width) 00: SJW = 1Tq 01: SJW = 2Tq 10: SJW = 3Tq 11: SJW = 4Tq 2-4 PH2 Sets Phase Segment2 (Phase Segment2) 000: Settings inhibited 001: Phase Segment2 = 2Tq 010: Phase Segment2 = 3Tq 011: Phase Segment2 = 4Tq 100: Phase Segment2 = 5Tq 101: Phase Segment2 = 6Tq 110: Phase Segment2 = 7Tq 111: Phase Segment2 = 8Tq 5-7 PH1 Sets Phase Segment1 (Phase Segment1) 000: Phase Segment1 = 1Tq 001: Phase Segment1 = 2Tq 010: Phase Segment1 = 3Tq 011: Phase Segment1 = 4Tq 100: Phase Segment1 = 5Tq 101: Phase Segment1 = 6Tq 110: Phase Segment1 = 7Tq 111: Phase Segment1 = 8Tq D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 SJW PH2 PH1 PRB SAM CAN MODULE

13-17 32170/32174 Group User's Manual (Rev. 2.1) <When reset:H'0000> D Bit Name Function R W 8-10 PRB Sets Propagation Segment (Propagation Segment) 000: Propagation Seqment =1Tq 001: Propagation Seqment = 2Tq 010: Propagation Seqment = 3Tq 011: Propagation Seqment = 4Tq 100: Propagation Seqment = 5Tq 101: Propagation Seqment = 6Tq 110: Propagation Seqment = 7Tq 111: Propagation Seqment = 8Tq

11 SAM 0: Samples once

(Number of times sampled) 1: Samples three times 12-15 No functions assigned 0 – CAN MODULE Note 1: During CAN operation (CAN Status Register CRS bit = 0), do not alter settings of the CAN Configuration Registers (CAN0CONF and CAN1CONF). Note 2: The bit configuration in this register must be set so as to meet the conditions below.

• Number of Tq’s in one bit: 8 to 25 Tq’s
• SJW < min (Phase Segment 1, Phase Segment 2)
• Phase Segment 2 = max (Phase Segment 1, IPT) However, IPT = 2 for the M32R/ECU’s internal CAN modules. Note that min() is the function that returns a smaller value, whereas max() is the function that returns the maximum value.

13-18 32170/32174 Group User's Manual (Rev. 2.1) (1) SJW bits (D0-D1) These bits set reSynchronization Jump Width. (2) PH2 bits (D2-D4) These bits set the width of Phase Segment2. Note: The internal CAN module of the M32R/ECU has IPT (Information Processing Time) = 2. Because PH2 bits = 0 after reset, be sure to change it to a value equal to or greater than 2 before you use the CAN module. (3) PH1 bits (D5-D7) These bits set the width of Phase Segment1. (4) PRB bits (D8-D10) These bits set the width of Propagation Segment. (5) SAM bit (D11) This bit sets the number of times each bit is sampled. When SAM = 0, the value sampled at the end of Phase Segment1 is assumed to be the value of the bit. When SAM = 1, the value of the bit is determined by a majority circuit from values sampled at three points-one sampled at the end of Phase Segment1, one sampled before 1Tq, and one sampled before 2Tq. Table 13.2.1 Typical Settings of Bit Timing when CPU Clock = 40 MHz Baud Rate BRP Set Value Tq Period (ns) Tq's for 1 Bit PROP+PH1 PH2 Sampling Point 1M bps 3 100 10 7 2 80% 3 100 10 6 3 70% 3 100 10 5 4 60% 4 125 8 5 2 75% 4 125 8 4 3 63% 500Kbps 4 125 16 13 2 88% 4 125 16 12 3 81% 4 125 16 11 4 75% 7 200 10 7 2 80% 7 200 10 6 3 70% 7 200 10 5 4 60% 9 250 8 5 2 75% 9 250 8 4 3 63% CAN MODULE

13-19 32170/32174 Group User's Manual (Rev. 2.1)

13.2.5 CAN Time Stamp Count Register

I CAN0 Time Stamp Count Register (CAN0TSTMP) <Address:H'0080 1008> <When reset:H'0000> D Bit Name Function R W 0-15 CANSTMP 16-bit counter value – The CAN module contains a 16-bit counter. The count period can be chosen to be the CAN bus bit period divided by 1, 2, 3, or 4 by setting the CAN Control Register (CAN0CNT)'s TSP (Time Stamp Prescaler) bits. When the CAN module finishes transmitting or receiving, it captures the counter value and stores it in a message slot. The counter is made to start counting by clearing the CAN Control Register (CAN0CNT)'s RST bit to 0. Note 1:The protocol control unit is reset and the counter is initialized to H'0000 by setting the CAN Control Register (CAN0CNT)'s RST (CAN Reset) bit to 1. Also, the counter can be initialized to H'0000 while the CAN module is operating by setting TSR (Time Stamp Counter Reset) bit to 1. Note 2:During loopback mode, if an ID-matching slot exists, the CAN module stores the time stamp value in the corresponding slot when it finished receiving. (No time stamp value is stored this way when the CAN module finished transmitting.) D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 CANTSTMP CAN MODULE

13-20 32170/32174 Group User's Manual (Rev. 2.1)

13.2.6 CAN Error Count Registers

I CAN0 Receive Error Count Register (CAN0REC) <Address:H'0080 100A> <When reset:H'00> D Bit Name Function R W 0-7 REC Receive error count value – (Receive error counter) In an error-active/error-passive state, a receive error count is stored in this register. When received normally, the counter counts down; when an error occurs, the counter counts up. When received normally while REC 128 (error-passive), REC is set to 127. In a bus-off state, an indeterminate value is stored in this register. The count is reset to H'00 upon returning to an error-active state. I CAN0 Transmit Error Count Register (CAN0TEC) <Address:H'0080 100B> In an error-active/error-passive state, a transmit error count is stored in this register. When transmitted normally, the counter counts down; when an error occurs, the counter counts up. In a bus-off state, an indeterminate value is stored in this register. The count is reset to H'00 upon returning to an error-active state. <When reset:H'00> D Bit Name Function R W 8-15 TEC Transmit error count value – (Transmit error counter) D 8 9 1 01 11 21 31 4 D 1 5 TEC D 0 123456 D 7 REC CAN MODULE

13-21 32170/32174 Group User's Manual (Rev. 2.1)

13.2.7 CAN Baud Rate Prescaler

I CAN0 Baud Rate Prescaler (CAN0BRP) <Address:H'0080 1016> <When reset:H'01> D Bit Name Function R W 0-7 BRP Selects baud rate prescaler value D 0 123456 D 7 CANBRP This register sets the Tq period of CAN. The CAN baud rate is determined by (Tq period × number of Tq's for 1 bit). Tq period = (CANBRP + 1)/ CPU clock Number of Tq's for 1 bit = Synchronization Segment + Progagation Segment + Phase Segment 1 + Phase Segment 2 Note 1: Setting H'00 (divided by 1) is inhibited. Note 2: During CAN operation (CAN Status Register CRS bit = 0), do not alter settings of the CAN Baud Rate Prescaler (CAN0BRP). CAN transfer baud rate = Tq period × number of Tq's for 1 bit CAN MODULE

13-22 32170/32174 Group User's Manual (Rev. 2.1)

13.2.8 CAN Interrupt Related Registers

I CAN0 Slot Interrupt Status Register (CAN0SLIST) <Address:H'0080 100C> W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 SSB0 SSB1 SSB2 SSB3 SSB4 SSB5 SSB6 SSB7 SSB8 SSB9 SSB10SSB11SSB12SSB13 SSB14 SSB15 <When reset:H'0000> D Bit Name Function R W

0 SSB0 (Slot 0 interrupt request status) 0: No interrupt request

1 SSB1 (Slot 1 interrupt request status) 1: Interrupt requested

2 SSB2 (Slot 2 interrupt request status)

3 SSB3 (Slot 3 interrupt request status)

4 SSB4 (Slot 4 interrupt request status)

5 SSB5 (Slot 5 interrupt request status)

6 SSB6 (Slot 6 interrupt request status)

7 SSB7 (Slot 7 interrupt request status)

8 SSB8 (Slot 8 interrupt request status)

9 SSB9 (Slot 9 interrupt request status)

10 SSB10 (Slot 10 interrupt request status)

11 SSB11 (Slot 11 interrupt request status)

12 SSB12 (Slot 12 interrupt request status)

13 SSB13 (Slot 13 interrupt request status)

14 SSB14 (Slot 14 interrupt request status)

15 SSB15 (Slot 15 interrupt request status)

13-23 32170/32174 Group User's Manual (Rev. 2.1) When using CAN interrupts, this register lets you know which slot requested an interrupt.

• Slots set for transmission The bit is set to 1 when the CAN module finished transmitting. The bit is cleared by writing a 0 in software.
• Slots set for reception The bit is set to 1 when the CAN module finished receiving and finished storing the received message in the message slot. The bit is cleared by writing a 0 in software. When writing to the CAN slot interrupt status, make sure the bits you want to clear are set to 0 and all other bits are set to 1. The bits thus set to 1 are unaffected by writing in software and retain the value they had before you write. Note 1:If the automatic response function is enabled for remote frame receive slots, the status is set after the CAN module received a remote frame and when it transmitted a data frame. Note 2:For remote frame transmit slots, the status is set after the CAN module transmitted a remote frame and when it received a data frame. Note 3:If the status is set by an interrupt request at the same time it is cleared in software, the former has priority so that the status is set. CAN MODULE

13-24 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Slot Interrupt Mask Register (CAN0SLIMK) <Address:H'0080 1010> This register controls interrupt requests generated at completion of data transmission or reception in each corresponding slot by enabling or disabling them. When IRBn (n = 0-15) is set to 1, interrupt requests to be generated at completion of transmission or reception in the corresponding slot are enabled. The CAN Slot Interrupt Status Register (CAN0SLIST) shows you which slot has requested the interrupt. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 IRB0 IRB1 IRB2 IRB3 IRB4 IRB5 IRB6 IRB7 IRB8 IRB9 IRB10 IRB11 IRB12 IRB13 IRB14 IRB15 <When reset:H'0000> D Bit Name Function R W

0 IRB0 (Slot 0 interrupt request mask) 0: Masks (disables) interrupt request

1 IRB1 (Slot 1 interrupt request mask) 1: Enables interrupt request

2 IRB2 (Slot 2 interrupt request mask)

3 IRB3 (Slot 3 interrupt request mask)

4 IRB4 (Slot 4 interrupt request mask)

5 IRB5 (Slot 5 interrupt request mask)

6 IRB6 (Slot 6 interrupt request mask)

7 IRB7 (Slot 7 interrupt request mask)

8 IRB8 (Slot 8 interrupt request mask)

9 IRB9 (Slot 9 interrupt request mask)

10 IRB10 (Slot 10 interrupt request mask)

11 IRB11 (Slot 11 interrupt request mask)

12 IRB12 (Slot 12 interrupt request mask)

13 IRB13 (Slot 13 interrupt request mask)

14 IRB14 (Slot 14 interrupt request mask)

15 IRB15 (Slot 15 interrupt request mask)

13-25 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Error Interrupt Status Register (CAN0ERIST) <Address:H'0080 1014> W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. When using CAN interrupts and the interrupt sources are associated with errors, this register lets you know which source generated the interrupt. (1) EIS (CAN Bus Error Interrupt Status) bit (D5) This bit is set to 1 when a communication error is detected. This bit is cleared by writing a 0 in software. (2) PIS (Error Passive Interrupt Status) bit (D6) This bit is set to 1 when the CAN module goes to an error passive state. This bit is cleared by writing a 0 in software. (3) OIS (Bus Off Interrupt Status) bit (D7) This bit is set to 1 when the CAN module goes to a bus-off state. This bit is cleared by writing a 0 in software. When writing to the CAN error interrupt status, make sure the bits you want to clear are set to 0 and all other bits are set to 1. The bits thus set to 1 are unaffected by writing in software and retain the value they had before you write. <When reset:H00> D Bit Name Function R W 0-4 No functions assigned 0 –

5 EIS 0: No interrupt request

(CAN bus error interrupt status) 1: Interrupt requested

6 PIS

(Error passive interrupt status)

7 OIS

(Bus off interrupt status) D 0 123456 D 7 EIS PIS OIS CAN MODULE

13-26 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Error Interrupt Mask Register (CAN0ERIMK) <Address:H'0080 1015> (1) EIM (CAN Bus Error Interrupt Mask) bit (D5) This bit controls interrupt requests generated for occurrence of CAN bus errors by enabling or disabling them. CAN bus error interrupt requests are enabled by setting this bit to 1. (2) PIM (Error Passive Interrupt Mask) bit (D6) This bit controls interrupt requests generated when the CAN module enters an error passive state by enabling or disabling them. Error passive interrupt requests are enabled by setting this bit to 1. (3) OIM (Bus Off Interrupt Mask) bit (D7) This bit controls interrupt requests generated when the CAN module enters a bus-off state by enabling or disabling them. Bus-off interrupt requests are enabled by setting this bit to 1. D 8 9 1 01 11 21 31 4 D 1 5 EIM PIM OIM <When reset:H00> D Bit Name Function R W 8-12 No functions assigned 0 –

13 EIM 0: Masks (disables) interrupt request

(CAN bus error interrupt mask) 1: Enables interrupt request

14 PIM

(Error passive interrupt mask)

15 OIM

(Bus off interrupt mask) CAN MODULE

13-27 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.2.5 Block Diagram of CAN0 Group Interrupts (1/3) CAN MODULE CAN0 transmit/receive & error interrupts Data bus IRB0 F/F SSB0 F/Fb0 IRB1 F/F SSB1 F/Fb1 IRB2 F/F SSB2 F/Fb2 IRB3 F/F SSB3 F/Fb3 IRB4 F/F SSB4 F/Fb4 (Level) 19-source inputs CAN0SLIST <H ’0080 100C> CAN0SLIMK <H ’0080 1010> Slot 0 transmit/receive completed IRB5 F/F SSB5 F/Fb5 IRB6 F/F SSB6 F/Fb6 IRB7 F/F To remaining 11-source inputs in the next page F/Fb7 SSB7 Slot 1 transmit/receive completed Slot 2 transmit/receive completed Slot 3 transmit/receive completed Slot 4 transmit/receive completed Slot 5 transmit/receive completed Slot 6 transmit/receive completed Slot 7 transmit/receive completed

13-28 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.2.6 Block Diagram of CAN0 Group Interrupts (2/3) CAN MODULE CAN0SLIST <H ’0080 100C> CAN0SLIMK <H ’0080 1010> b13 IRB13 F/F SSB13 F/Fb13 b14 IRB14 F/F SSB14 F/Fb14 b15 IRB15 F/F F/Fb15 SSB15 Data bus (Level) 19-source inputs Slot 8 transmit/receive completed To remaining 3-source inputs in the next page Slot 9 transmit/receive completed Slot 10 transmit/receive completed Slot 11 transmit/receive completed Slot 12 transmit/receive completed Slot 13 transmit/receive completed Slot 14 transmit/receive completed Slot 15 transmit/receive completed

13-29 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.2.7 Block Diagram of CAN0 Group Interrupts (3/3) CAN MODULE CAN0ERIST <H ’0080 1014> CAN0ERIMK <H ’0080 1015> CAN bus error occurs Go to error passive state Go to bus-off state To preceding page Data bus (Level) 19-source inputs

13-30 32170/32174 Group User's Manual (Rev. 2.1)

13.2.9 CAN Mask Registers

I CAN0 Global Mask Register Standard ID0 (C0GMSKS0) <Address:H'0080 1028> I CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0)<Address:H'0080 1030> I CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0)<Address:H'0080 1038> I CAN0 Global Mask Register Standard ID1 (C0GMSKS1) <Address:H'0080 1029> I CAN0 Local Mask Register A Standard ID1 (C0LMSKAS1)<Address:H'0080 1031> I CAN0 Local Mask Register B Standard ID1 (C0LMSKBS1)<Address:H'0080 1039> <When reset:H'00> D Bit Name Function R W 0-2 No functions assigned 0 – 3-7 SID0M-SID4M 0: ID not checked (Standard ID0 to standard ID4) 1: ID checked D 0 123456 D 7 SID0M SID1M SID2M SID3M SID4M <When reset:H'00> D Bit Name Function R W 8-9 No functions assigned 0 – 10-15 SID5M-SID10M 0: ID not checked (Standard ID5 to standard ID10) 1: ID checked D 8 9 1 01 11 21 31 4 D 1 5 SID5M SID6M SID7M SID8M SID9M SID10M CAN MODULE

13-31 32170/32174 Group User's Manual (Rev. 2.1) Three registers are used in acceptance filtering: Global Mask Register, Local Mask Register A, and Local Mask Register B. The Global Mask Register is used for message slots 0-13, while Local Mask Registers A and B are used for message slots 14 and 15, respectively.

• When a bit in this register is set to 0, its corresponding ID bit is masked (assumed to have matched) during acceptance filtering.
• When a bit in this register is set to 1, its corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set for the message slot, the received data is stored in it. Note 1:SID0M corresponds to the MSB of standard ID. Note 2:The Global Mask Register can only be changed when none of slots 0-13 have receive requests set. Note 3:The Local Mask Register A can only be changed when slot 14 does not have a receive request set. Note 4:The Local Mask Register B can only be changed when slot 15 does not have a receive request set. CAN MODULE

13-32 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Global Mask Register Extended ID1 (C0GMSKE1) <Address:H'0080 102B> I CAN0 Local Mask Register A Extended ID1 (C0LMSKAE1)<Address:H'0080 1033> I CAN0 Local Mask Register B Extended ID1 (C0LMSKBE1)<Address:H'0080 103B> I CAN0 Global Mask Register Extended ID0 (C0GMSKE0) <Address:H'0080 102A> I CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0)<Address:H'0080 1032> I CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0)<Address:H'0080 103A> <When reset:H'00> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 EID0M-EID3M 0: ID not checked (Extended ID0 to extended ID3) 1: ID checked D 0 123456 D 7 EID0M EID1M EID2M EID3M D 8 9 1 01 11 21 31 4 D 1 5 EID4M EID5M EID6M EID7M EID8M EID9M EID10M EID11M <When reset:H'00> D Bit Name Function R W 8-15 EID4M-EID11M 0: ID not checked (Extended ID4 to extended ID11) 1: ID checked CAN MODULE

13-33 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Global Mask Register Extended ID2 (C0GMSKE2) <Address:H'0080 102C> I CAN0 Local Mask Register A Extended ID2 (C0LMSKAE2)<Address:H'0080 1034> I CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2)<Address:H'0080 103C> Three registers are used in acceptance filtering: Global Mask Register, Local Mask Register A, and Local Mask Register B. The Global Mask Register is used for message slots 0-13, while Local Mask Registers A and B are used for message slots 14 and 15, respectively.

• When a bit in this register is set to 0, its corresponding ID bit is masked (assumed to have matched) during acceptance filtering.
• When a bit in this register is set to 1, its corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set for the message slot, the received data is stored in it. Note 1:EID0M corresponds to the MSB of extended ID. Note 2:The Global Mask Register can only be changed when none of slots 0-13 have receive requests set. Note 3:The Local Mask Register A can only be changed when slot 14 does not have a receive request set. Note 4:The Local Mask Register B can only be changed when slot 15 does not have a receive request set. D0 1 2 3 4 5 6 D7 EID12M EID13M EID14M EID15M EID16M EID17M <When reset:H'00> D Bit Name Function R W 0,1 No functions assigned 0 – 2-7 EID12M-EID17M 0: ID not checked (Extended ID12 to extended ID17) 1: ID checked CAN MODULE

13-34 32170/32174 Group User's Manual (Rev. 2.1)

13.2.10 CAN Message Slot Control Registers

I CAN0 Message Slot0 Control Registers (C0MSL0CNT) <Address:H'0080 1050> I CAN0 Message Slot1 Control Registers (C0MSL1CNT) <Address:H'0080 1051> I CAN0 Message Slot2 Control Registers (C0MSL2CNT) <Address:H'0080 1052> I CAN0 Message Slot3 Control Registers (C0MSL3CNT) <Address:H'0080 1053> I CAN0 Message Slot4 Control Registers (C0MSL4CNT) <Address:H'0080 1054> I CAN0 Message Slot5 Control Registers (C0MSL5CNT) <Address:H'0080 1055> I CAN0 Message Slot6 Control Registers (C0MSL6CNT) <Address:H'0080 1056> I CAN0 Message Slot7 Control Registers (C0MSL7CNT) <Address:H'0080 1057> I CAN0 Message Slot8 Control Registers (C0MSL8CNT) <Address:H'0080 1058> I CAN0 Message Slot9 Control Registers (C0MSL9CNT) <Address:H'0080 1059> I CAN0 Message Slot10 Control Registers (C0MSL10CNT)<Address:H'0080 105A> I CAN0 Message Slot11 Control Registers (C0MSL11CNT)<Address:H'0080 105B> I CAN0 Message Slot12 Control Registers (C0MSL12CNT)<Address:H'0080 105C> I CAN0 Message Slot13 Control Registers (C0MSL13CNT)<Address:H'0080 105D> I CAN0 Message Slot14 Control Registers (C0MSL14CNT)<Address:H'0080 105E> I CAN0 Message Slot15 Control Registers (C0MSL15CNT)<Address:H'0080 105F> <When reset:H'00> D Bit Name Function R W

0 TR 0: Does not use message slot as transmit slot

(Transmit request) 1: Uses message slot as transmit slot

1 RR 0: Does not use message slot as receive slot

(Receive request) 1: Uses message slot as receive slot

2 RM 0: Transmits/receives data frame

(Remote) 1: Transmits/receives remote frame

3 RL 0: Enables automatic response for remote frame

(Automatic response inhibit) 1: Disables automatic response for remote frame

4 RA BasicCAN mode –

(Remote active) 0: Receives data frame (status) 1: Receives remote frame (status) Normal mode 0: Data frame 1: Remote frame D0(D8) 1 23456 D7(D15) TR RR RM RL RA ML TRSTAT TRFIN CAN MODULE

13-35 32170/32174 Group User's Manual (Rev. 2.1) (1) TR (Transmit Request) bit (D0) To use the message slot as a transmit slot, set this bit to 1. To use the message slot as a data frame or remote frame receive slot, set this bit to 0. (2) RR (Receive Request) bit (D1) To use the message slot as a receive slot, set this bit to 1. To use the message slot as a data frame or remote frame transmit slot, set this bit to 0. If both TR (Transmit Request) and RR (Receive Request) bits are set to 1, device operation is indeterminate. D Bit Name Function R W

5 ML 0: Message-lost not occurred

(Message slot) 1: Message-lost occurred

6 TRSTAT For transmit slots –

(Transmit/receive status) 0: Transmission idle 1: Transmit request accepted For receive slots 0: Reception idle 1: Storing received data

7 TRFIN For transmit slots

(Transmit/receive complete) 0: Not transmitted yet 1: Finished transmitting For receive slots 0: Not received yet 1: Finished receiving W = : Only writing a 0 is effective; when you write a 1, the previous value is retained. Note 1: If a transmit request is written to the CAN Message Slot Control Register while the CAN module is reset (CANCNT’s FRST or RST bit = 1), the module does not start sending until it detects 11 consecutive recessive bits on the CAN bus after leaving the reset state. Note 2: If a data/remote frame transmit request is issued for multiple slots, the slot with the smallest slot number transmits a frame. If a data/remote frame receive request is issued for multiple slots, the slot with the smallest slot number among those that meet receive conditions receives a frame. CAN MODULE

13-36 32170/32174 Group User's Manual (Rev. 2.1) (3) RM (Remote) bit (D2) To handle remote frames in the message slot, set this bit to 1. The message slot may be set to handle remote frames in following two ways:

• Set for remote frame transmission The data set in the message slot is transmitted as a remote frame. When the CAN module finished transmitting, the slot is automatically changed to a data frame receive slot. However, if a data frame is received before the CAN module finished sending a remote frame, the data is stored in the message slot and the remote frame is not transmitted.
• Set for remote frame reception Remote frames are received. The processing to be performed after receiving a remote frame is selected by RL (automatic response inhibit) bit. (4) RL (Automatic Response Inhibit) bit (D3) This bit is effective when the message slot has been set as a remote frame receive slot. It selects the processing to be performed after receiving a remote frame. When this bit is set to 0, the message slot automatically changes to a transmit slot after receiving a remote frame and transmits the data set in it as a data frame. When this bit is set to 1, the message slot stops operating after receiving a remote frame. Note: Always set this bit to 0 unless the message slot is set for remote frame reception. (5) RA (Remote Active) bit (D4) This bit functions differently for slots 0-13 and slots 14 and 15.
• Slots 0-13 This bit is set to 1 when the message slot is set for remote frame transmission (reception). Then it is cleared to 0 when remote frame transmission (reception) is completed.
• Slots 14, 15 The function of this bit differs depending on how the CAN Control Register's BCM (BasicCAN mode) bit is set. If BCM = 0 (normal operation), this bit is set to 1 when the message slot is set for remote frame transmission (reception). If BCM = 1 (BasicCAN), this bit shows which type of frame is received. In BasicCAN mode, the received data is stored in slots 14 and 15 for both data frame and remote frame. If RA = 0, it means that the frame stored in the slot is a data frame; if RA = 1, it means that the frame stored in the slot is a remote frame. CAN MODULE

13-37 32170/32174 Group User's Manual (Rev. 2.1) (6) ML (Message Lost) bit (D5) This bit is effective for receive slots. It is set to 1 when the message slot contains unread receive data which is overwritten by reception. This bit is cleared by writing a 0 in software. (7) TRSTAT (Transmit/Receive Status) bit (D6) This bit indicates that the CAN module is transmitting or receiving and is accessing the message slot. This bit is set to 1 when the CAN module is accessing, and set to 0 when not accessing.

• For transmit slots This bit is set to 1 when a transmit request for the message slot is accepted. It is cleared to 0 when the CAN module lost bus arbitration, when a CAN bus error occurs, or when transmission is completed.
• For receive slots This bit is set to 1 when during data reception, the received data is being stored in the message slot. Note that the value read from message slot while TRSTAT bit remains set is indeterminate. (8) TRFIN (Transmit/Receive Finished) bit (D7) This bit indicates that the CAN module finished transmitting or receiving.
• When set for transmit slots This bit is set to 1 when the CAN module finished transmitting the data stored in the message slot. This bit is cleared by writing a 0 in software. However, it cannot be cleared when TRSTAT (Transmit/Receive Status) bit = 1.
• When set for receive slots This bit is set to 1 when the CAN module finished receiving normally the data to be stored in the message slot. This bit is cleared by writing a 0 in software. However, it cannot be cleared when TRSTAT (Transmit/Receive Status) bit = 1. Note 1:Before you can read received data from the message slot, you must clear the TRFIN (Transmit/Receive Finished) bit. Note also that if the TRFIN (Transmit/Receive Finished) bit is set to 1 after you read data, it means that new receive data was stored while you were reading and the data you read contains an indeterminate value. In this case, discard the read data, clear the TRFIN (Transmit/Receive Finished) bit, and read out data again. Note 2:The TRFIN (Transmit/Receive Finished) bit has no effect for remote frames, so that it is not set when remote frame transmission or reception is completed. CAN MODULE

13-38 32170/32174 Group User's Manual (Rev. 2.1)

13.2.11 CAN Message Slots

I CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) <Address:H'0080 1100> I CAN0 Message Slot 1 Standard ID0 (C0MSL1SID0) <Address:H'0080 1110> I CAN0 Message Slot 2 Standard ID0 (C0MSL2SID0) <Address:H'0080 1120> I CAN0 Message Slot 3 Standard ID0 (C0MSL3SID0) <Address:H'0080 1130> I CAN0 Message Slot 4 Standard ID0 (C0MSL4SID0) <Address:H'0080 1140> I CAN0 Message Slot 5 Standard ID0 (C0MSL5SID0) <Address:H'0080 1150> I CAN0 Message Slot 6 Standard ID0 (C0MSL6SID0) <Address:H'0080 1160> I CAN0 Message Slot 7 Standard ID0 (C0MSL7SID0) <Address:H'0080 1170> I CAN0 Message Slot 8 Standard ID0 (C0MSL8SID0) <Address:H'0080 1180> I CAN0 Message Slot 9 Standard ID0 (C0MSL9SID0) <Address:H'0080 1190> I CAN0 Message Slot 10 Standard ID0 (C0MSL10SID0) <Address:H'0080 11A0> I CAN0 Message Slot 11 Standard ID0 (C0MSL11SID0) <Address:H'0080 11B0> I CAN0 Message Slot 12 Standard ID0 (C0MSL12SID0) <Address:H'0080 11C0> I CAN0 Message Slot 13 Standard ID0 (C0MSL13SID0) <Address:H'0080 11D0> I CAN0 Message Slot 14 Standard ID0 (C0MSL14SID0) <Address:H'0080 11E0> I CAN0 Message Slot 15 Standard ID0 (C0MSL15SID0) <Address:H'0080 11F0> <When reset: Indeterminate> D Bit Name Function R W 0-2 No functions assigned. (Always set these bits to 0) 0 – 3-7 SID0-SID4 Standard ID0 to standard ID4 (Standard ID0 to standard ID4) These registers are the transmit frame/receive frame memory space. D 0 123456 D 7 SID0 SID1 SID2 SID3 SID4 CAN MODULE

13-39 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) <Address:H'0080 1101> I CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1) <Address:H'0080 1111> I CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1) <Address:H'0080 1121> I CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1) <Address:H'0080 1131> I CAN0 Message Slot 4 Standard ID1 (C0MSL4SID1) <Address:H'0080 1141> I CAN0 Message Slot 5 Standard ID1 (C0MSL5SID1) <Address:H'0080 1151> I CAN0 Message Slot 6 Standard ID1 (C0MSL6SID1) <Address:H'0080 1161> I CAN0 Message Slot 7 Standard ID1 (C0MSL7SID1) <Address:H'0080 1171> I CAN0 Message Slot 8 Standard ID1 (C0MSL8SID1) <Address:H'0080 1181> I CAN0 Message Slot 9 Standard ID1 (C0MSL9SID1) <Address:H'0080 1191> I CAN0 Message Slot 10 Standard ID1 (C0MSL10SID1) <Address:H'0080 11A1> I CAN0 Message Slot 11 Standard ID1 (C0MSL11SID1) <Address:H'0080 11B1> I CAN0 Message Slot 12 Standard ID1 (C0MSL12SID1) <Address:H'0080 11C1> I CAN0 Message Slot 13 Standard ID1 (C0MSL13SID1) <Address:H'0080 11D1> I CAN0 Message Slot 14 Standard ID1 (C0MSL14SID1) <Address:H'0080 11E1> I CAN0 Message Slot 15 Standard ID1 (C0MSL15SID1) <Address:H'0080 11F1> D 8 9 1 01 11 21 31 4 D 1 5 SID5 SID6 SID7 SID8 SID9 SID10 <When reset: Indeterminate> D Bit Name Function R W 8,9 No functions assigned. (Always set these bits to 0) 0 – 10-15 SID5-SID10 Standard ID5 to standard ID10 (Standard ID5 to standard ID10) These registers are the transmit frame/receive frame memory space. CAN MODULE

13-40 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) <Address:H'0080 1102> I CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0) <Address:H'0080 1112> I CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0) <Address:H'0080 1122> I CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0) <Address:H'0080 1132> I CAN0 Message Slot 4 Extended ID0 (C0MSL4EID0) <Address:H'0080 1142> I CAN0 Message Slot 5 Extended ID0 (C0MSL5EID0) <Address:H'0080 1152> I CAN0 Message Slot 6 Extended ID0 (C0MSL6EID0) <Address:H'0080 1162> I CAN0 Message Slot 7 Extended ID0 (C0MSL7EID0) <Address:H'0080 1172> I CAN0 Message Slot 8 Extended ID0 (C0MSL8EID0) <Address:H'0080 1182> I CAN0 Message Slot 9 Extended ID0 (C0MSL9EID0) <Address:H'0080 1192> I CAN0 Message Slot 10 Extended ID0 (C0MSL10EID0) <Address:H'0080 11A2> I CAN0 Message Slot 11 Extended ID0 (C0MSL11EID0) <Address:H'0080 11B2> I CAN0 Message Slot 12 Extended ID0 (C0MSL12EID0) <Address:H'0080 11C2> I CAN0 Message Slot 13 Extended ID0 (C0MSL13EID0) <Address:H'0080 11D2> I CAN0 Message Slot 14 Extended ID0 (C0MSL14EID0) <Address:H'0080 11E2> I CAN0 Message Slot 15 Extended ID0 (C0MSL15EID0) <Address:H'0080 11F2> These registers are the transmit frame/receive frame memory space. Note: When set for the receive slot standard ID format, values written to EID bits when storing received data in the slot are indeterminate. <When reset: Indeterminate> D Bit Name Function R W 0-3 No functions assigned. (Always set these bits to 0) 0 – 4-7 EID0-EID3 Extended ID0 to extended ID3 (Extended ID0 to extended ID3) D 0 123456 D 7 EID0 EID1 EID2 EID3 CAN MODULE

13-41 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) <Address:H'0080 1103> I CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1) <Address:H'0080 1113> I CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1) <Address:H'0080 1123> I CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1) <Address:H'0080 1133> I CAN0 Message Slot 4 Extended ID1 (C0MSL4EID1) <Address:H'0080 1143> I CAN0 Message Slot 5 Extended ID1 (C0MSL5EID1) <Address:H'0080 1153> I CAN0 Message Slot 6 Extended ID1 (C0MSL6EID1) <Address:H'0080 1163> I CAN0 Message Slot 7 Extended ID1 (C0MSL7EID1) <Address:H'0080 1173> I CAN0 Message Slot 8 Extended ID1 (C0MSL8EID1) <Address:H'0080 1183> I CAN0 Message Slot 9 Extended ID1 (C0MSL9EID1) <Address:H'0080 1193> I CAN0 Message Slot 10 Extended ID1 (C0MSL10EID1) <Address:H'0080 11A3> I CAN0 Message Slot 11 Extended ID1 (C0MSL11EID1) <Address:H'0080 11B3> I CAN0 Message Slot 12 Extended ID1 (C0MSL12EID1) <Address:H'0080 11C3> I CAN0 Message Slot 13 Extended ID1 (C0MSL13EID1) <Address:H'0080 11D3> I CAN0 Message Slot 14 Extended ID1 (C0MSL14EID1) <Address:H'0080 11E3> I CAN0 Message Slot 15 Extended ID1 (C0MSL15EID1) <Address:H'0080 11F3> These registers are the transmit frame/receive frame memory space. Note: When set for the receive slot standard ID format, values written to EID bits when storing received data in the slot are indeterminate. D 8 9 1 01 11 21 31 4 D 1 5 EID4 EID5 EID6 EID7 EID8 EID9 EID10 EID11 <When reset: Indeterminate> D Bit Name Function R W 8-15 EID4-EID11 Extended ID4 to extended ID11 (Extended ID4 to extended ID11) CAN MODULE

13-42 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) <Address:H'0080 1104> I CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2) <Address:H'0080 1114> I CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2) <Address:H'0080 1124> I CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2) <Address:H'0080 1134> I CAN0 Message Slot 4 Extended ID2 (C0MSL4EID2) <Address:H'0080 1144> I CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) <Address:H'0080 1154> I CAN0 Message Slot 6 Extended ID2 (C0MSL6EID2) <Address:H'0080 1164> I CAN0 Message Slot 7 Extended ID2 (C0MSL7EID2) <Address:H'0080 1174> I CAN0 Message Slot 8 Extended ID2 (C0MSL8EID2) <Address:H'0080 1184> I CAN0 Message Slot 9 Extended ID2 (C0MSL9EID2) <Address:H'0080 1194> I CAN0 Message Slot 10 Extended ID2 (C0MSL10EID2) <Address:H'0080 11A4> I CAN0 Message Slot 11 Extended ID2 (C0MSL11EID2) <Address:H'0080 11B4> I CAN0 Message Slot 12 Extended ID2 (C0MSL12EID2) <Address:H'0080 11C4> I CAN0 Message Slot 13 Extended ID2 (C0MSL13EID2) <Address:H'0080 11D4> I CAN0 Message Slot 14 Extended ID2 (C0MSL14EID2) <Address:H'0080 11E4> I CAN0 Message Slot 15 Extended ID2 (C0MSL15EID2) <Address:H'0080 11F4> These registers are the transmit frame/receive frame memory space. Note: When set for the receive slot standard ID format, values written to EID bits when storing received data in the slot are indeterminate. <When reset: Indeterminate> D Bit Name Function R W 0,1 No functions assigned. (Always set these bits to 0) 0 – 2-7 EID12-EID17 Extended ID12 to extended ID17 (Extended ID12 to extended ID17) D 0 123456 D 7 EID12 EID13 EID14 EID15 EID16 EID17 CAN MODULE

13-43 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Data Length Register (C0MSL0DLC)<Address:H'0080 1105> I CAN0 Message Slot 1 Data Length Register (C0MSL1DLC)<Address:H'0080 1115> I CAN0 Message Slot 2 Data Length Register (C0MSL2DLC)<Address:H'0080 1125> I CAN0 Message Slot 3 Data Length Register (C0MSL3DLC)<Address:H'0080 1135> I CAN0 Message Slot 4 Data Length Register (C0MSL4DLC)<Address:H'0080 1145> I CAN0 Message Slot 5 Data Length Register (C0MSL5DLC)<Address:H'0080 1155> I CAN0 Message Slot 6 Data Length Register (C0MSL6DLC)<Address:H'0080 1165> I CAN0 Message Slot 7 Data Length Register (C0MSL7DLC)<Address:H'0080 1175> I CAN0 Message Slot 8 Data Length Register (C0MSL8DLC)<Address:H'0080 1185> I CAN0 Message Slot 9 Data Length Register (C0MSL9DLC)<Address:H'0080 1195> I CAN0 Message Slot 10 Data Length Register (C0MSL10DLC)<Address:H'0080 11A5> I CAN0 Message Slot 11 Data Length Register (C0MSL11DLC)<Address:H'0080 11B5> I CAN0 Message Slot 12 Data Length Register (C0MSL12DLC)<Address:H'0080 11C5> I CAN0 Message Slot 13 Data Length Register (C0MSL13DLC)<Address:H'0080 11D5> I CAN0 Message Slot 14 Data Length Register (C0MSL14DLC)<Address:H'0080 11E5> I CAN0 Message Slot 15 Data Length Register (C0MSL15DLC)<Address:H'0080 11F5> D 8 9 1 01 11 21 31 4 D 1 5 DLC0 DLC1 DLC2 DLC3 <When reset: Indeterminate> D Bit Name Function R W 8-11 No functions assigned. (Always set these bits to 0) 0 – 12-15 DLC0-DLC3 0 0 0 0 : 0 byte (Sets data length) 0 0 0 1 : 1 byte 0 0 1 0 : 2 byte 0 0 1 1 : 3 byte 0 1 0 0 : 4 byte 0 1 0 1 : 5 byte 0 1 1 0 : 6 byte 0 1 1 1 : 7 byte

1 X X X : 8 byte

These registers are the transmit frame/receive frame memory space. When transmitting, the register sets the length of transmit data. When receiving, the register stores the received DLC. CAN MODULE

13-44 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Data 0 (C0MSL0DT0) <Address:H'0080 1106> I CAN0 Message Slot 1 Data 0 (C0MSL1DT0) <Address:H'0080 1116> I CAN0 Message Slot 2 Data 0 (C0MSL2DT0) <Address:H'0080 1126> I CAN0 Message Slot 3 Data 0 (C0MSL3DT0) <Address:H'0080 1136> I CAN0 Message Slot 4 Data 0 (C0MSL4DT0) <Address:H'0080 1146> I CAN0 Message Slot 5 Data 0 (C0MSL5DT0) <Address:H'0080 1156> I CAN0 Message Slot 6 Data 0 (C0MSL6DT0) <Address:H'0080 1166> I CAN0 Message Slot 7 Data 0 (C0MSL7DT0) <Address:H'0080 1176> I CAN0 Message Slot 8 Data 0 (C0MSL8DT0) <Address:H'0080 1186> I CAN0 Message Slot 9 Data 0 (C0MSL9DT0) <Address:H'0080 1196> I CAN0 Message Slot 10 Data 0 (C0MSL10DT0) <Address:H'0080 11A6> I CAN0 Message Slot 11 Data 0 (C0MSL11DT0) <Address:H'0080 11B6> I CAN0 Message Slot 12 Data 0 (C0MSL12DT0) <Address:H'0080 11C6> I CAN0 Message Slot 13 Data 0 (C0MSL13DT0) <Address:H'0080 11D6> I CAN0 Message Slot 14 Data 0 (C0MSL14DT0) <Address:H'0080 11E6> I CAN0 Message Slot 15 Data 0 (C0MSL15DT0) <Address:H'0080 11F6> These registers are the transmit frame/receive frame memory space. Note 1: If the data length (DLC value) of the data frame being stored by any receive slot is 0, an indeterminate value is written into the slot. Note 2: The first byte of a CAN frame’s data field corresponds to the data 0 of message slot n. The data is transmitted/received beginning with the register’s MSB side. <When reset: Indeterminate> D Bit Name Function R W 0-7 C0MSLnDT0 Message slot n data 0 D 0 123456 D 7 C0MSLnDT0 CAN MODULE

13-45 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Data 1 (C0MSL0DT1) <Address:H'0080 1107> I CAN0 Message Slot 1 Data 1 (C0MSL1DT1) <Address:H'0080 1117> I CAN0 Message Slot 2 Data 1 (C0MSL2DT1) <Address:H'0080 1127> I CAN0 Message Slot 3 Data 1 (C0MSL3DT1) <Address:H'0080 1137> I CAN0 Message Slot 4 Data 1 (C0MSL4DT1) <Address:H'0080 1147> I CAN0 Message Slot 5 Data 1 (C0MSL5DT1) <Address:H'0080 1157> I CAN0 Message Slot 6 Data 1 (C0MSL6DT1) <Address:H'0080 1167> I CAN0 Message Slot 7 Data 1 (C0MSL7DT1) <Address:H'0080 1177> I CAN0 Message Slot 8 Data 1 (C0MSL8DT1) <Address:H'0080 1187> I CAN0 Message Slot 9 Data 1 (C0MSL9DT1) <Address:H'0080 1197> I CAN0 Message Slot 10 Data 1 (C0MSL10DT1) <Address:H'0080 11A7> I CAN0 Message Slot 11 Data 1 (C0MSL11DT1) <Address:H'0080 11B7> I CAN0 Message Slot 12 Data 1 (C0MSL12DT1) <Address:H'0080 11C7> I CAN0 Message Slot 13 Data 1 (C0MSL13DT1) <Address:H'0080 11D7> I CAN0 Message Slot 14 Data 1 (C0MSL14DT1) <Address:H'0080 11E7> I CAN0 Message Slot 15 Data 1 (C0MSL15DT1) <Address:H'0080 11F7> These registers are the transmit frame/receive frame memory space. Note: For receive slots, if when storing a data frame the data length (DLC value) = 1, an indeterminate value is written to this register. <When reset: Indeterminate> D Bit Name Function R W 8-15 C0MSLnDT1 Message slot n data 1 D 8 9 1 01 11 21 31 4 D 1 5 C0MSLnDT1 CAN MODULE

13-46 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Data 2 (C0MSL0DT2) <Address:H'0080 1108> I CAN0 Message Slot 1 Data 2 (C0MSL1DT2) <Address:H'0080 1118> I CAN0 Message Slot 2 Data 2 (C0MSL2DT2) <Address:H'0080 1128> I CAN0 Message Slot 3 Data 2 (C0MSL3DT2) <Address:H'0080 1138> I CAN0 Message Slot 4 Data 2 (C0MSL4DT2) <Address:H'0080 1148> I CAN0 Message Slot 5 Data 2 (C0MSL5DT2) <Address:H'0080 1158> I CAN0 Message Slot 6 Data 2 (C0MSL6DT2) <Address:H'0080 1168> I CAN0 Message Slot 7 Data 2 (C0MSL7DT2) <Address:H'0080 1178> I CAN0 Message Slot 8 Data 2 (C0MSL8DT2) <Address:H'0080 1188> I CAN0 Message Slot 9 Data 2 (C0MSL9DT2) <Address:H'0080 1198> I CAN0 Message Slot 10 Data 2 (C0MSL10DT2) <Address:H'0080 11A8> I CAN0 Message Slot 11 Data 2 (C0MSL11DT2) <Address:H'0080 11B8> I CAN0 Message Slot 12 Data 2 (C0MSL12DT2) <Address:H'0080 11C8> I CAN0 Message Slot 13 Data 2 (C0MSL13DT2) <Address:H'0080 11D8> I CAN0 Message Slot 14 Data 2 (C0MSL14DT2) <Address:H'0080 11E8> I CAN0 Message Slot 15 Data 2 (C0MSL15DT2) <Address:H'0080 11F8> These registers are the transmit frame/receive frame memory space. Note: For receive slots, if when storing a data frame the data length (DLC value) = 2, an indeterminate value is written to this register. <When reset: Indeterminate> D Bit Name Function R W 0-7 C0MSLnDT2 Message slot n data 2 CAN MODULE

13-47 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Data 3 (C0MSL0DT3) <Address:H'0080 1109> I CAN0 Message Slot 1 Data 3 (C0MSL1DT3) <Address:H'0080 1119> I CAN0 Message Slot 2 Data 3 (C0MSL2DT3) <Address:H'0080 1129> I CAN0 Message Slot 3 Data 3 (C0MSL3DT3) <Address:H'0080 1139> I CAN0 Message Slot 4 Data 3 (C0MSL4DT3) <Address:H'0080 1149> I CAN0 Message Slot 5 Data 3 (C0MSL5DT3) <Address:H'0080 1159> I CAN0 Message Slot 6 Data 3 (C0MSL6DT3) <Address:H'0080 1169> I CAN0 Message Slot 7 Data 3 (C0MSL7DT3) <Address:H'0080 1179> I CAN0 Message Slot 8 Data 3 (C0MSL8DT3) <Address:H'0080 1189> I CAN0 Message Slot 9 Data 3 (C0MSL9DT3) <Address:H'0080 1199> I CAN0 Message Slot 10 Data 3 (C0MSL10DT3) <Address:H'0080 11A9> I CAN0 Message Slot 11 Data 3 (C0MSL11DT3) <Address:H'0080 11B9> I CAN0 Message Slot 12 Data 3 (C0MSL12DT3) <Address:H'0080 11C9> I CAN0 Message Slot 13 Data 3 (C0MSL13DT3) <Address:H'0080 11D9> I CAN0 Message Slot 14 Data 3 (C0MSL14DT3) <Address:H'0080 11E9> I CAN0 Message Slot 15 Data 3 (C0MSL15DT3) <Address:H'0080 11F9> These registers are the transmit frame/receive frame memory space. Note: For receive slots, if when storing a data frame the data length (DLC value) = 3, an indeterminate value is written to this register. <When reset: Indeterminate> D Bit Name Function R W 8-15 COMSLnDT3 Message slot n data 3 D 8 9 1 01 11 21 31 4 D 1 5 C0MSLnDT3 CAN MODULE

13-48 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Data 4 (C0MSL0DT4) <Address:H'0080 110A> I CAN0 Message Slot 1 Data 4 (C0MSL1DT4) <Address:H'0080 111A> I CAN0 Message Slot 2 Data 4 (C0MSL2DT4) <Address:H'0080 112A> I CAN0 Message Slot 3 Data 4 (C0MSL3DT4) <Address:H'0080 113A> I CAN0 Message Slot 4 Data 4 (C0MSL4DT4) <Address:H'0080 114A> I CAN0 Message Slot 5 Data 4 (C0MSL5DT4) <Address:H'0080 115A> I CAN0 Message Slot 6 Data 4 (C0MSL6DT4) <Address:H'0080 116A> I CAN0 Message Slot 7 Data 4 (C0MSL7DT4) <Address:H'0080 117A> I CAN0 Message Slot 8 Data 4 (C0MSL8DT4) <Address:H'0080 118A> I CAN0 Message Slot 9 Data 4 (C0MSL9DT4) <Address:H'0080 119A> I CAN0 Message Slot 10 Data 4 (C0MSL10DT4) <Address:H'0080 11AA> I CAN0 Message Slot 11 Data 4 (C0MSL11DT4) <Address:H'0080 11BA> I CAN0 Message Slot 12 Data 4 (C0MSL12DT4) <Address:H'0080 11CA> I CAN0 Message Slot 13 Data 4 (C0MSL13DT4) <Address:H'0080 11DA> I CAN0 Message Slot 14 Data 4 (C0MSL14DT4) <Address:H'0080 11EA> I CAN0 Message Slot 15 Data 4 (C0MSL15DT4) <Address:H'0080 11FA> These registers are the transmit frame/receive frame memory space. Note: For receive slots, if when storing a data frame the data length (DLC value) = 4, an indeterminate value is written to this register. <When reset: Indeterminate> D Bit Name Function R W 0-7 C0MSLnDT4 Message slot n data 4 CAN MODULE

13-49 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Data 5 (C0MSL0DT5) <Address:H'0080 110B> I CAN0 Message Slot 1 Data 5 (C0MSL1DT5) <Address:H'0080 111B> I CAN0 Message Slot 2 Data 5 (C0MSL2DT5) <Address:H'0080 112B> I CAN0 Message Slot 3 Data 5 (C0MSL3DT5) <Address:H'0080 113B> I CAN0 Message Slot 4 Data 5 (C0MSL4DT5) <Address:H'0080 114B> I CAN0 Message Slot 5 Data 5 (C0MSL5DT5) <Address:H'0080 115B> I CAN0 Message Slot 6 Data 5 (C0MSL6DT5) <Address:H'0080 116B> I CAN0 Message Slot 7 Data 5 (C0MSL7DT5) <Address:H'0080 117B> I CAN0 Message Slot 8 Data 5 (C0MSL8DT5) <Address:H'0080 118B> I CAN0 Message Slot 9 Data 5 (C0MSL9DT5) <Address:H'0080 119B> I CAN0 Message Slot 10 Data 5 (C0MSL10DT5) <Address:H'0080 11AB> I CAN0 Message Slot 11 Data 5 (C0MSL11DT5) <Address:H'0080 11BB> I CAN0 Message Slot 12 Data 5 (C0MSL12DT5) <Address:H'0080 11CB> I CAN0 Message Slot 13 Data 5 (C0MSL13DT5) <Address:H'0080 11DB> I CAN0 Message Slot 14 Data 5 (C0MSL14DT5) <Address:H'0080 11EB> I CAN0 Message Slot 15 Data 5 (C0MSL15DT5) <Address:H'0080 11FB> These registers are the transmit frame/receive frame memory space. Note: For receive slots, if when storing a data frame the data length (DLC value) = 5, an indeterminate value is written to this register. <When reset: Indeterminate> D Bit Name Function R W 8-15 C0MSLnDT5 Message slot n data 5 D 8 9 1 01 11 21 31 4 D 1 5 C0MSLnDT5 CAN MODULE

13-50 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Data 6 (C0MSL0DT6) <Address:H'0080 110C> I CAN0 Message Slot 1 Data 6 (C0MSL1DT6) <Address:H'0080 111C> I CAN0 Message Slot 2 Data 6 (C0MSL2DT6) <Address:H'0080 112C> I CAN0 Message Slot 3 Data 6 (C0MSL3DT6) <Address:H'0080 113C> I CAN0 Message Slot 4 Data 6 (C0MSL4DT6) <Address:H'0080 114C> I CAN0 Message Slot 5 Data 6 (C0MSL5DT6) <Address:H'0080 115C> I CAN0 Message Slot 6 Data 6 (C0MSL6DT6) <Address:H'0080 116C> I CAN0 Message Slot 7 Data 6 (C0MSL7DT6) <Address:H'0080 117C> I CAN0 Message Slot 8 Data 6 (C0MSL8DT6) <Address:H'0080 118C> I CAN0 Message Slot 9 Data 6 (C0MSL9DT6) <Address:H'0080 119C> I CAN0 Message Slot 10 Data 6 (C0MSL10DT6) <Address:H'0080 11AC> I CAN0 Message Slot 11 Data 6 (C0MSL11DT6) <Address:H'0080 11BC> I CAN0 Message Slot 12 Data 6 (C0MSL12DT6) <Address:H'0080 11CC> I CAN0 Message Slot 13 Data 6 (C0MSL13DT6) <Address:H'0080 11DC> I CAN0 Message Slot 14 Data 6 (C0MSL14DT6) <Address:H'0080 11EC> I CAN0 Message Slot 15 Data 6 (C0MSL15DT6) <Address:H'0080 11FC> These registers are the transmit frame/receive frame memory space. Note: For receive slots, if when storing a data frame the data length (DLC value) = 6, an indeterminate value is written to this register. <When reset: Indeterminate> D Bit Name Function R W 0-7 C0MSLnDT6 Message slot n data 6 D 0 123456 D 7 C0MSLnDT6 CAN MODULE

13-51 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Data 7 (C0MSL0DT7) <Address:H'0080 110D> I CAN0 Message Slot 1 Data 7 (C0MSL1DT7) <Address:H'0080 111D> I CAN0 Message Slot 2 Data 7 (C0MSL2DT7) <Address:H'0080 112D> I CAN0 Message Slot 3 Data 7 (C0MSL3DT7) <Address:H'0080 113D> I CAN0 Message Slot 4 Data 7 (C0MSL4DT7) <Address:H'0080 114D> I CAN0 Message Slot 5 Data 7 (C0MSL5DT7) <Address:H'0080 115D> I CAN0 Message Slot 6 Data 7 (C0MSL6DT7) <Address:H'0080 116D> I CAN0 Message Slot 7 Data 7 (C0MSL7DT7) <Address:H'0080 117D> I CAN0 Message Slot 8 Data 7 (C0MSL8DT7) <Address:H'0080 118D> I CAN0 Message Slot 9 Data 7 (C0MSL9DT7) <Address:H'0080 119D> I CAN0 Message Slot 10 Data 7 (C0MSL10DT7) <Address:H'0080 11AD> I CAN0 Message Slot 11 Data 7 (C0MSL11DT7) <Address:H'0080 11BD> I CAN0 Message Slot 12 Data 7 (C0MSL12DT7) <Address:H'0080 11CD> I CAN0 Message Slot 13 Data 7 (C0MSL13DT7) <Address:H'0080 11DD> I CAN0 Message Slot 14 Data 7 (C0MSL14DT7) <Address:H'0080 11ED> I CAN0 Message Slot 15 Data 7 (C0MSL15DT7) <Address:H'0080 11FD> These registers are the transmit frame/receive frame memory space. Note: For receive slots, if when storing a data frame the data length (DLC value) = 7, an indeterminate value is written to this register. <When reset: Indeterminate> D Bit Name Function R W 0-7 C0MSLnDT7 Message slot n data 7 D 8 9 1 01 11 21 31 4 D 1 5 C0MSLnDT7 CAN MODULE

13-52 32170/32174 Group User's Manual (Rev. 2.1) I CAN0 Message Slot 0 Time Stamp (C0MSL0TSP) <Address:H'0080 110E> I CAN0 Message Slot 1 Time Stamp (C0MSL1TSP) <Address:H'0080 111E> I CAN0 Message Slot 2 Time Stamp (C0MSL2TSP) <Address:H'0080 112E> I CAN0 Message Slot 3 Time Stamp (C0MSL3TSP) <Address:H'0080 113E> I CAN0 Message Slot 4 Time Stamp (C0MSL4TSP) <Address:H'0080 114E> I CAN0 Message Slot 5 Time Stamp (C0MSL5TSP) <Address:H'0080 115E> I CAN0 Message Slot 6 Time Stamp (C0MSL6TSP) <Address:H'0080 116E> I CAN0 Message Slot 7 Time Stamp (C0MSL7TSP) <Address:H'0080 117E> I CAN0 Message Slot 8 Time Stamp (C0MSL8TSP) <Address:H'0080 118E> I CAN0 Message Slot 9 Time Stamp (C0MSL9TSP) <Address:H'0080 119E> I CAN0 Message Slot 10 Time Stamp (C0MSL10TSP) <Address:H'0080 11AE> I CAN0 Message Slot 11 Time Stamp (C0MSL11TSP) <Address:H'0080 11BE> I CAN0 Message Slot 12 Time Stamp (C0MSL12TSP) <Address:H'0080 11CE> I CAN0 Message Slot 13 Time Stamp (C0MSL13TSP) <Address:H'0080 11DE> I CAN0 Message Slot 14 Time Stamp (C0MSL14TSP) <Address:H'0080 11EE> I CAN0 Message Slot 15 Time Stamp (C0MSL15TSP) <Address:H'0080 11FE> These registers are the transmit frame/receive frame memory space. When the CAN module finishes transmitting or receiving, the CAN0 Time Stamp Count Register value is set in this register. <When reset: Indeterminate> D Bit Name Function R W 0-15 C0MSLnTSP Message slot n time stamp D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 C0MSLnTSP CAN MODULE

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13.3.1 CAN Protocol Frame

There are four types of frames which are handled by CAN protocol: (1) Data frame (2) Remote frame (3) Error frame (4) Overload frame Frames are separated from each another by an interframe space. SOF Arbitration field Control field Data field CRC field ACK field EOF 11 1 6 0-64 16 2 7 11 11 1 18 6 0-64 16 2 7 SOF EOF 11 1 6 16 2 7 11 11 1 18 6 16 27 Data frame Remote frame Standard format Extended format Numbers in each field denote the number of bits. Standard format Extended format Arbitration field Control field CRC field ACK field Figure 13.3.1 CAN Protocol Frames (1) CAN MODULE

13-54 32170/32174 Group User's Manual (Rev. 2.1) Error flag Error delimiter Interframe space or overload flag 6-12 8 Overload flag Overload delimiter 6-12 8 Error frame Overload frame Interframe space Intermission Bus idle SOF of next frame In an error-active state 3 0- SOF Suspend transmission In an error-passive state 3 8 0- SOF Numbers in each field denote the number of bits. Interframe space or overload flag Intermission Bus idle SOF of next frame Figure 13.3.2 CAN Protocol Frames (2) CAN MODULE

13-55 32170/32174 Group User's Manual (Rev. 2.1) CAN MODULE Transmit error counter > 255 Transmit error counter ≥ 128 or Receive error counter ≥ 128 Transmit error counter < 128 and Receive error counter < 128 11 consecutive recessive bits detected on CAN bus 128 times or reset by software Error-active state Error-passive state Bus-off state Initial settings Figure 13.3.3 CAN Control Error States The CAN controller assumes one of the following three error states depending on the transmit error and receive error counter values. (1) Error-active state

• This is a state where almost no errors have occurred.
• When an error is detected, an active error flag is transmitted.
• Immediately after being initialized, the CAN controller is in this state. (2) Error-passive state
• This is a state where many errors have occurred.
• When an error is detected, a passive error flag is transmitted. (3) Bus-off state
• This is a state where a large number of errors have occurred.
• CAN communication with other nodes cannot be performed until the CAN module returns to an error-active state. Error status of the unit Error-active state Error-passive state Bus-off state Transmit error counter Receive error counter 0-127 and 0-127 128-255 or 128- 256-

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13.4.1 Initialization of the CAN Module

Before you perform communication, set up the CAN module as described below. (1) Selecting pin functions The CAN transmit data output pin (CTX) and CAN data receive input pin (CRX) are shared with input/output ports, so be sure to select the functions of these pins. (Refer to Chapter 8, "Input/ Output Ports and Pin Functions." (2) Setting the interrupt controller (ICU) When you use CAN module interrupts, set the interrupt priority. (3) Setting CAN Error Interrupt Mask and CAN Slot Interrupt Mask Registers When you use CAN bus error interrupts, CAN error passive interrupts, CAN error bus-off interrupts, or CAN slot interrupts, set each corresponding bit to 1 to enable interrupt requests. (4) Setting bit timing and the number of times sampled Using the CAN Configuration Register and CAN Baud Rate Prescaler, set the bit timing and the number of times the CAN bus is sampled. (a) Setting the bit timing Determine the period Tq that is the base of bit timing, the configuration of Propagation Segment, Phase Segment1, and Phase Segment2, and reSynchronization Jump Width. The equation to calculate Tq is shown below. Tq = (CANBRP+1) /CPU clock The baud rate is determined by the number of Tq's that comprise one bit. The equation to calculate the baud rate is shown below. Number of Tq's for 1 bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 Baud rate (bps) = Tq period × number of Tq's for 1 bit CAN MODULE

13-57 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.4.1 Example of Bit Timing (b) Setting the number of times sampled Select the number of times the CAN bus is sampled from "one time" and "three times."

• When you select one-time sampling, the value sampled at the end of Phase Segment1 is assumed to be the value of the bit.
• When you select three-time sampling, the value of the bit is determined by majority from values sampled at three points, i.e., the value sampled at the first point and those sampled one Tq before and two Tq's before that. (5) Setting ID Mask Registers Set the values of ID Mask Registers (Global Mask Register, Local Mask Register A, and Local Mask Register B) which are used in acceptance filtering of received messages. (6) Settings when running in BasicCAN mode
• Set the CAN Extended ID Register IDE14 and IDE15 bits. (We recommend setting the same value in these bits.)
• Set IDs for message slots 14 and 15.
• Set the Message Control Registers 14 and 15 for data frame reception (H'40). (7) Setting CAN module operation mode Using the CAN Control Register (CAN0CNT), select the CAN module's operation mode (BasicCAN or loopback mode) and the clock source for the time stamp counter. (8) Releasing the CAN module from reset After you finished settings (1) through (7) above, clear the CAN Control Register (CAN0CNT)'s forcible reset bit (FRST) and reset bit (RST) to 0. Then, after detecting 11 consecutive "recessive" bits on the CAN bus, the CAN module becomes ready to communicate.
• Shown in this diagram is the bit timing for cases where one bit consists of 8 Tq's.
• When one-time sampling is selected, the value sampled at Sampling Point (1) is assumed to be the value of the bit.
• When three-time sampling is selected, the value of the bit is determined by majority from CAN bus values sampled at Sampling Points (1), (2), and (3). CAN MODULE

Segment Propagation Segment Phase Segment1 Phase Segment2 (1)(2)(3) Sampling Point 1Tq

1 Bit Rate

13-58 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.4.2 Initializing the CAN Module CAN MODULE Set the number of times sampled Set bit timing (baud rate) Set ID mask bit Set BasicCAN mode Release CAN module from reset Enable/disable interrupt to be generated at completion of transmission or reception in the slot Set CAN Error Interrupt Mask Register Set CAN Slot Interrupt Mask Register Set CAN Extended IDRegister Set IDs for message slots 14 and 15 Set Message Slot Control Register Set loopback mode

13-59 32170/32174 Group User's Manual (Rev. 2.1) CAN MODULE

13.4.2 CAN Timing

In the M32R/ECU CAN, CRX asynchronous input signals are sampled with Tq clock cycles (= base clock). The sampled signal is assumed to be the CAN bus value, with which CAN operation is controlled. Operation timing is shown below. 1Tq Drift of up to 1 Tq Internal Tq signal CRX pin Internal CRX signal Figure 13.4.3 Operation Timing

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13.5.1 Data Frame Transmit Procedure

The following describes the procedure for transmitting data frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to transmit by writing H'00 to the register. (2) Confirming that transmission is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT (Transmit/Receive Status) bit to see that transmission has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot, so you need to wait until the bit is cleared. (3) Setting transmit data Set the transmit ID and transmit data in the message slot. (4) Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to transmit the data as a standard frame or 1 when you want to transmit the data as an extended frame. (5) Setting the CAN Message Slot Control Register Write H'80 (note) to the CAN Message Slot Control Register to set the TR (Transmit Request) bit to 1. Note: When you are transmitting a data frame, always write H'80 to this register. CAN MODULE

13-61 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.5.1 Data Frame Transmit Procedure CAN MODULE Data frame transmit procedure Initialize CAN Message Slot Control Register Set ID and data in message slot Set Extended ID Register Set CAN Message Slot Control Register Settings completed Write H’00 Standard ID or extended ID Write H’80 (transmit request) Read CAN Message Slot Control Register TRSTAT bit = 0 YES NO Verify that transmission is idle

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13.5.2 Data Frame Transmit Operation

The following describes data frame transmit operation. The operations described below are automatically performed in hardware. (1) Selecting a transmit frame The CAN module checks slots which have transmit requests (including remote frame transmit slots) every intermission to determine the frame to transmit. If there are multiple transmit slots, frames are transmitted in order of slot numbers beginning with the smallest. (2) Transmitting a data frame After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 1, thereby starting transmission. (3) If the CAN module lost bus arbitration or a CAN bus error occurs If the CAN module lost bus arbitration or a CAN bus error occurs while transmitting, the CAN module clears the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 0. If the CAN module requested a transmit abort, the transmit abort is accepted and writing to the message slot is enabled. (4) Completion of data frame transmission When data frame transmission is completed, the CAN Message Slot Control Register's TRFIN (Transmit/Receive Finished) bit and the CAN Slot Interrupt Status Register are set to 1. Also, a time stamp count value at the time transmission was completed is written to the CAN Message Slot Time Stamp (C0MSLnTSP), and the transmit operation is thereby completed. If the CAN slot interrupt has been enabled, an interrupt request is generated at completion of transmit operation. The slot which has had transmission completed goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software. CAN MODULE

13-63 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.5.2 Operation of the CAN Message Slot Control Register when Transmitting Data Frames

13.5.3 Transmit Abort Function

The transmit abort function is used to cancel a transmit request that has once been set. This is accomplished by writing H'0F to the CAN Message Slot Control Register for the slot concerned. When transmit abort is accepted, the CAN module clears the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 0, allowing for data to be written to the message slot. The following shows conditions under which transmit abort is accepted: [Conditions]

• When the target message is waiting for transmission
• When a CAN bus error occurs during transmission
• When the CAN module lost bus arbitration CAN MODULE

B’1000 0010 B’0000 0001 (Note) B’1000 0001 B’0000 0000 (Note) B’1000 0000 Write H’80 Transmit aborted Transmit request accepted Note: When in this state, data can be written to the message slot . Transmit aborted Lost bus arbitration CAN bus error occurre d Transmit request accepted Transmit aborted Transmit completed Transmit aborted Transmit complete d Waiting for transmission B’0000 0010 Lost bus arbitration CAN bus error occurred

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13.6.1 Data Frame Receive Procedure

The following describes the procedure for receiving data frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to receive by writing H'00 to the register. (2) Confirming that reception is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT (Transmit/Receive Status) bit to see that reception has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot, so you need to wait until the bit is cleared. (3) Setting the receive ID Set the ID you want to receive in the message slot. (4) Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to receive a standard frame or 1 when you want to receive an extended frame. (5) Setting the CAN Message Slot Control Register Write H'40 to the CAN Message Slot Control Register to set the RR (Receive Request) bit to 1. CAN MODULE

13-65 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.6.1 Data Frame Receive Procedure CAN MODULE Data frame receive procedure Initialize CAN Message Slot Control Register Set ID in message slot Set Extended ID Register Set CAN Message Slot Control Register Settings completed Read CAN Message Slot Control Register TRSTAT bit = 0 Write H’00 Standard ID or extended ID Write H’40 (receive request) Verify that reception is idle

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13.6.2 Data Frame Receive Operation

The following describes data frame receive operation. The operations described below are automatically performed in hardware. (1) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies conditions for receiving the received message sequentially from slot 0 (up to slot 15). The following shows receive conditions for slots that have been set for data frame reception. [Conditions]

• The receive frame is a data frame.
• The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to 0 are "Don't care bits."
• The standard and extended frame types are the same. Note: In BasicCAN mode, slots 14 and 15 while being set for data frame reception can also receive remote frames. (2) When receive conditions are met When receive conditions in (1) above are met, the CAN module sets the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) and TRFIN (Transmit/Receive Finished) bits to 1 while at the same time writing the received data to the message slot. If the TRFIN (Transmit/Receive Finished) bit is already 1, the CAN module also sets the ML (Message Lost) bit to 1, indicating that the message slot has been overwritten. The message slot has its ID field and DLC field both overwritten and an indeterminate value written in its unused area (e.g., extended ID field for standard frame reception and an unused data field). Furthermore, a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp (C0MSLnTSP) along with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot Interrupt Status bit to 1. If the interrupt for the slot has been enabled, an interrupt request is generated, and the slot goes to a wait state for the next reception. (3) When receive conditions are not met The received frame is discarded, and the CAN module goes to the next transmit/receive operation without writing to the message slot. CAN MODULE

13-67 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.6.2 Operation of the CAN Message Slot Control Register when Receiving Data Frames CAN MODULE B’0100 0011 B’0000 0001 B’0100 0001 B’0000 0000 B’0100 0000 Clear receive requestReceive request set Store received data Clear receive request Store received data Clear receive reques t Finished storing received data Finished storing received dat a Clear receive reques t B’0000 0011 B’0100 0111 Store received data B’0100 0101 Finished storing received data Clear receive request B’0000 0111 Store received data Clear receive reques t Clear receive request B’0000 0101 Finished storing received data Clear receive reques t Clear receive request Store received data Wait for receive data Wait for receive data Finished storing received data Finished storing received data CPU read CPU read

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13.6.3 Reading Out Received Data Frames

The following describes the procedure for reading out received data frames from the slot. (1) Clearing the TRFIN (Transmit/Receive Finished) bit Write H'4E, H'40 or H'00 to the CAN Message Control Register (C0MSLnCNT) to clear the TRFIN bit to 0. After this write, the slot operates as follows: Value written to Slot operation after write C0MSLnCNT H'4E Operates as a data frame receive slot. Overwrite can be verified by ML bit. H'40 Operates as a data frame receive slot. Overwrite cannot be verified by ML bit. H'00 The slot stops transmit/receive operation. Note 1:If message-lost check by the ML bit is needed, write H'4E to the C0MSLnCNT register as you clear the TRFIN bit. Note 2:If you clear the TRFIN bit by writing H'4E, H'40 or H'00, it is possible that new data will be stored in the slot while still reading a message from the slot. (2) Reading out from the message slot Read out a message from the message slot. (3) Checking the TRFIN (Transmit/Receive Finished) bit Read the CAN Message Control Register to check the TRFIN (Transmit/Receive Finished) bit. (a) When TRFIN (Transmit/Receive Finished) bit = 1 It means that new data was stored in the slot while still reading out from the slot in (2). In this case, the data read out in (2) may contain an indeterminate value. Therefore, reexecute beginning with clearing of the TRFIN (Transmit/Receive Finished) bit in (1). (b) When TRFIN (Transmit/Receive Finished) bit = 0 It means that the CAN module finished reading out from the slot normally. CAN MODULE

13-69 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.6.3 Procedure for Reading Out Received Data CAN MODULE Read out from message slot Finished reading out received data Read CAN Message Slot Control Register TRFIN bit = 0 YES NO

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13.7.1 Remote Frame Transmit Procedure

The following describes the procedure for transmitting remote frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to transmit by writing H'00 to the register. (2) Confirming that transmission is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT (Transmit/Receive Status) bit to see that transmission has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot, so you need to wait until the bit is cleared. (3) Setting transmit ID Set the ID to be transmitted in the message slot. (4) Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to transmit the frame as a standard frame or 1 when you want to transmit the frame as an extended frame. (5) Setting the CAN Message Slot Control Register Write H'A0 to the CAN Message Slot Control Register to set the TR (Transmit Request) and RM (Remote) bits to 1. CAN MODULE

13-71 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.7.1 Remote Frame Transmit Procedure CAN MODULE Remote frame transmit procedure Initialize CAN Message Slot Control Register Set ID in message slot Set Extended ID Register Set CAN Message Slot Control Register Settings completed Write H’00 Standard ID or extended ID Write H’A0 (transmit request, remote) Read CAN Message Slot Control Register TRSTAT bit = 0 YES NO Verify that transmission is idle

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13.7.2 Remote Frame Transmit Operation

The following describes remote frame transmit operation. The operations described below are automatically performed in hardware. (1) Setting the RA (Remote Active) bit At the same time H'A0 (Transmit Request, Remote) is written to the CAN Message Slot Control Register, the RA (Remote Active) bit is set to 1, indicating that the corresponding slot is to handle remote frames. (2) Selecting a transmit frame The CAN module checks slots which have transmit requests (including data frame transmit slots) every intermission to determine the frame to transmit. If there are multiple transmit slots, frames are transmitted in order of slot numbers beginning with the smallest. (3) Transmitting a remote frame After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 1, thereby starting transmission. (4) If the CAN module lost bus arbitration or a CAN bus error occurs If the CAN module lost bus arbitration or a CAN bus error occurs while transmitting, the CAN module clears the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 0. If the CAN module requested a transmit abort, the transmit abort is accepted and writing to the message slot is enabled. (5) Completion of remote frame transmission When remote frame transmission is completed, a time stamp count value at the time transmission was completed is written to the CAN Message Slot Time Stamp (C0MSLnTSP) and the CAN Message Slot Control Register's RA (Remote Active) bit is cleared to 0. Also, the CAN Slot Interrupt Status bit is set to 1 by completion of transmission, but the CAN Message Slot Control Register's TRFIN (Transmit/Receive Finished) bit is not set to 1. If the CAN slot interrupt has been enabled, an interrupt request is generated upon completion of transmission. (6) Receiving a data frame When remote frame transmission is completed, the slot automatically starts functioning as a data frame receive slot. (7) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies conditions for receiving the received message sequentially from slot 0 (up to slot 15). CAN MODULE

13-73 32170/32174 Group User's Manual (Rev. 2.1) The following shows receive conditions for slots that have been set for data frame reception. [Conditions]

• The receive frame is a data frame.
• The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to 0 are "Don't care bit."
• The standard and extended frame types are the same. Note: In BasicCAN mode, slots 14 and 15 cannot be used as transmit slots. (8) When receive conditions are met When receive conditions in (7) above are met, the CAN module sets the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) and TRFIN (Transmit/Receive Finished) bits to 1 while at the same time writing the received data to the message slot. If the TRFIN (Transmit/Receive Finished) bit is already 1, the CAN module also sets the ML (Message Lost) bit to 1, indicating that the message slot has been overwritten. The message slot has its ID field and DLC field both overwritten and an indeterminate value written in its unused area (e.g., extended ID field for standard frame reception and an unused data field). Furthermore, a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp (C0MSLnTSP) along with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot Interrupt Status bit to 1. If the interrupt for the slot has been enabled, an interrupt request is generated, and the slot goes to a wait state for the next reception. Note: If the CAN module received a data frame before transmitting a remote frame, it stores the data frame in the slot and does not transmit the data frame. (9) When receive conditions are not met The received frame is discarded, and the CAN module goes to the next transmit/receive operation without writing to the message slot. CAN MODULE

13-74 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.7.2 Operation of the CAN Message Slot Control Register when Transmitting Remote Frames CAN MODULE B’0000 0000 B’0000 0000 Store received data B’0000 1010 B’1010 0011 Store received data Clear transmit request B’0000 0011 B’0000 0001 Finished storing received data Finished transmitting remote frame CPU read B’1010 0101 B’1010 1000 B’1010 1010 Finished storing received dat a Clear receive reques t Store received data Clear receive request Finished storing received data B’1010 0001 B’1010 0111B’0000 0111 B’0000 0101 Finished storing received data Clear receive reques t Store received data Clear receive requestFinished storing received data Finished transmitting remote frame B’1010 0000 Wait for receive data B’1010 1011 B’0000 1011 B’0000 0001 Finished storing received data B’0000 1000 CAN bus error occurs Lost bus arbitratio n CAN bus error occurs Clear transmi t request Store received data Store received data Wait for receive data Clear transmit request Finished storing received data

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13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission

The following describes the procedure for reading out received data frames from the slot when it is set for remote frame transmission. (1) Clearing the TRFIN (Transmit/Receive Finished) bit Write H'AE or H'00 to the CAN Message Control Register (C0MSLnCNT) to clear the TRFIN bit to 0. After this write, the slot operates as follows: Value written to Slot operation after write C0MSLnCNT H'AE Operates as a data frame receive slot. Overwrite can be verified by ML bit. H'00 The slot stops transmit/receive operation. Note 1: If message-lost check by the ML bit is needed, write H'AE to the C0MSLnCNT register as you clear the TRFIN bit. Note 2: If you clear the TRFIN bit by writing H'AE or H'00, it is possible that new data will be stored in the slot while still reading a message from the slot. Note 3: The received data frame cannot be read out by writing H'A0 to the register. If you clear the TRFIN bit by writing H'A0, the slot performs remote frame transmit operation. (2) Reading out from the message slot Read out a message from the message slot. (3) Checking the TRFIN (Transmit/Receive Finished) bit Read the CAN Message Control Register to check the TRFIN (Transmit/Receive Finished) bit. (a) When TRFIN (Transmit/Receive Finished) bit = 1 It means that new data was stored in the slot while still reading out from the slot in (2). In this case, the data read out in (2) may contain an indeterminate value. Therefore, reexecute beginning with clearing of the TRFIN (Transmit/Receive Finished) bit in (1). (b) When TRFIN (Transmit/Receive Finished) bit = 0 It means that the CAN module finished reading out from the slot normally. CAN MODULE

13-76 32170/32174 Group User's Manual (Rev. 2.1) Figure 13.7.3Procedure for Reading Out Received Data when Set for Remote Frame Transmission CAN MODULE Read out from message slot Finished reading out received data Read CAN Message Slot Control Register TRFIN bit = 0 YES NO

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13.8.1 Remote Frame Receive Procedure

The following describes the procedure for receiving remote frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to receive by writing H'00 to the register. (2) Confirming that reception is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT (Transmit/Receive Status) bit to see that reception has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot, so you need to wait until the bit is cleared. (3) Setting the receive ID Set the ID you want to receive in the message slot. (4) Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to receive a standard frame or 1 when you want to receive an extended frame. (5) Setting the CAN Message Slot Control Register (a) When automatic response (data frame transmission) for remote frame reception is desired Write H'60 to the CAN Message Slot Control Register to set the RR (Receive Request) and RM (Remote) bits to 1. (b) When automatic response (data frame transmission) for remote frame reception is not needed Write H'70 to the CAN Message Slot Control Register to set the RR (Receive Request), RM (Remote), and RL (Automatic Response Enable) bits to 1. Note: In BasicCAN mode, slots 14 and 15, although capable of receiving remote frames, cannot automatically respond to remote frame reception. CAN MODULE

13-78 32170/32174 Group User's Manual (Rev. 2.1) CAN MODULE Figure 13.8.1 Remote Frame Receive Procedure Remote frame reception procedure Initialize CAN Message Slot Control Register Set ID in message slot Set Extended ID Register Set CAN Message Slot Control Register Settings completed Write H’00 Standard ID or extended ID Write H’60 (receive request, remote, automatic response enable) Write H’70 (receive request, remote, automatic response disable) Read CAN Message Slot Control Register TRSTAT bit = 0 YES NO Verify that reception is idle

13-79 32170/32174 Group User's Manual (Rev. 2.1) CAN MODULE

13.8.2 Remote Frame Receive Operation

The following describes remote frame receive operation. The operations described below are automatically performed in hardware. (1) Setting the RA (Remote Active) bit When H'60 (Transmit Request, Remote) or H'70 (Transmit Request, Remote, Automatic Response Disable) is written to the CAN Message Slot Control Register, the RA (Remote Active) bit is set to 1, indicating that the corresponding slot is to handle remote frames. (2) Acceptance filtering When the CAN module finished receiving data, it starts searching for the slot that satisfies conditions for receiving the received message sequentially from slot 0 (up to slot 15). The following shows receive conditions for slots that have been set for data frame reception. [Conditions]

• The receive frame is a remote frame.
• The receive ID and the slot ID are identical, assuming the ID Mask Register bits set to 0 are "Don't care bit."
• The standard and extended frame types are the same. (3) When receive conditions are met When receive conditions in (2) above are met, the CAN module sets the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) and TRFIN (Transmit/Receive Finished) bits to 1 while at the same time writing the received data to the message slot. Furthermore, a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp (C0MSLnTSP) along with the received data. When the CAN module finished writing to the message slot, it sets the CAN Slot Interrupt Status bit to 1. If the interrupt for the slot has been enabled, an interrupt request is generated. Note 1:The ID field and DLC value are written to the message slot. Note 2:When receiving standard format frames, an indeterminate value is written to the extended ID area. Note 3:The data field is not accessed for write. Note 4:The RA and TRFIN bits are cleared to 0 after writing the remote frame received data. (4) When receive conditions are not met The received frame is discarded, and the CAN module waits for the next receive frame. No data is written to the message slot.

13-80 32170/32174 Group User's Manual (Rev. 2.1) CAN MODULE (5) Operation after receiving a remote frame The operation performed after receiving a remote frame differs depending on how automatic response is set. (a) When automatic response is disabled The slot which finished receiving goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software. (b) When automatic response is enabled After receiving a remote frame, the slot automatically changes to a data frame transmit slot and performs the transmit operation described below. In this case, the transmitted data conforms to the ID and DLC of the received remote frame.

• Selecting a transmit frame The CAN module checks slots which have transmit requests (including remote frame transmit slots) every intermission to determine the frame to transmit. If there are multiple transmit slots, frames are transmitted in order of slot numbers beginning with the smallest.
• Transmitting a data frame After determining the transmit slot, the CAN module sets the corresponding CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 1, thereby starting transmission.
• If the CAN module failed to gain control of the bus or a CAN bus error occurs If the CAN module failed to gain control of the bus or a CAN bus error occurs while transmitting, the CAN module clears the CAN Message Slot Control Register's TRSTAT (Transmit/Receive Status) bit to 0. If the CAN module requested a transmit abort, the transmit abort is accepted and writing to the message slot is enabled.
• Completion of data frame transmission When data frame transmission is completed, the CAN Message Slot Control Register's TRFIN (Transmit/Receive Finished) bit and the CAN Slot Interrupt Status Register are set to 1. Also, a time stamp count value at the time transmission was completed is written to the CAN Message Slot Time Stamp (C0MSLnTSP), and the transmit operation is thereby completed. If the CAN slot interrupt has been enabled, an interrupt request is generated at completion of transmit operation. The slot which has had transmission completed goes to an inactive state and remains inactive (neither transmit nor receive) until it is newly set in software.

13-81 32170/32174 Group User's Manual (Rev. 2.1) CAN MODULE Figure 13.8.2 Operation of the CAN Message Slot Control Register when Receiving Remote Frames B’0000 0000 B’0000 0000 Clear receive request B’0000 1010 B’0110 0010 Store received data Clear receive request B’0000 0010 B’0000 0001 Finished storing received data B’0110 1000 B’0110 1011 Finished storing received data Clear receive request B’0110 0001 B’0110 0000 B’0111 1000 B’0000 1010 B’0000 0000 Wait for receive data Transmit data frame Clear receive requestFinished transmitting data frame Finished transmitting data frame Transmit data frame Finished storing received data Store received data B’0111 1011 B’0111 0000 Finished storing received data Finished storing received data Clear receive reques t Store received data Clear receive request Write H’60 (automatic response enable) Write H’70 (automatic response enable) Store received data

13-82 32170/32174 Group User's Manual (Rev. 2.1) CAN MODULE

• Note for cancelation of transmit and receive CAN remote frame When aborting remote frame transmission or canceling remote frame receiving, make sure that the RA (Remote Active) bit is cleared to 0 after writing "H'00" or "H'0F" to the CAN Message Slot Control Register. (1) When aborting remote frame transmission RA (Remote Active) bit = "0" Complete transmission abort Note 1: H'00 or H'0F can be used. No Ye s Start transmission abort Write H'00 or H'0F to CAN message slot control register (Note 1) Read CAN message slot control register Figure 13.9.1 Opertion Flow when Aborting Remote Frame Transmission Figure 13.9.2 Opertion Flow when Canceling Remote Frame Receiving Complete receiving abort No Ye s Start receiving abort Write H'00 or H'0F to CAN message slot control register (Note 1) Read CAN message slot control register RA (Remote Active) bit = "0" Note 1: H'00 or H'0F can be used. (1) When canceling remote frame receiving

(RTD)

14.1 Outline of the Real-Time

Debugger (RTD)

14.2 Pin Function of the RTD

14.3 Functional Description of the

14.4 Typical Connection with the

14-2 32170/32174 Group User's Manual (Rev. 2.1)

14.1 Outline of the Real-Time Debugger (RTD)

The Real-Time Debugger (RTD) is a serial I/O through which to read or write to the internal RAM's entire area using commands from outside the microprocessor. Because data transfers between the RTD and internal RAM are performed using an internal dedicated bus independently of the M32R CPU, operation can be controlled without having the stop the M32R CPU. Table 14.1.1 Outline of the Real-Time Debugger (RTD) Item Content Transfer method Clock-synchronized serial I/O Generation of transfer clock Generated by external host RAM access area Entire area of internal RAM (controlled by A16-A29) Transmit/receive data length 32 bits (fixed) Bit transfer sequence LSB first Maximum transfer rate 2 Mbits/second Input/output pins 4 lines (RTDTXD, RTDRXD, RTDACK, RTDCLK) Number of commands Following five functions

• Monitors continuously
• Outputs real-time RAM contents
• Forcibly rewrites RAM contents (with verify)
• Recovers from runaway
• Requests RTD interrupt REAL-TIME DEBUGGER (RTD)

Figure 14.1.1 Block Diagram of the Real-Time Debugger (RTD) Control circuit Command Data RTD control circuit Entire RAM area CPU Address Data Bus switching circuit RTDCLK RTDACK RTDTXD RTDRXD Address Data Data Address

14-3 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD) Pin functions of the RTD are shown below. Table 14.2.1 Pin Function of the RTD Pin Name Type Function RTDTXD Output RTD serial data output RTDRXD Input RTD serial data input RTDACK Output Outputs a low-level pulse synchronously with the beginning clock edge of the output data word. The width of the low-level pulse thus output indicates the type of instruction/data that the RTD received. 1 clock period : VER (continuous monitor) command 1 clock period : VEI (RTD interrupt request) command 2 clock periods : RDR (real-time RAM content output) command 3 clock periods : WRR (RAM content forcible rewrite) command or the data to rewrite 4 clock periods or more: RCV (recover from runaway) command RTDCLK Input RTD transfer clock input

14-4 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD)

14.3 Functional Description of the RTD

14.3.1 Outline of RTD Operation

Operation of the RTD is specified by a command entered from devices external to the chip. A command is specified in bits 16-19(note 1) of the RTD receive data. Table 14.3.1 RTD Commands RTD Receive Data Command Mnemonic RTD Function b19 b18 b17 b16 0 0 0 0 VER (VERify) Continuous monitor 0100 0101 0 1 1 0 VEI (VErify Interrupt request) RTD interrupt request 0 0 1 0 RDR (ReaD RAM) Real-time RAM content output 0 0 1 1 WRR (WRite RAM) RAM content forcibly rewrite (with verify) 1 1 1 1 RCV (ReCoVer) Recover from runaway (Note 2, Note 3) 0 0 0 1 System reserved (use inhibited) ↑ (Note 1) Note 1 : Bit 19 of RTD receive data is not actually stored in the command register and except for the RCV command, is handled as "Don't Care" bit. (Bits 16-18 are effective for the command specified.) Note 2 : The RCV command must always be transmitted twice in succession. Note 3 : For the RCV command, all bits, not just bits 16-19, (i.e., bits 0-15 and bits 20-31) must be set to 1.

14-5 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD)

14.3.2 Operation of RDR (Real-time RAM Content Output)

When the RDR (real-time RAM content output) command is issued, the RTD is made possible to transfer the contents of the internal RAM to external devices without causing the CPU's internal bus to stop. Because the RTD reads data from the internal RAM while no transfers are being performed between the CPU and internal RAM, no extra load is levied on the CPU. The address to be read from the internal RAM can only be specified on 32-bit word boundaries. (The two low-order address bits specified by a command are ignored.) Note also that data are read out in units of 32 bits as transferred from the internal RAM to an external device. Figure 14.3.1 RDR Command Data Format Figure 14.3.2 Operation of the RDR Command Note: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Note: (An) = Specified address D (An) = Data at specified address (An) X 0 0 1 0 19 18 17 16 X X 14 13 12 1 A16 X A17A28A29 Command (RDR) Specified address RTDRXD (MSB side)(LSB side) 32 clock periods 32 clock periods 32 clock periods 32 clock periods RDR (A1) RDR (A2) RDR (A3) D (A1) D (A2) 2 clock periods RTDCLK RTDRXD RTDTXD RTDACK

14-6 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD) Figure 14.3.3 Read Data Transfer Format Note: The read data is transferred LSB-first. D31 D30 Read data (Note) RTDTXD (MSB side)(LSB side)

14-7 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD)

14.3.3 Operation of WRR (RAM Content Forcible Rewrite)

When the WRR (RAM content forcible rewrite) command is issued, the RTD forcibly rewrites the contents of the internal RAM without causing the CPU's internal bus to stop. Because the RTD writes data to the internal RAM while no transfers are being performed between the CPU and internal RAM, no extra load is levied on the CPU. The address to be read from the internal RAM can only be specified on 32-bit word boundaries. (The two low-order address bits specified by a command are ignored.) Note also that data are written to the internal RAM in units of 32 bits. The external host should transmit the command and address in the first frame and then the write data in the second frame. The timing at which the RTD writes to the internal RAM occurs in the third frame after receiving the write data. Figure 14.3.4 WRR Command Data Format Note 1: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Note 2: The specified address and write data are transferred LSB-first. X 0 0 1 1 19 18 17 16 X X 14 13 12 1 A16 X A17A28A29 Command (WRR) Specified address RTDRXD (MSB side)(LSB side) D31 D30 Write data (Note) (MSB side)(LSB side) RTDRXD a) First frame b) Second frame

14-8 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD) Figure 14.3.5 Operation of the WRR Command The RTD reads out data from the specified address before writing to the internal RAM and again reads out from the same address immediately after writing to the internal RAM (this helps to verify the data written to the internal RAM). The read data is output at the timing shown below. Note: (An) = Specified address D (An) = Data at specified address (An) D (A1) Verify value after write WRR (A1) (A1) Write data RTDCLK RTDRXD RTDTXD RTDACK WRR (A2) (A2) Write data D (A1) Read value before write 32 clock periods 32 clock periods 32 clock periods 32 clock periods 3 clock periods

14-9 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD)

14.3.4 Operation of VER (Continuous Monitor)

When the VER (continuous monitor) command is issued, the RTD outputs data from the address that has been accessed by the instruction (either read or write) immediately before receiving the VER command. Figure 14.3.6 VER (Continuous Monitor) Command Data Format Figure 14.3.7 Operation of the VER (Continuous Monitor) Command Note: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Note 1: WRR command can also be used. Note 2: (An) = Specified address D (An) = Data at specified address (An) X0 0 0 0 19 18 17 16 X 15 0 X RTDRXD (MSB side)(LSB side) X Command (VER) RDR (A1) VER RTDCLK RTDRXD RTDTXD RTDACK D (A1) Read value (Note 2) D (A1) Latest read value (Note 1) VER 32 clock periods 32 clock periods 32 clock periods 32 clock periods 2 clock periods

14-10 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD)

14.3.5 Operation of VEI (Interrupt Request)

When the VEI (interrupt request) command is issued, the RTD outputs data from the address that has been accessed by the instruction (either read or write) immediately before receiving the VEI command. Figure 14.3.8 VEI (Interrupt Request) Command Data Format Figure 14.3.9 Operation of the VEI (Interrupt Request) Command Note: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Note 1: WRR command can also be used. Note 2: (An) = Specified address D (An) = Data at specified address (An) X 0110 19 18 17 16 X 15 0 X RTDRXD (MSB side)(LSB side) X VEI (interrupt request generation) command (Note) (Note) RTD interrupt RDR (A1) VEI RTDCLK RTDRXD RTDTXD RTDACK D (A1) Read value (Note 2) (Note 1) 32 clock periods 32 clock periods 32 clock periods 32 clock periods 2 clock periods D (A1) Read value (Note 2) RTD interrupt request

14-11 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD)

14.3.6 Operation of RCV (Recover from Runaway)

When the RTD runs out of control, the RCV (recover from runway) command can be issued to forcibly recover from the runaway condition without having to reset the system. The RCV command must always be issued twice in succession. Also, any command issued subsequently after the RCV command must have its bits 20-31 all set to 1. Figure 14.3.10 RCV Command Data Format Note: All of 32 data bits are 1's. The RCV command must always be issued twice in succession. Note: The next command following the RCV command must have its bits 20-31 all set to 1. Figure 14.3.11 Operation of the RCV Command 11 1 1 1 19 18 17 16 15 0 RTDRXD (MSB side)(LSB side) Command (RCV) (Note) (Note) RCV RCV command stored here RTDCLK RTDRXD RTDTXD RTDACK RCV Bits 20-31 D (A1)Indeterminate data during runway condition Indeterminate value during runway condition Next command following the RCV command 1 1 RDR (A1) 32 clock periods 32 clock periods 32 clock periods 32 clock periods 2 clock periods 2 clock periods

14-12 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD) Figure 14.3.12 Method for Setting Addresses in Real-Time Debugger

14.3.7 Method to Set a Specified Address when Using the RTD

When using the Real-Time Debugger (RTD), you can set low-order 16-bit addresses of the internal RAM area. Because the internal RAM area is located in a 48 KB area ranging from H'0080 4000 to H'0080 FFFF, you can set low-order 16-bit addresses of that area. However, access to any locations other than the area where the RAM resides is inhibited. Note also that two least significant address bits, A31 and A30, are always 0's because data are read and written to the internal RAM in a fixed length of 32 bits. SFR 16KB H’0080 0000 H’0080 4000 Memory map H’0080 FFFF XX A29 - A16 H’0080 4000~H’0080 FFFF RAM areaonly can be specified

14-13 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD) Figure 14.3.13 Command Transfer to the RTD after System Reset Note: (An) = Specified address D (An) = Data at specified address (An)

14.3.8 Resetting the RTD

The RTD is reset by applying a system rest (i.e., by entering the RESET signal). The status of the RTD related output pins after a system reset are shown below. Table 14.3.2 RTD Pin State after System Reset Pin Name State RTDACK High-level output RTDTXD High-level output The first command transfer to the RTD after it was reset is initiated by transferring data to the RTDRXD pin synchronously with falling edges of RTDCLK. Don ’t Care RDR (A1) RTDCLK RTDRXD RTDTXD RTDACK RESET System reset "H" RDR (A2) 0000 0000 0000 0000 D (A2) "H" D (A1) 32 clock periods 32 clock periods 32 clock periods 32 clock periods

14-14 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD)

14.4 Typical Connection with the Host

Figure 14.4.1 Connecting the RTD and Host Note: In this example, the RTDACK level is checked between transfer frames. The host uses a serial synchronous interface to transfer data. The clock for synchronous is generated by the host. An example for connecting the RTD and host is shown below. RTDRXD RTDTXD RTDCLK RTDACK M32R/ECU Host microprocessor RXD TXD SCLK PORT(Note)

14-15 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD) The RTD communication for a fixed length of 32 bits per frame generally is performed in four operations sending 8 bits at a time, because most serial interfaces transfer data in units of 8 bits. The RTDACK signal is used to verify that communication is performed normally. After transmitting a command, the RTDACK signal is pulled low, making it possible to verify the communication status. When issuing the VER command, the RTDACK signal goes low for only one clock period. Therefore, after sending 32 bits in one frame, turn off RTDCLK output and check whether RTDACK is low. If RTDACK is low, you know that the RTD is communicating normally. If you want to identify the type of transmitted command by the width of RTDACK, use the 32170's internal measurement timer (to count RTDCLK pulses while RTDACK is low) or create a dedicated circuit. Figure 14.4.2 Typical Operation for Communication with the Host (when Issuing VER Command) Transfer of next frame (8 bits) Check the RTDACK signal L level. RTDCLK RTDRXD RTDTXD RTDACK Transfer of 1 frame (32 bits) (8 bits) (8 bits)

14-16 32170/32174 Group User's Manual (Rev. 2.1) REAL-TIME DEBUGGER (RTD)

• This is a blank page.*

15.1 External Bus Interface

15.2 Read/Write Operations

15.3 Bus Arbitration

15.4 Typical Connection of

15-2 32170/32174 Group User's Manual (Rev. 2.1) EXTERNAL BUS INTERFACE

15.1 External Bus Interface Related Signals

The 32170 comes with external bus interface related signals shown below. These signals can be used in external extension mode or processor mode. (1) Address The 32170 outputs a 20-bit address (A11-A30) for addressing any location in 2 Mbytes of space.___ The least significant A31 is not output, and in external write cycles, the 32170 outputs BHW and___ BLW signals to indicate the valid byte position at which to write on the 16-bit data bus. In read cycles, the 32170 reads data always in 16 bits, transferring only the data read from the valid byte position of the bus. (2) Chip select (CS0, CS1) These signals are output in external extension mode or processor mode, with CS0 and CS1___ specifying an extended external area of 2 Mbytes each. The CS0 signal points to a 2-Mbyte area in processor mode or a 1-Mbyte area in external extension mode. (For details, refer to Chapter 3, "Address Space.") (3) Read strobe (RD) Output during external read cycle, this signal indicates the timing at which to read data from the bus. This signal is driven high when writing to the bus or accessing the internal function. (4) Byte High Write/Byte High Enable (BHW / BHE) The pin function changes depending on the Bus Mode Control Register (BUSMODC). ___ When BUSMOD = 0 and this signal is Byte High Write (BHW), during external write access it indicates that the upper byte (DB0-DB7) of the data bus is the valid data to transfer. During external read and when accessing the internal function it outputs a high. ___ When BUSMOD = 1 and this signal is Byte High Enable (BHE), during external access it indicates that the upper byte (DB0-DB7) of the data bus is the valid data to transfer. When accessing the internal function, it outputs a high. (5) Byte Low Write/Byte Low Enable (BLW / BLE) The pin function changes depending on the Bus Mode Control Register (BUSMODC). ___ When BUSMOD = 0 and this signal is Byte Low Write (BLW), during external write access it indicates that the lower byte (DB8-DB15) of the data bus is the valid data to transfer. During external read cycle, it outputs a high. ___ When BUSMOD = 1 and this signal is Byte Low Enable (BLE), during external access it indicates that the lower byte (DB8-DB15) of the data bus is the valid data to transfer. When accessing the internal function, it outputs a high.

15-3 32170/32174 Group User's Manual (Rev. 2.1) EXTERNAL BUS INTERFACE (6) Data bus (DB0 - DB15) This is the 16-bit data bus used to access external devices. (7) System clock/write (BCLK / WR) The pin function changes depending on the Bus Mode Control Register (BUSMODC). When BUSMOD = 0 and this signal is System Clock (BCLK), it outputs the system clock necessary to synchronize operations in an external system. When the CPU clock = 40 MHz, a 20 MHz clock is output from BCLK. When not using the BCLK/WR function, this pin can be used as P70 by setting the P7 Operation Mode Register P70MOD bit to 0. When BUSMOD = 1 and this signal is Write (WR), during external write access it indicates the valid data on the data bus to transfer. During external read cycle and when accessing the internal function, it outputs a high. ____ (8) Wait (WAIT) ____ When the 32170 started an external bus cycle, it automatically inserts wait cycles while the WAIT signal is asserted. For details, refer to Chapter 16, "Wait Controller." When not using the WAIT function, this pin can be used as P71 by setting the P7 Operation Mode Register P71MOD bit to 0. Note that the 32170 always inserts one or more wait cycles for external access. Therefore, the shortest time in which an external device can be accessed is one wait cycle (2 BCLK periods). (9) Hold control (HREQ, HACK) The hold state refers to a state in which the 32170 has stopped bus access and bus interface related pins are tristated (high impedance). While the 32170 is in a hold state, any bus master external to the chip can use the system bus to transfer data. ____ The 32170 is placed in a hold state by pulling the HREQ pin input low. While the 32170 remains in____ a hold state after accepting the hold request and during a transition to the hold state, the HACK pin outputs a low-level signal. To exit from the hold state and return to normal operating state, release____ the HREQ signal back high. When not using the HREQ and HACK functions, these pins can be used as P72 and P7 by setting the P73 Operation Mode Register P72MOD and P73MOD bits to 0. The status of each 32170 pin during hold are shown below. Table 15.1.1 Pin State during Hold Period Pin Name Pin State or Operation A11-A30, DB0-DB15, CS0, CS1, RD, BHW, BLW, BHE, BLE, WR High impedance ____ HACK Outputs a low Other pins (e.g., ports and timer output) Normal operation

15-4 32170/32174 Group User's Manual (Rev. 2.1) EXTERNAL BUS INTERFACE (10) Port P7 Operation Mode Register (P7MOD) The WAIT, HREQ, and HACK pins are shared with P71, P72, and P73, respectively. The Port P7 Operation Mode Register is used to select the function of port P7. Configuration of this register is shown below. I P7 Operation Mode Register <Address: H'0080 0747> D 8 9 1 01 11 21 31 4 D 1 5 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD <When reset : H'00> D Bit Name Function R W (Port P70 operation mode) 1 : BCLK / WR (Port P71 operation mode) ____ 1 : WAIT (Port P72 operation mode) ____ 1 : HREQ (Port P73 operation mode) ____ 1 : HACK (Port P74 operation mode) 1 : RTDTXD (Port P75 operation mode) 1 : RTDRXD (Port P76 operation mode) 1 : RTDACK (Port P77 operation mode) 1 : RTDCLK

15-5 32170/32174 Group User's Manual (Rev. 2.1) EXTERNAL BUS INTERFACE (11) Bus Mode Control Register (BUSMODC) The 32170 contains a function to switch between two external bus modes. I Bus Mode Control Register (BUSMODC) <Address: H'0080 077F> D 8 9 1 01 11 21 31 4 D 1 5 BUSMOD <When reset : H'00> D Bit Name Function R W 8 - 15 No functions assigned 0 —

15 BUSMOD 0: WR signal separate mode

(Bus mode control) 1: Byte enable separate mode This register is used to facilitate memory connection in processor mode and external extension mode. When Bus Mode Control Register (BUSMOD) = 0, the WR signal is output separately for each byte__ ___ ___ ____ ____ area. Signals RD, BHW, BLW, BCLK, and WAIT can be used. For memory connection in boot mode, the Bus Mode Control Register has no effect and the interface operates under conditions where Bus Mode Control Register (BUSMOD) = 0. When Bus Mode Control Register (BUSMOD) = 1, the byte enable signal is output separately for__ ___ ___ __ ____ each byte area. Signals RD, BHW, BLE, WR, and WAIT can be used. For WAIT control circuit configuration, because BCLK is not output, external timing control is required. Figure 15.1.1 Pin Function when Bus Modes are Changed CS0, CS1 DB0 - DB15 WAIT RD BHW BLW A11 - A30 CS0, CS1 DB0 - DB15 WAIT RD WR BHE BLE A11 - A30 BCLK BUSMOD = 0 BUSMOD = 1

15-6 32170/32174 Group User's Manual (Rev. 2.1) EXTERNAL BUS INTERFACE (1) When Bus Mode Control Register = 0 ___ External read/write operations are performed using the address bus, data bus, and signals CS0,___ __ ___ _______ ____ CS1, RD, BHW, BLW, WAIT, and BCLK. In external read cycle, the RD signal is low while BHW and BLW both are high, reading data from only the valid byte position of the bus. In external write cycle, BHW or BLW output for the byte position to which to write is pulled low as data is written to the bus. ____ When an external bus cycle starts, wait cycles are inserted as long as the WAIT signal is low.____ Unless the WAIT signal is needed, leave it held high. During external bus cycles, at least one wait cycle is inserted even for the shortest-case access. (The shortest bus cycle is 2 BCLK periods.) Figure 15.2.1 Internal Bus Access during Bus Free State Note: THi-Z denotes a high-impedance state. Bus-free state internal bus access "H" BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD "H" Hi-z "H"

15-7 32170/32174 Group User's Manual (Rev. 2.1) EXTERNAL BUS INTERFACE Figure 15.2.2 Read/Write Timing (for Shortest-case External Access) Note: Circles above indicate points at which signals are sampled. Read (2 cycles) "H" "H" "H" "H" One wait cycle BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Read Write (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Write

15-8 32170/32174 Group User's Manual (Rev. 2.1) EXTERNAL BUS INTERFACE Figure 15.2.3 Read/Write Timing (for Access with 2 Internal and 1 External Wait Cycles) Note: Circles above indicate points at which signals are sampled. "H" (Don’t Care) "H" "L" "H" (Don’t Care) "L" "H" 1 external wait cycle2 internal wait cycles Read (4 cycles) BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Read Write (4 cycles) BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Write 1 external wait cycle2 internal wait cycles

15-9 32170/32174 Group User's Manual (Rev. 2.1) EXTERNAL BUS INTERFACE Figure 15.2.4 Internal Bus Access during Bus Free State Note 1: Hi-Z denotes a high-impedance state. Note 2: BCLK is not output. (2) When Bus Mode Control Register = 1 ___ External read/write operations are performed using the address bus, data bus, and signals CS0,___ __ ___ ___ ____ __ __ ___ CS1, RD, BHE, BLE, WAIT, and WR. In external read cycle, the RD signal goes low and BHE or___ BLE output for the byte position from which to read is pulled low, reading data from only the byte__ ___ ___ position of the bus. In external write cycle, the WR signal goes low and BHE or BLE output for the byte position to which to write is pulled low, writing data to the necessary byte position. ____ When an external bus cycle starts, wait cycles are inserted as long as the WAIT signal is low.____ Unless the WAIT signal is needed, leave it held high. During external bus cycle, at least one wait cycle is inserted even for the shortest-case access. (The shortest bus cycle is 2 BCLK periods.) When not using the WAIT function, the pin can be used as P71 by setting the P7 Operation Mode Register P71MOD bit to 0. "H" "H" Hi-z "H" "H" Bus-free state internal bus access BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD WR

15-10 32170/32174 Group User's Manual (Rev. 2.1) EXTERNAL BUS INTERFACE Figure 15.2.5 Read/Write Timing (for Shortest-case External Access) Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. "H" "H" "H" "H" Read (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Read Write (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Write WR WR

15-11 32170/32174 Group User's Manual (Rev. 2.1) EXTERNAL BUS INTERFACE Figure 15.2.6 Read/Write Timing (for Access with 2 Internal and 1 External Wait Cycles) Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. "H" "H" "L" "H" "L" "H" (Don’t Care) 1 external wait cycle2 internal wait cycles Read (4 cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Read Write (4 cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Write 1 external wait cycle2 internal wait cycles WR WR (Don’t Care)

15-12 32170/32174 Group User's Manual (Rev. 2.1) Figure 15.3.1 Bus Arbitration Timing EXTERNAL BUS INTERFACE (1) When Bus Mode Control Register = 0 ____ When HREQ pin input is pulled low and the hold request is accepted, the 32170 goes to a hold state____ and outputs a low from the HACK pin. During hold state, all bus related pins are placed in the high- impedance state, allowing data to be transferred on the system bus. To exit the hold state and____ return to normal operating state, release the HREQ signal back high. Note 1: Circles above indicate points at which signals are sampled. Note 2: Hi-z indicate the high-impedance state. Note 3: Idle cycles are inserted only when the hold state is assumed after external lead access. DB0 - DB15 BCLK HREQ HACK A11 - A30 CS0 , CS1 RD BHW , BLW WAIT Hi-Z Hi-Z Hi-Z Hi-Z Bus cycle Idle Go to hold Hold state Return Next bus cycle

15-13 32170/32174 Group User's Manual (Rev. 2.1) Figure 15.3.2 Bus Arbitration Timing EXTERNAL BUS INTERFACE Note 1: Circles above indicate points at which signals are sampled. Note 2: Hi-z indicate the high-impedance state. Note 3: Idle cycles are inserted only when the hold state is assumed after external lead access. (2) When Bus Mode Control Register = 1 ____ When HREQ pin input is pulled low and the hold request is accepted, the 32170 goes to a hold state____ and outputs a low from the HACK pin. During hold state, all bus related pins are placed in the high- impedance state, allowing data to be transferred on the system bus. To exit the hold state and____ return to normal operating state, release the HREQ signal back high. DB0 - DB15 BCLK Hi-Z HREQ HACK A11 - A30 CS0 , CS1 RD WR BHW , BLW WAIT Hi-Z Hi-Z Hi-Z Hi-Z Bus cycle Idle Go to hold Hold state Return Next bus cycle

15-14 32170/32174 Group User's Manual (Rev. 2.1) Figure 15.4.1 Typical Connection of External Extension Memory (When BUSMOD = 0) Note: The 32170 addresses and data are arranged in such a way that bit 0 = MSB, and bit 15 = LSB. Therefore, the MSB and LSB sides must be reversed when connecting external extension memory. EXTERNAL BUS INTERFACE

15.4 Typical Connection of External Extension Memory

(1) When Bus Mode Control Register = 0 A typical connection when using external extension memory is shown in Figure 15.4.1. (External extension memory can only be used in external extension mode and processor mode.) Memory mapping Internal flash memory (768KB) External memory area (1MB) Number of bus wait cycles can be set to 1-4. Normally used as port. WAIT is used only when four or more wait cycles are needed. H ’0000 0000 H ’0040 0000 H ’0020 0000 H ’000C 0000 Unused H ’0010 0000 1M-CS0 area SRAM Flash memory A18 D15 RD CS max1MB A18 D15 RD (D0-D15) CS WR (D0-D7) WR (D8-D15) max1MB 2 (total2MB) 32170F6 A11 A30 D15 RD CS0 CS1 BLW BHW WAIT External memory area (2MB) 2M-CS1 area *

15-15 32170/32174 Group User's Manual (Rev. 2.1) Figure 15.4.2 Typical Connection of External Extension Memory (When BUSMOD = 1) Note: The 32170 addresses and data are arranged in such a way that bit 0 = MSB, and bit 15 = LSB. Therefore, the MSB and LSB sides must be reversed when connecting external extension memory. EXTERNAL BUS INTERFACE (2) When Bus Mode Control Register = 1 A typical connection when using external extension memory is shown in Figure 15.4.2. (External extension memory can only be used in external extension mode and processor mode.) M32170F6 A11 A30 D15 RD CS0 CS1 BLE BHE WAIT H ’0000 0000 H ’0040 0000 H ’0020 0000 H ’000C 0000 H ’0010 0000 A18 D15 RD CS max1MB A19 D15 RD (D0-D15) CS BHE (D0-D7) BLE (D8-D15) max2MB WR WR (D0-D15) Memory mapping Internal flash memory (768KB) External memory area (1MB) Number of bus wait cycles can be set to 1-4. Normally used as port. WAIT is used only when four or more wait cycles are needed. Unused 1M-CS0 area SRAM Flash memory External memory area (2MB) 2M-CS1 area

15-16 32170/32174 Group User's Manual (Rev. 2.1) Figure 15.4.3 Typical Connection of External Extension Memory (Using 8/16-bit Mixed Memories when BUSMOD = 1) Note: The 32170 addresses and data are arranged in such a way that bit 0 = MSB, and bit 15 = LSB. Therefore, the MSB and LSB sides must be reversed when connecting external extension memory. EXTERNAL BUS INTERFACE (3) Using 8/16-bit data bus memories in combination when Bus Mode Control Register = 1 The diagram below shows a typical connection of external extension memory, with 8-bit data bus memory located in the CS0 area, and 16-bit data bus memory located in the CS1 area. (External extension memory can only be used in external extension mode and processor mode.) Note: The QS32X2245 is a product made by IDT Company. When CL = 50 pF, memory can be connected with only 2 ns data delay H ’0000 0000 H ’0040 0000 H ’0020 0000 H ’000C 0000 H ’0010 0000 8-bit memory A18 RD CS max1MB A19 D15 BHE CS WR (D0-D15) RD (D0-D15) max2MB M32170F6VFP A11 A30 D15 RD CS0 CS1 BHE WR WAIT QS32X2245 BLEBLE A0 8-bit bus area Memory mapping Internal flash memory (768KB) External memory area (1MB) Number of bus wait cycles can be set to 1-4. Normally used as port. WAIT is used only when four or more wait cycles are needed. Unused 1M-CS0 area SRAM External memory area (2MB) 2M-CS1 area 16-bit bus area A B OE A B

16.1 Outline of the Wait Controller

16.2 Wait Controller Related

16.3 Typical Operation of the Wait

16-2 32170/32174 Group User's Manual (Rev. 2.1) WAIT CONTROLLER The wait controller controls the number of wait cycles inserted in bus cycles during access to an extended external area. The following outlines the wait controller. Table 16.1.1 Outline of the Wait Controller Item Specification Target space Wait cycles in following memory spaces are controlled depending on operation mode Single-chip mode : No target space (Wait controller settings have no effect) External extension mode: CS0 area (1 Mbytes), CS1 area (2 Mbytes) Processor mode : CS0 area (2 Mbytes), CS1 area (2 Mbytes) Number of wait cycles 1 to 4 wait cycles inserted by software + any number of wait cycles inserted from that can be inserted ____ WAIT pin (Bus cycles with 1 wait cycle are the shortest bus cycle for external access.) In external extension mode and processor mode, two chip select signals (CS0, CS1) are output to___ ___ an extended external area. Two areas in it corresponding to CS0 and CS1 signals are called the CS0 and the CS1 areas, respectively. Figure 16.1.1 CS0 and CS1 Area Address Map H’0000 0000 H’001F FFFF H’0020 0000 H’003F FFFF Non-CS0 area (Internal ROM access area) <Processor mode> CS1 area (2 Mbytes) CS0 area (1 Mbytes) <External extension mode> H’000F FFFF H’0010 0000 Extended external area Internal ROM area Reserved area Extended external areaCS1 area (2 Mbytes) CS0 area (2 Mbytes)

16-3 32170/32174 Group User's Manual (Rev. 2.1) WAIT CONTROLLER When accessing an extended external area, the wait controller controls the number of wait cycles to be inserted in bus cycles based on the number of wait cycles set by software and those entered____ from the WAIT pin. The number of wait cycles that can controlled in software is 1 to 4. (For external access, bus cycles with 1 wait cycle are the shortest bus cycle.) ____ When the WAIT pin input is sampled low in the last cycle of internal wait cycles set by software, the____ ____ wait cycle is extended as long as the WAIT signal is held low. Then when the WAIT signal is released back high, the wait cycle is terminated and the next new bus cycle is entered into. Table 16.1.2 Number of Wait Cycles that Can be Set by the Wait Controller Extended External Area Address Number of Wait Cycles Inserted CS0 area H'0010 0000 - H'001F FFFF One to 4 wait cycles set by software + any number of (External extension mode) ____ wait cycles entered from WAIT pin H'0000 0000 - H'001F FFFF (However, wait cycles set by software have priority.) (Processor mode) CS1 area H'0020 0000 - H'003F FFFF One to 4 wait cycles set by software + any number of (External extension mode ____ wait cycles entered from WAIT pin and processor mode) (However, wait cycles set by software have priority.)

16-4 32170/32174 Group User's Manual (Rev. 2.1) Figure 16.2.1 Wait Controller Related Register Map WAIT CONTROLLER

16.2 Wait Controller Related Registers

The following shows a wait controller related register map. H’0080 0180 Address D0 D7 +0 Address +1 Address D8 D15 Wait Cycles Control Register (WTCCR) Blank addresses are a reserved area.

16-5 32170/32174 Group User's Manual (Rev. 2.1)

16.2.1 Wait Cycles Control Register

I Wait Cycles Control Register (WTCCR) <Address: H'0080 0180> D 0 123456 D 7 CS0WTC CS1WTC <When reset : H'00> D Bit Name Function R W 0 , 1 No functions assigned 0 — 2 , 3 CS0WTC 00 : 4 wait cycles (when reset) (CS0 wait cycles control) 01 : 3 wait cycles 10 : 2 wait cycles 11 : 1 wait cycle 4 , 5 No functions assigned 0 — 6 , 7 CS1WTC 00 : 4 wait cycles (when reset) (CS1 wait cycles control) 01 : 3 wait cycles 10 : 2 wait cycles 11 : 1 wait cycle WAIT CONTROLLER

16-6 32170/32174 Group User's Manual (Rev. 2.1)

16.3 Typical Operation of the Wait Controller

The following shows a typical operation of the wait controller. The wait controller can control bus access in the range of 2 to 5 cycles. If more access cycles than that are needed, use the WAIT function in combination with the wait controller. (1) When Bus Mode Control Register = 0 ___ External read/write operations are performed using the address bus, data bus, and signals CS0,___ __ ___ ___ ____ CS1, RD, BHW, BLW, WAIT, and BCLK. Figure 16.3.1 Internal Bus Access during Bus Free State Note: THi-Z denotes a high-impedance state. Bus-free state internal bus access "H" BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD "H" Hi-z "H" WAIT CONTROLLER

16-7 32170/32174 Group User's Manual (Rev. 2.1) Figure 16.3.2 Read/Write Timing (for Access with 1 Internal Wait Cycle) Note: Circles above indicate points at which signals are sampled. Read (2 cycles) "H" "H" "H" "H" One wait cycle BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Read Write (2 cycles) One wait cycle BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Write WAIT CONTROLLER

16-8 32170/32174 Group User's Manual (Rev. 2.1) Figure 16.3.3 Read/Write Timing (for Access with 2 Internal Wait Cycles) Note: Circles above indicate points at which signals are sampled. "H" (Don’t Care) "H" "H" (Don’t Care) "H" 2 internal wait cycles Read (3 cycles) BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Read Write (3 cycles) BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Write 2 internal wait cycles WAIT CONTROLLER

16-9 32170/32174 Group User's Manual (Rev. 2.1) WAIT CONTROLLER Figure 16.3.4 Read/Write Timing (for Access with 3 Internal Wait Cycles) Note: Circles above indicate points at which signals are sampled. "H" (Don’t Care) "H" "H" (Don’t Care) "H" 3 internal wait cycles Read (4 cycles) BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Read Write (4 cycles) BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Write 3 internal wait cycles

16-10 32170/32174 Group User's Manual (Rev. 2.1) WAIT CONTROLLER Figure 16.3.5 Read/Write Timing (for Access with 4 Internal Wait Cycles) Note: Circles above indicate points at which signals are sampled. "H" (Don’t Care) "H" "H" (Don’t Care) "H" 4 internal wait cycles Read (5 cycles) BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Read Write (5 cycles) BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Write 4 internal wait cycles

16-11 32170/32174 Group User's Manual (Rev. 2.1) WAIT CONTROLLER Figure 16.3.6 Read/Write Timing (for Access with 4 Internal and 1 External Wait Cycles) Note: Circles above indicate points at which signals are sampled. "H" (Don’t Care) "H" "H" (Don’t Care) "H" 4 internal wait cycles Read (6 cycles) BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Read Write (6 cycles) BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Write 4 internal wait cycles "L" "L" 1 external wait cycle 1 external wait cycle

16-12 32170/32174 Group User's Manual (Rev. 2.1) WAIT CONTROLLER Figure 16.3.7 Read/Write Timing (for Access with 2 Internal and n External Wait Cycles) Note: Circles above indicate points at which signals are sampled. "H" (Don’t Care) "H" "H" (Don’t Care) "H" 2 internal wait cycles Read (3+n cycles) BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Read Write (3+n cycles) BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Write 2 internal wait cycles "L" "L" n external wait cycles n external wait cycles "L" "L" "L" "L"

16-13 32170/32174 Group User's Manual (Rev. 2.1) WAIT CONTROLLER Figure 16.3.8 Internal Bus Access during Bus Free State Note 1: Hi-Z denotes a high-impedance state. Note 2: BCLK is not output. (2) When Bus Mode Control Register = 1 ___ External read/write operations are performed using the address bus, data bus, and signals CS0,___ __ ___ ___ ____ __ CS1, RD, BHE, BLE, WAIT, and WR. "H" "H" Hi-z "H" "H" Bus-free state internal bus access BCLK A11 - A30 CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD WR

16-14 32170/32174 Group User's Manual (Rev. 2.1) Figure 16.3.9 Read/Write Timing (for Access with 1 Internal Wait Cycle) Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. "H" "H" "H" "H" Read (2 cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Read Write (2 cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Write WR WR 1 internal wait cycle 1 internal wait cycle WAIT CONTROLLER

16-15 32170/32174 Group User's Manual (Rev. 2.1) Figure 16.3.10 Read/Write Timing (for Access with 2 Internal Wait Cycles) Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. "H" "H" "H" "H" (Don’t Care) 2 internal wait cycles Read (3 cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Read Write (3 cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Write 2 internal wait cycles WR WR (Don’t Care) WAIT CONTROLLER

16-16 32170/32174 Group User's Manual (Rev. 2.1) Figure 16.3.11 Read/Write Timing (for Access with 3 Internal Wait Cycles) Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. WAIT CONTROLLER "H" "H" "H" "H" (Don’t Care) 3 internal wait cycles Read (4 cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Read Write (4 cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Write 3 internal wait cycles WR WR (Don’t Care)

16-17 32170/32174 Group User's Manual (Rev. 2.1) Figure 16.3.12 Read/Write Timing (for Access with 4 Internal Wait Cycles) Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. WAIT CONTROLLER "H" "H" "H" "H" (Don’t Care) 4 internal wait cycles Read (5 cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Read Write (5 cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Write 4 internal wait cycles WR WR (Don’t Care)

16-18 32170/32174 Group User's Manual (Rev. 2.1) Figure 16.3.13 Read/Write Timing (for Access with 4 Internal and 1 External Wait Cycles) Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. WAIT CONTROLLER "H" "H" "H" "H" (Don’t Care) 4 internal wait cycles Read (6 cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Read Write (6 cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Write 4 internal wait cycles WR WR (Don’t Care) "L" "L" 1 external wait cycle 1 external wait cycle

16-19 32170/32174 Group User's Manual (Rev. 2.1) Figure 16.3.14 Read/Write Timing (for Access with 2 Internal and n External Wait Cycles) Note 1: Circles above indicate points at which signals are sampled. Note 2: BCLK is not output. WAIT CONTROLLER "H" "H" "H" "H" (Don’t Care) 2 internal wait cycles Read (3+n cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Read Write (3+n cycles) BCLK A11 - A30 CS0, CS1 BHE, BLE DB0 - DB15 WAIT RD Write 2 internal wait cycles WR WR (Don’t Care) "L" "L" n external wait cycles n external wait cycles "L" "L" "L" "L"

16-20 32170/32174 Group User's Manual (Rev. 2.1) WAIT CONTROLLER

• This is a blank page.*

17.1 Outline

17.2 Example of RAM Backup

17.3 Example of RAM Backup for

17.4 Exiting RAM Backup Mode

(Wakeup)

17-2 32170/32174 Group User's Manual (Rev. 2.1) In RAM backup mode, the contents of the internal RAM are retained while the power is turned off. RAM backup mode is used for the following two purposes:

• Back up the internal RAM data when the power is down
• Turn off the power to the CPU whenever necessary to save on the system's power consumption The M32R/ECU CPU is placed in RAM backup mode by applying a voltage of 2.0-3.3 V to the VDD pin (provided for RAM backup) and 0 V to all other pins. During RAM backup mode, the contents of the internal RAM are retained, while the CPU and internal peripheral I/O remain idle. Also, because all pins except VDD are held low during RAM backup mode, power consumption in the system can effectively reduced.

17.2 Example of RAM Backup when Power is Down

A typical circuit for RAM backup at power outage is shown in Figure 17.2.1. The following explains how the RAM can be backed up by using this circuit as an example. RAM BACKUP MODE Figure 17.2.1 Typical Circuit for RAM Backup at Power Outage Note 1: Power outage is detected by the DC IN (regulator input) voltage. Note 2: These pins are used to detect a RAM backup signal. Note 3: This pin outputs a high when the power is on and outputs a low when the power is down. VREFn SBI ADnINi M32R/ECU C Backup battery VCC VDD VBB VREF Reference voltage for power outage detection Power outage detection signal Backup power supply for power outage Power supply monitor IC VDD DC IN Input OutputRegulator (5V system) VCCI AVCCnOSC-VCC OUT VCCE (Note 1) OutputRegulator (3.3V system) (Note 3) (Note 2)

17-3 32170/32174 Group User's Manual (Rev. 2.1) RAM BACKUP MODE

17.2.1 Normal Operating State

Figure 17.2.2 shows the normal operating state of the M32R/ECU. During normal operation, input___ on the SBI pin or ADnINi (i = 0-15) pin used for RAM backup signal detection remains high. Figure 17.2.2 Normal Operating State Note 1: Power outage is detected by the DC IN (regulator input) voltage. Note 2: These pins are used to detect a RAM backup signal. Note 3: This pin outputs a high when the power is on and outputs a low when the power is down. Note 4: Backup power supply = 2.0 to 3.3 V VREFn SBI ADnINi M32R/ECU C Backup battery VCC VDD VBB VREF Reference voltage for power outage detection Power outage detection signal Backup power supply for power outage Power supply monitor IC VDD DC IN Input OutputRegulator (5V system) VCCI AVCCnOSC-VCC OUT VCCE (Note 1) OutputRegulator (3.3V system) (Note 3) (Note 2) 5V3.3V 5V3.3V 5V3.3V(Note 4) "H"

17-4 32170/32174 Group User's Manual (Rev. 2.1) Figure 17.2.3 RAM Backup State at Power Outage Note 1:Power outage is detected by the DC IN (regulator input) voltage. Note 2:These pins are used to detect a RAM backup signal. Note 3:This pin outputs a high when the power is on and outputs a low when the power is down. Note 4: ___ Determined by the input voltage level on SBI pin or ADnINi pin. Note 5:Adjust this capacitance to provid the necessary processing time in (b) . RAM BACKUP MODE

17.2.2 RAM Backup State

Shown in Figure 17.2.3 is the power outage RAM backup state of the M32R/ECU. When the power supply goes down, the power supply monitor IC starts feeding current from the backup battery to the M32R/ECU. Also, the power supply monitor IC's power outage detection pin outputs a low, ___ causing the SBI pin or ADnINi pin input to go low, which generates a RAM backup signal ((a) in Figure 17.2.3). Whether the power is down or not must be determined with respect to the DC IN (regulator input) voltage in order to allow for a software processing time at power outage. To enable RAM backup mode, make the following settings. (1) Create check data to verify after returning from RAM backup to normal mode whether the RAM data has been retained normally ((b) in Figure 17.2.3). When the power supply to VCC goes down after settings in (1), the voltage applied to the VDD pin becomes 2.0-3.3 V and voltages applied to all other pins drop to 0 V, and the M32R/ECU thereby enters RAM backup mode ((c) in Figure 17.2.3). VREFn SBI ADnINi M32R/ECU C Backup battery VCC VDD VBB VREF Reference voltage for power outage detection Power outage detection signal Backup power supply for power outage Power supply monitor IC VDD DC IN Input OutputRegulator (5V system) VCCI AVCCnOSC-VCC OUT VCCE (Note 1) OutputRegulator (3.3V system) (Note 3) (Note 2) 3.3V 0V (Note 4) "L" (Note 5) 2.0V - 3.3V Example of RAM backup processing Power goes down (Note 4) Create check data for backup RAM (a) (b) (c) RAM backup mode 0V0V0V0V

17-5 32170/32174 Group User's Manual (Rev. 2.1) RAM BACKUP MODE

17.3 Example of RAM Backup for Saving Power Consumption

Figure 17.3.1 shows a typical circuit for RAM backup to save on power consumption. The following explains how the RAM is backed up for the purpose of low-power operation by using this circuit as an example. Figure 17.3.1 Typical Circuit for RAM Backup to Save on Power Consumption Note 1: This signal outputs a low for RAM backup. Note 2: This pin outputs a high when the power is on, and is set for input mode when in RAM backup mode. Note 3: These pins are used to detect a RAM backup signal. RAM backup signal (Note 1) External circuit Port X IB RAM backup power supplyDC IN Input OutputRegulator (3.3V system) OutputRegulator (5V system) OutputRegulator (3.3V system) VREFn SBI ADnINi M32R/ECU VDD VCCI AVCCnOSC-VCC VCCE (Note 3) (Note 2)

17-6 32170/32174 Group User's Manual (Rev. 2.1) RAM BACKUP MODE Figure 17.3.2 Normal Operating State Note 1: This signal outputs a low for RAM backup. Note 2: This pin outputs a high when the power is on, and is set for input mode when in RAM backup mode. Note 3: These pins are used to detect a RAM backup signal.

17.3.1 Normal Operating State

Figure 17.3.2 shows the normal operating state of the M32R/ECU. During normal operation, the ___ RAM backup signal output by the external signal is high. Also, input on the SBI pin or ADnINi (i = 0- 15) pin used for RAM backup signal detection remains high. Port X, which is the transistor's base connecting pin, should output a high. This causes the transistor's base voltage, IB, to go high, so that current is fed from the power supply to the VCC pin via the transistor. RAM backup signal (Note 1) External circuit Port X IB RAM backup power supplyDC IN Input OutputRegulator (3.3V system) OutputRegulator (5V system) OutputRegulator (3.3V system) VREFn SBI ADnINi M32R/ECU VDD VCCI AVCCnOSC-VCC VCCE (Note 3) (Note 2) 5V 3.3V5V3.3V 5V3.3V "H" "H" "H"

17-7 32170/32174 Group User's Manual (Rev. 2.1) RAM BACKUP MODE Figure 17.3.3 RAM Backup State for Low-Power Operation Note 1:This signal outputs a low for RAM backup. Note 2:This pin outputs a high when the power is on, and is set for input mode when in RAM backup mode. Note 3:These pins are used to detect a RAM backup signal. Note 4: ___ Determined by the input voltage level on SBI pin or ADnINi pin. Note 5:Base voltage IB = 0 causes the current fed to the VCC pin to stop. Explained in A to D above.

17.3.2 RAM Backup State

___ sequence. When the external circuit outputs a low, input on the SBI pin or ADnINi pin goes low. A low on these input pins generates a RAM backup signal (A and (a) in Figure 17.3.3). To enable RAM backup mode, make the following settings. (1) Create check data to verify after returning from RAM backup to normal mode whether the RAM data has been retained normally ((b) in Figure 17.3.3). (2) To materialize low-power operation, set all programmable input/output pins except port X for input mode (or for output mode, with pins outputting a low) ((c) in Figure 17.3.3). (3) Set port X for input mode (B and (d) in Figure 17.3.3). This causes the transistor's base voltage, IB, to go low, so that no current flows from the power supply to the VCC pin via the transistor (C in Figure 17.3.3). Consequently, the power to the VCC pin is shut off (D in Figure 17.3.3). Due to settings in (1) to (3), the voltage applied to the VDD pin becomes 3.3 V ± 10% and voltages applied to all other pins drop to 0 V, thus placing the M32R/ECU in RAM backup mode ((d) in Figure 17.2.3). RAM backup signal (Note 1) External circuit Port X IB Power supply for RAMDC IN Input OutputRegulator (3.3V system) OutputRegulator (5V system) OutputRegulator (3.3V system) VREFn SBI ADnINi M32R/ECU VDD VCCI AVCCnOSC-VCC VCCE (Note 3) (Note 2) 3.3V "L" "L" "L" DC "L" "L" B A 0V0V0V0V0V Example of RAM backup processing Generate RAM backup signal (Note 4) Create check data for backup RAM (a) (b) (d) RAM backup mode Set transistor’s base connecting pin (port X) for input mode (Note 5) (c)

17-8 32170/32174 Group User's Manual (Rev. 2.1) RAM BACKUP MODE Figure 17.3.4 Example of RAM Backup Sequence for Low-Power Operation

17.3.3 Precautions to Be Observed at Power-on

When changing port X from input mode to output mode after power-on, pay attention to the following. If port X is set for output mode while no data is set in the Port X Data Register, the port's initial output level is indeterminate. Therefore, be sure to set the output high level in the Port X Data Register before you set port X for output mode. Unless this method is followed, port output may go low at the same time port output is set after the clock oscillation has stabilized, causing the device to enter RAM backup mode. RESET SBI ADnINi VCCI, OSC-VCC VDD Oscillation stabilization time External input signal goes low RAM backup period Power on Port X Port input mode f (XIN) Port output setting (High level) VCCE, VREFn, AVCCn 3.3V 5.0V Port output setting (High level) External input signal goes high Oscillation stabilization time

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17.4 Exiting RAM Backup Mode (Wakeup)

Processing to exit RAM backup mode and return to normal operation is referred to as "wakeup processing." Figure 17.4.1 shows an example of wakeup processing. Wakeup processing is initiated by reset input. The following shows how to execute wakeup processing. (1) Reset the device ((a) in Figure 17.4.1). For details about reset, refer to Chapter 7, "Reset." (2) Set port X for output mode and output a high from the port ((b) in Figure 17.4.1).(Note) (3) Check the RAM contents against the check data created before entering RAM backup mode ((c) in Figure 17.4.1). (4) If the RAM contents and check data did not match when checked in (3), initialize the RAM ((d) in Figure 17.4.1). If the RAM contents and check data matched, use the retained data in the program. (5) After initializing each internal circuit ((e) in Figure 17.4.1), return the main routine ((f) in Figure 17.4.1). Note : For wakeup from power outage RAM backup mode, settings for port X are unnecessary. Figure 17.4.1 Wakeup Processing Note: For wakeup from power outage RAM backup mode, settings for port X are unnecessary. OK Error Check RAM contents against backup RAM check data Initialize RAM Example of wakeup processing Reset Set transistor’s base connecting pin (port X) for high-level output mode (Note) Initial each internal circuit To main routine (a) (b) (d) (c) (f) (e)

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18.1 Oscillator Circuit

18.2 Clock Generator Circuit

18-2 32170/32174 Group User's Manual (Rev. 2.1) OSCILLATION CIRCUIT Figure 18.1.1 Example of a System Clock Generating Circuit The M32R/ECU contains an oscillator circuit that supplies operating clocks for the CPU core, internal peripheral I/O, and internal memory. The frequency fed to the clock input pin (XIN) is multiplied by 4 by the internal PLL circuit to produce the CPU clock, which is the operating clock for the CPU core and internal memory. The frequency of this clock is divided by 2 in the subsequent circuit to produce the internal peripheral clock, which is the operating clock for the internal peripheral I/O.

18.1.1 Example of an Oscillator Circuit

A clock generating circuit can be configured by connecting a ceramic (or crystal) resonator between the XIN and XOUT pins external to the chip. Figure 18.1.1 below shows an example of a system clock generating circuit using a resonator connected external to the chip and an RC network connected to the PLL circuit control pin (VCNT). For constants Rf, CIN, COUT, and Rd, consult your resonator manufacturer to determine the appropriate values. When you use an externally sourced clock signal without using the internal oscillator circuit, connect the external clock signal to the XIN pin and leave the XOUT pin open. M32R/ECU OSCVCC XIN XOUTOSCVSS Rf Rd C IN C OUT VCNT BCLK / P70 C Oscillator circuit To internal peripheral clock PLL circuit 220pF (Note) 0.1µF1KΩ Oscillator module OSCVCC : 3.3 V power supply Note: allowable error ±10% To CPU clock (Note) (Note)

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18.1.2 System Clock Output Function

A clock whose frequency is twice the input frequency can be output from the BCLK pin. The BCLK pin is shared with port P70. When you use this pin to output the system clock, set the P7 Operation Mode Register (P7MOD)'s D8 bit to 1. Configuration of the P7 Operation Mode Register is shown below. I P7 Operation Mode Register (P7MOD) <Address: H'0080 0747> D 8 9 1 01 11 21 31 4 D 1 5 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD <When reset : H'00> D Bit Name Function R W (Port P70 operation mode) 1 : BCLK (Port P71 operation mode) ____ 1 : WAIT (Port P72 operation mode) ____ 1 : HREQ (Port P73 operation mode) ____ 1 : HACK (Port P74 operation mode) 1 : RTDTXD (Port P75 operation mode) 1 : RTDRXD (Port P76 operation mode) 1 : RTDACK (Port P77 operation mode) 1 : RTDCLK

18-4 32170/32174 Group User's Manual (Rev. 2.1) OSCILLATION CIRCUIT Figure 18.1.2 Oscillation Stabilization Time at Power-on

18.1.3 Oscillation Stabilization Time at Power-on

The oscillator circuit comprised of a ceramic (or crystal) resonator has a finite time after power-on at which its oscillation is instable. Therefore, create a certain amount of oscillation stabilization time that suits the oscillator circuit used. Figure 18.1.2 shows an oscillation stabilization time at power- on. RESET XIN Oscillation stabilization time OSC-VCC

18-5 32170/32174 Group User's Manual (Rev. 2.1) Figure 18.2.1 Configuration of the Clock Generator Circuit OSCILLATION CIRCUIT The clock generator supplies independent clocks to the CPU and internal peripheral circuits. XIN (8MHz - 10MHz) BCLK (16MHz - 20MHz) CPU clock (32MHz - 40MHz) 1/2 internal peripheral clock (8MHz - 10MHz)

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19.1 Outline of JTAG

19.2 Configuration of the JTAG

19.3 JTAG Registers

19.4 Basic Operation of JTAG

19.5 Boundary Scan Description

19.6 Precautions on Board Design

19.7 Processing Pins when Not

19-2 32170/32174 Group User's Manual (Rev. 2.1) The 32170/32174 contains a JTAG (Joint Test Action Group) interface based on IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1a-1993). This JTAG interface can be used as an input/output path for boundary-scan test (boundary-scan path). For details about IEEE 1149.1 JTAG test access ports, refer to the IEEE Std. 1149.1a-1993 documentation. The functions of JTAG interface related pins mounted on the 32170/32174 are shown below. Table 19.1.1 JTAG Pin Functions Type Symbol Pin Name I/O Function TAP JTCK Test clock Input Clock input to the test circuit. JTDI Test data input input Synchronous serial data input pin used to enter test instruction code and test data. This input is sampled on rising edges of JTCK. JTDO Test data output output Synchronous serial data output pin used to output test instruction code and test data. This signal changes state on falling edges of JTCK, and is output only in Shift-IR or Shift- DR state. JTMS Test mode select Input Test mode select input to control the test circuit's state transitions. This input is sampled on rising edges of JTCK. JTRST Test reset Input Active-low test reset input to initialize the test circuit asynchronously. To ensure that the test circuit is reset without fail, JTMS signal input must be held high while this signal changes state from low to high. Note: TAP = Test Access Port, a JTAG interface stipulated in IEEE 1149.1. JTAG (Note)

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19.2 Configuration of the JTAG Circuit

Figure 19.2.1 Configuration of the JTAG Circuit The 32170/32174's JTAG circuit consists of the following blocks:

• Instruction register to hold instruction codes which are fetched through the boundary-scan path
• A set of data registers which are accessed through the boundary-scan path
• Test access port (abbreviated TAP) controller to control the JTAG unit's state transitions
• Control logic to select input, output, etc. A configuration of the JTAG circuit is shown below. JTCK JTMS JTRST TAP controller Instruction register (6 bits) (JTAGIR) Decoder JTDO ID code register (JTAGIDR) Bypass register (JTAGBPR) Boundary-scan register (JTAGBSR)JTDI Data register set Output selection OutputselectionBuffer M32R/ECU

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19.3.1 Instruction Register (JTAGIR)

The Instruction Register (JTAGIR) is a 6-bit register to hold instruction code. This register is set in IR path sequence. The instructions set in this register determine the data register to be selected in the subsequent DR path sequence. When test is reset (to initialize the test circuit), the initial value of this register is b'000010 (IDCODE instruction). After a test reset, the IDCODE Register is selected as the data register until an instruction code is set by an external device. In "Capture-IR" state, this register always has b'110001 (fixed value) loaded into it. Therefore, when in "Shift-IR" state, no matter what value was set in this register, b'110001 is always output from the JTDO pin (sequentially beginning with LSB). However, this value normally is not handled as instruction code. Shown below is outside the scope of guaranteed operations. Note that if this operation is performed, the device may inadvertently handle b'110001 as instruction code, which makes it unable to operate normally. [Capture-IR] → [Exit1-IR] → [Update-IR] The 32170/32174's JTAG interface supports the following instructions:

• Three instructions stipulated as essential in IEEE 1149.1 (EXTEST, SAMPLE/PRELOAD, BYPASS)
• Device ID register access instruction (IDCODE) Table 19.3.1 JTAG Instruction List Instruction Code Abbreviation Operation b'000000 EXTEST Tests circuit/board-level connections outside the chip. b'000001 SAMPLE/PRELOAD Samples operating circuit status and outputs the sampled status from JTDO pin, while at the same time entering the data used for boundary-scan test from the JTDI pin and presets it in Boundary Scan Register. b'000010 IDCODE Selects ID Code Register and outputs device and manufacturer identification data from JTDO pin. b'111111 BYPASS Selects Bypass Register and inspects or sets data. Note 1: Do not set any other instruction code. Note 2: For details about "IR path sequence," "DR path sequence," "Test reset," "Capture-IR" state, "Shift-IR" state, "Exit1-IR" state, and "Update-IR" state, refer to Section 19.4.

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19.3.2 Data Registers

(1) Boundary Scan Register (JTAGBSR) The Boundary Scan Register is a 471-bit register used to perform boundary-scan test. Bits in this register are assigned to each pin on the 32170/32174. Connected between the JTDI and JTDO pins, this register is selected when issuing EXTEST or SAMPLE/PRELOAD instruction. In "Capture-DR" state, this register captures the status of input pins or internal logic output values. In "Shift-DR" state, while outputting the sampled value, it is used to set pin functions (input/output pin and tristate output pin direction) and output values by entering data for boundary-scan test. (2) Bypass Register (JTAGBPR) The Bypass Register is a 1-bit register used to bypass boundary-scan passes when the 32170/ 32174 is not the target of boundary-scan test. Connected between the JTDI and JTDO pins, this register is selected when issuing BYPASS instruction. This register when in "Capture-DR" state has b'0 (fixed value) loaded into it. (3) ID Code Register (JTAGIDR) The ID Code Register is a 32-bit register used to identify the device and manufacturer. It holds the following information:

• Version information (4 bits) : b'0000
• Part number (16 bits) : b'0011 0010 0010 0000
• Manufacturer ID (11 bits) : b'000 0001 1100 This register is connected between the JTDI and JTDO pins, and is selected when issuing IDCODE instruction. When in "Capture-DR" state, this register has the said IDCODE data loaded into it, which is output from the JTDO pin in "Shift_DR" state. This register is a read-only register, so that the data written from the JTDI pin during DR pass sequence is ignored. Therefore, make sure JTDI input = low during "Shift-DR" state. 03 4 1 9 2 0 3 0 3 1 Version Part number Manufacturer ID 1 4 bits 16 bits 11 bits Note : For details about "Capture-DR" and "Shift-DR" states, refer to Section 19.4.

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19.4.1 Outline of JTAG Operation

The instruction and data registers basically are accessed in the following three operations, which are performed based on state transitions of the TAP controller. The TAP controller changes state according to JTMS input, and generates control signals required for operation in each state.

• Capture operation The result of boundary-scan test or the fixed data defined for each register is sampled. As register operation, the input data is loaded into the shift register stage.
• Shift operation The register is accessed from outside through the boundary-scan path. The sampled value is output to an external device at the same time data is set from outside. As register operation, bits are shifted right between each shift register stage.
• Update operation The data set from outside during shift is driven. As register operation, the value set in the shift register stage is transferred to the parallel output stage. The JTAG interface undergoes transitions of internal state depending on JTMS input as it performs the following two operations. In either case, the operation basically is performed in order of Capture → Shift → Update.
• IR path sequence Instruction code is set in the instruction register to select the data register to be operated on in the subsequent DR path sequence.
• DR path sequence The selected data register is operated on to inspect or set data.

19-7 32170/32174 Group User's Manual (Rev. 2.1) JTAG The state transitions of the TAP controller and the basic configuration of the 32170/32174's JTAG related registers are shown below. Figure 19.4.2 Basic Configuration of JTAG Related Registers Note: Shown here is the basic configuration, and the configuration of DR and IR does not all have to be like this. Figure 19.4.1 TAP Controller State Transition Note: Values (0 and 1) in this diagram denote the state of JTMS input signal. Select-DR-Scan Test-Logic-Reset Run-Test/Idle Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR 1 0 Select-IR-Scan Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR 1 0 11 1 Data input G D T Q D T R Q "Shift-DR" or "Shift-IR" "Clock-DR" or "Clock-IR" "Update-DR" or "Update-IR" Test reset From preceding cell To next cell Data output Parallel output stage Shift register stageInput multiplexer

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19.4.2 IR Path Sequence

Instruction code is set in the Instruction Register (JTAGIR) to select the data register to be accessed in the subsequent DR path sequence. The IR path sequence is performed following the procedure described below. (1) Enter JTMS = high for a period of two JTCK cycles from "Run-Test/Idle" state to go to "Select-IR-Scan" state. (2) Set JTMS = low to go to "Capture-IR" state. At this time, b'110001 (fixed value) is set in the instruction register's shift register stage. (3) Subsequently, enter JTMS = low to go to "Shift-IR" state. In "Shift-IR" state, the value of the shift register stage is shifted right one bit every cycle, and the data b'110001 (fixed value) that was set in (2) is serially output from the JTDO pin. At the same time, the instruction code serially entered from the JTDI pin is set in the shift register stage bit by bit. Because instruction code is set in the instruction register which is comprised of 6 bits, the "Shift-IR" state continues for a period of 6 JTCK cycles. To stop the shift operation in the middle, go to "Pause-IR" state via temporarily "Exit1-IR" state (by setting JTMS input from high to low). Also, to return from "Pause-IR" state, go to "Shift-IR" state via temporarily "Exit1-IR" state (by setting JTMS input from high to low). (4) By setting JTMS = high, go from "Shift-IR" state to "Exit1-IR" state. This completes the shift operation. (5) Subsequently, enter JTMS = high to go to "Update-IR" state. In "Update-IR" state, the instruction code that was set in the instruction register's shift register stage is transferred to the instruction register's parallel output stage and, thus, JTAG instruction decoding begins. (6) Subsequently, enter JTMS = high to go to "Select-DR-Scan" state or JTMS = low to go to "Run-Test/Idle" state.

19-9 32170/32174 Group User's Manual (Rev. 2.1) JTAG Figure 19.4.3 IR Path Sequence JTCK Select-DR-ScanSelect-IR-Scan Capture-I R Shift-IR Exit1-IRUpdate-IR Run-Test/IdleRun-Test/Idl e Don’t CareDon ’t Care Instruction code (6 bits) 1 0 0 0 1 1 LSB value JTMS TAP state JTDI JTDO High impedance Shift output from the instruction register is fixed to b’110001. Finished storing instruction code in the instruction register’s shift register stage. Instruction code is set in the parallel output stage at fall of JTCK in "Update-IR" state. JTDI input is sampled at rise of JTCK in "Shift-IR" state. JTDO is output at fall of JTCK in "Shift-IR" state. MSB value High impedance

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19.4.3 DR Path Sequence

The data register that was selected during the IR path sequence prior to the DR path sequence is operated on to inspect or set data in it. The DR path sequence is performed following the procedure described below. (1) Enter JTMS = high for a period of one JTCK cycle from "Run-Test/Idle" state to go to "Select- DR-Scan" state. Which data register will be selected at this time depends on the instruction that was set during the IR path sequence performed prior to the DR path sequence. (2) Set JTMS = low to go to "Capture-DR" state. At this time, the result of boundary-scan test or the fixed data defined for each register is set in the data register's shift register stage. (3) Subsequently, enter JTMS = low to go to "Shift-DR" state. In "Shift-DR" state, the DR value is shifted right one bit every cycle, and the data that was set in (2) is serially output from the JTDO in. At the same time, the setup data serially entered from the JTDI pin is set in the data register's shift register stage bit by bit. By continuing the "Shift-DR" state as long as the number of bits of the selected data register (by entering JTMS = low), all bits of data can be set in and read out from the shift register stage. To stop the shift operation in the middle, go to "Pause-DR" state via temporarily "Exit1-DR" state (by setting JTMS input from high to low). Also, to return from "Pause-DR" state, go to "Shift-DR" state via temporarily "Exit1-DR" state (by setting JTMS input from high to low). (4) Set JTMS = high to go from "Shift-DR" state to "Exit2-DR" state. This completes the shift operation. (5) Subsequently, enter JTMS = high to go to "Update-DR" state. In "Update-DR" state, the data that was set in the data register's shift register stage is transferred to the parallel output stage and, thus, the setup data becomes ready for use. (6) Subsequently, enter JTMS = high to go to "Select-DR-Scan" state or JTMS = low to go to "Run-Test/Idle" state.

19-11 32170/32174 Group User's Manual (Rev. 2.1) JTAG Figure 19.4.4 DR Path Sequence Note: The shift operation of the data register for the shift register stage is right-shifted, therefore, the output from JTDO is from the LSB side. Input to JTDI starts from the value to be set in LSB side. JTCK Select-DR-Scan Capture-DR Shift-D R Exit1-DRUpdate-DRRun-Test/IdleRun-Test/Idl e Don’t CareDon ’t Care JTMS JTDI JTDO Finished storing setup data in the shift register stage of the selected data register. Setup data is set in the parallel output stage at fall of JTCK in "Update-DR" state. JTDI input is sampled at rise of JTCK in "Shift-DR" state. TAP state LSB value High impedance MSB value High impedance JTDO is output at fall of JTCK in "Shift-DR" state.

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19.4.4 Examining and Setting Data Registers

To inspect or set the data register, follow the procedure described below. (1) To access the test access port (JTAG) for the first time, enter test reset (to initialize the test circuit). Test reset can be entered by one of the following two methods:

• Pull JTRST pin input low
• Drive JTMS pin input high and enter JTCK for 5 cycles or more (2) Set JTMS = low to go to "Run-Test/Idle" state. To continue the idle state, hold JTMS input low. (3) Set JTMS = high to exit "Run-Test/Idle" state and perform IR path sequence. In IR path sequence, specify the data register you want to inspect or set. (4) Subsequently, perform DR path sequence. For the data register specified in IR path sequence, enter setup data from the JTDI pin and read out reference data from the JTDO pin. (5) If after DR path sequence is completed you want to proceed and perform IR path sequence or DR path sequence, enter JTMS = high to return to "Select-DR-Scan" state. If after a series of IR and DR path sequence processing is completed you want to wait for the next processing, enter JTMS = low to go to "Run-Test/Idle" state and retain the state.

19-13 32170/32174 Group User's Manual (Rev. 2.1) JTAG Figure 19.4.5 Continuous JTAG Access Note 1: The setup value for each register must be entered from the JTDI pin beginning with the LSB. Note 2: The value of each register is output from the JTDO pin beginning with the LSB. The JTDO pin outputs valid data in only "Shift-IR" state of IR path sequence and "Shift-DR" state of DR path sequence. In all other states, the JTDO pin is tristated (high impedance). Note 3: Data can only be read out from the data register which is selected by the instruction that was set in the immediately preceding IR path sequence. Output in the selected data register's shift register stage is the value that was sampled during "Capture-DR" state. Specify the data register you want to inspect or set. Test-Logic- Reset state Run-Test /Idle state IR path sequence TAP states Instruction code #0 Setup data JTDI (Note 1) Fixed value b’110001 (Note 3)JTDO (Note 2) Setup data is entered serially from JTDI. Reference data is serially output from JTDO. (1) Basic access Same data register can be operated on to inspect or set data continuously. (2) Continuous access to the same data register Specify the data register you want to inspect or set. DR path sequence Run-Test /Idle state IR path sequence DR path sequence Instruction code #1 Setup data Fixed value b’110001 (Note 3) Test-Logic- Reset state Run-Test /Idle state IR path sequence TAP states Instruction code #0 Setup data JTDI (Note 1) Fixed value b’110001 (Note 3)JTDO (Note 2) DR path sequence Run-Test /Idle state IR path sequence DR path sequence Setup data (Note 3) Setup data (Note 3)

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19.5 Boundary Scan Description Language

The Boundary Scan Description Language (abbreviated BSDL) is stipulated in supplements to "Standard Test Access Port and Boundary-Scan Architecture" of IEEE 1149.1-1990 and IEEE 1149.1a-1993. BSDL is a subset of IEEE 1076-1993 Standard VHSIC Hardware Description Language (VHDL). BSDL helps to precisely describe the functions of standard-compliant components to be tested. For package connection test, this language is used by Automated Test Pattern Generation tools, and for synthesized test logic and verification, it is used by Electronic Design Automation tools. BSDL provides powerful extended functions usable in internal test generation and necessary to write hardware debug and diagnostics software. The primary section of BSDL contains statements of logical port description, physical pin map, instruction set, and boundary register description.

• Logical port description The logical port description assigns meaningful symbol names to each pin on the chip. This determines the logic type of input, output, input/output, buffer, or link of each pin that defines the logical direction of signal flow.
• Physical pin map The physical pin map correlates the chip's logical ports to the physical pins on each package. Use of separate names for each map makes it possible to define multiple physical pin maps in one BSDL description.
• Instruction set statement The instruction set statement writes bit patterns to be shifted in into the chip's instruction register. This bit pattern is necessary to place the chip into each test mode defined in standards. It is also possible to write instructions exclusive to the chip.
• Boundary register description The boundary register description is a list of boundary register cells or shift stages. Each cell is assigned a separate number. The cell with number 0 is located closest to the test data output (JTDO) pin, and the cell with the largest number is located closest to the test data input (JTDI) pin. Cells also contain related other information which includes cell type, logical port corresponding to cell, logical function of cell, safety value, control cell number, disable value, and result value. Note: Information on the Boundary Scan Description Language (BSDL) can be downloaded from the M32R family application engineering data in “Mitsubishi Microcomputer Technology Home Page.” The URL address of this home page is shown below.
• http://www.infomicom.maec.co.jp/

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19.6 Precautions on Board Design when Using JTAG

The JTAG pins require that wiring lengths be matched during board design in order to accomplish fast, highly reliable communication with JTAG tools. An example of how to process pins when using JTAG tools is shown below. Figure 19.6.1 Example for Processing Pins when Using JTAG Tools (for the 240QFP) M32R/ECU JTDI JTMS JTCK JTRST User board JTAG tool Make sure wiring lengths are the equal, and avoid bending wiring as much as possible. Also, do not use through holes with in this wiring. JTDO 33Ω VCCE(5V) 2KΩ 10KΩ 0.1 F SDI connector (JTAG connector) Power TDI TMS TCK TRST TDO GND 33Ω 10KΩ 33Ω 10KΩ 33Ω 10KΩ 33Ω Note 1: Only if the JTRST pin is firmly tied to ground, it dosn’t matter whether the JTDO, JTDI, JTMS, and JTCK pins are pulled high or pulled low. Note 2: Even when not using JTAG tools, always be sure to process each pin. The same pulldown/pullup resistance values as when using JTAG tools may be used without causing any problem.

19-16 32170/32174 Group User's Manual (Rev. 2.1) Figure 19.6.2 Precautions to Be Observed when Connecting JTAG Tool (when Using the 255FBGA) JTAG TRDATA[0:7] EVENT[0:1] DBI TRCLK TRSYNC When connecting emulator TRDATA[0:7] EVENT[0:1] M32R/ECU JTDI JTMS JTCK JTRST When connecting JTAG tool JTDO 33Ω VCCE(5V) 2KΩ 10KΩ 0.1 F SDI connector (JTAG connector) Power TDI TMS TCK TRST TDO GND 33Ω 10KΩ 33Ω 10KΩ 33Ω 10KΩ 33Ω User board 33Ω 33Ω 33Ω 33Ω 33Ω 10KΩ Make sure wiring lengths are the same, and avoid bending wires as much as possible. Also, do not use through-holes within wiring. Note 1: Only if the JTRST pin is firmly tied to ground, it dosn’t matter whether the JTDO, JTDI, JTMS, and JTCK pins are pulled high or pulled low. Note 2: Even when not using JTAG tools, always be sure to process each pin. The same pulldown/pullup resistance values as when using JTAG tools may be used without causing any problem.

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19.7 Processing Pins when Not Using JTAG

The diagram below shows how to process JTAG pins when not using these pins (i.e. for boards that do not have pins/connectors connecting to JTAG tools). M32R/ECU JTDI JTMS JTCK JTRST User board JTDO VCCE(5V) 0— 100KΩ 0— 100KΩ 0— 100KΩ 0— 100KΩ 0— 100KΩ Note: Only if the JTRST pin is firmly tied to ground, it dosn’t matter whether the JTDO, JTDI, JTMS, and JTCK pins are pulled high or pulled low. Figure 19.7.1 Processing Pins when Not Using JTAG (for 240QFP)

19-18 32170/32174 Group User's Manual (Rev. 2.1) JTAG VCCE(5V) 0— 100K 0— 100KΩ DBI TRCLK TRSYNC TRDATA[0:7] EVENT[0:1] 0— 100KΩ 0— 100KΩ 0— 100KΩ 0— 100KΩ ( OPEN ) ( OPEN ) ( OPEN ) ( OPEN ) Note: Only if the JTRST pin is firmly tied to ground, it dosn’t matter whether the JTDO, JTDI, JTMS, and JTCK pins are pulled high or pulled low. Figure 19.7.2 Processing Pins when Not Using JTAG (for 255FBGA)

20.1 Configuration of the Power

20.2 Power-On Sequence

20.3 Power-Shutdown Sequence

20-2 32170/32174 Group User's Manual (Rev. 2.1)

20.1 Configuration of the Power Supply Circuit

To accomplish fast operation and low power consumption, the M32R/ECU is designed in such a way that its external interface circuits operate with a 5 V or 3.3 V power supply, and that all other circuits operate with 3.3 V. Therefore, control timings of 5 V and 3.3 V power supplies must be taken into consideration when designing the application circuit. Table 20.1.1 Power Supply Functions Type of Power Supply Pin name Function

5.0 V VCCE Power supply fed to external I/O ports

AVCC0, AVCC1 Power supply for the A-D converter VREF0, VREF1 Reference voltage for the A-D converter

3.3 V VCCI Power supply fed to the internal logic

FVCC Power supply for internal flash memory VDD Power supply for internal RAM backup OSC-VCC Power supply for the oscillator and PLL circuits Figure 20.1.1 Configuration of the Power Supply Circuit (when VCC=5V) POWER-ON/POWER-SHUTDOWN SEQUENCE Oscillator and PLL circuits

20-3 32170/32174 Group User's Manual (Rev. 2.1) POWER-ON/POWER-SHUTDOWN SEQUENCE 3.3V power supply I/O control circuit A-D converter circuit CPU Peripheral circuit Flash RAM Oscillator and PLL circuits Figure 20.1.2 Configuration of the Power Supply Circuit (when VCC=3.3V)

20-4 32170/32174 Group User's Manual (Rev. 2.1)

20.2.1 Power-On Sequence When Not Using RAM Backup

The diagram below shows a power-on sequence (5.0 V, 3.3 V power supply) of the M32R/ECU when not using RAM backup. POWER-ON/POWER-SHUTDOWN SEQUENCE (a): Turn on the 3.3 V power supply after turning on the 5 V power supply. (b): After turning on all power supplies and holding the RESET pin low for an oscillation stabilization time, release the RESET pin input back high (to deactivate reset). Note: Power-on limitations

• VDD OSC-VCC VCCI FVCC
• VCCE VCCI, FVCC, OSC-VCC Figure 20.2.1 Power-On Sequence When Not Using RAM Backup (when VCC=5V) VCCE AVCC0, AVCC1 VREF0, VREF1 RESET VDD VCCI FVCC OSC-VCC 3.3V 3.3V 3.3V 3.3V (b) (a) Note: Inversion of phases may not cause a problem providing the difference in voltage levels (about 0.1 to 0.2 V in a transient state) is within the safe region where current inflow due to diode characteristics do not occur. For stable operation, however, make sure the recommended operating conditions are met when designing the application circuit.

20-5 32170/32174 Group User's Manual (Rev. 2.1) POWER-ON/POWER-SHUTDOWN SEQUENCE (a) VCCE AVCC0, AVCC1 VREF0, VREF1 RESET VDD VCCI FVCC OSC-VCC 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V (a): After turning on all power supplies and holding the RESET pin low for an oscillation stabilization time, release the RESET pin input back high (to deactivate reset). Note: Power-on limitations

• VDD OSC-VCC VCCI FVCC
• VCCE VCCI, FVCC, OSC-VCC Figure 20.2.2 Power-On Sequence When Not Using RAM Backup (when VCC=3.3V)

20-6 32170/32174 Group User's Manual (Rev. 2.1)

20.2.2 Power-On Sequence When Using RAM Backup

The diagram below shows a power-on sequence (5.0 V, 3.3 V power supply) of the M32R/ECU when using RAM backup. Figure 20.2.3 Power-On Sequence When Using RAM Backup (when VCC=5V) (a): Turn on the 3.3 V power supply after turning on the 5 V power supply. (b): After turning on all power supplies and holding the RESET pin low for an oscillation stabilization time, release the RESET pin input back high (to deactivate reset). Note: Power-on limitations

• VDD OSC-VCC VCCI FVCC
• VCCE VCCI, FVCC, OSC-VCC VCCE AVCC0, AVCC1 VREF0, VREF1 RESET VDD VCCI FVCC OSC-VCC 3.3V 3.3V 3.3V 3.3V 2.0V (b) (a) POWER-ON/POWER-SHUTDOWN SEQUENCE

Note: Inversion of phases may not cause a problem providing the difference in voltage levels (about 0.1 to 0.2 V in a transient state) is within the safe region where current inflow due to diode characteristics do not occur. For stable operation, however, make sure the recommended operating conditions are met when designing the application circuit.

20-7 32170/32174 Group User's Manual (Rev. 2.1) POWER-ON/POWER-SHUTDOWN SEQUENCE (a) VCCE AVCC0, AVCC1 VREF0, VREF1 RESET VDD VCCI FVCC OSC-VCC 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 2.0V (a): After turning on all power supplies and holding the RESET pin low for an oscillation stabilization time, release the RESET pin input back high (to deactivate reset). Note: Power-on limitations

• VDD OSC-VCC VCCI FVCC
• VCCE VCCI, FVCC, OSC-VCC Figure 20.2.4 Power-On Sequence When Using RAM Backup (when VCC=3.3V)

20-8 32170/32174 Group User's Manual (Rev. 2.1)

20.3.1 Power-Shutdown Sequence When Not Using RAM Backup

The diagram below shows a power-shutdown sequence (5.0 V, 3.3 V power supply) of the M32R/ ECU when not using RAM backup. (a): Pull the RESET pin input low. (b): Turn off the 5 V and the 3 V power supply after the RESET pin goes low. Note: Power-shutdown requirements

• VDD VCCI FVCC
• OSC-VCC VCCI Figure 20.3.1 Power-Shutdown Sequence When Not Using RAM Backup (when VCC=5V) POWER-ON/POWER-SHUTDOWN SEQUENCE

AVCC0, AVCC1 VREF0, VREF1 RESET VDD VCCI FVCC OSC-VCC 3.3V 3.3V 3.3V 3.3V (b) (a) Note: Inversion of phases may not cause a problem providing the difference in voltage levels (about 0.1 to 0.2 V in a transient state) is within the safe region where current inflow due to diode characteristics do not occur. For stable operation, however, make sure the recommended operating conditions are met when designing the application circuit.

20-9 32170/32174 Group User's Manual (Rev. 2.1) POWER-ON/POWER-SHUTDOWN SEQUENCE AVCC0, AVCC1 VREF0, VREF1 RESET VDD VCCI FVCC OSC-VCC 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V (a) (a): Turn off the power supply after the RESET pin goes low. Note: Power-shutdown requirements

• VDD VCCI FVCC
• OSC-VCC VCCI Figure 20.3.2 Power-Shutdown Sequence When Not Using RAM Backup (when VCC=3.3V)

20-10 32170/32174 Group User's Manual (Rev. 2.1)

20.3.2 Power-Shutdown Sequence When Using RAM Backup

The diagram below shows a power-shutdown sequence (5.0 V, 3.3 V power supply) of the M32R/ ECU when using RAM backup. Figure 20.3.3 Power-Shutdown Sequence When Using RAM Backup(when VCC=5V) VCCE AVCC0, AVCC1 VREF0, VREF1 P72 / HREQ RESET VDD VCCI FVCC OSC-VCC 3.3V 3.3V 3.3V 3.3V 2.0V (b) (a) (c) (c) (d) (a): Pull the HREQ pin input low to halt the CPU at end of bus cycle. Or disable RAM access in software. The M32R/ECU allows P72 to be used as HREQ irrespective of its operation mode. (b): With the CPU halted, pull the RESET pin input low. Or while RAM access is disabled, pull the RESET pin input low. (c): Turn off the 5 V and the 3.3 V power supply after the RESET pin goes low. (d): Reduce the VDD voltage from 3.3 V to 2.0 V as necessary. Note: Power-shutdown requirements

• VDD VCCI FVCC
• OSC-VCC VCCI POWER-ON/POWER-SHUTDOWN SEQUENCE

Note: Inversion of phases may not cause a problem providing the difference in voltage levels (about 0.1 to 0.2 V in a transient state) is within the safe region where current inflow due to diode characteristics do not occur. For stable operation, however, make sure the recommended operating conditions are met when designing the application circuit.

20-11 32170/32174 Group User's Manual (Rev. 2.1) POWER-ON/POWER-SHUTDOWN SEQUENCE (a) (b) VCCE AVCC0, AVCC1 VREF0, VREF1 P72 / HREQ RESET VDD VCCI FVCC OSC-VCC 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V (c) (c) 0V (d) 2.0V (a): Pull the HREQ pin input low to halt the CPU at end of bus cycle. Or disable RAM access in software. The M32R/ECU allows P72 to be used as HREQ irrespective of its operation mode. (b): With the CPU halted, pull the RESET pin input low. Or while RAM access is disabled, pull the RESET pin input low. (c): Turn off the power supply after the RESET pin goes low. (d): Reduce the VDD voltage from 3.3 V to 2.0 V as necessary. Note: Power-shutdown requirements

• VDD VCCI FVCC
• OSC-VCC VCCI Figure 20.3.4 Power-Shutdown Sequence When Using RAM Backup(when VCC=3.3V)

20-12 32170/32174 Group User's Manual (Rev. 2.1) Figure 20.3.5 Microcomputer Ready to Run State 1 Figure 20.3.6 Microcomputer Ready to Run State 2 POWER-ON/POWER-SHUTDOWN SEQUENCE 3.3V power supply I/O control circuit A-D converter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 3.3V OSC-VCC FVCC VDD VCCI AVCC VCCE M32R/ECU 3.3V power supply I/O control circuit A-D converter circuit CPU Peripheral circuit Flash RAM Oscillator and PLL circuit 3.3V

20-13 32170/32174 Group User's Manual (Rev. 2.1) POWER-ON/POWER-SHUTDOWN SEQUENCE Figure 20.3.7 CPU Reset State 1 OSC-VCC FVCC VDD VCCI AVCC VCCE M32R/ECU I/O control circuit A-D converter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 3.3V 5V power supply 3.3V power supply Figure 20.3.8 CPU Reset State 2 OSC-VCC FVCC VDD VCCI AVCC VCCE M32R/ECU 3.3V power supply I/O control circuit A-D converter circuit CPU Peripheral circuit Flash RAM Oscillator and PLL circuit 3.3V

20-14 32170/32174 Group User's Manual (Rev. 2.1) Figure 20.3.9 CPU Halt State 1 Figure 20.3.10 CPU Halt State 2 POWER-ON/POWER-SHUTDOWN SEQUENCE Oscillator and PLL circuits 5V power supply 3.3V power supply OSC-VCC FVCC VDD VCCI AVCC VCCE M32R/ECU 5V power supply 3.3V power supply I/O control circuit A-D converter circuit CPU Peripheral circuit Flash RAM Oscillator and PLL circuit 3.3V

20-15 32170/32174 Group User's Manual (Rev. 2.1) OSC-VCC FVCC VDD VCCI AVCC VCCE M32R/ECU 3.3V-2.0V I/O control circuit A-D converter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 5V power supply 3.3V power supply POWER-ON/POWER-SHUTDOWN SEQUENCE Figure 20.3.11 SRAM Data Backup State 1 Figure 20.3.12 SRAM Data Backup State 2 OSC-VCC FVCC VDD VCCI AVCC VCCE M32R/ECU 3.3V power supply I/O control circuit A-D converter circuit CPU Peripheral circuit Flash RAM Oscillator and PLL circuit 3.3V-2.0V

20-16 32170/32174 Group User's Manual (Rev. 2.1) POWER-ON/POWER-SHUTDOWN SEQUENCE

• This is a blank page.*

21.1 Electrical Characteristics

(VCCE = 5V)

21.2 Electrical Characteristics

(VCCE = 3.3V)

21.3 AC Characteristics

21-2 32170/32174 Group User's Manual (Rev. 2.1) Ta=-40 to 85oC Ta=-40 to 125oC Symbol Parameter Condition Unit VCCI V VDD RAM Power Supply Voltage V AVCC Analog Power Supply Voltage VOSC-VCC PLL Power Supply Voltage V VREF Analog Reference Voltage V FVCC Flash Power Supply Voltage V VI Xin, VCNT VO Pd Power Dissipation mW TOPR Operating Ambient Temperature (Note) oC Tstg Storage Temperature oC V Internal Logic Power Supply Voltage VDD VCCI FVCC=OSC-VCC -0.3 to 4.2 VCCE External I/O Buffer VoltageVCCE AVCC VREF Xout -0.3 to 6.5 -40 to 125 -65 to 150 -0.3 to OSC-VCC+0.3 -0.3 to VCCE+0.3 -0.3 to OSC-VCC+0.3 600 -0.3 to VCCE+0.3 V V Other Other -0.3 to 4.2 -0.3 to 4.2 -0.3 to 4.2 -0.3 to 6.5 -0.3 to 6.5 Rated Value mW500 VDD VCCI FVCC=OSC-VCC VDD VCCI FVCC=OSC-VCC VDD VCCI FVCC=OSC-VCC VCCE AVCC VREF VCCE AVCC VREF

ELECTRICAL CHARACTERISTICS

21.1 Electrical Characteristics (VCCE = 5V)

21.1.1 Absolute Maximum Ratings

Absolute Maximum Ratings (Guaranteed for Operation at -40 to 125°C) Note: This does not guarantee that the device can operate continuously at 125°C. If you are considering the use of this product in 125°C application, please consult Mitsubishi.

21-3 32170/32174 Group User's Manual (Rev. 2.1)

21.1.2 Recommended Operating Conditions

Recommended Operating Conditions (Referenced to VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Note 1: Subject to conditions VCCE AVCC VREF. Note 2: Subject to conditions VDD VCCI FVCC = OSC-VCC Note 3: Make sure the total (peak) output current of ports is | ports P0 + P1 | 80 mA | ports P2 + P3 | 80 mA | ports P4 + P15 | 80 mA | ports P6 + P7 | 80 mA | ports P8 + P20 + P22 | 80 mA | ports P9 + P11 | 80 mA | ports P12 + P13 + P14 | 80 mA | ports P16 + P17 | 80 mA | ports P18 + P19 | 80 mA Note 4: The average output current is a value averaged during a 100 ms period. Symbol Parameter Rated Value Unit VCCE External I/O Buffer Power Supply Voltage (Note1) V VDD RAM Power Supply Voltage (Note2) AVCC Analog Power Supply Voltage (Note1) VREF Analog Reference Voltage (Note1) VIH Input High Voltage Min. Typ. Max. VIL Input Low Voltage IOH(peak) IOH(avg) IOL(peak) IOL(avg) mA mA mA mA MHzf(XIN) FVCC Flash Power Supply Voltage (Note2) PLL Power Supply Voltage (Note2)OSC-VCC VCCI Internal Logic Power Supply Voltage (Note2) 4.5 5.0 5.5 3.0 3.3 3.6 3.3 5.0 3.3 5.0 Ports P0, P1 (external extension/ processor mode only), WAIT 0.8VCCE VCCE 0.43VCCE VCCE Ports P0—P22, RESET, MOD0, MOD1, FP 0.2VCCE0 0.16VCCEPorts P0, P1 (external extension/ processor mode only), WAIT Low State Peak Output Current P0— P22 (Note 3) External Clock Input Frequency 5 -10 3.3 V V V V V V V V V V Ports P0—P22, RESET, MOD0, MOD1, FP 3.0 3.0 5.5 3.6 High State Peak Output Current P0— P22 (Note 3) CL Output Load Capacitance

80 PFJTCK,JTDI,JTMS,

JTDO,JTRST Other than above 50 PF High State Average Output Current P0— P22 (Note4) Low State Average Output Current P0— P22 (Note 4) 3.0 4.5 3.6 3.6 5.5 4.5

21-4 32170/32174 Group User's Manual (Rev. 2.1) Recommended Operating Conditions (Referenced to VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Note 1: Subject to conditions VCCE AVCC VREF. Note 2: Subject to conditions VDD VCCI FVCC = OSC-VCC Note 3: Make sure the total (peak) output current of ports is | ports P0 + P1 | 80 mA | ports P2 + P3 | 80 mA | ports P4 + P15 | 80 mA | ports P6 + P7 | 80 mA | ports P8 + P20 + P22 | 80 mA | ports P9 + P11 | 80 mA | ports P12 + P13 + P14 | 80 mA | ports P16 + P17 | 80 mA | ports P18 + P19 | 80 mA Note 4: The average output current is a value averaged during a 100 ms period. Symbol Parameter Rated Value Unit VCCE External I/O Buffer Power Supply Voltage (Note 1) V VDD RAM Power Supply Voltage (Note 2) AVCC Analog Power Supply Voltage (Note 1) VREF Analog Reference Voltage (Note 1) VIH Input High Voltage Min. Typ. Max. VIL Input Low Voltage IOH(peak) IOH(avg) IOL(peak) IOL(avg) mA mA mA mA MHzf(XIN) FVCC Flash Power Supply Voltage (Note 2) PLL Power Supply Voltage (Note 2)OSC-VCC VCCI Internal Logic Power Supply Voltage (Note 2) 4.5 5.0 5.5 3.0 3.3 3.6 3.3 5.0 3.3 5.0 Ports P0, P1 (external extension/ processor mode only), WAIT 0.8VCCE VCCE 0.43VCCE VCCE Ports P0— P22, RESET, MOD0, MOD1, FP 0.2VCCE0 0.16VCCEPorts P0, P1 (external extension/ processor mode only), WAIT Low State Peak Output Current P0— P22 (Note 3) External Clock Input Frequency 5 -10 3.3 V V V V V V V V V V Ports P0— P22, RESET, MOD0, MOD1, FP 3.0 3.0 5.5 3.6 High State Peak Output Current P0— P22 (Note 3) CL Output Load Capacitance JTDO,JTRST Other than above 50 PF High State Average Output Current P0— P22 (Note 4) Low State Average Output Current P0— P22 (Note 4) 3.0 4.5 3.6 3.6 5.5 4.5

21-5 32170/32174 Group User's Manual (Rev. 2.1)

21.1.3 DC Characteristics

21.1.3.1 Electrical Characteristics

(1) Electrical characteristics when f(XIN) = 10 MHz (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) Note 1: Total current when VCCE = AVCC = VREF in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. Note 2: Total current when VCCI = VDD = FVCC = OSC-VCC in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. Note 3: All these pins except RESET serve dual-functions. Note 4: The HREQ pin serves dual-functions. ICC-5V 5 V power supply (Note 1) 100 2000 f(XIN)=10.0MHz, When reset Ta=25oC Ta=85oC IDDhold See RAM retention power supply current characteristic graph 11 0 ICCI-3V 3.3 V power supply (Note 2) 75 125 VOH Output High Voltage V VDD RAM Retention Power Supply Voltage V IIH µA IIL VOL Output Low Voltage V VCCE+0.2 ×IOH(mA) 0.09×IOL (mA) VCCI IOH -5mA IOL 5mA VI=VCCE VI=0V 3.0 2.0 High State Input Current Low State Input Current 3.6 5 µA VCCE Symbol Parameter Rated Value Unit Min. Typ. Max. Condition V VT+ — VT- Hysteresis (Note 3) ADTRG, RTDCLK, RTDRXD, SCLKI0,1,2,3, RXD0, 1,2,3,4,5, TCLK3 — 0, JTMS,JTRST, JTDI, TIN0— 33, RESET, FP, MOD0,1 1.0 VCCE=5V VT+ — VT- Hysteresis (Note 4) SBI, HREQ VCCE=5V 0.3 V µA mA mA f(XIN)=10.0MHz, When operating RAM Retention Power Supply Current When operating When back-up f(XIN)=10.0MHz, When reset f(XIN)=10.0MHz, When operating

21-6 32170/32174 Group User's Manual (Rev. 2.1) (2) Electrical characteristics of each power supply pin when f(XIN) = 10 MHz (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 85°C Unless Otherwise Noted) IVREF mA mA ICCE VCCE power supply current when operating f(XIN)=10.0MHZ ICCI OSC-ICC IDD 35 IAVCC mA mA mA 120 50FICC mA VCCI power supply current when operating OSC-VCC power supply current when operating FVCC power supply current when operating (Note 1) VDD power supply current when operating (Note 2) AVCC power supply current when operating VREF power supply current Symbol Rated Value Unit Min. Typ. Max. Condition f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ f(XIN)=10.0MHZ Parameter Note 1: Maximum value including currents during program/erase operation. Note 2: Maximum value including cases where the program is executed in RAM.

21-7 32170/32174 Group User's Manual (Rev. 2.1) (3) Electrical characteristics when f(XIN) = 8 MHz (Referenced to VCCE = 5 V ± 10%, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Note 1: Total current when VCCE = AVCC = VREF in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. Note 2: Total current when VCCI = VDD = FVCC = OSC-VCC in single-chip mode. See the next page for the rated values of power supply current on each power supply pin. Note 3: All these pins except RESET serve dual-functions. Note 4: The HREQ pin serves dual-functions. ICC-5V 5 V power supply (Note 1) 100 7500 f(XIN)=8.0MHz, When reset Ta=25oC Ta=125oC IDDhold See RAM retention power supply current characteristic graph 11 0 ICCI-3V 3.3 V power supply (Note 2) 60 110 VOH Output High Voltage V VDD RAM Retention Power Supply Voltage V IIH µA IIL VOL Output Low Voltage V VCCE+0.2 ×IOH(mA) 0.09×IOL (mA) VCCI IOH -5mA IOL 5mA VI=VCCE VI=0V 3.0 2.0 High State Input Current Low State Input Current 3.6 5 µA VCCE Symbol Parameter Rated Value Unit Min. Typ. Max. Condition V VT+ — VT- Hysteresis (Note 3) ADTRG, RTDCLK, RTDRXD, SCLKI0,1,2,3, RXD0, 1,2,3,4,5, TCLK3 — 0, JTMS,JTRST, JTDI, TIN0— 33, RESET, FP, MOD0,1 1.0 VCCE=5V VT+ — VT- Hysteresis (Note 4) SBI, HREQ VCCE=5V 0.3 µA mA mA RAM Retention Power Supply Current f(XIN)=8.0MHz, When operating When operating When back-up f(XIN)=8.0MHz, When reset f(XIN)=8.0MHz, When operating V

21-8 32170/32174 Group User's Manual (Rev. 2.1) (4) Electrical characteristics of each power supply pin when f(XIN) = 8 MHz (Referenced to VCCE = 5 V ± 0.5V, VCCI = 3.3 V ± 0.3 V, Ta = -40 to 125°C Unless Otherwise Noted) Note 1: Maximum value including currents during program/erase operation. Note 2: Maximum value including cases where the program is executed in RAM. IVREF mA mA ICCE VCCE power supply current when operating f(XIN)=8.0MHZ ICCI OSC-ICC IDD 30 IAVCC mA mA mA 105 50FICC mA VCCI power supply current when operating OSCVCC power supply current when operating FVCC power supply current when operating (Note 1) VDD power supply current when operating (Note 2) AVCC power supply current when operating VREF power supply current Symbol Rated Value Unit Min. Typ. Max. ConditionParameter f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ f(XIN)=8.0MHZ RAM retention power supply current in a standard sample (reference value) 100 1000 1 1.5 Ta=25 o C Ta=85 o C Ta=125 o C IDD [ µA] VDD [V] 34 3.62

21-9 32170/32174 Group User's Manual (Rev. 2.1) VCCI(V) ICCI(mA) °C8MHz:25 °C90 °C110 °C130 °C10MHz:25 °C90 °C110 °C130 Standard sample’s ICCI-3V temperature characteristics (when operating: f = 8 MHz, 10 MHz) Note: VCCI = VDD = FVCC = OSCVCC, VCCE = AVCC = 5.0V Standard sample’s ICCI-3V temperature characteristics (when reset: f = 8 MHz, 10 MHz) Note: VCCI = VDD = FVCC = OSCVCC, VCCE = AVCC = 5.0V VCCI(V) ICCI(mA) °C8MHz:25 °C90 °C110 °C130 °C10MHz:25 °C90 °C110 °C130

21-10 32170/32174 Group User's Manual (Rev. 2.1)

21.1.3.2 Flash Related Electrical Characteristics

Flash Related Electrical Characteristics (Referenced to VCCE = 5 V ± 0.5 V, VCCI = 3.3 V ± 0.3 V Unless Otherwise Noted) Symbol Parameter Rated Value Unit Ifvcc1 FVCC Power Supply Current (when Programming) mA lfvcc2 mA Min. Typ. Max. Condition Flash Rewrite Ambient TemperatureTopr 07 0 o C cycle Rewrite Durabillity 100 times tPRG tBERS Program Time 8 120 600 ms ms

1 Page

1 Block

(when Erasing) Block Erase Time

21-11 32170/32174 Group User's Manual (Rev. 2.1)

21.1.4 A-D Conversion Characteristics

A-D Conversion Characteristics (Referenced to AVCC = VREF = VCCE = 5.12 V, Ta = -40 to 85°C, f(XIN) = 10.0 MHz Unless Otherwise Noted) Note 1:The nonlinearity error refers to a deviation from ideal conversion characteristics after the offset/ full-scale errors have been adjusted to 0. When AVCC = VREF = 5.12 V, 1 LSB = 5 mV. Note 2:This refers to input leakage current on AN0-AN15 when the A-D converter remains idle. Input voltage condition: 0 ANi AVCC. Temperature condition: -40 to 85°C. A-D Conversion Characteristics (Referenced to AVCC = VREF = VCCE = 5.12 V, Ta = -40 to 125°C, f(XIN) = 8.0 MHz Unless Otherwise Noted) Symbol Parameter Rated Value Unit — Resolution Bits Absolute Accuracy (Note 1) LSB MIN TYP MAX Condition TCONV Conversion Time 14950 IIAN Analog Input Leakage Current µA-5 5(Note 2) 8650 VREF=VCC During nomal mode During double- speed mode ns Note 1:The nonlinearity error refers to a deviation from ideal conversion characteristics after the offset/ full-scale errors have been adjusted to 0. When AVCC = VREF = 5.12 V, 1 LSB = 5 mV. Note 2:This refers to input leakage current on AN0-AN15 when the A-D converter remains idle. Input voltage condition: 0 ANi AVCC. Temperature condition: -40 to 125°C. Symbol Parameter Rated Value Unit — Resolution Bits Absolute Accuracy (Note 1) LSB MIN TYP MAX Condition TCONV Conversion Time 18687.5 IIAN Analog Input Leakage Current µA-5 5(Note 2) 10812.5 VREF=VCC During nomal mode During double- speed mode ns

21-12 32170/32174 Group User's Manual (Rev. 2.1) 21.2 ELECTRICAL CHARACTERISTICS (VCCE = 3.3V)

21.2.1 Absolute Maximum Ratings

Absolute Maximum Ratings (Guaranteed for Operation at -40 to 125°C) Ta=-40 to 85oC Ta=-40 to 125oC Symbol Parameter Condition Unit VCCI V VDD RAM Power Supply Voltage V AVCC Analog Power Supply Voltage VOSC-VCC PLL Power Supply Voltage V VREF Analog Reference Voltage V FVCC Flash Power Supply Voltage V VI Xin, VCNT VO Pd Power Dissipation mW TOPR Operating Ambient Temperature (Note) oC Tstg Storage Temperature oC V Internal Logic Power Supply Voltage VDD VCCI FVCC=OSC-VCC -0.3 to 4.2 VCCE External I/O Buffer VoltageVCCE AVCC VREF Xout -0.3 to 6.5 -40 to 125 -65 to 150 -0.3 to OSC-VCC+0.3 -0.3 to VCCE+0.3 -0.3 to OSC-VCC+0.3 600 -0.3 to VCCE+0.3 V V Other Other -0.3 to 4.2 -0.3 to 4.2 -0.3 to 4.2 -0.3 to 6.5 -0.3 to 6.5 Rated Value mW500 VDD VCCI FVCC=OSC-VCC VDD VCCI FVCC=OSC-VCC VDD VCCI FVCC=OSC-VCC VCCE AVCC VREF VCCE AVCC VREF Note: This does not guarantee that the device can operate continuously at 125°C. If you are considering the use of this product in 125°C application, please consult Mitsubishi. 21.2 Electrical Characteristics (VCCE = 3.3V)

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