32172

32172 RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

Before using this material, please visit the above website to confirm that this is the most current document available. Rev. 1.0 Revision date: Oct. 5, 2001 Mitsubishi 32-bit RISC Single-chip Microcomputers M32R Family M32R/ECU Series Group User’s Manual 3217232173

Keep safety first in your circuit designs! Notes regarding these materials

• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap.
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Rev. Date Description Page Summary REVISION HISTORY 32172/32173 GROUP USER’S MANUAL 1.0 10/5/2001 - First edition issued

How to read internal I/O register tables ➀ Bit Numbers: Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the registers located at even addresses are D0-D7, and those at odd addresses are D8-D15. ➁ State of Register at Reset: Represents the initial state of each register immediately after reset with hexadecimal numbers (undefined bits after reset are indicated each in column ➂ .) ➂ At read: ... read enabled ? ... read disabled (read value invalid) 0 ... Read always as 0 1 ... Read always as 1 { At write: : Write enabled ∆ : Write enable conditionally (include some conditions at write) - : Write disabled (Written value invalid) Abit 1234D0 D Bit name Function WR <at reset: H'04> 0 Not assigned. 0

1 Abit

0: ----- 1: ----- Not implemented in the shaded portion. <Example of representation> Bbit Cbit Bbit Cbit 0: ----- 1: ----- 0: ----- 1: ----- Registers represented with thick rectangles are accessible only with halfwords or words (not accessible with bytes) 3 4

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CHAPTER 5 INTERRUPT CONTROLLER (ICU) CHAPTER 6 INTERNAL MEMORY (3)

CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS (4)

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CHAPTER 10 INPUT/OUTPUT TIMERS (6)

(without Correction Function) (without Correction Function) (without Correction Function) CHAPTER 11 A-D CONVERTERS (7)

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13.7.3 Reading Out a Received Data Frame When Set for Remote Frame Transmission ...13-100 CHAPTER 14 REAL-TIME DEBUGGER (RTD) (10)

(11) CHAPTER 15 PD MODULE

(12) CHAPTER 16 D-A CONVERTERS CHAPTER 17 EXTERNAL BUS INTERFACE CHAPTER 18 WAIT CONTROLLER

(13) CHAPTER 19 RAM BACKUP MODE CHAPTER 20 OSCILLATION CIRCUIT CHAPTER 21 JTAG

CHAPTER 22 POWER-UP/POWER-SHUTDOWN SEQUENCE CHAPTER 23 ELECTRICAL CHARACTERISTICS CHAPTER 24 STANDARD CHARACTERISTICS (14)

APPENDIX 1 MECHANICAL SPECIFICATIONS APPENDIX 2 INSTRUCTION PROCESSING TIME APPENDIX 3 PRECAUTIONS ABOUT NOISE (15)

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1.1 Overview

1.2 Block Diagram

1.3 Pin Functions

1.4 Pin Layout

1-2 Rev.1.0

1.1.1 M32R Family CPU Core

(1) Uses the RISC architecture

• The 32172/32173 are 32-bit, RISC single-chip microcomputers built around the M32R family CPU core (hereafter referred to as the "M32R") and incorporating flash memory, RAM, and various other peripheral functions... all integrated into a single chip.
• The M32R uses the RISC architecture. Memory accesses are performed using Load and Store instructions, and various arithmetic operations are executed using register-to-register operating instructions. The M32R internally has sixteen 32-bit general-purpose registers and a total of 83 discrete instructions.
• In addition to Load and Store instructions, the M32R supports compound instructions such as Load & Address Update and Store & Address Update. These instructions are useful for speeding up data transfers. (2) 5-stage pipelined processing
• The M32R uses 5-stage pipelined instruction processing consisting of Instruction Fetch, Decode, Execute, Memory Access, and Write Back. Not just load and store instructions or register-to-register operation instructions, compound instructions such as Load & Address Update and Store & Address Update also are executed in one cycle.
• Instructions are entered into the execution stage in the order they are fetched, but this does not always mean that the first instruction entered is executed first. If the execution of a load or store instruction entered earlier is delayed by one or more wait cycles inserted in memory access, a register-to-register operation instruction entered later may be executed before said load or store instruction. By using "out-of-order-completion" like this, the M32R controls instruction execution without wasting clock cycles. (3) Compact instruction code
• Instructions of the M32R come in either a 16-bit instruction or a 32-bit instruction format. Use of the 16-bit instruction format especially helps to reduce the code size of a program.
• Some 32-bit instructions can branch directly to a location 32 Mbytes forward or backward from the currently executed instruction address. The availability of such instructions makes programming easier than for architectures with segmented address spaces. Overview

1-3 Rev.1.0 Overview

1.1.2 Built-in Multiply-Accumulate Operation Function

(1) Built in high-speed multiplier

• The M32R incorporates a 32-bit x 16-bit high-speed multiplier/accumulator which allows the processor to execute a 32-bit x 32-bit integer multiplication instruction in three cycles (one cycle is 25 ns when CPU memory clock = 40 MHz). (2) Supports Multiply-Accumulate operation instructions comparable to DSP
• The M32R supports the following four modes of Multiply-Accumulate operation instructions (or multiplication instructions) based on a 56-bit accumulator: 16 high-order register bits x 16 high-order register bits 16 low-order register bits x 16 low-order register bits All 32 register bits x 16 high-order register bits All 32 register bits x 16 low-order register bits
• The M32R has instructions to round off the value stored in the accumulator to 16 or 32 bits, as well as instructions to shift the accumulator value to adjust digits and store the digit-adjusted value in a register. These instructions also can be executed in one cycle, so that when combined with high-speed data transfer instructions such as Load & Address Update and Store & Address Update, they enable the M32R to exhibit high data processing capability comparable to that of DSP.

1.1.3 Built-in Flash Memory and RAM

• The 32172/32173 contains flash memory and RAM that can be accessed with no wait states, making it possible to build a high-speed embedded system.
• The internal flash memory allows for on-board programming (you can write to it while being mounted on the printed circuit board). Use of flash memory means the chip engineered at the development phase can be used directly in mass-production, so that you can smoothly migrate from prototype to mass-production without changing the printed circuit board.
• The internal flash memory can be rewritten 100 times.
• The internal flash memory has a virtual-flash emulation function, allowing the internal RAM tobe artificially mapped into part of the internal flash memory. This function, when combined with the internal Real-Time Debugger (RTD), facilitates data tuning on ROM tables.
• The internal RAM can be accessed for read or rewrite from an external device independently of the M32R by using RTD (real-time debugger). It is communicated with external devices by RTD's exclusive clock-synchronized serial I/O.

1-4 Rev.1.0

1.1.4 Built-in Clock Multiplier Circuit

• The 32172/32173 internally multiplies the frequency of the input clock signal by 4 (or by 2 for the internal peripheral clock). When the input clock frequency is 10.0 MHz, the CPU clock frequency is 40 MHz and that of the internal peripheral clock is 20 MHz.

1.1.5 Built-in Powerful Peripheral Functions

(1) Built-in input/output timers

• The timers used in the 32172/32173 consist of the following 26 channels of timers. (When not using the PDC module as a sensor interface circuit, eight more channels of input timers are available.) 16-bit output related timers x 16 channels 16-bit input related timers x 6 channels 32-bit input related timers x 4 channels Each timer has multiple modes to choose from, depending on the purpose of use. (2) Built-in 10-channel DMA
• The microcomputer contains 10 channels of DMA, allowing for data transfer between internal peripheral I/Os and between internal RAM and internal peripheral I/O. DMA transfer requests can be issued from the user-created software, as well as can be triggered by a signal generated by the internal peripheral I/O (A-D converter, input/output timer, or serial I/O).
• The microcomputer also supports cascaded operation between DMA channels (starting DMA transfer on a channel at the end of transfer on another channel). This makes advanced transfer processing possible without causing any additional CPU load. (3) Built-in two blocks of A-D converters
• The microcomputer contains an 8-channel A-D converter and a 4-channel A-D converter, both capable of 10-bit resolution.
• In addition to ordinary A-D conversion, the converters support comparator mode in which a set value and the A-D converted value are compared to determine which is larger or smaller than the other.
• When A-D conversion is finished, the converters can generate a DMA transfer request, as well as an interrupt. (4) High-speed serial I/O
• The microcomputer contains eight channels of serial I/Os which can be set for clock- synchronized serial I/O or UART.
• The transfer rate in clock-synchronized serial I/O mode is a high 2 Mbits per second, allowing for fast data transfer.
• The serial I/O has the function to generate a DMA transfer request when data reception is Overview

1-5 Rev.1.0 completed or the transmit register becomes empty. (5) Built-in Real-time Debugger (RTD)

• The Real-time Debugger (RTD) provides a function for accessing directly from the outside to the M32R/E's internal RAM. It uses a dedicated clock-synchronized serial I/O to communicate with external devices.
• Use of the RTD allows the contents of the internal RAM to be read out or its data to be rewritten from the outside, independently of the M32R.
• An RTD interrupt can be generated to indicate that RTD-based data transmission or reception is completed. (6) 8-level interrupt controller
• The Interrupt Controller controls interrupt requests from internal peripheral I/Os by using eight priority levels (including interrupt-disabled state) which are assigned to each interrupt source. It also handles external interrupt requests generated upon detection of power outage or generated by the watchdog timer as System Break Interrupt (SBI). (7) Three operation modes
• The M32R/E supports three operation modes: single-chip, external extended, and processor modes. The M32R/E's address space and external pin functions are switched over according to each mode. Modes are selected using the MOD0 and MOD1 pins. (8) Wait controller
• The Wait Controller supports access to external devices. In other than single-chip mode, up to 4 Mbytes of space is available for an external extended area.

1.1.6 Built-in Full-CAN Function

• The microcomputer contains two CAN modules compliant with CAN Specification V2.0B active, each of which has 16-channel message slots.

1.1.7 Two Built-in D-A Converters

• The microcomputer contains two blocks of 8-bit resolution D-A converters. Overview

1-6 Rev.1.0

• In addition to ordinary D-A conversion, these converters support the function to successively output any data. Also, the converters have a 256-byte output buffer (available for only the D- A0 converter).

1.1.8 Built-in Timer/Arithmetic Circuits for PD (Phase Digital) Sensors

• The microcomputer contains two blocks of timer/arithmetic circuits that operate along with PD (Phase Digital) sensors.
• With various arithmetic circuits needed for position predictive operations incorporated, and the timers interlocked with the D-A converters, fast data processing is possible.
• When not using the PD circuit, the PD sensor-handling timers can be used as ordinary input measurement timers or input event counters.

1.1.9 Built-in Debug Function

• The 32172/32173 supports the JTAG interface. Using this JTAG interface, the microcomputer can perform boundary scan test. Overview

1-7 Rev.1.0 Figure 1.2.1 Block Diagram Overview Figure 1.2.1 shows a block diagram of the 32172/32173. The features of each block are outlined in 32172 PLL Clock Generating Circuit Internal Bus Interface AddressData Internal RAM (M32172F2 : 16KB) Internal Flash Memory (256KB) M32R CPU Core (max 40MHz) Multiplier- accumulator DMAC (10 channels) Input/output Timer (26 channels) Serial I/O (8 channels) A-D Converter x 2 (A-D0: 10-bit A-D, 8 channels) (A-D1: 10-bit A-D, 4 channels) Wait Controller Interrupt Controller (interrupt sources in 8 levels) Real-time Debugger (RTD) External Bus Interface Internal 16-bit Bus Internal 32-bit Bus Input/output Ports (JTAG), 99 lines Full CAN (2 channels) D-A Converter x 2 (8 bits) PD Controller (M32173F2 : 32KB) 32173 (32 x 16+56)

1-8 Rev.1.0 Table 1.2.1 Features of the M32R Family CPU Core Functional Block Features M32R family • Bus specifications CPU core Basic bus cycle: 25 ns (when CPU clock = 40 MHz) Logical address space: 4 Gbytes linear External extended area: Maximum 4 Mbytes External data bus: 16 bits

• Implementation: Five-stage pipelined processing
• CPU core internally configured in 32 bits
• Register configuration General-purpose register: 32 bits x 16 Control register: 32 bits x 5
• Instruction set 16-bit/32-bit instruction formats 83 discrete instructions/6 addressing modes
• Built-in multiplier-accumulator (32 x 16 + 56) Table 1.2.2 Features of the Internal Memory Functional Block Features RAM • Capacity M32172F2: 16 Kbytes M32173F2: 32 Kbytes
• No-wait access
• By using the RTD (Real-time Debugger), the internal RAM can be accessed for data read or rewrite from the outside, independently of the M32R. Flash memory • Capacity: 256 Kbytes
• No-wait access
• Durability: Can be rewritten 100 times Overview

1-9 Rev.1.0 Overview Table 1.2.3 Features of Internal Peripheral I/Os Functional Block Features DMA • 10-channel DMA

• Supports data transfer between internal peripheral I/Os, between internal RAMs, and between internal peripheral I/O and internal RAM
• Capable of fast DMA transfer when used in combination with internal peripheral I/O
• Capable of cascaded operation between DMA channels (starting DMA transfer on a channel at the end of transfer on another) Timer • 26-channel multifunction timers
• 16 channels of 16-bit output related timers, 6 channels of 16-bit input related timers, and 4 channels of 32-bit input related timers
• Flexible timer configuration is possible by interconnecting each timer channel A-D converter • One 8-channel A-D converter and one 4-channel A-D converter, both capable of 10-bit resolution
• Supports comparator mode
• Can generate an interrupt or start DMA transfer at completion of A-D conversion
• Can monitor pin levels on a total of 20 channels (with reduced accuracy, however) Serial I/O • 8-channel serial I/O
• Can be set for clock-synchronized serial I/O or UART
• Capable of fast data transfer at 2 Mbits/second during clock-synchronized mode or

156 Kbits/second during UART mode

Real-time debugger • Can rewrite/monitor the internal RAM by command input from the outside, independently of the CPU

• Comes with dedicated clock-synchronized serial port Interrupt controller • Controls interrupt requests from internal peripheral I/Os
• Eight priority levels including interrupt-disabled state Wait controller • Controls wait state when accessing external extended area
• Inserts 1 to 4 wait cycles by software setting + extends wait period by external____ WAIT signal input Clock PLL • Multiply-by-4 clock generating circuit
• CPU clock of maximum 40 MHz (CPU, internal ROM, and internal RAM access)
• Internal peripheral clock of maximum 20 MHz (peripheral module access)
• Maximum external input clock frequency of 10.0 MHz D-A converter • Two channels of 8-bit resolution D-A converters D-A0 converter: D-A output, successive data output function, 256-byte output buffer available D-A1 converter: D-A output only PD Controller • Two blocks of PD sensor-accommodating timers and various arithmetic circuits for position predictive operation
• 16-bit input measurement timer: 4 channels; 16-bit input related timer: 4 channels
• When not using the PD circuit, the above timers can be used as input measurement timers or input event counters CAN • Two blocks of CAN modules, each with 16-channel message slots JTAG • Boundary scan function, Mitsubishi original SDI debug function included

1-10 Rev.1.0 of pin functions. Figure 1.3.1 Pin Function Diagram of 144LQFP Package Overview M32172F2VFP, M32173F2VFP Clock Reset VSS Address bus Bus control Data bus P72 / HREQ P73 / HACK /TXD3 P71 / WAIT P43 / RD P44 / CS0 P45 / CS1 P41 / BLW / BLE P42 / BHW / BHE Port 0 Port 8 XOUT VCNT OSC-VCC OSC-VSS MOD0 MOD1Mode P74 / RTDTXD P75 / RTDRXD P76 / RTDACK P77 / RTDCLK Realtime debugger P70 / BCLK / WR Port 7 P82 / TXD0 P83 / RXD0 P84 / SCLKI 0 / SCLKO 0 P85 / TXD1 P86 / RXD1 P87 / SCLKI 1 / SCLKO 1 Serial I/O VDD FVCC FP P220 / CTX0 P221 / CRX0 3.3V (Note) 5V (Note) 3.3V 3.3V 3.3V Note : The [3.3V] blocks operate with a 3.3 V power supply. : The [5V] blocks operate with a 5 V or 3.3 V power supply. JTMS JTCK JTRST JTDO JTAG JTDI Bus control address bus VCCE 4 P00 — P07/DB0 — DB7 8 P10 — P17/DB8 — DB15Port 1 P20 — P27 / A23 — A30 P30 — P37 / A15 — A22 P46 / A13 / CS3 P47 / A14 Port 2 Port 3 Port 4 Interrupt controller P61 — P63 Port 6 P64 / SBI Bus control serial I/O Clock P93 / RXD3 (/ AD0IN8) P94 / TXD6 P95 / RXD6 P96 / CTX1 P97 / CRX1 Port 9 CAN P100 — P103 / TO8 — TO11 P105 / TO13 / SCLKO4 P106 / TO14 / TXD4 P104 / TO12 / SCLKI4 P107 / TO15 / RXD4 Port 10 Input/output timer Input/output timer serial I/O P110 — P113 / TO0 — TO3 P115 / TO5 / SCLKO5 P116 / TO6 / TXD5 P114 / TO4/ SCLKI5 P117 / TO7 / RXD5 Port 11 Input/output timer Input/output timer serial I/O A-D converter AVCC0 VREF0 AD0IN0 — AD0IN7 AVSS0 AD1IN0 — AD1IN3 P125 / TIN0B (/ AD1IN9) P126 / TIN1A (/ AD0IN10) P124 / TIN0A (/ AD0IN9) P127 / TIN1B (/ AD1IN10) Port 12 PD module (A-D converter) P135 / TIN21 (/ AD1IN13) P136 / TIN22 (/ AD0IN14) P134 / TIN20 (/ AD0IN13) P137 / TIN23 (/ AD1IN14) Port 13 P131 / TIN17 / PWMOFF1 (/AD1IN11) P132 / TIN18 (/ AD0IN12) P130 / TIN16 / PWMOFF0 (/AD0IN11) P133 / TIN19 (/ AD1IN12) Input/output timer (A-D converter) P150 / TIN8 / TXD7 (/AD0IN15) P153 / TIN9 / RXD7 (/AD1IN15) Port 15 P173 / TIN11 (/ AD1IN7) P172 / TIN10 (/ AD1IN6) P174 / TXD2 P175 / RXD2 Port 17 P225 / A12 / CS2 Port 22 CAN DA0 (/ AD1IN4) DA1 (/ AD1IN5) D-A converter VCCI Serial I/O Input/output timer serial I/O (A-D converter)Input/output timer serial I/O (A-D converter)

1-11 Rev.1.0 XIN RESET M32172F2VWG, M32173F2VWG Clock Reset VSS Address bus Bus control Data bus P72 / HREQ P73 / HACK /TXD3 P71 / WAIT P43 / RD P44 / CS0 P45 / CS1 P41 / BLW / BLE P42 / BHW / BHE Port 0 Port 8 XOUT VCNT OSC-VCC OSC-VSS MOD0 MOD1Mode P74 / RTDTXD P75 / RTDRXD P76 / RTDACK P77 / RTDCLK Realtime debugger P70 / BCLK / WR Port 7 P82 / TXD0 P83 / RXD0 P84 / SCLKI 0 / SCLKO 0 P85 / TXD1 P86 / RXD1 P87 / SCLKI 1 / SCLKO 1 Serial I/O VDD FVCC FP P220 / CTX0 P221 / CRX0 3.3V (Note) 5V (Note) 3.3V 3.3V 3.3V Note : The [3.3V] blocks operate with a 3.3 V power supply. : The [5V] blocks operate with a 5 V power supply. JTMS JTCK JTRST JTDO JTAG JTDI Bus control address bus VCCE P00 — P07/DB0 — DB7 8 P10 — P17/DB8 — DB15Port 1 P20 — P27 / A23 — A30 P30 — P37 / A15 — A22 P46 / A13 / CS3 P47 / A14 Port 2 Port 3 Port 4 Interrupt controller P61 — P63 Port 6 P64 / SBI Bus control serial I/O Clock P93 / RXD3 (/ AD0IN8) P94 / TXD6 P95 / RXD6 P96 / CTX1 P97 / CRX1 Port 9 CAN P100 — P103 / TO8 — TO11 P105 / TO13 / SCLKO4 P106 / TO14 / TXD4 P104 / TO12 / SCLKI4 P107 / TO15 / RXD4 Port 10 Input/output timer Input/output timer serial I/O P110 — P113 / TO0 — TO3 P115 / TO5 / SCLKO5 P116 / TO6 / TXD5 P114 / TO4/ SCLKI5 P117 / TO7 / RXD5 Port 11 Input/output timer Input/output timer serial I/O A-D converter AVCC0 VREF0 AD0IN0 — AD0IN7 AVSS0 AD1IN0 — AD1IN3 P125 / TIN0B (/ AD1IN9) P126 / TIN1A (/ AD0IN10) P124 / TIN0A (/ AD0IN9) P127 / TIN1B (/ AD1IN10) Port 12 PD module (A-D converter) P135 / TIN21 (/ AD1IN13) P136 / TIN22 (/ AD0IN14) P134 / TIN20 (/ AD0IN13) P137 / TIN23 (/ AD1IN14) Port 13 P131 / TIN17 / PWMOFF1 (/AD1IN11) P132 / TIN18 (/ AD0IN12) P130 / TIN16 / PWMOFF0 (/AD0IN11) P133 / TIN19 (/ AD1IN12) Input/output timer (A-D converter) P150 / TIN8 / TXD7 (/ AD0IN15) P153 / TIN9 / RXD7 (/ AD1IN15) Port 15 P173 / TIN11 (/ AD1IN7) P172 / TIN10 (/ AD1IN6) P174 / TXD2 P175 / RXD2 Port 17 P225 / A12 / CS2 Port 22 CAN DA0 (/ AD1IN4) DA1 (/ AD1IN5) D-A converter VCCI Serial I/O TRCLK TRDATA TRSYNC DBI EVENT1 EVENT0 DEBUG Input/output timer serial I/O (A-D converter) Input/output timer serial I/O (A-D converter) Figure 1.3.2 Pin Function Diagram of 175FBGA Package Overview

1-12 Rev.1.0 Table 1.3.1 Description of Pin Functions (1/6) ClassificationPin Name Description Type Function Power supply VCCE Power supply –– Supplies power to external I/O ports (5 V). VCCI Power supply –– Supplies power to the internal logic (3.3 V). VDD RAM power supply –– Power supply pin for internal RAM backup (3.3 V). FVCC Flash power supply –– Power supply pin for the internal flash memory (3.3 V). VSS Ground –– Connect all VSS to ground (GND). Clock XIN, Clock Input Clock input/output pin. With a PLL-based XOUT Output frequency multiplier circuit included, enter a clock with 1/4 the operating frequency (XIN input = 10.0 MHz for the CPU clock of 40 MHz). Use this clock for external synchronized design. BCLK/WR System Output When this signal is System Clock (BCLK), it outputs a clock clock whose is twice that of extemal inpout clock. (BCLK output = 20 MHz when CPU clock operates at 40 MHz). When this signal is Write (WR), during extemal write access it indicates the valid data on the data bus to transfer. input clock (BCLK output = 20 MHz when the external input clock is 10 MHz). OSC-VCC Power supply –– Power supply for the PLL circuit. Connect OSC-VCC to the power supply (3.3 V). OSC-VSS Ground –– Connect OSC-VSS to ground. VCNT PLL control Input PLL circuit control pin. Connect a resistor and capacitor to this pin. (For details about an external circuit, refer to Section 20.1.1, "Example of an Oscillator Circuit." Reset RESET Reset Input Resets the internal circuits. Mode MOD0 Mode Input Sets operation mode. MOD1 FP MOD0 MOD1 Mode X 0 0 Single-chip mode X 0 1 External extended mode 0 1 0 Processor mode 1 1 0 Boot mode X 1 1 (Reserved) Address A12-A30 Address Output To allow four blocks of up to 1 MB memory space to bus bus be connected external to the chip, 19 address lines (A12-A30) are provided. A31 is not output to the outside. Note: For details about boot mode, refer to Chapter 6, "Internal Memory." Overview

1-13 Rev.1.0 Overview Table 1.3.1 Description of Pin Functions (2/6) ClassificationPin Name DescriptionType Function Data bus DB0-DB15 Data bus Input/Output 16-bit data bus for connecting external devices. In write___ ___ ___ ___ cycle, the CPU outputs BHW/BHE and BLW/BLE indicating the valid byte position to write on the 16-bit data bus. In read cycle, the CPU always reads data from the full 16-bit data bus. However, data at only the valid byte position is transferred to the internal circuit of the M32R. Bus control CS0, CS1 Chip select Output Chip select signal for external devices. For details about___ ___ CS2, CS3 areas for which the chip select signal is output, refer to Chapter 3, "Address Space." RD Read Output This signal is output when reading an external device. BHW/BHE Byte high Output Indicates the byte position to which valid data will be write/enable ___ transferred when writing to an external device.BHW/ BLW/BLE Byte low Output ___ BHE is output for the upper address side (D0-D7 is write/enable valid), while BLW/BLE is output for the lower address side (D8-D15 is valid). ____ WAIT Wait Input ____ If input on WAIT is low when the M32R accesses an external device, the wait cycle is extended. ____ HREQ Hold request Input This input pin is provided for external devices to request____ control of the external bus. If input on the HREQ pin is pulled low, the M32R goes to a hold state. ____ HACK Hold Output This signal is used to indicate that the M32R has entered acknowledge a hold state and relinquished control of the external bus. Input/ TIN8-TIN11, Timer input Input Input/output timer input pin. output timer TIN16-TIN23 TO0-TO15 Timer output Output Input/output timer output pin. Interrupt ___ SBI System breakInput System Break Interrupt (SBI) input pin for the interrupt controller interrupt controller.

1-14 Rev.1.0 Table 1.3.1 Description of Pin Functions (3/6) ClassificationPin Name Description Type Function PD controller TIN0A, TIN0B Timer input Input PD0 sensor interface and timer input pin. TIN1A, TIN1B Timer input Input PD1 sensor interface and timer input pin. A-D converter AVCC0 Analog power –– AVCC0 is the power supply for the A-D and D-A supply converters. Connect AVCC0 to the power supply (5 V). AVSS0 Analog ground –– AVSS0 is the analog ground for the A-D and D-A converters. Connect AVSS0 to ground. VREF0 Reference voltageInput VREF0 is the reference voltage input pin for the A-D input and D-A converters (5 V). AD0IN0 Analog input Input 8-channel analog input pins for the A-D0 converter. – AD0IN7 AD1IN0 Analog input Input 4-channel analog input pins for the A-D1 converter. – AD1IN3 (/AD0IN8) Analog input Input 20-channel analog input pins used to monitor the pin levels. – (AD0IN15,) (/AD1IN4) – (/AD1IN15) D-A DA0 Analog output Output Analog output pin for the D-A0 converter. converter DA1 Analog output Output Analog output pin for the D-A1 converter. Serial I/O SCLKI0/ UART transmit/ Input/ For UART mode: These pins output a clock derived SCLKO0, receive clock Output from BRG by dividing it by 2. SCLKI1/ output or CSIO For CSIO mode: These pins accept as input the SCLKO1 transmit/receive transmit/receive clock when an external clock is selected clock input/output or output the transmit/receive clock when an internal clock is selected Overview

1-15 Rev.1.0 Table 1.3.1 Description of Pin Functions (4/6) ClassificationPin Name Description Type Function Serial I/O SCLKI4, Clock output Input For UART mode: Use inhibited (in input state) SCLKI5 For CSIO mode: Transmit/receive clock input when external clock is selected SCLKO4, Clock output Output For UART mode: Clock output derived from BRG by SCLKO5 dividing it by 2 For CSIO mode: Transmit/receive clock output TXD0-TXD7 Transmit data Output Serial I/O transmit data output pins. RXD0-RXD7 Received data Input Serial I/O received data input pins. Overview

1-16 Rev.1.0 Table 1.3.1 Description of Pin Functions (5/6) ClassificationPin Name Description Type Function Real-time RTDTXD Transmit data Output Serial data output pin for the real-time debugger. debugger RTDRXD Received data Input Serial data input pin for the real-time debugger. RTDCLK Clock input Input Serial data transmit/receive clock input pin for the real-time debugger. RTDACK Acknowledge Output Outputs a low-level pulse synchronously with the first clock cycle of the real-time debugger's serial data output word. The low-level pulse width indicates the type of command/data received by the real-time debugger. Flash only FP Flash Protect Input This is a mode pin which has the function to protect the flash memory against E/W in hardware. CAN CTX0,CTX1 Data output Output These pins output the data from the CAN module. CRX0,CRX1 Data input Input These pins take in the data for the CAN module. JTAG JTMS Test mode Input Test mode select input to control the state transition of the test circuit. JTCK Clock Input Clock input for the debug module and test circuit. JTRST Test reset Input Test reset input to initialize the test circuit asynchronously. JTDI Serial input Input This pin takes in the test instruction code or test data serially. JTDO Serial output Output This pin outputs the test instruction code or test data serially. Input/output P00-P07 Input/output port 0Input/Output Programmable input/output port. port P10-P17 Input/output port 1Input/Output Programmable input/output port. (Note) P20-P27 Input/output port 2Input/Output Programmable input/output port. P30-P37 Input/output port 3Input/Output Programmable input/output port. Overview

1-17 Rev.1.0 Table 1.3.1 Description of Pin Functions (6/6) ClassificationPin Name Description Type Function Input/output P41-P47 Input/output port 4Input/Output Programmable input/output port. port P61-P64 Input/output port 6 Input/Output Programmable input/output port. (Note 1) (However, P64 is an input-only port.) P70-P77 Input/output port 7 Input/Output Programmable input/output port. P82-P87 Input/output port 8 Input/Output Programmable input/output port. P93-P97 Input/output port 9 Input/Output Programmable input/output port. (However, P93 and P97 are input-only ports.) P100-P107 Input/output port 10Input/Output Programmable input/output port. P110-P117 Input/output port 11Input/Output Programmable input/output port. P124-P127 Input/output port 12Input/Output Input-only port. P130-P137 Input/output port 13Input/Output Input-only port. P150, P153 Input/output port 15Input/Output Programmable input/output port. P172-P175 Input/output port 17Input/Output Programmable input/output port. (However, P172 and P173 are input-only pins.) P220,P221 Input/output port 22Input/Output Programmable input/output port. P225 (Note 2) (However, P22 is a CAN input-only pin.) Note 1: Input/output port 5 is reserved for future use. Input/output ports 14, 16, 18, 19, 20, and 21 are nonexistent. Note 2: Use of P225 requires caution because it has a debug event function. Overview

1-18 Rev.1.0 the 32172/32173. Figure 1.4.1 Pin Layout Diagram of the M32172F2VFP/M32173F2VFP (Top View) Overview P153/TIN9/RXD7 (/AD1IN15) P150/TIN8/TXD7 (/AD0IN15) VCCE P107/TO15/RXD4 P106/TO14/TXD4 P104/TO12/SCLKI4 P103/TO11 VCCI P42/ BHW / BHE P125/TIN0B (/AD1IN9) P124/TIN0A (/AD0IN9) P44/ CS0 P45/ CS1 P47/A14 P46/A13/ CS3 P127/TIN1B (/AD1IN10) P137/TIN23 (/AD1IN14) P136/TIN22 (/AD0IN14) P135/TIN21 (/AD1IN13) P134/TIN20 (/AD0IN13) P105/TO13/SCLKO4 P133/TIN19 (/AD1IN12) P132/TIN18 (/AD0IN12) P131/TIN17/PWMOFF1 (/AD1IN11) P130/TIN16/PWMOFF0 (/AD0IN11) P126/TIN1A (/AD0IN10) JTDI JTDO JTRST JTCK JTMS 112 119 116 115 113 111 110 109 120 117 114 124 132 130 129 127 121 137 144 143 142 141 140 139 138 133 136 135 134 123 122 131 128 125 126 118 P220/CTX0 P14/DB12 P15/DB13 P16/DB14 P17/DB15 P82/TXD0 P83/RXD0 P174/TXD2 P175/RXD2 VSS VCCI VREF0 AVCC0 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 P173/TIN11 (/AD1IN7) P172/TIN10 (/AD1IN6) DA1 (/AD1IN5) DA0 (/AD1IN4) AD1IN3 AD1IN2 AD1IN1 AD1IN0 AVSS0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 VSS P84/SCLKI0/SCLKO0 VCCE P13/DB11 2 43 5 6 7 8 9 3522 23 24 25 26 27 28 29 30 31 32 33 3411 12 13 14 15 16 17 18 19 20 21101 36 VCNT OSC-VCC XOUT XIN OSC-VSS P37/A22P36/A21P33/A18P31/A16P30/A15 P35/A20P34/A19P32/A17 P27/A30P25/A28P26/A29P24/A27 P11/DB9P07/DB7P05/DB5P02/DB2P01/DB1P00/DB0P23/A26P22/A25P20/A23 P10/DB8P06/DB6P04/DB4P03/DB3P21/A24 P221/CRX0 P12/DB10 VCCE (Note) P225/A12/CS2 VSS 899099 9897 96 9594 93 9291103102101108107106105104 737484 75767778798081828385868788100 RESET P62FP P94/TXD6 P74/RTDTXDP75/RTDRXDP76/RTDACKP77/RTDCLK P61P63P114/TO4/SCLKI5P115/TO5/SCLKO5P116/TO6/TXD5P117/TO7/RXD5 VCCE MOD1P112/TO2P113/TO3 P70/BCLK / WRP71/ WAITP72/ HREQP64/ SBIMOD0 P93/RXD3 (/AD0IN8)P73/ HACK /TXD3VDD FVCCVSSP100/TO8P101/TO9P102/TO10 P110/TO0P111/TO1 P97/CRX1P96/CTX1P95/RXD6 (/AD1IN8) Package: 144P6Q (0.5 mm pitch) Note: Use caution when using a pin because it has a debug event function.

1-19 Rev.1.0 Overview Table 1.4.1 Pin Arrangement of the 144LQFP Package (1/2) No. Pin Name No. Pin Name No. Pin Name

1 P221/CRX0 31 P05/DB5 61 VCCI

___ P225/A12/CS2 32 P06/DB6 62 VSS

3 OSC-VSS 33 P07/DB7 63 P174/TXD2

4 XIN 34 P10/DB8 64 P175/RXD2

5 XOUT 35 P11/DB9 65 VCCE

6 OSC-VCC 36 P12/DB10 66 P82/TXD0

7 VCNT 37 P13/DB11 67 P83/RXD0

8 P30/A15 38 P14/OB12 68 P84/SCLKI0/SCLKO0

9 P31/A16 39 P15/DB13 69 P85/TXD1

10 P32/A17 40 P16/DB14 70 P86/RXD1

11 P33/A18 41 P17/DB15 71 P87/SCLKI1/SCLKO1

12 P34/A19 42 VREF0 72 VSS

13 P35/A20 43 AVCC0 73 FVCC

14 P36/A21 44 AD0IN0 74 P61

15 P37/A22 45 AD0IN1 75 P62

16 P20/A23 46 AD0IN2 76 P63

17 P21/A24 47 AD0IN3 77

___ P64/SBI

18 P22/A25 48 AD0IN4 78

19 P23/A26 49 AD0IN5 79

____ P71/WAIT

20 VCCE 50 AD0IN6 80

____ P72/HREQ

21 VSS 51 AD0IN7 81

____ P73/HACK/TXD3

22 P24/A27 52 AD1IN0 82 P74/RTDTXD

23 P25/A28 53 AD1IN1 83 P75/RTDRXD

24 P26/A29 54 AD1IN2 84 P76/RTDACK

25 P27/A30 55 AD1IN3 85 P77/RTDCLK

26 P00/DB0 56 DA0 (/AD1IN4) 86 P93/RXD3 (/AD0IN8)

27 P01/DB1 57 DA1 (/AD1IN5) 87 P94/TXD6

28 P02/DB2 58 P172/TIN10 (/AD1IN6) 88 P95/RXD6 (/AD1IN8)

29 P03/DB3 59 P173/TIN11 (/AD1IN7) 89 P96/CTX1

30 P04/DB4 60 AVSS0 90 P97/CRX1

1-20 Rev.1.0 Overview Table 1.4.2 Pin Arrangement of the 144LQFP Package (2/2) No. Pin Name No. Pin Name No. Pin Name RESET 111 JTRST 131 P137/TIN23 (/AD1IN14)

92 MOD0 112 JTDO 132 VCCE

93 MOD1 113 JTDI 133 P150/TIN8/TXD7 (/AD0IN15)

94 FP 114 P103/TO11 134 P153/TIN9/RXD7 (/AD1IN15)

95 VCCE 115 P104/TO12/SCLKI4 135

96 VSS 116 P105/TO13/SCLKO4 136

97 P110/TO0 117 P106/TO14/TXD4 137 VCCI

98 P111/TO1 118 P107/TO15/RXD4 138 VSS

99 P112/TO2 119 P124/TIN0A (/ADIN9) 139

100 P113/TO3 120 P125/TIN0B (/AD1IN9) 140

___ P44/CS0

101 P114/TO4/SCLKI5 121 P126/TIN1A (/AD0IN10) 141

___ P45/CS1

102 P115/TO5/SCLKO5 122 P127/TIN1B (/AD1IN10) 142

___ P46/A13/CS3

103 P116/TO6/TXD5 123 VCCI 143 P47/A14

104 P117/TO7/RXD5 124

P130/TIN16/PWMOFF0 (/AD0IN11) 144 P220/CTX0

105 P100/TO8 125 P131/TIN17/PWMOFF1 (/AD0IN11)

106 P101/TO9 126 P132/TIN18 (/AD0IN12)

107 P102/TO10 127 P133/TIN19 (/AD1IN12)

108 VDD 128 P134/TIN20 (/AD0IN13)

109 JTMS 129 P135/TIN21 (/AD1IN13)

110 JTCK 130 P136/TIN22 (/AD0IN14)

1-21 Rev.1.0 P106/TO14 DBI EVENT1 P150/TIN8 VCCI N.C. N.C. P45/CS1 P153/TIN9 VSS N.C. N.C. P47/A14 P46/A13 (/AD0IN15) /TIN21 (/AD1IN13) P131/TIN17 /PWMOFF1 (/AD1IN11) /TXD4 /CS3 (/AD1IN15) /TIN22 (/AD0IN14) /TIN18 (/AD0IN12) /TIN1B (/AD1IN10) /TIN0B (/AD1IN9) /TO13 /SCLKO4 N.C. N.C. P44/CS0 P41/BLW P43/RD /TIN23 (/AD1IN14) /TIN19 (/AD1IN12) /TIN0A (/AD0IN9) /TO12 /SCLKI4 /BLE P221/CRX0 P220/CTX0 EVENT0 N.C. OSC-VSS XIN /TIN20 (/AD0IN13) /TIN1A (/AD0IN10) /TO15 /RXD4 P225/A12 /CS2 P42/BHW /BHE VCCE P130/TIN16 /PWMOFF0 (/AD0IN11) VCCI N.C. VCNT OSC-VCC XOUT P30/A15 P113/TO3 P33/A18 P32/A17 P31/A16 P34/A19 VSS P36/A21 TRCLK P35/A20 P37/A22 TRDATA7 P22/A25 P21/A24 P20/A23 P23/A26 P97/CRX1 VSS TRSYNC P24/A27 VCCE P96/CTX1 P26/A29 P27/A30 P00/DB0 P25/A28 TRDATA4 P02/DB2 P03/DB3 P04/DB4 P01/DB1 P75/RTDRXD P05/DB5 P06/DB6 P07/DB7 N.C. AD0IN2 AD0IN6 AD1IN2 /TIN10 (/AD1IN6) /TIN11 (/AD1IN7) TRDATA0 N.C. P174/TXD2 P10/DB8 P11/DB9 P16/DB14 N.C. AVCC0 AD0IN3 AD0IN7 AD1IN3 VSS TRDATA3 P82/TXD0 P85/TXD1 N.C. N.C. P13/DB11 P12/DB10 P17/DB15 AD0IN0 AD0IN4 AD1IN0 DA0 (/AD1IN14) VCCI TRDATA2 VCCE /SCLKI0 /SCLKO0 P14/DB12 P15/DB13 VREF0 AD0IN1 AD0IN5 AD1IN1 DA1 (/AD1IN15) AVSS0 TRDATA1 P175/RXD2 P83/RXD0 CAD E FG H J KLM NPRB M32172F2VWG M32173F2VWG /TXD7 /RXD7 P136 P137P135 P134 P132 P133 P127 P125 P124 P126 P105 P104 P107 P84 P173 P172 P110/TO0P102/TO0 TRDATA6 TRDATA5 P115/TO5 /SCLKO5 JTRST JTCK P117 /TO7 /RXD5 P114 /TO4 /SCLKI5 MOD1 P93 /RXD3 (/AD0IN8) P74 /RTDTXD P71/WAIT P63 FVCC N.C. JTDO JTMS VDD P100/TO8 P111/TO1 FP RESET P95 /RXD6 (/AD1IN8) P77 /RTDCLK P73/HACK /TXD3 P70/BCLK /WR P62 P61 VSS /TXD5 P112/TO2 VCCE MOD0 P94/TXD6 P76 /RTDACK P72/HREQ P64/SB1 P87 /SCLKI1 /SCLKO1 N.C. P86/RXD1 P103/TO11 JTDI Figure 1.4.2 Pin Layout Diagram (Top View) Overview

1-22 Rev.1.0 Overview Table 1.4.3 Pin Arrangement of the 175FBGA Package (1/2) No. Pin Name No. Pin Name No. Pin Name A1 –– D1 XIN G1 P36/A21 P45/CS1 D2 OSC-VSS G2 TRCLK A3 N.C. D3 P225/A12/CS2 G3 P35/A20 A4 N.C. D4 N.C. G4 P37/A22 A5 VCCI D5 P42/BHW/BHE G5 –– A6 P150/TIN8/TXD7(/AD0IN15) D6 VCCE G6 –– A7 P135/TIN21(/AD1IN13) D7 P134/TIN20(/AD0IN13) G7 –– A8 P131/TIN17/PMWOFF1(/AD1IN11) D8 P130/TIN16/PWMOFF0(/AD0IN11) G8 –– A9 EVENT1 D9 VCCI G9 –– A10 DBI D10 P126/TIN1A(/AD0IN10) G10 –– A11 P106/TO14/TXD4 D11 P107/TO15/RXD4 G11 –– A12 P103/TO11 D12 N.C. G12 TRDATA7 A13 N.C. D13 P101/TO9 G13 VCCE A14 JTDO D14 P100/TO8 G14 FP A15 JTRST D15 P117/TO7/RXD5 G15 MOD1 P46/A13/CS3 E1 VCNT H1 P22/A25 B2 P47/A14 E2 OSC-VCC H2 P21/A24 B3 N.C. E3 XOUT H3 P20/A23 B4 N.C. E4 P30/A15 H4 P23/A26 B5 VSS E5 –– H5 –– B6 P153/TIN9/RXD7(/AD1IN15) E6 –– H6 –– B7 P136/TIN22(/AD0IN14) E7 –– H7 –– B8 P132/TIN18(/AD01N12) E8 –– H8 –– B9 P127/TIN1B(/AD1IN10) E9 –– H9 –– B10 P125/TIN0B(/AD1IN9) E10 –– H10 –– B11 P105/TO13/SCLKO4 E11 –– H11 –– B12 JTDI E12 P113/TO3 H12 P97/CRX1 B13 N.C. E13 P116/TO6/TXD5 H13 MOD0 B14 JTMS E14 P115/TO5/SCLKO5 H14 RESET B15 JTCK E15 P114/TO4/SCLKI5 H15 TRDATA6 C1 P221/CRX0 F1 P33/A18 J1 VSS C2 P210/CTX0 F2 P32/A17 J2 TRSYNC P44/CS0 F3 P31/A16 J3 P24/A27 C4 N.C. F4 P34/A19 J4 VCCE P43/RD F5 –– J5 –– P41/BLW/BLE F6 –– J6 –– C7 P137/TIN23(/AD1IN14) F7 –– J7 –– C8 P133/TIN19(/AD1IN12) F8 –– J8 –– C9 EVENT0 F9 –– J9 –– C10 P124/TIN0A(/AD0IN9) F10 –– J10 –– C11 P104/TO12/SCLK14 F11 –– J11 –– C12 N.C. F12 VSS J12 P96/CTX1 C13 N.C. F13 P112/TO2 J13 P94/TXD6 C14 VDD F14 P111/TO1 J14 P95/RXD6(/AD1IN8) C15 P102/TO10 F15 P110/TO0 J15 TRDATA5

1-23 Rev.1.0 Overview Table 1.4.4 Pin Arrangement of the 175FBGA Package (2/2) No. Pin Name No. Pin Name No. Pin Name K1 P26/A29 M1 P05/DB5 P1 P13/DB11 K2 P27/A30 M2 P06/DB6 P2 P12/DB10 K3 P00/DB0 M3 P07/DB7 P3 N.C. K4 P25/A28 M4 N.C. P4 P17/DB15 K5 –– M5 AD0IN2 P5 AD0IN0 K6 –– M6 AD0IN6 P6 AD0IN4 K7 –– M7 AD1IN2 P7 AD1IN0 K8 –– M8 P172/TIN10(/AD1IN6) P8 DA0(/AD1IN14) K9 –– M9 P173/TIN11(/AD1IN7) P9 VCCI K10 –– M10 TRDATA0 P10 TRDATA2 K11 –– M11 P174/TXD2 P11 VCCE K12 TRDATA4 M12 N.C. P12 P84/SCLKI0/SCLKO0 K13 P76/RTDACK M13 ___ P64/SB1 P13 N.C. K14 P77/RTDCLK M14 P70/BCLK/WR P14 P61 K15 P93/RXD3(/AD0IN8) M15 ____ P71/WAIT P15 FVCC L1 P02/DB2 N1 P10/DB8 R1 P14/DB12 L2 P03/DB3 N2 P11/DB9 R2 P15/DB13 L3 P04/DB4 N3 P16/DB14 R3 N.C. L4 P01/DB1 N4 N.C. R4 VREF0 L5 –– N5 AVCC0 R5 AD0IN1 L6 –– N6 AD0IN3 R6 AD0IN5 L7 –– N7 AD0IN7 R7 AD1IN1 L8 –– N8 AD1IN3 R8 DA1(/AD1IN15) L9 –– N9 VSS R9 AVSS0 L10 –– N10 TRDATA3 R10 TRDATA1 L11 –– N11 P82/TXD0 R11 P175/RXD2 L12 P75/RTDRXD N12 P85/TXD1 R12 P83/RXD0 L13 ____ P72/HREQ N13 P87/SCLKI1/SCLKO1 R13 P86/RXD1 L14 ____ P73/HACK/TXD3 N14 P62 R14 VSS L15 P74/RTDTXD N15 P63 R15 N.C.

1-24 Rev.1.0 Overview

2.1 CPU Registers

2.2 General-purpose Registers

2.3 Control Registers

2.4 Accumulator

2.5 Program Counter

2.6 Data Formats

2-2 Rev.1.0 CPU The M32R has sixteen general-purpose registers, five control registers, an accumulator, and a program counter. The accumulator is a 56-bit configuration, and all other registers are a 32-bit configuration. General-purpose registers are 32 bits in width and there are sixteen of them (R0 to R15), which are used to hold data and base addresses. Especially, R14 is used as a link register, and R15 is used as a stack pointer. The link register is used to store the return address when executing a subroutine call instruction. The stack pointer is switched between an interrupt stack pointer (SPI) and a user stack pointer (SPU) depending on the value of the Processor Status Word register (PSW)'s stack mode (SM) bit. Figure 2.2.1 General-purpose Registers 31 3100 R10 R11 R12 R13 R14 (Link register) R15 (Stack pointer) (Note) Note: The stack pointer is switched between an interrupt stack pointer (SPI) and a user stack pointer (SPU) depending on the value of the PSW's SM bit.

2-3 Rev.1.0 CPU There are five control registers-Processor Status Word Register (PSW), Condition Bit Register (CBR), Interrupt Stack Pointer (SPI), User Stack Pointer (SPU), and Backup PC (BPC). Dedicated "MVTC" and "MVFC" instructions are used to set and read these control registers. Figure 2.3.1 Control Registers Control Registers CR0 CR1 CR2 CR3 0 31 PSW CBR SPI SPU Processor status Word Register Condition Bit Register Interrupt Stack Pointer User Stack Pointer BPCCR6 Backup PC CRn Notes 1: CRn (n = 0-3, 6) denotes control register numbers. 2: Dedicated "MVTC" and "MVFC" instructions are used to set and read the control registers.

2-4 Rev.1.0 CPU

2.3.1 Processor Status Word Register: PSW (CR0)

The Processor Status Word Register (PSW) is used to indicate the status of the M32R. It consists of a regularly used PSW field and a special BPSW field which is used to save the PSW field when an EIT occurs. The PSW field consists of several bits labeled Stack Mode (SM), Interrupt Enable (IE), and Condition bit (C). The BPSW field consists of backup bits of the foregoing, i.e., Backup SM bit (BSM), Backup IE bit (BIE), and Backup C bit (BC). D Bit Name Function Initial R W

16 BSM (Backup SM) Holds the value of SM bit when EIT Indeterminate

is accepted.

17 BIE (Backup IE) Holds the value of IE bit when EIT Indeterminate

is accepted.

23 BC (Backup C) Holds the value of C bit when EIT Indeterminate

is accepted. 24 SM (Stack Mode) 0: Interrupt stack pointer is used. 0 1: User stack pointer is used. 25 IE (Interrupt Enable) 0: No interrupt is accepted. 0 1: Interrupt is accepted.

31 C (Condition bit) Depending on instruction execution, it indicates 0

whether operation resulted in a carry, borrow, or overflow. Note 1: "Initial" shows the state immediately after reset, R = O means the register is readable, W = O means the register is writable. Note 2: For changes of the state of each bit when an EIT event occurs, refer to Chapter 4, "EIT.” (Note 1) 16 17 23 24 25 31(LSB)15870(MSB) SM IE CBCBSM BIE 00000000000000000000000000PS W BPSW field PSW field

2-5 Rev.1.0 CPU

2.3.2 Condition Bit Register: CBR (CR1)

The Condition Bit Register (CBR) is created as a separate register from the PSW by extracting the Condition bit (C) from it. The value written to the PSW C bit is reflected in this register. This register is a read-only register (writes to this register by "MVTC" instruction are ignored).

2.3.3 Interrupt Stack Pointer: SPI (CR2)

User Stack Pointer: SPU (CR3) The Interrupt Stack Pointer (SPI) and User Stack Pointer (SPU) hold the current address of the stack pointer. These registers can be accessed as general-purpose register R15. In this case, whether R15 is used as SPI or as SPU depends on the PSW's Stack Mode (SM) bit.

2.3.4 Backup PC: BPC (CR6)

The Backup PC (BPC) is a register used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31 is fixed to 0. When an EIT occurs, the value held in the PC immediately before the EIT occurred or the value of the next instruction is set in this register. When the "RTE" instruction is executed, the saved value is returned from the BPC to the PC. However, the two low-order bits of the PC when thus returned are always fixed to "00" (control always returns to word boundaries.) BPC BPC 0 31(LSB)0(MSB) SPI SPI SPU SPU 0(MSB) 0(MSB) 31(LSB) 31(LSB) CBR 0(MSB) 31(LSB) 00 00 00 00 00 0 00 0000 0000 0 0 0 00 000 0 0 C

2-6 Rev.1.0 The accumulator (ACC) is a 56-bit register used by DSP function instructions. When read out or written to, it is handled as a 64-bit register. When reading, the value of bit 8 is sign-extended. When writing, bits 0-7 are ignored. Also, the accumulator is used by the multiplication instruction "MUL." Note that when executing this instruction, the value of the accumulator is destroyed. The "MVTACHI" and "MVTACLO" instructions are used to write to the accumulator. The "MVTACHI" instruction writes data to the 32 high-order bits (bits 0-31), and the "MVTACLO" instruction writes data to the 32 low-order bits (bits 32-63). The "MVFACHI," "MVFACLO," and "MVFACMI" instructions are used to read data from the accumulator. The "MVFACHI" instruction reads data from the 32 high-order bits (bits 0-31), the "MVFACLO" instruction reads data from the 32 low-order bits (bits 32-63), and the "MVFACHI" instruction reads data from the 32 middle bits (bits 16-47). CPU Note: Bits 0-7 always show the sign-extended value of bit 8. Writes to this bit field are ignored. The Program Counter (PC) is a 32-bit counter used to hold the address of the currently executed instruction. Because M32R instructions each start from an even address, the LSB (bit 31) is always 0. 32 48 63(LSB)3116150(MSB) 4778 Range of bits read by MVFACMI instruction Range of bits read/written to by MVFACHI/MVTACHI instructions Range of bits read/written to by MVFACLO/MVTACLO instructions ACC (Note) PC PC 0 31(LSB)0(MSB)

2-7 Rev.1.0

2.6.1 Data Types

There are several data types that can be handled by the M32R's instruction set. These include signed and unsigned 8, 16, and 32-bit integers. Values of signed integers are represented by 2's complements. Figure 2.6.1 Data Types CPU Signed byte (8-bit) integer Unsigned byte (8-bit) integer Signed halfword (16-bit) integer Unsigned halfword (16-bit) integer Signed word (32-bit) integer Unsigned word (32-bit) integer 0(MSB) 0(MSB) 0(MSB) 0(MSB) 0(MSB) 0(MSB) 7(LSB) 7(LSB) 15(LSB) 15(LSB) 31(LSB) 31(LSB) S S S S : Sign bit

2-8 Rev.1.0 CPU

2.6.2 Data Formats

(1) Data formats in register Data sizes in M32R registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign- extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) into word (32-bit) data before being stored in the register. When storing data from M32R register into memory, the register data is stored in memory in different sizes depending on the instructions used. The ST instruction stores the entire 32-bit data of the register, the STH instruction stores the least significant 16-bit data, and the STB instruction stores the least significant 8-bit data. Figure 2.6.2 Data Formats in Register Rn 0(MSB) 31(LSB) <When loading> Byte Rn 0(MSB) 31(LSB) Halfword Rn 0(MSB) 31(LSB) Word Sign-extended (LDB instruction) or zero-extended (LDUB instruction) From memory (LDB, LDUB instructions) <When storing> Rn 0(MSB) 31(LSB) Byte Rn 0(MSB) 31(LSB) Halfword Rn 0(MSB) 31(LSB) Word To memory (STB instruction) To memory (STH instruction) To memory (ST instruction) From memory (LDH, LDUH instructions) From memory (LD instructions) Sign-extended (LDH instruction) or zero-extended (LDUH instruction)

2-9 Rev.1.0 (2) Data formats in memory Data sizes in memory are either byte (8 bits), halfword (16 bits), or word (32 bits). Byte data can be located at any address. However, halfword data must be located at halfword boundaries (where the LSB address bit = "0"), and word data must be located at word boundaries (where two LSB address bits = "00"). If an attempt is made to access memory data across these halfword or word boundaries, an address exception is generated. Figure 2.6.3 Data Formats in Memory CPU + 0 address + 1 address + 2 address + 3 address Byte 7 8 15 16 23 24 (MSB) 15(LSB) 0(MSB) 31(LSB) Byte Byte Byte Halfword Halfword Word

2-10 Rev.1.0 CPU Figure 2.6.5 M32R Family Endian Little/Little LL LH HL HH Big/Big HH HL LH LL Little/Big HH HL LH LL Endian (Bit/Byte) Data arrangement MPU name 7700 family M16C family Competition M32R family M16 family 7-031-24 15-823-16 0-7 24-31 8-15 16-23Bit number MSB LSB MSB LSB MSB LSB Ex:0x01234567 .byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67 Note: The M32R's endian method is big endian for both bit and byte. 7-031-24 15-823-16 Figure 2.6.4 Endian Methods Bit endian Byte endian Big endian Little endian Note: Even for bit big endian, H'01 is not B'10000000. MSB LSB HH HL LH LL H'01 H'23 H'45 H'6 7 MSB LSB LL LH HL HH H'67 H'45 H'23 H'0 1 MSB LSB B'0000001 D0 D7 MSB LSB B'0000001 D7 D0 (3) Endian The following shows the generally used endian methods and the M32R family endian.

2-11 Rev.1.0 CPU

• Constant transfer LD24 Rdest, #imm24 LDI Rdest, #imm16 LDI Rdest, #imm8 SETH Rdest, #imm16 230 Rdest imm24 310 LD24 Rdest, #imm2 4 150 Rdest imm16 310 SETH Rdest, #imm16 00 00
• Register to register transfer MV Rdest, Rsrc
• Control register transfer MVFC Rdest, CRsrc MVTC Rsrc, CRdest Note: For the MVTC instruction, the condition bit C does not change unless CRdest is CR0 (PSW). Rsrc 310 Rdest 310 Rsrc 310 CRdest 310 MVTC Rsrc, CRdest MV Rdest, Rsrc (4) Transfer instructions Figure 2.6.6 Transfer instructions

2-12 Rev.1.0 CPU

• Unsigned 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc
• Unsigned 16 bits LD24 Rsrc, #label LDUB Rdest, @Rsrc
• Unsigned 8 bits LD24 Rsrc, #label LDUH Rdest, @Rsrc Rdest 00 00 310 label +0 +1 +2 +3 label +0 +1 +2 +3 Rdest 310 label +0 +1 +2 +3 Rdest 00 00 00 310 Memory Register
• Signed 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc
• Signed 16 bits LD24 Rsrc, #label LDH Rdest, @Rsrc
• Signed 8 bits LD24 Rsrc, #label LDB Rdest, @Rsrc label Rdest 310+0 +1 +2 +3 Rdestlabel 00 00 FF F F Check the MSB 0 = positive 1 = negative 310 +0 +1 +2 +3 Rdestlabel 00 00 00 FF FF F F 310 +0 +1 +2 +3 Memory Register Check the MSB 0 = positive 1 = negative (5) Memory (signed) to register transfer Figure 2.6.7 Memory (signed) to register transfer (6) Memory (unsigned) to register transfer Figure 2.6.8 Memory (unsigned) to register transfer

2-13 Rev.1.0 CPU (7) Things to be noted for data transfer Note that in data transfer, data arrangements in registers and those in memory are different. Figure 2.6.9 Difference in Data Arrangements Data in memoryData in register Word data (32 bits) +0 +1 +2 +3 D0 D31 HH HL LH LL D0 D31 HH HL LH LL Half-word data (16 bits) +0 +1 +2 +3 D0 D31 H L D0 D15 H L Byte data (8 bits) +0 +1 +2 +3 D0 D3 1 D0 D7 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB (R0-R15) (R0-R15) (R0-R15)

2-14 Rev.1.0 ❊ This is a blank page. ❊ CPU

3.1 Outline of the Address Space

3.2 Operation Modes

3.3 Internal ROM and External

3.4 Internal RAM and SFR Areas

3.5 EIT Vector Entry

3.6 ICU Vector Table

3.7 Precautions on Address

3-2 Rev.1.0 The logical addresses of the M32R are always handled in 32-bit width, providing a 4-Gbyte linear address space. The address space of the M32R consists of the following: (1) User space

• Internal ROM area
• External extended area
• Internal RAM area
• SFR (Special Function Register) area (2) Boot program space (3) System space (not open to the user) (1) User space A 2 Gbytes of space in addresses from H'0000 0000 to H'7FFF FFFF is the user space. Located in this space are the internal ROM, external extended, and internal RAM areas and the SFR (Special Function Register) area (i.e., internal peripheral I/O registers). Of these, the internal ROM and external extended areas are allocated to different addresses depending on mode settings which are described later. (2) Boot program space A 1 Gbytes of space in addresses from H'8000 0000 to H'BFFF FFFF is the boot program space. This space stores a program (boot program) which enables on-board programming when the internal flash area is blank. (3) System space A 1 Gbytes of space in addresses from H'C000 0000 to H'FFFF FFFF is the system space. This space is reserved for use by development tools such as an in-circuit emulator or debug monitor, and cannot be used by the user. ADDRESS SPACE

3-3 Rev.1.0 ADDRESS SPACE Figure 3.1.1 Address Space of the M32172F2 Note 1: Locations vary with chip mode settings. Note 2: The boot program space can be read out only when FP = 1, MOD0 = 1, and MOD1 = 0. Boot ROM Area (8 Kbytes) H ’0000 0000 H ’FFFF FFFF <Logical Space of the M32172F2> H ’7FFF FFFF H ’8000 0000 User Space EIT Vector Entry Logical Address H ’BFFF FFFF H ’C000 0000 Boot Program Space (Note 2) System Space (16 Mbytes) H ’0000 0000 SFR Area (16 Kbytes) H ’0080 3FFF H ’0080 4000 User ROM Area (Note 1) External Extended Area (8 Mbytes)

1 Gbytes

2 Gbytes

Ghost Areas,

16 Mbytes

(16 Kbytes) H ’0080 7FFF H ’8000 0000 H ’8000 1FFF Ghost Areas,

16 Kbytes

(8 Kbytes) Reserved Area (96 Kbytes) H ’0080 8000H ’8000 3FFF H ’8000 2000 H ’8000 4000 H ’BFFF FFFF H ’0040 0000 H ’003F FFFF H ’000F FFFF H ’0010 0000 H ’0003 FFFF Reserved Area (768 Kbytes) H ’001F FFFF H ’0020 0000 H ’0004 0000 CS0 Area (1 Mbytes) (Note 1) CS1 Area (2 Mbytes) (Note 1) CS2 Area (2 Mbytes) (Note 1) H ’0060 0000 H ’005F FFFF H ’0080 0000 H ’007F FFFF CS3 Area (2 Mbytes) (Note 1) H ’00FF FFFF H ’0081 FFFF H ’0082 0000 Ghost Areas,

128 Kbytes Each

3-4 Rev.1.0 ADDRESS SPACE Figure 3.1.2 Address Space of the M32173F2 Note 1: Locations vary with chip mode settings. Note 2: The boot program space can be read out only when FP = 1, MOD0 = 1, and MOD1 = 0. H ’0000 0000 H ’FFFF FFFF H ’7FFF FFFF H ’8000 0000 H ’BFFF FFFF H ’C000 0000 H ’0000 0000 H ’0080 3FFF H ’0080 4000 H ’0080 BFFF H ’8000 0000 H ’8000 1FFF H ’0080 C000H ’8000 3FFF H ’8000 2000 H ’8000 4000 H ’BFFF FFFF H ’0040 0000 H ’003F FFFF H ’000F FFFF H ’0010 0000 H ’0003 FFFF H ’001F FFFF H ’0020 0000 H ’0004 0000 H ’0060 0000 H ’005F FFFF H ’0080 0000 H ’007F FFFF H ’00FF FFFF H ’0081 FFFF H ’0082 0000 <Logical Space of the M32173F2> User Space Boot Program Space (Note 2) System Space Logical Address (8 Kbytes) (16 Mbytes) Reserved Area (8 Kbytes) Ghost Areas, Ghost Areas, EIT Vector EntryExternal Extended Area (8 Mbytes) SFR Area (16 Kbytes) User ROM Area (Note 1) Internal RAM (32 Kbytes) Reserved Area (80 Kbytes) Reserved Area (768 Kbytes) CS0 Area (1 Mbytes) (Note 1) CS1 Area (2 Mbytes) (Note 1) CS2 Area (2 Mbytes) (Note 1) CS3 Area (2 Mbytes) (Note 1) Ghost Areas,

3-5 Rev.1.0 ADDRESS SPACE The 32172/32173 is placed in one of the following modes by settings of chip operation mode (setting the MOD0 and MOD1 pins) . For details about internal flash memory rewrite mode, refer to Section 6.5, "Programming the Internal Flash Memory." Table 3.2.1 Setting Operation Modes MOD0 MOD1 (Note 1) Operation mode (Note 2) VSS VSS Single-chip mode VSS VCC External extended mode VCC VSS Processor mode (FP = VSS) VCC VCC Reserved (use inhibited) Note 1: VCC and VSS are connected to +5 V and GND, respectively. Note 2: For internal flash memory rewrite mode (when FP=VCC) not listed in the above table, refer to Section 6.5, "Programming the Internal Flash Memory." The locations of the internal ROM and external extended areas in the address space of the 32172/ 32173 vary depending on its operation mode. (All other areas in address space located the same way.) Also, during external extended mode, the available size of the external extended area varies with pin functions of CS0, CS1, CS2, and CS3. Figure 3.2.1 shows an address map of internal ROM and external extended areas in each mode. Figure 3.2.2 shows an address map of internal ROM and external extended areas varying with pin functions of CS0, CS1, CS2, and CS3 during external extended mode. (For details about internal flash memory rewrite mode, refer to Section 6.5, "Programming the Internal Flash Memory.")

3-6 Rev.1.0 ADDRESS SPACE Figure 3.2.1 Internal ROM and External Extended Areas in Each Operation Mode of the M32172F2/M32173F2 H'0000 0000 H'0003 FFFF H'0004 0000 Non-CS0 Area <Single-chip mode> <Processor mode><External extended mode> H'001F FFFF H'0020 0000 CS0 Area (1 Mbytes) H'000F FFFF H'0010 0000 H'003F FFFF H'0040 0000 External Extended Area CS2 Area (2 Mbytes) CS3 Area (2 Mbytes) Reserved Area (768 Kbytes) CS1 Area (2 Mbytes) CS2 Reserved Area (2 Mbytes) CS3 Reserved Area (2 Mbytes) CS0 Area (2 Mbytes) External Extended Area Internal ROM Area (256 Kbytes) Internal ROM Area (256 Kbytes) H'005F FFFF H'0060 0000 H'007F FFFF CS1 Area (2 Mbytes)

3-7 Rev.1.0 ADDRESS SPACE Figure 3.2.2 Internal ROM and External Extended Areas Varying with Pin Functions of the M32172F2/M32173F2 H'0000 0000 H'0003 FFFF H'0004 0000 H'001F FFFF H'0020 0000 CS0 Area (512 Kbytes) H'000F FFFF H'0010 0000 H'003F FFFF H'0040 0000 Reserved Area (768 Kbytes) Internal ROM Area (256 Kbytes) H'005F FFFF H'0060 0000 H'007F FFFF Internal ROM Area (256 Kbytes) Internal ROM Area (256 Kbytes) Reserved Area (768 Kbytes) Reserved Area (768 Kbytes) Reserved Area (768 Kbytes) Ghost of CS0 Area CS1 Area (512 Kbytes) Ghost of CS1 Area CS2 Area (512 Kbytes) Ghost of CS2 Area CS0 Area (256 Kbytes) Ghost of CS0 Area CS1 Area (256 Kbytes) Ghost of CS1 Area CS2 Area (256 Kbytes) Ghost of CS2 Area CS3 Area (256 Kbytes) Ghost of CS3 Area Internal ROM Area (256 Kbytes) CS3 Area (256 Kbytes) Ghost of CS3 Area CS3 Area (256 Kbytes) Ghost of CS3 Area CS1 Area (256 Kbytes) Ghost of CS1 Area CS1 Area (256 Kbytes) Ghost of CS1 Area CS0 Area (256 Kbytes) Ghost of CS0 Area CS0 Area (256 Kbytes) Ghost of CS0 Area CS0 CS1 A12 /CS2 A13 /CS3 Pin functions (Note) CS0 CS1 A12/ CS2 CS0 CS1 A12/ CS2 CS0 CS1 A12 /CS2 A13 /CS3 A13/ CS3 A13/ CS3 Note: The pin functions enclosed in are effective. CS0 Area (1 Mbytes) CS1 Area (1 Mbytes) Ghost of CS1 Area

3-8 Rev.1.0 ADDRESS SPACE

3.3 Internal ROM and External Extended Areas

The 8-Mbyte area in user space addresses from H'0000 0000 to H'007F FFFF is used for the internal ROM and external extended areas. For details on how the locations of the internal ROM and external extended areas vary depending on 32172/32173 operation mode settings, refer to Section 3.2, "Operation Modes."

3.3.1 Internal ROM Area

The internal ROM is allocated to the addresses listed below. Located at the beginning of this area is the EIT vector entry (and ICU vector table). Table 3.3.1 Internal ROM Area Type Name Size Location Address M32172F2 , M32173F2 256 Kbytes H'0000 0000-H'0003 FFFF

3.3.2 External Extended Area

The external extended area is available only when external extended or processor mode is selected for the chip operation mode. For access to the external extended area, the 32172/32173 outputs the control signals that are required for accessing an external device. The 32172/32173's CS0, CS1, CS2, and CS3 signals are output according to the address into___ which the external extended area is mapped. Namely, the CS0 signal is output for the CS0 area,___ ___ ___ the CS1 signal is output for the CS1 area, the CS2 sognal is output for the CS2 area, and the CS3 signal is output for the CS3 area. Table 3.3.2 Address Mapping of the External Extended Area in Each Operation Mode of the Operation Mode Address Mapping of External Extended Area Single-chip mode None External extended mode Addresses H'0010 0000 to H'001F FFFF (CS0 area: 1 Mbytes) Addresses H'0020 0000 to H'003F FFFF (CS1 area: 2 Mbytes) Addresses H'0040 0000 to H'005F FFFF (CS2 area: 2 Mbytes) Addresses H'0060 0000 to H'007F FFFF (CS3 area: 2 Mbytes) Processor mode Addresses H'0000 0000 to H'001F FFFF (CS0 area: 2 Mbytes) Addresses H'0020 0000 to H'003F FFFF (CS1 area: 2 Mbytes)

3-9 Rev.1.0 ADDRESS SPACE The 8-Mbyte area in user space addresses from H'0080 0000 to H'00FF FFFF is used for the internal RAM area and the SFR (Special Function Register) area. Of these, the space that the user can actually use is a 128-Kbyte area from H'0080 0000 to H'0081 FFFF, and the other addresses comprise ghost areas in units of 128 Kbytes. (When programming, do not use the ghost area unless absolutely necessary.)

3.4.1 Internal RAM Area

For the M32172F2, the internal RAM is allocated to addresses H'0080 4000 through H'0080 7FFF (16 Kbytes). For the M32173F2, the internal RAM is allocated to addresses H'0080 4000 through H'0080 BFFF (32 Kbytes).

3.4.2 SFR (Special Function Register) Area

Addresses H'0080 0000 to H'0080 3FFF are the SFR (Special Function Register) area. Located in this area are the internal peripheral I/O registers. Figure 3.4.1 Internal RAM Area and SFR (Special Function Register) Area of the M32172F2 H'0080 0000 SFR area (16 Kbytes) Internal RAM (16 Kbytes) H'0080 3FFF H'0080 4000 H'0080 7FFF Virtual-flash emulation area separated in units of 8 Kbytes can be mapped into this area. For details, see Section 6.7.

3-10 Rev.1.0 ADDRESS SPACE Figure 3.4.2 Internal RAM Area and SFR (Special Function Register) Area of the M32173F2 H'0080 0000 SFR area (16 Kbytes) Internal RAM (32 Kbytes) H'0080 3FFF H'0080 4000 H'0080 BFFF Virtual-flash emulation area separated in units of 8 or 4 Kbytes can be mapped into this area. For details, see Section 6.7.

3-11 Rev.1.0 Figure 3.4.3 Outline of the SFR Area Mapping ADDRESS SPACE H ’0080 0000 H ’0080 007E H ’0080 0180 Interrupt Controller (ICU) H ’0080 0080 A-D0 Converter H ’0080 00EE Serial I/O0-3 H ’0080 0100 H ’0080 0146 Wait Controller Note: The Realtime Debugger (RTD) is an independent module operated on from the outside, and is designed not to be transparent to the CPU. 0 7 8 15 +0 address +1 address +0 address +1 address 0 7 8 15 H ’0080 0D8C H ’0080 0DDE H ’0080 0400 DMAC H ’0080 0478 CAN0 H ’0080 1000 H ’0080 11FE H ’0080 0700 Input/output Ports H ’0080 0744 H ’0080 3FFE CAN1 H ’0080 1400 H ’0080 15FE H ’0080 1800 H ’0080 18BA Flash Control H ’0080 07E0 H ’0080 07F2 H ’0080 0A00 H ’0080 0A46 Serial I/O4-7 H ’0080 0A80 H ’0080 0AEE A-D1 Converter H ’0080 0800 H ’0080 08F8 Timers (TML, TMS) H ’0080 09FF H ’0080 0C8C H ’0080 0CDE Timers (TOM0_0 — 7, TID0) Timers (TOM1_0 — 7, TID1) D-A0, 1 Converters H ’0080 1C78 H ’0080 1DFE PD Controller (PD0, PD1)

3-12 Rev.1.0 ADDRESS SPACE H'0080 0000 H'0080 0002 H'0080 0004 H'0080 0006 H'0080 006C H'0080 006E H'0080 0070 H'0080 0072 H'0080 0074 H'0080 0076 H'0080 0078 H'0080 007A H'0080 007C H'0080 007E H'0080 0080 H'0080 0082 H'0080 0084 H'0080 0086 H'0080 0088 H'0080 008A H'0080 0090 +0 address +1 address Interrupt Vector Register (IVECT) D0 D7 D8 D15 Interrupt Mask Register (IMASK) SBI Control Register (SBICR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR)SIO1 Receive Interrupt Control Register (ISIO1RXCR) SIO0 Transmit Interrupt Control Register (ISIO0TXCR) A-D0 Conversion Interrupt Control Register (IAD0CCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) DMA0-4 Interrupt Control Register (IDMA04CR) TID1 Output Interrupt Control Register (ITID1CR) TMS0 Output Interrupt Control Register (ITMS0CR) TOM0 Output Interrupt Control Register (ITOM0CR) Timer Input Interrupt Control Register 1 (IMJTOCR1) Timer Input Interrupt Control Register 3 (IMJTICR3) TID0 Output Interrupt Control Register (ITID0CR) TOM1 Output Interrupt Control Register (ITOM1CR) Timer Input Interrupt Control Register 0 (IMJTOCR0) Timer Input Interrupt Control Register 2 (IMJTOCR2) Timer Input Interrupt Control Register 4 (IMJTICR4) Timer Input Interrupt Control Register 5 (IMJTICR5)PWM Off Input Interrupt Control Register (IPWMOFFCR) PDC Input & Error Interrupt Control Register (IPDCCR) A-D0 Single Mode Register 0 (AD0SIM0) A-D0 Single Mode Register 1 (AD0SIM1) A-D0 Scan Mode Register 0 (AD0SCM0) A-D0 Scan Mode Register 1 (AD0SCM1) A-D0 Successive Approximation Register (AD0SAR) A-D0 Comparate Data Register (AD0CMP)H'0080 008C H'0080 0092 H'0080 0094 10-bit A-D0 Data Register 0 (AD0DT0) 10-bit A-D0 Data Register 1 (AD0DT1) 10-bit A-D0 Data Register 2 (AD0DT2) 10-bit A-D0 Data Register 3 (AD0DT3) 10-bit A-D0 Data Register 4 (AD0DT4) 10-bit A-D0 Data Register 5 (AD0DT5) 10-bit A-D0 Data Register 6 (AD0DT6) 10-bit A-D0 Data Register 7 (AD0DT7) 10-bit A-D0 Data Register 8 (AD0DT8) 10-bit A-D0 Data Register 9 (AD0DT9) 10-bit A-D0 Data Register 10 (AD0DT10) 10-bit A-D0 Data Register 11 (AD0DT11) 10-bit A-D0 Data Register 12 (AD0DT12) 10-bit A-D0 Data Register 13 (AD0DT13) 10-bit A-D0 Data Register 14 (AD0DT14) 10-bit A-D0 Data Register 15 (AD0DT15) H'0080 0096 H'0080 0098 H'0080 009A H'0080 009C H'0080 009E H'0080 00A0 H'0080 00A2 H'0080 00A4 H'0080 00A6 H'0080 00A8 H'0080 00AA H'0080 00AC H'0080 00AE H'0080 00D0 Address H'0080 0066 H'0080 0068 H'0080 006A SIO4 Transmit Interrupt Control Register (ISIO4TXCR) SIO4 Receive Interrupt Control Register (ISIO4RXCR)SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) DMA5-9 Interrupt Control Register (IDMA59CR) A-D1 Conversion Interrupt Control Register (IAD1CCR) 8-bit A-D0 Data Register 0 (AD08DT0) H'0080 0064 H'0080 0062 H'0080 0060 CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR) PDC Compare Match & Error Interrupt Control Register (IPDCOPCR)RTD Interrupt Control Register (IRTDCR) SIO6,7 Transmit/Receive Interrupt Control Register (ISIO67CR)SIO5 Transmit Interrupt Control Register (ISIO5TXCR) SIO5 Receive Interrupt Control Register (ISIO5RXCR) Blank areas are reserved for future use. A-D0 Conversion Rate Control Register (AD0CVSCR) H'0080 008E A-D0 Digital Input Control Register (AD0CHCON) CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) Figure 3.4.4 Register Mapping of the SFR Area (1)

3-13 Rev.1.0 ADDRESS SPACE H'0080 00DA H'0080 00DC H'0080 00DE H'0080 00E0 H'0080 00E4 H'0080 00E6 H'0080 00E8 H'0080 00EA H'0080 00EC H'0080 00EE H'0080 0100 H'0080 0102 H'0080 0110 H'0080 0112 H'0080 0114 H'0080 0116 H'0080 0120 H'0080 0126 H'0080 0122 H'0080 0130 SIO0 Baud Rate Register (S0BAUR) SIO0 Transmit Buffer Register (S0TXB) SIO0 Receive Buffer Register (S0RXB) SIO23 Interrupt Status Register (SI23STAT) 8-bit A-D0 Data Register 5 (AD08DT5) 8-bit A-D0 Data Register 6 (AD08DT6) 8-bit A-D0 Data Register 7 (AD08DT7) 8-bit A-D0 Data Register 8 (AD08DT8) 8-bit A-D0 Data Register 9 (AD08DT9) 8-bit A-D0 Data Register 10 (AD08DT10) 8-bit A-D0 Data Register 11 (AD08DT11) 8-bit A-D0 Data Register 12 (AD08DT12) 8-bit A-D0 Data Register 13 (AD08DT13) 8-bit A-D0 Data Register 14 (AD08DT14) 8-bit A-D0 Data Register 15 (AD08DT15) H'0080 0132 H'0080 0134 H'0080 0136 H'0080 0180 H'0080 00E2 SIO03 Interrupt Mask Register (SI03MASK) SIO03 Receive Interrupt Cause Select Register (SI03SEL) SIO0 Transmit Control Register (S0TCNT) SIO0 Transmit/Receive Mode Register (S0MOD) SIO0 Receive Control Register (S0RCNT) H'0080 0124 SIO1 Baud Rate Register (S1BAUR) SIO1 Transmit Buffer Register (S1TXB) SIO1 Receive Buffer Register (S1RXB) SIO1 Transmit Control Register (S1TCNT) SIO1 Transmit/Receive Mode Register (S1MOD) SIO1 Receive Control Register (S1RCNT) SIO2 Baud Rate Register (S2BAUR) SIO2 Transmit Buffer Register (S2TXB) SIO2 Receive Buffer Register (S2RXB) SIO2 Transmit Control Register (S2TCNT) SIO2 Transmit/Receive Mode Register (S2MOD) SIO2 Receive Control Register (S2RCNT) Wait Cycles Control Register (WTCCR) H'0080 00D2 H'0080 00D4 H'0080 00D6 H'0080 00D8 8-bit A-D0 Data Register 1 (AD08DT1) 8-bit A-D0 Data Register 2 (AD08DT2) 8-bit A-D0 Data Register 3 (AD08DT3) 8-bit A-D0 Data Register 4 (AD08DT4) D0 D7 D8 D15 H'0080 0140 H'0080 0142 H'0080 0144 H'0080 0146 SIO3 Transmit/Receive Mode Register (S3MOD)SIO3 Transmit Control Register (S3TCNT) SIO3 Transmit Buffer Register (S3TXB) SIO3 Receive Buffer Register (S3RXB) SIO3 Baud Rate Register (S3BAUR)SIO3 Receive Control Register (S3RCNT) +0 address +1 addressAddress Blank areas are reserved for future use. Figure 3.4.5 Register Mapping of the SFR Area (2)

3-14 Rev.1.0 ADDRESS SPACE DMA0-4 Interrupt Mask Register (DM04ITMK) DMA0 Channel Control Register (DM0CNT) DMA0 Transfer Count Register (DM0TCT) DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA1 Channel Control Register (DM1CNT) DMA1 Transfer Count Register (DM1TCT) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) H ’0080 0412 H ’0080 0414 H ’0080 0416 H ’0080 0418 H ’0080 041A H ’0080 041C H ’0080 0410 H ’0080 041E H ’0080 0422 H ’0080 0424 H ’0080 0426 H ’0080 0428 H ’0080 0420 DMA0-4 Interrupt Request Status Register (DM04ITST)H ’0080 0400 H ’0080 0408 DMA5-9 Interrupt Mask Register (DM59ITMK)DMA5-9 Interrupt Request Status Register (DM59ITST) DMA5 Channel Control Register (DM5CNT) DMA5 Transfer Count Register (DM5TCT) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA6 Channel Control Register (DM6CNT) DMA6 Transfer Count Register (DM6TCT) H ’0080 042A H ’0080 042C H ’0080 042E DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) DMA0 Request Cause Extension Register (DM0REQ) DMA5 Request Cause Extension Register (DM5REQ) DMA1 Request Cause Extension Register (DM1REQ) DMA6 Request Cause Extension Register (DM6REQ) +0 address +1 addressAddress Blank areas are reserved for future use. Figure 3.4.6 Register Mapping of the SFR Area (3)

3-15 Rev.1.0 ADDRESS SPACE DMA2 Channel Control Register (DM2CNT) DMA2 Transfer Count Register (DM2TCT)H ’0080 0430 H ’0080 0432 H ’0080 0434 H ’0080 0436 H ’0080 0438 H ’0080 043A H ’0080 043C H ’0080 043E H ’0080 0442 H ’0080 0444 H ’0080 0446 H ’0080 0448 H ’0080 044A H ’0080 044C H ’0080 0440 H ’0080 044E H ’0080 0450 H ’0080 0452 H ’0080 0454 H ’0080 0456 H ’0080 0458 H ’0080 045A H ’0080 045C H ’0080 045E H ’0080 0460 H ’0080 0464 H ’0080 0466 H ’0080 0462 DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA3 Channel Control Register (DM3CNT) DMA3 Transfer Count Register (DM3TCT) DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA4 Channel Control Register (DM4CNT) DMA4 Transfer Count Register (DM4TCT) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA7 Channel Control Register (DM7CNT) DMA7 Transfer Count Register (DM7TCT) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) DMA8 Channel Control Register (DM8CNT) DMA8 Transfer Count Register (DM8TCT) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA9 Channel Control Register (DM9CNT) DMA9 Transfer Count Register (DM9TCT) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA4 Software Request Generation Register (DM4SRI) DMA5 Software Request Generation Register (DM5SRI) DMA6 Software Request Generation Register (DM6SRI) DMA7 Software Request Generation Register (DM7SRI) DMA8 Software Request Generation Register (DM8SRI) DMA9 Software Request Generation Register (DM9SRI) H ’0080 0468 H ’0080 0470 H ’0080 0474 H ’0080 0476 H ’0080 0472 H ’0080 0478 H ’0080 0700 P0 Data Register (P0DATA) P1 Data Register (P1DATA) P2 Data Register (P2DATA) P3 Data Register (P3DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P7 Data Register (P7DATA) H ’0080 0702 H ’0080 0704 H ’0080 0706 H ’0080 0708 H ’0080 070A H ’0080 070C P8 Data Register (P8DATA ) P10 Data Register (P10DATA) P12 Data Register (P12DATA) P9 Data Register (P9DATA) P11 Data Register (P11DATA) P13 Data Register (P13DATA) H ’0080 070E H ’0080 0710 H ’0080 0712 H ’0080 0714 P15 Data Register (P15DATA) P17 Data Register (P17DATA) DMA2 Request Cause Extension Register (DM2REQ) DMA7 Request Cause Extension Register (DM7REQ) DMA3 Request Cause Extension Register (DM3REQ) DMA8 Request Cause Extension Register (DM8REQ) DMA4 Request Cause Extension Register (DM4REQ) DMA9 Request Cause Extension Register (DM9REQ) +0 address +1 addressAddress Blank areas are reserved for future use. Figure 3.4.7 Register Mapping of the SFR Area (4)

3-16 Rev.1.0 ADDRESS SPACE P2 Direction Register (P2DIR) P3 Direction Register (P3DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P7 Direction Register (P7DIR) P8 Direction Register (P8DIR) P9 Direction Register (P9DIR) P10 Direction Register (P10DIR) P11 Direction Register (P11DIR) P15 Direction Register (P15DIR) H ’0080 0724 H ’0080 0722 H ’0080 0728 H ’0080 0726 H ’0080 072C H ’0080 072A H ’0080 0730 H ’0080 072E H ’0080 0746 H ’0080 074A H ’0080 0748 H ’0080 074E H ’0080 074C P7 Operation Mode Register (P7MOD) P8 Operation Mode Register (P8MOD) P9 Operation Mode Register (P9MOD) P10 Operation Mode Register (P10MOD) P11 Operation Mode Register (P11MOD) P12 Operation Mode Register (P12MOD) P13 Operation Mode Register (P13MOD) P15 Operation Mode Register (P15MOD) P17 Direction Register (P17DIR) H ’0080 0750 P17 Operation Mode Register (P17MOD) H ’0080 07E0 H ’0080 07E2 H ’0080 07E4 H ’0080 07E8 H ’0080 07E6 H ’0080 0744 Port Input Function Enable Register (PIEN) P22 Data Register (P22DATA)H ’0080 0716 H ’0080 0720 H ’0080 0736 P22 Direction Register (P22DIR) H ’0080 0752 H ’0080 0754 H ’0080 0756 P22 Operation Mode Register (P22MOD) Bus Mode Control Register (BUSMODC) P0 Direction Register (P0DIR) P1 Direction Register (P1DIR) H ’0080 077E Flash Mode Register (FMOD) Flash Control Register 1 (FCNT1) Flash Status Register 1 (FSTAT1) Flash Control Register 2 (FCNT2) Flash Control Register 3 (FCNT3) Flash Control Register 4 (FCNT4) Virtual-flash L Bank Register 0 (FELBANK0) Virtual-flash L Bank Register 2 (FELBANK2) H ’0080 0742 H ’0080 0740 P0 Operation Mode Register (P0MOD) P2 Operation Mode Register (P2MOD) P4 Operation Mode Register (P4MOD) P1 Operation Mode Register (P1MOD) P3 Operation Mode Register (P3MOD) P4 Peripheral Output Select Register (P4SMOD) P7 Peripheral Output Select Register (P7SMOD) P10-P11 Peripheral Output Select Register (P1011SMOD) P15 Peripheral Output Select Register (P15SMOD) H ’0080 0766 H ’0080 0764 H ’0080 076A H ’0080 0768 H ’0080 076C H ’0080 076E H ’0080 07EA H ’0080 07EE H ’0080 07EC H ’0080 07A4 PWM Output Disable Register 0 (PWMOFF0) PWM Output Disable Control Register 0 (PLVCNT0) H ’0080 0776 P22 Peripheral Output Select Register (P22SMOD) Virtual-flash L Bank Register 1 (FELBANK1) H ’0080 07F2 H ’0080 07F0 Virtual-flash S Bank Register 0 (FESBANK0) Virtual-flash S Bank Register 1 (FESBANK1) H ’0080 07A2 H ’0080 07A0 PWM Output Disable Register 1 (PWMOFF1) PWM Output Disable Control Register 1 (PLVCNT1) +0 address +1 addressAddress Blank areas are reserved for future use. Figure 3.4.8 Register Mapping of the SFR Area (5)

3-17 Rev.1.0 ADDRESS SPACE H ’0080 0800 H ’0080 0802 H ’0080 0804 H ’0080 0850 H ’0080 0880 H ’0080 0882 H ’0080 088A H ’0080 0890 H ’0080 0892 H ’0080 0894 H ’0080 0896 H ’0080 0898 H ’0080 089A H ’0080 089C H ’0080 089E H ’0080 08A4 D0 D7 D8 D15 H ’0080 08A0 H ’0080 08A6 H ’0080 00A8 H ’0080 08AA H ’0080 08AC H ’0080 08AE H ’0080 08E0 H ’0080 08E2 H ’0080 08E4 H ’0080 08E6 H ’0080 08E8 H ’0080 08EA H ’0080 08F2 H ’0080 08F4 H ’0080 08F6 H ’0080 08F8 H ’0080 0846 H ’0080 0848 H ’0080 084A H ’0080 0844 H ’0080 0842 H ’0080 0840 H ’0080 08A2 TML0 Counter H (TML0CTH) TML0 Counter L (TML0CTL) Input Processing Control Register 0 (TINCR0) Input Processing Control Register 1 (TINCR1) Input Processing Control Register 2 (TINCR2) Input Processing Control Register 3 (TINCR3) Input Processing Control Register 4 (TINCR4) Input Processing Control Register 5 (TINCR5) TIN Interrupt Status Register 0 (TINIST0) TIN Interrupt Mask Register 0 (TINIMA0) TIN Interrupt Status Register 1 (TINIST1) TIN Interrupt Mask Register 1 (TINIMA1) TIN Interrupt Status Register 2 (TINIST2) TIN Interrupt Mask Register 2 (TINIMA2) TIN Interrupt Status Register 3 (TINIST3) TIN Interrupt Mask Register 3 (TINIMA3) TIN Interrupt Status Register 4 (TINIST4) TIN Interrupt Mask Register 4 (TINIMA4) TIN Interrupt Status Register 5 (TINIST5) TIN Interrupt Mask Register 5 (TINIMA5) TIN Interrupt Status Register 8 (TINIST8) TIN Interrupt Mask Register 8 (TINIMA8) TML0 Control Register 0 (TML0CR) Prescaler 1 (PRS1) TML0 Measurement 3 Register H (TML0MR3H) TML0 Measurement 3 Register L (TML0MR3L) TML0 Measurement 2 Register H (TML0MR2H) TML0 Measurement 2 Register L (TML0MR2L) TML0 Measurement 1 Register H (TML0MR1H) TML0 Measurement 1 Register L (TML0MR1L) TML0 Measurement 0 Register H (TML0MR0H) TML0 Measurement 0 Register L (TML0MR0L) TML0 Old Measurement 3 Register H (TML0OLDMR3H) TML0 Old Measurement 3 Register L (TML0OLDMR3L) TML0 Old Measurement 2 Register H (TML0OLDMR2H) TML0 Old Measurement 2 Register L (TML0OLDMR2L) TML0 Old Measurement 1 Register H (TML0OLDMR1H) TML0 Old Measurement 1 Register L (TML0OLDMR1L) TML0 Old Measurement 0 Register H (TML0OLDMR0H) TML0 Old Measurement 0 Register L (TML0OLDMR0L) TMS0 Old Measurement 3 Register (TMS0OLDMR3) TMS0 Old Measurement 2 Register (TMS0OLDMR2) TMS0 Old Measurement 1 Register (TMS0OLDMR1) TMS0 Old Measurement 0 Register (TMS0OLDMR0) TMS0 Counter (TMS0CT) TMS0 Measurement 3 Register (TMS0MR3) TMS0 Measurement 2 Register (TMS0MR2) TMS0 Measurement 1 Register (TMS0MR1) TMS0 Measurement 0 Register (TMS0MR0) TMS0 Control Register (TMS0CR) Prescaler (PRS0) +0 address +1 addressAddress Blank areas are reserved for future use. Figure 3.4.9 Register Mapping of the SFR Area (6)

3-18 Rev.1.0 ADDRESS SPACE H'0080 0A10 H'0080 0A12 H'0080 0A30 H'0080 0A32 H'0080 0A36 H'0080 0A40 H'0080 0A42 H'0080 0A44 H'0080 0A46 H'0080 0A80 H'0080 0A82 H'0080 0A84 H'0080 0A86 H'0080 0A8E D0 D7 D8 D15 H'0080 0A8A H'0080 0A90 H'0080 0A94 H'0080 0A96 H'0080 0A98 H'0080 0A9A H'0080 0A9E H'0080 0AA0 H'0080 0AA2 H'0080 0AA4 H'0080 0AA6 H'0080 0AA8 H'0080 0AAC H'0080 0AAE H'0080 0A16 H'0080 0A14 H'0080 0A8C H'0080 0A00 SIO67 Interrupt Status Register (SI67STAT) SIO47 Interrupt Mask Register (SI47MASK) H'0080 0A02 H'0080 0A20 H'0080 0A22 H'0080 0A24 H'0080 0A26 H'0080 0A34 SIO47 Receive Interrupt Cause Select Register (SI47SEL) SIO4 Transmit Control Register (S4TCNT) SIO4 Transmit/Receive Mode Register (S4MOD) SIO4 Transmit Buffer Register (S4TXB) SIO4 Receive Buffer Register (S4RXB) SIO4 Receive Control Register (S4RCNT) SIO4 Baud Rate Register (S4BAUR) SIO5 Transmit Control Register (S5TCNT) SIO5 Transmit/Receive Mode Register (S5MOD) SIO5 Transmit Buffer Register (S5TXB) SIO5 Receive Buffer Register (S5RXB) SIO5 Receive Control Register (S5RCNT) SIO5 Baud Rate Register (S5BAUR) SIO6 Transmit Control Register (S6TCNT) SIO6 Transmit/Receive Mode Register (S6MOD) SIO6 Transmit Buffer Register (S6TXB) SIO6 Receive Buffer Register (S6RXB) SIO6 Receive Control Register (S6RCNT) SIO6 Baud Rate Register (S6BAUR) SIO7 Transmit Control Register (S7TCNT) SIO7 Transmit/Receive Mode Register (S7MOD) SIO7 Transmit Buffer Register (S7TXB) SIO7 Receive Buffer Register (S7RXB) SIO7 Receive Control Register (S7RCNT) SIO7 Baud Rate Register (S7BAUR) H'0080 0A88 H'0080 0A92 H'0080 0A9C H'0080 0AAA A-D1 Single Mode Register 0 (AD1SIM0) A-D1 Single Mode Register 1 (AD1SIM1) A-D1 Scan Mode Register 0 (AD1SCM0) A-D1 Scan Mode Register 1(AD1SCM1) A-D1 Conversion Rate Control Register (AD1CVCR) A-D1 Successive Approximation Register (AD1SAR) A-D1 Comparate Data Register (AD1CMP) A-D1 Digital Input Control Register (AD1CHCON) 10-bit A-D1 Data Register 0 (AD1DT0) 10-bit A-D1 Data Register 1 (AD1DT1) 10-bit A-D1 Data Register 2 (AD1DT2) 10-bit A-D1 Data Register 3 (AD1DT3) 10-bit A-D1 Data Register 4 (AD1DT4) 10-bit A-D1 Data Register 5 (AD1DT5) 10-bit A-D1 Data Register 6 (AD1DT6) 10-bit A-D1 Data Register 7 (AD1DT7) 10-bit A-D1 Data Register 8 (AD1DT8) 10-bit A-D1 Data Register 9 (AD1DT9) 10-bit A-D1 Data Register 10 (AD1DT10) 10-bit A-D1 Data Register 11 (AD1DT11) 10-bit A-D1 Data Register 12 (AD1DT12) 10-bit A-D1 Data Register 13 (AD1DT13) 10-bit A-D1 Data Register 14 (AD1DT14) 10-bit A-D1 Data Register 15 (AD1DT15) +0 address +1 addressAddress Blank areas are reserved for future use. Figure 3.4.10 Register Mapping of the SFR Area (7)

3-19 Rev.1.0 ADDRESS SPACE H'0080 0AD8 H'0080 0ADA H'0080 0AEC H'0080 0AEE H'0080 0AD6 D0 D7 D8 D15 H'0080 0ADE H'0080 0ADC H'0080 0AD0 8-bit A-D1 Data Register 1 (AD18DT1) 8-bit A-D1 Data Register 0 (AD18DT0) H'0080 0AD2 H'0080 0AE2 H'0080 0AE4 H'0080 0AE6 H'0080 0AE8 8-bit A-D1 Data Register 2 (AD18DT2) 8-bit A-D1 Data Register 7 (AD18DT7) 8-bit A-D1 Data Register 3 (AD18DT3) 8-bit A-D1 Data Register 4 (AD18DT4) 8-bit A-D1 Data Register 5 (AD18DT5) 8-bit A-D1 Data Register 12 (AD18DT12) 8-bit A-D1 Data Register 6 (AD18DT6) 8-bit A-D1 Data Register 8 (AD18DT8) 8-bit A-D1 Data Register 9 (AD18DT9) 8-bit A-D1 Data Register 10 (AD18DT10) 8-bit A-D1 Data Register 11 (AD18DT11) 8-bit A-D1 Data Register 13 (AD18DT13) 8-bit A-D1 Data Register 14 (AD18DT14) 8-bit A-D1 Data Register 15 (AD18DT15) H'0080 0AE0 H'0080 0AEA H'0080 0AD4 +0 address +1 addressAddress Blank areas are reserved for future use. Figure 3.4.11 Register Mapping of the SFR Area (8)

3-20 Rev.1.0 D0 D7 D8 D15 H ’0080 0CC0 H ’0080 0CBE H ’0080 0CC4 H ’0080 0CC2 H ’0080 0CC8 H ’0080 0CC6 H ’0080 0CD2 H ’0080 0CD6 H ’0080 0CD4 H ’0080 0CCE H ’0080 0CD8 H ’0080 0C9A H ’0080 0C9C H ’0080 0C9E H ’0080 0CA2 H ’0080 0CA4 H ’0080 0CAA H ’0080 0CA8 H ’0080 0CA0 H ’0080 0CB4 H ’0080 0CB8 H ’0080 0CBC H ’0080 0CBA H ’0080 0CB6 H ’0080 0CDA H ’0080 0CA6 H ’0080 0CCC H ’0080 0CAC H ’0080 0CAE H ’0080 0CB0 H ’0080 0CDC TID0 Counter (TID0CT) TID0 Reload Register (TID0RL) TOM0_0 Reload Register (TOM00CT) H ’0080 0C8C H ’0080 0C8E H ’0080 0C90 H ’0080 0C94 H ’0080 0C96 H ’0080 0C92 H ’0080 0C98 H ’0080 0CB2 H ’0080 0CCA H ’0080 0CDE TOM0_0 Reload 1 Register (TOM00RL1) TOM0_0 Reload 0 Register (TOM00RL0) TOM0_1 Counter (TOM01CT) TOM0_1 Reload 1 Register (TOM01RL1) TOM0_1 Reload 0 Register (TOM01RL0) TOM0_2 Counter (TOM02CT) TOM0_2 Reload 1 Register (TOM02RL1) TOM0_2 Reload 0 Register (TOM02RL0) TOM0_3 Counter (TOM03CT) TOM0_3 Reload 1 Register (TOM03RL1) TOM0_3 Reload 0 Register (TOM03RL0) TOM0_4 Counter (TOM04CT) TOM0_4 Reload 1 Register (TOM04RL1) TOM0_4 Reload 0 Register (TOM04RL0) TOM0_5 Counter (TOM05CT) TOM0_5 Reload 1 Register (TOM05RL1) TOM0_5 Reload 0 Register (TOM05RL0) TOM0_6 Counter (TOM06CT) TOM0_6 Reload 1 Register (TOM06RL1) TOM0_6 Reload 0 Register (TOM06RL0) TOM0_7 Counter (TOM07CT) TOM0_7 Reload 1 Register (TOM07RL1) TOM0_7 Reload 0 Register (TOM07RL0) H ’0080 0CD0 Prescaler Register 2 (PRS2) TID0 Control & Prescaler 2 Enable Register (TID0PRS2EN) TOM0 Interrupt Mask Register (TOM0IMA) TOM0 Interrupt Status Register (TOM0IST) F/F Protect Register 0 (FFP0) F/F Protect Register 0 (FFD0) TOM0 Control Register (TOM0CR) TOM0 Enable Protect Register (TOM0PRO) TOM0 Count Enable Register (TOM0CEN) +0 address +1 addressAddress Blank areas are reserved for future use. ADDRESS SPACE Figure 3.4.12 Register Mapping of the SFR Area (9)

3-21 Rev.1.0 ADDRESS SPACE H'0080 0DC0 H'0080 0DBE H'0080 0DC4 H'0080 0DC2 H'0080 0DC8 H'0080 0DC6 H'0080 0DD2 H'0080 0DD6 H'0080 0DD4 H'0080 0DCE H'0080 0DD8 H'0080 0D9A H'0080 0D9C H'0080 0D9E H'0080 0DA2 H'0080 0DA4 H'0080 0DAA H'0080 0DA8 H'0080 0DA0 H'0080 0DB4 H'0080 0DB8 H'0080 0DBC H'0080 0DBA H'0080 0DB6 H'0080 0DDA H'0080 0DA6 H'0080 0DCC H'0080 0CAC H'0080 0DAE H'0080 0DB0 H'0080 0DDC TID1 Counter (TID1CT) TID1 Reload Register (TID1RL) TOM1_0 Counter Register (TOM10CT) H'0080 0D8C H'0080 0D8E H'0080 0D90 H'0080 0D94 H'0080 0D96 H'0080 0D92 H'0080 0D98 H'0080 0DB2 H'0080 0DCA H'0080 0DDE TOM1_0 Reload 1 Register (TOM10RL1) TOM1_0 Reload 0 Register (TOM10RL0) TOM1_1 Counter (TOM11CT) TOM1_1 Reload 1 Register (TOM11RL1) TOM1_1 Reload 0 Register (TOM11RL0) TOM1_2 Counter (TOM12CT) TOM1_2 Reload 1 Register (TOM12RL1) TOM1_2 Reload 0 Register (TOM12RL0) TOM1_3 Counter (TOM13CT) TOM1_3 Reload 1 Register (TOM13RL1) TOM1_3 Reload 0 Register (TOM13RL0) TOM1_4 Counter (TOM14CT) TOM1_4 Reload 1 Register (TOM14RL1) TOM1_4 Reload 0 Register (TOM14RL0) TOM1_5 Counter (TOM15CT) TOM1_5 Reload 1 Register (TOM15RL1) TOM1_5 Reload 0 Register (TOM15RL0) TOM1_6 Counter (TOM16CT) TOM1_6 Reload 1 Register (TOM16RL1) TOM1_6 Reload 0 Register (TOM16RL0) TOM1_7 Counter (TOM17CT) TOM1_7 Reload 1 Register (TOM17RL1) TOM1_7 Reload 0 Register (TOM17RL0) H'0080 0DD0 Prescaler 3 Register (PRS3) TID1 Control & Prescaler 3 Enable Register (TID1PRS3EN) TOM1 Interrupt Mask Register (TOM1IMA) TOM1 Interrupt Status Register (TOM1IST) F/F Protect Register 1 (FFP1) F/F Data Register 1 (FFD1) TOM1 Control Register (TOM1CR) TOM1 Enable Protect Register (TOM1PRO) TOM1 Count Enable Register (TOM1CEN) +0 address +1 addressAddress Blank areas are reserved for future use. Figure 3.4.13 Register Mapping of the SFR Area (10)

3-22 Rev.1.0 ADDRESS SPACE H ’0080 1034 H ’0080 1032 H ’0080 1038 H ’0080 1036 H ’0080 103C H ’0080 103A H ’0080 1054 H ’0080 1058 H ’0080 1056 H ’0080 1052 H ’0080 105A CAN0 Configuration Register (CAN0CONF) CAN0 Global Mask Register Standard ID0 (C0GMSKS0) CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0) H ’0080 1000 H ’0080 1002 H ’0080 1004 H ’0080 1008 H ’0080 100A H ’0080 1010 H ’0080 100E H ’0080 1006 H ’0080 1028 H ’0080 102C H ’0080 1030 H ’0080 102E H ’0080 102A H ’0080 105C H ’0080 100C H ’0080 1050 CAN0 Control Register (CAN0CNT) CAN0 Extended ID Register (CAN0EXTID) CAN0 Timestamp Count Register (CAN0TSTMP) CAN0 Slot Interrupt Status Register (CAN0SLIST) CAN0 Message Slot 3 Control Register (C0MSL3CNT)CAN0 Message Slot 2 Control Register (C0MSL2CNT) CAN0 Message Slot 4 Control Register (C0MSL4CNT) CAN0 Status Register (CAN0STAT) CAN0 Receive Error Count Register (CAN0REC) CAN0 Transmit Error Count Register (CAN0TEC) CAN0 Message Slot 0 Control Register (C0MSL0CNT) CAN0 Message Slot 1 Control Register (C0MSL1CNT) CAN0 Message Slot 5 Control Register (C0MSL5CNT) CAN0 Message Slot 7 Control Register (C0MSL7CNT) CAN0 Message Slot 9 Control Register (C0MSL9CNT) CAN0 Message Slot 11 Control Register (C0MSL11CNT) CAN0 Message Slot 13 Control Register (C0MSL13CNT) CAN0 Message Slot 15 Control Register (C0MSL15CNT) CAN0 Message Slot 6 Control Register (C0MSL6CNT) CAN0 Message Slot 8 Control Register (C0MSL8CNT) CAN0 Message Slot 10 Control Register (C0MSL10CNT) CAN0 Message Slot 12 Control Register (C0MSL12CNT) CAN0 Message Slot 14 Control Register (C0MSL14CNT) H ’0080 1012 CAN0 Error Interrupt Status Register (CAN0ERIST)CAN0 Error Interrupt Mask Register (CAN0ERIMK)H ’0080 1014 H ’0080 1016 CAN0 Baud Rate Prescaler (CAN0BRP) H ’0080 105E CAN0 Global Mask Register Standard ID1 (C0GMSKS1) CAN0 Global Mask Register Extended ID0 (C0GMSKE0) CAN0 Global Mask Register Extended ID1 (C0GMSKE1) CAN0 Global Mask Register Extended ID2 (C0GMSKE2) CAN0 Local Mask Register A Standard ID1 (C0LMSKAS1) CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0) CAN0 Local Mask Register A Extended ID1 (C0LMSKAE1) CAN0 Local Mask Register A Extended ID2 (C0LMSKAE2) CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0) CAN0 Local Mask Register B Standard ID1 (C0LMSKBS1) CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) CAN0 Local Mask Register B Extended ID1 (C0LMSKBE1) CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2) CAN0 Slot Interrupt Mask Register (CAN0SLIMK) +0 address +1 addressAddress Blank areas are reserved for future use. Figure 3.4.14 Register Mapping of the SFR Area (11)

3-23 Rev.1.0 ADDRESS SPACE H'0080 1102 H'0080 1104 H'0080 110C H'0080 110E H'0080 1112 H'0080 1114 H'0080 1116 H'0080 1110 H'0080 1108 H'0080 1106 H'0080 110A CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) CAN0 Message Slot 0 Extended ID2(C0MSL0EID2) CAN0 Message Slot 0 Data 0 (C0MSL0DT0) CAN0 Message Slot 0 Data 2(C0MSL0DT2) CAN0 Message Slot 0 Data 4(C0MSL0DT4) CAN0 Message Slot 0 Extended ID1(C0MSL0EID1) CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) CAN0 Message Slot 0 Data 1(C0MSL0DT1) CAN0 Message Slot 0 Data 3(C0MSL0DT3) CAN0 Message Slot 0 Data 5(C0MSL0DT5) CAN0 Message Slot 0 Data 6(C0MSL0DT6) CAN0 Message Slot 0 Data 7(C0MSL0DT7) CAN0 Message Slot 0 Timestamp (C0MSL0TSP) CAN0 Message Slot 1 Standard ID0(C0MSL1SID0) CAN0 Message Slot 1 Extended ID0(C0MSL1EID0) CAN0 Message Slot 1 Extended ID2(C0MSL1EID2) CAN0 Message Slot 1 Data 0(C0MSL1DT0) CAN0 Message Slot 1 Standard ID1(C0MSL1SID1) CAN0 Message Slot 1 Extended ID1(C0MSL1EID1) CAN0 Message Slot 1 Data Length Register(C0MSL1DLC) CAN0 Message Slot 1 Data 1(C0MSL1DT1) CAN0 Message Slot 1 Data 3(C0MSL1DT3) CAN0 Message Slot 1 Data 5(C0MSL1DT5) CAN0 Message Slot 1 Data 2(C0MSL1DT2) CAN0 Message Slot 1 Data 4(C0MSL1DT4) H'0080 1118 H'0080 111A H'0080 111E H'0080 1120 H'0080 1122 H'0080 1126 H'0080 1128 H'0080 112E H'0080 112C H'0080 1124 H'0080 112A CAN0 Message Slot 2 Data 6(C0MSL2DT6) CAN0 Message Slot 2 Timestamp(C0MSL2TSP) CAN0 Message Slot 2 Data 7(C0MSL2DT7) H'0080 111C CAN0 Message Slot 2 Data 4(C0MSL2DT4) CAN0 Message Slot 2 Data 2(C0MSL2DT2) CAN0 Message Slot 2 Data 0(C0MSL2DT0) CAN0 Message Slot 2 Extended ID2(C0MSL2EID2) CAN0 Message Slot 2 Extended ID0(C0MSL2EID0) CAN0 Message Slot 2 Standard ID0(C0MSL2SID0) CAN0 Message Slot 1 Timestamp(C0MSL1TSP) CAN0 Message Slot 1 Data 6(C0MSL1DT6) CAN0 Message Slot 2 Data 5(C0MSL2DT5) CAN0 Message Slot 2 Data 3(C0MSL2DT3) CAN0 Message Slot 2 Data 1(C0MSL2DT1) CAN0 Message Slot 2 Data Length Register(C0MSL2DLC) CAN0 Message Slot 2 Extended ID1(C0MSL2EID1) CAN0 Message Slot 2 Standard ID1(C0MSL2SID1) CAN0 Message Slot 1 Data 7(C0MSL1DT7) H'0080 1130 H'0080 1132 H'0080 1136 H'0080 1138 H'0080 113E H'0080 113C H'0080 1134 H'0080 113A CAN0 Message Slot 3 Data 6(C0MSL3DT6) CAN0 Message Slot 3 Timestamp(C0MSL3TSP) CAN0 Message Slot 3 Data 7(C0MSL3DT7) CAN0 Message Slot 3 Data 4(C0MSL3DT4) CAN0 Message Slot 3 Data 2(C0MSL3DT2) CAN0 Message Slot 3 Data 0(C0MSL3DT0) CAN0 Message Slot 3 Extended ID2(C0MSL3EID2) CAN0 Message Slot 3 Extended ID0(C0MSL3EID0) CAN0 Message Slot 3 Standard ID0(C0MSL3SID0) CAN0 Message Slot 3 Data 5(C0MSL3DT5) CAN0 Message Slot 3 Data 3(C0MSL3DT3) CAN0 Message Slot 3 Data 1(C0MSL3DT1) CAN0 Message Slot 3 Data Length Register(C0MSL3DLC) CAN0 Message Slot 3 Extended ID1(C0MSL3EID1) CAN0 Message Slot 3 Standard ID1(C0MSL3SID1) H'0080 1140 H'0080 1142 H'0080 1146 H'0080 1148 H'0080 114E H'0080 114C H'0080 1144 H'0080 114A CAN0 Message Slot 4 Data 6(C0MSL4DT6) CAN0 Message Slot 4 Timestamp(C0MSL4TSP) CAN0 Message Slot 4 Data 7(C0MSL4DT7) CAN0 Message Slot 4 Data 4(C0MSL4DT4) CAN0 Message Slot 4 Data 2(C0MSL4DT2) CAN0 Message Slot 4 Data 0(C0MSL4DT0) CAN0 Message Slot 4 Extended ID2(C0MSL4EID2) CAN0 Message Slot 4 Extended ID0(C0MSL4EID0) CAN0 Message Slot 4 Standard ID0(C0MSL4SID0) CAN0 Message Slot 4 Data 5(C0MSL4DT5) CAN0 Message Slot 4 Data 3(C0MSL4DT3) CAN0 Message Slot 4 Data 1(C0MSL4DT1) CAN0 Message Slot 4 Data Length Register(C0MSL4DLC) CAN0 Message Slot 4 Extended ID1(C0MSL4EID1) CAN0 Message Slot 4 Standard ID1(C0MSL4SID1) H'0080 1150 H'0080 1152 CAN0 Message Slot 5 Extended ID0(C0MSL5EID0) CAN0 Message Slot 5 Standard ID0(C0MSL5SID0) CAN0 Message Slot 5 Extended ID1(C0MSL5EID1) CAN0 Message Slot 5 Standard ID1(C0MSL5SID1) H'0080 1100 CAN0 Message Slot 0 Standard ID1(C0MSL0SID1)CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) +0 address +1 addressAddress Blank areas are reserved for future use. Figure 3.4.15 Register Mapping of the SFR Area (12)

3-24 Rev.1.0 D0 D7 D8 D15 H'0080 1156 H'0080 1158 H'0080 115E H'0080 115C H'0080 1154 H'0080 115A H'0080 1160 H'0080 1162 H'0080 1166 H'0080 1168 H'0080 116E H'0080 116C H'0080 1164 H'0080 116A H'0080 1170 H'0080 1172 H'0080 1176 H'0080 1174 CAN0 Message Slot 5 Data 6(C0MSL5DT6) CAN0 Message Slot 5 Timestamp (C0MSL5TSP) CAN0 Message Slot 5 Data 7(C0MSL5DT7) CAN0 Message Slot 5 Data 4(C0MSL5DT4) CAN0 Message Slot 5 Data 2(C0MSL5DT2) CAN0 Message Slot 5 Data 0 (C0MSL5DT0) CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) CAN0 Message Slot 5 Data 5(C0MSL5DT5) CAN0 Message Slot 5 Data 3(C0MSL5DT3) CAN0 Message Slot 5 Data 1(C0MSL5DT1) CAN0 Message Slot 5 Data Length Register (C0MSL5DLC) CAN0 Message Slot 6 Data 6(C0MSL6DT6) CAN0 Message Slot 6 Timestamp (C0MSL6TSP) CAN0 Message Slot 6 Data 7(C0MSL6DT7) CAN0 Message Slot 6 Data 4(C0MSL6DT4) CAN0 Message Slot 6 Data 2(C0MSL6DT2) CAN0 Message Slot 6 Data 0(C0MSL6DT0) CAN0 Message Slot 6 Extended ID2(C0MSL6EID2) CAN0 Message Slot 6 Extended ID0 (C0MSL6EID0) CAN0 Message Slot 6 Standard ID0 (C0MSL6SID0) CAN0 Message Slot 6 Data 5(C0MSL6DT5) CAN0 Message Slot 6 Data 3(C0MSL6DT3) CAN0 Message Slot 6 Data 1(C0MSL6DT1) CAN0 Message Slot 6 Data Length Register (C0MSL6DLC) CAN0 Message Slot 6 Extended ID1(C0MSL6EID1) CAN0 Message Slot 6 Standard ID1(C0MSL6SID1) CAN0 Message Slot 7 Data 0(C0MSL7DT0) CAN0 Message Slot 7 Extended ID2(C0MSL7EID2) CAN0 Message Slot 7 Extended ID0(C0MSL7EID0) CAN0 Message Slot 7 Standard ID0(C0MSL7SID0) CAN0 Message Slot 7 Data 1(C0MSL7DT1) CAN0 Message Slot 7 Data Length Register (C0MSL7DLC) CAN0 Message Slot 7 Extended ID1(C0MSL7EID1) CAN0 Message Slot 7 Standard ID1(C0MSL7SID1) H'0080 117A H'0080 117C H'0080 117E H'0080 1182 H'0080 1184 H'0080 118A H'0080 1188 H'0080 1180 H'0080 1186 H'0080 1178 H'0080 118C H'0080 118E H'0080 1192 H'0080 1194 H'0080 119A H'0080 1198 H'0080 1190 H'0080 1196 H'0080 119C H'0080 119E CAN0 Message Slot 8 Data 6(C0MSL8DT6) CAN0 Message Slot 8 Timestamp (C0MSL8TSP) CAN0 Message Slot 8 Data 7(C0MSL8DT7) CAN0 Message Slot 8 Data 4(C0MSL8DT4) CAN0 Message Slot 8 Data 2(C0MSL8DT2) CAN0 Message Slot 8 Data 0(C0MSL8DT0) CAN0 Message Slot 8 Extended ID2(C0MSL8EID2) CAN0 Message Slot 8 Extended ID0(C0MSL8EID0) CAN0 Message Slot 8 Standard ID0(C0MSL8SID0) CAN0 Message Slot 8 Data 5(C0MSL8DT5) CAN0 Message Slot 8 Data 3(C0MSL8DT3) CAN0 Message Slot 8 Data 1(C0MSL8DT1) CAN0 Message Slot 8 Data Length Register (C0MSL8DLC) CAN0 Message Slot 8 Extended ID1(C0MSL8EID1) CAN0 Message Slot 8 Standard ID1(C0MSL8SID1) CAN0 Message Slot 7 Data 6(C0MSL7DT6) CAN0 Message Slot 7 Timestamp (C0MSL7TSP) CAN0 Message Slot 7 Data 7(C0MSL7DT7) CAN0 Message Slot 7 Data 4(C0MSL7DT4) CAN0 Message Slot 7 Data 2(C0MSL7DT2) CAN0 Message Slot 7 Data 5(C0MSL7DT5) CAN0 Message Slot 7 Data 3(C0MSL7DT3) CAN0 Message Slot 9 Data 6(C0MSL9DT6) CAN0 Message Slot 9 Timestamp (C0MSL9TSP) CAN0 Message Slot 9 Data 7(C0MSL9DT7) CAN0 Message Slot 9 Data 4(C0MSL9DT4) CAN0 Message Slot 9 Data 2(C0MSL9DT2) CAN0 Message Slot 9 Data 0(C0MSL9DT0) CAN0 Message Slot 9 Extended ID2(C0MSL9EID2) CAN0 Message Slot 9 Extended ID0(C0MSL9EID0) CAN0 Message Slot 9 Standard ID0(C0MSL9SID0) CAN0 Message Slot 9 Data 5(C0MSL9DT5) CAN0 Message Slot 9 Data 3(C0MSL9DT3) CAN0 Message Slot 9 Data 1(C0MSL9DT1) CAN0 Message Slot 9 Data Length Register (C0MSL9DLC) CAN0 Message Slot 9 Extended ID1(C0MSL9EID1) CAN0 Message Slot 9 Standard ID1(C0MSL9SID1) H'0080 11A2 H'0080 11A4 H'0080 11A0 CAN0 Message Slot 10 Extended ID2(C0MSL10EID2) CAN0 Message Slot 10 Extended ID0(C0MSL10EID0) CAN0 Message Slot 10 Standard ID0(C0MSL10SID0) CAN0 Message Slot 10 Data Length Register (C0MSL10DLC) CAN0 Message Slot 10 Extended ID1(C0MSL10EID1) CAN0 Message Slot 10 Standard ID1(C0MSL10SID1) H'0080 11A6 CAN0 Message Slot 10 Data 0(C0MSL10DT0) CAN0 Message Slot 10 Data 1(C0MSL10DT1) +0 address +1 addressAddress Blank areas are reserved for future use. ADDRESS SPACE Figure 3.4.16 Register Mapping of the SFR Area (13)

3-25 Rev.1.0 D0 D7 D8 D15 H ’0080 11AA H ’0080 11A8 H ’0080 11AC H ’0080 11AE H ’0080 11B2 H ’0080 11BC H ’0080 11BA H ’0080 11B8 H ’0080 11B0 H ’0080 11B6 H ’0080 11BE H ’0080 11C2 H ’0080 11C4 H ’0080 11CA H ’0080 11C8 H ’0080 11C0 H ’0080 11C6 H ’0080 11CE H ’0080 11D2 H ’0080 11D0 CAN0 Message Slot 10 Data 6(C0MSL10DT6) CAN0 Message Slot 10 Timestamp (C0MSL10TSP) CAN0 Message Slot 10 Data 7(C0MSL10DT7) CAN0 Message Slot 10 Data 4(C0MSL10DT4) CAN0 Message Slot 10 Data 2(C0MSL10DT2) CAN0 Message Slot 10 Data 5(C0MSL10DT5) CAN0 Message Slot 10 Data 3(C0MSL10DT3) CAN0 Message Slot 11 Data 6(C0MSL11DT6) CAN0 Message Slot 11 Timestamp (C0MSL11TSP) CAN0 Message Slot 11 Data 7(C0MSL11DT7) CAN0 Message Slot 11 Data 4(C0MSL11DT4) CAN0 Message Slot 11 Data 2(C0MSL11DT2) CAN0 Message Slot 11 Data 0(C0MSL11DT0) CAN0 Message Slot 11 Extended ID2(C0MSL11EID2) CAN0 Message Slot 11 Extended ID0(C0MSL11EID0) CAN0 Message Slot 11 Standard ID0(C0MSL11SID0) CAN0 Message Slot 11 Data 5(C0MSL11DT5) CAN0 Message Slot 11 Data 3(C0MSL11DT3) CAN0 Message Slot 11 Data 1(C0MSL11DT1) CAN0 Message Slot 11 Data Length Register(C0MSL11DLC) CAN0 Message Slot 11 Extended ID1(C0MSL11EID1) CAN0 Message Slot 11 Standard ID1(C0MSL11SID1) CAN0 Message Slot 12 Data 6(C0MSL12DT6) CAN0 Message Slot 12 Timestamp (C0MSL12TSP) CAN0 Message Slot 12 Data 7(C0MSL12DT7) CAN0 Message Slot 12 Data 4(C0MSL12DT4) CAN0 Message Slot 12 Data 2(C0MSL12DT2) CAN0 Message Slot 12 Data 0(C0MSL12DT0) CAN0 Message Slot 12 Extended ID2(C0MSL12EID2) CAN0 Message Slot 12 Extended ID0(C0MSL12EID0) CAN0 Message Slot 12 Standard ID0(C0MSL12SID0) CAN0 Message Slot 12 Data 5(C0MSL12DT5) CAN0 Message Slot 12 Data 3(C0MSL12DT3) CAN0 Message Slot 12 Data 1(C0MSL12DT1) CAN0 Message Slot 12 Data Length Register(C0MSL12DLC) CAN0 Message Slot 12 Extended ID1(C0MSL12EID1) CAN0 Message Slot 12 Standard ID1(C0MSL12SID1) CAN0 Message Slot 13 Extended ID0(C0MSL13EID0) CAN0 Message Slot 13 Standard ID0(C0MSL13SID0) CAN0 Message Slot 13 Extended ID1(C0MSL13EID1) CAN0 Message Slot 13 Standard ID1(C0MSL13SID1) H ’0080 11D6 H ’0080 11D8 H ’0080 11DA H ’0080 11DE H ’0080 11E0 H ’0080 11E6 H ’0080 11E4 H ’0080 11DC H ’0080 11E2 H ’0080 11D4 H ’0080 11E8 H ’0080 11EA H ’0080 11EE H ’0080 11F0 H ’0080 11F6 H ’0080 11F4 H ’0080 11EC H ’0080 11F2 H ’0080 11F8 H ’0080 11FA H ’0080 11FE H ’0080 11FC CAN0 Message Slot 14 Data 6(C0MSL14DT6) CAN0 Message Slot 14 Timestamp (C0MSL14TSP) CAN0 Message Slot 14 Data 7(C0MSL14DT7) CAN0 Message Slot 14 Data 4(C0MSL14DT4) CAN0 Message Slot 14 Data 2(C0MSL14DT2) CAN0 Message Slot 14 Data 0(C0MSL14DT0) CAN0 Message Slot 14 Extended ID2(C0MSL14EID2) CAN0 Message Slot 14 Extended ID0(C0MSL14EID0) CAN0 Message Slot 14 Standard ID0(C0MSL14SID0) CAN0 Message Slot 14 Data 5(C0MSL14DT5) CAN0 Message Slot 14 Data 3(C0MSL14DT3) CAN0 Message Slot 14 Data 1(C0MSL14DT1) CAN0 Message Slot 14 Data Length Register(C0MSL14DLC) CAN0 Message Slot 14 Extended ID1(C0MSL14EID1) CAN0 Message Slot 14 Standard ID1(C0MSL14SID1) CAN0 Message Slot 13 Data 6(C0MSL13DT6) CAN0 Message Slot 13 Timestamp (C0MSL13TSP) CAN0 Message Slot 13 Data 7(C0MSL13DT7) CAN0 Message Slot 13 Data 4(C0MSL13DT4) CAN0 Message Slot 13 Data 2(C0MSL13DT2) CAN0 Message Slot 13 Data 0(C0MSL13DT0) CAN0 Message Slot 13 Extended ID2(C0MSL13EID2) CAN0 Message Slot 13 Data 5(C0MSL13DT5) CAN0 Message Slot 13 Data 3(C0MSL13DT3) CAN0 Message Slot 13 Data 1(C0MSL13DT1) CAN0 Message Slot 15 Data 6(C0MSL15DT6) CAN0 Message Slot 15 Timestamp (C0MSL15TSP) CAN0 Message Slot 15 Data 7(C0MSL15DT7) CAN0 Message Slot 15 Data 4(C0MSL15DT4) CAN0 Message Slot 15 Data 2(C0MSL15DT2) CAN0 Message Slot 15 Data 0(C0MSL15DT0) CAN0 Message Slot 15 Extended ID2(C0MSL15EID2) CAN0 Message Slot 15 Extended ID0(C0MSL15EID0) CAN0 Message Slot 15 Standard ID0(C0MSL15SID0) CAN0 Message Slot 15 Data 5(C0MSL15DT5) CAN0 Message Slot 15 Data 3(C0MSL15DT3) CAN0 Message Slot 15 Data 1(C0MSL15DT1) CAN0 Message Slot 15 Data Length Register(C0MSL15DLC) CAN0 Message Slot 15 Extended ID1(C0MSL15EID1) CAN0 Message Slot 15 Standard ID1(C0MSL15SID1) CAN0 Message Slot 13 Data Length Register(C0MSL13DLC) H ’0080 11CC H ’0080 11B4 +0 address +1 addressAddress Blank areas are reserved for future use. ADDRESS SPACE Figure 3.4.17 Register Mapping of the SFR Area (14)

3-26 Rev.1.0 D0 D7 D8 D15 H ’0080 1434 H ’0080 1432 H ’0080 1438 H ’0080 1436 H ’0080 143C H ’0080 143A H ’0080 1454 H ’0080 1458 H ’0080 1456 H ’0080 1452 H ’0080 145A CAN1 Configuration Register (CAN1CONF) CAN1 Global Mask Register Standard ID0 (C1GMSKS0) CAN1 Local Mask Register A Standard ID0 (C1LMSKAS0) H ’0080 1400 H ’0080 1402 H ’0080 1404 H ’0080 1408 H ’0080 140A H ’0080 1410 H ’0080 140E H ’0080 1406 H ’0080 1428 H ’0080 142C H ’0080 1430 H ’0080 142E H ’0080 142A H ’0080 145C H ’0080 140C H ’0080 1450 CAN1 Control Register (CAN1CNT) CAN1 Extended ID Register (CAN1EXTID) CAN1 Timestamp Count Register (CAN1TSTMP) CAN1 Slot Interrupt Status Register (CAN1SLIST) CAN1 Message Slot 3 Control Register (C1MSL3CNT)CAN1 Message Slot 2 Control Register (C1MSL2CNT) CAN1 Message Slot 4 Control Register (C1MSL4CNT) CAN1 Status Register (CAN1STAT) CAN1 Receive Error Count Register (CAN1REC) CAN1 Transmit Error Count Register (CAN1TEC) CAN1 Message Slot 0 Control Register (C1MSL0CNT) CAN1 Message Slot 1 Control Register (C1MSL1CNT) CAN1 Message Slot 5 Control Register (C1MSL5CNT) CAN1 Message Slot 7 Control Register (C1MSL7CNT) CAN1 Message Slot 9 Control Register (C1MSL9CNT) CAN1 Message Slot 11 Control Register (C1MSL11CNT) CAN1 Message Slot 13 Control Register (C1MSL13CNT) CAN1 Message Slot 15 Control Register (C1MSL15CNT) CAN1 Message Slot 6 Control Register (C1MSL6CNT) CAN1 Message Slot 8 Control Register (C1MSL8CNT) CAN1 Message Slot 10 Control Register (C1MSL10CNT) CAN1 Message Slot 12 Control Register (C1MSL12CNT) CAN1 Message Slot 14 Control Register (C1MSL14CNT) H ’0080 1412 CAN1 Error Interrupt Status Register (CAN1ERIST)CAN1 Error Interrupt Mask Register (CAN1ERIMK)H ’0080 1414 H ’0080 1416 CAN1 Baud Rate Prescaler (CAN1BRP) H ’0080 145E CAN1 Global Mask Register Standard ID1 (C1GMSKS1) CAN1 Global Mask Register Extended ID0 (C1GMSKE0) CAN1 Global Mask Register Extended ID1 (C1GMSKE1) CAN1 Global Mask Register Extended ID2 (C1GMSKE2) CAN1 Local Mask Register A Standard ID1 (C1LMSKAS1) CAN1 Local Mask Register A Extended ID0 (C1LMSKAE0) CAN1 Local Mask Register A Extended ID1 (C1LMSKAE1) CAN1 Local Mask Register A Extended ID2 (C1LMSKAE2) CAN1 Local Mask Register B Standard ID0 (C1LMSKBS0) CAN1 Local Mask Register B Standard ID1 (C1LMSKBS1) CAN1 Local Mask Register B Extended ID0 (C1LMSKBE0) CAN1 Local Mask Register B Extended ID1 (C1LMSKBE1) CAN1 Local Mask Register B Extended ID2 (C1LMSKBE2) CAN1 Slot Interrupt Mask Register (CAN1SLIMK) +0 address +1 addressAddress Blank areas are reserved for future use. ADDRESS SPACE Figure 3.4.18 Register Mapping of the SFR Area (15)

3-27 Rev.1.0 D0 D7 D8 D15 H'0080 1502 H'0080 1504 H'0080 150C H'0080 150E H'0080 1512 H'0080 1514 H'0080 1516 H'0080 1510 H'0080 1508 H'0080 1506 H'0080 150A CAN1 Message Slot 0 Extended ID0(C1MSL0EID0) CAN1 Message Slot 0 Extended ID2(C1MSL0EID2) CAN1 Message Slot 0 Data 0(C1MSL0DT0) CAN1 Message Slot 0 Data 2(C1MSL0DT2) CAN1 Message Slot 0 Data 4(C1MSL0DT4) CAN1 Message Slot 0 Extended ID1(C1MSL0EID1) CAN1 Message Slot 0 Data Length Register (C1MSL0DLC) CAN1 Message Slot 0 Data 1(C1MSL0DT1) CAN1 Message Slot 0 Data 3(C1MSL0DT3) CAN1 Message Slot 0 Data 5(C1MSL0DT5) CAN1 Message Slot 0 Data 6(C1MSL0DT6) CAN1 Message Slot 0 Data 7(C1MSL0DT7) CAN1 Message Slot 0 Timestamp (C1MSL0TSP) CAN1 Message Slot 1 Standard ID0(C1MSL1SID0) CAN1 Message Slot 1 Extended ID0(C1MSL1EID0) CAN1 Message Slot 1 Extended ID2(C1MSL1EID2) CAN1 Message Slot 1 Data 0(C1MSL1DT0) CAN1 Message Slot 1 Standard ID1(C1MSL1SID1) CAN1 Message Slot 1 Extended ID1(C1MSL1EID1) CAN1 Message Slot 1 Data Length Register (C1MSL1DLC) CAN1 Message Slot 1 Data 1(C1MSL1DT1) CAN1 Message Slot 1 Data 3(C1MSL1DT3) CAN1 Message Slot 1 Data 5(C1MSL1DT5) CAN1 Message Slot 1 Data 2(C1MSL1DT2) CAN1 Message Slot 1 Data 4(C1MSL1DT4) H'0080 1518 H'0080 151A H'0080 151E H'0080 1520 H'0080 1522 H'0080 1526 H'0080 1528 H'0080 152E H'0080 152C H'0080 1524 H'0080 152A CAN1 Message Slot 2 Data 6(C1MSL2DT6) CAN1 Message Slot 2 Timestamp (C1MSL2TSP) CAN1 Message Slot 2 Data 7(C1MSL2DT7) H'0080 151C CAN1 Message Slot 2 Data 4(C1MSL2DT4) CAN1 Message Slot 2 Data 2(C1MSL2DT2) CAN1 Message Slot 2 Data 0(C1MSL2DT0) CAN1 Message Slot 2 Extended ID2(C1MSL2EID2) CAN1 Message Slot 2 Extended ID0(C1MSL2EID0) CAN1 Message Slot 2 Standard ID0(C1MSL2SID0) CAN1 Message Slot 1 Timestamp (C1MSL1TSP) CAN1 Message Slot 1 Data 6(C1MSL1DT6) CAN1 Message Slot 2 Data 5(C1MSL2DT5) CAN1 Message Slot 2 Data 3(C1MSL2DT3) CAN1 Message Slot 2 Data 1(C1MSL2DT1) CAN1 Message Slot 2 Data Length Register(C1MSL2DLC) CAN1 Message Slot 2 Extended ID1(C1MSL2EID1) CAN1 Message Slot 2 Standard ID1(C1MSL2SID1) CAN1 Message Slot 1 Data 7(C1MSL1DT7) H'0080 1530 H'0080 1532 H'0080 1536 H'0080 1538 H'0080 153E H'0080 153C H'0080 1534 H'0080 153A CAN1 Message Slot 3 Data 6(C1MSL3DT6) CAN1 Message Slot 3 Timestamp (C1MSL3TSP) CAN1 Message Slot 3 Data 7(C1MSL3DT7) CAN1 Message Slot 3 Data 4(C1MSL3DT4) CAN1 Message Slot 3 Data 2(C1MSL3DT2) CAN1 Message Slot 3 Data 0(C1MSL3DT0) CAN1 Message Slot 3 Extended ID2(C1MSL3EID2) CAN1 Message Slot 3 Extended ID0(C1MSL3EID0) CAN1 Message Slot 3 Standard ID0(C1MSL3SID0) CAN1 Message Slot 3 Data 5(C1MSL3DT5) CAN1 Message Slot 3 Data 3(C1MSL3DT3) CAN1 Message Slot 3 Data 1(C1MSL3DT1) CAN1 Message Slot 3 Data Length Register(C1MSL3DLC) CAN1 Message Slot 3 Extended ID1(C1MSL3EID1) CAN1 Message Slot 3 Standard ID1(C1MSL3SID1) H'0080 1540 H'0080 1542 H'0080 1546 H'0080 1548 H'0080 154E H'0080 154C H'0080 1544 H'0080 154A CAN1 Message Slot 4 Data 6(C1MSL4DT6) CAN1 Message Slot 4 Timestamp (C1MSL4TSP) CAN1 Message Slot 4 Data 7(C1MSL4DT7) CAN1 Message Slot 4 Data 4(C1MSL4DT4) CAN1 Message Slot 4 Data 2(C1MSL4DT2) CAN1 Message Slot 4 Data 0(C1MSL4DT0) CAN1 Message Slot 4 Extended ID2(C1MSL4EID2) CAN1 Message Slot 4 Extended ID0(C1MSL4EID0) CAN1 Message Slot 4 Standard ID0(C1MSL4SID0) CAN1 Message Slot 4 Data 5(C1MSL4DT5) CAN1 Message Slot 4 Data 3(C1MSL4DT3) CAN1 Message Slot 4 Data 1(C1MSL4DT1) CAN1 Message Slot 4 Data Length Register(C1MSL4DLC) CAN1 Message Slot 4 Extended ID1(C1MSL4EID1) CAN1 Message Slot 4 Standard ID1(C1MSL4SID1) H'0080 1550 H'0080 1552 CAN1 Message Slot 5 Extended ID0(C1MSL5EID0) CAN1 Message Slot 5 Standard ID0(C1MSL5SID0) CAN1 Message Slot 5 Extended ID1(C1MSL5EID1) CAN1 Message Slot 5 Standard ID1(C1MSL5SID1) H'0080 1500 CAN1 Message Slot 0 Standard ID1(C1MSL0SID1)CAN1 Message Slot 0 Standard ID0(C1MSL0SID0) +0 address +1 addressAddress Blank areas are reserved for future use. ADDRESS SPACE Figure 3.4.19 Register Mapping of the SFR Area (16)

3-28 Rev.1.0 D0 D7 D8 D15 H ’0080 1556 H ’0080 1558 H ’0080 155E H ’0080 155C H ’0080 1554 H ’0080 155A H ’0080 1560 H ’0080 1562 H ’0080 1566 H ’0080 1568 H ’0080 156E H ’0080 156C H ’0080 1564 H ’0080 156A H ’0080 1570 H ’0080 1572 H ’0080 1576 H ’0080 1574 CAN1 Message Slot 5 Data 6(C1MSL5DT6) CAN1 Message Slot 5 Timestamp (C1MSL5TSP) CAN1 Message Slot 5 Data 7(C1MSL5DT7) CAN1 Message Slot 5 Data 4(C1MSL5DT4) CAN1 Message Slot 5 Data 2(C1MSL5DT2) CAN1 Message Slot 5 Data 0(C1MSL5DT0) CAN1 Message Slot 5 Extended ID2(C1MSL5EID2) CAN1 Message Slot 5 Data 5(C1MSL5DT5) CAN1 Message Slot 5 Data 3(C1MSL5DT3) CAN1 Message Slot 5 Data 1(C1MSL5DT1) CAN1 Message Slot 5 Data Length Register (C1MSL5DLC) CAN1 Message Slot 6 Data 6(C1MSL6DT6) CAN1 Message Slot 6 Timestamp (C1MSL6TSP) CAN1 Message Slot 6 Data 7(C1MSL6DT7) CAN1 Message Slot 6 Data 4(C1MSL6DT4) CAN1 Message Slot 6 Data 2(C1MSL6DT2) CAN1 Message Slot 6 Data 0(C1MSL6DT0) CAN1 Message Slot 6 Extended ID2(C1MSL6EID2) CAN1 Message Slot 6 Extended ID0(C1MSL6EID0) CAN1 Message Slot 6 Standard ID0(C1MSL6SID0) CAN1 Message Slot 6 Data 5(C1MSL6DT5) CAN1 Message Slot 6 Data 3(C1MSL6DT3) CAN1 Message Slot 6 Data 1(C1MSL6DT1) CAN1 Message Slot 6 Data Length Register (C1MSL6DLC) CAN1 Message Slot 6 Extended ID1(C1MSL6EID1) CAN1 Message Slot 6 Standard ID1(C1MSL6SID1) CAN1 Message Slot 7 Data 0(C1MSL7DT0) CAN1 Message Slot 7 Extended ID2(C1MSL7EID2) CAN1 Message Slot 7 Extended ID0(C1MSL7EID0) CAN1 Message Slot 7 Standard ID0(C1MSL7SID0) CAN1 Message Slot 7 Data 1(C1MSL7DT1) CAN1 Message Slot 7 Data Length Register (C1MSL7DLC) CAN1 Message Slot 7 Extended ID1(C1MSL7EID1) CAN1 Message Slot 7 Standard ID1(C1MSL7SID1) H ’0080 157A H ’0080 157C H ’0080 157E H ’0080 1582 H ’0080 1584 H ’0080 158A H ’0080 1588 H ’0080 1580 H ’0080 1586 H ’0080 1578 H ’0080 158C H ’0080 158E H ’0080 1592 H ’0080 1594 H ’0080 159A H ’0080 1598 H ’0080 1590 H ’0080 1596 H ’0080 159C H ’0080 159E CAN1 Message Slot 8 Data 6(C1MSL8DT6) CAN1 Message Slot 8 Timestamp (C1MSL8TSP) CAN1 Message Slot 8 Data 7(C1MSL8DT7) CAN1 Message Slot 8 Data 4(C1MSL8DT4) CAN1 Message Slot 8 Data 2(C1MSL8DT2) CAN1 Message Slot 8 Data 0(C1MSL8DT0) CAN1 Message Slot 8 Extended ID2(C1MSL8EID2) CAN1 Message Slot 8 Extended ID0(C1MSL8EID0) CAN1 Message Slot 8 Standard ID0(C1MSL8SID0) CAN1 Message Slot 8 Data 5(C1MSL8DT5) CAN1 Message Slot 8 Data 3(C1MSL8DT3) CAN1 Message Slot 8 Data 1(C1MSL8DT1) CAN1 Message Slot 8 Data Length Register (C1MSL8DLC) CAN1 Message Slot 8 Extended ID1(C1MSL8EID1) CAN1 Message Slot 8 Standard ID1(C1MSL8SID1) CAN1 Message Slot 7 Data 6(C1MSL7DT6) CAN1 Message Slot 7 Timestamp (C1MSL7TSP) CAN1 Message Slot 7 Data 7(C1MSL7DT7) CAN1 Message Slot 7 Data 4(C1MSL7DT4) CAN1 Message Slot 7 Data 2(C1MSL7DT2) CAN1 Message Slot 7 Data 5(C1MSL7DT5) CAN1 Message Slot 7 Data 3(C1MSL7DT3) CAN1 Message Slot 9 Data 6(C1MSL9DT6) CAN1 Message Slot 9 Timestamp (C1MSL9TSP) CAN1 Message Slot 9 Data 7(C1MSL9DT7) CAN1 Message Slot 9 Data 4(C1MSL9DT4) CAN1 Message Slot 9 Data 2(C1MSL9DT2) CAN1 Message Slot 9 Data 0(C1MSL9DT0) CAN1 Message Slot 9 Extended ID2(C1MSL9EID2) CAN1 Message Slot 9 Extended ID0(C1MSL9EID0) CAN1 Message Slot 9 Standard ID0(C1MSL9SID0) CAN1 Message Slot 9 Data 5(C1MSL9DT5) CAN1 Message Slot 9 Data 3(C1MSL9DT3) CAN1 Message Slot 9 Data 1(C1MSL9DT1) CAN1 Message Slot 9 Data Length Register (C1MSL9DLC) CAN1 Message Slot 9 Extended ID1(C1MSL9EID1) CAN1 Message Slot 9 Standard ID1(C1MSL9SID1) H ’0080 15A2 H ’0080 15A4 H ’0080 15A0 CAN1 Message Slot 10 Extended ID2(C1MSL10EID2) CAN1 Message Slot 10 Extended ID0(C1MSL10EID0) CAN1 Message Slot 10 Standard ID0(C1MSL10SID0) CAN1 Message Slot 10 Data Length Register (C1MSL10DLC) CAN1 Message Slot 10 Extended ID1(C1MSL10EID1) CAN1 Message Slot 10 Standard ID1(C1MSL10SID1) H ’0080 15A6 CAN1 Message Slot 10 Data 0(C1MSL10DT0) CAN1 Message Slot 10 Data 1(C1MSL10DT1) +0 address +1 addressAddress Blank areas are reserved for future use. ADDRESS SPACE Figure 3.4.20 Register Mapping of the SFR Area (17)

3-29 Rev.1.0 D0 D7 D8 D15 H ’0080 15AA H ’0080 15A8 H ’0080 15AC H ’0080 15AE H ’0080 15B2 H ’0080 15BC H ’0080 15BA H ’0080 15B8 H ’0080 15B0 H ’0080 15B6 H ’0080 15BE H ’0080 15C2 H ’0080 15C4 H ’0080 15CA H ’0080 15C8 H ’0080 15C0 H ’0080 15C6 H ’0080 15CE H ’0080 15D2 H ’0080 15D0 CAN1 Message Slot 10 Data 6(C1MSL10DT6) CAN1 Message Slot 10 Timestamp (C1MSL10TSP) CAN1 Message Slot 10 Data 7(C1MSL10DT7) CAN1 Message Slot 10 Data 4(C1MSL10DT4) CAN1 Message Slot 10 Data 2(C1MSL10DT2) CAN1 Message Slot 10 Data 5(C1MSL10DT5) CAN1 Message Slot 10 Data 3(C1MSL10DT3) CAN1 Message Slot 11 Data 6(C1MSL11DT6) CAN1 Message Slot 11 Timestamp (C1MSL11TSP) CAN1 Message Slot 11 Data 7(C1MSL11DT7) CAN1 Message Slot 11 Data 4(C1MSL11DT4) CAN1 Message Slot 11 Data 2(C1MSL11DT2) CAN1 Message Slot 11 Data 0(C1MSL11DT0) CAN1 Message Slot 11 Extended ID2(C1MSL11EID2) CAN1 Message Slot 11 Extended ID0(C1MSL11EID0) CAN1 Message Slot 11 Standard ID0(C1MSL11SID0) CAN1 Message Slot 11 Data 5(C1MSL11DT5) CAN1 Message Slot 11 Data 3(C1MSL11DT3) CAN1 Message Slot 11 Data 1(C1MSL11DT1) CAN1 Message Slot 11 Data Length Register (C1MSL11DLC) CAN1 Message Slot 11 Extended ID1(C1MSL11EID1) CAN1 Message Slot 11 Standard ID1(C1MSL11SID1) CAN1 Message Slot 12 Data 6(C1MSL12DT6) CAN1 Message Slot 12 Timestamp (C1MSL12TSP) CAN1 Message Slot 12 Data 7(C1MSL12DT7) CAN1 Message Slot 12 Data 4(C1MSL12DT4) CAN1 Message Slot 12 Data 2(C1MSL12DT2) CAN1 Message Slot 12 Data 0(C1MSL12DT0) CAN1 Message Slot 12 Extended ID2(C1MSL12EID2) CAN1 Message Slot 12 Extended ID0(C1MSL12EID0) CAN1 Message Slot 12 Standard ID0(C1MSL12SID0) CAN1 Message Slot 12 Data 5(C1MSL12DT5) CAN1 Message Slot 12 Data 3(C1MSL12DT3) CAN1 Message Slot 12 Data 1(C1MSL12DT1) CAN1 Message Slot 12 Data Length Register (C1MSL12DLC) CAN1 Message Slot 12 Extended ID1(C1MSL12EID1) CAN1 Message Slot 12 Standard ID1(C1MSL12SID1) CAN1 Message Slot 13 Extended ID0(C1MSL13EID0) CAN1 Message Slot 13 Standard ID0(C1MSL13SID0) CAN1 Message Slot 13 Extended ID1(C1MSL13EID1) CAN1 Message Slot 13 Standard ID1(C1MSL13SID1) H ’0080 15D6 H ’0080 15D8 H ’0080 15DA H ’0080 15DE H ’0080 15E0 H ’0080 15E6 H ’0080 15E4 H ’0080 15DC H ’0080 15E2 H ’0080 15D4 H ’0080 15E8 H ’0080 15EA H ’0080 15EE H ’0080 15F0 H ’0080 15F6 H ’0080 15F4 H ’0080 15EC H ’0080 15F2 H ’0080 15F8 H ’0080 15FA H ’0080 15FE H ’0080 15FC CAN1 Message Slot 14 Data 6(C1MSL14DT6) CAN1 Message Slot 14 Timestamp (C1MSL14TSP) CAN1 Message Slot 14 Data 7(C1MSL14DT7) CAN1 Message Slot 14 Data 4(C1MSL14DT4) CAN1 Message Slot 14 Data 2(C1MSL14DT2) CAN1 Message Slot 14 Data 0(C1MSL14DT0) CAN1 Message Slot 14 Extended ID2(C1MSL14EID2) CAN1 Message Slot 14 Extended ID0(C1MSL14EID0) CAN1 Message Slot 14 Standard ID0(C1MSL14SID0) CAN1 Message Slot 14 Data 5(C1MSL14DT5) CAN1 Message Slot 14 Data 3(C1MSL14DT3) CAN1 Message Slot 14 Data 1(C1MSL14DT1) CAN1 Message Slot 14 Data Length Register (C1MSL14DLC) CAN1 Message Slot 14 Extended ID1(C1MSL14EID1) CAN1 Message Slot 14 Standard ID1(C1MSL14SID1) CAN1 Message Slot 13 Data 6(C1MSL13DT6) CAN1 Message Slot 13 Timestamp (C1MSL13TSP) CAN1 Message Slot 13 Data 7(C1MSL13DT7) CAN1 Message Slot 13 Data 4(C1MSL13DT4) CAN1 Message Slot 13 Data 2(C1MSL13DT2) CAN1 Message Slot 13 Data 0(C1MSL13DT0) CAN1 Message Slot 13 Extended ID2(C1MSL13EID2) CAN1 Message Slot 13 Data 5(C1MSL13DT5) CAN1 Message Slot 13 Data 3(C1MSL13DT3) CAN1 Message Slot 13 Data 1(C1MSL13DT1) CAN1 Message Slot 15 Data 6(C1MSL15DT6) CAN1 Message Slot 15 Timestamp (C1MSL15TSP) CAN1 Message Slot 15 Data 7(C1MSL15DT7) CAN1 Message Slot 15 Data 4(C1MSL15DT4) CAN1 Message Slot 15 Data 2(C1MSL15DT2) CAN1 Message Slot 15 Data 0(C1MSL15DT0) CAN1 Message Slot 15 Extended ID2(C1MSL15EID2) CAN1 Message Slot 15 Extended ID0(C1MSL15EID0) CAN1 Message Slot 15 Standard ID0(C1MSL15SID0) CAN1 Message Slot 15 Data 5(C1MSL15DT5) CAN1 Message Slot 15 Data 3(C1MSL15DT3) CAN1 Message Slot 15 Data 1(C1MSL15DT1) CAN1 Message Slot 15 Data Length Register (C1MSL15DLC) CAN1 Message Slot 15 Extended ID1(C1MSL15EID1) CAN1 Message Slot 15 Standard ID1(C1MSL15SID1) CAN1 Message Slot 13 Data Length Register (C1MSL13DLC) H ’0080 15CC H ’0080 15B4 +0 address +1 addressAddress Blank areas are reserved for future use. ADDRESS SPACE Figure 3.4.21 Register Mapping of the SFR Area (18)

3-30 Rev.1.0 D0 D7 D8 D15 H ’0080 1808 TPD Counter (TPDCT) TPD Measurement Register 0 (TPDMR0) H ’0080 180E H ’0080 1810 H ’0080 1812 H ’0080 1814 H ’0080 1816 H ’0080 181A H ’0080 181C H ’0080 181E H ’0080 1830 H ’0080 1832 H ’0080 1840 H ’0080 1842 H ’0080 1844 H ’0080 1846 H ’0080 184C PD Calculation Interrupt Control Register (PDICR) Position Detection Accuracy Select Register (PDASR) Prescaler Register 0C(PRS0C) H ’0080 184E H ’0080 1860 H ’0080 1862 H ’0080 1864 H ’0080 1866 SMSB Control Register 0 (SMSBCR0) ABD0 Compare Register (ABD0CM) PNEWLT0 Register (PNEWLT0) H ’0080 186E H ’0080 1872 H ’0080 1876 H ’0080 1878 H ’0080 187A H ’0080 1800 H ’0080 1806 H ’0080 1802 H ’0080 1804 H ’0080 1818 H ’0080184A H ’0080 186A H ’0080 186C H ’0080 1874 Prescaler Register B (PRSB) TIN Input Processing Control Register (TINPDCR) TIN Interrupt Control Register (TINPDICR)TIN Interrupt Status Register (TINPDIST) TPD Control Register (TPDCR) TPD Measurement Register 1 (TPDMR1) TPD Measurement Register 2 (TPDMR2) TPD Measurement Register 3 (TPDMR3) TPD Measurement Register 4 (TPDMR4) TPD Measurement Register 5 (TPDMR5) TPD Measurement Register 6 (TPDMR6) TPD Measurement Register 7 (TPDMR7) H ’0080 1848 H ’0080 1870 H ’0080 1868 PD Calculation Interrupt Status Register (PDIST) TEP0P Control Register (TEP0PCR) TEP0M Control Register (TEP0MCR) TEP0P Counter (TEP0PCT) TEP0M Counter (TEP0MCT) PD0 Data Update Disable Event Select Register (PDNSEL0R) AB0 Mask Register (ABD0MK) PICH0 Compare Register (PITCH0CMR) POLDLT0 Register (POLDLT0) MOLDLT0 Register (MOLDLT0) MNEWLT0 Register (MNEWLT0) PSUBLT0 Register (PSUBLT0) MSUBLT0 Register (MSUBLT0) PRLT0 Register (PRLT0) SNEWLT0 Register (SNEWLT0) MRLT0 Register (MRLT0) FDLT0 Register (FDLT0) ABDLT0 Register (ABDLT0) PITCHLT0 Register (PITCHLT0) RSUMLT0 Register (RSUMLT0) SSLT0 Register (SSLT0) PD0 Data Update Control Register (PDNCNT0R) S Error 0 Detection Range Select Register (SNEW0MK) DMA Transfer Request Cause Select Register (DMAREQSL) Note: Enclosed in are the intermediate registers used for arithmetic operations. Do not access these registers for read/write. Prescaler Register A (PRSA) DACNT Reload Register A (DACNTRL) DACNT Control Register A (DACNTCR) DACNT Counter (DACNT) +0 address +1 addressAddress Blank areas are reserved for future use. ADDRESS SPACE Figure 3.4.22 Register Mapping of the SFR Area (19)

3-31 Rev.1.0 D0 D7 D8 D15 H ’0080 1888 H ’0080 188A H ’0080 188C H ’0080 188E H ’0080 18A0 H ’0080 18A4 H ’0080 18A6 H ’0080 18A8 H ’0080 18AA H ’0080 18AC H ’0080 18B0 H ’0080 18B2 H ’0080 18B4 H ’0080 18B6 ABDLT1 Register (ABDLT1) H ’0080 1880 H ’0080 1886 H ’0080 1882 H ’0080 1884 H ’0080 18A2 Prescaler Register 1C (PRS1C) SMSB Control Register 1 (SMSBCR1) TEP1P Control Register (TEP1PCR) TEP1M Control Register (TEP1MCR) SNEWLT1 Register (SNEWLT1) FDLT1 Register (FDLT1) PRLT1 Register (PRLT1) PITCHL1 Register (PITCHLT1) MRLT1 Register (MRTL1) PNEWLT1 Register (PNEWLT1) POLDT1 Register (POLDLT1) MNEWLT1 Register (MNEWLT1) MOLDLT1 Register (MOLDLT1) PSUBLT1 Register (PSUBLT1) MSUBLT1 Register (MSUBLT1) RSUMLT1 Register (RSUMLT1) H ’0080 18AE H ’0080 18BA TEP1P Counter (TEP1PCT) TEP1M Counter (TEP1MCT) PD1 Data Update Disable Event Select Register (PDNSEL1R)PD1 Data Update Control Register (PDNCNT1R) ABD1 Mask Register (ABD1MK) S Error 1 Detection Range Select Register (SNEW1MK) ABD1 Compare Register (ABD1CM) PITCH1 Compare Register (PITCH1CMR) SSLT1 Register (SSLT1) H ’0080 18B8 +0 address +1 addressAddress Blank areas are reserved for future use. Note: Enclosed in are the intermediate registers used for arithmetic operations. Do not access these registers for read/write. ADDRESS SPACE Figure 3.4.23 Register Mapping of the SFR Area (20)

3-32 Rev.1.0 D0 D7 D8 D15 H ’0080 1C7A H ’0080 1C78 H ’0080 1C7C H ’0080 1D00 H ’0080 1D0A H ’0080 1D08 H ’0080 1D06 H ’0080 1D04 H ’0080 1D0C H ’0080 1D10 H ’0080 1D12 H ’0080 1D18 H ’0080 1D16 H ’0080 1D0E H ’0080 1D14 H ’0080 1D1C H ’0080 1D20 H ’0080 1D1E H ’0080 1D24 H ’0080 1D26 H ’0080 1D28 H ’0080 1D2C H ’0080 1D2E H ’0080 1D34 H ’0080 1D32 H ’0080 1D2A H ’0080 1D30 H ’0080 1D22 H ’0080 1D36 H ’0080 1D38 H ’0080 1D3C H ’0080 1D3E H ’0080 1D44 H ’0080 1D42 H ’0080 1D3A H ’0080 1D40 H ’0080 1D46 H ’0080 1D48 H ’0080 1D4C H ’0080 1D4A H ’0080 1D1A H ’0080 1D02 D-A0 Conversion Register (DA0CNV) D-A1 Conversion Register (DA1CNV) D-A Conversion Register (DACR) D-A0 Data Register 0 (DA0DT0) D-A0 Data Register 1 (DA0DT1) D-A0 Data Register 2 (DA0DT2) D-A0 Data Register 4 (DA0DT4) D-A0 Data Register 3 (DA0DT3) D-A0 Data Register 6 (DA0DT6) D-A0 Data Register 5 (DA0DT5) D-A0 Data Register 7 (DA0DT7) D-A0 Data Register 8 (DA0DT8) D-A0 Data Register 9 (DA0DT9) D-A0 Data Register 10 (DA0DT10) D-A0 Data Register 11 (DA0DT11) D-A0 Data Register 12 (DA0DT12) D-A0 Data Register 13 (DA0DT13) D-A0 Data Register 14 (DA0DT14) D-A0 Data Register 15 (DA0DT15) D-A0 Data Register 16 (DA0DT16) D-A0 Data Register 17 (DA0DT17) D-A0 Data Register 18 (DA0DT18) D-A0 Data Register 19 (DA0DT19) D-A0 Data Register 20 (DA0DT20) D-A0 Data Register 21 (DA0DT21) D-A0 Data Register 22 (DA0DT22) D-A0 Data Register 23 (DA0DT23) D-A0 Data Register 24 (DA0DT24) D-A0 Data Register 25 (DA0DT25) D-A0 Data Register 26 (DA0DT26) D-A0 Data Register 27 (DA0DT27) D-A0 Data Register 28 (DA0DT28) D-A0 Data Register 29 (DA0DT29) D-A0 Data Register 30 (DA0DT30) D-A0 Data Register 31 (DA0DT31) D-A0 Data Register 32 (DA0DT32) D-A0 Data Register 33 (DA0DT33) D-A0 Data Register 34 (DA0DT34) D-A0 Data Register 35 (DA0DT35) D-A0 Data Register 36 (DA0DT36) D-A0 Data Register 37 (DA0DT37) D-A0 Data Register 38 (DA0DT38) D-A0 Data Register 39 (DA0DT39) D-A0 Data Register 40 (DA0DT40) D-A0 Data Register 41 (DA0DT41) D-A0 Data Register 42 (DA0DT42) D-A0 Data Register 43 (DA0DT43) D-A0 Data Register 44 (DA0DT44) D-A0 Data Register 45 (DA0DT45) D-A0 Data Register 46 (DA0DT46) D-A0 Data Register 47 (DA0DT47) D-A0 Data Register 48 (DA0DT48) D-A0 Data Register 49 (DA0DT49) D-A0 Data Register 50 (DA0DT50) D-A0 Data Register 51 (DA0DT51) D-A0 Data Register 52 (DA0DT52) D-A0 Data Register 53 (DA0DT53) D-A0 Data Register 54 (DA0DT54) D-A0 Data Register 55 (DA0DT55) D-A0 Data Register 56 (DA0DT56) D-A0 Data Register 63 (DA0DT63)D-A0 Data Register 62 (DA0DT62) D-A0 Data Register 61 (DA0DT61)D-A0 Data Register 60 (DA0DT60) D-A0 Data Register 59 (DA0DT59)D-A0 Data Register 58 (DA0DT58) D-A0 Data Register 57 (DA0DT57) D-A0 Data Register 75 (DA0DT75)D-A0 Data Register 74 (DA0DT74) D-A0 Data Register 73 (DA0DT73)D-A0 Data Register 72 (DA0DT72) D-A0 Data Register 71 (DA0DT71)D-A0 Data Register 70 (DA0DT70) D-A0 Data Register 69 (DA0DT69)D-A0 Data Register 68 (DA0DT68) D-A0 Data Register 64 (DA0DT64) D-A0 Data Register 67 (DA0DT67) D-A0 Data Register 65 (DA0DT65) D-A0 Data Register 66 (DA0DT66) D-A0 Data Register 77 (DA0DT77)D-A0 Data Register 76 (DA0DT76) D-A0 Data Register 79 (DA0DT79)D-A0 Data Register 78 (DA0DT78)H ’0080 1D4E +0 address +1 addressAddress Blank areas are reserved for future use. ADDRESS SPACE Figure 3.4.24 Register Mapping of the SFR Area (21)

3-33 Rev.1.0 D0 D7 D8 D15 H'0080 1D52 H'0080 1D50 H'0080 1D54 H'0080 1D56 H'0080 1D60 H'0080 1D5E H'0080 1D5C H'0080 1D5A H'0080 1D62 H'0080 1D68 H'0080 1D6A H'0080 1D70 H'0080 1D6E H'0080 1D66 H'0080 1D6C H'0080 1D74 H'0080 1D78 H'0080 1D76 H'0080 1D7C H'0080 1D7E H'0080 1D80 H'0080 1D84 H'0080 1D86 H'0080 1D8C H'0080 1D8A H'0080 1D82 H'0080 1D88 H'0080 1D7A H'0080 1D8E H'0080 1D90 H'0080 1D94 H'0080 1D96 H'0080 1D9C H'0080 1D9A H'0080 1D92 H'0080 1D98 H'0080 1D9E H'0080 1DA0 H'0080 1DA4 H'0080 1DA2 H'0080 1D72 H'0080 1D58 D-A0 Data Register 80 (DA0DT80) D-A0 Data Register 82 (DA0DT82) D-A0 Data Register 84 (DA0DT84) D-A0 Data Register 90 (DA0DT90) D-A0 Data Register 91 (DA0DT91) D-A0 Data Register 92 (DA0DT92) D-A0 Data Register 94 (DA0DT94) D-A0 Data Register 93 (DA0DT93) D-A0 Data Register 96 (DA0DT96) D-A0 Data Register 95 (DA0DT95) D-A0 Data Register 97 (DA0DT97) D-A0 Data Register 98 (DA0DT98) D-A0 Data Register 99 (DA0DT99) D-A0 Data Register 100 (DA0DT100) D-A0 Data Register 101 (DA0DT101) D-A0 Data Register 102 (DA0DT102) D-A0 Data Register 103 (DA0DT103) D-A0 Data Register 104 (DA0DT104) D-A0 Data Register 105 (DA0DT105) D-A0 Data Register 106 (DA0DT106) D-A0 Data Register 107 (DA0DT107) D-A0 Data Register 108 (DA0DT108) D-A0 Data Register 109 (DA0DT109) D-A0 Data Register 110 (DA0DT110) D-A0 Data Register 111 (DA0DT111) D-A0 Data Register 112 (DA0DT112) D-A0 Data Register 113 (DA0DT113) D-A0 Data Register 114 (DA0DT114) D-A0 Data Register 115 (DA0DT115) D-A0 Data Register 116 (DA0DT116) D-A0 Data Register 117 (DA0DT117) D-A0 Data Register 118 (DA0DT118) D-A0 Data Register 119 (DA0DT119) D-A0 Data Register 120 (DA0DT120) D-A0 Data Register 121 (DA0DT121) D-A0 Data Register 122 (DA0DT122) D-A0 Data Register 123 (DA0DT123) D-A0 Data Register 124 (DA0DT124) D-A0 Data Register 125 (DA0DT125) D-A0 Data Register 126 (DA0DT126) D-A0 Data Register 127 (DA0DT127) D-A0 Data Register 128 (DA0DT128) D-A0 Data Register 129 (DA0DT129) D-A0 Data Register 130 (DA0DT130) D-A0 Data Register 131 (DA0DT131) D-A0 Data Register 132 (DA0DT132) D-A0 Data Register 133 (DA0DT133) D-A0 Data Register 134 (DA0DT134) D-A0 Data Register 135 (DA0DT135) D-A0 Data Register 136 (DA0DT136) D-A0 Data Register 137 (DA0DT137) D-A0 Data Register 138 (DA0DT138) D-A0 Data Register 139 (DA0DT139) D-A0 Data Register 140 (DA0DT140) D-A0 Data Register 141 (DA0DT141) D-A0 Data Register 142 (DA0DT142) D-A0 Data Register 143 (DA0DT143) D-A0 Data Register 144 (DA0DT144) D-A0 Data Register 145 (DA0DT145) D-A0 Data Register 146 (DA0DT146) D-A0 Data Register 153 (DA0DT153)D-A0 Data Register 152 (DA0DT152) D-A0 Data Register 151 (DA0DT151)D-A0 Data Register 150 (DA0DT150) D-A0 Data Register 149 (DA0DT149)D-A0 Data Register 148 (DA0DT148) D-A0 Data Register 147 (DA0DT147) D-A0 Data Register 165 (DA0DT165)D-A0 Data Register 164 (DA0DT164) D-A0 Data Register 163 (DA0DT163)D-A0 Data Register 162 (DA0DT162) D-A0 Data Register 161 (DA0DT161)D-A0 Data Register 160 (DA0DT160) D-A0 Data Register 159 (DA0DT159)D-A0 Data Register 158 (DA0DT158) D-A0 Data Register 154 (DA0DT154) D-A0 Data Register 157 (DA0DT157) D-A0 Data Register 155 (DA0DT155) D-A0 Data Register 156 (DA0DT156) D-A0 Data Register 167 (DA0DT167)D-A0 Data Register 166 (DA0DT166) D-A0 Data Register 169 (DA0DT169)D-A0 Data Register 168 (DA0DT168) H'0080 1DA6 H'0080 1DA8 D-A0 Data Register 81 (DA0DT81) D-A0 Data Register 83 (DA0DT83) D-A0 Data Register 85 (DA0DT85) D-A0 Data Register 86 (DA0DT86) D-A0 Data Register 88 (DA0DT88) D-A0 Data Register 87 (DA0DT87) D-A0 Data Register 89 (DA0DT89) H'0080 1D64 +0 address +1 addressAddress Blank areas are reserved for future use. ADDRESS SPACE Figure 3.4.25 Register Mapping of the SFR Area (22)

3-34 Rev.1.0 D0 D7 D8 D15 H'0080 1DAC H'0080 1DAA H'0080 1DAE H'0080 1DB0 H'0080 1DBA H'0080 1DB8 H'0080 1DB6 H'0080 1DB4 H'0080 1DBC H'0080 1DC2 H'0080 1DC4 H'0080 1DCA H'0080 1DC8 H'0080 1DC0 H'0080 1DC6 H'0080 1DCE H'0080 1DD2 H'0080 1DD0 H'0080 1DD6 H'0080 1DD8 H'0080 1DDA H'0080 1DDE H'0080 1DE0 H'0080 1DE6 H'0080 1DE4 H'0080 1DDC H'0080 1DE2 H'0080 1DD4 H'0080 1DE8 H'0080 1DEA H'0080 1DEE H'0080 1DF0 H'0080 1DF6 H'0080 1DF4 H'0080 1DEC H'0080 1DF2 H'0080 1DF8 H'0080 1DFA H'0080 1DFE H'0080 1DFC H'0080 1DCC H'0080 1DB2 D-A0 Data Register 170 (DA0DT170) D-A0 Data Register 172 (DA0DT172) D-A0 Data Register 174 (DA0DT174) D-A0 Data Register 180 (DA0DT180) D-A0 Data Register 181 (DA0DT181) D-A0 Data Register 182 (DA0DT182) D-A0 Data Register 184 (DA0DT184) D-A0 Data Register 183 (DA0DT183) D-A0 Data Register 186 (DA0DT186) D-A0 Data Register 185 (DA0DT185) D-A0 Data Register 187 (DA0DT187) D-A0 Data Register 188 (DA0DT188) D-A0 Data Register 189 (DA0DT189) D-A0 Data Register 190 (DA0DT190) D-A0 Data Register 191 (DA0DT191) D-A0 Data Register 192 (DA0DT192) D-A0 Data Register 193 (DA0DT193) D-A0 Data Register 194 (DA0DT194) D-A0 Data Register 195 (DA0DT195) D-A0 Data Register 196 (DA0DT196) D-A0 Data Register 197 (DA0DT197) D-A0 Data Register 198 (DA0DT198) D-A0 Data Register 199 (DA0DT199) D-A0 Data Register 200 (DA0DT200) D-A0 Data Register 201 (DA0DT201) D-A0 Data Register 202 (DA0DT202) D-A0 Data Register 203 (DA0DT203) D-A0 Data Register 204 (DA0DT204) D-A0 Data Register 205 (DA0DT205) D-A0 Data Register 206 (DA0DT206) D-A0 Data Register 207 (DA0DT207) D-A0 Data Register 208 (DA0DT208) D-A0 Data Register 209 (DA0DT209) D-A0 Data Register 210 (DA0DT210) D-A0 Data Register 211 (DA0DT211) D-A0 Data Register 212 (DA0DT212) D-A0 Data Register 213 (DA0DT213) D-A0 Data Register 214 (DA0DT214) D-A0 Data Register 215 (DA0DT215) D-A0 Data Register 216 (DA0DT216) D-A0 Data Register 217 (DA0DT217) D-A0 Data Register 218 (DA0DT218) D-A0 Data Register 219 (DA0DT219) D-A0 Data Register 220 (DA0DT220) D-A0 Data Register 221 (DA0DT221) D-A0 Data Register 222 (DA0DT222) D-A0 Data Register 223 (DA0DT223) D-A0 Data Register 224 (DA0DT224) D-A0 Data Register 225 (DA0DT225) D-A0 Data Register 226 (DA0DT226) D-A0 Data Register 227 (DA0DT227) D-A0 Data Register 228 (DA0DT228) D-A0 Data Register 229 (DA0DT229) D-A0 Data Register 230 (DA0DT230) D-A0 Data Register 231 (DA0DT231) D-A0 Data Register 232 (DA0DT232) D-A0 Data Register 233 (DA0DT233) D-A0 Data Register 234 (DA0DT234) D-A0 Data Register 235 (DA0DT235) D-A0 Data Register 236 (DA0DT236) D-A0 Data Register 243 (DA0DT243)D-A0 Data Register 242 (DA0DT242) D-A0 Data Register 241 (DA0DT241)D-A0 Data Register 240 (DA0DT240) D-A0 Data Register 239 (DA0DT239)D-A0 Data Register 238 (DA0DT238) D-A0 Data Register 237 (DA0DT237) D-A0 Data Register 255 (DA0DT255)D-A0 Data Register 254 (DA0DT254) D-A0 Data Register 253 (DA0DT253)D-A0 Data Register 252 (DA0DT252) D-A0 Data Register 251 (DA0DT251)D-A0 Data Register 250 (DA0DT250) D-A0 Data Register 249 (DA0DT249)D-A0 Data Register 248 (DA0DT248) D-A0 Data Register 244 (DA0DT244) D-A0 Data Register 247 (DA0DT247) D-A0 Data Register 245 (DA0DT245) D-A0 Data Register 246 (DA0DT246) D-A0 Data Register 171 (DA0DT171) D-A0 Data Register 173 (DA0DT173) D-A0 Data Register 175 (DA0DT175) D-A0 Data Register 176 (DA0DT176) D-A0 Data Register 178 (DA0DT178) D-A0 Data Register 177 (DA0DT177) D-A0 Data Register 179 (DA0DT179) H'0080 1DBE +0 address +1 addressAddress Blank areas are reserved for future use. ADDRESS SPACE Figure 3.4.26 Register Mapping of the SFR Area (23)

3-35 Rev.1.0 The EIT vector entry is located at the beginning of the internal ROM/extended external areas. Instructions for branching to the start addresses of respective EIT event handlers are written here. Note that it is branch instructions and not the jump addresses that are written here. For details, refer to Chapter 4, "EIT." Figure 3.5.1 EIT Vector Entry ADDRESS SPACE H'0000 0040 TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 AE (Address Exception) EI (External Interrupt) (Note) H'0000 0044 H'0000 0048 H'0000 004C H'0000 0050 H'0000 0054 H'0000 0058 H'0000 005C H'0000 0060 H'0000 0064 H'0000 0068 H'0000 006C H'0000 0070 H'0000 0074 H'0000 0078 H'0000 007C H'0000 0080 RI (Reset Interrupt) SBI (System Break Interrupt) RIE (Reserved Instruction Exception) H'0000 0030 H'0000 0020 H'0000 0010 H'0000 0000 03 1 H'0000 0034 H'0000 0038 H'0000 003C H'0000 0024 H'0000 0028 H'0000 002C H'0000 0004 H'0000 0008 H'0000 000C H'0000 0014 H'0000 0018 H'0000 001C Note: When the flash entry bit = 1 (flash enable mode), the EI vector entry is located at H'0080 4000.

3-36 Rev.1.0 The ICU vector table is used by the internal Interrupt Controller. The start addresses of interrupt handlers for interrupt requests from internal peripheral I/Os are set at the corresponding addresses of this table, as shown below. For details, refer to Chapter 5, "Interrupt Controller." Figure 3.6.1 Configuration of the ICU Vector Table (1/2) ADDRESS SPACE H'0000 0094 Address D0 D7 +0 address +1 address D8 D15 H'0000 0096 PDC Input Interrupt Handler Start Address (A0-A15) PDC Input Interrupt Handler Start Address (A16-A31) H'0000 0098 H'0000 009A PWM Off Input Interrupt Handler Start Address (A0-A15) PWM Off Input Interrupt Handler Start Address (A16-A31) H'0000 009C H'0000 009E MJT Input Interrupt 5 Handler Start Address (A0-A15) MJT Input Interrupt 5 Handler Start Address (A16-A31) H'0000 00A0 H'0000 00A2 H'0000 00A4 H'0000 00A6 H'0000 00A8 H'0000 00AA H'0000 00AC H'0000 00AE H'0000 00B0 H'0000 00B2 H'0000 00B4 H'0000 00B6 H'0000 00B8 H'0000 00BA H'0000 00BC H'0000 00BE H'0000 00C0 H'0000 00C2 H'0000 00C4 H'0000 00C6 MJT Input Interrupt 4 Handler Start Address (A0-A15) MJT Input Interrupt 4 Handler Start Address (A16-A31) Blank areas are reserved for future use. MJT Input Interrupt 3 Handler Start Address (A0-A15) MJT Input Interrupt 3 Handler Start Address (A16-A31) MJT Input Interrupt 2 Handler Start Address (A0-A15) MJT Input Interrupt 2 Handler Start Address (A16-A31) MJT Input Interrupt 1 Handler Start Address (A0-A15) MJT Input Interrupt 1 Handler Start Address (A16-A31) MJT Input Interrupt 0 Handler Start Address (A0-A15) MJT Input Interrupt 0 Handler Start Address (A16-A31) TOM0 Output Interrupt Handler Start Address (A0-A15) TOM0 Output Interrupt Handler Start Address (A16-A31) TOM1 Output Interrupt Handler Start Address (A0-A15) TOM1 Output Interrupt Handler Start Address (A16-A31) TMS0 Output Interrupt Handler Start Address (A0-A15) TMS0 Output Interrupt Handler Start Address (A16-A31) TID0 Output Interrupt Handler Start Address (A0-A15) TID0 Output Interrupt Handler Start Address (A16-A31) TID1 Output Interrupt Handler Start Address (A0-A15) TID1 Output Interrupt Handler Start Address (A16-A31)

3-37 Rev.1.0 H'0000 00C8 D0 D7 D8 D15 H'0000 00CA DMA0-4 Interrupt Handler Start Address (A0-A15) DMA0-4 Interrupt Handler Start Address (A16-A31) H'0000 00CC H'0000 00CE H'0000 00D0 H'0000 00D2 H'0000 00D4 H'0000 00D6 H'0000 00D8 H'0000 00DA H'0000 00DC H'0000 00DE A-D0 Conversion Interrupt Handler Start Address (A0-A15) A-D0 Conversion Interrupt Handler Start Address (A16-A31) SIO0 Receive Interrupt Handler Start Address (A0-A15) SIO0 Receive Interrupt Handler Start Address (A16-A31) SIO0 Transmit Interrupt Handler Start Address (A0-A15) SIO0 Transmit Interrupt Handler Start Address (A16-A31) SIO1 Receive Interrupt Handler Start Address (A0-A15) SIO1 Receive Interrupt Handler Start Address (A16-A31) SIO1 Transmit Interrupt Handler Start Address (A0-A15) SIO1 Transmit Interrupt Handler Start Address (A16-A31) H'0000 00E0 H'0000 00E2 H'0000 00E4 H'0000 00E6 H'0000 00E8 H'0000 00EA H'0000 00EC H'0000 00EE DMA5-9 Interrupt Handler Start Address (A0-A15) DMA5-9 Interrupt Handler Start Address (A16-A31) SIO4 Transmit/Receive Interrupt Handler Start Address (A0-A15) SIO4 Transmit/Receive Interrupt Handler Start Address (A16-A31) H'0000 00F0 H'0000 00F2 H'0000 00F4 H'0000 00F6 H'0000 00F8 H'0000 00FA H'0000 00FC H'0000 00FE H'0000 0100 H'0000 0102 H'0000 0104 H'0000 0106 H'0000 0108 H'0000 010A H'0000 010C H'0000 010E CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A0-A15) CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A16-A31) A-D1 Conversion Interrupt Handler Start Address (A0-A15) A-D1 Conversion Interrupt Handler Start Address (A16-A31) SIO2,3 Transmit/Receive Interrupt Handler Start Address (A0-A15) SIO2,3 Transmit/Receive Interrupt Handler Start Address (A16-A31) SIO4 Transmit Interrupt Handler Start Address (A0-A15) SIO4 Transmit Interrupt Handler Start Address (A16-A31) SIO5 Receive Interrupt Handler Start Address (A0-A15) SIO5 Receive Interrupt Handler Start Address (A16-A31) SIO5 Transmit Interrupt Handler Start Address (A0-A15) SIO5 Transmit Interrupt Handler Start Address (A16-A31) SIO6,7 Transmit/Receive Interrupt Handler Start Address (A0-A15) SIO6,7 Transmit/Receive Interrupt Handler Start Address (A16-A31) RTD Interrupt Handler Start Address (A0-A15) RTD Interrupt Handler Start Address (A16-A31) PDC Compare Match & Error Interrupt Handler Start Address (A0-A15) PDC Compare Match & Error Interrupt Handler Start Address (A16-A31) CAN1 Transmit/Receive & Error Interrupt Handler Start Address (A0-A15) CAN1 Transmit/Receive & Error Interrupt Handler Start Address (A16-A31) Address +0 address +1 address Blank areas are reserved for future use. ADDRESS SPACE Figure 3.6.2 Configuration of the ICU Vector Table (2/2)

3-38 Rev.1.0

3.7 Precautions on Address Space

• Virtual-flash emulation function The 32172 has a function for mapping up to two 8-Kbyte blocks of the internal RAM beginning with the first address into the internal flash memory areas divided in units of 8 Kbytes (L banks). Similarly, the 32173 has a function for mapping up to three 8-Kbyte blocks of the internal RAM beginning with the first address into the internal flash memory areas divided in units of 8 Kbytes (L banks), as well as mapping up to two 4-Kbyte blocks of the internal RAM beginning with the H'0080 A000 area into the internal flash memory areas divided in units of 4 Kbytes (S banks) (the latter available for only the 32173). This is referred to as the virtual-flash emulation function. For details about this function, refer to Section 6.7, "Virtual-flash Emulation Function." ADDRESS SPACE

4.1 Outline of EIT

4.2 EIT Events

4.3 EIT Processing Procedure

4.4 EIT Processing Mechanism

4.5 Accepting EIT Events

4.6 Saving and Restoring PC

4.7 EIT Vector Entry

4.8 Exception Handling

4.9 Interrupt Handling

4.10 Trap Handling

4.11 EIT Priority

4.12 Example of EIT Processing

4.13 Precautions on EIT

4-2 Rev.1.0 EIT If an event occurs while the CPU is executing an ordinary program, the CPU may have to suspend execution of the program and execute another program. Such an event is referred to by the generic name "EIT (Exception, Interrupt, Trap)." (1) Exception This event relates to the context being executed, and is generated by an error or a violation of rules in instruction execution. In the M32R/E, Address Exception (AE) and Reserved Instruction Exception (RIE) fall under the category of this type of event. (2) Interrupt This event occurs independently of the context being executed. It is generated by a signal sent by means of hardware from the outside. In the M32R/E, External Interrupt (EI), System Break Interrupt (SBI), and Reset Interrupt (RI) fall under the category of this type of event. (3) Trap This refers to a software interrupt, which is issued by executing the TRAP instruction. As in the case of system calls of the OS, this type of event is generated intentionally in a program by the programmer. Figure 4.1.1 Classification of EIT EIT Exception Reserved Instruction Exception (RIE) Address Exception (AE) Interrupt Reset Interrupt (RI) System Break Interrupt (SBI) External Interrupt (EI) Trap TRAP

4-3 Rev.1.0 EIT

4.2.1 Exceptions

(1) Reserved Instruction Exception (RIE) A Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (an unimplemented instruction) is detected. (2) Address Exception (AE) An Address Exception (AE) occurs when access to an unaligned address is attempted in a Load or Store instruction.

4.2.2 Interrupts

(1) Reset Interrupt (RI) A Reset Interrupt (RI) is accepted by asserting a RESET signal to the CPU. The Reset Interrupt has the highest priority. (2) System Break Interrupt (SBI) The System Break Interrupt (SBI) is an emergency interrupt which is issued when power outage is detected or a fault condition is notified from an external watchdog timer. This interrupt can be used only when after interrupt processing, the CPU does not as a rule return to the program it was executing when the interrupt occurred. (3) External Interrupt (EI) The External Interrupt (EI) is an interrupt request from one of the internal peripheral I/Os managed by the Interrupt Controller. The M32R's internal Interrupt Controller controls these interrupts by means of eight interrupt priority levels (including an interrupt-disabled state).

4.2.3 Trap

The Trap (TRAP) is a software interrupt, which is generated by executing the TRAP instruction. Sixteen vector addresses are provided, corresponding to operands 0-15 of the TRAP instruction.

4-4 Rev.1.0 EIT Figure 4.3.1 Outline of EIT Processing Procedure Instruction A Instruction B Instruction C PC BPC PSW (B)PSW EIT vector entry EIT handlers except for SBI RTE instruction Instruction C Instruction D • • • • Suspend program execution Accept EIT request Instruction processing cancel type (RIE, AE) Instruction processing complete type (EI, TRAP) Program execution restarts EIT request generated Hardware preprocessing Save BPC, (B)PSW, and general-purpose registers to the stack Branch instruction Restore general- purpose registers (B)PSW, and BPC from the stack SBI (System Break Interrupt) processing Hardware postprocessing(SBI) Terminate the program or reset the system User-created processing program (B)PSW PSW BPC PC Processing by handler Note: (B)PSW denotes the PSW Register’s BPSW field. EIT processing consists of two parts, one automatically processed by hardware, and one processed by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except for a rest interrupt, is shown below.

4-5 Rev.1.0 EIT When an EIT is accepted, the M32R/E saves the PC and PSW to the stack (described later) and branches to the EIT vector. The EIT vector has entry addresses assigned for each EIT. This is where the BRA (branch) instruction (note that these are not branch addresses) for the EIT handler is written. In hardware preprocessing by the M32R/E, the contents of the PC and PSW Register are transferred to the backup registers (BPC Register and the PSW Register BPSW field). This is the only operation performed here. Therefore, it is necessary to save to the stack in a user-created EIT handler the BPC Register, the PSW Register (including the BPSW field), and the general-purpose registers to be used in the EIT handler. (Remember that these registers must be saved to the stack in a program by the user.) When processing by the EIT handler is completed, restore the registers from the stack to which they have been saved and then execute the RTE instruction to return from EIT processing to the original program (except for System Break Interrupt). In hardware postprocessing by the M32R/E, the contents of the backup registers (BPC Register and the PSW Register BPSW field) are restored into the PC and PSW Registers.

4-6 Rev.1.0 EIT The EIT processing mechanism of the M32R/E consists of the M32R CPU Core unit and the internal peripheral I/O Interrupt Controller. It also has backup registers for the PC and PSW (BPC Register and the BPSW fild of the PSW register). The M32R/E's internal EIT processing mechanism is shown below. Figure 4.4.1 EIT Processing Mechanism of the M32R/E Interrupt Controller (ICU) SBI EI Internal Peripheral I/O RESET RI AE, RIE, TRAP IE Flag (PSW) M32R CPU Core SBI Low High Priority SBI EI RI M32R/E PSW Register PSWBPSW BPC Register PC Register

4-7 Rev.1.0 EIT When an EIT event occurs, the M32R/E suspends execution of the program being executed and branches to EIT handler processing. The table below shows occurrence conditions of each EIT event and the timing at which they are accepted. Table 4.5.1 Accepting EIT Events EIT Event Processing Type Acceptance Timing Values Set in BPC Register Reserved Instruction Instruction processing During instruction PC value of the instruction that Exception (RIE) cancel type execution generated RIE Address Exception Instruction processing During instruction PC value of the instruction that (AE) cancel type execution generated AE Reset Interrupt (RI) Instruction processing Each machine cycle Indeterminate value abandon type System Break Instruction processing Break in instructions PC value of the next instruction Interrupt (SBI) complete type (Word boundary only) External Interrupt (EI) Instruction processing Break in instructions PC value of the next instruction complete type (Word boundary only) Trap (TRAP) Instruction processing Break in instructions PC value of TRAP instruction + 4 complete type

4-8 Rev.1.0 EIT

4.6 Saving and Restoring PC and PSW

The following describes the operations performed by the M32R when accepting an EIT and when executing the RTE instruction. (1) Hardware preprocessing when accepting an EIT (a) Save the PSW Register SM, IE, and C bits BSM ← SM BIE ← IE BC ← C (b) Update the PSW Register SM, IE, and C bits SM ← Unchanged (RIE, AE, TRAP) or set to 0 (SBI, EI, RI) IE ← Set to 0 C ← Set to 0 (c) Save the PC Register BPC ← PC (d) Set the vector address in the PC Register Branches to the EIT vector and executes the branch instruction (BRA instruction) written in it, thereby transferring control to EIT handler processing written by the user. (2) Hardware postprocessing when executing the RTE instruction (e) Restore the PSW Register BSM, BIE, and BC bits SM ← BSM IE ← BIE C ← BC (f) Restore the BPC Register value to the PC Register PC ← BPC Note: After executing the RTE instruction, the values of the BPC Register and the PSW Register BSM, BIE, and BC bits are indeterminate.

4-9 Rev.1.0 EIT (b) (d) (a) Save the SM, IE, and C bits (b) Update the SM, IE, and C bits SM Unchanged/0 (c) Save the PC (d) Set the vector address in the PC PC Vector address (f) Restore the BPC value into the PC After executing the RTE instruction, the value of the BPC is indeterminate. (e) Restore the BSM, BIE, and BC bits After executing the RTE instruction, the values of the BSM, BIE, and BC bits are indeterminate. BSM BIE BC SM IE C IE C BPC PC SM IE C BSM BIE BC (C)(a) (f)(e) 16 17 23 24 25 31(LSB)15870(MSB) SM IE CBCBSM BIE 00000000000000000000000000PSW BPSW field PSW field Figure 4.6.1 Saving and Restoring the PC and PSW

4-10 Rev.1.0 EIT The EIT vector entry is placed in the user space beginning with address H'0000 0000. The EIT vector entry is listed below. Table 4.7.1 EIT Vector Entry Name Abbreviation Vector Address SM IE BPC Reset Interrupt RI H'0000 0000 0 0 Indeterminate (Note 1) System Break SBI H'0000 0010 0 0 PC of the next instruction Interrupt Reserved Instruction RIE H'0000 0020 Unchanged 0 PC of the instruction that generated EIT Exception Address Exception AE H'0000 0030 Unchanged 0 PC of the instruction that generated EIT Trap TRAP0 H'0000 0040 Unchanged 0 PC of the TRAP instruction + 4 TRAP1 H'0000 0044 Unchanged 0 PC of the TRAP instruction + 4 TRAP2 H'0000 0048 Unchanged 0 PC of the TRAP instruction + 4 TRAP3 H'0000 004C Unchanged 0 PC of the TRAP instruction + 4 TRAP4 H'0000 0050 Unchanged 0 PC of the TRAP instruction + 4 TRAP5 H'0000 0054 Unchanged 0 PC of the TRAP instruction + 4 TRAP6 H'0000 0058 Unchanged 0 PC of the TRAP instruction + 4 TRAP7 H'0000 005C Unchanged 0 PC of the TRAP instruction + 4 TRAP8 H'0000 0060 Unchanged 0 PC of the TRAP instruction + 4 TRAP9 H'0000 0064 Unchanged 0 PC of the TRAP instruction + 4 TRAP10 H'0000 0068 Unchanged 0 PC of the TRAP instruction + 4 TRAP11 H'0000 006C Unchanged 0 PC of the TRAP instruction + 4 TRAP12 H'0000 0070 Unchanged 0 PC of the TRAP instruction + 4 TRAP13 H'0000 0074 Unchanged 0 PC of the TRAP instruction + 4 TRAP14 H'0000 0078 Unchanged 0 PC of the TRAP instruction + 4 TRAP15 H'0000 007C Unchanged 0 PC of the TRAP instruction + 4 External Interrupt EI H'0000 0080 0 0 PC of the next instruction (Note 2) Note 1: During boot mode, control jumps to the beginning of the boot ROM (address H'8000 0000). For details, refer to Section 6.5 "Programming the Internal Flash Memory." Note 2: During flash E/W enable mode, control jumps to the beginning of the internal RAM (address H'0080 4000). For details, refer to Section 6.5, "Programming the Internal Flash Memory."

4-11 Rev.1.0 EIT

4.8.1 Reserved Instruction Exception (RIE)

[Occurrence condition] A Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (an unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a Reserved Instruction Exception occurs, the instruction that caused the exception is not executed. Even if an external interrupt is requested when a Reserved Instruction Exception is detected, the Reserved Instruction Exception is accepted. [EIT processing] (1) Saving the SM, IE, and C bits The PSW Register SM, IE, and C bits are saved to the backup bits-BSM, BIE, and BC. BSM ← SM BIE ← IE BC ← C (2) Updating the SM, IE, and C bits The PSW Registmer SM, IE, and C bits are updated in the manner shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC The PC value of the instruction that caused the Reserved Instruction Exception is set in the BPC Register. For example, if the instruction that caused the Reserved Instruction Exception is at address 4, then the value 4 is set in the BPC Register; if at address 6, then the value 6 is set in the BPC Register. In this case, the value of the BPC Register bit 30 indicates whether the instruction that caused the Reserved Instruction Exception exists on the word boundary (BPC[30] = 0), or not (BPC[30] = 1). However, in either case of the above, the location to which the RTE instruction returns after the end of the EIT handler is always address 4. (This is because the two low-order bits are cleared to '00' when returning to the PC.)

4-12 Rev.1.0 EIT H'00 Address RIE occurredH'04 H'08 H'0C +0 +1 +2 +3 H'00 Address RIE occurredH'04 H'08 H'0C +0 +1 +2 +3 Return address Return address BPC H'06BPC H'04 Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE) (4) Branching to the EIT vector entry Control branches to a user space address H'0000 0020. This is the last operation in hardware preprocessing performed by the M32R/E. (5) Branching from the EIT vector entry to the user-created handler The M32R/E executes the BRA instruction written at the EIT vector entry address H'0000 0020 by the user, thereby branching to the start address of the user-created handler. At the beginning of the user-created EIT handler, the BPC and PSW Registers and the necessary general-purpose registers must first be saved to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW Registers from the stack and execute the RTE instruction. Then hardware postprocessing will be performed automatically. In this case, operation restarts from a word-boundary instruction including one that caused the RIE exception (see Figure 4.8.1).

4-13 Rev.1.0 EIT

4.8.2 Address Exception (AE)

[Occurrence condition] An Address Exception (AE) occurs when access to an unaligned address is attempted in a Load or Store instruction. The following shows combinatorial instruction and address conditions under which an Address Exception is invoked.

• LDH, LDUH, or STH instruction and the two low-order address bits are '01' or '11'
• LD, ST, LOCK, or UNLOCK instruction and the two low-order address bits are '01,' '10,' or '11' When an Address Exception occurs, memory access by the instruction that caused the exception is not performed. Even if an external interrupt is requested when an Address Exception is detected, the Address Exception is accepted. [EIT processing] (1) Saving the SM, IE, and C bits The PSW Register SM, IE, and C bits are saved to the backup bits-BSM, BIE, and BC. BSM ← SM BIE ← IE BC ← C (2) Updating the SM, IE, and C bits The PSW Register SM, IE, and C bits are updated in the manner shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC The PC value of the instruction that caused the Address Exception is set in the BPC Register. For example, if the instruction that caused the Address Exception is at address 4, then the value 4 is set in the BPC Register; if at address 6, then the value 6 is set in the BPC Register. In this case, the value of the BPC Register bit 30 indicates whether the instruction that caused the Address Exception exists on the word boundary (BPC[30] = 0), or not (BPC[30] = 1). However, in either case of the above, the location to which the RTE instruction returns after the end of the EIT handler is always address 4. (This is because the two low-order bits are cleared to '00' when returning to the PC.)

4-14 Rev.1.0 EIT H'00 Address AE occurredH'04 H'08 H'0C +0 +1 +2 +3 H'00 Address AE occurredH'04 H'08 H'0C +0 +1 +2 +3 Return address Return address BPC H'06BPC H'04 Figure 4.8.2 Example of a Return Address for Address Exception (AE) (4) Branching to the EIT vector entry Control branches to a user space address H'0000 0030. This is the last operation in hardware preprocessing performed by the M32R/E. (5) Branching from the EIT vector entry to the user-created handler The M32R/E executes the BRA instruction written at the EIT vector entry address H'0000 0030 by the user, thereby branching to the start address of the user-created handler. At the beginning of the user-created EIT handler, the BPC and PSW Registers and the necessary general-purpose registers must first be saved to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW Registers from the stack and execute the RTE instruction. Then hardware postprocessing will be performed automatically. In this case, operation restarts from a word-boundary instruction including one that caused the AE exception (see Figure 4.8.2).

4-15 Rev.1.0 EIT

4.9.1 Reset Interrupt (RI)

[Occurrence condition] When input on RESET pin is pulled low, a Reset Interrupt (RI) is accepted unconditionally in each machine cycle. The Reset Interrupt has the highest priority of all EIT. [EIT processing] (1) Initializing the SM, IE, and C bits The PSW Register SM, IE, and C bits are initialized in the manner shown below. SM ← 0 IE ← 0 C ← 0 For Reset Interrupt, the values of the BSM, BIE, and BC bits become indeterminate. (2) Branching to the EIT vector entry Control branches to a user space address H'0000 0000. During boot mode, however, control goes to the beginning of the boot ROM (address H'8000 0000). (For details, refer to Section 6.5, "Programming the Internal Flash Memory.") (3) Branching from the EIT vector entry to the user program The M32R/E executes the instruction written at the EIT vector entry address H'0000 0000 by the user. In the reset vector entry, initialize the PSW and SPI Registers and then branch to the start address of the user program.

4-16 Rev.1.0 EIT Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted 16-bit instruction Order in which instructions are executed 32-bit instruction Address 1000 Address 1002 Address 1004 Address 1008 Interrupt can be accepted Interrupt cannot be accepted Interrupt can be accepted Interrupt can be accepted 16-bit instruction

4.9.2 System Break Interrupt (SBI)

The System Break Interrupt (SBI) is an emergency interrupt which is issued when power outage is detected or a fault condition is notified from an external watchdog timer. The System Break Interrupt cannot be masked with the PSW Register IE bit. Therefore, the System Break Interrupt can only be used when some fatal event has already occurred in the system when the interrupt is detected. Also, this interrupt must be used on condition that after processing with the SBI handler, the control will not return to the program it was executing when the system break interrupt occurred. [Occurrence condition] ___ A System Break Interrupt is accepted by a falling edge at the input of the SBI pin. (The System Break Interrupt cannot be masked with the PSW Register IE bit.) In no case will a System Break Interrupt be activated immediately after executing any 16-bit instruction that begins from the word boundary. (However, this does not apply to 16-bit branch instructions, in which case the interrupt is accepted immediately after branching.)

4-17 Rev.1.0 EIT [EIT processing] (1) Saving the SM, IE, and C bits The PSW Register SM, IE, and C bits are saved to the backup bits-BSM, BIE, and BC. BSM ← SM BIE ← IE BC ← C (2) Updating the SM, IE, and C bits The PSW Register SM, IE, and C bits are updated in the manner shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving the PC The contents of the PC Register (always on word boundary) are saved to the BPC Register. (4) Branching to the EIT vector entry Control branches to a user space address H'0000 0010. This is the last operation in hardware preprocessing performed by the M32R/E. (5) Branching from the EIT vector entry to the user-created handler The M32R/E executes the BRA instruction written at the EIT vector entry address H'0000 0010 by the user, thereby branching to the start address of the user-created handler. The System Break Interrupt can only be used when some fatal event has already occurred in the system when the interrupt is detected. Also, this interrupt must be used on condition that after processing with the SBI handler, the control will not return to the program it was executing when the system break interrupt occurred.

4-18 Rev.1.0 EIT Figure 4.9.2 Timing at Which External Interrupt (EI) is Accepted 16-bit instruction Order in which instructions are executed 32-bit instruction Address 1000 Address 1002 Address 1004 Address 1008 Interrupt can be accepted Interrupt cannot be accepted Interrupt can be accepted Interrupt can be accepted 16-bit instruction

4.9.3 External Interrupt (EI)

An External Interrupt (EI) is generated based on interrupt requests output by the internal Interrupt Controller. The Interrupt Controller manages interrupt requests by means of 7-level interrupt priority. For details about the Interrupt Controller, refer to Chapter 5, "Interrupt Controller." For details about the causes of interrupts, refer to each relevant chapter where the internal peripheral I/ O in interest is described. [Occurrence condition] External Interrupts are managed by the Interrupt Controller based on interrupt requests from each internal peripheral I/O, and are notified to the M32R CPU by the Interrupt Controller. The M32R/E checks for this request at instruction breaks on word boundaries. When an interrupt request from the Interrupt Controller is detected and the PSW Register IE flag = 1, an External Interrupt is accepted. In no case will an External Interrupt be activated immediately after executing any 16-bit instruction that begins from the word boundary. (However, this does not apply to 16-bit branch instructions, in which case the interrupt is accepted immediately after branching.)

4-19 Rev.1.0 EIT [EIT Processing] (1) Saving the SM, IE, and C bits The PSW Register SM, IE, and C bits are saved to the backup bits-BSM, BIE, and BC. BSM ← SM BIE ← IE BC ← C (2) Updating the SM, IE, and C bits The PSW Register SM, IE, and C bits are updated in the manner shown below. SM ← 0 IE ← 0 C ← 0 (3) Saving the PC The contents of the PC Register (always on word boundary) are saved to the BPC Register. (4) Branching to the EIT vector entry Control branches to a user space address H'0000 0080. However, when in flash E/W enable mode, control jumps to the beginning of the internal RAM (address H'0080 4000). (For details, refer to Section 6.5, "Programming the Internal Flash Memory.") This is the last operation in hardware preprocessing performed by the M32R/E. (5) Branching from the EIT vector entry to the user-created handler The M32R/E executes the BRA instruction written at the EIT vector entry address H'0000 0080 by the user, thereby branching to the start address of the user-created handler. At the beginning of the user-created EIT handler, the BPC and PSW Registers and the necessary general-purpose registers must first be saved to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW Registers from the stack and execute the RTE instruction. Then hardware postprocessing will be performed automatically.

4-20 Rev.1.0 EIT

4.10.1 Trap (TRAP)

[Occurrence condition] The Trap (TRAP) is a software interrupt, which is generated by executing the TRAP instruction. Sixteen types of Traps are generated corresponding to operands 0-15 of the TRAP instruction. Accordingly, there are sixteen vector entry addresses, one for each type of Trap. [EIT processing] (1) Saving the SM, IE, and C bits The PSW Register SM, IE, and C bits are saved to the backup bits-BSM, BIE, and BC. BSM ← SM BIE ← IE BC ← C (2) Updating the SM, IE, and C bits The PSW Register SM, IE, and C bits are updated in the manner shown below. SM ← Unchanged IE ← 0 C ← 0 (3) Saving the PC When the TRAP instruction is executed, the "PC value of TRAP instruction + 4" is set in the BPC Register. For example, if the TRAP instruction is located at address 4, then the value H'08 is set in the BPC Register; if located at address 6, the value H'0A is set in the BPC Register. The value of the BPC Register bit 30 indicates whether the TRAP instruction exists on the word boundary (BPC[30] = 0), or not (BPC[30] = 1). However, in either case of the above, the location to which the RTE instruction returns after the end of the EIT handler is always address 8. (This is because the two low-order bits are cleared to '00' when returning to the PC.)

4-21 Rev.1.0 EIT H'00 Address H'04 H'08 H'0C +0 +1 +2 +3 H'00 Address H'04 H'08 H'0C +0 +1 +2 +3 Return address Return address BPC H'0ABPC H'08 TRAP instructionTRAP instruction Figure 4.10.1 Example of a Return Address for Trap (TRAP) (4) Branching to the EIT vector entry Control branches to user space addresses H'0000 0040 through H'0000 007C. This is the last operation in hardware preprocessing performed by the M32R/E. (5) Branching from the EIT vector entry to the user-created handler The M32R/E executes the BRA instruction written at the EIT vector entry addresses H'0000 0040 through H'0000 007C by the user, thereby branching to the start address of the user-created handler. At the beginning of the user-created EIT handler, the BPC and PSW Registers and the necessary general-purpose registers must first be saved to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW Registers from the stack and execute the RTE instruction. After execution of the RTE instruction, hardware postprocessing is performed automatically.

4-22 Rev.1.0 EIT The priority of EIT events is shown below. If two or more EIT events occur at the same time, the EIT with the highest priority of all is accepted first. Table 4.11.1 Priority of EIT Events and Manner of Return Priority EIT Event Processing Type Values Set in BPC Register 1 (highest priority)Reset Interrupt (RI) Instruction processing Indeterminate abandon type Address Exception (AE)Instruction processing PC of the instruction that generated EIT cancel type

2 Reserved Instruction Instruction processing PC of the instruction that generated EIT

Exception (RIE) cancel type Trap (TRAP) Instruction processing TRAP instruction + 4 complete type

3 System Break Instruction processing PC of the next instruction

Interrupt (SBI) complete type

4 External Interrupt (EI) Instruction processing PC of the next instruction

For External Interrupt (EI), the priority of each interrupt request from peripheral I/O is set by the M32R's internal Interrupt Controller. For details, refer to Chapter 5, "Interrupt Controller."

4-23 Rev.1.0 EIT (1) When an RIE, AE, SBI, EI, or TRAP occurs singly Figure 4.12.1 Processing of a Single Event of RIE, AE, SBI, EI, or TRAP (2) When an RIE, AE, or TRAP occurs simultaneously with EI Figure 4.12.2 Processing of RIE, AE, or TRAP and EI when They Occurred Simultaneously RTE instruction IE=0 IE=1 BPC Register = return address A IE=1 Occurrence of a single RIE, AE, SBI, EI, or TRAP event Return address A: If IE = 0 (remains unchanged), nothing but reset and SBI are accepted : EIT handler RTE instruction IE=0 RIE, AE, or TRAP is accepted first BPC Register = return address A IE=1 Occurrence of an RIE, AE, or TRAP simultaneously with EI Return address A: IE=1 IE=0 IE=1 RTE instruction EI is accepted next BPC Register = return address A : EIT handler

4-24 Rev.1.0 EIT (SBI) Processing of System Break Interrupt Terminate the program or reset the system (Other than SBI) PC BPC PSW (B)PSW Hardware preprocessing Hardware postprocessing (B)PSW PSW BPC PC Figure 4.12.3 Example of EIT Processing

4-25 Rev.1.0 The Address Exception (AE) requires caution because when an Address Exception occurs pursuant to execution of an instruction (one of the following three) that uses the "register indirect + register update" addressing mode, the value of the automatically updated register (Rsrc or Rsrc2) becomes indeterminate. Except that the values of Rsrc and Rsrc2 are indeterminate, the behavior is the same as when using other addressing modes.

• Applicable instructions LD Rdest, @Rsrc+ ST Rsrc1, @-Rsrc2 ST Rsrc1, @+Rsrc2 If the above applies, take into account the fact that the register value becomes indeterminate when programming the system processing to be performed after occurrence of the exception. (If an Address Exception occurs, it means that some fatal fault already occurred in the system at that point in time. Therefore, use the Address Exception on condition that after processing by the Address Exception handler, the CPU will not return to the program it was executing when the exception occurred.) EIT

4-26 Rev.1.0 EIT

5.1 Outline of the Interrupt

Controller (ICU)

5.2 Interrupt Sources of Internal

5.3 ICU Related Registers

5.4 ICU Vector Table

5.5 Description of Interrupt

5.6 Description of System Break

Interrupt (SBI) Operation CHAPTER 5CHAPTER 5 INTERRUPT CONTROLLER (ICU)

5-2 Rev.1.0 INTERRUPT CONTROLLER (ICU)

5.1 Outline of the Interrupt Controller (ICU)

The Interrupt Controller (ICU) controls maskable interrupts from internal peripheral I/Os and System Break Interrupt (SBI). The maskable interrupts from internal peripheral I/Os are notified to the M32R CPU as External Interrupts (EI). There is a total of 31 sources for the maskable interrupts from internal peripheral I/Os, which are controlled by assigning them one of eight priority levels including an interrupt-disabled state. If multiple interrupt requests with the same priority level occur simultaneously, they are prioritized according to the fixed hardware priority. Which sources of internal peripheral I/Os generated the interrupt requests are identified by reading the Interrupt Status Register of the internal peripheral I/O. On the other hand, the System Break Interrupt (SBI) is an interrupt generated by a falling edge of___ the SBI input signal. This interrupt is always accepted regardless of the status of the PSW Register IE bit, and is used as an emergency interrupt which is issued when power failure is detected or a fault condition is notified from an external watchdog timer. After processing for the SBI is finished, terminate or reset the system without returning to the program that was executing when the interrupt occurred. The Interrupt Controller is outlined below. Table 5.1.1 Outline of the Interrupt Controller (ICU) Item Specification Interrupt source Maskable interrupts from internal peripheral I/Os : 31 sources System Break Interrupt ___ : 1 source (entered from the SBI pin) Priority level 8 levels including interrupt-disabled state (However, interrupts with the same priority level are prioritized by the fixed hardware priority.)

5-3 Rev.1.0 INTERRUPT CONTROLLER (ICU) Figure 5.1.1 Block Diagram of the Interrupt Controller Interrupt Vector Register (IVECT) Interrupt Vector Register (IMASK) NEW_IMASK Maskable interrupt requests generated Resolved by fixed hardware priority IMASK compared ILEV EL Resolved according to interrupt priority level System Break Interrupt request generated SBI EI SBI Interrupt Controller Interrupt Control Register SBI Control Register (SBICR) SBIREQ IREQ IREQ IREQ IREQ IREQ IREQ Peripheral circuit Edge Interrupt control circuit Interrupt control circuit Interrupt control circuit Edge Edge Level Interrupt request Interrupt request Interrupt request Level Level To the CPU core To the CPU core

5-4 Rev.1.0 INTERRUPT CONTROLLER (ICU)

5.2 Interrupt Sources of Internal Peripheral I/Os

The Interrupt Controller accepts as its input the interrupt requests from the timers, DMA, serial I/O, A-D converter, RTD, CAN, and PD controller. For details about these interrupts, refer to each relevant chapter where the internal peripheral I/O in interest is described. Table 5.2.1 Interrupt Sources of Internal Peripheral I/Os (1/2) Interrupt Source Content No. of Type of Input Sources Input Source (Note) PDC input & error PDC input 0-3 (TINA0, TINA1, TINB0, or TINB1) detected, 8Level detection interrupt PDC input 0-3 error detected PWM-off input interruptPWM off input 0,1 interrupt 2 Level A-D0 converter interruptA-D0 converter scan mode single shot, single mode, 1 Edge or comparator mode finished A-D1 converter interruptA-D1 converter scan mode single shot, single mode, 1 Edge or comparator mode finished SIO0 transmit interruptSIO0 transmit buffer empty interrupt 1 Edge SIO0 receive interruptSIO0 reception finished or receive error interrupt 1 Edge SIO1 transmit interruptSIO1 transmit buffer empty interrupt 1 Edge SIO1 receive interrupt SIO1 reception finished or receive error interrupt 1 Edge SIO2,3 transmit/receiveSIO2,3 reception finished or receive error interrupt, 2 Level interrupt transmit buffer empty interrupt SIO4 transmit interrupt SIO4 transmit buffer empty interrupt 1 Edge SIO4 receive interrupt SIO4 reception finished or receive error interrupt 1 Edge SIO5 transmit interrupt SIO5 transmit buffer empty interrupt 1 Edge SIO5 receive interrupt SIO5 reception finished or receive error interrupt 1 Edge SIO6,7 transmit/receiveSIO6,7 reception finished or receive error interrupt, 2 Level interrupt transmit buffer empty interrupt RTD interrupt RTD interrupt generating command 1 Edge DMA transfer interrupt 0DMA0-4 transfer finished 5 Level DMA transfer interrupt 1DMA5-9 transfer finished 5 Level PDC compare match & PDC compare match, S error interrupt 8 Level error interrupt CAN0 transmit/receive &CAN0 transmission finished, CAN0 reception finished, 19 Level error interrupt CAN0 error passive, CAN0 error bus off, CAN0 bus error CAN1 transmit/receive &CAN1 transmission finished, CAN1 reception finished, 19 Level error interrupt CAN1 error passive, CAN1 error bus off, CAN1 bus error Note: Type of input source

• Edge: An interrupt request is generated by a falling edge on the interrupt signal fed into the ICU.
• Level: An interrupt request is generated while the interrupt signal fed into the ICU is held low. Level- type interrupt requests cannot be set or cleared by writing to the ICU's Interrupt Control Register IRQ bit in software.

5-5 Rev.1.0 INTERRUPT CONTROLLER (ICU) Table 5.2.2 Interrupt Sources of Internal Peripheral I/Os (2/2) Interrupt Source Content No. of Type of Input Sources Input Source (Note) TOM0 output interrupt TOM0_0 to TOM0_7 output 8 Level TOM1 output interrupt TOM1_0 to TOM1_7 output 8 Level TMS0 output interrupt TMS0 output 1 Edge TID0 output interrupt TID0 output 1 Edge TID1 output interrupt TID1 output 1 Edge Timer input interrupt 5 Timer input interrupt group 5 (TIN8, TIN9 input) 2 Level Timer input interrupt 4 Timer input interrupt group 4 (TIN10, TIN11 input) 2 Level Timer input interrupt 3 Timer input interrupt group 3 (TIN20, TIN21 input) 3 Level Timer input interrupt 2 Timer input interrupt group 2 (TIN22, TIN23 input) 3 Level Timer input interrupt 1 Timer input interrupt group 1 (TIN16, TIN17 input) 3 Level Timer input interrupt 0 Timer input interrupt group 0 (TIN18, TIN19 input) 3 Level Note: Type of input source

• Edge: An interrupt request is generated by a falling edge on the interrupt signal fed into the ICU.
• Level: An interrupt request is generated while the interrupt signal fed into the ICU is held low. Level-type interrupt requests cannot be set or cleared by writing to the ICU's Interrupt Control Register IRQ bit in software.

5-6 Rev.1.0 INTERRUPT CONTROLLER (ICU) A register map associated with the Interrupt Controller (ICU) is shown below. H'0080 0000 Address D0 D7 +0 address +1 address D8 D15 H'0080 0004 H'0080 0006 H'0080 0066 H'0080 0068 Interrupt Mask Register (IMASK) SBI Control Register (SBICR) H'0080 006A H'0080 006C H'0080 006E H'0080 0070 H'0080 0072 H'0080 0074 H'0080 0076 H'0080 0078 H'0080 0002 H'0080 007A H'0080 007C H'0080 007E A-D1 Conversion Interrupt Control Register (IAD1CCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) SIO1 Receive Interrupt Control Register (ISIO1RXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) SIO0 Transmit Interrupt Control Register (ISIO0TXCR) DMA0-4 Interrupt Control Register (IDMA04CR) TID1 Output Interrupt Control Register (ITID1CR) Timer Input Interrupt Control Register 1 (IMJTICR1) Timer Input Interrupt Control Register 0 (IMJTICR0) Timer Input Interrupt Control Register 2 (IMJTICR2) Timer Input Interrupt Control Register 4 (IMJTICR4) Timer Input Interrupt Control Register 5 (IMJTICR5) PWM Off Input Interrupt Control Register (IPWMOFFCR) PDC Input & Error Detection Interrupt Control Register (IPDCCR) SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) DMA5-9 Interrupt Control Register (IDMA59CR) Interrupt Vector Register (IVECT) H'0080 0060 CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR) H'0080 0062 H'0080 0064 Blank areas are reserved for future use. CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) RTD Interrupt Control Register (IRTDCR) PDC Compare Match & Error Interrupt Control Register (IPDCOPCR) SIO6,7 Transmit/Receive Interrupt Control Register (ISIO67CR) SIO5 Transmit Interrupt Control Register (ISIO5TXCR) SIO5 Receive Interrupt Control Register (ISIO5RXCR) SIO4 Transmit Interrupt Control Register (ISIO4TXCR) SIO4 Receive Interrupt Control Register (ISIO4RXCR) A-D0 Conversion Interrupt Control Register (IAD0CCR) TID0 Output Interrupt Control Register (ITID0CR) TMS0 Output Interrupt Control Register (ITMS0CR) TOM1 Output Interrupt Control Register (ITOM1CR) TOM0 Output Interrupt Control Register (ITOM0CR) Timer Input Interrupt Control Register 3 (IMJTICR3) Figure 5.3.1 Interrupt Controller (ICU) Related Register Map

5-7 Rev.1.0 INTERRUPT CONTROLLER (ICU) <When reset: Indeterminate> D Bit Name Function R W 0-15 IVECT (ICU vector When an interrupt is accepted, – table address, this register stores the 16 low-order 16 low-order bits) bits of ICU vector table address for the accepted interrupt source. Note: This register must always be accessed in halfwords. The Interrupt Vector Register (IVECT) is a register which when an interrupt is accepted, stores the 16 low-order bits of ICU vector table address for the accepted interrupt source. The ICU vector table (addresses H'0000 0094 to H'0000 010F) contains the start address of the interrupt handler for each internal peripheral I/O which have been set in advance. When an interrupt is accepted, the 16 low-order bits of ICU vector table address for the accepted interrupt source are set in the IVECT Register. The EIT handler reads the content of the IVECT Register using the LDH instruction to get the ICU vector table address needed. When the IVECT Register is read out, operations (1) through (4) below are automatically performed in hardware. (1) Set the accepted new IMASK value (NEW_IMASK) in the IMASK Register (2) Clear the accepted interrupt request (not cleared for level interrupt sources) (3) Interrupt request (EI) to the CPU core is cleared. (4) Activate the ICU's internal sequencer to start internal processing (interrupt priority resolution)

5.3.1 Interrupt Vector Register

I Interrupt Vector Register (IVECT) <Address: H'0080 0000> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 IVECT CAUTION Do not read the Interrupt Vector Register (IVECT) in other than the EIT handler (unless the PSW Register IE bit is disabled). In the EIT handler, be sure to read the Interrupt Mask Register (IMASK) before reading the IVECT Register.

5-8 Rev.1.0 INTERRUPT CONTROLLER (ICU)

5.3.2 Interrupt Mask Register

I Interrupt Mask Register (IMASK) <Address: H'0080 0004> <When reset: H'07> D Bit Name Function R W 0-4 No functions assigned 0 – 5-7 IMASK (interrupt mask) 000: Disables maskable interrupt 001: Enables level 0 interrupt to be accepted 010: Enables level 0-1 interrupts to be accepted 011: Enables level 0-2 interrupts to be accepted 100: Enables level 0-3 interrupts to be accepted 101: Enables level 0-4 interrupts to be accepted 110: Enables level 0-5 interrupts to be accepted 111: Enables level 0-6 interrupts to be accepted The Interrupt Mask Register (IMASK) is used to set an interrupt mask to be compared with the priority level that has been set for each interrupt source (i.e., the Interrupt Control Register ILEVEL bit) to determine whether or not to accept the interrupt request. When the Interrupt Vector Register (IVECT) described above is read out, a new mask value (NEW_IMASK) is set in this IMASK Register. Upon writing to the IMASK Register, operations (1) to (2) below are automatically performed in hardware. (1) Negate the interrupt request (EI) sent to the CPU core (2) Activate the ICU's internal sequencer to start internal processing (interrupt priority resolution) D 0 123456 D 7 IMASK CAUTION Do not write to the Interrupt Mask Register (IMASK) in other than the EIT handler (unless the PSW Register IE bit is disabled).

5-9 Rev.1.0 INTERRUPT CONTROLLER (ICU)

5.3.3 SBI (System Break Interrupt) Control Register

I SBI (System Break Interrupt) Control Register (SBICR) <Address: H'0080 0006> <When reset: H'00> D Bit Name Function R W 0-6 No functions assigned 0 –

7 SBIREQ (SBI request) 0: SBI not requested

1: SBI requested W = : Writable for only clearing (see the explanation below) ___ The SBI (System Break Interrupt) is an interrupt generated by a falling edge of the SBI input signal. When an SBI interrupt occurs, the SBI Control Register SBIREQ (SBI request) bit is set to 1. The SBIREQ bit cannot be set in software. To clear the SBIREQ bit after being set, follow the procedure described below. (However, do not perform this clearing operation unless an SBI request has been generated.)

• Write a 1 and then a 0 to SBIREQ. D 0 123456 D 7 SBIREQ

5-10 Rev.1.0 INTERRUPT CONTROLLER (ICU)

5.3.4 Interrupt Control Registers

I CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR )<Address: H'0080 0060> I CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR )<Address: H'0080 0061> I PDC Compare Match & Error Interrupt Control Register (IPDCOPCR)<Address: H'0080 0062> I RTD Interrupt Control Register (IRTDCR) <Address: H'0080 0063> I SIO6,7 Transmit/Receive Interrupt Control Register (ISIO67CR) <Address: H'0080 0064> I SIO5 Transmit Interrupt Control Register (ISIO5TXCR) <Address: H'0080 0065> I SIO5 Receive Interrupt Control Register (ISIO5RXCR) <Address: H'0080 0066> I SIO4 Transmit/Receive Interrupt Control Register (ISIO4TXCR) <Address: H'0080 0067> I SIO4 Receive Interrupt Control Register (ISIO4RXCR) <Address: H'0080 0068> I SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) <Address: H'0080 0069> I DMA5-9 Interrupt Control Register (IDMA59CR) <Address: H'0080 006A> I A-D1 Conversion Interrupt Control Register (IAD1CCR) <Address: H'0080 006B> I SIO1 Transmit Interrupt Control Register (ISIO1TXCR) <Address: H'0080 006C> I SIO1 Receive Interrupt Control Register (ISIO1RXCR) <Address: H'0080 006D> I SIO0 Transmit Interrupt Control Register (ISIO0TXCR) <Address: H'0080 006E> I SIO0 Receive Interrupt Control Register (ISIO0RXCR) <Address: H'0080 006F> I A-D0 Conversion Interrupt Control Register (IAD0CCR) <Address: H'0080 0070> I DMA0-4 Interrupt Control Register (IDMA04CR) <Address: H'0080 0071> I TID1 Output Interrupt Control Register (ITID1CR) <Address: H'0080 0072> I TID0 Output Interrupt Control Register (ITID0CR) <Address: H'0080 0073> I TMS0 Output Interrupt Control Register (ITMS0CR) <Address: H'0080 0074> I TOM1 Output Interrupt Control Register (ITOM1CR) <Address: H'0080 0075> I TOM0 Output Interrupt Control Register (ITOM0CR) <Address: H'0080 0076> I Timer Input Interrupt Control Register 0 (IMJTICR0) <Address: H'0080 0077> I Timer Input Interrupt Control Register 1 (IMJTICR1) <Address: H'0080 0078> I Timer Input Interrupt Control Register 2 (IMJTICR2) <Address: H'0080 0079> I Timer Input Interrupt Control Register 3 (IMJTICR3) <Address: H'0080 007A> I Timer Input Interrupt Control Register 4 (IMJTICR4) <Address: H'0080 007B> I Timer Input Interrupt Control Register 5 (IMJTICR5) <Address: H'0080 007C> I PWM Off Input Interrupt Control Register (IPWMOFFCR) <Address: H'0080 007D> I PDC Input & Error Detection Interrupt Control Register 4 (IPDCCR)<Address: H'0080 007E>

5-11 Rev.1.0 INTERRUPT CONTROLLER (ICU) <When reset: H'07> D Bit Name Function R W 0-2 No functions assigned 0 – (8-10)

3 IREQ (interrupt request) 0 : Interrupt not requested

(11) 1 : Interrupt requested

4 No functions assigned 0 –

(12) 5-7 ILEVEL 000: Interrupt priority level 0 (13-15) (interrupt priority level) 001: Interrupt priority level 1 010: Interrupt priority level 2 011: Interrupt priority level 3 100: Interrupt priority level 4 101: Interrupt priority level 5 110: Interrupt priority level 6 111: Interrupt priority level 7(Interrupt-disabled state) W = : Can only be set/cleared when the "type of input source" is the edge type (and one input source). (1) IREQ (interrupt request) bit (D3 or D11) When an interrupt request from internal peripheral I/O occurs, the IREQ (interrupt request) bit is set to 1. This bit can be set and cleared in software for only the edge input type of interrupt sources (and cannot for the level type). The IREQ bit when set for an interrupt request generated by an edge input type of interrupt source is automatically cleared to 0 upon reading the Interrupt Vector Register (IVECT). (However, this bit is not automatically cleared for the level type of interrupt source.) If this bit is cleared in software at the same time it is set by an interrupt request generated, the former has priority (i.e., the bit is cleared). Also, if this bit is cleared by reading the IVECT Register at the same time it is set by an interrupt request generated, the former has priority (i.e., the bit is cleared). D 0 123456 D 7 (D8 9 10 11 12 13 14 D15) IREQ ILEVEL

5-12 Rev.1.0 INTERRUPT CONTROLLER (ICU) [0-7 levels] D3,11Data bus D5-7,13-15 3 F/F set set/clear IREQ Figure 5.3.2 Configuration of the Interrupt Control Register (Edge Type) Figure 5.3.3 Configuration of the Interrupt Control Register (Level Type) Interrupt priority resolving circuit Interrupt request from each peripheral equipment group Interrupt enabled D3,11 Data bus D5-7,13-15 RD IREQ Read-only circuit ILEVEL [0-7 levels] Group interrupt

5-13 Rev.1.0 INTERRUPT CONTROLLER (ICU) (2) ILEVEL (interrupt priority level) (D5-D7 or D13-D15) These bits set the priority level of an interrupt request from each internal peripheral I/O. Set the priority level to 7 to disable the interrupt from internal peripheral I/O or 0-6 to use the interrupt. When an interrupt occurs, the interrupt controller resolves priority between this interrupt and other interrupt sources based on ILEVEL settings and finally compares its priority with the IMASK value to determine whether to forward an EI request to the CPU or keep it pending. The relationship between ILEVEL values and the IMASK values at which interrupts are accepted is shown below. Table 5.3.1 ILEVEL Settings and the Accepted IMASK Values LEVEL set value IMASK values at which interrupts are accepted 0 (ILEVEL = "000") Accepted when IMASK is 1-7 1 (ILEVEL = "001") Accepted when IMASK is 2-7 2 (ILEVEL = "010") Accepted when IMASK is 3-7 3 (ILEVEL = "011") Accepted when IMASK is 4-7 4 (ILEVEL = "100") Accepted when IMASK is 5-7 5 (ILEVEL = "101") Accepted when IMASK is 6-7 6 (ILEVEL = "110") Accepted when IMASK is 7 7 (ILEVEL = "111") Not accepted (interrupt disabled)

5-14 Rev.1.0 INTERRUPT CONTROLLER (ICU) The ICU vector table is used to set the start address of the interrupt handler for each internal peripheral I/O. The 31 interrupt sources are assigned the following vector table addresses. Table 5.4.1 ICU Vector Table Addresses Interrupt Source ICU Vector Table Address PDC input & error detection interrupt H'0000 009 – H'0000 0097 PWM off input interrupt H'0000 0098 – H'0000 009B Timer input interrupt 5 H'0000 009C – H'0000 009F Timer input interrupt 4 H'0000 00A0 – H'0000 00A3 Timer input interrupt 3 H'0000 00A4 – H'0000 00A7 Timer input interrupt 2 H'0000 00A8 – H'0000 00AB Timer input interrupt 1 H'0000 00AC – H'0000 00AF Timer input interrupt 0 H'0000 00B0 – H'0000 00B3 TOM0 output interrupt H'0000 00B4 – H'0000 00B7 TOM1 output interrupt H'0000 00B8 – H'0000 00BB TMS0 output interrupt H'0000 00BC – H'0000 00BF TID0 output interrupt H'0000 00C0 – H'0000 00C3 TID1 output interrupt H'0000 00C4 – H'0000 00C7 DMA0-4 interrupt H'0000 00C8 – H'0000 00CB A-D0 converter interrupt H'0000 00CC – H'0000 00CF SIO0 receive interrupt H'0000 00D0 – H'0000 00D3 SIO0 transmit interrupt H'0000 00D4 – H'0000 00D7 SIO1 receive interrupt H'0000 00D8 – H'0000 00DB SIO1 transmit interrupt H'0000 00DC – H'0000 00DF A-D1 converter interrupt H'0000 00E0 – H'0000 00E3 DMA5-9 interrupt H'0000 00E4 – H'0000 00E7 SIO2,3 transmit/receive interrupt H'0000 00E8 – H'0000 00EB SIO4 receive interrupt H'0000 00EC – H'0000 00EF SIO4 transmit interrupt H'0000 00F0 – H'0000 00F3 SIO5 receive interrupt H'0000 00F4 – H'0000 00F7 SIO5 transmit interrupt H'0000 00F8 – H'0000 00FB SIO6,7 transmit/receive interrupt H'0000 00FC – H'0000 00FE RTD interrupt H'0000 0100 – H'0000 0103 PDC compare match & error interrupt H'0000 0104 – H'0000 0107 CAN0 transmit/receive & error interrupt H'0000 0108 – H'0000 010B CAN1 transmit/receive & error interrupt H'0000 010C – H'0000 010F

5-15 Rev.1.0 INTERRUPT CONTROLLER (ICU) H'0000 0094 Address D0 D7 +0 address +1 address D8 D15 H'0000 0096 PDC Input & Error Detection Interrupt Handler Start Address (A0-A15) PDC Input & Error Detection Interrupt Handler Start Address(A16-A31) H'0000 0098 H'0000 009A PWM Off Input Interrupt Handler Start Address (A0-A15) PWM Off Input Interrupt Handler Start Address (A16-A31) H'0000 009C H'0000 009E Timer Input Interrupt 5 Handler Start Address (A0-A15) Timer Input Interrupt 5 Handler Start Address (A16-A31) H'0000 00A0 H'0000 00A2 H'0000 00A4 H'0000 00A6 H'0000 00A8 H'0000 00AA H'0000 00AC H'0000 00AE H'0000 00B0 H'0000 00B2 H'0000 00B4 H'0000 00B6 H'0000 00B8 H'0000 00BA H'0000 00BC H'0000 00BE H'0000 00C0 H'0000 00C2 H'0000 00C4 H'0000 00C6 Timer Input Interrupt 4 Handler Start Address (A0-A15) Timer Input Interrupt 4 Handler Start Address (A16-A31) Blank areas are reserved for future use. Timer Input Interrupt 3 Handler Start Address (A0-A15) Timer Input Interrupt 3 Handler Start Address (A16-A31) Timer Input Interrupt 2 Handler Start Address (A0-A15) Timer Input Interrupt 2 Handler Start Address (A16-A31) Timer Input Interrupt 1 Handler Start Address (A0-A15) Timer Input Interrupt 1 Handler Start Address (A16-A31) Timer Input Interrupt 0 Handler Start Address (A0-A15) Timer Input Interrupt 0 Handler Start Address (A16-A31) TOM0 Output Interrupt Handler Start Address (A0-A15) TOM0 Output Interrupt Handler Start Address (A16-A31) TOM1 Output Interrupt Handler Start Address (A0-A15) TOM1 Output Interrupt Handler Start Address (A16-A31) TMS0 Output Interrupt Handler Start Address (A0-A15) TMS0 Output Interrupt Handler Start Address (A16-A31) TID0 Output Interrupt Handler Start Address (A0-A15) TID0 Output Interrupt Handler Start Address (A16-A31) TID1 Output Interrupt Handler Start Address (A0-A15) TID1 Output Interrupt Handler Start Address (A16-A31) Figure 5.4.1 Memory Map of ICU Vector Table (1/2)

5-16 Rev.1.0 INTERRUPT CONTROLLER (ICU) H'0000 00C8 Address D0 D7 +0 address +1 address D8 D15 H'0000 00CA DMA0-4 Interrupt Handler Start Address (A0-A15) DMA0-4 Interrupt Handler Start Address (A16-A31) H'0000 00CC H'0000 00CE H'0000 00D0 H'0000 00D2 H'0000 00D4 H'0000 00D6 H'0000 00D8 H'0000 00DA H'0000 00DC H'0000 00DE A-D0 Conversion Interrupt Handler Start Address (A0-A15) A-D0 Conversion Interrupt Handler Start Address (A16-A31) SIO0 Receive Interrupt Handler Start Address (A0-A15) SIO0 Receive Interrupt Handler Start Address(A16-A31) SIO0 Transmit Interrupt Handler Start Address (A0-A15) SIO0 Transmit Interrupt Handler Start Address(A16-A31) SIO1 Receive Interrupt Handler Start Address (A0-A15) SIO1 Receive Interrupt Handler Start Address (A16-A31) SIO1 Transmit Interrupt Handler Start Address (A0-A15) SIO1 Transmit Interrupt Handler Start Address (A16-A31) H'0000 00E0 H'0000 00E2 H'0000 00E4 H'0000 00E6 H'0000 00E8 H'0000 00EA H'0000 00EC H'0000 00EE DMA5-9 Interrupt Handler Start Address (A0-A15) DMA5-9 Interrupt Handler Start Address (A16-A31) SIO4 Transmit/Receive Interrupt Handler Start Address (A0-A15) SIO4 Transmit/Receive Interrupt Handler Start Address (A16-A31) H'0000 00F0 H'0000 00F2 H'0000 00F4 H'0000 00F6 H'0000 00F8 H'0000 00FA H'0000 00FC H'0000 00FE H'0000 0100 H'0000 0102 H'0000 0104 H'0000 0106 H'0000 0108 H'0000 010A H'0000 010C H'0000 010E CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A0-A15) CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A16-A31) Blank areas are reserved for future use. A-D1 Conversion Interrupt Handler Start Address (A0-A15) A-D1 Conversion Interrupt Handler Start Address (A16-A31) SIO2,3 Transmit/Receive Interrupt Handler Start Address (A0-A15) SIO2,3 Transmit/Receive Interrupt Handler Start Address (A16-A31) SIO4 Transmit Interrupt Handler Start Address (A0-A15) SIO4 Transmit Interrupt Handler Start Address (A16-A31) SIO5 Receive Interrupt Handler Start Address (A0-A15) SIO5 Receive Interrupt Handler Start Address (A16-A31) SIO5 Transmit Interrupt Handler Start Address (A0-A15) SIO5 Transmit Interrupt Handler Start Address (A16-A31) SIO6,7 Transmit/Receive Interrupt Handler Start Address (A0-A15) SIO6,7 Transmit/Receive Interrupt Handler Start Address (A16-A31) RTD Interrupt Handler Start Address (A0-A15) RTD Interrupt Handler Start Address (A16-A31) PDC Compare Match & Error Interrupt Handler Start Address (A0-A15) PDC Compare Match & Error Interrupt Handler Start Address (A16-A31) CAN1 Transmit/Receive & Error Interrupt Handler Start Address (A0-A15) CAN1 Transmit/Receive & Error Interrupt Handler Start Address (A16-A31) Figure 5.4.2 Memory Map of ICU Vector Table (2/2)

5-17 Rev.1.0 INTERRUPT CONTROLLER (ICU)

5.5 Description of Interrupt Operation

5.5.1 Accepting Interrupts from Internal Peripheral I/O

An interrupt from any internal peripheral I/O is accepted when its priority level is found to be higher than the IMASK value by comparing its ILEVEL set value in the Interrupt Control Register and the Interrupt Mask Register's IMASK value. However, if multiple interrupt requests occur at the same time, their priority is resolved following the procedure described below to determine which interrupt request to accept. ➀ Compare the ILEVEL values set with the Interrupt Control Registers for the respective internal peripheral I/Os ➁ If the ILEVEL values are the same, use the predetermined hardware priority to arbitrate ➂ Compare the ILEVEL and the IMASK values When multiple interrupt requests occur at the same time, their priority levels set with ILEVEL of the respective Interrupt Control Registers are compared to select the interrupt request with the highest priority. If the selected interrupt requests have the same ILEVEL value, they are arbitrated according to the fixed hardware priority. The ILEVEL of the finally selected interrupt request is compared with the IMASK value, and if its priority is higher than the IMASK value, an EI request for it is sent to the CPU. Interrupt requests may be masked setting the Interrupt Mask Register and the Interrupt Control Register ILEVEL bits (level 7 disables interrupt) provided for each internal peripheral I/O, as well as setting the PSW Register IE bit. Figure 5.5.1 Example of Priority Resolution when Accepting an Interrupt Request Interrupt request Priority resolution by interrupt priority level (ILEVEL) Priority resolution by hardware priority Comparison with IMASK value MJT output interrupt 4 MJT output interrupt 3 MJT output interrupt 2 MJT output interrupt 1 DMA0-4 interrupt A-D0 converter interrupt (ILEVEL setting) Level 3 Level 4 Level 5 Level 3 Level 1 Level 3 Not requested Requested Requested Requested Requested Requested Fixed hardware priority is high Interrupt accepted if PSW Register IE bit = 1 Level 3 Level 3 Level 3 1 2 3 Can be accepted when IMASK = 4-7

5-18 Rev.1.0 INTERRUPT CONTROLLER (ICU) Table 5.5.1 Fixed Hardware Priority Priority Interrupt Source ICU Vector Table Address Type of Input Source High PDC input & error detection interrupt H'0000 0094 – H'0000 0097 Level PWM off input interrupt H'0000 0098 – H'0000 009B Level Timer input interrupt 5 (IRQ28) H'0000 009C – H'0000 009F Level Timer input interrupt 4 (IRQ27) H'0000 00A0 – H'0000 00A3 Level Timer input interrupt 3 (IRQ25) H'0000 00A4 – H'0000 00A7 Level Timer input interrupt 2 (IRQ24) H'0000 00A8 – H'0000 00AB Level Timer input interrupt 1 (IRQ23) H'0000 00AC – H'0000 00AF Level Timer input interrupt 0 (IRQ22) H'0000 00B0 – H'0000 00B3 Level TOM0 output interrupt (IRQ21) H'0000 00B4 – H'0000 00B7 Level TOM1 output interrupt (IRQ20) H'0000 00B8 – H'0000 00BB Level TMS0 output interrupt (IRQ19) H'0000 00BC – H'0000 00BF Level TID0 output interrupt (IRQ18) H'0000 00C0 – H'0000 00C3 Level TID1 output interrupt (IRQ17) H'0000 00C4 – H'0000 00C7 Level DMA0-4 interrupt H'0000 00C8 – H'0000 00CB Level A-D0 converter interrupt H'0000 00CC – H'0000 00CF Edge SIO0 receive interrupt H'0000 00D0 – H'0000 00D3 Edge SIO0 transmit interrupt H'0000 00D4 – H'0000 00D7 Edge SIO1 receive interrupt H'0000 00D8 – H'0000 00DB Edge SIO1 transmit interrupt H'0000 00DC – H'0000 00DF Edge A-D1 converter interrupt H'0000 00E0 – H'0000 00E3 Edge DMA5-9 interrupt H'0000 00E4 – H'0000 00E7 Level SIO2,3 transmit/receive interrupt H'0000 00E8 – H'0000 00EB Level SIO4 receive interrupt H'0000 00EC – H'0000 00EF Edge SIO4 transmit interrupt H'0000 00F0 – H'0000 00F3 Edge SIO5 receive interrupt H'0000 00F4 – H'0000 00F7 Edge SIO5 transmit interrupt H'0000 00F8 – H'0000 00FB Edge SIO6,7 transmit/receive interrupt H'0000 00FC – H'0000 00FF Level RTD interrupt H'0000 0100 – H'0000 0103 Edge PDC compare match & error interruptH'0000 0100 – H'0000 0103 Level CAN0 transmit/receive & error interruptH'0000 0108 – H'0000 010B Level Low CAN1 transmit/receive & error interruptH'0000 010C – H'0000 010F Level

5-19 Rev.1.0 INTERRUPT CONTROLLER (ICU) Table 5.5.2 ILEVEL Settings and the Accepted IMASK Values ILEVEL set value IMASK values at which interrupts are accepted 0 (ILEVEL = "000") Accepted when IMASK is 1-7 1 (ILEVEL = "001") Accepted when IMASK is 2-7 2 (ILEVEL = "010") Accepted when IMASK is 3-7 3 (ILEVEL = "011") Accepted when IMASK is 4-7 4 (ILEVEL = "100") Accepted when IMASK is 5-7 5 (ILEVEL = "101") Accepted when IMASK is 6-7 6 (ILEVEL = "110") Accepted when IMASK is 7 7 (ILEVEL = "111") Not accepted (interrupt disabled)

5-20 Rev.1.0 INTERRUPT CONTROLLER (ICU)

5.5.2 Processing of Internal Peripheral I/O Interrupts by Handler

(1) Branching to the interrupt handler When the CPU accepts an interrupt, it branches to the EIT vector entry after performing hardware preprocessing as described in Section 4.3, "EIT Processing Procedure." The EIT vector entry assigned to the External Interrupt (EI) resides at address H'0000 0080, at which the instruction for branching to the beginning of the interrupt handler routine for the External Interrupt is written by the user. Note that this is the branch instruction, and not the jump address. (2) Processing in the interrupt handler In the External Interrupt (EI) handler, first save the BPC Register, PSW Register, and general- purpose registers to the stack. Next, read the Interrupt Mask Register (IMASK) and save it to the stack. Then read the Interrupt Vector Register (IVECT). Always be sure to read the IMASK before reading the IVECT. Reading the IMASK and the IVECT each activates operations necessary to clear the interrupt request to the CPU and accept the next interrupt. On top of that, reading the IVECT causes NEW_IMASK to be set in the IMASK Register and the accepted interrupt request to be cleared (not cleared in the case of level-recognized interrupt sources, however). The IVECT Register has set in it the 16 low-order bits of the ICU vector table address for the accepted interrupt source. Read the IVECT Register using a signed halfword load instruction (LDH instruction) to get the vector table address and then the content of the ICU interrupt vector table at that address. The ICU vector table contains the start address of the interrupt handler for each internal peripheral I/O, so branch to the address thus read out and execute the interrupt handler. When returning from the interrupt handler, clear the PSW Register IE bit to 0 to disable interrupts before restoring the IMASK value. (3) Identifying the interrupt source If any internal peripheral I/O has multiple interrupt sources, inspect the Interrupt Status Register for that internal peripheral I/O to identify the interrupt source. (4) Enabling multiple interrupts To enable another interrupt within an interrupt handler, set the PSW Register IE (Interrupt Enable) bit to 1 in that interrupt handler to enable the interrupt to be accepted. However, be sure to save each register (BPC, PSW, general-purpose registers, and IMASK) to the stack before setting the IE bit.

5-21 Rev.1.0 INTERRUPT CONTROLLER (ICU) H'0000 0080 BRA instruction Read Interrupt Vector Register (IVECT) Read ICU vector table Branch to interrupt handler for the internal peripheral I/O RTE H'0080 0004 H'0000 0094 H'0000 010F Interrupt handler Interrupt handler EI (External Interrupt) handler EI (External Interrupt) vector entry Address Program being executed Interrupt generated IVECT Save BPC to stack Save PSW to stack Save general-purpose registers to stack Restore BPC Restore PSW Restore general- purpose registers Read Interrupt Mask Register (IMASK) and save to stack IMASK H'0080 0000 PSW Register IE bit = 1 PSW Register IE bit = 0 Restore Interrupt Mask Register (IMASK) 10 101 : Processing by interrupt handler for EI : When enabling another interrupt in an interrupt ICU vector table Note: For operations performed when accepting EIT and returning from processing, refer to Section 4.3, "EIT Processing Procedure." (Note) (Note) Figure 5.5.2 Example of Operations Performed for Interrupts from Internal Peripheral I/O

5-22 Rev.1.0 INTERRUPT CONTROLLER (ICU)

5.6 Description of System Break Interrupt (SBI) Operation

5.6.1 Accepting SBI Interrupt

The System Break Interrupt (SBI) is an emergency interrupt issued when power outage is detected or a fault condition is notified from an external watchdog timer. The SBI interrupt is always accepted___ by a falling edge of the SBI signal regardless of how the PSW Register IE bit is set, and cannot be masked.

5.6.2 SBI Processing by Handler

After processing for the SBI is finished, always be sure to terminate or reset the system without returning to the program the CPU was executing when the interrupt occurred. Figure 5.6.1 Example of Operation for SBI Interrupt H'0000 0010 BRA instruction SBI (System Break Interrupt) handler SBI (System Break Interrupt) vector entry Program being executed SBI generated System terminate processing Note: Do not return to the program the CPU was executing when the interrupt occurred. Terminate or reset the system

6.1 Outline of the Internal Memory

6.2 Internal RAM

6.3 Internal Flash Memory

6.4 Internal Flash Memory Related

6.5 Programming the Internal

6.6 Boot ROM

6.7 Virtual-flash Emulation Function

6.8 Connecting a Serial Programmer

6.9 Precautions on Rewriting

6-2 Rev.1.0 INTERNAL MEMORY The M32172F2/M32173F2 contains the following types of memory:

• 16-Kbyte RAM for the M32172F2 or 32-Kbyte RAM for the M32173F2
• 256-Kbyte flash memory

Specifications of the internal RAM are shown below. Table 6.2.1 Specifications of the Internal RAM Item Specification Capacity M32172F2: 16 Kbytes; M32173F2: 32 Kbytes Location address M32172F2: H'0080 4000-H'0080 7FFF M32173F2: H'0080 4000-H'0080 BFFF Wait insertion Operates with no wait cycles (when CPU clock = 40 MHz) Internal bus connection Connects to 32-bit bus Dual port By using the RTD (Real-time Debugger), data can be read out (monitored) or written to any area of the internal RAM via serial communication from the outside independently of the CPU. (For details, refer to Chapter 14, "Real-time Debugger.") Specifications of the internal flash memory are shown below. Table 6.3.1 Specifications of the Internal Flash Memory Item Specification Capacity M32172F2, M32173F2: 256 Kbytes Location address M32172F2, M32173F2: H'0000 0000-H'0003 FFFF Wait insertion Operates with no wait cycles (when CPU clock = 40 MHz) Durability Can be rewritten 100 times Internal bus connection Connects to 32-bit bus Other Virtual-flash emulation function is included. (For details, refer to Section 6.7, "Virtual-flash Emulation Function." )

6-3 Rev.1.0 INTERNAL MEMORY

6.4 Internal Flash Memory Related Registers

A register map associated with the internal flash memory is shown below. Figure 6.4.1 Internal Flash Memory Related Register Map Virtual-flash L Bank Register 1 Virtual-flash L Bank Register 2 (FELBANK2)(Note) H'0080 07E0 H'0080 07E2 Address D0 D7 +0 address +1 address D8 D15 H'0080 07E4 Flash Control Register 1 (FCNT1) Flash Mode Register (FMOD) Flash Status Register 1 (FSTAT1) Flash Control Register 2 (FCNT2) Flash Control Register 3 (FCNT3) Flash Control Register 4 (FCNT4) H'0080 07E6 H'0080 07E8 H'0080 07EA H'0080 07EC H'0080 07EE Virtual-flash L Bank Register 0 (FELBANK0) Virtual-flash S Bank Register 0 (FESBANK0)(Note) Virtual-flash S Bank Register 1 (FESBANK1)(Note) H'0080 07F0 H'0080 07F2 Blank areas are reserved for future use. Note: The FELBANK2, FESBANK0, and FESBANK1 Registers are nonexistent for the M32172F2. (FELBANK1)

6-4 Rev.1.0 D 0 123456 D 7 FPMOD <When reset: H'0?> D Bit Name Function R W 0-6 No functions assigned 0 –

7 FPMOD 0: FP pin = low –

(External FP pin status) 1: FP pin = high

6.4.1 Flash Mode Register

I Flash Mode Register (FMOD) <Address: H'0080 07E0> The Flash Mode Register (FMOD) is a read-only status register, with FPMOD showing the status of the FP (Flash Protect) pin. The flash memory is enabled for write only when FPMOD = 1. Write to the flash memory executed when FPMOD = 0 has no effect. INTERNAL MEMORY

6-5 Rev.1.0

6.4.2 Flash Status Registers

The 32172/32173 has two registers to show the flash memory status, one of which is Flash Status Register 1 (FSTAT1) located in the SFR area (address H'0080 07E1), and the other is Flash Status Register 2 (FSTAT2) included in the flash memory itself. Use these two status registers (FSTAT1, FSTAT2) to control operations when programming or erasing the flash memory. I Flash Status Register 1 (FSTAT1) <Address: H'0080 07E1> INTERNAL MEMORY <When reset: H'01> D Bit Name Function R W 8-14 No functions assigned 0 –

15 FSTAT 0: Busy –

(Ready/Busy status) 1: Ready The Flash Status Register 1 (FSTAT1) is a read-only status register used to know the status of whether the flash memory is being programmed or erased. When the FSTAT bit = 0, the flash memory is being programmed or erased, during which time the flash memory is disabled against access for programming. D 8 9 1 01 11 21 31 4 D 1 5 FSTAT

6-6 Rev.1.0 I Flash Status Register 2 (FSTAT2) D 8 9 1 01 11 21 31 4 D 1 5 FBUSY ERASE WRERR1 WRERR2 <When reset: H'80> D Bit Name Function R W

8 FBUSY 0: Being programmed or erased –

(Flash busy) 1: Ready state

9 No functions assigned 0 –

10 ERASE 0: Erase normally operating or finished –

(Auto erase operating status) 1: Erase error occurred

11 WRERR1 0: Programming normally operating or finished–

(Program operating status 1) 1: Programming error occurred

12 WRERR2 0: Programming normally operating or finished–

(Program operating status 2) 1: Over-programming occurred 13-15 No functions assigned 0 – The Flash Status Register 2 (FSTAT2) consists of the following four read-only status bits that indicate the operating status of the flash memory. (1) FBUSY (flash busy) bit (D8) The FBUSY bit is used to determine whether the operation is under way or finished when programming or erasing the flash memory. The programming/erase operation is under way when FBUSY = 0 or finished when FBUSY = 1. (2) ERASE (auto erase operating status) bit (D10) The ERASE bit is used to determine whether an error occurred after the CPU has finished erasing the flash memory. The erase operation terminated normally when ERASE = 0 or terminated in an error when ERASE = 1. (3) WRERR1 (program operating status 1) bit (D11) The WRERR1 bit is used to determine whether an error occurred after the CPU has finished programming the flash memory. The programming operation terminated normally when WRERR1 = 0 or terminated in an error when WRERR1 = 1. The condition under which WRERR1 is set to 1 is when any bit other than those that must be 0 is found to be a 0 by comparison between the write data and the data in the flash memory. INTERNAL MEMORY

6-7 Rev.1.0 (4) WRERR2 (program operating status 2) bit (D12) The WRERR2 bit is used to determine whether an error occurred after the CPU has finished programming the flash memory. The programming operation terminated normally when WRERR2 = 0 or terminated in an error when WRERR2 = 1. The condition for which this bit is set to 1 is that even when the write operation was executed a specified number of times repeatedly, the flash memory could not be programmed. Note: This status register is provided within the flash memory, so that by writing a read status command (H'7070) to any address of the internal flash memory, this register is enabled for readout. For details, refer to Section 6.5, "Programming the Internal Flash Memory." INTERNAL MEMORY

6-8 Rev.1.0 <When reset: H'00> D Bit Name Function R W 0-2 No functions assigned 0 –

3 FENTRY 0: Normal read

(Flash mode entry) 1: Erase/program possible 4-6 No functions assigned 0 –

7 FEMMOD 0: Normal mode

(Virtual-flash emulation mode) 1: Virtual-flash emulation mode D 0 123456 D 7 FENTRY FEMMOD

6.4.3 Flash Control Registers

I Flash Control Register 1 (FCNT1) <Address:H'0080 07E2> The Flash Control Register 1 (FCNT1) consists of the following two bits that control the internal flash memory. (1) FENTRY (flash mode entry) bit (D3) The FENTRY bit controls state transition to flash E/W enable mode. Flash E/W enable mode can be entered only when FENTRY = 1. To set the FENTRY bit to 1, write 0 and then 1 to this bit successively while the FP pin = high. The FENTRY bit is cleared under the following conditions:

• When the microcomputer is reset
• When a 0 is written to the FENTRY bit
• When the FP pin status is changed from high to low INTERNAL MEMORY

6-9 Rev.1.0 When using a program in the flash memory while the FENTRY bit = 0, the EI vector entry is at the flash memory address H'0000 0080. To run the flash rewrite program in RAM while the FENTRY bit = 1, the EI vector entry is at the RAM address H'0080 4000, in which case flash rewrite operation can be controlled using an interrupt. Table 6.4.1 EI Vector Entry Transition by FENTRY FENTRY EI Vector Entry Address

0 Flash area H'0000 0080

1 Internal RAM area H'0080 4000

(2) FEMMOD (virtual-flash emulation mode) bit (D7) The FEMMOD bit controls state transition to virtual-flash emulation mode. The CPU is placed in virtual-flash emulation mode by setting the FEMMOD bit to 1 while the FENTRY bit = 0. (For details, refer to Section 6.7, "Virtual-flash Emulation Function.") INTERNAL MEMORY

6-10 Rev.1.0 I Flash Control Register 2 (FCNT2) <Address: H'0080 07E3> D 8 9 1 01 11 21 31 4 D 1 5 FPROT <When reset: H'00> D Bit Name Function R W 8-14 No functions assigned 0 –

15 FPROT 0: Enables protection by lock bits

(Unlock) 1: Disables protection by lock bits The Flash Control Register 2 (FCNT2) controls flash memory protection by lock bits (disables the internal flash memory against erase/programming). Protection is disabled by setting the FPROT bit to 1, so that blocks of the flash memory protected by lock bits can be erased/programmed. To set the FPROT bit to 1, write 0 and then 1 to this bit successively while the FENTRY bit = 1. The FPROT bit is cleared to 0 immediately after chip reset or by writing 0 to this bit, pulling input on the FP pin low, or resetting the FENTRY bit to 0. Figure 6.4.2 Protection Unlocking Flow INTERNAL MEMORY FPROT=0 FENTRY=1 YES NO FENTRY=1 FPROT=1 If write to any other area occurs during this interval, FPROT is not set to 1 FPROT=0 FPROT=1

6-11 Rev.1.0 I Flash Control Register 3 (FCNT3) <Address: H'0080 07E4> D 0 123456 D 7 FELEVEL <When reset: H'00> D Bit Name Function R W 0-6 No functions assigned 0 –

7 FELEVEL 0: Normal level

(Erase margin up) 1: Increases erase margin The Flash Control Register 3 (FCNT3) controls the depth of erase levels when erasing the internal flash memory with an erase command. By setting the FELEVEL bit is set to 1, the flash memory erase level can be deepened, which will result in an increased reliability margin. INTERNAL MEMORY

6-12 Rev.1.0 I Flash Control Register 4 (FCNT4) <Address: H'0080 07E5> D 8 9 1 01 11 21 31 4 D 1 5 FRESET <When reset: H'00> D Bit Name Function R W 8-14 No functions assigned 0 –

15 FRESET 0: No operation

(Reset flash) 1: Resets the flash memory The Flash Control Register 4 (FCNT4) controls canceling the erase or program operation in the middle or initializing each status bit of Flash Status Register 2 (FSTAT2). Setting the FRESET bit to 1 cancels the erase or program operation in the middle and initializes each status bit of the FSTAT2 Register (to H'80). The FRESET bit is effective only when the FENTRY bit = 1. Information of the FRESET bit is ignored unless the FENTRY bit = 1. When programming or erasing the flash memory, make sure the FRESET bit = 0. INTERNAL MEMORY

6-13 Rev.1.0 FRESET=1 YES NO FENTRY=1 Program/erase flash memory Error detected Program/erase operation terminated normally FRESET=0 Program/erase flash memory FENTRY=0 Figure 6.4.3 Example for Using the FCNT4 Register INTERNAL MEMORY

6-14 Rev.1.0

6.4.4 Virtual-flash L Bank Registers

I Virtual-flash L Bank Register 0 (FELBANK0) <Address: H'0080 07E8> I Virtual-flash L Bank Register 1 (FELBANK1) <Address: H'0080 07EA> I Virtual-flash L Bank Register 2 (FELBANK2) <Address: H'0080 07EC> <When reset: H'0000> D Bit Name Function R W

0 MODENL 0: Disables virtual-flash function

(Virtual-flash emulation enable) 1: Enables virtual-flash function 1-7 No functions assigned 0 – 8-14 LBANKAD Start address A12-A18 of the desired (L bank address) L bank

15 No functions assigned 0 –

Note: This register must always be accessed in halfwords. (1) MODENL (virtual-flash emulation enable) bit (D0) After entering virtual-flash emulation mode (by setting the FEMMOD bit to 1 while the FENTRY bit = 0), set the MODENL bit to 1 and the virtual-flash emulation function is enabled for the L bank area selected with LBANKAD bits. (2) LBANKAD (L bank address) bits (D8-D14) The LBANKAD bits select one of the L banks divided in units of 8 KB. Use these seven LBANKAD bits to set the start address A12-A18 (of the 32-bit address) of the desired L bank. (For details, refer to Section 6.7, "Virtual-flash Emulation Function.") Note: The M32172F2 does not have Virtual-flash L Bank Register 2 (FELBANK2). INTERNAL MEMORY D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 LBANKAD

6-15 Rev.1.0

6.4.5 Virtual-flash S Bank Registers

I Virtual-flash S Bank Register 0 (FESBANK0) <Address: H'0080 07F0> I Virtual-flash S Bank Register 1 (FESBANK1) <Address: H'0080 07F2> <When reset: H'0000> D Bit Name Function R W

0 MODENS 0: Disables virtual-flash function

(Virtual-flash emulation enable) 1: Enables virtual-flash function 1-7 No functions assigned 0 – 8-15 SBANKAD Start address A12-A19 of the relevant (S bank address) S bank (1) MODENS (virtual-flash emulation enable) bit (D0) After entering virtual-flash emulation mode (by setting the FEMMOD bit to 1 while the FENTRY bit = 0), set the MODENS bit to 1 and the virtual-flash emulation function is enabled for the S bank area selected with SBANKAD bits. (2) SBANKAD (S bank address) bits (D8-D15) The SBANKAD bits select one of the S banks divided in units of 4 KB. Use these eight SBANKAD bits to set the start address A12-A19 (of the 32-bit address) of the desired S bank. (For details, refer to Section 6.7, "Virtual-flash Emulation Function.") Note:The M32172F2 does not have the Virtual-flash S Bank Registers (FESBANK0 and FESBANK1). INTERNAL MEMORY D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 MOD ENS SBANKAD

6-16 Rev.1.0

6.5 Programming the Internal Flash Memory

6.5.1 Outline of Flash Memory Programming

There are following two methods for writing to the internal flash memory. (1) When no write programs exist in the internal flash memory Set the FP pin = high, MOD0 = high, and MOD1 = low to enter boot mode. In this case, the reset vector entry is at the beginning of the boot program area (H'8000 0000). (Normally the reset vector entry is at the start address of the internal flash memory.) Use the boot program to transfer the "flash write program" from the boot area into the internal RAM. Then jump to the RAM and by using the program in the RAM, set the Flash Control Register 1 FENTRY bit to 1 to enable the flash memory for write (flash E/W enable mode). After that, use the "flash write program" that has been transferred into the RAM to write to the internal flash memory. (2) When a write program already exists in the internal flash memory Set the FP pin = high, MOD0 = low, and MOD1 = low to enter single-chip mode. Transfer the "flash write program" from the internal flash memory in which it was prepared beforehand into the internal RAM. Then jump to the RAM and by using the program in the RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1 to enable the flash memory for write (flash E/W enable mode). After that, use the "flash write program" that has been transferred into the RAM to write to the internal flash memory. Or you can set the FP pin = high, MOD0 = low, and MOD1 = high to enter flash E/W enable mode in external extended mode. During flash E/W enable mode (FP pin = 1, FENTRY = 1), the EIT vector entry for External Interrupt (EI) moves to the start address of the internal RAM (H'0080 4000). During normal mode, it is at the flash area address (H'0000 0080). INTERNAL MEMORY

6-17 Rev.1.0 Figure 6.5.1 EI Vector Entry when in Flash E/W Enable Mode INTERNAL MEMORY ( H'0000 0080 ) H'0000 0000 H'00FF FFFF H'0080 4000 Internal ROM area Internal RAM H'0080 3FFF Flash E/W enable mode (FENTRY=1) Normal mode (FENTRY=0) H'0000 0000 H'0080 3FFF EI vector entry ( H'0080 4000 )H'0080 4000 H'00FF FFFF

6-18 Rev.1.0 (1) When the write programs do not exist in the internal flash memory Use the program in the boot ROM located on the 32172/32173 memory map to write to the flash memory. To transfer the write data, use serial I/O1 in clock-synchronized serial mode. This method is used for writing to the flash memory using a flash programmer. Figure 6.5.2 Procedure for Writing to the Internal Flash Memory (when no write programs exist in the flash memory) INTERNAL MEMORY MOD1= L SIO1 CPU RAM Flash memory FP=L or H RAM RAM <Step 1>

• Initial state (no write programs exist in the flash memory) <Step 2> <Step 3> M32R/E M32R/E M32R/E External device Flash write data Flash memory MOD0=L Boot ROM MOD1= LFP=H MOD0=H MOD1= LFP=H MOD0=H RESET=L RESET=H RESET=H Write data Flash memory Boot ROM Flash write program Boot ROM External device Write data
• Set the FP pin = high, MOD0 pin = high, and MOD1 pin = low to place the microcomputer in boot mode.
• Negate reset, then start up from the boot program.
• Transfer the flash write program from the boot ROM into the RAM.
• Jump to the flash write program now in the RAM.
• Using the flash write program in the RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1 to enter flash E/W enable mode.
• Write data to the internal flash memory using the flash write program.
• When the CPU finished writing data, return MOD0 low and jump to the flash memory or go to normal mode by resetting the microcomputer. External device Write data

6-19 Rev.1.0 RESET MOD0 FENTRY FP MOD1 POWER ON Select mode Negate reset (start the boot program) Select mode Negate reset Write to the flash memory using the boot program Set up using the boot program Figure 6.5.3 Timing at Which Writing to the Internal Flash Memory (when no write programs exist in the flash memory) INTERNAL MEMORY

6-20 Rev.1.0 (2) When a write program already exists in the internal flash memory Use the write program available in the internal flash memory to write to the flash memory. For this write operation, use the internal peripheral circuits as needed for the system to which you are writing. (The data bus, serial I/O, and ports can be used.) The following shows an example where the flash memory is written to in single-chip mode using serial I/O0. Figure 6.5.4 Procedure for Writing to the Internal Flash Memory (when write program exists in the flash memory) INTERNAL MEMORY MOD1= L SIO0 CPU RAM Flash write program FP=L or H Write data RAM RAM <Step 1>

• Initial state (write program exists in the flash memory)
• Ordinary program in the flash memory is being executed <Step 2> <Step 3> M32R/E M32R/E M32R/E External device Flash write data Flash memory MOD0=L Boot ROM MOD1= LFP=H MOD0=L MOD1= LFP=H MOD0=L Flash memory Boot ROM Flash write program Boot ROM
• Set the FP pin = high, MOD0 pin = low, and MOD1 pin = low to place the microcomputer in single-chip mode.
• After inspecting the FP and MOD1 pin levels, transfer the flash write program from the flash memory area into the RAM.
• Jump to the flash write program now in the RAM. Write data External device
• Using the flash write program in the RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1 to enter flash E/W enable mode.
• Write data to the internal flash memory using the flash write program in the RAM.
• When the CPU finished writing data, jump to the program in the flash memory or go to normal mode by resetting the microcomputer. Write data External device

6-21 Rev.1.0 RESET MOD0 FENTRY FP "H"or"L" "H"or"L" (Single-chip or external extended mode)MOD1 "L" "H"or"L" Write to the flash memory using the flash write program Flash rewrite startsFlash mode ON Flash mode OFF Transfer the flash rewrite program to the RAM Set up using the flash write program Figure 6.5.5 Timing at Which Writing to the Internal Flash Memory (when write program exists in the flash memory) INTERNAL MEMORY

6-22 Rev.1.0

6.5.2 Controlling Operation Modes during Flash Programming

Chip operation modes are set using MOD0, MOD1, and Flash Control Register 1 (FCNT1) FENTRY bit. Operation modes during flash programming are listed below. Table 6.5.1 Setting Operation Modes during Flash Programming FP MOD0 MOD1 FENTRY (Note) Operation Mode Reset Vector Entry EI Vector Entry 00 0 – Single-chip mode Flash memory Flash area 1 0 0 0 start address (H'0000 0080) (H'0000 0000) 01 0 – Processor mode External area External area start address (H'0000 0080) (H'0000 0000) 00 1 – External extended Flash memory Flash area 1 0 1 0 mode start address (H'0000 0080) (H'0000 0000) 1 0 0 1 Single-chip Flash memory Internal RAM mode + start address start address flash E/W (H'0000 0000) (H'0080 4000) enable 1 1 0 0 Boot mode Boot program area Flash area start address (H'0000 0080) (H'8000 0000) 1 1 0 1 Boot mode + Boot program area Internal RAM flash E/W start address start address enable (H'8000 0000) (H'0080 4000) 1 0 1 1 External extended Flash memory Internal RAM mode + flash start address start address E/W enable (H'0000 0000) (H'0080 4000) – 11 – reserved – – Note: Shows the status of the Flash Control Register 1 (FCNT1) FENTRY bit. (- denotes "Don't care") (1) Flash E/W enable mode Flash E/W enable mode is a mode in which the internal flash memory can be programmed or erased. In flash E/W enable mode, no programs can be executed in the internal flash memory. Therefore, you need to transfer the necessary program into the internal RAM before entering flash E/W enable mode, so the program can be run from the RAM. INTERNAL MEMORY

6-23 Rev.1.0 (2) Entering flash E/W enable mode The microcomputer can enter flash E/W enable mode only when it is operating in single-chip or external extended mode. The microcomputer enters flash E/W enable mode only when the FP pin is at the high level and the Flash Control Register 1 (FCNT1) FENTRY bit = 1, and cannot enter flash E/W enable mode when operating in processor mode or the FP pin is low. (3) Detecting the MOD0 and MOD1 pin levels Whether the MOD0 and MOD1 pin levels (high or low) can be detected by inspecting the P8 Port Data Register (H'0080 0708) MOD0DT and MOD1DT bits. I P8 Port Data Register (P8DATA) <Address: H'0080 0708> INTERNAL MEMORY <When reset: Indeterminate> D Bit Name Function R W

0 MOD0DT 0: MOD0 pin = low –

(MOD0 data) 1: MOD0 pin = high

1 MOD1DT 0: MOD1 pin = low –

(MOD1 data) 1: MOD1 pin = high

2 P82DT • When the direction bit is set to 0

(Port P82 data) (input mode) by Port Direction Register

3 P83DT 0: Port input pin = low

(Port P83 data) 1: Port input pin = high

4 P84DT • When the direction bit is set to 1

(Port P84 data) (output mode) by Port Direction Register

5 P85DT 0: Port output latch = low

(Port P85 data) 1: Port output latch = high

6 P86DT

(Port P86 data)

7 P87DT

(Port P87 data) D 0 123456 D 7 MOD0DT MOD1DT P82DT P83DT P84DT P85DT P86DT P87DT

6-24 Rev.1.0 END START Go to one of the following modes

• Single-chip mode + flash E/W enable mode
• Boot mode + flash E/W enable mode
• External extended mode + flash E/W enable mode Transfer E/W program to internal RAM in each mode Set Flash Control Register in SFR area (FCNT1, H’0080 07E2) flash entry (FENTRY) bit to 0 Set Flash Control Register in SFR area (FCNT1, H’0080 07E2) flash entry (FENTRY) bit to 1 Execute flash E/W command and various read commands (Note) Change to the flash E/W program Wait for 1 µs (as counted by hardware or software timer) Jump to flash memory or reset the microcomputer Change to normal mode Check MOD0,1 and FP pin levels OK NO END FMOD(H ’0080 07E0) FPMOD P8DATA(H ’0080 0708) MOD0DT MOD1DT Note: For details about each command, refer to Section 6.5.3, "Procedure for Programming the Internal Flash Memory." Figure 6.5.6 Procedure for Entering Flash E/W Enable Mode INTERNAL MEMORY

6-25 Rev.1.0

6.5.3 Procedure for Programming the Internal Flash Memory

To program the internal flash memory, use the flash write program which has been transferred from the flash memory into the internal RAM after entering flash E/W enable mode. In flash E/W enable mode, unlike in normal mode, data cannot be read from the internal flash memory and, hence, no programs in the flash memory can be executed. Therefore, the flash write program must be prepared in the internal RAM before entering flash E/W enable mode. (Once flash E/W enable mode is entered into, accessing the flash memory is inhibited unless accessed with flash commands.) To access the internal flash memory in flash E/W enable mode, issue a command for the internal flash memory address to be accessed. The commands that can be issued in flash E/W enable mode are listed below. Note: During flash E/W enable mode, the flash memory cannot be accessed for read/write wordwise. Table 6.5.2 Commands in Flash E/W Enable Mode Command Name Command Data Issued Read Array command H'FFFF Page Program command H'4141 Lock Bit Program command H'7777 Block Erase command H'2020 Erase All Unlock Blocks command H'A7A7 Read Status Register command H'7070 Clear Status Register command H'5050 Read Lock Bit Status command H'7171 Verify command (Note) H'D0D0 Note: Use this command you performed Lock Bit Program, Block Erase, or Erase All Unlock Blocks operation. (1) Read Array command The internal flash memory is placed in read mode by writing command data H'FFFF to any flash memory address. Read the desired address, and the memory content at that address is read out. To exit flash E/W enable mode, be sure to run the Read Array command before exiting flash E/W enable mode. INTERNAL MEMORY

6-26 Rev.1.0 (2) Page Program command The flash memory is programmed in units of pages, each page consisting of 256 bytes (lower address H'00-H'FF). To write data to the flash memory (i.e., to program the flash memory), write the program command H'4141 to any address of the internal flash memory and then write the program data to the desired flash memory address. Protected blocks of the flash memory cannot be accessed for write with the Page Program command. Page Program is automatically performed by an internal control circuit, and the conpletion of programming can be verified by checking the Flash Status Register 1 (FSTAT1) FSTAT1 bit. (Refer to Section 6.4.2, "Flash Status Registers.") While the FSTAT1 bit = 0, the next programming can not be performed. (3) Lock Bit Program command The flash memory can be protected (against write and erase) in units of blocks. The Lock Bit Program command is used to protect any memory block. Write the lock bit command data H'7777 to any address of the internal flash memory. Next, write the Verify command data H'D0D0 to the last even address of the memory block to be protected, and this memory block is protected (against write and erase). To remove protection, disable lock bit-effectuated protection using the Flash Control Register 2(FCNT2) FPROT bit (see Section 6.4.3, "Flash Control Registers") and erase the block whose protection you want to remove. (The content of this memory block is also erased. Table 6.5.3 M32172F2/M32173F2 Target Blocks and the Addresses to Specify Target Block Address to Specify

0 H'0000 3FFE

1 H'0000 5FFE

2 H'0000 7FFE

3 H'0000 FFFE

4 H'0001 FFFE

5 H'0002 FFFE

6 H'0003 FFFE

6-27 Rev.1.0 H ’0002 0000 8KB 16KB 8KB 32KB 64KB H ’0000 0000 H ’0000 7FFF H ’0000 8000 H ’0001 FFFF H ’0000 3FFF H ’0000 4000 H ’0000 FFFF H ’0001 0000 Internal flash memory area (256 KB) Block 2 Block 3 Block 4 H ’0000 5FFF H ’0000 6000 64KB H ’0002 FFFF Block 5 64KB Block 0 Block 6 Uneven blocks Even blocks H ’0003 0000 H ’0003 FFFF H ’0004 0000 Block 1 Figure 6.5.7 M32172F2/M32173F2 Flash Memory Block Configuration INTERNAL MEMORY

6-28 Rev.1.0 (4) Block Erase command The Block Erase command erases the contents of the internal flash memory one block at a time. For Block Erase, write the command data H'2020 to any address of the internal flash memory. Next, write the confirm command data H'D0D0 to the last even address of the memory block to be erased. (See Table 6.5.3, "Target Blocks and the Addresses to Specify.") The content of the memory block is erased. Protected blocks of the flash memory cannot be accessed for erase with the Block Erase command. Block Erase is automatically performed by the internal control circuit, and the completion of Block Erase can be verified by checking the Flash Status Register 1 (FSTAT1) FSTAT1 bit. (Refer to Section 6.4.2, "Flash Status Registers.") While the FSTAT1 bit = 0, you cannot erase the next block. (5) Erase All Unlock Blocks command The Erase All Unlock Blocks command erases all unprotected memory blocks. To erase all unprotected memory blocks, write the command data H'A7A7 to any address of the internal flash memory. Next, write the command data H'D0D0 to any address of the internal flash memory, and all of the unprotected memory blocks are erased. (6) Read Status Register command The Read Status Register command reads the content of Flash Status Register 2 (FSTAT2) that indicates whether programming or erase operation on flash memory has terminated normally or in an error. To read Flash Status Register 2, write the command data H'7070 to any address of the internal flash memory. Next, read any address of the internal flash memory, and Flash Status Register 2 (FSTAT2) is read out. (7) Clear Status Register command The Clear Status Register command clears the Flash Status Register 2 (FSTAT2) ERASE (auto erase operating status), WRERR1 (program operating status 1), and WRERR2 (program operating status 2) bits to 0. Write the command data H'5050 to any address of the internal flash memory, and Flash Status Register 2 is cleared to 0. If an error occurs when programming or erasing the flash memory and the Flash Status Register 2 (FSTAT2) ERASE (auto erase operating status), WRERR1 (program operating status 1), or WRERR2 (program operating status 2) bit is set to 1, you cannot perform the next program or erase operation unless WRERR1 (Program operating condition 1) or WRERR2 (Program operating condition 2) is cleared to 0. INTERNAL MEMORY

6-29 Rev.1.0 (8) Read Lock Bit Status command The Read Lock Bit Status command is used to verify whether memory blocks are protected (against write/erase) or not protected. Write the command data H'7171 to any address of the internal flash memory. Next, read the last even address of the desired block (See Table 6.5.3, "Target Blocks and the Addresses to Specify."), and you know whether the block you read is protected or not. If the FLBST0 (lock bit 0) and FLBST1 (lock bit 1) bits of the data you read are 0, it means that the memory block is protected. If the FLBST0 (lock bit 0) and FLBST1 (lock bit 1) bits of the data you read are 1, it means that the memory block is not protected. I Lock Bit Status Register (FLBST) INTERNAL MEMORY <When reset: Indeterminate> D Bit Name Function R W 0 No functions assigned ? –

1 FLBST0 0: Protected –

(Lock bit 0) 1: Not protected 2-8 No functions assigned ? –

9 FLBST1 0: Protected –

(Lock bit 1) 1: Not protected (Same content as FLBST0 is output) 10-15 No functions assigned ? – The Lock Bit Status Register is a read-only register which contains lock bits independently for each block. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 FLBST0 FLBST1

6-30 Rev.1.0 Follow the procedure below to write to the lock bits. a) Setting the lock bits to 0 (protect a memory block) Issue the lock bit program command (H'7777) to the memory block to be protected. b) Setting the lock bits to 1 (unprotect a memory block) Set the Flash Control Register 2 FPROT bit to 1 to disable protection by lock bits, then use the Block Erase command (H'2020) or Erase All Unlock Blocks command (H'A7A7) to erase the memory block you want to unprotect. This is the only way to remove protection from a memory block. The lock bits cannot alone be set to 1. c) Lock bit status when reset The lock bits are nonvolatile bits, so that they are unaffected by resetting or powering off the microcomputer. (9) Command execution flow The diagrams below show command execution flow for each command used. Figure 6.5.8 Read Array Command INTERNAL MEMORY Write Read Array command (H'FFFF) to any internal flash memory address Read the desired internal flash memory address END

6-31 Rev.1.0 END Read any internal flash memory address to check for program error (Note 3) Last address? YES NO START Write data to the desired internal flash memory address (Note 1) Increment the previous write address by 2 and write the next data to the new address Write Page Program command (H’4141) to any internal flash memory address Data is written to the internal flash memory by page program (Note 2) Finished writing for one page? NO YES Wait for 1 µs (as counted by hardware or software timer) FSTAT bit = 1 TIME OUT ? 0.5s YES NO Forcibly terminated YES NO Go to the next page Note 1: Start writing from the beginning of the 256-byte boundary (lower address H'00). Note 2: After programming operation starts, the flash memory is automatically in the same condition as when the Read Status Register command is entered. (There is no need to issue the Read Status Register command until entering any other command.) Note 3: Inspect the Flash Status Register 2 (FSTAT2) ERASE (auto erase operating status), WRERR1 (program operating status 1), and WRERR2 (program operating status 2) bits to check for program errors. Figure 6.5.9 Page Program Command INTERNAL MEMORY

6-32 Rev.1.0 END Read any internal flash memory address to check for program error (Note 2) START Write Verify command (H’D0D0) to the last even address of the memory block to be protected Write Lock Bit Program command (H’7777) to any internal flash memory address Data is written to the lock bits by program (Note 1) Wait for 1 µs (as counted by hardware or software timer) FSTAT bit = 1 TIME OUT ? 0.5s YES NO Forcibly terminated YES NO Note 1: After programming operation starts, the flash memory is automatically in the same condition as when the Read Status Register command is entered. (There is no need to issue the Read Status Register command until entering any other command.) Note 2: Inspect the Flash Status Register 2 (FSTAT2) ERASE (auto erase operating status), WRERR1 (program operating status 1), and WRERR2 (program operating status 2) bits to check for program errors. Figure 6.5.10 Lock Bit Program Command INTERNAL MEMORY

6-33 Rev.1.0 END Read any internal flash memory address to check for program error (Note 2) START Write Verify command (H’D0D0) to the last even address of the memory block to be erased Write Block Erase command (H’2020) to any internal flash memory address Flash memory contents are erased by erase program (Note 1) Wait for 1 µs (as counted by hardware or software timer) FSTAT bit = 1 TIME OUT ? YES NO Forcibly terminated YES NO Note 1: After erase operation starts, the flash memory is automatically in the same condition as when the Read Status Register command is entered. (There is no need to issue the Read Status Register command until entering any other command.) Note 2: Inspect the Flash Status Register 2 (FSTAT2) ERASE (auto erase operating status), WRERR1 (program operating status 1), and WRERR2 (program operating status 2) bits to check for program errors. Figure 6.5.11 Block Erase Command INTERNAL MEMORY

6-34 Rev.1.0 END Read any internal flash memory address to check for program error (Note 2) START Write Verify command (H’D0D0) to any address of the memory blocks to be erased Write Erase All Unlock Blocks command (H’A7A7) to any internal flash memory address Flash memory contents are erased by erase program (Note 1) Wait for 1 µs (as counted by hardware or software timer) FSTAT bit = 1 TIME OUT ? 10s YES NO Forcibly terminated YES NO Note 1: After erase operation starts, the flash memory is automatically in the same condition as when the Read Status Register command is entered. (There is no need to issue the Read Status Register command until entering any other command.) Note 2: Inspect the Flash Status Register 2 (FSTAT2) ERASE (auto erase operating status), WRERR1 (program operating status 1), and WRERR2 (program operating status 2) bits to check for program errors. Figure 6.5.12 Erase All Unlock Blocks Command INTERNAL MEMORY

6-35 Rev.1.0 START Write Clear Status Register command (H'5050) to any internal flash memory address END START Write Read Status Register command (H'7070) to any internal flash memory address Read any internal flash memory address END Figure 6.5.13 Read Status Register Command Figure 6.5.14 Clear Status Register Command Figure 6.5.15 Read Lock Bit Status Register Command INTERNAL MEMORY Write Read Lock Bit Status Register command (H ’7171) to any internal flash memory address Read the last even address of the desired block END

6-36 Rev.1.0

6.5.4 Flash Programming Time (Reference Data)

The time required for programming the internal flash memory is described below for your reference. (1)M32172F2 and M32173F2 ➀ SIO transfer time (when transfer data size = 256 KB) 1/57600bpsx 1 (frame) x 11 (number of transfer bits) x 256 KB 50.1 [s] ➁ Flash programming time 256 KB/ 256-byte blocks x 8 ms 8.2 [s] ➂ Erase time (entire area) 50 ms x number of blocks 350 [ms] { Total flash programming time (entire 256 KB area)

• When communicating in UART mode at a rate of 57,600 bps, the flash programming time is extremely short as compared with the serial communication time and can, therefore, be ignored. In this case, the flash programming time can be calculated using the equation below ➀ + ➂ 50.5 [s]
• When writing data at high speed by increasing the serial communication rate or by other means, the fastest flash programming time possible is calculated using the equation below ➁ + ➂ 8.6 [s] INTERNAL MEMORY

6-37 Rev.1.0 Specifications of the boot ROM are shown below. Table 6.6.1 Specifications of the boot ROM Item Specification Capacity 8 Kbytes Location address H'8000 0000 - H'8000 1FFF Wait insertion Operates with no wait cycles (when internal CPU memory clock = 40 MHz) Internal bus connection Connects to a 32-bit bus Readout Can only be read out when FP = 1, MOD0 = 1, and MOD1 = 0. If read out in any other mode, the read value is indeterminate. Cannot be accessed for write. Other Because the boot ROM area is a reserved area that can only be used during boot mode, the program in it cannot be modified. INTERNAL MEMORY

6-38 Rev.1.0 The microcomputer can map 8-Kbyte blocks of internal RAM (up to two for the M32172F2 or up to three for the M32173F2) beginning with the start address into the internal flash memory area divided in units of 8-kbytes (L banks), and can map 4-Kbyte blocks of internal RAM (up to two for the M32173F2) beginning with address H'0080 A000 into the internal flash memory area divided in units of 4-kbyts (S banks). (The M32172F2 does not have the function for mapping into S banks of the internal flash memory.) This capability is referred to as the "virtual-flash emulation" function. This function allows the data located in 8-Kbyte or 4-Kbyte blocks of the internal RAM to be used by switching to the L or S banks of flash memory specified by the Virtual-Flash Bank Register. Therefore, applications that require changes of data during program operation can have data dynamically changed using 8 or 4 Kbytes of RAM area. The RAM used for virtual-flash emulation can be accessed for read and write from both the internal RAM and the internal flash memory areas. When this function is used in combination with the internal Realtime Debugger (RTD), the data tables created in the internal flash memory can be referenced or rewritten from the outside, allowing for each data table tuning from the outside. Before writing to the internal flash memory, always be sure to terminate this virtual-flash emulation mode. Figure 6.7.1 Configuration of the M32172F2's Internal RAM Banks INTERNAL MEMORY (FELBANK0)

8 Kbytes

H ’0080 4000 H ’0080 6000 RAM bank L block 1 (FELBANK1) H ’0080 7FFF Note: The M32172F2 does not have RAM bank S (4-Kbyte) blocks.

6-39 Rev.1.0 RAM bank L block 0 (FELBANK0) H ’0080 4000 H ’0080 6000 H ’0080 8000 H ’0080 A000 H ’0080 B000 RAM bank L block 1 (FELBANK1) (FELBANK2) (FESBANK0)

4 Kbytes

(FESBANK1)

4 KbytesH ’0080 BFFF

Figure 6.7.2 Configuration of the M32173F2's Internal RAM Banks INTERNAL MEMORY

6-40 Rev.1.0

6.7.1 Virtual-Flash Emulation Areas

The following shows the areas effective for the virtual-flash emulation function. Using the Virtual-Flash L Bank Registers, select 8-Kbyte blocks L banks of flash memory, one for each register (by setting the seven bits A12-A18 of start address of the desired L bank in the Virtual- Flash L Bank Register LBANKAD bits). Then set the Virtual-Flash L Bank Register MODENL bit to 1. The selected L bank areas can be replaced with 8-Kbyte blocks of the internal RAM beginning with its start address (up to two blocks for the M32172F2 or up to three blocks for the M32173F2). Furthermore, the M32173F2 has Virtual-Flash S Bank Registers (FESBANK0, FESBANK1). Using these registers, select 4-Kbyte blocks S banks of flash memory, one for each register (by setting the eight bits A12-A19 of start address of each desired S bank in the Virtual-Flash S Bank Register SBANKAD bits). Then set the Virtual-Flash S Bank Register MODENS0 and MODENS1 bits to 1. The selected S bank areas can be replaced with up to two 4-Kbyte blocks of the internal RAM beginning with the address H'0080 A000. In this way, the M32172F2 can have two 8-Kbyte L banks selected. For the M32173F2, three 8- Kbyte L banks and two 4-Kbyte S banks for a total of up to five banks can be selected. Note1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbyte) to be replaced with is selected by priority as follows:

• M32172F2 FELBANK0 > FELBANK1
• M32173F2 FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1 Note 2: During virtual-flash emulation mode, the RAM can be accessed for read and write from the internal RAM area and the area that has been set as a virtual-flash area. Note 3: When performing virtual-flash read after setting Flash Control Register 1’s Virtual- Flash Emulation Mode bit to 1, be sure to wait for three CPU clock periods or more before performing virtual-flash read after setting the said bit to 1. Note 4: When performing virtual-flash read after setting the Virtual-Flash Bank Register (LBank or S Bank Register)’s Virtual-Flash Emulation Enable bit and bank address bits, be sure to wait for three CPU clock periods or more before performing virtual-flash read after setting the Virtual-Flash Bank Register. INTERNAL MEMORY

6-41 Rev.1.0 H'0000 0000 H'0000 2000 <Internal flash> <Internal RAM> L bank 1 (8 Kbytes) H'0080 4000 L bank 0 (8 Kbytes) H'0000 4000 L bank 2 (8 Kbytes) (8 Kbytes) L bank 30 (8 Kbytes) H'0003 E000 H'0003 C000

8 Kbytes H'0080 6000

Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area to be replaced with is selected by priority: FELBANK0 > FELBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) selected by Virtual-Flash L Bank Register 0 or 1, what is actually accessed is the internal RAM area. During virtual-flash emulation mode, the RAM can be read and written to from both the internal RAM and the selected virtual-flash memory areas. Figure 6.7.3 Virtual-Flash Emulation Areas of the M32172F2 Divided in Units of 8 Kbytes Figure 6.7.4 Virtual-Flash Emulation Areas of the M32172F2 Divided in Units of 8 Kbytes INTERNAL MEMORY H'0000 0000 H'0000 2000 <Internal flash> L bank 1 (8 Kbytes) L bank 0 (8 Kbytes) H'0000 4000 L bank 2 (8 Kbytes) L bank 31 (8 Kbytes) L bank 30 (8 Kbytes) H'0003 E000 H'0003 C000 <Internal RAM> H'0080 4000 H'0080 6000 H'0080 8000 Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area to be replaced with is selected by priority: FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 8-Kbyte area (L bank) selected by Virtual-Flash L Bank Registers 0- 2, what is actually accessed is the internal RAM area. During virtual-flash emulation mode, the RAM can be read and written to from both the internal RAM and the selected virtual-flash memory areas.

6-42 Rev.1.0 H ’0000 0000 H ’0000 1000 <Internal flash> <Internal RAM> S bank 1 (4 Kbytes) H ’0080 4000 S bank 0 (4 Kbytes) H ’0000 2000 S bank 2 (4 Kbytes) (4 Kbytes) S bank 62 (4 Kbytes) H ’0003 F000 H ’0003 E000 H ’0080 A000 H ’0080 B000 Note 1: If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in two or more Virtual-Flash Bank Registers, the internal RAM area to be replaced with is selected by priority: FELBANK0 > FELBANK1 > FELBANK2 > FESBANK0 > FESBANK1. Note 2: When access is made to the 4-Kbyte area (S bank) selected by Virtual-Flash S Bank Register 0 or 1, what is actually accessed is the internal RAM area. During virtual-flash emulation mode, the RAM can be read and written to from both the internal RAM and the selected virtual-flash memory areas. Figure 6.7.5 Virtual-Flash Emulation Areas of the M32173F2 Divided in Units of 4 Kbytes INTERNAL MEMORY

6-43 Rev.1.0 H ’0000 0000 L bank Start address of flash memory bank Values set with L bank address (LBANKAD) bits L bank 0 L bank 1 L bank 2 L bank 30 L bank 31 H ’0000 2000 H ’0000 4000 H ’0003 C000 H ’0003 E000 H ’00 H ’02 H ’04 H ’3C H ’3E (Note) H ’0000 0000 L bank Start address of flash memory bank Values set with L bank address (LBAKNKAD) bits L bank 0 L bank 1 L bank 2 L bank 30 L bank 31 H ’0000 2000 H ’0000 4000 H ’0003 C000 H ’0003 E000 H ’00 H ’02 H ’04 H ’3C H ’3E (Note) Note: Set seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8-kbyte in the Virtual-Flash L Bank Register L bank address (LBANKAD) bits. Note: Set eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4-kbyte in the Virtual-Flash S Bank Register S bank address (SBANKAD) bits. Figure 6.7.6 Values Set in the M32172F2's Virtuar-Flash Bank Register when Divided in Units of 8-kbyte Figure 6.7.7 Values Set in the M32173F2's Virtual-Flash Bank Register when Divided in Units of 8-kbyte INTERNAL MEMORY

6-44 Rev.1.0 H ’0000 0000 S bank Start address of flash memory bank Values set with L bank address (SBAKNKAD) bits S bank 0 S bank 1 S bank 2 S bank 62 S bank 63 H ’0000 1000 H ’0000 2000 H ’0003 E000 H ’0003 F000 H ’00 H ’01 H ’02 H ’3E H ’3F (Note) Note: Set eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4-Kbyte in the Virtual-Flash S Bank Register S bank address (SBANKAD) bits. Figure 6.7.8 Values Set in the M32173F2's Virtual-Flash Bank Register when Divided in Units of 4-Kbyte INTERNAL MEMORY

6-45 Rev.1.0

6.7.2 Transition to Virtual-Flash Emulation Mode

To enter virtual-flash emulation mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit to 1. After entering virtual-flash emulation mode, set the Virtual-Flash Bank Register MODEN bit to 1 to enable the virtual-flash emulation function. Even during virtual-flash emulation mode, the internal RAM area (H'0080 4000 through H'0080 7FFF for the M32172F2 or H'0080 4000 through H'0080 BFFF for the M32173F2) can be accessed as internal RAM. Figure 6.7.9 Setup Sequence for Virtual-Flash Emulation Mode INTERNAL MEMORY Set RAM location address in virtual-flash bank register LBANKAD address A12-A18 SBANKAD address A12-A19 Write flash data to RAM Enable virtual-flash emulation MODENL 1 MODENS 1 End of setting Go to virtual-flash emulation mode FEMMOD 1 Setup start

6-46 Rev.1.0

6.7.3 Application Example for Virtual-Flash Emulation Mode

By locating two RAM areas in the same virtual-flash area using the Virtual-Flash Emulation Function, you can rewrite data in the flash memory successively. Figure 6.7.10 Usage Example for Virtual-Flash Emulation (1/2) INTERNAL MEMORY RAM block 0 Data write to RAM0 RAM block 1 (1) Operation when reset Replace Data write to RAM1 (2) Program operation with RAM block 0 RAM block 0 Flash Initial value Initial value RAM block 0 RAM block 1 Replace (3) Changing program operation from RAM block 0 to RAM block 1 RAM block 0 Flash Initial value RAM block 0 RAM block 1 RAM block 1Bank xx Bank xx Bank xx Specify bank xx Specify bank xx Specify bank xx (settings have no effect)

6-47 Rev.1.0 Replace (4) Program operation with RAM block 1 Flash Initial value RAM block 0 RAM block 1 RAM block 1Bank xx Specify bank xx Data write to RAM0 Replace (5) Changing program operation from RAM block 1 to RAM block 0 RAM block 0 Flash Initial value RAM block 0 RAM block 1 RAM block 1Bank xx Specify bank xx Specify bank xx (settings have no effect) (6) Go to item (2) Note: shows the effective area. Figure 6.7.11 Usage Example for Virtual-Flash Emulation (2/2) INTERNAL MEMORY

6-48 Rev.1.0 To rewrite the internal flash memory using a general-purpose serial programmer in boot mode + flash E/W enable mode, pins on the microcomputer listed below need to be processed to be suitable for use with the serial programmer. Table 6.8.1 Processing Pins when Using a Serial Programmer INTERNAL MEMORY Pin Name Pin No. Function Remark SCLKI1 71 Transfer clock input Pullup required RXD1 70 Serial data input Pullup required (received data) TXD1 69 Serial data output (transmit data) P84 68 Transmit/receive enable output Pullup required FP 94 Flash memory protect MOD0 92 Operation mode 0 MOD1 93 Operation mode 1 Connect to ground RESET 91 Reset XIN 4 Clock input XOUT 5 Clock output VCNT 7 PLL circuit control input OSC-VCC 6 PLL circuit power supply Connect to 3.3 V power supply OSC-VSS 3 PLL circuit ground Connect to ground VREF0 42 A-D converter reference voltage inputConnect to 5 V power supply AVCC0 43 Analog power supply Connect to 5 V power supply AVSS0 60 Analog ground Connect to ground FVCC 73 Flash memory power supply Connect to 3.3 V power supply VDD 108 RAM backup power supply Connect to 3.3 V power supply VCCE 20,65,95,132 5 V power supply VCCI 61,123,137 3.3 V power supply VSS 21,62,72,96,138 Ground Note: Any other pins do not need to be processed.

6-49 Rev.1.0 The diagram below shows a typical user system configuration with a serial programmer connected. After the user system is powered on, the serial programmer is used in clock-synchronized serial mode to write data to the flash memory. In this configuration, no oscillation frequency-dependent problems with communication may occur. If the pins connecting to the serial programmer are used by the system, measures must be taken to prevent any adverse effect on operation of the serial programmer. Note that addresses H'0000 0084 through H'0000 0093 are used as a flash memory protect ID check area by the serial programmer. Figure 6.8.1 Pin Connection Diagram for the 32172 INTERNAL MEMORY Connects to the 3.3 V power supply P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P84/SCLKI0/SCLKO0 ConnectorFlash programmer signals MOD0 FP RESET VSS Sets microcomputer operating conditions XIN XOUT VCNT AVSS0 OSC-VSS To the system circuit RxD (input) TxD (output) SCLKO (output) BUSY (input) MOD0 (output) FP (output) RESET (output) GND (output)

5 V (input)

about 2KΩ MOD1 Note 1: Turn on the power to the user system before writing to the flash memory. Note 2: When using P84-P87 in the system circuit, consideration must be taken for connection to the serial programmer. Note 3: Measures must be taken for P64/SBI not to generate interrupts by fixing it high or low. Note 4: Select the appropriate pullup resistance values for P84, P86, and P87 according to the system design conditions. Note 5: The typical pullup resistance values for P84, P86, and P87 are 4.7 to 10 kΩ . Note 6: The status of the ports not shown above do not affect writing to the flash memory.

6-50 Rev.1.0

6.9 Precautions on Rewriting Flash Memory

The following describes precautions to be observed when rewriting the internal flash memory using a serial programmer in boot mode + flash E/W enable mode.

• When you use the pins with the system that are used by a serial programmer, take measures not to affect the system when connecting a serial programmer.
• If the flash memory needs to be protected, set any ID in the flash memory protect ID check area (H'0000 0084-H'0000 0093).
• If the flash memory does not need to be protected, fill the flash memory protect ID check area (H'0000 0084-H'0000 0093) with data H'FF. INTERNAL MEMORY

7.1 Outline of Reset

7.2 Reset Operation

7.3 Internal State Immediately

7.4 Precautions to Be Taken

7-2 Rev.1.0 RESET The microcomputer is reset by applying a low-level signal to the RESET input pin. The_____ microcomputer is gotten out of a reset state by releasing the RESET input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the program starts executing from the reset vector entry.

7.2.1 Power-on Reset

When powering on the microcomputer, hold the input signal on the RESET pin low until the internal multiply-by-4 clock generator becomes oscillating stably.

7.2.2 Reset during Operation

To reset the microcomputer during operation, hold the RESET input low for more than four clock periods of XIN signal.

7.2.3 Reset Vector Movement during Flash Rewrite

When placed in boot mode, the microcomputer's reset vector entry address changes to the start address of the boot program space (address H'8000 0000). For details, refer to Section 6.5, "Programming the Internal Flash Memory."

7-3 Rev.1.0 RESET

7.3 Internal State Immediately after Reset

The table below shows the internal state of the microcomputer immediately after reset. For details about the initial state of internal peripheral I/O registers, refer to the relevant section of this manual where each internal peripheral I/O in interest is described. Table 7.3.1 Internal State Immediately after Reset Register State after reset PSW (CR0) B'0000 0000 0000 0000 ??00 000? 0000 0000 (BSM, BIE, BC bits = indeterminate) CBR (CR1) H'0000 0000 (C bit = 0) SPI (CR2) Indeterminate SPU (CR3) Indeterminate BPC (CR6) Indeterminate PC H'0000 0000 (Executed beginning with address H'0000 0000) (Note) ACC (Accumulator) Indeterminate Note: During boot mode, this is located at the start address of the boot program space (address H'8000 0000).

7-4 Rev.1.0 Table 7.3.2 Pin Status When Reset RESET Note: The state of JTAG pins cannot be initialized by a reset.When the low-level signal is applied to JTRST pin, the state of JTAG pins is initialized. Pin name Single chip mode External extended modeMicroprocessor mode Boot RESET, MOD0, Input Input Input Input MOD1, and FP Port P0, P1 Input Input Input Input P2, P3 Input Input Hi-Z Input P41 Input Input Hi-Z Input P42 P43 P45 P46 P47 Input Input Hi-Z Input P6, P7 Input Input Input Input P8, P12 Input Input Input Input P9, P13 P10, P15 P11, P17 P220, P221 P225 Input Input Hi-Z Input DA0, DA1 Input Input Input Input AD0IN0-7 Input Input Input Input AD1IN0-3 JTAG JTMS Input Input Input Input JTCK Input Input Input Input JTRST Input Input Input Input JTDO Indeterminate Indeterminate Indeterminate Indeterminate JTDI Input Input Input Input

7-5 Rev.1.0

7.4 Precautions to Be Taken Immediately after Reset

• Input/output ports After reset release, its input/output ports are disabled against input in order to prevent electric current from flowing through the pins. To use any ports in input mode, enable them for input using the Port Input Function Enable Register (PIEN)'s PIEN0 bit. For details, refer to Section 8.3, "Input/ Output Port Related Registers." RESET

7-6 Rev.1.0 RESET

8.1 Outline of Input/Output Ports

8.2 Selecting Pin Functions

8.3 Input/Output Port Related

8.4 Port Peripheral Circuits

8.5 Precautions on Using Input/

8-2 Rev.1.0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS The 32172/32173 has a total of 99 input/output ports connecting to external pins, comprised of P0- P13, P15, P17, and P22 (with P5 reserved for future use). These input/output ports can be used as input ports or output ports by setting up the direction registers. The input/output ports each are shared with other internal peripheral I/O or external extended bus signal lines, thus comprising dual-function or triple-function pins. The pin functions are selected depending on selected chip operation mode or by using the input/output port operation mode registers. (If any internal peripheral I/O has still another function, the register for that internal peripheral I/O needs to be set to select the desired pin function.) Each input port contains a port input function enable bit that may be used to prevent electric current from flowing into the input port. This helps to simplify hardware and software processing to be performed immediately after reset or when rewriting the flash memory. For any port to be used in input mode, a port input function enable bit for that port needs to be set. The input/output ports are outlined in the next page.

8-3 Rev.1.0 Table 8.1.1 Outline of the Input/Output Ports Item Specification Number of ports Total 99 bits (Note 1) P0 : P00-P07 (8 bits) P1 : P10-P17 (8 bits) P2 : P20-P27 (8 bits) P3 : P30-P37 (8 bits) P4 : P41-P47 (7 bits) P6 : P61-P64 (4 bits) P7 : P70-P77 (8 bits) P8 : P82-P87 (6 bits) P9 : P93-P97 (5 bits) P10 : P100-P107 (8 bits) P11 : P110-P117 (8 bits) P12 : P124-P127 (4 bits) P13 : P130-P137 (8 bits) P15 : P150, P153 (2 bits) P17 : P172-P175 (4 bits) P22 : P220, P221, P225, (3 bits) Port function Each port can be set for input or output mode by using the input/output port ___ direction control register. (However, P64 is a SBI input-only port; P97 is a CAN1 input-only port; P93, P124-P127, P130-P137, P172, and P173 are input-only ports; P221 is a CAN0 input-only port.) Pin function Dual functions with peripheral I/O or external extended signals (or multiple functions with two or more peripheral I/O functions) Pin function P0-P4(Note2), P225 : Depends on CPU operation mode (determined by setting selection MOD0 and MOD1 pins) P6(Note3)-P22 : Selected by setting input/output port operation mode registers. (However, peripheral I/O pin functions are selected using peripheral I/O registers.) Note 1: P14, P16, and P18-P21 are nonexistent. Note 2: Only when the CPU is operating in external extended mode, P0-P4 (except P46) have their pin functions switched by setting operation mode registers. (When the CPU is operating in single-chip or processor mode, the pin functions of these ports are switched depending on CPU operation mode.) Note 3: P16-P63 are always input/output ports (single function pins). INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-4 Rev.1.0 Each input/output port serves dual functions sharing the pin with other internal peripheral I/O or extended external bus signal lines (or triple functions sharing the pin with two or more functions of peripheral I/O). Pin functions are selected depending on the operation modes set or by using the input/output port operation mode registers. When the CPU is set to opreate in external extended or processor mode, P0-P4 and P225 all are switched to the signal pins needed for external access. The CPU operation mode is determined by setting the MOD0 and MOD1 pins. (See the table below.) Table 8.2.1 CPU Operation Modes and P0-P4 and P225 Pin Functions MOD0 MOD1 Operation Mode P0-P4 Pin Function (except P46)P46 and P225 Pin Function VSS (Note1)VSS Single-chip mode Input/output port pin Input/output port pin VSS VCC External extended mode External extended signal pin External extended signal pin or input/output port pin (Note 2) VCC VSS Processor mode External extended signal pin External extended signal pin VCC VCC Reserved (use inhibited) — — Note 1: VCC connects to +5 V, and VSS connects to GND. Note 2: Only when the CPU is operating in external extended mode, P0-P4 (except P46) have their pin functions switched by setting operation mode registers. Only when the PCU is operating in external extended mode, P0-P4 (except P46) have their pin functions switched between input/output port pins and internal peripheral I/O pins by setting up the input/output port operation mode registers. Ports P6-P13, P15, P17, and P22 (except P6-P64, P97, P221, P225) have their pin functions switched between input/output port and internal peripheral I/O pins by setting up the input/output port operation mode registers. If any internal peripheral I/O has multiple functions, select the desired pin function using the relevant internal peripheral I/O register. Operation on FP and MOD1 pins during write to the internal flash memory does not affect the pin functions. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-5 Rev.1.0 Figure 8.2.1 Input/Output Ports and Pin Function Assignments DB0 01 23 4567 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 A23 A24 A25 A26 A27 A28 A29 A30 A15 A16 A17 A18 A19 A20 A21 A22 A13 / CS3 A14RD CS0 CS1 (P61) (P62) (P63) RTDTXD RTDRXD RTDACK RTDCLKWAIT HREQ HACK / TXD3 TXD0 RXD0 SCLKI0 / SCLKO0 TXD1 RXD1 SCLKI1/ SCLKO1 RXD3 (/AD0IN8) TXD6 RXD6 (/AD1IN8) CTX1 CRX1 TO11 TO12 / SCLKI4 TO13 / SCLKO4 TO14 / TXD4 TO15 / RXD4TO10TO9TO8 TO3 TO4 / SCLKI5 TO5 / SCLKO5 TO6 / TXD5 TO7 / RXD5TO2TO1TO0 TIN0A (/AD0IN9) TIN0B (/AD1IN9) TIN1A (/AD0IN10) TIN1B (/AD1IN10) TIN17 / PWMOFF1 (/AD1IN11) TIN18 (/AD0IN12) TIN19 (/AD1IN12) TIN20 (/AD0IN13) TIN21 (/AD1IN13) TIN22 (/AD0IN14) TIN23 (/AD1IN14) TXD2 CTX0 A12 / CS2 (Note3) BCLK / WR BLW / BLE BHW / BHE CRX0 RXD2 TIN8 / TXD7 (/AD0IN15) TIN9 / RXD7 (/AD1IN15) SBI TIN11 (/AD1IN7) TIN10 (/AD1IN6) P10 P11 P12 P14 P15 Chip operation mode settings (Note1) (Reserved) P16 P17 P18 P19 P20 P21 P22 TIN16 / PWMOFF0 (/AD0IN11) P13 Input/output port operation mode register settings Input/output port operation mode register settings (Note2) Note 1: The pin function is selected depending on how the MOD0 and MOD1 pins are set. Note 2: Only when the CPU is operating in external extended mode, P0 - P4 (except P46) have their pin functions switched by setting operation mode registers. Note 3: The pin function is selected depending on how the MOD0 and MOD1 pins are set. Use of these pins requires caution because they have a debug event function. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-6 Rev.1.0

8.3 Input/Output Port Related Registers

The input/output port related registers consist of the Port Data Register, Port Direction Register, and Port Operation Mode Register. Ports P0-P4 and P225 have their pin functions determined depending on CPU operation mode (selected with the FP, MOD0, and MOD1 pins). Port P5 is reserved for future use. An input/output port related register map is shown below. Note: When the CPU is operating in single-chip or processor mode, the pin functions of these ports are switched depending on CPU operation mode. Figure 8.3.1 Input/Output Port Related Register Map (1/2) INPUT/OUTPUT PORTS AND PIN FUNCTIONS H'0080 0700 Address D0 D7 +0 Address +1 Address D8 D15 H'0080 0702 H'0080 0704 H'0080 0706 H'0080 0708 H'0080 070A H'0080 070C H'0080 070E P0 Data Register (P0DATA) P2 Data Register (P2DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P8 Data Register (P8DATA) P10 Data Register (P10DATA) P1 Data Register (P1DATA) P3 Data Register (P3DATA) P7 Data Register (P7DATA) P9 Data Register (P9DATA) P11 Data Register (P11DATA) P15 Data Register (P15DATA) H'0080 0720 H'0080 0722 H'0080 0724 H'0080 0726 H'0080 0728 H'0080 072A H'0080 072C H'0080 072E P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P8 Direction Register (P8DIR) P10 Direction Register (P10DIR) P1 Direction Register (P1DIR) P3 Direction Register (P3DIR) P7 Direction Register (P7DIR) P9 Direction Register (P9DIR) P11 Direction Register (P11DIR) P15 Direction Register (P15DIR) Blank areas are reserved for future use. P17 Data Register (P17DATA)H'0080 0710 H'0080 0730 P17 Direction Register (P17DIR) H'0080 0712 H'0080 0714 P22 Data Register (P22DATA)H'0080 0716 H'0080 0732 H'0080 0734 H'0080 0736 P22 Direction Register (P22DIR) P12 Data Register (P12DATA) P13 Data Register (P13DATA)

8-7 Rev.1.0 Figure 8.3.2 Input/Output Port Related Register Map (2/2) Address D0 D7 +0 Address +1 Address D8 D15 H ’0080 0746 H ’0080 0748 H ’0080 074A H ’0080 074C H ’0080 074E P8 Operation Mode Register (P8MOD) P10 Operation Mode Register (P10MOD) P12 Operation Mode Register (P12MOD) P7 Operation Mode Register (P7MOD) P9 Operation Mode Register (P9MOD) P11 Operation Mode Register (P11MOD) P13 Operation Mode Register (P13MOD) P15 Operation Mode Register (P15MOD) P17 Operation Mode Register (P17MOD)H ’0080 0750 H ’0080 0744 Port Input Function Enable Register (PIEN) H ’0080 0752 H ’0080 0754 P22 Operation Mode Register (P22MOD)H ’0080 0756 Blank areas are reserved for future use. Note: The registers enclosed in the thick frames must always be accessed in halfwords. H ’0080 0742 H ’0080 0740 P0 Operation Mode Register (P0MOD) P1 Operation Mode Register (P1MOD) P2 Operation Mode Register (P2MOD) P3 Operation Mode Register (P3MOD) P4 Operation Mode Register (P4MOD) H ’0080 0764 H ’0080 0766 H ’0080 0768 H ’0080 076A H ’0080 076C H ’0080 076E H ’0080 0770 H ’0080 0772 H ’0080 0774 H ’0080 0776 H ’0080 0778 P4 Peripheral Output Select Register (P4SMOD) P7 Peripheral Output Select Register (P7SMOD) P15 Peripheral Output Select Register (P15SMOD) P22 Peripheral Output Select Register (P22SMOD) P10-P11 Peripheral Output Select Register (P1011SMOD) INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-8 Rev.1.0 <When reset: indeterminate> D Bit Name Function R W

0 Pn0DT (Port Pn0 data) • When the direction bit is set to 0 (input

1 Pn1DT (Port Pn1 data) mode) by Port Direction Register

2 Pn2DT (Port Pn2 data) 0: Port input pin = low

3 Pn3DT (Port Pn3 data) 1: Port input pin = high

4 Pn4DT (Port Pn4 data) • When the direction bit is set to 1 (output

5 Pn5DT (Port Pn5 data) mode) by Port Direction Register

6 Pn6DT (Port Pn6 data) 0: Port output latch = low

7 Pn7DT (Port Pn7 data) 1: Port output latch = high

Note 1: The bits listed below have no functions assigned. (They show a 0 when read; writing to these bits has no effect.) P40, P60, P65-P67, P90-P92, P120-P123, P151, P152, P154-P157, P170, P171, P176, P177, P222-P224, P226, P227 Note 2: Port P64 is available for only input mode. Writing to the P64DT bit has no effect. Note 3: Ports P80 and P81 are available for only input mode. Writing to the P80DT and P81DT bits has no effect. When read, P80 and P81 show the MOD0 and MOD1 pin levels, respectively. Note 4: Ports P93, P97, P124-P127, P130-P137, P172, P173 and P221 are available for only input mode. Writing to the P93DT, P97DT, P124-127DT, P130-P137DT, P172DT, P173DT and P221DT bit has no effect.

8.3.1 Port Data Registers

I P0 Data Register (P0DATA) <Address : H'0080 0700> I P1 Data Register (P1DATA) <Address : H'0080 0701> I P2 Data Register (P2DATA) <Address : H'0080 0702> I P3 Data Register (P3DATA) <Address : H'0080 0703> I P4 Data Register (P4DATA) <Address : H'0080 0704> I P6 Data Register (P6DATA) <Address : H'0080 0706> I P7 Data Register (P7DATA) <Address : H'0080 0707> I P8 Data Register (P8DATA) <Address : H'0080 0708> I P9 Data Register (P9DATA) <Address : H'0080 0709> I P10 Data Register (P10DATA) <Address : H'0080 070A> I P11 Data Register (P11DATA) <Address : H'0080 070B> I P12 Data Register (P12DATA) <Address : H'0080 070C> I P13 Data Register (P13DATA) <Address : H'0080 070D> I P15 Data Register (P15DATA) <Address : H'0080 070F> I P17 Data Register (P17DATA) <Address : H'0080 0711> I P22 Data Register (P22DATA) <Address : H'0080 0716> ( D8 9 10 11 12 13 14 D15 ) Pn0DT Pn1DT Pn2DT Pn3DT Pn4DT Pn5DT Pn6DT Pn7DT Note: n = 0-4, 6-13, 15, 17, and 22 D 0 123456 D 7 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-9 Rev.1.0 <When reset: indeterminate> D Bit Name Function R W

0 Pn0DIR (Port Pn0 direction bit) 0: Input mode (when reset)

1 Pn1DIR (Port Pn1 direction bit) 1: Output mode

2 Pn2DIR (Port Pn2 direction bit)

3 Pn3DIR (Port Pn3 direction bit)

4 Pn4DIR (Port Pn4 direction bit)

5 Pn5DIR (Port Pn5 direction bit)

6 Pn6DIR (Port Pn6 direction bit)

7 Pn7DIR (Port Pn7 direction bit)

Note 1: The bits listed below have no functions assigned. (They show a 0 when read; writing to these bits has no effect.) P40, P60, P64-P67, P90-P92, P97, P120 -P123, P151, P152, P154-P157, P170, P171, P176, P177, P221-P224, P226, P227 Note 2: When reset, all ports are set for input mode. Note 3: Port P64 is available for only input mode. The P64DIR is nonexistent. Note 4: Ports P93, P97, P124-127, P130-P137, P172, P173 and P221 are available for only input mode. The P93DIR, P97DIR, P124-P127DIR, P130-P137DIR, P172DIR, P173DIR and P221DIR bits are nonexistent. Note 5: Ports P80 and P81 are available for only input mode. The P80DIR and P81DIR bits are nonexistent.

8.3.2 Port Direction Registers

I P0 Direction Register (P0DIR) <Address : H'0080 0720> I P1 Direction Register (P1DIR) <Address : H'0080 0721> I P2 Direction Register (P2DIR) <Address : H'0080 0722> I P3 Direction Register (P3DIR) <Address : H'0080 0723> I P4 Direction Register (P4DIR) <Address : H'0080 0724> I P6 Direction Register (P6DIR) <Address : H'0080 0726> I P7 Direction Register (P7DIR) <Address : H'0080 0727> I P8 Direction Register (P8DIR) <Address : H'0080 0728> I P9 Direction Register (P9DIR) <Address : H'0080 0729> I P10 Direction Register (P10DIR) <Address : H'0080 072A> I P11 Direction Register (P11DIR) <Address : H'0080 072B> I P15 Direction Register (P15DIR) <Address : H'0080 072F> I P17 Direction Register (P17DIR) <Address : H'0080 0731> I P22 Direction Register (P22DIR) <Address : H'0080 0736> ( D8 9 10 11 12 13 14 D15 ) Pn0DIR Pn1DIR Pn2DIR Pn3DIR Pn4DIR Pn5DIR Pn6DIR Pn7DIR Note: n = 0-4, 6-11, 15, 17, and 22 D 0 123456 D 7 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-10 Rev.1.0 D 0 123456 D 7 P00MOD P01MOD P02MOD P03MOD P04MOD P05MOD P06MOD P07MOD

8.3.3 Port Operation Mode Registers

I P0 Operation Mode Register (P0MOD) <Address: H'0080 0740> <When reset: H'00> D Bit Name Function R W

0 P00MOD 0: DB0

(Port P00 operation mode) 1: P00

1 P01MOD 0: DB1

(Port P01 operation mode) 1: P01

2 P02MOD 0: DB2

(Port P02 operation mode) 1: P02

3 P03MOD 0: DB3

(Port P03 operation mode) 1: P03

4 P04MOD 0: DB4

(Port P04 operation mode) 1: P04

5 P05MOD 0: DB5

(Port P05 operation mode) 1: P05

6 P06MOD 0: DB6

(Port P06 operation mode) 1: P06

7 P07MOD 0: DB7

(Port P07 operation mode) 1: P07 Note: The value set in the P0 Operation Mode Register takes effect only when the CPU operates in external extended mode INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-11 Rev.1.0 I P1 Operation Mode Register (P1MOD) <Address: H'0080 0741> <When reset: H'00> D Bit Name Function R W

8 P10MOD 0: DB8

(Port P10 operation mode) 1: P10

9 P11MOD 0: DB9

(Port P11 operation mode) 1: P11

10 P12MOD 0: DB10

(Port P12 operation mode) 1: P12

11 P13MOD 0: DB11

(Port P13 operation mode) 1: P13

12 P14MOD 0: DB12

(Port P14 operation mode) 1: P14

13 P15MOD 0: DB13

(Port P15 operation mode) 1: P15

14 P16MOD 0: DB14

(Port P16 operation mode) 1: P16

15 P17MOD 0: DB15

(Port P17 operation mode) 1: P17 Note: The value set in the P1 Operation Mode Register takes effect only when the CPU operates in external extended mode. INPUT/OUTPUT PORTS AND PIN FUNCTIONS D 8 9 1 01 11 21 31 4 D 1 5 P10MOD P11MOD P12MOD P13MOD P14MOD P15MOD P16MOD P17MOD

8-12 Rev.1.0 I P2 Operation Mode Register (P2MOD) <Address: H'0080 0742> <When reset: H'00> D Bit Name Function R W

0 P20MOD 0: A23

(Port P20 operation mode) 1: P20

1 P21MOD 0: A24

(Port P21 operation mode) 1: P21

2 P22MOD 0: A25

(Port P22 operation mode) 1: P22

3 P23MOD 0: A26

(Port P23 operation mode) 1: P23

4 P24MOD 0: A27

(Port P24 operation mode) 1: P24

5 P25MOD 0: A28

(Port P25 operation mode) 1: P25

6 P26MOD 0: A29

(Port P26 operation mode) 1: P26

7 P27MOD 0: A30

(Port P27 operation mode) 1: P27 Note: The value set in the P2 Operation Mode Register takes effect only when the CPU operates in external extended mode. INPUT/OUTPUT PORTS AND PIN FUNCTIONS P20MOD P21MOD P22MOD P23MOD P24MOD P25MOD P26MOD P27MOD

8-13 Rev.1.0 I P3 Operation Mode Register (P3MOD) <Address: H'0080 0743> D 8 9 1 01 11 21 31 4 D 1 5 P30MOD P31MOD P32MOD P33MOD P34MOD P35MOD P36MOD P37MOD <When reset: H'00> D Bit Name Function R W

8 P30MOD 0: A15

(Port P30 operation mode) 1: P30

9 P31MOD 0: A16

(Port P31 operation mode) 1: P31

10 P32MOD 0: A17

(Port P32 operation mode) 1: P32

11 P33MOD 0: A18

(Port P33 operation mode) 1: P33

12 P34MOD 0: A19

(Port P34 operation mode) 1: P34

13 P35MOD 0: A20

(Port P35 operation mode) 1: P35

14 P36MOD 0: A21

(Port P36 operation mode) 1: P36

15 P37MOD 0: A22

(Port P37 operation mode) 1: P37 Note: The value set in the P3 Operation Mode Register takes effect only when the CPU operates in external extended mode INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-14 Rev.1.0 I P4 Operation Mode Register (P4MOD) <Address: H'0080 0744> <When reset: H'00> D Bit Name Function R W

0 No functions assigned 0 –

1 P41MOD

0: BLW/BLE (Port P41 operation mode) 1: P41

2 P42MOD

0: BHW/BHE (Port P42 operation mode) 1: P42

3 P43MOD

0: RD (Port P43 operation mode) 1: P43

4 P44MOD

___ 0: CS0 (Port P44 operation mode) 1: P44

5 P45MOD

___ 0: CS1 (Port P45 operation mode) 1: P45

6 No functions assigned 0 –

7 P47MOD 0: A14

(Port P47 operation mode) 1: P47 Note: The value set in the P4 Operation Mode Register takes effect only when the CPU operates in external extended mode. INPUT/OUTPUT PORTS AND PIN FUNCTIONS P41MOD P42MOD P43MOD P44MOD P45MOD P47MOD

8-15 Rev.1.0 I P7 Operation Mode Register (P7MOD) <Address: H'0080 0747> <When reset: H'00> D Bit Name Function R W

8 P70MOD 0: P70

(Port P70 operation mode) ___ 1: BCLK/WR

9 P71MOD 0: P71

(Port P71 operation mode) ____ 1: WAIT

10 P72MOD 0: P72

(Port P72 operation mode) ____ 1: HREQ

11 P73MOD 0: P73

(Port P73 operation mode) ____ 1: HACK/TXD3

12 P74MOD 0: P74

(Port P74 operation mode) 1: RTDTXD

13 P75MOD 0: P75

(Port P75 operation mode) 1: RTDRXD

14 P76MOD 0: P76

(Port P76 operation mode) 1: RTDACK

15 P77MOD 0: P77

(Port P77 operation mode) 1: RTDCLK INPUT/OUTPUT PORTS AND PIN FUNCTIONS D 8 9 1 01 11 21 31 4 D 1 5 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD

8-16 Rev.1.0 I P8 Operation Mode Register (P8MOD) <Address: H'0080 0748> D 0 123456 D 7 P82MOD P83MOD P84MOD P85MOD P86MOD P87MOD <When reset: H'00> D Bit Name Function R W 0,1 No functions assigned 0 –

2 P82MOD 0: P82

(Port P82 operation mode) 1: TXD0

3 P83MOD 0: P83

(Port P83 operation mode) 1: RXD0

4 P84MOD 0: P84

(Port P84 operation mode) 1: SCLKI0/SCLKO0

5 P85MOD 0: P85

(Port P85 operation mode) 1: TXD1

6 P86MOD 0: P86

(Port P86 operation mode) 1: RXD1

7 P87MOD 0: P87

(Port P87 operation mode) 1: SCLKI1/SCLKO1 Note: Ports P80 and P81 are nonexistent. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-17 Rev.1.0 I P9 Operation Mode Register (P9MOD) <Address: H'0080 0749> D 8 9 1 01 11 21 31 4 D 1 5 P93MOD P94MOD P95MOD P96MOD <When reset: H'00> D Bit Name Function R W 8-10 No functions assigned 0 –

11 P93MOD 0: P93

(Port P93 operation mode) 1: RXD3

12 P94MOD 0: P94

(Port P94 operation mode) 1: TDX6

13 P95MOD 0: P95

(Port P95 operation mode) 1: RXD6

14 P96MOD 0: P96

(Port P96 operation mode) 1: CTX1 Note 1: Ports P90-P92 are nonexistent. Note 2: P97 is a CAN1 input-only pin. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-18 Rev.1.0 I P10 Operation Mode Register (P10MOD) <Address: H'0080 074A> D 0 123456 D 7 P100MOD P101MOD P102MOD P103MOD P104MOD P105MOD P106MOD P107MOD <When reset: H'00> D Bit Name Function R W

0 P100MOD 0: P100

(Port P100 operation mode) 1: TO8

1 P101MOD 0: P101

(Port P101 operation mode) 1: TO9

2 P102MOD 0: P102

(Port P102 operation mode) 1: TO10

3 P103MOD 0: P103

(Port P103 operation mode) 1: TO11

4 P104MOD 0: P104

(Port P104 operation mode) 1: TO12/SCLKI4

5 P105MOD 0: P105

(Port P105 operation mode) 1: TO13/SCLKO4

6 P106MOD 0: P106

(Port P106 operation mode) 1: TO14/TXD4

7 P107MOD 0: P107

(Port P107 operation mode) 1: TO15/RXD4 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-19 Rev.1.0 I P11 Operation Mode Register (P11MOD) <Address: H'0080 074B> D 8 9 1 01 11 21 31 4 D 1 5 P110MOD P111MOD P112MOD P113MOD P114MOD P115MOD P116MOD P117MOD <When reset: H'00> D Bit Name Function R W

8 P110MOD 0: P110

(Port P110 operation mode) 1: TO0

9 P111MOD 0: P111

(Port P111 operation mode) 1: TO1

10 P112MOD 0: P112

(Port P112 operation mode) 1: TO2

11 P113MOD 0: P113

(Port P113 operation mode) 1: TO3

12 P114MOD 0: P114

(Port P114 operation mode) 1: TO4/SCLKI5

13 P115MOD 0: P115

(Port P115 operation mode) 1: TO5/SCLKO5

14 P116MOD 0: P116

(Port P116 operation mode) 1: TO6/TXD5

15 P117MOD 0: P117

(Port P117 operation mode) 1: TO7/RXD5 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-20 Rev.1.0 I P12 Operation Mode Register (P12MOD) <Address: H'0080 074C> D 0 123456 D 7 P124MOD P125MOD P126MOD P127MOD <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 –

4 P124MOD 0: P124

(Port P124 operation mode) 1: TIN0A

5 P125MOD 0: P125

(Port P125 operation mode) 1: TIN0B

6 P126MOD 0: P126

(Port P126 operation mode) 1: TIN1A

7 P127MOD 0: P127

(Port P127 operation mode) 1: TIN1B Note : Ports P120-P123 are nonexistent. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-21 Rev.1.0 I P13 Operation Mode Register (P13MOD) <Address: H'0080 074D> D 8 9 1 01 11 21 31 4 D 1 5 P130MOD P131MOD P132MOD P133MOD P134MOD P135MOD P136MOD P137MOD <When reset: H'00> D Bit Name Function R W

8 P130MOD 0: P130

(Port P130 operation mode) 1: TIN16/PWMOFF0

9 P131MOD 0: P131

(Port P131 operation mode) 1: TIN17/PWMOFF1

10 P132MOD 0: P132

(Port P132 operation mode) 1: TIN18

11 P133MOD 0: P133

(Port P133 operation mode) 1: TIN19

12 P134MOD 0: P134

(Port P134 operation mode) 1: TIN20

13 P135MOD 0: P135

(Port P135 operation mode) 1: TIN21

14 P136MOD 0: P136

(Port P136 operation mode) 1: TIN22

15 P137MOD 0: P137

(Port P137 operation mode) 1: TIN23 Note: Ports P130-P137 are input-only pins. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-22 Rev.1.0 I P15 Operation Mode Register (P15MOD) <Address: H'0080 074F> D 8 9 1 01 11 21 31 4 D 1 5 P150MOD P153MOD <When reset: H'00> D Bit Name Function R W

8 P150MOD 0: P150

(Port P150 operation mode) 1: TIN8/TXD7 9,10 No functions assigned 0 –

11 P153MOD 0: P153

(Port P153 operation mode) 1: TIN9/TXD7 12-15 No functions assigned 0 – Note: Ports P151, P152, P154-P157 are nonexistent. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-23 Rev.1.0 I P17 Operation Mode Register (P17MOD) <Address: H'0080 0751> D 8 9 1 01 11 21 31 4 D 1 5 P172MOD P173MOD P174MOD P175MOD <When reset: H'00> D Bit Name Function R W 8,9 No functions assigned 0 –

10 P172MOD 0: P172

(Port P172 operation mode) 1: TIN10

11 P173MOD 0: P173

(Port P173 operation mode) 1: TIN11

12 P174MOD 0: P174

(Port P174 operation mode) 1: TXD2

13 P175MOD 0: P175

(Port P175 operation mode) 1: RXD2 14,15 No functions assigned 0 – Note: Ports P170-P171, P176, P177 are nonexistent. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-24 Rev.1.0 I P22 Operation Mode Register (P22MOD) <Address: H'0080 0756> D 0 123456 D 7 P220MOD P225MOD <When reset: H'00> D Bit Name Function R W

0 P220MOD 0: P220

(Port P220 operation mode) 1: CTX0 1-4 No functions assigned 0 –

5 P225MOD 0: P225

(Port P225 operation mode) 1: use inhibited 6-7 No functions assigned 0 – Note 1: P221 is a CAN0 input-only pin. Note 2: P225 has its pin function altered depending on how the MOD0 and MOD1 pins are set. Use of this port requires caution because it has a debug event function. Note 3: P222-P224, P226, and P227 are nonexistent. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-25 Rev.1.0 I P4 Peripheral Output Select Register (P4SMOD) <Address: H'0080 0764> D 0 123456 D 7 P46SMOD <When reset: H'00> D Bit Name Function R W 0-5 No functions assigned 0 –

6 P46SMOD 0:A13

(Selects port P46 peripheral output) 1:CS3

7 No functions assigned 0 –

INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-26 Rev.1.0 I P7 Peripheral Output Select Register (P7SMOD) <Address: H'0080 0767> D 8 9 1 01 11 21 31 4 D 1 5 P73SMOD <When reset: H'00> D Bit Name Function R W 8-10 No functions assigned 0 –

11 P73SMOD

0: HACK (Selects port P73 peripheral output) 1: TXD3 12-15 No functions assigned 0 – INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-27 Rev.1.0 D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 I P10-P11 Peripheral Output Select Register (P1011SMOD) <Address: H'0080 076A> <When reset: H'0000> D Bit Name Function R W 0-3 No functions assigned 0 –

4 P104SMOD 0: TO12

(Selects port P104 peripheral output) 1: SCLKI4

5 P105SMOD 0: TO13

(Selects port P105 peripheral output) 1: SCLKO4

6 P106SMOD 0: TO14

(Selects port P106 peripheral output) 1: TXD4

7 P107SMOD 0: TO15

(Selects port P107 peripheral output) 1: RXD4 8-11 No functions assigned 0 –

12 P114SMOD 0: TO4

(Selects port P114 peripheral output) 1: SCLKI5

13 P115SMOD 0: TO5

(Selects port P115 peripheral output) 1: SCLKO5

14 P116SMOD 0: TO6

(Selects port P116 peripheral output) 1: TXD5

15 P117SMOD 0: TO7

(Selects port P117 peripheral output) 1: RXD5 Note: This register must always be accessed in halfwords. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-28 Rev.1.0 I P15 Peripheral Output Select Register (P15SMOD) <Address: H'0080 076F> INPUT/OUTPUT PORTS AND PIN FUNCTIONS D 8 9 1 01 11 21 31 4 D 1 5 P150SMOD P153SMOD <When reset: H'00> D Bit Name Function R W

8 P150SMOD 0: TIN8

(Port P150 operation mode) 1: TXD7 9,10 No functions assigned

11 P153SMOD 0: TIN9

(Port P153 operation mode) 1: RXD7 12-15 No functions assigned 0 –

8-29 Rev.1.0 I P22 Peripheral Output Select Register (P22SMOD) <Address: H'0080 0776> D 0 123456 D 7 P225SMOD <When reset: H'00> D Bit Name Function R W 0-4 No functions assigned 0 –

5 P225SMOD 0: A12

(Selects port P225 peripheral output) ___ 1: CS2 6-7 No functions assigned 0 – Note: The value set in the P22 Peripheral Output Select Register takes effect only when the CPU operates in external extended mode. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-30 Rev.1.0 I Port Input Function Enable Register (PIEN) <Address: H'0080 0745> <When reset: H'00> D Bit Name Function R W 8-14 No functions assigned 0 –

15 PIEN0 0: Disables input (to prevent current

(Port input function enable bit) from flowing in) 1: Enables input This register is used to prevent electric current from flowing into the port input pin. Because the ports are disabled against input after reset, they need to be enabled for input by setting this register bit to 1. During boot mode, the pins shared with serial I/O function are enabled for input. Therefore, when rewriting the flash memory via serial communication, they can be protected against the current flowing in from pins other than the serial I/O function by setting this register bit to 0. The pins that can be controlled by the port input function enable bit in each mode are listed below. Table 8.3.1 Pins Controllable by Port Input Function Enable Bit Mode Name Controllable Pin Noncontrollable Pin P00-P07, P10-P17, P20-P27 P64, P93, P97 P30-P37, P41-P47, P61-P63 P124-P127 Single chip P70-P77, P82-P87, P94-P96 P130-P137, P221 P100-P107, P110-P117, FP, MOD0, MOD1, RESET P150, P153, P174, P175 P220, P225 P61-P63, P70-P77, P82-P87 P00-P07, P10-P17 External extended P94-P96, P100-P107, P110-P117 P20-P27, P30-P37 Microprocessor P150, P153, P174, P175, P220 P41-P47, P64, P93,P97 P124-P127, P130-P137 P221, P225, FP,MOD0,MOD1,RESET P00-P07, P10-P17, P20-P27 P64, P82-P87, P93,P97, P30-P37, P41-P47, P61-P63 P124-P127, P130-P137 Boot P67, P70-P77,P94-P96 P174, P175, P221, FP (Single chip) P100-P107, P110-P117, MOD0, MOD1, RESET P140-P147, P150-P157 P160-P167, P172-P173, P180-P187 P190-P197, P210-P217, P220 P222-P225 INPUT/OUTPUT PORTS AND PIN FUNCTIONS D 8 9 1 01 11 21 31 4 D 1 5 PIEN0

8-31 Rev.1.0 Figure 8.4.1 Port Peripheral Circuit Diagram (1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS P00 - P07(DB0 - DB7) P10 - P17(DB8 - DB15) P20 - P27(A23 - A30) P30 - P37(A15 - A22) P41(BLW/BLE) P42(BHW/BHE) P43(RD) P44(CS0) P45(CS1) P47(A14) Data bus (DB0 - DB15) Direction register Operation mode register Input function enable Port output latch P70(BCLK/WR) P76(RTDACK) P82(TXD0) P85(TXD1) P94(TXD6) , P96(CTX1) P174(TXD2) P220(CTX0) Operation mode register Direction register Port output latch Data bus (DB0 - DB15) Peripheral function output Input function enable Note 2: denotes a pin. Note 3: denotes a parasitic diode. Make sure the voltage applied to each port will not exceed VCCE. Note 1: Although P00-P07, P10-P17, P20-P27, P30-P37, and P41-P47 serve as external bus interface control signal pins during external extended and processor modes, their functional description in this block diagram is omitted. P74(RTDTXD)

8-32 Rev.1.0 Figure 8.4.2 Port Peripheral Circuit Diagram (2) P61 - P63 P225 P46 Data bus (DB0 - DB15) Port output latch Direction register Input function enable P64(SBI) Data bus (DB0 - DB15) SBI RD P71(WAIT) Operation mode register Direction register Port output latch Data bus (DB0 - DB15) WAIT Input function enable Note 2: denotes a pin. Note 3: denotes a parasitic diode. Make sure the voltage applied to each port will not exceed VCCE. Note 1: Although P46, P61-P63, and P225 serve as external bus interface control signal pins during external extended and processor modes, their functional description in this block diagram is omitted. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-33 Rev.1.0 Figure 8.4.3 Port Peripheral Circuit Diagram (3) P72(HREQ) Operation mode register Direction register Port output latch Data bus (DB0 - DB15) HREQ Input function enable P73(HACK /TXD3) P106(TO14 /TXD4) P116(TO6/TXD5) Data bus (DB0 - DB15) Direction register Operation mode register Input function enable Port output latch Peripheral function output selector Peripheral function output 1 Peripheral function output 2 P75(RTDRXD) P77(RTDCLK) P83(RXD0) P86(RXD1) P175(RXD2) Data bus (DB0 - DB15) Direction register Operation mode register Input function enable Port output latch Peripheral function input Note 1: denotes a pin. Note 2: denotes a parasitic diode. Make sure the voltage applied to each port will not exceed VCCE. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-34 Rev.1.0 Figure 8.4.4 Port Peripheral Circuit Diagram (4) P84(SCLKI0,SCLKO0) P87(SCLKI1,SCLKO1) Operation mode register Direction register Port output latch Data bus (DB0 - DB15) SCLKIi input UART/CSIO function select bit Internal/external clock select bit SCLKOi output RESET, XIN, JTRST Input function enable MOD0 MOD1 MOD0 , MOD1 FP FP JTDI ,JTCK, JTMS RESET XIN JTRST JTDI JTCK JTMS Note 1: denotes a pin. Note 2: denotes a parasitic diode. Make sure the voltage applied to each port will not exceed VCCE. JTDO JTDO OSC-VCC, VCCI, VDD, VCCE OSC-VCC VCCI VDD VCCE INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-35 Rev.1.0 Figure 8.4.5 Port Peripheral Circuit Diagram (5) Data bus (DB0 - DB15) Operation mode register Peripheral function input A-D input P93(RXD3(/AD0IN8)) P124(TIN0A(/AD0IN9)) P125(TIN0B(/AD1IN9)) P126(TIN1A(/AD0IN10)) P127(TIN1B(/AD1IN10)) P132(TIN18(/AD0IN12)) P133(TIN19(/AD1IN12)) P134(TIN20(/AD0IN13)) P135(TIN21(/AD1IN13)) P136(TIN22(/AD0IN14)) P137(TIN23(/AD1IN14)) P172(TIN10(/AD1IN9)) P173(TIN11(/AD1IN7)) P95(RXD5(/AD1IN8)) P150(TIN8(/TXD7 /AD0IN15)) Data bus (DB0 - DB15) Direction register Operation mode register Input function enable Port output latch Peripheral function output selector Peripheral function output Peripheral function input A-D input P97/CRX1 P221/CRX0 Data bus (DB0 - DB15) CRX0 , CRX1 RD Note 1: denotes a pin. Note 3: denotes a parasitic diode. Make sure the voltage applied to each port will not exceed VCCE. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-36 Rev.1.0 Figure 8.4.6 Port Peripheral Circuit Diagram (6) P100 - P103(TO8 - TO11) P110 - P113(TO0 - TO3) Data bus (DB0 - DB15) Direction register Operation mode register Input function enable Port output latch Peripheral function output PWM output disable P104(TO12 /SCLKI4) P114(TO4/SCLKI5) Data bus (DB0 - DB15) Direction register Operation mode register Input function enable Port output latch Peripheral function output selector Peripheral function output Peripheral function input PWM output disable Note 1: denotes a pin. Note 2: denotes a parasitic diode. Make sure the voltage applied to each port will not exceed VCCE. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-37 Rev.1.0 P105(TO13/SCLKO4) P115(TO5/SCLKO5) Data bus (DB0 - DB15) Direction register Operation mode register Input function enable Port output latch PWM output disable Peripheral function output selector Peripheral function output 1 Peripheral function output 2 P107(TO15/RXD4) P117(TO7/RXD5) Data bus (DB0 - DB15) Direction register Operation mode register Input function enable Port output latch Peripheral function output selector Peripheral function output Peripheral function input Note 1: denotes a pin. Note 2: denotes a parasitic diode. Make sure the voltage applied to each port will not exceed VCCE. Figure 8.4.7 Port Peripheral Circuit Diagram (7) INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-38 Rev.1.0 Figure 8.4.8 Port Peripheral Circuit Diagram (8) Data bus (DB0 - DB15) Direction register Operation mode register Input function enable Port output latch Peripheral function input 1 Peripheral function input 2 Peripheral function input 1 Peripheral function input 2 A-D input P153(TIN9/RXD7/AD1IN15) Operation mode register Input function enable A-D input P130(TIN16/PWMOFF0/AD0IN11) P131(TIN17/PWMOFF1/AD1IN11) Data bus (DB0 - DB15) Note 1: denotes a pin. Note 2: denotes a parasitic diode. Make sure the voltage applied to each port will not exceed VCCE. INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8-39 Rev.1.0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

8.5 Precautions on Input/Output Ports

• When using ports in output mode Immediately after reset, the Port Data Register values are indeterminate.Therefore, write the initial output value to the Port Data Register before setting the Port Direction Register for output. Note that if the Port Direction Register is set for output before writing to the Port Data Register, an indeterminate value may be output for a while until the write data is set in the Port Data Register.

8-40 Rev.1.0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS

9.1 Outline of DMAC

9.2 DMAC Related Registers

9.3 Functional Description of

9.4 Precautions on Using DMAC

9-2 Rev.1.0 The microcomputer has 10-channel DMA (Direct Memory Access) Controller allowing data to be transferred at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs when triggered in software or by request from internal peripheral I/O. Table 9.1.1 Outline of DMAC Item Content Number of channels 10 channels Transfer request • Software trigger

• Request from internal peripheral I/O: A-D converter, input/output timer, serial I/O (reception complete, transmit buffer empty), or PD controller
• Cascaded operation between DMA channels (Note) Maximum transfer count 256 times Transferable address space • 64 Kbytes (address space in H'0080 0000 through H'0080 FFFF)
• Supports transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs Transfer data size 16 or 8 bits Transfer method Single-transfer method DMA (control of internal bus released for each transfer performed), dual-address transfer Transfer mode Single transfer mode Direction of transfer Selectable among three modes for the source and destination
• Address fixed
• Address increment
• Ring buffer Channel priority Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 > (fixed priority) Maximum transfer rate 13.3 Mbytes per second (when internal peripheral clock = 20 MHz) Interrupt request Group interrupt request can be generated when any transfer count register underflows Transfer area 64 Kbytes in H'0080 0000 through H'0080 FFFF (transferable in the entire internal RAM and SFR area) DMAC

Note: The DMA channels can be cascaded in the manner shown below. Completion of one DMA transfer on channel 0 starts a DMA transfer on channel 1. Completion of one DMA transfer on channel 1 starts a DMA transfer on channel 2. Completion of one DMA transfer on channel 2 starts a DMA transfer on channel 0. Completion of one DMA transfer on channel 3 starts a DMA transfer on channel 4. Completion of one DMA transfer on channel 5 starts a DMA transfer on channel 6. Completion of one DMA transfer on channel 6 starts a DMA transfer on channel 7. Completion of one DMA transfer on channel 7 starts a DMA transfer on channel 5. Completion of one DMA transfer on channel 8 starts a DMA transfer on channel 9. Completion of one DMA transfer on channel 9 starts a DMA transfer on channel 1-9. Completion of all DMA transfers on channel 0 (i.e., the transfer count register underflows) starts a DMA transfer on channel 5. Completion of all DMA transfers on channel 1 (i.e., the transfer count register underflows) starts DMA transfers on channels 0-9. Completion of all DMA transfers on channel 3 (i.e., the transfer count register underflows) starts DMA transfers on channel 8.

9-3 Rev.1.0 Figure 9.1.1 DMA Block Diagram (1/2) DMA request selector A-D0 conversion completed DMA channel 0 Internal bus Software start One DMA2 transfer completed Timer (TOM00_udf) All DMA1 transfers completed Source address register Destination address register Transfer count registerudf Timer (TID0_udf,ovf) Timer (TID1_udf,ovf) Timer (TIN16 input signal) PD module (TIN0A input signal) Serial I/O-2(transmit buffer empty) Serial I/O-7(transmit buffer empty) DMA request selector DMA channel 1 Software start One DMA0 transfer completed Timer (TOM01_udf) All DMA1 transfers completed Source address register Destination address register Transfer count registerudf Timer (TID0_udf,ovf) Timer (TID1_udf,ovf) Timer (TIN16 input signal) Timer (TIN17 input signal) Timer (TOM02_udf) Serial I/O-4(reception completed) One DMA9 transfer completed PD module (PD_CMP0) PD module (PD_CMP1) DMA request selector DMA channel 2 Software start One DMA1 transfer completed PD module (TIN0B input signal) All DMA1 transfers completed Source address register Destination address register Transfer count registerudf Timer (TID0_udf,ovf) Timer (TID1_udf,ovf) Timer (TIN16 input signal) Timer (TIN18 input signal) Timer (TOM07_udf) Serial I/O-5(reception completed) One DMA9 transfer completed PD module (PD_CMP0) PD module (PD_CMP1) DMA request selector DMA channel 3 Software start Serial I/O-1(reception completed) All DMA1 transfers completed Source address register Destination address register Transfer count registerudf Timer (TID0_udf,ovf) Timer (TID1_udf,ovf) Timer (TIN16 input signal) Timer (TIN19 input signal) Timer (TOM03_udf) A-D1 conversion completed One DMA9 transfer completed PD module (PD_CMP0) PD module (PD_CMP1) Serial I/O-0(transmit buffer empty) DMA request selector DMA channel 4 Software start Serial I/O-0(reception completed) All DMA1 transfers completed Source address register Destination address register Transfer count registerudf Timer (TID0_udf,ovf) Timer (TID1_udf,ovf) Timer (TIN16 input signal) Timer (TIN23 input signal) Timer (TOM04_udf) Serial I/O-3(transmit buffer empty) One DMA9 transfer completed PD module (PD_CMP0) PD module (PD_CMP1) DMA start Judgment block Internal bus arbitration Interrupt request One DMA3 transfer completed DMAC

9-4 Rev.1.0 Figure 9.1.2 DMA Block Diagram (2/2) DMA request selector DMA channel 5 Internal bus Software start One DMA7 transfer completed Serial I/O-2(reception completed) Source address register Destination address register Transfer count registerudf DMA request selector DMA channel 6 Software start One DMA5 transfer completed All DMA1 transfers completed Source address register Destination address register Transfer count registerudf Timer (TID0_udf,ovf) Timer (TID1_udf,ovf) Timer (TIN16 input signal) Timer (TIN20 input signal) Timer (TOM05_udf) Serial I/O-6(reception completed) One DMA9 transfer completed PD module (PD_CMP0) PD module (PD_CMP1) DMA request selector DMA channel 7 Software start One DMA6 transfer completed All DMA1 transfers completed Source address register Destination address register Transfer count registerudf Timer (TID0_udf,ovf) Timer (TID1_udf,ovf) Timer (TIN16 input signal) PD module (TIN1B input signal) Timer (TOM06_udf) Serial I/O-5(transmit buffer empty) One DMA9 transfer completed PD module (PD_CMP0) PD module (PD_CMP1) DMA request selector DMA channel 8 Software start Serial I/O-3(reception completed) All DMA1 transfers completed Source address register Destination address register Transfer count registerudf Timer (TID0_udf,ovf) Timer (TID1_udf,ovf) Timer (TIN16 input signal) Timer (TIN21 input signal) Timer (TOM17_udf) Serial I/O-6(transmit buffer empty) One DMA9 transfer completed PD module (PD_CMP0) PD module (PD_CMP1) All DMA3 transfers completed DMA request selector DMA channel 9 Software start Serial I/O-7(reception completed) All DMA1 transfers completed Source address register Destination address register Transfer count registerudf Timer (TID0_udf,ovf) Timer (TID1_udf,ovf) Timer (TIN16 input signal) Timer (TIN22 input signal) Timer (TOM10_udf) Serial I/O-3(transmit buffer empty) One DMA9 transfer completed PD module (PD_CMP0) PD module (PD_CMP1) DMA start Judgment block Internal bus arbitration Interrupt request One DMA8 transfer completed All DMA0 transfers completed All DMA1 transfers completed Timer (TID0_udf,ovf) Timer (TID1_udf,ovf) Timer (TIN16 input signal) PD module (TIN1A input signal) Timer (TOM16_udf) Serial I/O-4(transmit buffer empty) One DMA9 transfer completed PD module (PD_CMP0) PD module (PD_CMP1) Serial I/O-1(transmit buffer empty) Serial I/O-2(transmit buffer empty) DMAC

9-5 Rev.1.0 A memory map of DMA related registers is shown below. Figure 9.2.1 DMA Related Register Map (1/2) H'0080 0400 H'0080 0414 H'0080 0416 H'0080 0418 H'0080 0410 H'0080 0412 DMA0 Channel Control Register (DM0CNT) Address D0 D7 +0 address +1 address D8 D15 DMA0 Transfer Count Register (DM0TCT) H'0080 0422 H'0080 0424 H'0080 0426 H'0080 0428 H'0080 042A H'0080 0420 DMA1 Channel Control Register (DM1CNT) DMA1 Transfer Count Register (DM1TCT) H'0080 0432 H'0080 0434 H'0080 0436 H'0080 0438 H'0080 043A H'0080 0430 DMA2 Channel Control Register (DM2CNT) DMA2 Transfer Count Register (DM2TCT) Note: The registers enclosed in the thick frames can only be accessed in halfwords. DMA0-4 Interrupt Request Status Register (DM04ITST) DMA0-4 Interrupt Mask Register (DM04ITMK) H'0080 0408 DMA5-9 Interrupt Request Status Register (DM59ITST) DMA5-9 Interrupt Mask Register (DM59ITMK) DMA5 Channel Control Register (DM5CNT) DMA5 Transfer Count Register (DM5TCT) DMA6 Channel Control Register (DM6CNT) DMA6 Transfer Count Register (DM6TCT) H'0080 042C H'0080 042E H'0080 043C H'0080 043E DMA7 Channel Control Register (DM7CNT) DMA7 Transfer Count Register (DM7TCT) H'0080 041A H'0080 041C H'0080 041E Blank areas are reserved for future use. DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) DMA0 Request Extended Cause Register (DM0REQ) DMA5 Request Extended Cause Register (DM5REQ) DMA1 Request Extended Cause Register (DM1REQ) DMA6 Request Extended Cause Register (DM6REQ) DMA2 Request Extended Cause Register (DM2REQ) DMA7 Request Extended Cause Register (DM7REQ) DMAC

9-6 Rev.1.0 H ’0080 0444 H ’0080 0446 H ’0080 0448 H ’0080 044A H ’0080 0442 DMA3 Channel Control Register (DM3CNT) Address D0 D7 +0 address +1 address D8 D15 DMA3 Transfer Count Register (DM3TCT) H ’0080 0452 H ’0080 0454 H ’0080 0456 H ’0080 0458 H ’0080 045A H ’0080 0450 DMA4 Channel Control Register (DM4CNT) DMA4 Transfer Count Register (DM4TCT) H ’0080 0462 H ’0080 0464 H ’0080 0466 H ’0080 0468 H ’0080 0460 H ’0080 0440 Note: The registers enclosed in the thick frames can only be accessed in halfwords. DMA8 Channel Control Register (DM8CNT) DMA8 Transfer Count Register (DM8TCT) H ’0080 044C H ’0080 044E DMA9 Channel Control Register (DM9CNT) DMA9 Transfer Count Register (DM9TCT) H ’0080 045C H ’0080 045E DMA7 Software Request Generation Register (DM7SRI) DMA8 Software Request Generation Register (DM8SRI) DMA9 Software Request Generation Register (DM9SRI) H ’0080 0470 H ’0080 0472 H ’0080 0474 H ’0080 0476 H ’0080 0478 Blank areas are reserved for future use. DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA1 Software Request Generation Register (DM1SRI) DMA0 Software Request Generation Register (DM0SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 Software Request Generation Register (DM4SRI) DMA5 Software Request Generation Register (DM5SRI) DMA6 Software Request Generation Register (DM6SRI) DMA3 Request Extended Cause Register (DM3REQ) DMA8 Request Extended Cause Register (DM8REQ) DMA4 Request Extended Cause Register (DM4REQ) DMA9 Request Extended Cause Register (DM9REQ) Figure 9.2.2 DMA Related Register Map (2/2) DMAC

9-7 Rev.1.0

9.2.1 DMA Channel Control Registers

I DMA0 Channel Control Register (DM0CNT) <Address: H'0080 0410> D 0 123456 D 7 MDSEL0 TREQF0 REQSL0 TENL0 TSZSL0 SADSL0 DADSL0 <When reset: H'00> D Bit Name Function R W

0 MDSEL0 0: Normal mode

(Selects DMA0 transfer mode) 1: Ring buffer mode

1 TREQF0 0: Not requested

(DMA0 transfer request flag) 1: Requested 2, 3 REQSL0 00: Software start or one DMA2 (Selects cause of DMA0 request) transfer completed 01: A-D0 conversion completed 10: Timer (TOM00_udf) 11: Extended request cause (Note)

4 TENL0 0: Disables transfer

(DMA0 transfer enable) 1: Enables transfer

5 TSZSL0 0: 16 bits

(Selects DMA0 transfer size) 1: 8 bits

6 SADSL0 0: Fixed

(Selects DMA0 source address direction)1: Increment

7 DADSL0 0: Fixed

(Selects DMA0 destination 1: Increment address direction) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. Note: When "Extended request cause" is selected, be sure to set the DMA0 Request Extended Cause Register (DM0REQ). DMAC

9-8 Rev.1.0 I DMA1 Channel Control Register (DM1CNT) <Address: H'0080 0420> <When reset: H'00> D Bit Name Function R W

0 MDSEL1 0: Normal mode

(Selects DMA1 transfer mode) 1: Ring buffer mode

1 TREQF1 0: Not requested

(DMA1 transfer request flag) 1: Requested 2, 3 REQSL1 00: Software start (Selects cause of DMA1 request)01: Extended request cause (Note) 10: Timer (TOM01_udf) 11: One DMA0 transfer completed

4 TENL1 0: Disables transfer

(DMA1 transfer enable) 1: Enables transfer

5 TSZSL1 0: 16 bits

(Selects DMA1 transfer size) 1: 8 bits

6 SADSL1 0: Fixed

(Selects DMA1 source address direction)1: Increment

7 DADSL1 0: Fixed

(Selects DMA1 destination 1: Increment address direction) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. Note: When "Extended request cause" is selected, be sure to set the DMA1 Request Extended Cause Register (DM1REQ). D 0 123456 D 7 MDSEL1 TREQF1 REQSL1 TENL1 TSZSL1 SADSL1 DADSL1 DMAC

9-9 Rev.1.0 I DMA2 Channel Control Register (DM2CNT) <Address: H'0080 0430> <When reset: H'00> D Bit Name Function R W

0 MDSEL2 0: Normal mode

(Selects DMA2 transfer mode) 1: Ring buffer mode

1 TREQF2 0: Not requested

(DMA2 transfer request flag) 1: Requested 2, 3 REQSL2 00: Software start (Selects cause of DMA2 request)01: Extended request cause (Note) 10: PD module (TIN0B input signal) 11: One DMA1 transfer completed

4 TENL2 0: Disables transfer

(DMA2 transfer enable) 1: Enables transfer

5 TSZSL2 0: 16 bits

(Selects DMA2 transfer size) 1: 8 bits

6 SADSL2 0: Fixed

(Selects DMA2 source address direction)1: Increment

7 DADSL2 0: Fixed

(Selects DMA2 destination 1: Increment address direction) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. Note: When "Extended request cause" is selected, be sure to set the DMA2 Request Extended Cause Register (DM2REQ). D 0 123456 D 7 MDSEL2 TREQF2 REQSL2 TENL2 TSZSL2 SADSL2 DADSL2 DMAC

9-10 Rev.1.0 I DMA3 Channel Control Register (DM3CNT) <Address: H'0080 0440> <When reset: H'00> D Bit Name Function R W

0 MDSEL3 0: Normal mode

(Selects DMA3 transfer mode) 1: Ring buffer mode

1 TREQF3 0: Not requested

(DMA3 transfer request flag) 1: Requested 2, 3 REQSL3 00: Software start (Selects cause of DMA3 request)01: Serial I/O-0 (transmit buffer empty) 10: Serial I/O-1 (reception completed) 11: Extended request cause (Note)

4 TENL3 0: Disables transfer

(DMA3 transfer enable) 1: Enables transfer

5 TSZSL3 0: 16 bits

(Selects DMA3 transfer size) 1: 8 bits

6 SADSL3 0: Fixed

(Selects DMA3 source address direction)1: Increment

7 DADSL3 0: Fixed

(Selects DMA3 destination 1: Increment address direction) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. Note: When "Extended request cause" is selected, be sure to set the DMA3 Request Extended Cause Register (DM3REQ). D 0 123456 D 7 MDSEL3 TREQF3 REQSL3 TENL3 TSZSL3 SADSL3 DADSL3 DMAC

9-11 Rev.1.0 I DMA4 Channel Control Register (DM4CNT) <Address: H'0080 0450> <When reset: H'00> D Bit Name Function R W

0 MDSEL4 0: Normal mode

(Selects DMA4 transfer mode) 1: Ring buffer mode

1 TREQF4 0: Not requested

(DMA4 transfer request flag) 1: Requested 2, 3 REQSL4 00: Software start (Selects cause of DMA4 request)01: One DMA3 transfer completed 10: Serial I/O-0 (reception completed) 11: Extended request cause (Note)

4 TENL4 0: Disables transfer

(DMA4 transfer enable) 1: Enables transfer

5 TSZSL4 0: 16 bits

(Selects DMA4 transfer size) 1: 8 bits

6 SADSL4 0: Fixed

(Selects DMA4 source address direction)1: Increment

7 DADSL4 0: Fixed

(Selects DMA4 destination 1: Increment address direction) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. Note: When "Extended request cause" is selected, be sure to set the DMA4 Request Extended Cause Register (DM4REQ). D 0 123456 D 7 MDSEL4 TREQF4 REQSL4 TENL4 TSZSL4 SADSL4 DADSL4 DMAC

9-12 Rev.1.0 I DMA5 Channel Control Register (DM5CNT) <Address: H'0080 0418> D 0 123456 D 7 MDSEL5 TREQF5 REQSL5 TENL5 TSZSL5 SADSL5 DADSL5 <When reset: H'00> D Bit Name Function R W

0 MDSEL5 0: Normal mode

(Selects DMA5 transfer mode) 1: Ring buffer mode

1 TREQF5 0: Not requested

(DMA5 transfer request flag) 1: Requested 2, 3 REQSL5 00: Software start or one DMA7 (Selects cause of DMA5 request) transfer completed 01: All DMA0 transfers completed 10: Serial I/O-2 (reception completed) 11: Extended request cause (Note)

4 TENL5 0: Disables transfer

(DMA5 transfer enable) 1: Enables transfer

5 TSZSL5 0: 16 bits

(Selects DMA5 transfer size) 1: 8 bits

6 SADSL5 0: Fixed

(Selects DMA5 source address direction)1: Increment

7 DADSL5 0: Fixed

(Selects DMA5 destination 1: Increment address direction) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. Note: When "Extended request cause" is selected, be sure to set the DMA5 Request Extended Cause Register (DM5REQ). DMAC

9-13 Rev.1.0 I DMA6 Channel Control Register (DM6CNT) <Address: H'0080 0428> <When reset: H'00> D Bit Name Function R W

0 MDSEL6 0: Normal mode

(Selects DMA6 transfer mode) 1: Ring buffer mode

1 TREQF6 0: Not requested

(DMA6 transfer request flag) 1: Requested 2, 3 REQSL6 00: Software start (Selects cause of DMA6 request)01: Serial I/O-1 (transmit buffer empty) 10: Extended request cause (Note) 11: One DMA5 transfer completed

4 TENL6 0: Disables transfer

(DMA6 transfer enable) 1: Enables transfer

5 TSZSL6 0: 16 bits

(Selects DMA6 transfer size) 1: 8 bits

6 SADSL6 0: Fixed

(Selects DMA6 source address direction)1: Increment

7 DADSL6 0: Fixed

(Selects DMA6 destination 1: Increment address direction) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. Note: When "Extended request cause" is selected, be sure to set the DMA6 Request Extended Cause Register (DM6REQ). D 0 123456 D 7 MDSEL6 TREQF6 REQSL6 TENL6 TSZSL6 SADSL6 DADSL6 DMAC

9-14 Rev.1.0 I DMA7 Channel Control Register (DM7CNT) <Address: H'0080 0438> <When reset: H'00> D Bit Name Function R W

0 MDSEL7 0: Normal mode

(Selects DMA7 transfer mode) 1: Ring buffer mode

1 TREQF7 0: Not requested

(DMA7 transfer request flag) 1: Requested 2, 3 REQSL7 00: Software start (Selects cause of DMA7 request)01: Serial I/O-2 (transmit buffer empty) 10: Extended request cause (Note) 11: One DMA6 transfer completed

4 TENL7 0: Disables transfer

(DMA7 transfer enable) 1: Enables transfer

5 TSZSL7 0: 16 bits

(Selects DMA7 transfer size) 1: 8 bits

6 SADSL7 0: Fixed

(Selects DMA7 source address direction)1: Increment

7 DADSL7 0: Fixed

(Selects DMA7 destination 1: Increment address direction) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. Note: When "Extended request cause" is selected, be sure to set the DMA7 Request Extended Cause Register (DM7REQ). D 0 123456 D 7 MDSEL7 TREQF7 REQSL7 TENL7 TSZSL7 SADSL7 DADSL7 DMAC

9-15 Rev.1.0 I DMA8 Channel Control Register (DM8CNT) <Address: H'0080 0448> <When reset: H'00> D Bit Name Function R W

0 MDSEL8 0: Normal mode

(Selects DMA8 transfer mode) 1: Ring buffer mode

1 TREQF8 0: Not requested

(DMA8 transfer request flag) 1: Requested 2, 3 REQSL8 00: Software start (Selects cause of DMA8 request)01: All DMA3 transfers completed 10: Serial I/O-3 (reception completed) 11: Extended request cause (Note)

4 TENL8 0: Disables transfer

(DMA8 transfer enable) 1: Enables transfer

5 TSZSL8 0: 16 bits

(Selects DMA8 transfer size) 1: 8 bits

6 SADSL8 0: Fixed

(Selects DMA8 source address direction)1: Increment

7 DADSL8 0: Fixed

(Selects DMA8 destination 1: Increment address direction) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. Note: When "Extended request cause" is selected, be sure to set the DMA8 Request Extended Cause Register (DM8REQ). D 0 123456 D 7 MDSEL8 TREQF8 REQSL8 TENL8 TSZSL8 SADSL8 DADSL8 DMAC

9-16 Rev.1.0 I DMA9 Channel Control Register (DM9CNT) <Address: H'0080 0458> <When reset: H'00> D Bit Name Function R W

0 MDSEL9 0: Normal mode

(Selects DMA9 transfer mode) 1: Ring buffer mode

1 TREQF9 0: Not requested

(DMA9 transfer request flag) 1: Requested 2, 3 REQSL9 00: Software start (Selects cause of DMA9 request)01: Serial I/O-3 (transmit buffer empty) 10: Extended request cause (Note) 11: One DMA8 transfer completed

4 TENL9 0: Disables transfer

(DMA9 transfer enable) 1: Enables transfer

5 TSZSL9 0: 16 bits

(Selects DMA9 transfer size) 1: 8 bits

6 SADSL9 0: Fixed

(Selects DMA9 source address direction)1: Increment

7 DADSL9 0: Fixed

(Selects DMA9 destination 1: Increment address direction) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. Note: When "Extended request cause" is selected, be sure to set the DMA9 Request Extended Cause Register (DM9REQ). D 0 123456 D 7 MDSEL9 TREQF9 REQSL9 TENL9 TSZSL9 SADSL9 DADSL9 DMAC

9-17 Rev.1.0 The DMA Channel Control Register consists of a bit to select DMA transfer mode for each channel, set DMA transfer request flag, and the bits to select the cause of DMA request, enable a DMA transfer, set the transfer size, and source/destination address directions. (1) MDSELn (DMAn transfer mode select) bit (D0) This bit when in single transfer mode selects normal or ring buffer mode. Setting this bit to 0 selects normal mode, and setting this bit to 1 selects ring buffer mode. In ring buffer mode, operation starts from the transfer start address and when transferred 32 times, returns to the transfer start address again, from which transfer operation restarts. In this case, the transfer count register operates in free-running mode, so that transfer operation is continued until the transfer enable bit is set to 0 (to disable transfer). No DMA transfer-finished interrupts are generated. (2) TREQFn (DMAn transfer request flag) bit (D1) This flag is set to 1 when a DAM transfer request occurs. Reading this flag helps to know whether there is a DMA transfer request on any channel. The DMA transfer request is cleared by writing 0 to this bit. Writing 1 has no effect, the bit retains the value it had before writing. Even when a new DMA transfer request occurs for a channel whose DMA transfer request flag is already set to 1, the next DMA transfer request is not accepted until after a transfer on the channel is completed. (3) REQSLn (cause of DMAn request select) bits (D2, D3) These bits select the cause of DMA request on each DMA channel. Note: If "Extended request cause" is selected for the cause of DMA request, always be sure to set the DMA Request Extended Cause Register to select a DMA request extended cause. (4) TENLn (DMAn transfer enable) bit (D4) Setting this bit to 1 enables transfer, making a DMA transfer ready to run. Setting this bit to 0 disables transfer. However, if a transfer request has already been accepted, transfer is not disabled until after the requested transfer is completed. (5) TSZSLn (DMAn transfer size select) bit (D5) This bit selects the number of data bits to be transferred in one DMA transfer operation (unit of one transfer). The unit of one transfer is 16 bits when this bit = 0, or 8 bits when this bit = 1. (6) SADSLn (DMAn source address direction select) bit (D6) This bit selects the direction in which the source address changes from two modes available: address fixed or address increment. (7) DADSLn (DMAn destination address direction select) bit (D7) This bit selects the direction in which the destination address changes from two modes available: address fixed or address increment. DMAC

9-18 Rev.1.0

9.2.2 DMA Request Extended Cause Register

I DMA0 Request Extended Cause Register (DM0REQ) <Address: H'0080 0416> D 0 123456 D 7 REQESEL0 <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 REQESEL0 0000: All DMA1 transfers completed (Selects DMA0 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN0A input signal 0101: Serial I/O-2 (transmit buffer empty) 0110: Serial I/O-7 (transmit buffer empty) 0111: No selection 1xxx: No selection Figure 9.2.3 Block Diagram of the DMA0 Request Extended Cause DMAC S DMA0 All DMA1 transfers completed TID0_udf,ovf TID1_udf,ovf TIN16 TIN0A SIO2-TXD SIO7-TXD DM0REQ REQESEL0 DM0CNT REQSL0 One DMA2 transfer completed A-D conversion completed TOM00_udf S <H ’0080 0416> Software start <H ’0080 0410>

9-19 Rev.1.0 I DMA1 Request Extended Cause Register (DM1REQ) <Address: H'0080 0426> D 0 123456 D 7 REQESEL1 <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 REQESEL1 0000: All DMA1 transfers completed (Selects DMA1 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN17 input signal 0101: TOM02_udf 0110: Serial I/O-4 (reception completed) 0111: One DMA9 transfer completed 1000: PD_CMP0 1001: PD_CMP1 101x: No selection 11xx: No selection Figure 9.2.4 Block Diagram of the DMA1 Request Extended Cause S DMA1 DM1REQ REQESEL1 DM1CNT REQSL1 S <H ’0080 0426> <H ’0080 0420>All DMA1 transfers completed TID0_udf,ovf TID1_udf,ovf TIN16 TIN17 One DMA9 transfer completed TOM02_udf SIO4_RXD PD_CMP0 PD_CMP1 Software start One DMA0 transfer completed TOM01_udf DMAC

9-20 Rev.1.0 I DMA2 Request Extended Cause Register (DM2REQ) <Address: H'0080 0436> D 0 123456 D 7 REQESEL2 <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 REQESEL2 0000: All DMA1 transfers completed (Selects DMA2 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN18 input signal 0101: TOM07_udf 0110: Serial I/O-5 (reception completed) 0111: One DMA9 transfer completed 1000: PD_CMP0 1001: PD_CMP1 101x: No selection 11xx: No selection Figure 9.2.5 Block Diagram of the DMA2 Request Extended Cause S DMA2 DM2REQ REQESEL2 DM2CNT REQSL2 S <H ’0080 0436> <H ’0080 0430> All DMA1 transfers completed TID0_udf,ovf TID1_udf,ovf TIN16 TIN18 TOM07_udf SIO5_RXD PD_CMP0 PD_CMP1 One DMA9 transfer completed Software start One DMA1 transfer completed TIN0B DMAC

9-21 Rev.1.0 I DMA3 Request Extended Cause Register (DM3REQ) <Address: H'0080 0446> D 0 123456 D 7 REQESEL3 <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 REQESEL3 0000: All DMA1 transfers completed (Selects DMA3 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN19 input signal 0101: TOM03_udf 0110: A-D1 conversion completed 0111: One DMA9 transfer completed 1000: PD_CMP0 1001: PD_CMP1 101x: No selection 11xx: No selection Figure 9.2.6 Block Diagram of the DMA3 Request Extended Cause S DMA3 DM3REQ REQESEL3 DM3CNT REQSL3 S <H ’0080 0446> <H ’0080 0440> All DMA1 transfers completed TID0_udf,ovf TID1_udf,ovf TIN16 TIN19 TOM03_udf A-D1 conversion completed PD_CMP0 PD_CMP1 One DMA9 transfer completed Software start SIO0-TXD SIO1-RXD DMAC

9-22 Rev.1.0 I DMA4 Request Extended Cause Register (DM4REQ) <Address: H'0080 0456> D 0 123456 D 7 REQESEL4 <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 REQESEL4 0000: All DMA1 transfers completed (Selects DMA4 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN23 input signal 0101: TOM04_udf 0110: Serial I/O-3 (transmit buffer empty) 0111: One DMA9 transfer completed 1000: PD_CMP0 1001: PD_CMP 101x: No selection 11xx: No selection S DMA4 DM4REQ REQESEL4 DM4CNT REQSL4 S <H ’0080 0456> <H ’0080 0450> All DMA1 transfers completed TID0_udf,ovf TID1_udf,ovf TIN16 TIN23 TOM04_udf SIO3-TXD PD_CMP0 PD_CMP1 One DMA9 transfer completed Software start One DMA3 transfer completed SIO0-RXD Figure 9.2.7 Block Diagram of the DMA4 Request Extended Cause DMAC

9-23 Rev.1.0 I DMA5 Request Extended Cause Register (DM5REQ) <Address: H'0080 041E> D 0 123456 D 7 REQESEL5 <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 REQESEL5 0000: All DMA1 transfers completed (Selects DMA5 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN1A input signal 0101: TOM16_udf 0110: Serial I/O-4 (transmit buffer empty) 0111: One DMA9 transfer completed 1000: PD_CMP0 1001: PD_CMP1 101x: No selection 11xx: No selection Figure 9.2.8 Block Diagram of the DMA5 Request Extended Cause S DMA5 DM5REQ REQESEL5 DM5CNT REQSL5 S <H ’0080 041E> <H ’0080 0418> All DMA1 transfers completed TID0_udf,ovf TID1_udf,ovf TIN16 TIN1A TOM16_udf SIO4-TXD PD_CMP0 PD_CMP1 One DMA9 transfers completed One DMA7 transfer completed All DMA0 transfer completed SIO2-RXD Software start DMAC

9-24 Rev.1.0 I DMA6 Request Extended Cause Register (DM6REQ) <Address: H'0080 042E> D 0 123456 D 7 REQESEL6 <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 REQESEL6 0000: All DMA1 transfers completed (Selects DMA6 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN20 input signal 0101: TOM05_udf 0110: Serial I/O-6 (reception completed) 0111: One DMA9 transfer completed 1000: PD_CMP0 1001: PD_CMP1 101x: No selection 11xx: No selection Figure 9.2.9 Block Diagram of the DMA6 Request Extended Cause S DMA6 DM6REQ REQESEL6 DM6CNT REQSL6 S <H ’0080 042E> <H ’0080 0428> All DMA1 transfer completed TID0_udf,ovf TID1_udf,ovf TIN16 TIN20 TOM05_udf SIO6-RXD PD_CMP0 PD_CMP1 One DMA9 transfer completed Software start One DMA5 transfer completed SIO1-TXD DMAC

9-25 Rev.1.0 I DMA7 Request Extended Cause Register (DM7REQ) <Address: H'0080 043E> D 0 123456 D 7 REQESEL7 <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 REQESEL7 0000: All DMA1 transfers completed (Selects DMA7 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN1B input signal 0101: TOM06_udf 0110: Serial I/O-5 (transmit buffer empty) 0111: One DMA9 transfer completed 1000: PD_CMP0 1001: PD_CMP1 101x: No selection 11xx: No selection Figure 9.2.10 Block Diagram of the DMA7 Request Extended Cause S DMA7 DM7REQ REQESEL7 DM7CNT REQSL7 S <H ’0080 043E> <H ’0080 0438> All DMA1 transfer completed TID0_udf,ovf TID1_udf,ovf TIN16 TIN1B TOM06_udf SIO5-TXD PD_CMP0 PD_CMP1 One DMA9 transfer completed Software start One DMA6 transfer completed SIO2-TXD DMAC

9-26 Rev.1.0 I DMA8 Request Extended Cause Register (DM8REQ) <Address: H'0080 044E> D 0 123456 D 7 REQESEL8 <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 REQESEL8 0000: All DMA1 transfers completed (Selects DMA8 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN21 input signal 0101: TOM17_udf 0110: Serial I/O-6 (transmit buffer empty) 0111: One DMA9 transfer completed 1000: PD_CMP0 1001: PD_CMP1 101x: No selection 11xx: No selection Figure 9.2.11 Block Diagram of the DMA8 Request Extended Cause S DMA8 DM8REQ REQESEL8 DM8CNT REQSL8 S <H ’0080 044E> <H ’0080 0448> All DMA1 transfer completed TID0_udf,ovf TID1_udf,ovf TIN16 TIN21 TOM17_udf SIO6-TXD PD_CMP0 PD_CMP1 One DMA9 transfer completed Software start All DMA3 transfer completed SIO3-RXD DMAC

9-27 Rev.1.0 I DMA9 Request Extended Cause Register (DM9REQ) <Address: H'0080 045E> D 0 123456 D 7 REQESEL9 <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 REQESEL9 0000: All DMA1 transfers completed (Selects DMA9 request 0001: TID0_udf,ovf extended cause) 0010: TID1_udf,ovf 0011: TIN16 input signal 0100: TIN22 input signal 0101: TOM10_udf 0110: Serial I/O-7 (reception completed) 0111: One DMA9 transfer completed 1000: PD_CMP0 1001: PD_CMP1 101x: No selection 11xx: No selection Figure 9.2.12 Block Diagram of the DMA9 Request Extended Cause S DMA9 DM9REQ REQESEL9 DM9CNT REQSL9 S <H ’0080 045E> <H ’0080 0458> All DMA1 transfer completed TID0_udf,ovf TID1_udf,ovf TIN16 TIN22 TOM10_udf SIO7-RXD PD_CMP0 PD_CMP1 One DMA9 transfer completed Software start One DMA8 transfer completed SIO3-TXD DMAC

9-28 Rev.1.0 The DMA Request Extended Source Register is used to select a DMA transfer request extended source when "Extended request source" has been selected with the DMA Channel Control Register's cause of DMA request select (REQSLn) bits. (1) REQESELn (DMAn request extended source select) bits (D4-D7) These bits select a DMA transfer request extended source for each DMA channel. Note : The DMA transfer request extended source selected with the REQESELn (DMAn request extended source select) bits is effective only when "Extended request source" has been selected with the DMA Channel Control Register's cause of DMA request select (REQSLn) bits. Figure 9.2.13 Block Diagram of the DMAn Request Extended Source DMAC S DMAn DMnREQ DMnCNT S DMAn request extended source DMAn request source

9-29 Rev.1.0

9.2.3 DMA Software Request Generation Registers

I DMA0 Software Request Generation Registers (DM0SRI) <Address: H'0080 0460> I DMA1 Software Request Generation Registers (DM1SRI) <Address: H'0080 0462> I DMA2 Software Request Generation Registers (DM2SRI) <Address: H'0080 0464> I DMA3 Software Request Generation Registers (DM3SRI) <Address: H'0080 0466> I DMA4 Software Request Generation Registers (DM4SRI) <Address: H'0080 0468> I DMA5 Software Request Generation Registers (DM5SRI) <Address: H'0080 0470> I DMA6 Software Request Generation Registers (DM6SRI) <Address: H'0080 0472> I DMA7 Software Request Generation Registers (DM7SRI) <Address: H'0080 0474> I DMA8 Software Request Generation Registers (DM8SRI) <Address: H'0080 0476> I DMA9 Software Request Generation Registers (DM9SRI) <Address: H'0080 0478> <When reset: indeterminate> D Bit Name Function R W 0-15 DM0SRI-DM9SRI A DMA transfer request is generated ? (Generates DMA software request) by writing any data to this register. Note: This register can be accessed in either bytes or halfwords. The DMA Software Request Generation Register is used to generate a DMA transfer request in software. A DMA transfer request is generated by writing any data to this register while "Software start" has been selected for the DMA request source. DM0SRI-DM9SRI (DMA software request generation) bits A software DMA transfer request is generated by writing any data-halfword (16 bits) or a byte (8 bits) starting from an even or odd address-to this register while "Software start" has been selected for the cause of DMA source (by setting the DMA Channel Control Register D2, D3 bits to '00'). DMAC D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 DM0SRI-DM9SRI

9-30 Rev.1.0

9.2.4 DMA Source Address Registers

I DMA0 Source Address Registers (DM0SA) <Address: H'0080 0412> I DMA1 Source Address Registers (DM1SA) <Address: H'0080 0422> I DMA2 Source Address Registers (DM2SA) <Address: H'0080 0432> I DMA3 Source Address Registers (DM3SA) <Address: H'0080 0442> I DMA4 Source Address Registers (DM4SA) <Address: H'0080 0452> I DMA5 Source Address Registers (DM5SA) <Address: H'0080 041A> I DMA6 Source Address Registers (DM6SA) <Address: H'0080 042A> I DMA7 Source Address Registers (DM7SA) <Address: H'0080 043A> I DMA8 Source Address Registers (DM8SA) <Address: H'0080 044A> I DMA9 Source Address Registers (DM9SA) <Address: H'0080 045A> <When reset: indeterminate> D Bit Name Function R W 0-15 DM0SA-DM9SA Source address A16-A31 (DMA source address) (A0-A15 are fixed to H'0080) Note: This register must always be accessed in halfwords. In the DMA Source Address Register, set the source address of DMA transfer in such a way that D0 is for A16, and D15 is for A31. Because this register is comprised of a current register, its read value is always the current value. When a DMA transfer is finished (at which the transfer count register underflows), the source address remains unchanged or changes depending on the selected transfer address direction. If "Address fixed" is selected, the source address remains the same as the set value before the DMA transfer started; if "Address increment" is selected, the source address is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Source Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If this register is accessed in bytes, its value becomes indeterminate. DM0SA-DM9SA (source address A16-A31) Set this register to specify the source address of DMA transfer in the internal I/O or RAM space from address H'0080 0000 to H'0080 FFFF. The 16 high-order bits of the source address (A0 - A15) are always fixed to H'0080. Use this register to set the 16 low-order bits of the source address. (D0 corresponds to the source address A16, and D15 corresponds to the source address A31.) DMAC D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 DM0SA-DM9SA

9-31 Rev.1.0

9.2.5 DMA Destination Address Registers

I DMA0 Destination Address Registers (DM0DA) <Address: H'0080 0414> I DMA1 Destination Address Registers (DM1DA) <Address: H'0080 0424> I DMA2 Destination Address Registers (DM2DA) <Address: H'0080 0434> I DMA3 Destination Address Registers (DM3DA) <Address: H'0080 0444> I DMA4 Destination Address Registers (DM4DA) <Address: H'0080 0454> I DMA5 Destination Address Registers (DM5DA) <Address: H'0080 041C> I DMA6 Destination Address Registers (DM6DA) <Address: H'0080 042C> I DMA7 Destination Address Registers (DM7DA) <Address: H'0080 043C> I DMA8 Destination Address Registers (DM8DA) <Address: H'0080 044C> I DMA9 Destination Address Registers (DM9DA) <Address: H'0080 045C> <When reset: indeterminate> D Bit Name Function R W 0-15 DM0DA-DM9DA Destination address A16-A31 (DMA destination address) (A0-A15 are fixed to H'0080) Note: This register must always be accessed in halfwords. In the DMA Destination Address Register, set the destination address of DMA transfer in such a way that D0 is for A16, and D15 is for A31. Because access to this register is comprised of a current register, its read value is always the current value. When a DMA transfer is finished (at which the transfer count register underflows), the destination address remains unchanged or changes depending on the selected transfer address direction. If "Address fixed" is selected, the destination address remains the same as the set value before the DMA transfer started; if "Address increment" is selected, the destination address is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Destination Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If this register is accessed in bytes, its value becomes indeterminate. DM0DA-DM9DA (destination address A16-A31) Set this register to specify the destination address of DMA transfer in the internal I/O or RAM space from address H'0080 0000 to H'0080 FFFF. The 16 high-order bits of the destination address (A0 - A15) are always fixed to H'0080. Use this register to set the 16 low-order bits of the destination address. (D0 corresponds to the destination address A16, and D15 corresponds to the destination address A31.) DMAC D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 DM0DA-DM9DA

9-32 Rev.1.0

9.2.6 DMA Transfer Count Registers

I DMA0 Transfer Count Registers (DM0TCT) <Address: H'0080 0411> I DMA1 Transfer Count Registers (DM1TCT) <Address: H'0080 0421> I DMA2 Transfer Count Registers (DM2TCT) <Address: H'0080 0431> I DMA3 Transfer Count Registers (DM3TCT) <Address: H'0080 0441> I DMA4 Transfer Count Registers (DM4TCT) <Address: H'0080 0451> I DMA5 Transfer Count Registers (DM5TCT) <Address: H'0080 0419> I DMA6 Transfer Count Registers (DM6TCT) <Address: H'0080 0429> I DMA7 Transfer Count Registers (DM7TCT) <Address: H'0080 0439> I DMA8 Transfer Count Registers (DM8TCT) <Address: H'0080 0449> I DMA9 Transfer Count Registers (DM9TCT) <Address: H'0080 0459> <When reset: indeterminate> D Bit Name Function R W 8-15 DM0TCT-DM9TCT Number of times a DMA transfer is performed (DMA transfer count) (Ignored during 32-channel ring buffer mode) The DMA Transfer Count Register is used to set the number of times data is transferred in each channel. However, the value in this register is ignored during ring buffer mode. The transfer count is the (value set in the transfer count register + 1). Because the DMA Transfer Count Register is comprised of a current register, the value you get by reading this register is always the current value. (However, if you read this register in a cycle immediately after a transfer, the value you get is the value that was in the count register before the transfer began.) When transfer finishes, this count register underflows, so that the read value you get is H'FF. If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed, or when all transfers are completed (at which the transfer count register underflows), transfer in the cascaded channel starts. DMAC D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 DM0TCT-DM9TCT

9-33 Rev.1.0

9.2.7 DMA Interrupt Request Status Registers

I DMA0-4 Interrupt Request Status Register (DM04ITST) <Address: H'0080 0400> D 0 123456 D 7 DMITST4 DMITST3 DMITST2 DMITST1 DMITST0 <When reset: H'00> D Bit Name Function R W 0-2 No functions assigned 0 –

3 DMITST4 0: No interrupt requested

(DMA4 interrupt request status) 1: Interrupt requested

4 DMITST3

(DMA3 interrupt request status)

5 DMITST2

(DMA2 interrupt request status)

6 DMITST1

(DMA1 interrupt request status)

7 DMITST0

(DMA0 interrupt request status) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. The DMA0-4 Interrupt Request Status Register helps to know the status of interrupt requests on DMA channels 0-4. If the DMAn interrupt request status bit (n = 0-4) is set to 1, it means that the channel has a DMA interrupt request generated. DMITSTn (DMAn interrupt request status) bit (n = 0-4) The DMAn interrupt request status bit is set in hardware, and cannot be set in software. The DMAn interrupt request status bit is cleared by writing 0 in software. Note: The DMAn interrupt request status bit is not cleared by writing 0 to the DMA Interrupt Control Register "interrupt request bit" of the Interrupt Controller. When writing to the DMA0-4 Interrupt Request Status Register, be sure to write 0 for the bits to be cleared and 1 for all other bits. Writing 1 in software does not affect any bit of this register, the bit retains the value it had before writing. DMAC

9-34 Rev.1.0 I DMA5-9 Interrupt Request Status Register (DM59ITST) <Address: H'0080 0408> D 0 123456 D 7 DMITST9 DMITST8 DMITST7 DMITST6 DMITST5 <When reset: H'00> D Bit Name Function R W 0-2 No functions assigned 0 –

3 DMITST9 0: No interrupt requested

(DMA9 interrupt request status) 1: Interrupt requested

4 DMITST8

(DMA8 interrupt request status)

5 DMITST7

(DMA7 interrupt request status)

6 DMITST6

(DMA6 interrupt request status)

7 DMITST5

(DMA5 interrupt request status) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. The DMA5-9 Interrupt Request Status Register helps to know the status of interrupt requests on DMA channels 5-9. If the DMAn interrupt request status bit (n = 5-9) is set to 1, it means that the channel has a DMA interrupt request generated. DMITSTn (DMAn interrupt request status) bit (n = 5-9) The DMAn interrupt request status bit is set in hardware, and cannot be set in software. The DMAn interrupt request status bit is cleared by writing 0 in software. Note: The DMAn interrupt request status bit is not cleared by writing 0 to the DMA Interrupt Control Register "interrupt request bit" of the Interrupt Controller. When writing to the DMA5-9 Interrupt Request Status Register, be sure to write 0 for the bits to be cleared and 1 for all other bits. Writing 1 in software does not affect any bit of this register, the bit retains the value it had before writing. DMAC

9-35 Rev.1.0

9.2.8 DMA Interrupt Mask Registers

I DMA0-4 Interrupt Mask Register (DM04ITMK) <Address: H'0080 0401> D 8 9 1 01 11 21 31 4 D 1 5 DMITMK4 DMITMK3 DMITMK2 DMITMK1 DMITMK0 <When reset: H'00> D Bit Name Function R W 8-10 No functions assigned 0 –

11 DMITMK4 0: Enables interrupt request

(DMA4 interrupt request mask) 1: Masks (disables) interrupt request

12 DMITMK3

(DMA3 interrupt request mask)

13 DMITMK2

(DMA2 interrupt request mask)

14 DMITMK1

(DMA1 interrupt request mask)

15 DMITMK0

(DMA0 interrupt request mask) The DMA0-4 Interrupt Mask Register masks interrupt requests on DMA channels 0-4. DMITMKn (DMAn interrupt request mask) bits (n = 0-4) Setting the DMAn interrupt request mask bit to 1 masks a DMAn interrupt request. However, whenever an interrupt request occurs, the DMAn interrupt request status bit is set to 1 no matter how this register is set. DMAC

9-36 Rev.1.0 I DMA5-9 Interrupt Mask Register (DM59ITMK) <Address: H'0080 0409> D 8 9 1 01 11 21 31 4 D 1 5 DMITMK9 DMITMK8 DMITMK7 DMITMK6 DMITMK5 <When reset: H'00> D Bit Name Function R W 8-10 No functions assigned 0 –

11 DMITMK9 0: Enables interrupt request

(DMA9 interrupt request mask) 1: Masks (disables) interrupt request

12 DMITMK8

(DMA8 interrupt request mask)

13 DMITMK7

(DMA7 interrupt request mask)

14 DMITMK6

(DMA6 interrupt request mask)

15 DMITMK5

(DMA5 interrupt request mask) The DMA5-9 Interrupt Mask Register masks interrupt requests on DMA channels 5-9. DMITMKn (DMAn interrupt request mask) bits (n = 5-9) Setting the DMAn interrupt request mask bit to 1 masks a DMAn interrupt request. However, whenever an interrupt request occurs, the DMAn interrupt request status bit is set to 1 no matter how this register is set. DMAC

9-37 Rev.1.0 DMA transfer interrupt 0 Data bus DMITST4 F/F DMITMK4 F/Fb11 DMITST3 F/F DMITMK3 F/Fb12 b5 DMITST2 F/F DMITMK2 F/Fb13 DMITMK1 F/F F/Fb14 b7 DMITST0 F/F DMITMK0 F/Fb15 (Level) 5-source inputs DM04ITST <H'0080 0400> DM04ITMK <H'0080 0401> DMA4UDF DMA1UDF DMA0UDF DMA3UDF DMA2UDF DMITST1 Figure 9.2.14 Block Diagram of DMA Transfer Interrupt 0 DMAC

9-38 Rev.1.0 Figure 9.2.15 Block Diagram of DMA Transfer Interrupt 1 DMA transfer interrupt 1 Data bus DMITST9 F/F DMITMK9 F/Fb11 DMITST8 F/F DMITMK8 F/Fb12 b5 DMITST7 F/F DMITMK7 F/Fb13 DMITMK6 F/F F/Fb14 b7 DMITST5 F/F DMITMK5 F/Fb15 (Level) 5-source inputs DM59ITST <H ’0080 0408> DM59ITMK <H ’0080 0409> DMA9UDF DMA6UDF DMA5UDF DMA8UDF DMA7UDF DMITST6 DMAC

9-39 Rev.1.0

9.3 Functional Description of DMAC

9.3.1 Cause of DMA Request

A DMA transfer can be requested individually for each DMA channel (0-9 channels) from multiple sources. There are various causes of DMA transfer request, so that a DMA transfer may be started by an internal peripheral I/O, started in software by a program, or started by completion of one or all DMA transfers on another channel (cascade mode). To select a cause of DMA request, use the cause of request select bits for the desired channel REQSLn (DMAn Channel Control Register D2, D3 bits) or the extended request cause select bits REQESELn (DMAn Request Extended Cause Register D4-D7 bits). The causes of DMA request on each channel are listed below. Table 9.3.1 Causes of DMA Request on DMA0 and the Timing at Which Requests are Generated REQSL0 Causes of DMA Request DMA Request Generation Timing 0 0 Software start or When any data is written to the DMA0 Software Request One DMA2 transfer completed Generation Register (software start) or one transfer on DMA2 is completed (cascade mode) 0 1 A-D0 conversion completed When A-D0 conversion is completed 1 0 Timer (TOM00_udf) When TOM00 timer underflows 1 1 Extended request cause – Table 9.3.2 DMA Request Extended Causes on DMA0 and the Timing at Which Requests are Generated REQESEL0 DMA Request Extended Cause DMA Request Generation Timing

0000 All DMA1 transfers completed When all transfers on DMA1 are completed (cascade mode)

0001 TID0_udf,ovf When TID0 timer underflows or overflows

0010 TID1_udf,ovf When TID1 timer underflows or overflows

0011 TIN16 input signal When the timer's TIN16 input signal is generated

0100 TIN0A input signal When PD module's TIN0A input signal is generated

0101 Serial I/O-2 When serial I/O-2 transmit buffer is empty

(transmit buffer empty)

0110 Serial I/O-7 When serial I/O-7 transmit buffer is empty

(transmit buffer empty) Note: The DMA request extended causes are effective only when "Extended request cause" is selected with the DMA0 Channel Control Register REQSL0 bits. DMAC

9-40 Rev.1.0 Table 9.3.3 Causes of DMA Request on DMA1 and the Timing at Which Requests are Generated REQSL1 Causes of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to the DMA1 Software Request Generation Register 0 1 Extended request cause – 1 0 Timer (TOM01_udf) When TOM01 timer underflows 1 1 One DMA0 transfer completed When one transfer on DMA0 is completed (cascade mode) Table 9.3.4 DMA Request Extended Causes on DMA1 and the Timing at Which Requests are Generated REQESEL1 DMA Request Extended Cause DMA Request Generation Timing

0100 TIN17 input signal When the timer's TIN17 input signal is generated

0101 TOM02_udf When TOM02 timer underflows

0110 Serial I/O-4 (reception completed) When serial I/O-4 reception is completed

0111 One DMA9 transfer completed When one transfer on DMA9 is completed (cascade mode)

1000 PD_CMP0 When absolute data comparison on PD module channel 0

1001 PD_CMP1 When absolute data comparison on PD module channel 1

Note: The DMA request extended causes are effective only when "Extended request cause" is selected with the DMA1 Channel Control Register REQSL1 bits. DMAC

9-41 Rev.1.0 Table 9.3.5 Causes of DMA Request on DMA2 and the Timing at Which Requests are Generated REQSL2 Causes of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to the DMA2 Software Request Generation Register 0 1 Extended request cause – 1 0 PD module (TIN0B input signal) When PD module's TIN0B input signal is generated 1 1 One DMA1 transfer completed When one transfer on DMA1 is completed (cascade mode) Table 9.3.6 DMA Request Extended Causes on DMA2 and the Timing at Which Requests are Generated REQESEL2 DMA Request Extended Cause DMA Request Generation Timing

0100 TIN18 input signal When the timer's TIN18 input signal is generated

0101 TOM07_udf When TOM07 timer underflows

0110 Serial I/O-5 (reception completed) When serial I/O-5 reception is completed

Note: The DMA request extended causes are effective only when "Extended request cause" is selected with the DMA2 Channel Control Register REQSL2 bits. DMAC

9-42 Rev.1.0 Table 9.3.7 Causes of DMA Request on DMA3 and the Timing at Which Requests are Generated REQSL3 Causes of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to the DMA3 Software Request Generation Register 0 1 Serial I/O-0 When serial I/O-0 transmit buffer is empty (transmit buffer empty) 1 0 Serial I/O-1 (reception completed) When serial I/O-1 reception is completed 1 1 Extended request cause – Table 9.3.8 DMA Request Extended Causes on DMA3 and the Timing at Which Requests are Generated REQESEL3 DMA Request Extended Cause DMA Request Generation Timing

0100 TIN19 input signal When the timer's TIN19 input signal is generated

0101 TOM03_udf When TOM03 timer underflows

0110 A-D1 conversion completed When A-D1 conversion is completed

Note: The DMA request extended causes are effective only when "Extended request cause" is selected with the DMA3 Channel Control Register REQSL3 bits. DMAC

9-43 Rev.1.0 Table 9.3.9 Causes of DMA Request on DMA4 and the Timing at Which Requests are Generated REQSL4 Causes of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to the DMA4 Software Request Generation Register 0 1 One DMA3 transfer completed When one transfer on DMA3 is completed (cascade mode) 1 0 Serial I/O-0 (reception completed) When serial I/O-0 reception is completed 1 1 Extended request cause – Table 9.3.10 DMA Request Extended Causes on DMA4 and the Timing at Which Requests are Generated REQESEL4 DMA Request Extended Cause DMA Request Generation Timing

0100 TIN23 input signal When the timer's TIN23 input signal is generated

0101 TOM04_udf When TOM04 timer underflows

0110 Serial I/O-3 When serial I/O-3 transmit buffer is empty

(transmit buffer empty)

0111 One DMA9 transfer completed When one transfer on DMA0 is completed (cascade mode)

Note: The DMA request extended causes are effective only when "Extended request cause" is selected with the DMA4 Channel Control Register REQSL4 bits. DMAC

9-44 Rev.1.0 Table 9.3.11 Causes of DMA Request on DMA5 and the Timing at Which Requests are Generated REQSL5 Causes of DMA Request DMA Request Generation Timing 0 0 Software start or When any data is written to the DMA5 Software Request One DMA7 transfer completed Generation Register (software start) or one transfer on DMA7 is completed (cascade mode) 0 1 All DMA0 transfers completed When all transfers on DMA0 are completed (cascade mode) 1 0 Serial I/O-2 (reception completed) When serial I/O-2 reception is completed 1 1 Extended request cause – Table 9.3.12 DMA Request Extended Causes on DMA0 and the Timing at Which Requests are Generated REQESEL5 DMA Request Extended Cause DMA Request Generation Timing

0100 TIN1A input signal When PD module's TIN1A input signal is generated

0101 TOM16_udf When TOM16 timer underflows

0110 Serial I/O-4 When serial I/O-4 transmit buffer is empty

(transmit buffer empty) Note: The DMA request extended causes are effective only when "Extended request cause" is selected with the DMA5 Channel Control Register REQSL5 bits. DMAC

9-45 Rev.1.0 Table 9.3.13 Causes of DMA Request on DMA6 and the Timing at Which Requests are Generated REQSL6 Causes of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to the DMA6 Software Request Generation Register 0 1 Serial I/O-1 When serial I/O-1 transmit buffer is empty (transmit buffer empty) 1 0 Extended request cause – 1 1 One DMA5 transfer completed When one transfer on DMA5 is completed (cascade mode) Table 9.3.14 DMA Request Extended Causes on DMA6 and the Timing at Which Requests are Generated REQESEL6 DMA Request Extended Cause DMA Request Generation Timing

0100 TIN20 input signal When the timer's TIN20 input signal is generated

0101 TOM05_udf When TOM05 timer underflows

0110 Serial I/O-6 (reception completed) When serial I/O-6 reception is completed

Note: The DMA request extended causes are effective only when "Extended request cause" is selected with the DMA6 Channel Control Register REQSL6 bits. DMAC

9-46 Rev.1.0 Table 9.3.15 Causes of DMA Request on DMA7 and the Timing at Which Requests are Generated REQSL7 Causes of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to the DMA7 Software Request Generation Register 0 1 Serial I/O-2 When serial I/O-2 transmit buffer is empty (transmit buffer empty) 1 0 Extended request cause – 1 1 One DMA6 transfer completed When one transfer on DMA6 is completed (cascade mode) Table 9.3.16 DMA Request Extended Causes on DMA7 and the Timing at Which Requests are Generated REQESEL7 DMA Request Extended Cause DMA Request Generation Timing

0100 TIN1B input signal When PD module's TIN1B input signal is generated

0101 TOM06_udf When TOM06 timer underflows

0110 Serial I/O-5 When serial I/O-5 transmit buffer is empty

(transmit buffer empty) Note: The DMA request extended causes are effective only when "Extended request cause" is selected with the DMA7 Channel Control Register REQSL7 bits. DMAC

9-47 Rev.1.0 Table 9.3.17 Causes of DMA Request on DMA8 and the Timing at Which Requests are Generated REQSL8 Causes of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to the DMA8 Software Request Generation Register 0 1 All DMA3 transfers completed When all transfers on DMA3 are completed (cascade mode) 1 0 Serial I/O-3 (reception completed) When serial I/O-3 reception is completed 1 1 Extended request cause – Table 9.3.18 DMA Request Extended Causes on DMA8 and the Timing at Which Requests are Generated REQESEL8 DMA Request Extended Cause DMA Request Generation Timing

0100 TIN21 input signal When the timer's TIN21 input signal is generated

0101 TOM17_udf When TOM17 timer underflows

0110 Serial I/O-6 When serial I/O-6 transmit buffer is empty

(transmit buffer empty) Note: The DMA request extended causes are effective only when "Extended request cause" is selected with the DMA8 Channel Control Register REQSL8 bits. DMAC

9-48 Rev.1.0 Table 9.3.19 Causes of DMA Request on DMA9 and the Timing at Which Requests are Generated REQSL9 Causes of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to the DMA9 Software Request Generation Register 0 1 Serial I/O-3 When serial I/O-3 transmit buffer is empty (transmit buffer empty) 1 0 Extended request cause – 1 1 One DMA8 transfer completed When one transfer on DMA8 is completed (cascade mode) Table 9.3.20 DMA Request Extended Causes on DMA9 and the Timing at Which Requests are Generated REQESEL9 DMA Request Extended Cause DMA Request Generation Timing

0100 TIN22 input signal When the timer's TIN22 input signal is generated

0101 TOM10_udf When TOM10 timer underflows

0110 Serial I/O-7 (reception completed) When serial I/O-7 reception is completed

Note: The DMA request extended causes are effective only when "Extended request cause" is selected with the DMA9 Channel Control Register REQSL9 bits. DMAC

9-49 Rev.1.0

9.3.2 DMA Transfer Processing Procedure

The following explains how DMA transfers are performed by using DAM channel 0 as an example. Note: If "Extended request cause" is selected with the DMA0 Channel Control Register's cause of DMA0 request select (REQSL0) bits, always be sure to set the DMA0 Request Ex- tended Cause Register (DM0REQ). Figure 9.3.1 DMA Transfer Processing Procedure (Example) DMAC DMA transfer starts by request from internal peripheral I/O Start DMA transfer processing Transfer Count Register underflows Interrupt request generated Set DMA0 Channel Control Register Set DMA0-4 Interrupt Request Status Register Set DMA0 Channel Control Register (Set DMA0 Request Extended Cause Register) (Note) Set DMA0 Source Address Register Set DMA0 Destination Address Register Set DMA0 Count Register DMAC related register settings DMA transfer start DMA transfer complete

• Transfers disabled
• Clear the interrupt request status bit Set DMA0-4 Interrupt Mask Register
• Source address of DMA transfer
• Destination address of DMA transfer
• Number of times a DMA transfer is performed
• Transfer mode, request cause, transfer size, address direction, and transfer enable End of DMA operation
• Enable interrupt request Set Interrupt Controller DMA0-4 Interrupt Control Register • Interrupt priority level Interrupt controller related register settings

9-50 Rev.1.0

9.3.3 Starting DMA

Use the REQSL (cause of DMA request select) bits to select the cause of DMA request. To enable DMA, set the TENL (DMA transfer enable) bit to 1. A DMA transfer starts when the selected cause of DMA request becomes effective after setting the TENL (DMA transfer enable) bit to 1. Note: If the request source specified with the REQSL (DMA request source select) bit is an input/ output timer (TIN input signal), the time required for DMA transfer to start after detecting the rising or falling edge or both edges of the TIN input signal is three cycles at the least (150 ns when operating with the internal peripheral clock = 20 MHz). Or, depending on the bus usage condition before or after the DMA transfer, up to six cycles may be required (300 ns when operating with the internal peripheral clock = 20 MHz). (The above required time for DMA transfer to start after detecting the TIN input signal is calculated assuming that the external bus is unused, and that HOLD and the LOCK instruction are not used.) To ensure that changes of state of the TIN input signal will be detected correctly, make sure the TIN input signal has a pulse width of at least 7tc(BCLK)/2. (For details, see Section 23.6, "AC Characteristics.")

9.3.4 Priority of DMA Channels

DMA channel 0 has the highest priority, which is followed by other channels as shown below. The channel priority is fixed. Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 > Transfer requests on channels are sampled every transfer cycle (= three DMA bus cycles), and the channel that has the highest priority among those which have transfer requests generated is selected. DMAC

9-51 Rev.1.0

9.3.5 Gaining and Releasing Control of the Internal Bus

Gaining and releasing control of the internal bus is arbitrated by a single-transfer method DMA on all channels. With the single-transfer method DMA, the DMA controller gains control of the internal bus when a DMA transfer request is accepted and returns bus control to the CPU after executing one session of DMA transfer (one read cycle + one write cycle of the internal peripheral clock). The diagram below shows the behavior of the single-transfer method DMA. Figure 9.3.2 Gaining and Releasing Control of the Internal Bus

9.3.6 Transfer Unit

The number of data bits transferred in one DMA transfer (8 or 16 bits), referred to as the transfer unit, is selected for each channel with the TSZSL (DMA transfer size select) bit.

9.3.7 Transfer Count

The transfer count, or the number of times a DMA transfer is performed, is set for each channel by using the DMA Transfer Count Register. DMA transfer can be performed up to 256 times. The value of the transfer count register is decremented by one for each transfer unit transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-running mode, with its set value ignored. DMAC (Request from the DMAC) Internal bus R: Read W: Write RW RW RW Request Granted Request Granted Request Granted One session of DMA transfer One session of DMA transfer Relinquished Relinquished Relinquished

9-52 Rev.1.0

9.3.8 Address Space

The address space in which DMA transfers can be performed is 64 Kbytes (H'0080 0000 to H'0080 FFFF) of internal peripheral I/O or RAM for both source and destination. The source and destination addresses on each channel are set using the DMA Source Address and DMA Destination Address Registers.

9.3.9 Transfer Operation

(1) Dual-address transfer Regardless of the transfer unit, a DMA transfer is performed with two bus cycles consisting of a source read access and a destination write access. (The transfer data is temporarily stored in the DMAC's internal temporary register before being transferred.) (2) Bus protocol and bus timing The bus interface is shared with the CPU. Therefore, the bus protocol and bus timing both are the same as in peripheral module access from the CPU. (3) Transfer rate The maximum transfer rate is calculated using the equation below. (4) Address count direction and address change The directions in which the source and destination addresses are counted (address fixed or address increment) are set for each channel by using the SADSL (source address direction select) bit and DADSL (designation address direction select) bit. When "Address increment" is selected, the address is incremented by 2 when the transfer unit = 16 bits or by 1 when the transfer unit = 8 bits each time one DMA transfer is performed. Table 9.3.11 Address Count Direction and Address Change Address count direction Transfer unit Address change for one DMA transfer performed Address fixed 8 bits 0 16 bits 0 Address increment 8 bits +1 16 bits +2 DMAC Maximum transfer rate [bytes/second] = 2 bytes x 1 / f (BCLK) x 3 cycles

9-53 Rev.1.0 (5) Transfer count value The transfer count value is decremented by one for each DMA transfer performed, regardless of whether the transfer unit is 8 or 16 bits. (6) Transfer byte position When the transfer unit = 8 bits, the LSB of the address register is effective for both the source and destination. (Therefore, even to odd address or odd to even address transfers, as well as even to even address and odd to odd address transfers, are possible.) When the transfer unit = 16 bits, the LSB of the address register (address register D15 bit) is ignored, and the two bytes of data transferred are always aligned with the 16-bit bus. The diagram below shows the valid transfer byte positions. Figure 9.3.3 Transfer Byte Positions DMAC +0 +1 Source Destination <When transfer size = 8 bits> 8 bits 8 bits 8 bits 16 bits 16 bits D0 D7 D8 D15 +0 +1 <When transfer size = 16 bits>

9-54 Rev.1.0 (7) Ring buffer mode When ring buffer mode is selected, operation starts from the transfer start address and when transferred 32 times, returns to the transfer start address again, from which transfer operation restarts. However, the 5 low-order bits of the ring buffer start address must always be B'00000. The following describes how the addresses are incremented in ring buffer mode. x When the transfer size is 8 bits The 27 high-order bits of the transfer start address are fixed, with the 5 low-order bits incremented by one for each transfer performed. When the 5 low-order bits reach B'11111 after performing transfers beginning with the start address, the bits are reset to B'00000 by the next increment action, thus returning to the start address. ➁ When the transfer size is 16 bits The 26 high-order bits of the transfer start address are fixed, with the 6 low-order bits incremented by two for each transfer performed. When the 6 low-order bits reach B'111110 after performing transfers beginning with the start address, the bits are reset to B'000000 by the next increment action, thus returning to the start address. It is the source address if the source has been set to increment or the destination address if the destination has been set to increment that returns to the start address in this way. If the source and destination addresses both have been set to increment, both addresses return to the start address. However, the start addresses on either side must always have the 5 low- order bits initially set to B'00000. During ring buffer mode, the transfer counter register is ignored. After DMA operation starts, the counter operates in free-running mode, with transfers continued until the transfer enable bit is cleared to 0 (to disable transfers). Figure 9.3.4 Typical Address Increment Action in 32-channel Ring Buffer Mode DMAC <When the transfer size = 8 bits> Transfer count Transfer address

1 H'0080 1000

2 H'0080 1001

3 H'0080 1002

31 H'0080 101E

32 H'0080 101F

<When the transfer size = 16 bits> Transfer count Transfer address

2 H'0080 1002

3 H'0080 1004

31 H'0080 103C

32 H'0080 103E

9-55 Rev.1.0

9.3.10 End of DMA and Interrupt

In normal mode, a DMA transfer ends when the transfer count register underflows after reaching the terminal count. When a transfer ends, the transfer enable bit is cleared to 0 to disable transfers. Also an interrupt request is generated at completion of a transfer. For channels where interrupt requests are masked with the DMA Interrupt Mask Register, no interrupts are generated, however. During ring buffer mode, the transfer counter operates in free-running mode, so that a transfer continues until the transfer enable bit is cleared to 0 (to disable transfers). Therefore, no DMA transfer-finished interrupt requests are generated. Nor are DMA transfer-finished interrupt requests are generated when ring buffer mode transfer is terminated by clearing the transfer enable bit.

9.3.11 Register Status after End of DMA Transfer

When a DMA transfer ends, the Source Address and Destination Address Registers are in the following state. (1) When address fixed

• The address remains fixed, i.e., the same as the set value before the DMA transfer started (2) When address incremented
• For 8-bit transfers, the last transfer address + 1
• For 16-bit transfers, the last transfer address + 2 When a DMA transfer has finished, the transfer count register is in an underflow condition (H'FF). Therefore, to reexecute a DMA transfer, set the transfer count register back again, unless you are performing transfers 256 times (H'FF). DMAC

9-56 Rev.1.0

• About writing to the DMA related registers In DMA transfers, data are exchanged via the internal bus. Therefore, make sure the DMA related registers basically are written to immediately after reset or when transfers are disabled (transfer enable bit = 0). When transfers are enabled, do not write to the DMA related registers, except for the DMA transfer enable bit, transfer request flag, and the DMA transfer count register that is protected against write in hardware. This is necessary to ensure stable operation of DMA transfers. The table below shows whether DMA related registers can be accessed for write. Table 9.4.1 DMA Related Registers That Can Be and Cannot Be Accessed for Write State Transfer enable bit Transfer request flag Other DMA related registers Transfers enabled ✕ Transfers disabled : Can be accessed; 5: Cannot be accessed Even for a few exceptional registers that can be accessed for write while transfers are enabled, make sure the following conditions are met. x DMA Channel Control Register's transfer enable bit and transfer request flag For all other bits of the channel control register, write the same data as they had before writing. Note that for the transfer request flag, only writing 0 is effective. ➁ DMA Transfer Count Register When transfers are enabled, this register is protected against write in hardware. Therefore, the data written to this register is ignored. ➂ Rewriting the source and destination addresses of DMA on other channels by a DMA transfer Although this means accessing the DMA related registers while transfers are enabled, it may not cause any problem. However, a DMA transfer to any DMA related registers on the current channel cannot be performed. DMAC

9-57 Rev.1.0

• Operating on DMA related registers by a DMA transfer When operating on DMA related registers using a DMA transfer (e.g., reloading the DMA related registers with their initial values by a DMA transfer), do not write to any DMA related registers on the local channel, i.e., the channel on which the DMA transfer is being performed. If this precaution is neglected, device operation cannot be guaranteed. Rewriting the DMA related registers by a DMA transfer is possible on only other channels. For example, the DMAn Source Address and DMAn Destination Address Registers on channel 1 can be rewritten by a DMA transfer through channel 0.
• About the DMA Interrupt Request Status Register When writing to the DMA Interrupt Request Status Register to clear some bits, be sure to write 1 to all bits other than those to be cleared. Any bit of this register is unaffected by writing 1, the bit retains the value it had before writing.
• About the stable operation of DMA transfers To ensure stable operation of DMA transfers, do not rewrite the DMA related registers unless transfers are disabled, except for the DMA Channel Control Register's transfer enable bit. It is only the DMA Source Address and Destination Address Registers that can be rewritten when transfers are enabled, provided, however, that the rewriting is performed by a DMA transfer through another channel. DMAC

9-58 Rev.1.0 DMAC

10.1 Outline of the Input/Output

10.2 Common Timer Unit

10.3 TMS (Input Related 16-bit

Timers)

10.4 TML (Input Related 32-bit

Timers)

10.5 TID (Input Related 16-bit

Timers)

10.6 TOM (Output Related 16-bit

Timers) CHAPTER 10CHAPTER 10 INPUT/OUTPUT TIMERS

10-2 Rev.1.0

10.1 Outline of the Input/Output Timers

The 32172/32173 has four types of input/output timers, providing a total of 26 channels of timers. INPUT/OUTPUT TIMERS Table 10.1.1 Outline of Timers Name Type No. of Channels Content TMS Input related 4 16-bit input measurement timer. (Timer 16-bit timers With new/old captured data hold function Measure (up-counters) Small) TML Input related 4 32-bit input measurement timer. (Timer 32-bit timers With new/old captured data hold function Measure (up-counters) Large) TID Input related 2 Four modes are available that can be selected in software. (Timer 16-bit timers • Fixed period mode Input (up/down-counters) • Event count mode Derivation) • Multiply-by-4 event count mode

• Up/down event count mode TOM Output related 16 Four output modes are available that can be selected in software. (Timer 16-bit timers <Without correction function> Output (down-counters) • PWM output mode Modification) • Sing le-shot PWM output mode
• Single-shot output mode
• Successive output mode

10-3 Rev.1.0 Table 10.1.2 Interrupt Generating Functions of Timers Signal Name Timer Interrupt Request Source Input to Interrupt Controller (ICU)ICU Cause Input IRQ30 PWMOFF0, PWMOFF1 inputs PWM off input interrupt 2 IRQ28 TIN8, TIN9 inputs Timer input interrupt 5 2 IRQ27 TIN10, TIN11 inputs Timer input interrupt 4 2 IRQ25 TIN20, TIN21 inputs Timer input interrupt 3 3 IRQ24 TIN22, TIN23 inputs Timer input interrupt 2 3 IRQ23 TIN16, TIN17 inputs Timer input interrupt 1 3 IRQ22 TIN18, TIN19 inputs Timer input interrupt 0 3 IRQ21 TOM0_0 - TOM0_7 outputs TOM0 output interrupt 8 IRQ20 TOM1_0 - TOM1_7 outputs TOM1 output interrupt 8 IRQ19 TMS0 outputs TMS0 output interrupt 1 IRQ18 TID0 outputs TID0 output interrupt 1 IRQ17 TID1 outputs TID1 output interrupt 1 Table 10.1.3 DMA Transfer Request Generating Functions of Timers Signal Name DMA Transfer Request Source DMA Input Channel DRQ0 TID0 underflow/overflow Channel 0 to channel 9 DRQ1 TID1 underflow/overflow Channel 0 to channel 9 DRQ2 TOM0_0 underflow Channel 0 DRQ3 TOM0_1 underflow Channel 1 DRQ4 TOM0_2 underflow Channel 1 DRQ5 TOM0_3 underflow Channel 3 DRQ6 TOM0_4 underflow Channel 4 DRQ7 TOM0_5 underflow Channel 6 DRQ8 TOM0_6 underflow Channel 7 DRQ9 TOM0_7 underflow Channel 2 DRQ10 TOM1_0 underflow Channel 9 DRQ11 TOM1_6 underflow Channel 5 DRQ12 TOM1_7 underflow Channel 8 DRQ13 TIN16 input Channel 0 to channel 9 DRQ14 TIN17 input Channel 1 DRQ15 TIN18 input Channel 2 DRQ16 TIN19 input Channel 3 DRQ17 TIN20 input Channel 6 DRQ18 TIN21 input Channel 8 DRQ19 TIN22 input Channel 9 DRQ20 TIN23 input Channel 4 INPUT/OUTPUT TIMERS

10-4 Rev.1.0 Table 10.1.4 A-D Conversion Start Request Functions of Timers Signal Name A-D Conversion Start Request Source A-D Converter AD0TRG TIN16 input, TOM0_6 underflow, Can be input for A-D0 conversion start trigger or TOM0 enable event AD1TRG TIN16 input, TOM0_6 underflow, Can be input for A-D1 conversion start trigger or TOM1_6 underflow INPUT/OUTPUT TIMERS

10-5 Rev.1.0 Figure 10.1.1 Block Diagram of Timers (1/3) clk TID0 TIN8 TIN9 I/2 Internal Peripheral Clock IRQ18 clk TOM0_0 udf F/F0 clk TOM0_1 udf F/F1 TO0 TO1 clk TOM0_2 udf F/F2 clk TOM0_3 udf F/F3 TO2 TO3 clk TOM0_4 udf F/F4 clk TOM0_5 udf F/F5 TO4 TO5 clk TOM0_6 udf F/F6 clk TOM0_7 udf F/F7 TO6 TO7 IRQ21 IRQ21 IRQ21 IRQ21 IRQ21 IRQ21 IRQ21 IRQ21 CLK1 CLK2 PRS2 EN EN EN EN EN EN ovf udf EN EN DRQ0 DRQ2 DRQ3 DRQ4 DRQ5 DRQ6 DRQ7 DRQ8 DRQ9 PWM Output Disable Control Register 0 To A-D0 Converter IRQ28 IRQ28 PWMOFF0S TIN8S TIN9S TIN16/PWMOFF0 S S clk TID1 TIN10 TIN11 I/2 Internal Peripheral Clock IRQ17 clk TOM1_0 udf F/F8 clk TOM1_1 udf F/F9 TO8 TO9 clk TOM1_2 udf F/F10 clk TOM1_3 udf F/F11 TO10 TO11 clk TOM1_4 udf F/F12 clk TOM1_5 udf F/F13 TO12 TO13 clk TOM1_6 udf F/F14 clk TOM1_7 udf F/F15 TO14 TO15 IRQ20 IRQ20 IRQ20 IRQ20 IRQ22 IRQ20 IRQ20 IRQ20 CLK1 CLK2 PRS3 EN EN EN EN EN EN ovf udf EN EN DRQ1 DRQ10 DRQ11 DRQ12 PWM Output Disable Control Register 1 IRQ27 IRQ27 PWMOFF1S TIN10S TIN11S TIN17/PWMOFF1 S S IRQ30 TIN18 TIN19 TIN18S IRQ22 IRQ22 TIN19S IRQ30 To A-D1 Converter To A-D0, 1Converter or PD Module INPUT/OUTPUT TIMERS

10-6 Rev.1.0 Figure 10.1.2 Block Diagram of Timers (2/3) clk TMS0 ovfcap3 cap2 cap1 cap0 S S TIN16/PWMOFF0 TIN17/PWMOFF1 TIN18 TIN19 IRQ23 IRQ23 IRQ22 IRQ22 I/2 Internal Peripheral Clock IRQ19 TIN16S TIN17S TIN18S TIN19S PRS0 IRQ23 TIN16S1 IRQ22 TIN18S1 clk TML0 cap3 cap2 cap1 cap0 S S TIN20 TIN21 TIN22 TIN23 IRQ25 IRQ25 IRQ24 IRQ24 I/2 Internal Peripheral Clock TIN20S TIN21S TIN22S TIN23S PRS1 IRQ25 TIN20S1 IRQ24 TIN22S1 S DRQ17 DRQ18 DRQ19 DRQ20 DRQ13 DRQ14 DRQ15 DRQ16 To A-D0, 1 Converter or PD Module INPUT/OUTPUT TIMERS

10-7 Rev.1.0 Figure 10.1.3 Block Diagram of Timers (3/3) udf endDMA0 DMAIRQ0 TOM02_udf SIO4-RXD AD0 finished TOM00_udf TIN16 SIO2-TXD SIO7-TXD TIN17 TOM01_udf PD_CMP0 PD_CMP1 TOM07_udf SIO5-RXD TIN18 TIN0B TOM03_udf AD1 finished TIN19 SIO0-TXD SIO1-RXD TOM04_udfTIN23 SIO0-RXD SIO3-TXD TOM16_udf TIN1A SIO2-RXD SIO4-TXD TOM05_udf TIN20 SIO1-TXD SIO6-RXD TOM06_udfTIN1B SIO2-TXD SIO5-TXD TOM17_udfTIN21 SIO3-RXD SIO6-TXD STOM10_udf TIN22 SIO3-TXD SIO7-RXD udf endDMA1 udf endDMA2 udf endDMA3 udf endDMA4 udf endDMA5 udf endDMA6 udf endDMA7 udf endDMA8 udf endDMA9 DMAIRQ0 DMAIRQ0 DMAIRQ0 DMAIRQ0 DMAIRQ1 DMAIRQ1 DMAIRQ1 DMAIRQ1 DMAIRQ1 S S S S S S S S S TID0_udf,ovf TID1_udf,ovf S S S S S S S S S S TIN0A INPUT/OUTPUT TIMERS

10-8 Rev.1.0 The common timer unit includes the following blocks:

• Prescaler unit
• Input processing control unit
• Output flip-flop control unit
• Interrupt control unit

10.2.1 Register Map of the Common Timer Unit

The next page shows a register map of the common timer unit. INPUT/OUTPUT TIMERS

10-9 Rev.1.0 H'0080 0800 Address D0 D7 +0 address +1 address D8 D15 H'0080 0802 H'0080 0804 H'0080 0840 H'0080 0842 H'0080 0844 H'0080 0846 H'0080 0850 H'0080 0848 H'0080 0CD0 H'0080 0CD2 H'0080 0CD4 H'0080 0CD6 H'0080 084A TIN Input Processing Control Register0 (TINCR0) Prescaler Register 2 (PRS2) TOM0 Interrupt Mask Register (TOM0IMA) TOM0 Interrupt Status Register (TOM0IST) F/F Protect Register 0 (FFP0) F/F Data Register 0 (FFD0) TID0 Control & Prescaler 2 Enable Register (TID0PRS2EN) Blank areas are reserved for future use. TIN Input Processing Control Register1 (TINCR1) TIN Input Processing Control Register2 (TINCR2) TIN Input Processing Control Register3 (TINCR3) TIN Input Processing Control Register4 (TINCR4) TIN Input Processing Control Register5 (TINCR5) TIN Interrupt Mask Register 0 (TINIMA0) TIN Interrupt Status Register 0 (TINIST0) TIN Interrupt Mask Register 1 (TINIMA1) TIN Interrupt Status Register 1 (TINIST1) TIN Interrupt Mask Register 2 (TINIMA2) TIN Interrupt Status Register 2 (TINIST2) TIN Interrupt Mask Register 3 (TINIMA3) TIN Interrupt Status Register 3 (TINIST3) TIN Interrupt Mask Register 4 (TINIMA4) TIN Interrupt Status Register 4 (TINIST4) TIN Interrupt Mask Register 5 (TINIMA5) TIN Interrupt Status Register 5 (TINIST5) TIN Interrupt Mask Register 8 (TINIMA8) TIN Interrupt Status Register 8 (TINIST8) H'0080 088A Prescaler Register 1 (PRS1) H'0080 08EA Prescaler Register 0 (PRS0) Prescaler Register 3 (PRS3) TOM1 Interrupt Mask Register (TOM1IMA) TOM1 Interrupt Status Register (TOM1IST) TID1 Control & Prescaler 3 Enable Register (TID1PRS3EN)H'0080 0DD0 H'0080 0DD2 H'0080 0DD4 H'0080 0DD6 F/F Data Register 1 (FFD1) F/F Protect Register 1 (FFP1) Figure 10.2.1 Register Map of the Common Timer Unit INPUT/OUTPUT TIMERS

10-10 Rev.1.0

10.2.2 Prescaler Unit

The prescalers PRS0-3 are 8-bit counter, which generates clocks supplied to each timer (TMS, TML, TID, and TOM) from the divided-by-2 frequency of the internal peripheral clock (10.0 MHz when the internal peripherals are operating at 20 MHz). The value of each prescaler register is initialized to H'00 when reset. When the set value of the prescaler register is rewritten, the prescaler starts operating with the newly set value synchronously with the timing at which it underflows. Values H'00 to H'FF can be set in the prescaler's counter register. The prescaler's divide ratio is given by the equation below. I Prescaler Register 0 (PRS0) <Address: H'0080 08EB> I Prescaler Register 1 (PRS1) <Address: H'0080 088B> I Prescaler Register 2 (PRS2) <Address: H'0080 0CD0> I Prescaler Register 3 (PRS3) <Address: H'0080 0DD0> (D8 9 10 11 12 13 14 D15) PRS0-PRS3 D 0 123456 D 7 <When reset: H'00> D Bit Name Function R W 0-7 PRS2,3 Sets the prescaler's divide-by value 8-15 PRS0,1 Prescaler Registers 0 and 1 start counting after reset. Prescaler Registers 2 and 3 respectively are activated by setting the TID0 Control & Prescaler 2 Enable Register and TID1 Control & Prescaler 3 Enable Register prescaler n enable (PRSnEN) bits to 1 (letting count start) and with the prescaler register value reloaded, start counting. For details, see Section 10.5, "TID (Input Related 16-bit Timer)." INPUT/OUTPUT TIMERS Prescaler divide ratio = Prescaler set value + 1

10-11 Rev.1.0

10.2.3 Input Processing Control Unit

The input processing control unit performs TIN signal input processing. In its TIN input processing unit, this unit selects the active signal edge (rising or falling edge or both edges) or the active level (high or low) at which to generate the signal to be fed to each timer for the enable, measurement, and count source signals. There are following input processing control registers.

• TIN Input Processing Control Register 0 (TINCR0)
• TIN Input Processing Control Register 1 (TINCR1)
• TIN Input Processing Control Register 2 (TINCR2)
• TIN Input Processing Control Register 3 (TINCR3)
• TIN Input Processing Control Register 4 (TINCR4)
• TIN Input Processing Control Register 5 (TINCR5) INPUT/OUTPUT TIMERS

10-12 Rev.1.0 Item Function Functions of TIN Input Processing Control Registers INPUT/OUTPUT TIMERS

10-13 Rev.1.0 I TIN Input Processing Control Register 0 (TINCR0) <Address: H'0080 0800> D 0 123456 D 7 TIN21S TIN20S1 TIN20S <When reset: H'00> D Bit Name Function R W 0,1 No functions assigned 0 – 2,3 TIN21S 00: Ignores input (Selects TIN21 input processing)01: Rising edge 10: Falling edge 11: Both edges 4,5 TIN20S1 00: Ignores input (Selects TIN20 input processing01: Rising edge for TML measurement 2) 10: Falling edge 11: Both edges 6,7 TIN20S 00: Ignores input (Selects TIN20 input processing)01: Rising edge 10: Falling edge 11: Both edges INPUT/OUTPUT TIMERS

10-14 Rev.1.0 I TIN Input Processing Control Register 1 (TINCR1) <Address: H'0080 0801> D 8 9 1 01 11 21 31 4 D 1 5 TIN23S TIN22S1 TIN22S <When reset: H'00> D Bit Name Function R W 8,9 No functions assigned 0 – 10,11 TIN23S 00: Ignores input (Selects TIN23 input processing) 01: Rising edge 10: Falling edge 11: Both edges 12,13 TIN22S1 00: Ignores input (Selects TIN22 input processing01: Rising edge for TML measurement 0) 10: Falling edge 11: Both edges 14,15 TIN22S 00: Ignores input (Selects TIN22 input processing) 01: Rising edge 10: Falling edge 11: Both edges INPUT/OUTPUT TIMERS

10-15 Rev.1.0 I TIN Input Processing Control Register 2 (TINCR2) <Address: H'0080 0802> D 0 123456 D 7 TIN17S TIN16S1 TIN16S <When reset: H'00> D Bit Name Function R W 0,1 No functions assigned 0 – 2,3 TIN17S 00: Ignores input (Selects TIN17 input processing)01: Rising edge 10: Falling edge 11: Both edges 4,5 TIN16S1 00: Ignores input (Selects TIN16 input processing01: Rising edge for TML measurement 2) 10: Falling edge 11: Both edges 6,7 TIN16S 00: Ignores input (Selects TIN16 input processing)01: Rising edge 10: Falling edge 11: Both edges INPUT/OUTPUT TIMERS

10-16 Rev.1.0 I TIN Input Processing Control Register 3 (TINCR3) <Address: H'0080 0803> D 8 9 1 01 11 21 31 4 D 1 5 TIN19S TIN18S1 TIN18S <When reset: H'00> D Bit Name Function R W 8,9 No functions assigned 0 – 10,11 TIN19S 00: Ignores input (Selects TIN19 input processing) 01: Rising edge 10: Falling edge 11: Both edges 12,13 TIN18S1 00: Ignores input (Selects TIN18 input processing01: Rising edge for TML measurement 0) 10: Falling edge 11: Both edges 14,15 TIN18S 00: Ignores input (Selects TIN18 input processing) 01: Rising edge 10: Falling edge 11: Both edges INPUT/OUTPUT TIMERS

10-17 Rev.1.0 For PWM output to be disabled by selecting output disable processing "PWMOFF0" by TIN16 or output disable processing "PWMOFF1" by TIN17, the related registers must be set following the procedure described below. [Setup procedure]

• When selecting output disable processing "PWMOFF1" by TIN17 x Set the TIN17S2 write control (TIN17S2P) bit to 1. ➁ Subsequently after writing in (1) above, set the TIN17S2 write control (TIN17S2P) bit to 0 and the TIN17 "PWMOFF1" select (TIN17S2) bits to '000,' '001,' '010,' '011,' '10X,' or '11X.' Note: If a write cycle for any other area occurs between (1) and (2), the values written to the TIN17 "PWMOFF1" select (TIN17S2) bits have no effect.
• When selecting output disable processing "PWMOFF0" by TIN16 x Set the TIN16S2 write control (TIN16S2P) bit to 1. ➁ Subsequently after writing in (1) above, set the TIN16S2 write control (TIN16S2P) bit to 0 and the TIN16 "PWMOFF0" select (TIN16S2) bits to '000,' '001,' '010,' '011,' '10X,' or '11X.' Note: If a write cycle for any other area occurs between (1) and (2), the values written to the TIN16 "PWMOFF0" select (TIN16S2) bits have no effect. I TIN Input Processing Control Register 4 (TINCR4) <Address: H'0080 0804> D 0 123456 D 7 TIN17S2P TIN17S2 TIN16S2P TIN16S2 <When reset: H'00> D Bit Name Function R W

0 TIN17S2P – 0

(Controls TIN17S2 write) 1-3 TIN17S2 000: Ignores input (Selects TIN17 "PWMOFF1") 001: Rising edge 010: Falling edge 011: Both edges 10X: Low level 11X: High level

4 TIN16S2P – 0

(Controls TIN16S2 write) 5-7 TIN16S2 000: Ignores input (Selects TIN16 "PWMOFF0") 001: Rising edge 010: Falling edge 011: Both edges 10X: Low level 11X: High level INPUT/OUTPUT TIMERS

10-18 Rev.1.0 Figure 10.2.2 Procedure for Setting the TINCR4 Register when Output Disable Processing "PWMOFF1" by TIN17 is Selected Figure 10.2.3 Procedure for Setting the TINCR4 Register when Output Disable Processing "PWMOFF0" by TIN16 is Selected If a write cycle for any other area occurs within this interval, no data are set in the TIN17S2 bits.

• Set the TINCR4 Register TIN17S2P bit to 1 Note: The data that is set here may be "11X."
• Set the TINCR4 Register TIN17S2P bit to 0
• Set data in TINCR4 Register TIN17S2 bits If a write cycle for any other area occurs within this interval, no data are set in the TIN16S2 bits.
• Set the TINCR4 Register TIN16S2P bit to 1 Note: The data that is set here may be "11X."
• Set the TINCR4 Register TIN16S2P bit to 0
• Set data in TINCR4 Register TIN16S2 bits INPUT/OUTPUT TIMERS

10-19 Rev.1.0 I TIN Input Processing Control Register 5 (TINCR5) <Address: H'0080 0805> <When reset: H'00> D Bit Name Function R W 8,9 TIN11S 00: Ignores input (Selects TIN11 input processing)01: Rising edge 10: Falling edge 11: Both edges 10,11 TIN10S 00: Ignores input (Selects TIN10 input processing)01: Rising edge 10: Falling edge 11: Both edges 12,13 TIN9S 00: Ignores input (Selects TIN9 input processing)01: Rising edge 10: Falling edge 11: Both edges 14,15 TIN8S 00: Ignores input (Selects TIN8 input processing)01: Rising edge 10: Falling edge 11: Both edges D 8 9 1 01 11 21 31 4 D 1 5 TIN11S TIN10S TIN9S TIN8S INPUT/OUTPUT TIMERS

10-20 Rev.1.0

10.2.4 Output Flip-flop Control Unit

The output flip-flop control unit controls the flip-flop (F/F) provided for each timer output. There are following output flip-flop control registers.

• F/F Protect Register 0 (FFP0)
• F/F Protect Register 1 (FFP1)
• F/F Data Register 0 (FFD0)
• F/F Data Register 1 (FFD1) Table 10.2.1 below lists the timing at which a signal for the output flip-flop is generated by each timer. Table 10.2.1 Timing at Which Signal for Output Flip-flop is Generated by Each Timer Timer Mode Timing at which signal for output flip-flop is generated TMS (16-bit measurement input) No signal generating function TML (32-bit measurement input) No signal generating function TID Fixed period count mode No signal generating function Event count mode No signal generating function Multiply-by-4 event count mode No signal generating function Up/down event count mode No signal generating function TOM PWM output mode When counter is enabled or underflows Single-shot PWM output mode When counter underflows Single-shot output mode When counter is enabled or underflows Successive output mode When counter is enabled or underflows INPUT/OUTPUT TIMERS

10-21 Rev.1.0 Dn F/F Protect (FPn) WR Dn Output Control (ON/OFF) TOn Port Operation Mode Register (PnMOD) F/Fn Output Data (FDn) TOM_udf Note: Dn denotes the data bus. F/F F/F F/F Figure 10.2.4 Configuration of the F/F Output Circuit INPUT/OUTPUT TIMERS

10-22 Rev.1.0 I F/F Protect Register 0 (FFP0) <Address: H'0080 0CD5> D 8 9 1 01 11 21 31 4 D 1 5 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 <When reset: H'00> D Bit Name Function R W

8 FP0 (F/F0 protect) 0: Enables write to F/F output bit

9 FP1 (F/F1 protect) 1: Disables write to F/F output bit

10 FP2 (F/F2 protect)

11 FP3 (F/F3 protect)

12 FP4 (F/F4 protect)

13 FP5 (F/F5 protect)

14 FP6 (F/F6 protect)

15 FP7 (F/F7 protect)

I F/F Protect Register 1 (FFP1) <Address: H'0080 0DD5> D 8 9 1 01 11 21 31 4 D 1 5 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 <When reset: H'00> D Bit Name Function R W

8 FP8 (F/F8 protect) 0: Enables write to F/F output bit

9 FP9 (F/F9 protect) 1: Disables write to F/F output bit

10 FP10 (F/F10 protect)

11 FP11 (F/F11 protect)

12 FP12 (F/F12 protect)

13 FP13 (F/F13 protect)

14 FP14 (F/F14 protect)

15 FP15 (F/F15 protect)

These registers enable/disable write to the respective output flip-flops (F/Fs). When disabled against write, writing to the F/F Data Register has no effect.

10-23 Rev.1.0 I F/F Data Register 0 (FFD0) <Address: H'0080 0CD7> D 8 9 1 01 11 21 31 4 D 1 5 FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 <When reset: H'00> D Bit Name Function R W

8 FD0 (F/F0 output data) 0: F/F output data = 0

9 FD1 (F/F1 output data) 1: F/F output data=1

10 FD2 (F/F2 output data)

11 FD3 (F/F3 output data)

12 FD4 (F/F4 output data)

13 FD5 (F/F5 output data)

14 FD6 (F/F6 output data)

15 FD7 (F/F7 output data)

I F/F Data Register 1 (FFD1) <Address: H'0080 0DD7> D 8 9 1 01 11 21 31 4 D 1 5 FD8 FD9 FD10 FD11 FD12 FD13 FD14 FD15 <When reset: H'00> D Bit Name Function R W

8 FD8 (F/F8 output data) 0: F/F output data = 0

9 FD9 (F/F9 output data) 1: F/F output data=1

10 FD10 (F/F10 output data)

11 FD11 (F/F11 output data)

12 FD12 (F/F12 output data)

13 FD13 (F/F13 output data)

14 FD14 (F/F14 output data)

15 FD15 (F/F15 output data)

These registers set the output data in the respective output flip-flops (F/Fs). Although the F/F output normally varies with timer output, any F/F output (0 or 1) can be produced by setting the desired data in these registers. The F/F Data Registers can only be accessed for setting said data when the corresponding F/F Protect Registers described in the preceding page are enabled. INPUT/OUTPUT TIMERS

10-24 Rev.1.0

10.2.5 Interrupt Control Unit

The interrupt control unit controls the interrupt signals output to the Interrupt Controller by each timer. There are following 11 timer interrupt control registers for each timer.

• TIN Interrupt Control Register 0 (TINIR0)
• TIN Interrupt Control Register 1 (TINIR1)
• TIN Interrupt Control Register 2 (TINIR2)
• TIN Interrupt Control Register 3 (TINIR3)
• TIN Interrupt Control Register 4 (TINIR4)
• TIN Interrupt Control Register 5 (TINIR5)
• TIN Interrupt Control Register 8 (TINIR8)
• TOM0 Interrupt Mask Register (TOM0IMA)
• TOM0 Interrupt Status Register (TOM0IST)
• TOM1 Interrupt Mask Register (TOM1IMA)
• TOM1 Interrupt Status Register (TOM1IST) For interrupts which have only one interrupt source for one interrupt vector table, no interrupt control registers are provided within the timer, and the interrupt status flags are automatically managed within the interrupt controller. (For details, see Chapter 5, "Interrupt Controller.")
• TMS0 TMS0 Output Interrupt (IRQ19)
• TID0 TID0 Output Interrupt (IRQ18)
• TID1 TID1 Output Interrupt (IRQ17) INPUT/OUTPUT TIMERS

10-25 Rev.1.0 For interrupts which have two or more interrupt sources for one interrupt vector table, the interrupt control registers are used to control their interrupt requests and determine interrupt inputs. For this reason, the status flags in the Interrupt Controller only serve as the bits to determine whether interrupts are requested from the sources that have been enabled for interrupt and cannot be accessed for write. (1) Interrupt request status bit The status bit is used to determine whether an interrupt is requested. When an interrupt request occurs, this bit is set in hardware, and cannot be set in software. The status bit is cleared by writing 0. Writing 1 has no effect, the bit retains its status. Because the status bit is unaffected by the interrupt mask bit, it can also be used to check operation of the peripheral function. During interrupt processing, make sure that among the grouped interrupt flags, only the flag which has had its associated interrupt serviced is cleared. If any flag for which the interrupt has not been serviced is cleared, unexecuted interrupt requests are also cleared. (2) Interrupt mask bit This flag is used to disable an unnecessary interrupt among the grouped interrupt requests. Setting this bit to 0 enables the interrupt; setting this bit to 1 disables the interrupt. Figure 10.2.5 Interrupt Status Register and Mask Register INPUT/OUTPUT TIMERS Data=0

10-26 Rev.1.0 b4 5 6 b7 Interrupt status flag Initial state b6 event occurs Interrupt request b4 event occurs Only b6 is cleared b4 retains data b4 5 6 b7 1101 Write to interrupt status Example for clearing interrupt status 000 0 001 0 011 0 010 0 Figure 10.2.6 Example for Clearing Interrupt Status INPUT/OUTPUT TIMERS

10-27 Rev.1.0 The table below shows the relationship between the interrupt signals generated by the input/output timers and the inputs to the Interrupt Controller. Table 10.2.2 Interrupt Signals Generated by Timers Signal Name Generating Source Interrupt Input Source to ICU (Note1)Number of Input Sources IRQ20 TOM1_0 - TOM1_7 TOM1 output interrupt 8 IRQ21 TOM0_0 - TOM0_7 TOM0 output interrupt 8 IRQ22 TIN18, TIN19 Timer input interrupt 0 3 IRQ23 TIN16, TIN17 Timer input interrupt 1 3 IRQ24 TIN22, TIN23 Timer input interrupt 2 3 IRQ25 TIN20, TIN21 Timer input interrupt 3 3 IRQ27 TIN10, TIN11 Timer input interrupt 4 2 IRQ28 TIN8, TIN9 Timer input interrupt 5 2 IRQ30 PWMOFF0, PWMOFF1 PWM off input interrupt 2 Note 1: For details, see Chapter 5, "Interrupt Controller (ICU).") Note 2: TMS0, TID0, and TID1 have only one interrupt source in the respective interrupt groups. Therefore, the timer interrupt control registers for these interrupts do not include the status and mask registers. (These interrupts are controlled directly by the Interrupt Controller.) INPUT/OUTPUT TIMERS

10-28 Rev.1.0 I TIN Interrupt Status Register 0 (TINIST0) <Address: H'0080 0840> D 0 123456 D 7 TIN21IS TIN20IS1 TIN20IS <When reset: H'00> D Bit Name Function R W 0-4 No functions assigned 0 –

5 TIN21IS (TIN21 interrupt status) 0: Interrupt not requested

6 TIN20IS1 1: Interrupt requested

(TML measure 2 input detection interrupt status)

7 TIN20IS (TIN20 interrupt status)

W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. INPUT/OUTPUT TIMERS I TIN Interrupt Mask Register 0 (TINIMA0) <Address: H'0080 0841> D 8 9 1 01 11 21 31 4 D 1 5 TIN21IM TIN20IM1 TIN20IM <When reset: H'00> D Bit Name Function R W 8-12 No functions assigned 0 –

13 TIN21IM (TIN21 interrupt mask) 0: Enables interrupt request

14 TIN20IM1 1: Masks (disables) interrupt request

(TML measure 2 input detection interrupt mask)

15 TIN20IM (TIN20 interrupt mask)

10-29 Rev.1.0 Timer input interrupt 3 IRQ25 Data bus TIN21IS F/F TIN21IM F/Fb13 TIN20IS1 F/F TIN20IM1 F/Fb14 b7 TIN20IS F/F TIN20IM F/Fb15 (Level) 3-source inputs TIN21edge TIN20edge TIN20edge TINIMA0 <H'0080 0841> TINIST0 <H'0080 0840> Figure 10.2.7 Block Diagram of Timer Input Interrupt 3 INPUT/OUTPUT TIMERS

10-30 Rev.1.0 I TIN Interrupt Status Register 1 (TINIST1) <Address: H'0080 0842> D 0 123456 D 7 TIN23IS TIN22IS1 TIN22IS <When reset: H'00> D Bit Name Function R W

1 TIN23IS (TIN23 interrupt status) 0: Interrupt not requested

2 TIN22IS1 1: Interrupt requested

(TML measure 0 input detection interrupt status)

3 TIN22IS (TIN22 interrupt status)

4-7 No functions assigned 0 – W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. INPUT/OUTPUT TIMERS I TIN Interrupt Mask Register 1 (TINIMA1) <Address: H'0080 0843> <When reset: H'00> D Bit Name Function R W

8 No functions assigned 0 –

9 TIN23IM (TIN23 interrupt mask) 0: Enables interrupt request

10 TIN22IM1 1: Masks (disables) interrupt request

(TML measure 0 input detection interrupt mask)

11 TIN22IM (TIN22 interrupt mask)

12-15 No functions assigned 0 – D 8 9 1 01 11 21 31 4 D 1 5 TIN23IM TIN22IM1 TIN22IM

10-31 Rev.1.0 Timer input interrupt 2 IRQ24 Data bus TIN23IS F/F TIN21IM F/Fb9 TIN22IS1 F/F TIN22IM1 F/Fb10 b3 TIN22IS F/F TIN22IM F/Fb11 (Level) 3-source inputs TIN23edge TIN22edge TIN22edge TINIMA1 <H'0080 0843> TINIST1 <H'0080 0842> Figure 10.2.8 Block Diagram of Timer Input Interrupt 2 INPUT/OUTPUT TIMERS

10-32 Rev.1.0 I TIN Interrupt Status Register 2 (TINIST2) <Address: H'0080 0844> <When reset: H'00> D Bit Name Function R W 0-4 No functions assigned 0 –

5 TIN17IS (TIN17 interrupt status) 0: Interrupt not requested

6 TIN16IS1 1: Interrupt requested

(TMS measure 2 input detection interrupt status)

7 TIN16IS (TIN16 interrupt status)

W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. D 0 123456 D 7 TIN17IS TIN16IS1 TIN16IS INPUT/OUTPUT TIMERS I TIN Interrupt Mask Register 2 (TINIMA2) <Address: H'0080 0845> <When reset: H'00> D Bit Name Function R W 8-12 No functions assigned 0 –

13 TIN17IM (TIN17 interrupt mask) 0: Enables interrupt request

14 TIN16IM1 1: Masks (disables) interrupt request

(TMS measure 2 input detection interrupt mask)

15 TIN16IM (TIN16 interrupt mask)

D 8 9 1 01 11 21 31 4 D 1 5 TIN17IM TIN16IM1 TIN16IM

10-33 Rev.1.0 Timer input interrupt 1 IRQ23 Data bus TIN17IS F/F TIN17IM F/Fb13 TIN16IS1 F/F TIN16IM1 F/Fb14 b7 TIN16IS F/F TIN16IM F/Fb15 (Level) 3-source inputs TIN17edge TIN16edge TIN16edge TINIMA2 <H'0080 0845> TINIST2 <H'0080 0844> Figure 10.2.9 Block Diagram of Timer Input Interrupt 1 INPUT/OUTPUT TIMERS

10-34 Rev.1.0 I TIN Interrupt Status Register 3 (TINIST3) <Address: H'0080 0846> <When reset: H'00> D Bit Name Function R W

1 TIN19IS (TIN19 interrupt status) 0: Interrupt not requested

2 TIN18IS1 1: Interrupt requested

(TMS measure 0 input detection interrupt status)

3 TIN18IS (TIN22 interrupt status)

4-7 No functions assigned 0 – W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. D 0 123456 D 7 TIN19IS TIN18IS1 TIN18IS INPUT/OUTPUT TIMERS I TIN Interrupt Mask Register 3 (TINIMA3) <Address: H'0080 0847> <When reset: H'00> D Bit Name Function R W

9 TIN19IM (TIN19 interrupt mask) 0: Enables interrupt request

10 TIN18IM1 1: Masks (disables) interrupt request

(TMS measure 0 input detection interrupt mask)

11 TIN18IM (TIN18 interrupt mask)

12-15 No functions assigned 0 – D 8 9 1 01 11 21 31 4 D 1 5 TIN19IM TIN18IM1 TIN18IM

10-35 Rev.1.0 Figure 10.2.10 Block Diagram of Timer Input Interrupt 0 Timer input interrupt 0 IRQ22 Data bus TIN19IS F/F TIN19IM F/Fb9 TIN18IS1 F/F TIN18IM1 F/Fb10 TIN18IS F/F TIN18IM F/Fb11 (Level) 3-source inputs TIN19edge TIN18edge TIN18edge TINIMA3 <H'0080 0847> TINIST3 <H'0080 0846> INPUT/OUTPUT TIMERS

10-36 Rev.1.0 I TIN Interrupt Status Register 4 (TINIST4) <Address: H'0080 0848> <When reset: H'00> D Bit Name Function R W 0-5 No functions assigned 0 –

6 TIN9IS (TIN9 interrupt status) 0: Int errupt not requested

7 TIN8IS (TIN8 interrupt status) 1: Interrupt requested

W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. D 0 123456 D 7 TIN9IS TIN8IS INPUT/OUTPUT TIMERS Figure 10.2.11 Block Diagram of Timer Input Interrupt 5 I TIN Interrupt Mask Register 4 (TINIMA4) <Address: H'0080 0849> Timer input interrupt 5 IRQ28 Data bus TIN9IS F/F TIN9IM F/Fb14 TIN8IS F/F TIN8IM F/Fb15 (Level) 2-source inputs TIN9edge TIN8edge TINIMA4 <H'0080 0849> TINIST4 <H'0080 0848> <When reset: H'00> D Bit Name Function R W 8-13 No functions assigned 0 –

6 TIN9IM (TIN9 interrupt mask) 0: Enables interrupt request

7 TIN8IM (TIN8 interrupt mask) 1: Masks (disables) interrupt request

D 8 9 1 01 11 21 31 4 D 1 5 TIN9IM TIN8IM

10-37 Rev.1.0 I TIN Interrupt Status Register 5 (TINIST5) <Address: H'0080 084A> <When reset: H'00> D Bit Name Function R W 0, 1 No functions assigned 0 –

2 TIN11IS (TIN11 interrupt status) 0: Interrupt not requested

3 TIN10IS (TIN10 interrupt status) 1: Interrupt requested

4-7 No functions assigned 0 – W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. D 0 123456 D 7 TIN11IS TIN10IS Figure 10.2.12 Block Diagram of Timer Input Interrupt 4 INPUT/OUTPUT TIMERS (Level) 2-source inputs TIN11edge TIN10edge TINIMA5 <H’0080 084B> TINIST5 <H’0080 084A> I TIN Interrupt Mask Register 5 (TINIMA5) <Address: H'0080 084B> <When reset: H'00> D Bit Name Function R W 8, 9 No functions assigned 0 –

10 TIN11IM (TIN11 interrupt mask) 0: Enables interrupt request

11 TIN10IM (TIN10 interrupt mask) 1: Masks (disables) interrupt request

12-15 No functions assigned 0 – D 8 9 1 01 11 21 31 4 D 1 5 TIN11IM TIN10IM

10-38 Rev.1.0 I TIN Interrupt Status Register 8 (TINIST8) <Address: H'0080 0850> D 0 123456 D 7 PWOFIS1 PWOFIS0 <When reset: H'00> D Bit Name Function R W 0-5 No functions assigned 0 –

6 PWOFIS1 0: Interrupt not requested

(PMW output disable interrupt status 1) 1: Interrupt requested

7 PWOFIS0

(PMW output disable interrupt status 0) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. <When reset: H'00> D Bit Name Function R W 8-13 No functions assigned 0 –

6 PWOFIM1 0: Enables interrupt request

(PMW output disable interrupt mask 1) 1: Masks (disables) interrupt request

7 PWOFIM0

(PMW output disable interrupt mask 0) D 8 9 1 01 11 21 31 4 D 1 5 PWOFIM1 PWOFIM0 I TIN Interrupt Mask Register 8 (TINIMA8) <Address: H'0080 0851> INPUT/OUTPUT TIMERS Figure 10.2.13 Block Diagram of PWM Off Input Interrupt PWM off input interrupt IRQ30 Data bus PWOFIS1 F/F PWOFIM1 F/Fb14 PWOFIS0 F/F PWOFIM0 F/Fb15 (Level) 2-source inputs PWMOFF1edge TINIMA8 <H'0080 0851> TINIST8 <H'0080 0850> PWMOFF0edge

10-39 Rev.1.0 I TOM0 Interrupt Mask Register (TOM0IMA) <Address: H'0080 0CD2> D 0 123456 D 7 TOM07IMA TOM06IMA TOM05IMA TOM04IMA TOM03IMA TOM02IMA TOM01IMA TOM00IMA <When reset: H'00> D Bit Name Function R W

0 TOM07IMA (TOM0_7 interrupt mask) 0: Enables interrupt request

1 TOM06IMA (TOM0_6 interrupt mask) 1: Masks (disables) interrupt request

2 TOM05IMA (TOM0_5 interrupt mask)

3 TOM04IMA (TOM0_4 interrupt mask)

4 TOM03IMA (TOM0_3 interrupt mask)

5 TOM02IMA (TOM0_2 interrupt mask)

6 TOM01IMA (TOM0_1 interrupt mask)

7 TOM00IMA (TOM0_0 interrupt mask)

<When reset: H'00> D Bit Name Function R W

8 TOM07IST (TOM0_7 interrupt status) 0: Interrupt not requested

9 TOM06IST (TOM0_6 interrupt status) 1: Interrupt requested

10 TOM05IST (TOM0_5 interrupt status)

11 TOM04IST (TOM0_4 interrupt status)

12 TOM03IST (TOM0_3 interrupt status)

13 TOM02IST (TOM0_2 interrupt status)

14 TOM01IST (TOM0_1 interrupt status)

15 TOM00IST (TOM0_0 interrupt status)

W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. I TOM0 Interrupt Status Register (TOM0IST) <Address: H'0080 0CD3> D 8 9 1 01 11 21 31 4 D 1 5 TOM07IST TOM06IST TOM05IST TOM04IST TOM03IST TOM02IST TOM01IST TOM00IST

10-40 Rev.1.0 Data bus TOM07IST F/F TOM07IMA F/Fb0 TOM06IST F/F TOM06IMA F/Fb1 b10 TOM05IST F/F TOM05IMA F/Fb2 b11 TOM04IST F/F TOM04IMA F/Fb3 b12 TOM03IST F/F TOM03IMA F/Fb4 TOM0IMA <H'0080 0CD2> TOM0IST <H'0080 0CD3> TOM07udf TOM06udf TOM05udf TOM04udf TOM03udf b13 TOM02IST F/F TOM02IMA F/Fb5 b14 TOM01IST F/F TOM01IMA F/Fb6 b15 TOM00IST F/F F/Fb7 TOM02udf TOM01udf TOM00udf TOM00IMA TOM0 output interrupt IRQ21(Level) Figure 10.2.14 Block Diagram of TOM0 Output Interrupt INPUT/OUTPUT TIMERS

10-41 Rev.1.0 I TOM1 Interrupt Mask Register (TOM1IMA) <Address: H'0080 0DD2> <When reset: H'00> D Bit Name Function R W

0 TOM17IMA (TOM1_7 interrupt mask) 0: Enables interrupt request

1 TOM16IMA (TOM1_6 interrupt mask) 1: Masks (disables) interrupt request

2 TOM15IMA (TOM1_5 interrupt mask)

3 TOM14IMA (TOM1_4 interrupt mask)

4 TOM13IMA (TOM1_3 interrupt mask)

5 TOM12IMA (TOM1_2 interrupt mask)

6 TOM11IMA (TOM1_1 interrupt mask)

7 TOM10IMA (TOM1_0 interrupt mask)

<When reset: H'00> D Bit Name Function R W

8 TOM17IST (TOM1_7 interrupt status) 0: Interrupt not requested

9 TOM16IST (TOM1_6 interrupt status) 1: Interrupt requested

10 TOM15IST (TOM1_5 interrupt status)

11 TOM14IST (TOM1_4 interrupt status)

12 TOM13IST (TOM1_3 interrupt status)

13 TOM12IST (TOM1_2 interrupt status)

14 TOM11IST (TOM1_1 interrupt status)

15 TOM10IST (TOM1_0 interrupt status)

W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. I TOM1 Interrupt Status Register (TOM1IST) <Address: H'0080 0DD3> D 0 123456 D 7 TOM17IMA TOM16IMA TOM15IMA TOM14IMA TOM13IMA TOM12IMA TOM11IMA TOM10IMA D 8 9 1 01 11 21 31 4 D 1 5 TOM17IST TOM16IST TOM15IST TOM14IST TOM13IST TOM12IST TOM11IST TOM10IST INPUT/OUTPUT TIMERS

10-42 Rev.1.0 Figure 10.2.15 Block Diagram of TOM1 Output Interrupt Data bus TOM17IST F/F TOM17IMA F/Fb0 TOM16IST F/F TOM16IMA F/Fb1 b10 TOM15IST F/F TOM15IMA F/Fb2 b11 TOM14IST F/F TOM14IMA F/Fb3 b12 TOM13IST F/F TOM13IMA F/Fb4 TOM1IMA <H'0080 0DD2> TOM1IST <H'0080 0DD3> TOM17udf TOM16udf TOM15udf TOM14udf TOM13udf b13 TOM12IST F/F TOM12IMA F/Fb5 b14 TOM11IST F/F TOM11IMA F/Fb6 b15 TOM10IST F/F F/Fb7 TOM12udf TOM11udf TOM10udf TOM10IMA TOM1 output interrupt IRQ20(Level) INPUT/OUTPUT TIMERS

10-43 Rev.1.0

10.3 TMS (Input Related 16-bit Timers)

10.3.1 Outline of the TMS

TMS (Timer Measure Small) consists of input related 16-bit timers allowing input pulses on four channels to be measured. Specifications of the TMS are listed below. A block diagram of the TMS is shown in the next page. INPUT/OUTPUT TIMERS Table 10.3.1 Specifications of TMS (Input Related 16-bit Timers) Item Specification Number of channels 4 channels Counter 16-bit up-counter (1 pc.) Measure register 6-bit measure register (4 pcs.) and 16-bit old measure register (4 pcs.) Timer start Started by writing to the enable bit in software Interrupt generation Can be generated by counter overflow

10.3.2 Functional Outline of the TMS

In TMS, when the timer is activated (by writing to the enable bit in software), the counter starts operating. The counter is a 16-bit up-counter. When a measure signal is asserted by means of external input, the value of each measure register is latched into each old measure register, while the counter value is latched into each measure register. Counting is stopped immediately by writing to the enable bit in software to disable counting. A TIN and a TMS interrupt can be generated by input of an external measure signal and by occurrence a counter overflow, respectively.

10-44 Rev.1.0 clk TMS 0 ovf cap3 cap2 cap1 cap0 S S PRS0 TIN16S TIN17S IRQ23 TIN16 TIN17 TIN18STIN18 TIN19STIN19 IRQ23 IRQ22 IRQ22 IRQ19 Measure Register 3Counter (16-bit) 1/2 internal peripheral clock Old Measure Register 3 Measure Register 2 Old Measure Register 2 Measure Register 1 Old Measure Register 1 Measure Register 0 Old Measure Register 0 TIN16S1 IRQ23 TIN18S1 IRQ22 To A-D0,1 and PD module DRQ13 DRQ14 DRQ15 DRQ16 To TML0 Figure 10.3.1 Block Diagram of TMS (Input Related 16-bit Timers) INPUT/OUTPUT TIMERS

10-45 Rev.1.0

10.3.3 TMS Related Register Map

A TMS related register map is shown below. Figure 10.3.2 TMS Related Register Map INPUT/OUTPUT TIMERS H'0080 08E0 Address D0 D7 +0 address +1 address D8 D15 H'0080 08E2 H'0080 08E4 H'0080 08E6 TMS0Measure 2 Register (TMS0MR2) TMS0Measure 1 Register (TMS0MR1) H'0080 08EA Prescaler Register 0 (PRS0) H'0080 08E8 TMS0 Control Register (TMS0CR) TMS0 Measure 3 Register (TMS0MR3) TMS0Measure 0 Register (TMS0MR0) H'0080 08F2 H'0080 08F4 H'0080 08F6 TMS0 Old Measure 2 Register (TMS0OLDMR2) TMS0 Old Measure 1 Register (TMS0OLDMR1) H'0080 08F8 TMS0 Old Measure 3 Register (TMS0OLDMR3) TMS0 Old Measure 0 Register (TMS0OLDMR0) Note: The registers enclosed in the thick frames must always be accessed in halfwords TMS0 Counter (TMS0CT) Blank ares are reserved for future use.

10-46 Rev.1.0

10.3.4 TMS Control Register

The TMS control register is used to select a TMS0 input event and controls TMS and TML counter startup. Following TMS control registers are included.

• TMS0 Control Register (TMS0CR) INPUT/OUTPUT TIMERS

I TMS0 Control Register (TMS0CR) <Address: H'0080 08EA> <When reset: H'00> D Bit Name Function R W

0 TMS0SS0 0: External input TIN19

(Selects TMS0 measure 0 source) 1: External input TIN18

1 No functions assigned 0 –

2 TMS0SS2 0: External input TIN17

(Selects TMS0 measure 2 source) 1: External input TIN16 3-6 No functions assigned 0 –

7 TMSLCEN 0: Stops counting

(TMS/TML count enable) 1: Starts counting D 0 123456 D 7 TMSLCEN TMS0 TMS0 SS0 SS2

10-47 Rev.1.0

10.3.5 TMS Counter (TMS0CT)

I TMS0 Counter (TMS0CT) <Address: H'0080 08E0> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TMS0CT <When reset: indeterminate> D Bit Name Function R W 0-15 TMS0CT 16-bit counter value Note: This register must always be accessed in halfwords. The TMS counter is a 16-bit up-counter, which starts counting when the timer is activated (by writing to the enable bit in software). The counter can be read out on-the-fly. INPUT/OUTPUT TIMERS

10-48 Rev.1.0

10.3.6 TMS Measure Registers (TMS0MR3-0)

I TMS0 Measure 3 Register (TMS0MR3) <Address: H'0080 08E2> I TMS0 Measure 2 Register (TMS0MR2) <Address: H'0080 08E4> I TMS0 Measure 1 Register (TMS0MR1) <Address: H'0080 08E6> I TMS0 Measure 0 Register (TMS0MR0) <Address: H'0080 08E8> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TMS0MR3-0 <When reset: indeterminate> D Bit Name Function R W 0-15 TMS0MR3-TMS0MR0 16-bit counter value – Note 1: This register is a read-only register. Note 2: This register can be accessed in either bytes or halfwords. The TMS measure registers are used to capture the content of the counter upon event input. The TMS measure registers are a read-only register. INPUT/OUTPUT TIMERS

10-49 Rev.1.0

10.3.7 TMS Old Measure Registers (TMS0OLDMR3-0)

I TMS0 Old Measure 3 Register (TMS0OLDMR3) <Address: H'0080 08F2> I TMS0 Old Measure 2 Register (TMS0OLDMR2) <Address: H'0080 08F4> I TMS0 Old Measure 1 Register (TMS0OLDMR1) <Address: H'0080 08F6> I TMS0 Old Measure 0 Register (TMS0OLDMR0) <Address: H'0080 08F8> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TMS0OLDMR3-0 <When reset: indeterminate> D Bit Name Function R W 0-15 TMS0OLDMR3-TMS0OLDMR0 TMS0 measure register value – Note 1: This register is a read-only register. Note 2: This register can be accessed in either bytes or halfwords. The TMS old measure registers are used to capture the contents of the respective TMS measure registers upon event input. The TMS old measure registers are a read-only register. INPUT/OUTPUT TIMERS

10-50 Rev.1.0

10.3.8 Operation of TMS Measure Input

(1) Outline of TMS measure input For TMS measure input, the counter first starts counting up when the timer is activated (by writing to the enable bit in software). Each time there is event input to TMS while the timer is operating, the values of the measure registers 0-3 are latched into the corresponding old measure registers 0-3 and the counter value is latched into the measure registers 0-3. The timer is stopped immediately by writing to the enable bit to disable counting. A TIN interrupt can be generated when a measure signal is entered from an external source. A TMS interrupt can be generated when the counter overflows. Figure 10.3.3 Typical Operation of TMS Measure Input INPUT/OUTPUT TIMERS H'FFFF H'0000 Enabled (by writing to the enable bit) Measure event 1 occurs Indeterminate Enable bit Note: Detailed timing information is not shown in this diagram. Measure 0 register H'8000 Overflow occurs TIN18 interrupt H'C000 IndeterminateMeasure 1 register TIN19 interrupt Measure event 0 occurs TMS interrupt by overflow H'C000 H'6000 H'D000 Measure event 1 occurs Measure event 0 occurs H'6000 H'D000 H'8000 Indeterminate value IndeterminateOld measure 0 register H'8000Indeterminate IndeterminateOld measure 1 register H'C000Indeterminate

10-51 Rev.1.0 (2) Precautions on using TMS measure input The following describes precautions to be observed when using TMS measure input.

• If measure event input and write to the counter occur simultaneously in the same clock cycle, the write value is set in the counter and also latched into the measure register. INPUT/OUTPUT TIMERS

10-52 Rev.1.0

10.4 TML (Input Related 32-bit Timers)

10.4.1 Outline of the TML

TML (Timer Measure Large) consists of input related 32-bit timers allowing input pulses on four channels to be measured. Specifications of the TML are listed below. A block diagram of the TML is shown in the next page. Table 10.4.1 Specifications of TML (Input Related 32-bit Timers) Item Specification Number of channels 4 channels Counter 32-bit up-counter Measure register 32-bit measure register (4 pcs.) Timer start Started by writing to the enable bit in software INPUT/OUTPUT TIMERS

10-53 Rev.1.0 clk TML0 cap3 cap2 cap1 cap0 S S PRS1 TIN20S TIN21S IRQ25 TIN20 TIN21 TIN22STIN22 TIN23STIN23 IRQ25 IRQ24 IRQ24 Measure register 3Counter (32-bit) 1/2 internal peripheral clock Old measure register 3 Measure register 2 Old measure register 2 Measure register 1 Old measure register 1 Measure register 0 Old measure register 0 TIN20S1 IRQ25 TIN22S1 IRQ24 DRQ17 DRQ18 DRQ19 DRQ20 S PRS0 To TMS0 Figure 10.4.1 Block Diagram of TML (Input Related 32-bit Timers)

10.4.2 Functional Outline of the TML

The TML is designed in such a way that when the timer is activated (by writing to the enable bit in software), the counter starts operating. The counter is a 32-bit up-counter. When a measure event signal is asserted by means of external input, the content of each measure register (32-bit) is latched into each old measure register (32-bit), while the counter value is latched into each measure register (32-bit). Counting is stopped immediately by writing to the enable bit in software to disable counting. A TIN interrupt can be generated by input of an external measure signal. The TML does not have a counter overflow interrupt. INPUT/OUTPUT TIMERS Note: The enable bit of TML timer is shared with enable bit of TMS timer. For details, refer to section 10.3.4 "TMS Control Register".

10-54 Rev.1.0

10.4.3 TML Related Register Map

A TML related register map is shown below. Figure 10.4.2 TML Related Register Map INPUT/OUTPUT TIMERS H'0080 0880 Address D0 D7 +0 address +1 address D8 D15 H'0080 0882 TML0 Counter, High (TML0CTH) Prescaler Register 1 (PRS1)H'0080 088A TML0 Counter, Low (TML0CTL) H'0080 0890 H'0080 0892 H'0080 0894 H'0080 0896 TML0 Measure 3 Register, Low (TML0MR3L) H'0080 0898 H'0080 089A H'0080 089C H'0080 089E TML0 Measure 3 Register, High (TML0MR3H) TML0 Measure 2 Register, Low (TML0MR2L) TML0 Measure 2 Register, High (TML0MR2H) TML0 Measure 1 Register, Low (TML0MR1L) TML0 Measure 1 Register, High (TML0MR1H) TML0 Measure 0 Register, Low (TML0MR0L) TML0 Measure 0 Register, High (TML0MR0H) Note: The registers enclosed in the thick frames must always be accessed in words. H'0080 08A0 H'0080 08A2 H'0080 08A4 H'0080 08A6 TML0 Old Measure 3 Register, Low (TML0OLDMR3L) H'0080 08A8 H'0080 08AA H'0080 08AC H'0080 08AE TML0 Old Measure 3 Register, High (TML0OLDMR3H) TML0 Old Measure 2 Register, Low (TML0OLDMR2L) TML0 Old Measure 2 Register, High (TML0OLDMR2H) TML0 Old Measure 1 Register, Low (TML0OLDMR1L) TML0 Old Measure 1 Register, High (TML0OLDMR1H) TML0 Old Measure 0 Register, Low (TML0OLDMR0L) TML0 Old Measure 0 Register, High (TML0OLDMR0H) Blank ares are reserved for future use. TML0 Control Register (TML0CR)

10-55 Rev.1.0

10.4.4 TML Control Register

I TML0 Control Register (TML0CR) <Address: H'0080 088A> D 8 9 1 01 11 21 31 4 D 1 5 TML0SS0 TML0SS2 TML0CKS <When reset: H'00> D Bit Name Function R W

8 TML0SS0 0: External input TIN23

(Selects TML0 measure 0 source) 1: External input TIN22

10 TML0SS2 0: External input TIN21

(Selects TML0 measure 2 source) 1: External input TIN20 11-14 No functions assigned 0 –

15 TML0CKS 0: Prescaler 1 (PRS1)

(Selects TML0 clock source) 1: Prescaler 0 (PRS0) The TML0 Control Register is used to select TML0 input event and the count clock. Note: The counter can be written to normally only when the selected clock source is a 1/2 internal peripheral clock. When using any other clock source, the counter cannot be written correctly. Under this condition, do not write to the counter. INPUT/OUTPUT TIMERS

10-56 Rev.1.0

10.4.5 TML Counters

I TML0 Counter, High (TML0CTH) <Address: H'0080 0880> I TML0 Counter, Low (TML0CTL) <Address: H'0080 0882> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML0CTH (16 high-order bits) D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML0CTL (16 low-order bits) <When reset: indeterminate> D Bit Name Function R W 0-15 TML0CTH 32-bit counter value (16 high-order bits) TML0CTL 32-bit counter value (16 low-order bits) Note: This register must always be accessed words (32 bits) beginning with the TML0CTH address. The TML0 Counter is a 32-bit up-counter, which starts counting when the timer is activated (by writing to the enable bit in software). The TML0CTH and TML0CTL registers accommodate the 16 high-order bits and the 16 low-order bits of the 32-bit counter, respectively. The counter can be read out on-the-fly. INPUT/OUTPUT TIMERS

10-57 Rev.1.0

10.4.6 TML Measure Registers

I TML0 Measure 3 Register (TML0MR3H) <Address: H'0080 0890> I TML0 Measure 3 Register (TML0MR3L) <Address: H'0080 0892> I TML0 Measure 2 Register (TML0MR2H) <Address: H'0080 0894> I TML0 Measure 2 Register (TML0MR2L) <Address: H'0080 0896> I TML0 Measure 1 Register (TML0MR1H) <Address: H'0080 0898> I TML0 Measure 1 Register (TML0MR1L) <Address: H'0080 089A> I TML0 Measure 0 Register (TML0MR0H) <Address: H'0080 089C> I TML0 Measure 0 Register (TML0MR0L) <Address: H'0080 089E> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML0MR3H-TML0MR0H (16 high-order bits) D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML0MR3L-TML0MR0L (16 low-order bits) <When reset: indeterminate> D Bit Name Function R W 0-15 TML0MR3H-0H 32-bit measure register value (16 high-order bits) – TML0MR3L-0L 32-bit measure register value (16 low-order bits) Note 1: These registers are a read-only register. Note 2: These registers must always be accessed words (32 bits) beginning with each word boundary. The TML0 Measure Registers are used to capture the content of the counter upon event input. The TML0 Measure Registers each are configured with 32 bits, with the TML0MR3H-0H and the TML0MR3L-0L accommodating the 16 high-order bits and the 16 low-order bits, respectively. The TML0 Measure Registers are a read-only register. These registers must always be accessed in words beginning with each word boundary. INPUT/OUTPUT TIMERS

10-58 Rev.1.0

10.4.7 TML Old Measure Registers

I TML0 Old Measure 3 Register (TML0OLDMR3H) <Address: H'0080 08A0> I TML0 Old Measure 3 Register (TML0OLDMR3L) <Address: H'0080 08A2> I TML0 Old Measure 2 Register (TML0OLDMR2H) <Address: H'0080 08A4> I TML0 Old Measure 2 Register (TML0OLDMR2L) <Address: H'0080 08A6> I TML0 Old Measure 1 Register (TML0OLDMR1H) <Address: H'0080 08A8> I TML0 Old Measure 1 Register (TML0OLDMR1L) <Address: H'0080 08AA> I TML0 Old Measure 0 Register (TML0OLDMR0H) <Address: H'0080 08AC> I TML0 Old Measure 0 Register (TML0OLDMR0L) <Address: H'0080 08AE> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML0OLDMR3H-TML0OLDMR0H (16 high-order bits) D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TML0OLDMR3L-TML0OLDMR0L (16 low-order bits) <When reset: indeterminate> D Bit Name Function R W 0-15 TML0OLDMR3H-0H 32-bit old measure register value (16 high-order bits)– TML0OLDMR3L-0L 32-bit old measure register value (16 low-order bits) Note 1: These registers are a read-only register. Note 2: These registers must always be accessed words (32 bits) beginning with each word boundary. The TML0 Old Measure Registers are used to capture the contents of the corresponding TML0 Measure Registers upon event input. The TML0 Old Measure Registers each are configured with 32 bits, with the TML0OLDMR3H-0H and the TML0OLDMR3L-0L accommodating the 16 high- order bits and the 16 low-order bits, respectively. The TML0 Old Measure Registers are a read-only register. These registers must always be accessed in words beginning with each word boundary. INPUT/OUTPUT TIMERS

10-59 Rev.1.0

10.4.8 Operation of TML Measure Input

(1) Outline of TML measure input For TML measure input, the counter starts counting up when the timer is activated (by writing to the enable bit in software). Each time there is event input to the measure registers 0-3, the counter value is latched into the measure registers. The timer is stopped immediately by writing to the enable bit to disable counting. A TIN interrupt can be generated by input of an external measure signal. (The TML does not have a counter overflow interrupt.) Figure 10.4.3 Typical Operation of TML Measure Input INPUT/OUTPUT TIMERS Counter (32-bit) H'FFFF FFFF H'0000 0000 Enabled (by writing to the enable bit) Measure event 1 occurs Indeterminate Enable bit Note: Detailed timing information is not shown in this diagram. Measure 0 register Overflow occurs TIN22 interrupt Indeterminate TIN23 interrupt by overflow Measure event 0 occurs H'8000 0000 H'C000 0000 H'8000 0000 H'C000 0000 H'6000 0000 H'D000 0000 H'6000 0000 H'D000 0000 Measure event 1 occurs Measure event 0 occurs Indeterminate value IndeterminateOld measure 0 register Measure 1 register Old measure 1 register H'8000 0000Indeterminate Indeterminate H'C000 0000Indeterminate

10-60 Rev.1.0 (2) Precautions on using TML measure input The following describes precautions to be observed when using TML measure input.

• If measure event input and write to the counter occur simultaneously in the same clock cycle, the write value is set in the counter, whereas the up-count value (before rewriting) is latched into the measure register.
• If the timer operates with any clock other than the 1/2 internal peripheral clock while clock bus 1 is selected for the count clock, the counter cannot be written to normally. Therefore, when operating with any clock other than the 1/2 internal peripheral clock, do not write to the counter.
• If the timer operates with any clock other than the 1/2 internal peripheral clock while clock bus 1 is selected for the count clock, the captured value is one that leads the actual counter value by one clock period. However, during the 1/2 internal peripheral clock interval from the count clock, this problem dose not occur and the counter value is captured at exact timing. The diagram below shows the relationship between counter operation and the data that can be captured. Figure 10.4.4 Mistimed Counter Value and Captured Value INPUT/OUTPUT TIMERS
• When using the 1/2 internal peripheral clock 1/2 internal peripheral clock Capture Counter BAC
• When using any clock other than the 1/2 internal peripheral clock 1/2 internal peripheral clock Count clock Capture BC D F

10-61 Rev.1.0

10.5 TID (Input Related 16-bit Timers)

10.5.1 Outline of the TID

TID (Timer Input Derivation) consists of input related 16-bit timers which can be operated in one of the following modes as selected in software:

• Fixed period count mode
• Event count mode
• Multiply-by-4 event count mode
• Up/down event count mode Specifications of the TID are listed below. A block diagram of the TID is shown in the next page. INPUT/OUTPUT TIMERS

Table 10.5.1 Specifications of TID (Input Related 16-bit Timers) Item Specification Number of channels 2 channels Counter 16-bit up/down-counter Reload register 16-bit reload register Timer start Started by writing to the enable bit in software Mode selection <Input mode>

• Fixed period count mode
• Event count mode
• Multiply-by-4 event count mode
• Up/down event count mode Interrupt generation Can be generated by counter overflow or underflow

10-62 Rev.1.0 Up/down-counter TID0 IRQ18 PRS2 TIN8 TIN9 S 1/2 internal peripheral clock Edge control CLK1 CLK2 TOM0_0-7 Reload register clk DRQ0 Up/down-counter TID1 IRQ17 PRS3 TIN10 TIN11 S 1/2 internal peripheral clock Edge control CLK1 CLK2 TOM1_0-7 Reload register clk DRQ1 To TOM0_0-7 EN and A-D0TRG control circuits To TOM1_0-7 EN control circuit To TOM0_0-7 EN and A-D0TRG control circuits To TOM1_0-7 EN control circuit TIN11S IRQ27 TIN10S IRQ27 TIN9S IRQ28 TIN8S IRQ28 Figure 10.5.1 Block Diagram of TID (Input Related 16-bit Timers) INPUT/OUTPUT TIMERS

10-63 Rev.1.0

10.5.2 TID Related Register Map

A TID related register map is shown below. Figure 10.5.2 TID Related Register Map INPUT/OUTPUT TIMERS H'0080 0C8C Address D0 D7 +0 address +1 addressD8 D15 H'0080 0C8E TID0 Counter (TID0CT) TID0 Control & Prescaler 2 Enable Register (TID0PRS2EN)H'0080 0CD0 Note: The registers enclosed in the thick frames must always be accessed in halfwords. TID0 Reload Register (TID0RL) Prescaler Register 2 (PRS2) H'0080 0D8C H'0080 0D8E TID1 Counter (TID1CT) TID1 Control & Prescaler 3 Enable Register (TID1PRS3EN)H'0080 0DD0 TID1 Reload Register (TID1RL) Prescaler Register 3 (PRS3) Blank ares are reserved for future use.

10-64 Rev.1.0

10.5.3 TID Control & Prescaler Enable Registers

I TID0 Control & Prescaler 2 Enable Register (TID0PRS2EN) <Address: H'0080 0CD1> D 8 9 1 01 11 21 31 4 D 1 5 TID0M TID0CEN TOM0ENS PRS2EN <When reset: H'00> D Bit Name Function R W 8-10 TID0M X0X: Fixed period count mode (Selects TID0 operation mode) X10: Multiply-by-4 event count mode 011: Event count mode 111: Up/down event count mode

11 TID0CEN 0: Stops counting

(TID0 count enable) 1: Starts counting 12-14 TOM0ENS X0X: Disables event enable (Selects TOM0_0-7 010: TID0 output enable source) 011: TOM0_7 output 110: TID1 or TOM1_7 output 111: External input TIN18

15 PRS2EN 0: Stops counting

(Prescaler 2 enable) 1: Starts counting Note: Operation mode can only be set or changed when the counter is inactive. The TID0 Control & Prescaler 2 Enable Register is used to select TID0 operation mode (fixed period count, event count, multiply-by-4 event count, or up/down event count mode), as well as select one of TOM0_0-7 timer enable sources and control startup of Prescaler 2. INPUT/OUTPUT TIMERS

10-65 Rev.1.0 I TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) <Address: H'0080 0DD1> D 8 9 1 01 11 21 31 4 D 1 5 TID1M TID1CEN TOM1ENS PRS3EN <When reset: H'00> D Bit Name Function R W 8-10 TID1M X0X: Fixed period count mode (Selects TID1 operation mode) X10: Multiply-by-4 event count mode 011: Event count mode 111: Up/down event count mode

11 TID1CEN 0: Stops counting

(TID1 count enable) 1: Starts counting 12-14 TOM1ENS X0X: Disables event enable (Selects TOM1_0-7 010: TID1 output enable source) 011: TOM1_7 output 110: TID0 or TOM0_7 output 111: External input TIN19

15 PRS3EN 0: Stops counting

(Prescaler 3 enable) 1: Starts counting Note: Operation mode can only be set or changed when the counter is inactive. The TID1 Control & Prescaler 3 Enable Register is used to select TID1 operation mode (fixed period count, event count, multiply-by-4 event count, or up/down event count mode), as well as select one of TOM1_0-7 timer enable sources and control startup of Prescaler 3. INPUT/OUTPUT TIMERS

10-66 Rev.1.0

10.5.4 TID Counters (TID0CT and TID1CT)

I TID0 Counter (TID0CT) <Address: H'0080 0C8C> I TID1 Counter (TID1CT) <Address: H'0080 0D8C> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TID0CT , TID1CT <When reset: indeterminate> D Bit Name Function R W 0-15 TID0CT,TID1CT 16-bit counter value Note: This register must always be accessed in halfwords. The TID Counters are a 16-bit up/down-counter which starts counting synchronously with the count clock after the timer is enabled (by writing to the enable bit in software). INPUT/OUTPUT TIMERS

10-67 Rev.1.0

10.5.5 TID Reload Registers (TID0RL and TID1RL)

I TID0 Reload Register (TID0RL) <Address: H'0080 0C8E> I TID1 Reload Register (TID1RL) <Address: H'0080 0D8E> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TID0RL , TID1RL <When reset: indeterminate> D Bit Name Function R W 0-15 TID0RL,TID1RL 16-bit reload register value Note: This register must always be accessed in halfwords. The TID Reload Registers are used to reload the TID Counter Registers (TID0CT and TID1CT) with data. The following shows the timing at which the content of the reload register is loaded into the corresponding counter.

• When the counter underflows in fixed count mode
• When the counter is enabled in fixed count mode Simply because data is written to the reload register does not mean that the counter is loaded with the data. INPUT/OUTPUT TIMERS

10-68 Rev.1.0

10.5.6 Outline of Each TID Operation Mode

The following outlines each TID operation mode. When using the TID, select one of these operation modes. (1) Fixed period count mode In fixed period count mode, the TID uses the reload register to generate an interrupt at intervals of the reload register set value + 1. When the timer is enabled (by writing to the enable bit in software) after setting the reload register (initially indeterminate), the counter is loaded with the content of the reload register synchronously with the count clock and thereby starts counting. The counter counts down and when it underflows after reaching the minimum count, the counter is loaded with the content of the reload register again, from which it continues counting. To stop the counter, write to the enable bit in software to disable counting. Also, an interrupt can be generated each time the counter underflows. The reload register set value + 1 is the valid count value. Figure 10.5.3 Typical Operation of TID in Fixed Period Count Mode INPUT/OUTPUT TIMERS H'FFFF H'0000 Enabled (by writing to the enable bit) Underflow (first time) TID0 interrupt by underflow Enable bit Counts down from the reload register set value Note: Detailed timing information is not shown in this diagram. Reload register H'E000 Underflow (second time) H'E000 Counts down from the reload register set value H'DFFF Counts down from the reload register set value H'DFFFH'E000 Write simultaneously when enabled

10-69 Rev.1.0 (2) Event count mode In event count mode, the TID uses the signal (TIN8 or TIN10) entered from the outside as the clock source with which to run the counter. Note: TIN9 and TIN11 cannot be used as the clock source for the TID. By detecting the rising and falling edges of the externally sourced signal (TIN8 or TIN10), the TID generates a clock that is synchronized to the internal clock. When after setting the counter the timer is enabled (by writing to the enable bit in software), the counter starts counting up from its set value synchronously with the generated clock. An interrupt can be generated when the counter overflows. To stop the counter, write to the enable bit in software to disable counting or fix the externally sourced signal level high or low. Figure 10.5.4 Typical Operation of the TID in Event Count Mode (Basic Operation) Figure 10.5.5 Typical Operation of the TID in Event Count Mode (when the Counter Overflows) INPUT/OUTPUT TIMERS Count value 7FFF 8000 8001 8002 8003 8004 TIN8 Count value FFFE FFFF 0000 0001 0002 0003 TID interrupt by overflow FFFD

10-70 Rev.1.0 (3) Multiply-by-4 event count mode In Multiply-by-4 event count mode, the TID uses two train of signals (TIN8 and TIN9, TIN10 and TIN11) entered from the outside as the clock sources with which to run the counter. The counter is switched between up-count and down-count by the input state of the two signals. By detecting the rising and falling edges of both of the two externally sourced signals, the TID generates a clock that is synchronized to the internal clock. When after setting the counter the timer is enabled (by writing to the enable bit in software), the counter starts counting from its set value synchronously with the generated clock. For details on whether the counter counts up or down, see Table 10.5.2. An interrupt can be generated when the counter overflows or underflows. To stop the counter, write to the enable bit in software to disable counting or fix the externally sourced signal levels high or low. Table 10.5.2 Count Direction during Multiply-by-4 Event Count Mode TIN8 (TIN10) TIN9 (TIN11) Input H H L L H L L H Up-count Down-count Count Direction INPUT/OUTPUT TIMERS

10-71 Rev.1.0 TIN8 TIN9 Up-count Down-count 8000 8001 8002 8001 8000 8003 7FFE 8003Counter value Counter 80027FFF7FFE 7FFF 7FFE Switched over 8000 TIN8 TIN9 Up-count Down-count 8001 8000 8001 7FFE Counter value Counter 7FFF7FFE Timer enable Switched over Count disabled Count enabled Count disabled Count enabled Count disabled 7FFF Enabled Figure 10.5.6 Up/Down Count Operation (Switchover Timing) Figure 10.5.7 Up/Down Count Operation (Count Enabled/Disabled) INPUT/OUTPUT TIMERS

10-72 Rev.1.0 TID interrupt TIN8 TIN9 Up-count Down-count FFFF 0000 0001 0000 FFFF FFFF 0000 0002Counter value Counter 0001FFFEFFFD FFFE FFFD Switched over Figure 10.5.8 Up/Down Count Operation (Interrupt Timing) INPUT/OUTPUT TIMERS

10-73 Rev.1.0 (5) Up/down event count mode In up/down event count mode, the TID uses one of two train of signals (TIN8 or TIN10) entered from the outside as the clock source and the other (TIN9 or TIN11) as the up/down signal with which to run the counter. The counter is switched between up-count and down-count by the input state of the up/down signal. By detecting the rising and falling edges of the externally sourced clock signal, the TID generates a clock that is synchronized to the internal clock. When after setting the counter the timer is enabled (by writing to the enable bit in software), the counter starts counting up or down from its set value synchronously with the generated clock. The direction in which the counter counts is determined by the input level of the up/down signal (see Table 10.5.3). An interrupt can be generated when the counter overflows or underflows. To stop the counter, write to the enable bit in software to disable counting or fix the externally sourced clock signal level high or low. Note: TIN9 and TIN11 cannot be used as the clock source. Table 10.5.3 Count Direction during Up/Down Event Count Mode TIN8 (TIN10) TIN9 (TIN11) Input Low level Up-count Count Direction High level Down-count Figure 10.5.9 Up/Down Count Operation INPUT/OUTPUT TIMERS (TIN10) Counter value 8000 8001 8002 8001 8000 TIN9 (TIN11) Up-count Down-count 7FFF7FFF

10-74 Rev.1.0 TIN8 (TIN10) Counter value FFFE TIN9 (TIN11) FFFF 0000 0001 0002 0003 0002 0001 0000 FFFF FFFEFFFD FFFD TID interrupt by overflow or underflow Figure 10.5.10 Up/Down Count Operation (Interrupt Timing) INPUT/OUTPUT TIMERS

10-75 Rev.1.0

10.6 TOM (Output Related 16-bit Timers)

10.6.1 Outline of the TOM

TOM (Timer Output Modification) consists of output related 16-bit timers which can be run in one of the following modes as selected in software: <Output modes without correction function>

• PWM output mode
• Single-shot output mode
• Single-shot PWM output mode
• Successive output mode Specifications of the TOM are listed below. A block diagram of the TOM is shown in the next page. INPUT/OUTPUT TIMERS

Table 10.6.1 Specifications of TOM (Output Related 16-bit Timers) Item Specification Number of channels 16 channels (two blocks, 8 channels each, for a total of 16 channels) Counter 16-bit down-counter (16 pcs.) Reload register 16-bit reload register (16 pcs.) Timer start TOM0_0-7: Started by writing to the enable bit in software or by an underflow/ overflow signal from TID0 timer, an underflow signal from TOM0_7, an underflow/overflow signal from TID1 timer, or an underflow signal from TOM1_7 TOM1_0-7: Started by writing to the enable bit in software or by an underflow/ overflow signal from TID1 timer, an underflow signal from TOM1_7, an underflow/overflow signal from TID0 timer, or an underflow signal from TOM0_7 Mode selection <Output modes without correction function>

• PWM output mode
• Single-shot output mode
• Single-shot PWM output mode
• Successive output mode Interrupt generation Can be generated by counter underflow

10-76 Rev.1.0 clk TID0 TIN8 TIN9 1/2 internal peripheral clock IRQ18 clk TOM0_0 udf F/F0 clk TOM0_1 udf F/F1 TO0 TO1 clk TOM0_2 udf F/F2 clk TOM0_3 udf F/F3 TO2 TO3 clk TOM0_4 udf F/F4 clk TOM0_5 udf F/F5 TO4 TO5 clk TOM0_6 udf F/F6 clk TOM0_7 udf F/F7 TO6 TO7 IRQ22 IRQ22 IRQ22 IRQ22 IRQ22 IRQ22 IRQ22 IRQ22 CLK1 CLK2 PRS2 EN EN EN EN EN EN ovf udf EN EN DRQ0 DRQ2 DRQ3 DRQ4 DRQ5 DRQ6 DRQ7 DRQ8 DRQ9 PWM output disable control register To A-D0 converter IRQ28 IRQ28 PWMOFF0S TIN8S TIN9S PWMOFF0 S S clk TID1 TIN10 TIN11 1/2 internal peripheral clock IRQ17 clk TOM1_0 udf F/F8 clk TOM1_1 udf F/F9 TO8 TO9 clk TOM1_2 udf F/F10 clk TOM1_3 udf F/F11 TO10 TO11 clk TOM1_4 udf F/F12 clk TOM1_5 udf F/F13 TO12 TO13 clk TOM1_6 udf F/F14 clk TOM1_7 udf F/F15 TO14 TO15 IRQ20 IRQ20 IRQ20 IRQ20 IRQ22 IRQ20 IRQ20 IRQ20 CLK1 CLK2 PRS3 EN EN EN EN EN EN ovf udf EN EN DRQ1 DRQ10 DRQ11 DRQ12 PWM output disable control register IRQ27 IRQ27 PWMOFF1S TIN10S TIN11S PWMOFF1 S S IRQ30 TIN18 TIN19 TIN18S IRQ22 IRQ22 TIN19S IRQ30 To A-D1 converter To A-D0,1 converter or PD module Figure 10.6.1 Block Diagram of TOM (Output Related 16-bit Timers) INPUT/OUTPUT TIMERS

10-77 Rev.1.0

10.6.2 Outline of Each TOM Operation Mode

The following outlines each TOM operation mode. When using the TOM, select one of these operation modes. (1) PWM output mode (without correction function) In PWM output mode, the TOM uses two reload registers to generate a waveform with any duty cycle. When the timer is enabled after setting the initial value in the reload 0 and the reload 1 registers, the counter is loaded with the value of the reload 0 register synchronously with the count clock, from which it starts counting down. The first time the counter underflows after reaching the minimum count, it is loaded with the content of the reload 1 register. Thereafter, the counter is alternately reloaded by the reload 0 and the reload 1 registers each time it underflows. The F/F output waveform in PWM output mode is inverted when the counter starts counting and each time it underflows. To stop the timer, write to the enable bit to disable counting, and the timer immediately stops (not synchronized to the PWM output period). An interrupt and a DMA transfer request can be generated the second, the fourth, and other even-numbered times the counter underflows after being enabled. (2) Single-shot output mode (without correction function) In single-shot output mode, the TOM generates a pulse in duration of the reload 0 register set value + 1 only once and then stops. When the timer is enabled after setting the reload 0 register, the counter is loaded with the content of the reload 0 register synchronously with the count clock, from which it starts counting. The counter counts down and when it underflows after reaching the minimum count, it stops. The F/F output waveform in single-shot output mode is inverted when the counter starts counting and when it underflows. In this way, the TOM generates a single-shot pulse in duration of the reload 0 register set value + 1 only once. An interrupt and a DMA transfer request can be generated when the counter underflows. INPUT/OUTPUT TIMERS

10-78 Rev.1.0 (3) Single-shot PWM output mode (without correction function) In single-shot PWM output mode, the TOM uses two reload registers to generate a waveform with any duty cycle only once. When the timer is enabled after setting the initial value in the reload 0 and the reload 1 registers, the counter is loaded with the value of the reload 0 register synchronously with the count clock, from which it starts counting down. The first time the counter underflows after reaching the minimum count, it is loaded with the content of the reload 1 register. When the counter underflows second time, it stops counting. The reload 0 register set value + 1 and the reload 1 register set value + 1 respectively are the valid count values. To stop the timer in software, write to the enable bit to disable counting, and the timer immediately stops (not synchronized to the PWM output period). The F/F output waveform in single-shot PWM output mode is inverted (F/F output changes level from low to high or vice versa) each time the counter underflows. (Unlike in PWM output mode, the F/F output waveform is not inverted when the counter is enabled.) An interrupt and a DMA transfer request can be generated the second time the counter underflows after being enabled. (4) Successive output mode (without correction function) In successive output mode, the counter counts down from its set value and upon underflowing, it is loaded with the value of the reload 0 register. Therefore, this operation is repeated each time the counter underflows, thereby successively generating a pulse in duration of the reload 0 register set value + 1. When the timer is enabled after setting the counter and the reload 0 register, the counter starts counting down from its set value synchronously with the count clock. When the counter underflows after reaching the minimum count, it is loaded with the content of the reload 0 register and starts counting again. This is repeated each time the counter underflows. To stop the counter, write to the enable bit in software to disable counting. The F/F output waveform in successive output mode is inverted when the counter starts counting and when it underflows, thereby successively generating a pulse until the count stops. An interrupt and a DMA transfer request can be generated each time the counter underflows. INPUT/OUTPUT TIMERS

10-79 Rev.1.0

10.6.3 TOM Related Register Map

A TOM related register map is shown below. Figure 10.6.2 TOM Related Register Map (1/3) INPUT/OUTPUT TIMERS H'0080 0C90 Address D0 D7 +0 address +1 address D8 D15 H'0080 0C92 H'0080 0C94 H'0080 0C96 H'0080 0CA0 H'0080 0CA2 H'0080 0CA4 H'0080 0CA6 H'0080 0CB0 H'0080 0CB2 H'0080 0CB4 H'0080 0CB6 H'0080 0CBA H'0080 0CBC H'0080 0CBE TOM0_1 Counter (TOM01CT) H'0080 0C9A H'0080 0C98 H'0080 0CB8 Note: The registers enclosed in the thick frames must always be accessed in halfwords. TOM0_0 Reload 0 Register (TOM00RL0) TOM0_0 Reload 1 Register (TOM00RL1) TOM0_0 Counter (TOM00CT) TOM0_2 Counter (TOM02CT) TOM0_1 Reload 0 Register (TOM01RL0) TOM0_1 Reload 1 Register (TOM01RL1) TOM0_3 Counter (TOM03CT) TOM0_2 Reload 0 Register (TOM02RL0) TOM0_2 Reload 1 Register (TOM02RL1) TOM0_4 Counter (TOM04CT) TOM0_3 Reload 0 Register (TOM03RL0) TOM0_3 Reload 1 Register (TOM03RL1) TOM0_5 Counter (TOM05CT) TOM0_4 Reload 0 Register (TOM04RL0) TOM0_4 Reload 1 Register (TOM04RL1) TOM0_5 Reload 0 Register (TOM05RL0) TOM0_5 Reload 1 Register (TOM05RL1) H'0080 0C9C H'0080 0C9E H'0080 0CA8 H'0080 0CAA H'0080 0CAC H'0080 0CAE Blank ares are reserved for future use. H'0080 0CC2 H'0080 0CC0 TOM0_6 Counter (TOM06CT) PWM Output Disable Register 1 (PWMOFF1) PWM Output Disable Register 0 (PWMOFF0) PWM Output Disable Control Register 1 (PLVCNT1) PWM Output Disable Control Register 0 (PLVCNT0) H'0080 07A0 H'0080 07A2 H'0080 07A4

10-80 Rev.1.0 Figure 10.6.3 TOM Related Register Map (2/3) H ’0080 0D90 Address D0 D7 +0 address +1 address D8 D15 H ’0080 0D92 H ’0080 0D94 H ’0080 0D96 H ’0080 0CD0 H ’0080 0CD2 H ’0080 0CD4 H ’0080 0CD6 TOM1_1 Counter (TOM11CT) H ’0080 0D9A H ’0080 0D98 TOM1_0 Reload 0 Register (TOM10RL0) TOM1_0 Reload 1 Register (TOM10RL1) TID0 Control & Prescaler 2 Enable Register (TID0PRS2EN) (Note 1) TOM1_1 Reload 0 Register (TOM11RL0) TOM1_1 Reload 1 Register (TOM11RL1)H ’0080 0D9C H ’0080 0D9E H ’0080 0CD8 Prescaler Register 2 (PRS2) TOM0 Interrupt Mask Register (TOM0IMA) TOM0 Interrupt Status Register (TOM0IST) F/F Protect Register 0 (FFP0) F/F Data Register 0 (FFD0) Note 1: The Prescaler Register 2 is shared with TOM0_0-7 and TID0, and the TID0 Control & Prescaler 2 Enable Register is used to control TID0. Note 2: The registers enclosed in the thick frames must always be accessed in halfwords. H ’0080 0CDA H ’0080 0CDC H ’0080 0CDE TOM0 Control Register (TOM0CR) TOM0 Enable Protect Register (TOM0PRO) TOM0 Count Enable Register (TOM0CEN) Blank ares are reserved for future use. TOM1_0 Counter (TOM10CT) H ’0080 0DA0 H ’0080 0DA2 H ’0080 0DA4 H ’0080 0DA6 TOM1_3 Counter (TOM13CT) H ’0080 0DAA H ’0080 0DA8 TOM1_2 Reload 0 Register (TOM12RL0) TOM1_2 Reload 1 Register (TOM12RL1) TOM1_3 Reload 0 Register (TOM13RL0) TOM1_3 Reload 1 Register (TOM13RL1)H ’0080 0DAC H ’0080 0DAE TOM1_2 Counter (TOM12CT) H ’0080 0DB0 H ’0080 0DB2 TOM1_4 Counter (TOM14CT) TOM0_7 Counter (TOM07CT) TOM0_6 Reload 0 Register (TOM06RL0) TOM0_6 Reload 1 Register (TOM06RL1) TOM0_7 Reload 0 Register (TOM07RL0) TOM0_7 Reload 1 Register (TOM07RL1) H ’0080 0CC4 H ’0080 0CC6 H ’0080 0CC8 H ’0080 0CCA H ’0080 0CCC H ’0080 0CCE INPUT/OUTPUT TIMERS

10-81 Rev.1.0 H ’0080 0DC0 Address D0 D7 +0 address +1 address D8 D15 H ’0080 0DC2 H ’0080 0DC4 H ’0080 0DC6 H ’0080 0DD0 H ’0080 0DD2 H ’0080 0DD4 H ’0080 0DD6 TOM1_7 Counter (TOM17CT) H ’0080 0DCA H ’0080 0DC8 TOM1_6 Reload 0 Register (TOM16RL0) TOM1_6 Reload 1 Register (TOM16RL1) TOM1_6 Counter (TOM16CT) TID1 Control & Prescaler 3 Enable Register (TID1PRS3EN) (Note 1) TOM1_7 Reload 0 Register (TOM17RL0) TOM1_7 Reload 1 Register (TOM17RL1)H ’0080 0DCC H ’0080 0DCE H ’0080 0DD8 Prescaler Register 3 (PRS3) TOM1 Interrupt Mask Register (TOM1IMA) TOM1 Interrupt Status Register (TOM1IST) F/F Protect Register 1 (FFP1) F/F Data Register 1 (FFD1) Note 1: The Prescaler Register 3 is shared with TOM1_0-7 and TID1, and the TID1 Control & Prescaler 3 Enable Register is used to control TID1. Note 2: The registers enclosed in the thick frames must always be accessed in halfwords. H ’0080 0DDA H ’0080 0DDC H ’0080 0DDE TOM1 Control Register (TOM1CR) TOM1 Enable Protect Register (TOM1PRO) TOM1 Count Enable Register (TOM1CEN) Blank ares are reserved for future use. TOM1_5 Reload 0 Register (TOM15RL0) TOM1_5 Reload 1 Register (TOM15RL1) TOM1_5 Counter (TOM15CT) TOM1_4 Reload 0 Register (TOM14RL0) TOM1_4 Reload 1 Register (TOM14RL1)H ’0080 0DB4 H ’0080 0DB6 H ’0080 0DB8 H ’0080 0DBC H ’0080 0DBA H ’0080 0DBE Figure 10.6.4 TOM Related Register Map (3/3) INPUT/OUTPUT TIMERS

10-82 Rev.1.0

10.6.4 PWM Output Disable Registers

I PWM Output Disable Register 1 (PWMOFF1) <Address: H'0080 07A0> D 0 123456 D 7 PWMOFF1P PWMOFF1S <When reset: H'00> D Bit Name Function R W 0-5 No functions assigned 0 –

6 PWMOFF1P 0

(PWMOFF1S write control)

7 PWMOFF1S 0: Enables output

(Selects port P100-P105 output disable) 1: Disables output This register controls PWM outputs from TOM1_0 through TOM1_5 timers by enabling or disabling PWM outputs on the corresponding ports P100-P105. To ensure that the value set in the port P100-P105 output disable select (PWMOFF1S) bit is effective (0: enables output, 1: disables output), bits in this register must be written correctly by following the procedure described below. [Write procedure] x Set the PWMOFF1S write control (PWMOFF1P) bit to 1. ➁ Subsequently after writing in x above, set the PWMOFF1S write control (PWMOFF1P) bit to 0 and the port P100-P105 output disable select (PWMOFF1S) bit to 0 or 1. Note : If a write cycle for any other area occurs between x and ➁ , the value set in the PWMOFF1S write control (PWMOFF1P) bit has no effect. Figure 10.6.5 Procedure for Writing to the PWMOFF1 Register INPUT/OUTPUT TIMERS

• Set the PWMOFF1P bit to 1
• Set the PWMOFF1P bit to 0
• Set the PWMOFF1S bit to 0 or 1 If a write cycle for any other area occurs within this interval, no values are set in the PWMOFF1S bit.

10-83 Rev.1.0 I PWM Output Disable Register 0 (PWMOFF0) <Address: H'0080 07A1> <When reset: H'00> D Bit Name Function R W 8-13 No functions assigned 0 –

14 PWMOFF0P 0

(PWMOFF0S write control)

15 PWMOFF0S 0: Enables output

(Selects port P110-P115 output disable) 1: Disables output This register controls PWM outputs from TOM0_0 through TOM0_5 timers by enabling or disabling PWM outputs on the corresponding ports P110-P115. To ensure that the value set in the port P110-P115 output disable select (PWMOFF0S) bit is effective (0: enables output, 1: disables output), bits in this register must be written correctly by following the procedure described below. [Write procedure] x Set the PWMOFF0S write control (PWMOFF0P) bit to 1. ➁ Subsequently after writing in x above, set the PWMOFF0S write control (PWMOFF0P) bit to 0 and the port P110-P115 output disable select (PWMOFF0S) bit to 0 or 1. Note: If a write cycle for any other area occurs between x and ➁ , the value set in the PWMOFF0S write control (PWMOFF0P) bit has no effect. Figure 10.6.6 Procedure for Writing to the PWMOFF0 Register D 8 9 1 01 11 21 31 4 D 1 5 PWMOFF0P PWMOFF0S INPUT/OUTPUT TIMERS

• Set the PWMOFF0P bit to 1
• Set the PWMOFF0P bit to 0
• Set the PWMOFF0S bit to 0 or 1 If a write cycle for any other area occurs within this interval, no values are set in the PWMOFF0S bit.

10-84 Rev.1.0

10.6.5 PWM Output Disable Control Registers

I PWM Output Disable Control Register 1 (PLVCNT1) <Address: H'0080 07A4> D 0 123456 D 7 PLVSEL1 PLVDIS1 <When reset: H'00> D Bit Name Function R W 0-5 No functions assigned 0 –

6 PLVSEL1 0: Selects to disable port output when low

(Selects port P100-P105 output disable level)1: Selects to disable port output when high

7 PLVDIS1 0: Invalidates output disable selection

(Invalidates/validates output disable selection)1: Validates output disable selection This register controls PWM outputs from the corresponding TOM1_0 through TOM1_5 timers by enabling or disabling them depending on the port P100-P105 levels (high or low). The port disable level select function forcibly turns port output off depending on the port output status. This function may be used in determining whether the three-phase PWM signals turn on simultaneously. Or because its behavior depends on the port output status, it may also be used to check ports for duplicates. (1) PLVSEL1 (port P100-P105 output disable level select) bit (D6) This bit selects the port P100-P105 level (high or low) at which to disable PWM output. To disable PWM output when the port level is low, set this bit to 0. To disable PWM output when the port level is high, set this bit to 1. The following shows conditions under which port output is turned off depending on the port output status. x When PLVSEL1 = 0, port level = 0 Port output is forcibly turned off when one of the following conditions holds true:

• Ports P100 and P101 both are 0
• Ports P102 and P103 both are 0
• Ports P104 and P105 both are 0 ➁ When PLVSEL1 = 1, port level = 1 Port output is forcibly turned off when one of the following conditions holds true:
• Ports P100 and P101 both are 1
• Ports P102 and P103 both are 1
• Ports P104 and P105 both are 1 INPUT/OUTPUT TIMERS

10-85 Rev.1.0 (2) PLVDIS1 (port P100-P105 output disable selection validate/invalidate) bit (D7) This bit validates or invalidates the PWM output disable level selected with the PLVSEL1 bit. Setting this bit to 1 validates the PWM output disable level selected with the PLVSEL1 bit, so that PWM output is disabled when the port P100-P105 is at the level selected with the PLVSEL1 bit. Setting this bit to 0 invalidates the PWM output disable level selected with the PLVSEL1 bit, so that PWM output cannot be disabled according to the port P100-P105 level. INPUT/OUTPUT TIMERS

10-86 Rev.1.0 I PWM Output Disable Control Register 0 (PLVCNT0) <Address: H'0080 07A5> <When reset: H'00> D Bit Name Function R W 8-10 No functions assigned 0 –

14 PLVSEL0 0: Selects to disable port output when low

(Selects port P110-P115 output disable level)1: Selects to disable port output when high

15 PLVDIS0 0: Invalidates output disable selection

(Invalidates/validates output disable selection)1: Validates output disable selection This register controls PWM outputs from the corresponding TOM0_0 through TOM0_5 timers by enabling or disabling them depending on the port P110-P115 levels (high or low). The port disable level select function forcibly turns port output off depending on the port output status. This function may be used in determining whether the three-phase PWM signals turn on simultaneously. Or because its behavior depends on the port output status, it may also be used to check ports for duplicates. (1) PLVSEL0 (port P110-P115 output disable level select) bit (D14) This bit selects the port P110-P115 level (high or low) at which to disable PWM output. To disable PWM output when the port level is low, set this bit to 0. To disable PWM output when the port level is high, set this bit to 1. The following shows conditions under which port output is turned off depending on the port output status. x When PLVSEL0 = 0, port level = 0 Port output is forcibly turned off when one of the following conditions holds true:

• Ports P110 and P111 both are 0
• Ports P112 and P113 both are 0
• Ports P114 and P115 both are 0 ➁ When PLVSEL0 = 1, port level = 1 Port output is forcibly turned off when one of the following conditions holds true:
• Ports P110 and P111 both are 1
• Ports P112 and P113 both are 1
• Ports P114 and P115 both are 1 D 8 9 1 01 11 21 31 4 D 1 5 PLVSEL0 PLVDIS0 INPUT/OUTPUT TIMERS

10-87 Rev.1.0 (2) PLVDIS0 (port P110-P115 output disable selection validate/invalidate) bit (D15) This bit validates or invalidates the PWM output disable level selected with the PLVSEL1 bit. Setting this bit to 1 validates the PWM output disable level selected with the PLVSEL1 bit, so that PWM output is disabled when the port P110-P115 is at the level selected with the PLVSEL0 bit. Setting this bit to 0 invalidates the PWM output disable level selected with the PLVSEL1 bit, so that PWM output cannot be disabled according to the port P110-P115 level. INPUT/OUTPUT TIMERS

10-88 Rev.1.0

10.6.6 TOM Control Registers

I TOM0 Control Register (TOM0CR) <Address: H'0080 0CDA> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOM00M TOM01M TOM02M TOM03M TOM04M TOM05M TOM06M TOM07M <When reset: H'0000> D Bit Name Function R W 0,1 TOM00M 00: Single-shot output mode (Selects TOM0_0 operation mode) 01: Single-shot PWM output mode 2,3 TOM01M 10: Successive output mode (Selects TOM0_1 operation mode) 11: PWM output mode 4,5 TOM02M (Selects TOM0_2 operation mode) 6,7 TOM03M (Selects TOM0_3 operation mode) 8,9 TOM04M (Selects TOM0_4 operation mode) 10,11 TOM05M (Selects TOM0_5 operation mode) 12,13 TOM06M (Selects TOM0_6 operation mode) 14,15 TOM07M (Selects TOM0_7 operation mode) The TOM0 Control Registers are used to select operation modes of TOM0_0-7 (PWM output, single-shot output, single-shot PWM output, or successive output mode). INPUT/OUTPUT TIMERS

10-89 Rev.1.0 I TOM1 Control Register (TOM1CR) <Address: H'0080 0DDA> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOM10M TOM11M TOM12M TOM13M TOM14M TOM15M TOM16M TOM17M <When reset: H'0000> D Bit Name Function R W 0,1 TOM10M 00: Single-shot output mode (Selects TOM1_0 operation mode) 01: Single-shot PWM output mode 2,3 TOM11M 10: Successive output mode (Selects TOM1_1 operation mode) 11: PWM output mode 4,5 TOM12M (Selects TOM1_2 operation mode) 6,7 TOM13M (Selects TOM1_3 operation mode) 8,9 TOM14M (Selects TOM1_4 operation mode) 10,11 TOM15M (Selects TOM1_5 operation mode) 12,13 TOM16M (Selects TOM1_6 operation mode) 14,15 TOM17M (Selects TOM1_7 operation mode) The TOM1 Control Registers are used to select operation modes of TOM1_0-7 (PWM output, single-shot output, single-shot PWM output, or successive output mode). INPUT/OUTPUT TIMERS

10-90 Rev.1.0

10.6.7 TOM Counters

I TOM0_0 Counter (TOM00CT) <Address: H'0080 0C90> I TOM0_1 Counter (TOM01CT) <Address: H'0080 0C98> I TOM0_2 Counter (TOM02CT) <Address: H'0080 0CA0> I TOM0_3 Counter (TOM03CT) <Address: H'0080 0CA8> I TOM0_4 Counter (TOM04CT) <Address: H'0080 0CB0> I TOM0_5 Counter (TOM05CT) <Address: H'0080 0CB8> I TOM0_6 Counter (TOM06CT) <Address: H'0080 0CC0> I TOM0_7 Counter (TOM07CT) <Address: H'0080 0CC8> INPUT/OUTPUT TIMERS <When reset: indeterminate> D Bit Name Function R W 0-15 TOM00CT-TOM07CT 16-bit counter value W= : Writing to the counter in PWM output or single-shot PWM output mode has no effect. Note: These registers must always be accessed in halfwords. The TOM0 Counters are a 16-bit counter which after the timer is enabled, starts counting synchronously with the count clock. Writing to these counters in PWM output or single-shot PWM output mode has no effect. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOM00CT-TOM07CT

10-91 Rev.1.0 I TOM1_0 Counter (TOM10CT) <Address: H'0080 0D90> I TOM1_1 Counter (TOM11CT) <Address: H'0080 0D98> I TOM1_2 Counter (TOM12CT) <Address: H'0080 0DA0> I TOM1_3 Counter (TOM13CT) <Address: H'0080 0DA8> I TOM1_4 Counter (TOM14CT) <Address: H'0080 0DB0> I TOM1_5 Counter (TOM15CT) <Address: H'0080 0DB8> I TOM1_6 Counter (TOM16CT) <Address: H'0080 0DC0> I TOM1_7 Counter (TOM17CT) <Address: H'0080 0DC8> INPUT/OUTPUT TIMERS <When reset: indeterminate> D Bit Name Function R W 0-15 TOM10CT-TOM17CT 16-bit counter value W= : Writing to the counter in PWM output or single-shot PWM output mode has no effect. Note: These registers must always be accessed in halfwords. The TOM1 Counters are a 16-bit counter which after the timer is enabled, starts counting synchronously with the count clock. Writing to these counters in PWM output or single-shot PWM output mode has no effect. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOM10CT-TOM17CT

10-92 Rev.1.0

10.6.8 TOM Reload 0 Registers

I TOM0_0 Reload 0 Register (TOM00RL0) <Address: H'0080 0C96> I TOM0_1 Reload 0 Register (TOM01RL0) <Address: H'0080 0C9E> I TOM0_2 Reload 0 Register (TOM02RL0) <Address: H'0080 0CA6> I TOM0_3 Reload 0 Register (TOM03RL0) <Address: H'0080 0CAE> I TOM0_4 Reload 0 Register (TOM04RL0) <Address: H'0080 0CB6> I TOM0_5 Reload 0 Register (TOM05RL0) <Address: H'0080 0CBE> I TOM0_6 Reload 0 Register (TOM06RL0) <Address: H'0080 0CC6> I TOM0_7 Reload 0 Register (TOM07RL0) <Address: H'0080 0CCE> INPUT/OUTPUT TIMERS <When reset: indeterminate> D Bit Name Function R W 0-15 TOM00RL0-TOM07RL0 16-bit reload register value Note: These registers must always be accessed in halfwords. The TOM0 Reload 0 Registers are used to reload the TOM0 Counter Registers (TOM00CT through TOM07CT) with data. The following shows the timing at which the content of the reload 0 register is loaded into the corresponding counter.

• When the counter is enabled in single-shot output, PWM output, or single-shot PWM output mode
• When the counter underflows in successive output mode
• When the counter underflows after reaching the count value set by reload 1 register in PWM output mode Simply because data is written to the reload 0 register does not mean that the counter is loaded with the data. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOM00RL0-TOM07RL0

10-93 Rev.1.0 I TOM1_0 Reload 0 Register (TOM10RL0) <Address: H'0080 0D96> I TOM1_1 Reload 0 Register (TOM11RL0) <Address: H'0080 0D9E> I TOM1_2 Reload 0 Register (TOM12RL0) <Address: H'0080 0DA6> I TOM1_3 Reload 0 Register (TOM13RL0) <Address: H'0080 0DAE> I TOM1_4 Reload 0 Register (TOM14RL0) <Address: H'0080 0DB6> I TOM1_5 Reload 0 Register (TOM15RL0) <Address: H'0080 0DBE> I TOM1_6 Reload 0 Register (TOM16RL0) <Address: H'0080 0DC6> I TOM1_7 Reload 0 Register (TOM17RL0) <Address: H'0080 0DCE> INPUT/OUTPUT TIMERS <When reset: indeterminate> D Bit Name Function R W 0-15 TOM10RL0 - TOM17RL0 16-bit reload register value Note: These registers must always be accessed in halfwords. The TOM1 Reload 0 Registers are used to reload the TOM1 Counter Registers (TOM10CT through TOM17CT) with data. The following shows the timing at which the content of the reload 0 register is loaded into the corresponding counter.

• When the counter is enabled in single-shot output, PWM output, or single-shot PWM output mode
• When the counter underflows in successive output mode
• When the counter underflows after reaching the count value set by reload 1 register in PWM output mode Simply because data is written to the reload 0 register does not mean that the counter is loaded with the data. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOM10RL0-TOM17RL0

10-94 Rev.1.0

10.6.9 TOM Reload 1 Registers

I TOM0_0 Reload 1 Register (TOM00RL1) <Address: H'0080 0C94> I TOM0_1 Reload 1 Register (TOM01RL1) <Address: H'0080 0C9C> I TOM0_2 Reload 1 Register (TOM02RL1) <Address: H'0080 0CA4> I TOM0_3 Reload 1 Register (TOM03RL1) <Address: H'0080 0CAC> I TOM0_4 Reload 1 Register (TOM04RL1) <Address: H'0080 0CB4> I TOM0_5 Reload 1 Register (TOM05RL1) <Address: H'0080 0CBC> I TOM0_6 Reload 1 Register (TOM06RL1) <Address: H'0080 0CC4> I TOM0_7 Reload 1 Register (TOM07RL1) <Address: H'0080 0CCC> INPUT/OUTPUT TIMERS <When reset: indeterminate> D Bit Name Function R W 0-15 TOM00RL1-TOM07RL1 16-bit reload register value Note: These registers must always be accessed in halfwords. The TOM0 Reload 1 Registers are used to reload the TOM0 Counter Registers (TOM00CT through TOM07CT) with data. The following shows the timing at which the content of the reload 1 register is loaded into the corresponding counter.

• When the counter underflows after reaching the count value set by reload 0 register in PWM output or single-shot PWM output mode Simply because data is written to the reload 1 register does not mean that the counter is loaded with the data. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOM00RL1-TOM07RL1

10-95 Rev.1.0 I TOM1_0 Reload 1 Register (TOM10RL1) <Address: H'0080 0D94> I TOM1_1 Reload 1 Register (TOM11RL1) <Address: H'0080 0D9C> I TOM1_2 Reload 1 Register (TOM12RL1) <Address: H'0080 0DA4> I TOM1_3 Reload 1 Register (TOM13RL1) <Address: H'0080 0DAC> I TOM1_4 Reload 1 Register (TOM14RL1) <Address: H'0080 0DB4> I TOM1_5 Reload 1 Register (TOM15RL1) <Address: H'0080 0DBC> I TOM1_6 Reload 1 Register (TOM16RL1) <Address: H'0080 0DC4> I TOM1_7 Reload 1 Register (TOM17RL1) <Address: H'0080 0DCC> INPUT/OUTPUT TIMERS <When reset: indeterminate> D Bit Name Function R W 0-15 TOM10RL1-TOM17RL1 16-bit reload register value Note: These registers must always be accessed in halfwords. The TOM1 Reload 1 Registers are used to reload the TOM1 Counter Registers (TOM10CT through TOM17CT) with data. The following shows the timing at which the content of the reload 1 register is loaded into the corresponding counter.

• When the counter underflows after reaching the count value set by reload 0 register in PWM output or single-shot PWM output mode Simply because data is written to the reload 1 register does not mean that the counter is loaded with the data. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TOM10RL1-TOM17RL1

10-96 Rev.1.0

10.6.10 TOM Enable Protect Registers

I TOM0 Enable Protect Register (TOM0PRO) <Address: H'0080 0CDD> D 8 9 1 01 11 21 31 4 D 1 5 TOM00PRO TOM01PRO TOM02PRO TOM03PRO TOM04PRO TOM05PRO TOM06PRO TOM07PRO <When reset: H'00> D Bit Name Function R W

8 TOM00PRO 0: Enables rewriting

(TOM0_0 enable protect) 1: Disables rewriting

9 TOM01PRO

(TOM0_1 enable protect)

10 TOM02PRO

(TOM0_2 enable protect)

11 TOM03PRO

(TOM0_3 enable protect)

12 TOM04PRO

(TOM0_4 enable protect)

13 TOM05PRO

(TOM0_5 enable protect)

14 TOM06PRO

(TOM0_6 enable protect)

15 TOM07PRO

(TOM0_7 enable protect) The TOM0 Enable Protect Register is used to control rewriting of the TOM0 count enable bit described in the next page by disabling or enabling the rewrite. INPUT/OUTPUT TIMERS

10-97 Rev.1.0 I TOM1 Enable Protect Register (TOM1PRO) <Address: H'0080 0DDD> <When reset: H'00> D Bit Name Function R W

8 TOM10PRO 0: Enables rewriting

(TOM1_0 enable protect) 1: Disables rewriting

9 TOM11PRO

(TOM1_1 enable protect)

10 TOM12PRO

(TOM1_2 enable protect)

11 TOM13PRO

(TOM1_3 enable protect)

12 TOM14PRO

(TOM1_4 enable protect)

13 TOM15PRO

(TOM1_5 enable protect)

14 TOM16PRO

(TOM1_6 enable protect)

15 TOM17PRO

(TOM1_7 enable protect) The TOM1 Enable Protect Register is used to control rewriting of the TOM1 count enable bit described in the next page by disabling or enabling the rewrite. D 8 9 1 01 11 21 31 4 D 1 5 TOM10PRO TOM11PRO TOM12PRO TOM13PRO TOM14PRO TOM15PRO TOM16PRO TOM17PRO INPUT/OUTPUT TIMERS

10-98 Rev.1.0

10.6.11 TOM Count Enable Registers

I TOM0 Count Enable Register (TOM0CEN) <Address: H'0080 0CDF> <When reset: H'00> D Bit Name Function R W

8 TOM00CEN 0: Stops counting

(TOM0_0 count enable) 1: Enables counting

9 TOM01CEN

(TOM0_1 count enable)

10 TOM02CEN

(TOM0_2 count enable)

11 TOM03CEN

(TOM0_3 count enable)

12 TOM04CEN

(TOM0_4 count enable)

13 TOM05CEN

(TOM0_5 count enable)

14 TOM06CEN

(TOM0_6 count enable)

15 TOM07CEN

(TOM0_7 count enable) D 8 9 1 01 11 21 31 4 D 1 5 TOM00CEN TOM01CEN TOM02CEN TOM03CEN TOM04CEN TOM05CEN TOM06CEN TOM07CEN The TOM0 Count Enable Register controls operation of the TOM0 counters. To enable any counter in software, enable the corresponding TOM0 Enable Protect Register for write and set the count enable bit to 1. To stop the counter, enable the TOM0 Enable Protect Register for write and set the count enable bit to 0. In single-shot output and single-shot PWM output modes, the count enable bit is automatically reset to 0 when the counter stops after reaching the minimum count. Therefore, the TOM0 Count Enable Register when read serves as a status register, indicating the operating status of the counter (operating or idle). INPUT/OUTPUT TIMERS

10-99 Rev.1.0 I TOM1 Count Enable Register (TOM1CEN) <Address: H'0080 0DDF> <When reset: H'00> D Bit Name Function R W

8 TOM10CEN 0: Stops counting

(TOM1_0 count enable) 1: Enables counting

9 TOM11CEN

(TOM1_1 count enable)

10 TOM12CEN

(TOM1_2 count enable)

11 TOM13CEN

(TOM1_3 count enable)

12 TOM14CEN

(TOM1_4 count enable)

13 TOM15CEN

(TOM1_5 count enable)

14 TOM16CEN

(TOM1_6 count enable)

15 TOM17CEN

(TOM1_7 count enable) The TOM1 Count Enable Register controls operation of the TOM1 counters. To enable any counter in software, enable the corresponding TOM1 Enable Protect Register for write and set the count enable bit to 1. To stop the counter, enable the TOM1 Enable Protect Register for write and set the count enable bit to 0. In single-shot output and single-shot PWM output modes, the count enable bit is automatically reset to 0 when the counter stops after reaching the minimum count. Therefore, the TOM1 Count Enable Register when read serves as a status register, indicating the operating status of the counter (operating or idle). D 8 9 1 01 11 21 31 4 D 1 5 TOM10CEN TOM11CEN TOM12CEN TOM13CEN TOM14CEN TOM15CEN TOM16CEN TOM17CEN INPUT/OUTPUT TIMERS

10-100 Rev.1.0

10.6.12 TID Control & Prescaler Enable Registers

I TID0 Control & Prescaler 2 Enable Register (TID0PRS2EN) <Address: H'0080 0CD1> D 8 9 1 01 11 21 31 4 D 1 5 TID0M TID0CEN TOM0ENS PRS2EN <When reset: H'00> D Bit Name Function R W 8-10 TID0M X0X: Fixed period count mode (Selects TID0 operation mode) X10: Multiply-by-4 event count mode 011: Event count mode 111: Up/down event count mode (TID0 count enable) 1: Starts counting 12-14 TOM0ENS X0X: Disables event enable (Selects TOM0_0-7 X10: TID0 output enable source) 011: TOM0_7 output 110: TID1 or TOM1_7 output 111: External input TIN18 (Prescaler 2 enable) 1: Starts counting Note: Operation mode can only be set or changed when the counter is inactive. The TID0 Control & Prescaler 2 Enable Register is used to select TID0 operation mode (fixed period count, event count, multiply-by-4 event count, or up/down event count mode), as well as select one of TOM0_0-7 timer enable sources and control startup of Prescaler 2. INPUT/OUTPUT TIMERS

10-101 Rev.1.0 I TID1 Control & Prescaler 3 Enable Register (TID1PRS3EN) <Address: H'0080 0DD1> <When reset: H'00> D Bit Name Function R W 8-10 TID1M X0X: Fixed period count mode (Selects TID1 operation mode) X10: Multiply-by-4 event count mode 011: Event count mode 111: Up/down event count mode (TID1 count enable) 1: Starts counting 12-14 TOM1ENS X0X: Disables event enable (Selects TOM1_0-7 X10: TID1 output enable source) 011: TOM1_7 output 110: TID0 or TOM0_7 output 111: External input TIN19 (Prescaler 3 enable) 1: Starts counting Note: Operation mode can only be set or changed when the counter is inactive. The TID1 Control & Prescaler 3 Enable Register is used to select TID1 operation mode (fixed period count, event count, multiply-by-4 event count, or up/down event count mode), as well as select one of TOM1_0-7 timer enable sources and control startup of Prescaler 3. D 8 9 1 01 11 21 31 4 D 1 5 TID1M TID1CEN TOM1ENS PRS3EN INPUT/OUTPUT TIMERS

10-102 Rev.1.0 WR Dn TOM0m enable protect (TOM0mPRO) WR EN-ON Selects TOM0 enable source (TOM0ENS) TOM0m enable (TOM0mCEN) TOM0m enable control F/F F/F Disables event enable TID0 output TOM0_7 output External input TIN18 Selects TOM1 enable source (TOM1ENS) Disables event enable TID1 output TOM1_7 output External input TIN19 TID0 or TOM0_7 output Note: Effective only when TID1 output or TOM1_7 output is selected Figure 10.6.7 Configuration of the TOM0 Enable Circuit Figure 10.6.8 Configuration of the TOM1 Enable Circuit INPUT/OUTPUT TIMERS (TOM1mPRO) WR EN-ON Selects TOM1 enable source (TOM1ENS) TOM1m enable (TOM1mCEN) TOM1m enable control F/F F/F Disables event enable TID1 output TOM1_7 output External input TIN19 Selects TOM0 enable source (TOM0ENS) Disables event enable TID0 output TOM0_7 output External input TIN18 TID1 or TOM1_7 output Note: Effective only when TID0 output or TOM0_7 output is selected

10-103 Rev.1.0

10.6.13 Operation of TOM in PWM Output Mode

(1) Outline of PWM Output Mode for TOM In PWM output mode, the TOM uses two reload registers to generate a waveform with any duty cycle. When the timer is enabled after setting the initial value in the reload 0 and the reload 1 registers, the counter is loaded with the value of the reload 0 register synchronously with the count clock, from which it starts counting down. The first time the counter underflows after reaching the minimum count, it is loaded with the content of the reload 1 register. Thereafter, the counter is alternately reloaded by the reload 0 and the reload 1 registers each time it underflows. The reload 0 register set value + 1 and the reload 1 register set value + 1 respectively are the valid count values. To stop the timer, write to the enable bit to disable counting, and the timer immediately stops (not synchronized to the PWM output period). The F/F output waveform in PWM output mode is inverted (F/F output changes level from low to high or vice versa) when the counter starts counting and each time it underflows. An interrupt and a DMA transfer request can be generated the second, the fourth, and other even-numbered times the counter underflows after being enabled. PWM output mode for TOM does not have a correction function. INPUT/OUTPUT TIMERS

10-104 Rev.1.0 Count clock Counter H'FFFF H'0000 Enabled (by writing to the enable bit or by external input) F/F output Underflow (first time) TOM interrupt by underflow Enable bit Note: Detailed timing information is not shown in this diagram. Reload 0 register H'A000 Underflow (second time) Counts down from reload 1 register set value H'(C000-1) Data inverted by underflow Data inverted by enable H'(A000-1) Data inverted by underflow Reload 1 register H'C000 Counts down from reload 0 register set value Counts down from reload 0 register set value H'A000 PWM output period H'C000 H'A000 Figure 10.6.9 Typical Operation of TOM in PWM Output Mode INPUT/OUTPUT TIMERS

10-105 Rev.1.0 (2) Updating of TOM reload registers in PWM mode In PWM output mode, when the timer is idle, the reload 0 and reload 1 registers are updated simultaneously when data are written to the registers. However, when the timer is operating, the reload 1 register is updated by updating the reload 0 register. The values obtained by reading the reload 0 and reload 1 registers are always the data written to the registers. Figure 10.6.10 PWM Circuit Diagram When the reload 0 and reload 1 registers need to be rewritten while the timer is operating, rewrite the reload 1 register first and then the reload 0 register. As a result, the reload 0 and reload 1 registers both are updated synchronously with PWM period. Normally, this can be accomplished at a time by accessing the 32-bit address space wordwise beginning with the reload 1 register address. (The reload 1 and then the reload 0 registers are automatically written to in succession.) If the reload registers are updated in reverse by updating the reload 0 and then the reload 1 registers, only the reload 0 register is updated. The values obtained by reading the reload 0 and reload 1 registers are always the data written to the registers, and not the reload values actually being used. While rewriting the PWM period, if the PWM period expires before writing to the reload 0 register, the PWM period is not immediately updated and the updating is reflected in the next period. INPUT/OUTPUT TIMERS 16-bit counterPrescaler output F/F TO TOM0nRL0 Reload 0 PWM mode control

10-106 Rev.1.0 (a) When updating of the reload registers takes effect in the current period (reflected in the next period) Note: Detailed timing information is not shown in this diagram. Count clock Reload 0 register Reload 1 register H'0001 H'FFFF H'1000 H'7FFF H'2000 H'8000 H'9000 Counter Interrupt by underflow Timing at which reload 1 and reload 0 registers are updated New PWM output period Operation with the written reload value Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (reload 1 data latched) H'1000 H'2000 H'8000 H'9000 Enlarged view New PWM output period Old PWM output period F/F output H'7FFEH'0000 PWM period latched Reload 1 buffer H'2000 H'9000 Note: Detailed timing information is not shown in this diagram. Count clock Reload 0 register Reload 1 register H'0001 H'FFFF H'1000 H'0FFF H'2000 H'8000 H'9000 Counter Interrupt by underflow (b) When updating of the reload registers takes effect in the next period (reflected in the period after next) Timing at which reload 1 and reload 0 registers are updated Old PWM output period Operation with the old reload value Reload 0 register Reload 1 register F/F output Write to reload 1 Write to reload 0 (reload 1 data latched) H'1000 H'2000 H'8000 H'9000 Enlarged view Old PWM output period Old PWM output period F/F output H'0FFEH'0000 PWM period latched Reload 1 buffer H'2000 H'9000 Figure 10.6.11 Updating Reload 0 and Reload 1 Registers in PWM Output Mode INPUT/OUTPUT TIMERS

10-107 Rev.1.0

10.6.14 Operation of TOM in Single-shot Output Mode (without Correction Function)

(1) Outline of single-shot output mode for TOM In single-shot output mode, the TOM generates a pulse in duration of the reload 0 register set value + 1 only once and then stops. When the timer is enabled after setting the reload 0 register, the counter is loaded with the content of the reload 0 register synchronously with the count clock, from which it starts counting. The counter counts down and when it underflows after reaching the minimum count, it stops. The F/F output waveform in single-shot output mode is inverted (F/F output changes level from low to high or vice versa) when the counter starts counting and when it underflows. In this way, the TOM generates a single-shot pulse in duration of the reload 0 register set value + 1 only once. An interrupt and a DMA transfer request can be generated when the counter underflows. The count value is the reload 0 register set value + 1. (2) Precautions on using TOM in single-shot output mode The following describes precautions to be observed when using the TOM in single-shot output mode.

• If the counter stops upon underflowing while it is enabled by external input in the same clock cycle, the former has priority so that the counter stops.
• If the counter stops upon underflowing while it is enabled for counting by writing to the enable bit in the same clock cycle, the latter has priority so that the counter is enabled for counting.
• If the counter is enabled by external input while it is disabled against counting by writing to the enable bit in the same clock cycle, the latter has priority so that the counter is disabled against counting.
• Because the internal circuit operation is synchronized to the count clock (prescaler output), a prescaler equivalent delay time exists before the F/F starts operation after being enabled. INPUT/OUTPUT TIMERS

10-108 Rev.1.0 Count clock H'FFFF H'0000 Enabled (by writing to the enable bit or by external input) F/F output Disabled (by underflow) (Unused) TOM interrupt by underflow Enable bit Counts down from the reload 0 register set value Note: Detailed timing information is not shown in this diagram. Reload 0 registerH'A000 H'A000 Data inverted by enable Data inverted by underflow Counter Reload 1 register Figure 10.6.12 Typical Operation of TOM in Single-shot Output Mode (without Correction Function) INPUT/OUTPUT TIMERS

10-109 Rev.1.0

10.6.15 Operation of TOM in Single-shot PWM Output Mode (without Correction Function)

(1) Outline of single-shot PWM output mode for TOM In single-shot PWM output mode, the TOM uses two reload registers to generate a waveform with any duty cycle only once. When the timer is enabled after setting the initial value in the reload 0 and the reload 1 registers, the counter is loaded with the value of the reload 0 register synchronously with the count clock, from which it starts counting down. The first time the counter underflows after reaching the minimum count, it is loaded with the content of the reload 1 register. When the counter underflows second time, it stops counting. The reload 0 register set value + 1 and the reload 1 register set value + 1 respectively are the valid count values. To stop the timer in software, write to the enable bit to disable counting, and the timer immediately stops (not synchronized to the PWM output period). The F/F output waveform in single-shot PWM output mode is inverted (F/F output changes level from low to high or vice versa) each time the counter underflows. (Unlike in PWM output mode, the F/F output waveform is not inverted when the counter is enabled.) An interrupt and a DMA transfer request can be generated the second time the counter underflows after being enabled. Single-shot PWM output mode for TOM does not have a correction function. INPUT/OUTPUT TIMERS

10-110 Rev.1.0 Count clock H'FFFF H'0000 Enabled (by writing to the enable bit or by external input) F/F output Underflow (first time) TOM interrupt by underflow Enable bit Note: Detailed timing information is not shown in this diagram. Reload 0 register H'A000 H'A000 Underflow (second time) H'F000 Counts down from reload 1 register set value H'EFFF Data inverted by underflow Data inverted by underflow Counter Reload 1 register H'F000 Counts down from reload 0 register set value PWM output period Figure 10.6.13 Typical Operation of TOM in Single-shot PWM Output Mode (without Correction Function) INPUT/OUTPUT TIMERS

10-111 Rev.1.0

10.6.16 Operation of TOM in Successive Output Mode (without Correction Function)

(1) Outline of successive output mode for TOM In successive output mode, the counter counts down from its set value and upon underflowing, it is loaded with the value of the reload 0 register. Therefore, this operation is repeated each time the counter underflows, thereby successively generating a pulse in duration of the reload 0 register set value + 1. When the timer is enabled after setting the counter and the reload 0 register, the counter starts counting down from its set value synchronously with the count clock. When the counter underflows after reaching the minimum count, it is loaded with the content of the reload 0 register and starts counting again. This is repeated each time the counter underflows. To stop the counter, write to the enable bit in software to disable counting. The F/F output waveform in successive output mode is inverted (F/F output changes level from low to high or vice versa) when the counter starts counting and when it underflows, thereby successively generating a pulse waveform until the count stops. An interrupt and a DMA transfer request can be generated each time the counter underflows. The counter set value + 1 and the reload 0 register set value + 1 are the valid count values. (2) Precautions on using TOM in successive output mode The following describes precautions to be observed when using the TOM in successive output mode.

• If the counter is enabled by external input while it is disabled against counting by writing to the enable bit in the same clock cycle, the latter has priority so that the counter is disabled against counting.
• When the counter is read immediately after being reloaded pursuant to underflowing, it temporarily shows the value H'FFFF which, however, immediately changes to the "reload value - 1" in the next clock cycle.
• Because the internal circuit operation is synchronized to the count clock (prescaler output), a prescaler equivalent delay time exists before the F/F starts operation after being enabled. INPUT/OUTPUT TIMERS

10-112 Rev.1.0 Count clock Counter H'FFFF H'0000 Enabled (by writing to the enable bit or by external input) F/F output Underflow (first time) TOM interrupt by underflow Enable bit Counts down from the counter set value Note: Detailed timing information is not shown in this diagram. Reload 0 register H'E000 H'A000 Underflow (second time) H'E000 Counts down from the reload 0 register set value H'DFFF Data inverted by underflow Data inverted by enable Counts down from the reload 0 register set value H'DFFF Data inverted by underflow (Unused)Reload 1 register Figure 10.6.14 Typical Operation of TOM in Successive Output Mode (without Correction Function) INPUT/OUTPUT TIMERS

10-113 Rev.1.0

10.6.17 TOM Output Disable Function

The TOM has the function to disable PWM outputs from TOM0_0-TOM0_5 and TOM1_0-TOM1_5 timers. The circuit configuration of this PWM output disable function is shown in Figure 10.6.15. There are following three methods to disable PWM outputs. Figure 10.6.15 Circuit Configuration of PWM Output Disable Function INPUT/OUTPUT TIMERS PWMOFF0(WR) RD TMS0(cap3) D15 P110 (internal) P111 (internal) P112 (internal) P113 (internal) P114 (internal) P115 (internal) P110/TO0 P111/TO1 P112/TO2 P113/TO3 P114/TO4 P115/TO5 P110 (internal) P111 (internal) P112 (internal) P113 (internal) P114 (internal) P115 (internal) TIN17S2 IRQ30 P131/TIN17/PWMOFF1 TIN17S IRQ23 SET WR F/F F/F F/F PLVSEL1 PLVDIS1 PWMOFF1 WR F/FD6 Address F/F PWMOFF1(WR) RD TMS0(cap2) P100 (internal) P101 (internal) P102 (internal) P103 (internal) P104 (internal) P105 (internal) P100/TO8 P101/TO9 P102/TO10 P103/TO11 P104/TO12 P105/TO13 P100 (internal) P101 (internal) P102 (internal) P103 (internal) P104 (internal) P105 (internal) P106 (internal) P106/TO14 P107 (internal) P107/TO15 P116 (internal) P116/TO6 P117 (internal) P117/TO7 WR D15

10-114 Rev.1.0 (1) Disabling PWM outputs with the signal entered from the external pin (TIN16 or TIN17) The input signal on the external pin TIN16 may be used to disable PWM outputs of TOM0_0- TOM0_5 timers from being output to the corresponding ports P110-P115. Similarly, the input signal on the external pin TIN17 may be used to disable PWM outputs of TOM1_0-TOM1_5 timers from being output to the corresponding ports P100-P105. To disable PWM outputs using the input signal on the external pin TIN16 or TIN17, the TIN Input Processing Control Register 4 (TINCR4) must be set up following the procedure described below. [Setting up the TINCR4 Register]

• To disable PWM outputs using TIN17 x Set the TINCR4 Register D0 bit to 1. ➁ Subsequently after writing in x above, set the D0 bit to 0 and the D1-D3 bits to "000," "001," Note: If a write cycle for any other area occurs between x and ➁ , the value set in the D1-D3 bits has no effect.
• To disable PWM outputs using TIN16 x Set the TINCR4 Register D4 bit to 1. ➁ Subsequently after writing in x above, set the D4 bit to 0 and the D5-D7 bits to "000," "001," Note: If a write cycle for any other area occurs between x and ➁ , the value set in the D5-D7 bits has no effect. (2) Disabling PWM outputs with the pin level on ports P100-P105 or P110-P115 The pin level on ports P100-P105 (high or low) may be used to disable PWM outputs of TOM1_0- TOM1_5 timers from being output to the corresponding ports P100-P105. Similarly, the pin level on ports P110-P115 (high or low) may be used to disable PWM outputs of TOM0_0-TOM0_5 timers from being output to the corresponding ports P110-P115. To disable PWM outputs using the pin level on said ports, the Port P100-P105 Output Disable Control Register (PLVCNT1) or Port P110-P115 Output Disable Control Register (PLVCNT0) must be set up following the procedure described below.
• To disable PWM outputs using the port P100-P105 level x Set the PLVCNT1 Register D6 bit (PLVSEL1) to 1 or 0 to select the port level (high or low) at which to disable PWM outputs. ➁ Set the PLVCNT1 Register D7 bit (PLVDIS1) to 1 (to validate output disable setting). INPUT/OUTPUT TIMERS

10-115 Rev.1.0

• To disable PWM outputs using the port P110-P115 level x Set the PLVCNT0 Register D14 bit (PLVSEL0) to 1 or 0 to select the port level (high or low) at which to disable PWM outputs. ➁ Set the PLVCNT0 Register D15 bit (PLVDIS0) to 1 (to validate output disable setting). (3) Disabling PWM outputs with the Port Output Disable Register (PWMOFF0 or PWMOFF1) The Port P110-P115 Output Disable Register (PWMOFF0) may be used to disable PWM outputs of TOM0_0-TOM0_5 timers from being output to the corresponding ports P110-P115. Similarly, the Port P100-P105 Output Disable Register (PWMOFF1) may be used to disable PWM outputs of TOM1_0-TOM1_5 timers from being output to the corresponding ports P100-P105. To disable PWM outputs using the Port P110-P115 Output Disable Register (PWMOFF0) or Port P100-P105 Output Disable Register (PWMOFF1), the respective registers must be set up following the procedure described below.
• To disable PWM outputs using the Port P110-P115 Output Disable Register (PWMOFF0) x Set the PWMOFF0 Register D14 bit to 1. ➁ Subsequently after writing in x above, set the D14 to 0 and the D15 bit to 1, respectively. Note: If a write cycle for any other area occurs between x and ➁ , the value set in the D15 bit has no effect.
• To disable PWM outputs using the Port P100-P105 Output Disable Register (PWMOFF1) x Set the PWMOFF1 Register D6 bit to 1. ➁ Subsequently after writing in x above, set the D6 to 0 and the D7 bit to 1, respectively. Note: If a write cycle for any other area occurs between x and ➁ , the value set in the D7 bit has no effect. INPUT/OUTPUT TIMERS

10-116 Rev.1.0

10.6.18 Example for Using the TOM in Motor Control Applications

The microcomputer contains two blocks of TOM timers which are designed to reduce software load during motor control. This section explains an example for using TOM0 in motor control applications. The three-phase motor control waveforms start TOM0 according to the TOM0 startup timing at a fixed period of 20 kHz generated by TID0. By using the TOM0's internal single-shot PWM function, the output waveform can easily be configured because the waveform data only needs to be stored at the necessary rewrite timing. The H and L transistor short-circuiting prevention time can be accomplished by changing the TOM0 setup time in software. Up to 8-phase motors can be controlled by a combined use of TID and TOM. Figure 10.6.16 System Configuration Diagram Figure 10.6.17 Interconnecting Timers for Three-phase Motor Control INPUT/OUTPUT TIMERS V W TMS TMS TMS TOM TOM TOM TOM TOM TOM clk TOM0_0 clk TOM0_1 clk TOM0_2 clk TOM0_3 clk TOM0_4 clk TOM0_5 F/F0 F/F1 F/F2 F/F3 F/F4 F/F5 TO0(U) PRS2 EN EN EN EN EN EN clk TID0 Single-shot PWM Single-shot PWM Single-shot PWM Single-shot PWM Single-shot PWM Single-shot PWM Fixed period udf udf udf udf udf udf TO1(/U) TO2(V) TO3(/V) TO4(W) TO5(/W) Generates 20 kHz Start udf

10-117 Rev.1.0 U V W 20KHzTOM start TO0(U) TO1(/U) TO2(V) TO3(/V) TO4(W) TO5(/W) Delay Single shot Delay Single shot : Short-circuiting prevention time Figure 10.6.18 Conceptual Diagram of Motor Control INPUT/OUTPUT TIMERS

10-118 Rev.1.0 INPUT/OUTPUT TIMERS

11.1 Outline of the A-D Converters

11.2 A-D Converter Related

11.3 Functional Description of the

11.4 Precautions on Using the

11-2 Rev.1.0 The 32172/32173 contains two 10-bit resolution A-D converters based on successive approximation method (A-D0 and A-D1 Converters). The A-D0 Converter has eight channels of dedicated analog input pins (AD0IN0-AD0IN7) and eight other channels of analog input pins which are shared with input/output ports or internal peripheral I/O input/output pins (AD0IN8-AD0IN15), for a total of 16 channels. The A-D1 Converter has four channels of dedicated analog input pins (AD1IN0-AD1IN3) and 12 other channels of analog input pins which are shared with input/output ports or internal peripheral I/O input/output pins (AD1IN4-AD1IN15), for a total of 16 channels. For both converters, the A-D converted value can be read out in either 8 bits or 10 bits. The A-D converters have the following conversion modes and operation modes. (1) Conversion modes

• A-D conversion mode: This is an ordinary mode, in which analog input voltages are A-D converted.
• Comparator mode (Note): In this mode, the set comparison voltage and the analog input voltage are compared to determine which is larger or smaller than the other (single mode only). (2) Operation modes
• Single mode: The analog input voltage on one channel is A-D converted once or comparated (note).
• Scan mode: Analog input voltages on multiple channels are sequentially A-D converted. (3) Types of scan modes
• Single-shot scan mode: Scan operation is performed only one cycle.
• Continuous scan mode: Scan operation is performed repeatedly until halted. (4) Special operation modes
• Forcibly execute single mode during scan mode operation: Single mode conversion is forcibly executed during scan operation.
• Start scan mode after executing single mode: Scan operation is started from single mode in succession.
• Restart conversion: A-D convert operation under way is restarted in single or scan mode. The A-D conversion and comparate speed can be selected from four speeds available: low speed (normal or twice normal) or high speed (normal or twice normal). Also, an A-D conversion interrupt request or DMA transfer request can be generated when the A-D conversion, comparate, or single- shot scan is finished, or each time one cycle of continuous scan mode is finished. Note: The comparison performed internally by the A-D converter which is of the successive approximation type and its operation in comparator mode where the A-D converter is used as a comparator are different. In this manual, therefore, operation in comparator mode is referred to as "comparate" in order to discriminate it against ordinary comparison. A-D CONVERTERS

11-3 Rev.1.0 The A-D converters are outlined in Table 11.1.1. A block diagram of the A-D converters are shown Table 11.1.1 Outline of the A-D Converters (1/2) Item Content Analog input 16 channels x 2 A-D0 Converter : 8 channels of dedicated analog input pins 8 channels of analog input pins shared with input/output ports or peripheral I/O pins A-D1 Converter : 4 channels of dedicated analog input pins 12 channels of analog input pins shared with input/output ports or peripheral I/O pins A-D conversion method Successive approximation method Resolution 10 bits (Conversion results read out in 8 or 10 bits) Absolute accuracy (Note 1) Low speed mode Normal ±2LSB (Conditions: Ta = -40 ~ +125°C, Double speed ±2LSB AVCC0 = VREF0 = 5.12V) High speed mode Normal ±3LSB Double speed ±3LSB Conversion mode A-D conversion mode, comparator mode Operation mode Single mode, scan mode Scan mode Single-shot scan mode, continuous scan mode Conversion start trigger Started in software By setting A-D conversion start bit to 1 Started in hardware A-D0 Converter : Input on external pin TIN16 Underflow of TOM0_6 timer Enable event on TOM0_0-7 (Note 2) Completion of A-D1 conversion A-D1 Converter : Input on external pin TIN16 Underflow of TOM0_6 timer Underflow of TOM1_6 timer Completion of A-D0 conversion Note 1: The rated value of conversion accuracy here is that of the microcomputer's own as a single unit which can be exhibited when the microcomputer is used in an environment where it may not be affected by the power supply wiring or noise on the board. Note 2: There are following sources of enable event on TOM0_0-7 (for details, see Chapter 10, "Input/ output Timers"):

• TID0 overflow/underflow
• TOM0_7 underflow
• Input on external pin TIN18
• TID1 overflow/underflow or TOM1_7 underflow A-D CONVERTERS

11-4 Rev.1.0 Table 11.1.2 Outline of the A-D Converters (2/2) Item Content Conversion speed During single Low speed mode Normal 299 × 1/f(BCLK) f(BCLK): mode Double speed 173 × 1/f(BCLK) Internal peripheral clock High speed mode Normal 131 × 1/f(BCLK) operating frequency (Note) Double speed 89 × 1/f(BCLK) During comparator Low speed mode Normal 47 × 1/f(BCLK) mode Double speed 29 × 1/f(BCLK) High speed mode Normal 23 × 1/f(BCLK) Double speed 17 × 1/f(BCLK) Interrupt request generation When A-D conversion, comparate, single-shot scan, or one cycle of function continuous scan mode is finished DMA transfer request generation When A-D conversion, comparate, single-shot scan, or one cycle of function continuous scan mode is finished Note: When the input clock (XIN) = 10 MHz, this is f(BCLK) = 20 MHz A-D CONVERTERS

11-5 Rev.1.0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 Selector Interrupt requestAVSS0 VREF0 10-bit A-D Successive Approximation Register (AD0SAR) 10-bit A-D0 Data Register 0 10-bit A-D0 Data Register 1 A-D0 Single Mode Register A-D Comparate Data Register A-D Control Circuit

• Mode selection
• Channel selection
• Conversion time selection
• Flag control
• Interrupt control 10-bit D-A Converter Comparator AD0IN8 (Note) AD0IN9 (Note) AD0N10 (Note) AD0IN11 (Note) AD0IN12 (Note) AD0IN13 (Note) AD0IN14 (Note) AD0IN15 (Note) AD0CMP AD0DT0 AD0DT1 AD0DT2 AD0DT3 AD0DT4 AD0DT5 AD0DT6 AD0DT7 AD0DT8 AD0DT9 AD0DT10 AD0DT11 AD0DT12 AD0DT13 AD0DT14 AD0DT15 DMA transfer request Successive Approximation Method A-D Converter Unit Internal data bus A-D0 Scan Mode RegisterAD0SCM0,1 AD0SIM0,1 AVCC0 Read out in 10 bits Read out in 8 bits Shifter 10-bit A-D0 Data Register 2 10-bit A-D0 Data Register 3 10-bit A-D0 Data Register 4 10-bit A-D0 Data Register 5 10-bit A-D0 Data Register 6 10-bit A-D0 Data Register 7 10-bit A-D0 Data Register 8 10-bit A-D0 Data Register 9 10-bit A-D0 Data Register 10 10-bit A-D0 Data Register 11 10-bit A-D0 Data Register 12 10-bit A-D0 Data Register 13 10-bit A-D0 Data Register 14 10-bit A-D0 Data Register 15 Starts A-D1 converter Note: The AD0IN8-AD0IN15 pins are shared with input/output ports or internal peripheral I/O input/output pins. TIN16 TOM0-6udf TOM00-7EN AD1 finished S S AD0CTRG1 AD0STRG1 Figure 11.1.1 Block Diagram of the A-D0 Converter A-D CONVERTERS

11-6 Rev.1.0 AD1IN0 AD1IN1 AD1IN2 AD1IN3 AD1IN4 AD1IN5 AD1IN6 AD1IN7 Selector Interrupt requestAVSS0 VREF0 10-bit A-D Successive Approximation Register (AD1SAR) 10-bit A-D1 Data Register 0 10-bit A-D1 Data Register 1 A-D1 Single Mode Register A-D Comparate Data Register A-D Control Circuit

• Mode selection
• Channel selection
• Conversion time selection
• Flag control
• Interrupt control 10-bit D-A Converter Comparator AD1IN8 (Note) AD1IN9 (Note) AD1N10 (Note) AD1IN11 (Note) AD1IN12 (Note) AD1IN13 (Note) AD1IN14 (Note) AD1IN15 (Note) AD1CMP AD1DT0 AD1DT1 AD1DT2 AD1DT3 AD1DT4 AD1DT5 AD1DT6 AD1DT7 AD1DT8 AD1DT9 AD1DT10 AD1DT11 AD1DT12 AD1DT13 AD1DT14 AD1DT15 DMA transfer request Successive Approximation Method A-D Converter Unit Internal data bus A-D1 Scan Mode RegisterAD1SCM0,1 AD1SIM0,1 AVCC0 Read out in 10 bits Read out in 8 bits Shifter 10-bit A-D1 Data Register 2 10-bit A-D1 Data Register 3 10-bit A-D1 Data Register 4 10-bit A-D1 Data Register 5 10-bit A-D1 Data Register 6 10-bit A-D1 Data Register 7 10-bit A-D1 Data Register 8 10-bit A-D1 Data Register 9 10-bit A-D1 Data Register 10 10-bit A-D1 Data Register 11 10-bit A-D1 Data Register 12 10-bit A-D1 Data Register 13 10-bit A-D1 Data Register 14 10-bit A-D1 Data Register 15 Starts A-D0 converter Note: The AD1IN4-AD1IN15 pins are shared with input/output ports or internal peripheral I/O input/output pins. TIN16 TOM0-6udf TOM1-6udf AD0 finished S S AD1CTRG1 AD1STRG1 (Note) (Note) (Note) (Note) Figure 11.1.2 Block Diagram of the A-D1 Converter A-D CONVERTERS

11-7 Rev.1.0

11.1.1 Conversion Modes

The A-D converters have two conversion modes: "A-D conversion mode" and "comparator mode." (1) A-D conversion mode In A-D conversion mode, the A-D converter converts the analog input voltage on a specified channel from analog to digital quantities. When operating in single mode, the A-D converter performs conversion on a channel selected with the Single Mode Register 1 analog input select bits (Note). When operating in scan mode, the A-D converter performs conversion on channels selected with Scan Mode Register 1 according to settings of Scan Mode Register 0. The conversion result is stored in the 10-bit A-D Data Register provided for each channel converted. Also, an 8-bit conversion result can be read out from the 8-bit A-D Data Register. An A-D conversion interrupt request or DMA transfer request can be generated when A-D conversion is finished during single mode or one cycle of scan loop is finished during scan mode. Note: If the analog input pins AD0IN8-AD0IN15 or AD1IN6-AD1IN15 are selected with Single Mode Register 1, always be sure to set the AD Digital Input Control Register (AD0CHCON or AD1CHCON). (2) Comparator mode In comparator mode, the A-D converter "comparates" the analog input voltage on a specified channel with the Successive Approximation Register value and returns a flag for the result (relative magnitude of the compared values). The Single Mode Register 1 analog input pin select bits (Note) are used to specify the channel to comparate. The flag for the comparate result (1 or 0) is set in the A-D Comparate Data Register bit corresponding to the selected channel. An A-D conversion interrupt request or DMA transfer request can be generated when comparate operation is finished. Note: If the analog input pins AD0IN8-AD0IN15 or AD1IN6-AD1IN15 are selected with Single Mode Register 1, always be sure to set the AD Digital Input Control Register (AD0CHCON or AD1CHCON). A-D CONVERTERS

11-8 Rev.1.0 Figure 11.1.3 Single Mode Operation (A-D Conversion) Figure 11.1.4 Single Mode Operation (Comparate) A-D CONVERTERS

11.1.2 Operation Modes

The A-D converters have two operation modes: "single mode" and "scan mode." (1) Single mode In single mode, the A-D converter A-D converts or comparates the analog input voltage on one selected channel only once. An A-D conversion interrupt request or DMA transfer request can be generated when A-D conversion is finished. A-D conversion interrupt request or DMA transfer request ANiINn Finished ADiDTn 10-bit A-Di Data Register Conversion starts (Note) i=0,1 n=0~15 Note: A-D0 conversion start: Software trigger → By setting the A-D0 conversion start bit to 1 Hardware trigger → By TOM0_6 underflow, input signal on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion A-D1 conversion start: Software trigger → By setting the A-D1 conversion start bit to 1 Hardware trigger → By TOM0_6 underflow, input signal on external pin TIN16, TOM1_6 underflow, or completion of A-D0 conversion A-D conversion interrupt request or DMA transfer request Note: Comparate start: By writing a comparison value to the Successive Approximation Register (ADiSAR) ADiINn Finished ADiCMP A-Di Comparate Data Register ADiSAR A-D Successive Approximation Register Comparate result ADiCMP=0(ANn>ADiSAR) ADiCMP=1(ANn<ADiSAR) i=0,1 n=0~15 Conversion starts (Note)

11-9 Rev.1.0 (2) Scan mode In scan mode, the A-D converter sequentially A-D converts analog input voltages on specified channels (channel 0-15) selected with Scan Mode Register 1 scan loop select bits, beginning with the channel ADiIN0 (i = 0, 1). This mode further consists of "single-shot scan mode" in which A-D conversion is finished by performing one cycle of scan operation, and "continuous scan mode" in which scan operation is continued until it is halted by setting the Scan Mode Register A-D conversion stop bit to 1. Scan Mode Register 0 is used to select between these two scan modes. Also, the Scan Mode Register 1 scan loop select bits are used to select the channels to scan. The channels selected with the scan loop select bits (channels 0-15) beginning with the channel ADiIN0 comprise the scan loop, and this group of channels are sequentially scanned beginning with the channel ADiIN0. An A-D conversion interrupt request or DMA transfer request can be generated when one cycle of scan operation is finished. Figure 11.1.5 A-D Convert Operation in Scan Mode A-D CONVERTERS A-D conversion interrupt request or DMA transfer request ADiIN0 Finished here during single-shot scan mode ADiDT010-bit A-Di Data Register Conversion starts (Note) ADiIN1 ADiINn-1 ADiINn ADiDT1 ADiDTn-1 ADiDTn During continuous scan mode <n channel scan> i=0,1 n=0~15 Note: A-D0 conversion start: Software trigger → By setting the A-D0 conversion start bit to 1 Hardware trigger → By TOM0_6 underflow, input signal on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion A-D1 conversion start: Software trigger → By setting the A-D1 conversion start bit to 1 Hardware trigger → By TOM0_6 underflow, input signal on external pin TIN16, TOM1_6 underflow, or completion of A-D0 conversion

11-10 Rev.1.0 A-D CONVERTERS

• • •
• • •
• • •
• • • Table 11.1.2 A-D Conversion Result Storage Registers during Scan Mode Channels selected with Channels to be converted Channels to be converted A-D conversion result Scan Mode Register 1 in single-shot scan mode in continuous scan mode storage register B'0000 : 0 ADiIN0 ADiIN0 10-bit A-Di Data Register 0 (ADiIN0) Finishes ADiIN0 10-bit A-Di Data Register 0 (Repeated until forcibly terminated) B'0001 : 1 ADiIN0 ADiIN0 10-bit A-Di Data Register 0 (ADiIN1) ADiIN1 ADiIN1 10-bit A-Di Data Register 1 Finishes ADiIN0 10-bit A-Di Data Register 0 (Repeated until forcibly terminated) B'0010 : 2 ADiIN0 ADiIN0 10-bit A-Di Data Register 0 (ADiIN2) ADiIN1 ADiIN1 10-bit A-Di Data Register 1 ADiIN2 ADiIN2 10-bit A-Di Data Register 2 Finishes ADiIN0 10-bit A-Di Data Register 0 (Repeated until forcibly terminated) B'0011 : 3 ADiIN0 ADiIN0 10-bit A-Di Data Register 0 (ADiIN3) ADiIN1 ADiIN1 10-bit A-Di Data Register 1 ADiIN2 ADiIN2 10-bit A-Di Data Register 2 ADiIN3 ADiIN3 10-bit A-Di Data Register 3 Finishes ADiIN0 10-bit A-Di Data Register 0 (Repeated until forcibly terminated) B'XXXX : n ADiIN0 ADiIN0 10-bit A-Di Data Register 0 (ADiINn) ADiIN1 ADiIN1 10-bit A-Di Data Register 1 ADiIN2 ADiIN2 10-bit A-Di Data Register 2 n≤15 ADiINn ADiINn 10-bit A-Di Data Register n Finishes ADiIN0 10-bit A-Di Data Register 0 (Repeated until forcibly terminated) (i = 0, 1)

11-11 Rev.1.0

11.1.3 Special Operation Modes

(1) Forcibly execute single mode during scan mode operation In this special operation mode, the A-D converter forcibly executes single mode conversion (A-D conversion or comparate) on a specified channel while operating in scan mode. The conversion result is stored in the 10-bit A-D Data Register of the selected channel in the case of A-D conversion mode, or in the 10-bit A-D Comparate Data Register of the selected channel in the case of comparator mode. When A-D conversion or comparate on the specified channel finishes, scan mode A-D conversion restarts beginning with the channel that has been canceled during scan. To start single mode conversion in software during scan mode operation, select software trigger using the Single Mode Register 0's A-D conversion start trigger select bit and for A-D conversion, set the said register's A-D conversion start bit to 1. For comparate mode, write the value to be compared into the A-D Successive Approximation Register (AD0SAR or AD1SAR) while operating in scan mode. To start single mode conversion in hardware during scan mode operation, select hardware trigger using Single Mode Register 0's A-D conversion start trigger select bit and enter the hardware trigger selected with said register (TOM0_6 underflow, input on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion for the A-D0 Converter; TOM0_6 underflow, input on external pin TIN16, TOM1_6 underflow, or completion of A-D0 conversion for the A-D1 Converter). An A-D conversion interrupt request or DMA transfer request can be generated when conversion on the selected channel is finished or when one cycle of scan operation is finished. Figure 11.1.6 Forcibly Executing Single Mode during Scan Mode Operation A-D CONVERTERS A-D conversion interrupt request or DMA transfer request ADiIN0 ADiDT010-bit A-Di Data Register Scan mode conversion starts ADiIN1 ADiDT1 ADiDT5 Note: Conversion on channel 2 that has been aborted is reexecuted from the beginning. <When performing single mode conversion on ADiIN5 while converting ADiIN2 in n-channel single-shot scan mode> FinishesADiIN2 ADiINn ADiDT2 ADiDTn ADiIN5 Forcible single mode execution starts (Note)ADiIN2 i=0,1 n=0~15

11-12 Rev.1.0 (2) Start scan mode after executing single mode In this special operation mode, the A-D converter starts scan operation from single mode conversion (A-D conversion or comparate) in succession. To start in software, select software trigger using the Scan Mode Register 0's A-D conversion start trigger select bit and set the said register's A-D conversion start bit to 1 while performing single mode conversion. To start in hardware, select hardware trigger using Scan Mode Register 0's A-D conversion start trigger select bit and enter the hardware trigger selected with said register (TOM0_6 underflow, input on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion for the A- D0 Converter; TOM0_6 underflow, input on external pin TIN16, TOM1_6 underflow, or completion of A-D0 conversion for the A-D1 Converter) while performing single mode conversion. When a hardware trigger (TOM0_6 underflow, input on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion for the A-D0 Converter; TOM0_6 underflow, input on external pin TIN16, TOM1_6 underflow, or completion of A-D0 conversion for the A-D1 Converter) is entered after selecting it with the A-D conversion start trigger select bits of both Single Mode Register 0 and Scan Mode Register 0, single mode conversion is performed first and then after executing it, scan mode conversion is performed in succession. An A-D conversion interrupt request or DMA transfer request can be generated when single mode conversion on the selected channel is finished or when one cycle of scan operation is finished. Figure 11.1.7 Starting Scan Mode after Executing Single Mode A-D CONVERTERS A-D conversion interrupt request or DMA transfer request ADiIN0 ADiDT010-bit A-Di Data Register Instruction to start scan mode conversion ADiIN1 ADiDT1ADiDT5 <When starting n-channel scan/single-shot mode after executing single mode conversion on ADiIN5 in succession> FinishesADiINn-1 ADiINn ADiDTn-1 ADiDTn ADiIN5Single mode conversion starts i=0,1 n=0~15

11-13 Rev.1.0 (3) Restart conversion In this special operation mode, the A-D converter reexecutes single mode or scan mode operation from the beginning after stopping it while in progress. In the case of single mode, the operation being executed is reexecuted by setting Single Mode Register 0's A-D conversion start bit to 1 again or by entering a hardware trigger signal (TOM0_6 underflow, input on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion for the A-D0 Converter; TOM0_6 underflow, input on external pin TIN16, TOM1_6 underflow, or completion of A-D0 conversion for the A-D1 Converter) while A-D conversion or comparate is under way. For scan mode, the channel being converted is canceled and A-D conversion is restarted from channel 0 by setting Scan Mode Register 0's A-D conversion start bit to 1 again or by entering a hardware trigger signal (TOM0_6 underflow, input on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion for the A-D0 Converter; TOM0_6 underflow, input on external pin TIN16, TOM1_6 underflow, or completion of A-D0 conversion for the A-D1 Converter) while scan operation is under way. Figure 11.1.8 Restarting Conversion during Single Mode Operation Figure 11.1.9 Restarting Conversion during Scan Mode Operation A-D CONVERTERS A-D conversion interrupt request or DMA transfer request Single mode conversion on ADiIN5 starts ADiDT5 <Restarting single mode conversion on ADiIN5> Finishes Single mode on ADiIN5 restarts ADiIN5 ADiIN5 10-bit A-Di Data Register i=0,1 A-D conversion interrupt request or DMA transfer request ADiIN0 ADiDT010-bit A-Di Data Register Scan mode conversion starts ADiIN1 ADiDT1 <When restarting conversion while performing ADiIN2 conversion in n-channel scan/single-shot mode> FinishesADiINn-1 ADiINn ADiDTn-1 ADiDTn Scan mode restarts ADiIN2 ADiIN0 ADiDT0 ADiIN1 ADiDT1 i=0,1 n=0~15

11-14 Rev.1.0

11.1.4 Interrupt and DMA Transfer Requests by A-D Converters

The A-D converter can generate an A-D conversion interrupt request or DMA transfer request when A-D conversion, comparate, or single-shot scan is finished or each time one cycle of continuous scan mode is finished. To select between A-D conversion interrupt and DMA transfer requests to generate, use Single Mode Register 0 and Scan Mode Register 0. Figure 11.1.10 Selecting between A-D Conversion Interrupt and DMA Transfer Requests A-D CONVERTERS (when one cycle of scan is finished) Single mode (when A-D conversion or comparate is finished) A-D conversion interrupt request (to the Interrupt Controller) DMA transfer request (to the DMAC) A-Di Scan Mode Register 0's interrupt/ DMA transfer request select bit A-Di Single Mode Register 0's interrupt/ DMA transfer request select bit i=0,1

11-15 Rev.1.0

11.2 A-D Converter Related Registers

An A-D converter related register map is shown below. Figure 11.2.1 A-D Converter Related Register Map (1/4) A-D CONVERTERS H’0080 0084 H’0080 0086 H’0080 0088 H’0080 008A H’0080 008C H’0080 0080 H’0080 0082 A-D0 Single Mode Register 0 (AD0SIM0) Address D0 D7 +0 address +1 addressD8 D15 10-bit A-D0 Data Register0(AD0DT0) A-D0 Single Mode Register 1 (AD0SIM1) A-D0 Scan Mode Register 0 (AD0SCM0) A-D0 Scan Mode Register 1 (AD0SCM1) H’0080 0090 H’0080 0092 H’0080 0094 H’0080 0096 H’0080 0098 H’0080 009A H’0080 009C H’0080 009E 10-bit A-D0 Data Register1(AD0DT1) 10-bit A-D0 Data Register2(AD0DT2) 10-bit A-D0 Data Register3(AD0DT3) 10-bit A-D0 Data Register4(AD0DT4) 10-bit A-D0 Data Register5(AD0DT5) 10-bit A-D0 Data Register6(AD0DT6) 10-bit A-D0 Data Register7(AD0DT7) 10-bit A-D0 Data Register8(AD0DT8)H’0080 00A0 H’0080 00A2 H’0080 00A4 H’0080 00A6 H’0080 00A8 H’0080 00AA H’0080 00AC H’0080 00AE 10-bit A-D0 Data Register9(AD0DT9) 10-bit A-D0 Data Register10(AD0DT10) 10-bit A-D0 Data Register11(AD0DT11) 10-bit A-D0 Data Register12(AD0DT12) 10-bit A-D0 Data Register13(AD0DT13) 10-bit A-D0 Data Register14(AD0DT14) 10-bit A-D0 Data Register15(AD0DT15) Blank areas are reserved for future use. Note: The registers enclosed in the thick frames must always be accessed in halfwords. A-D0 Digital Input Control Register(AD0CHCON)H’0080 008E A-D0 Comparate Data Register(AD0CMP) A-D0 Successive Approximation Register(AD0SAR) A-D0 Conversion Speed Control Register (AD0CVSCR)

11-16 Rev.1.0 H'0080 00D2 H'0080 00D4 H'0080 00D6 H'0080 00D8 H'0080 00DA H'0080 00D0 D0 D7 D8 D15 H'0080 00DC H'0080 00DE H'0080 00E0 H'0080 00E2 H'0080 00E4 H'0080 00E6 H'0080 00E8 H'0080 00EA H'0080 00EC H'0080 00EE 8-bit A-D0 Data Register0 (AD08DT0) 8-bit A-D0 Data Register1 (AD08DT1) 8-bit A-D0 Data Register2 (AD08DT2) 8-bit A-D0 Data Register3 (AD08DT3) 8-bit A-D0 Data Register4 (AD08DT4) 8-bit A-D0 Data Register5 (AD08DT5) 8-bit A-D0 Data Register6 (AD08DT6) 8-bit A-D0 Data Register9 (AD08DT9) 8-bit A-D0 Data Register10 (AD08DT10) 8-bit A-D0 Data Register11 (AD08DT11) 8-bit A-D0 Data Register12 (AD08DT12) 8-bit A-D0 Data Register13 (AD08DT13) 8-bit A-D0 Data Register14 (AD08DT14) 8-bit A-D0 Data Register15 (AD08DT15) 8-bit A-D0 Data Register7 (AD08DT7) 8-bit A-D0 Data Register8 (AD08DT8) Blank areas are reserved for future use. Address +0 address +1 address Figure 11.2.2 A-D Converter Related Register Map (2/4) A-D CONVERTERS

11-17 Rev.1.0 H'0080 0A84 H'0080 0A86 H'0080 0A88 H'0080 0A8A H'0080 0A8C H'0080 0A80 H'0080 0A82 A-D1 Single Mode Register 0 (AD1SIM0) Address D0 D7 +0 address +1 addressD8 D15 10-bit A-D1 Data Register0(AD1DT0) A-D1 Single Mode Register 1 (AD1SIM1) A-D1 Scan Mode Register 0 (AD1SCM0) A-D1 Scan Mode Register 1 (AD1SCM1) H'0080 0A90 H'0080 0A92 H'0080 0A94 H'0080 0A96 H'0080 0A98 H'0080 0A9A H'0080 0A9C H'0080 0A9E 10-bit A-D1 Data Register1(AD1DT1) 10-bit A-D1 Data Register2(AD1DT2) 10-bit A-D1 Data Register3(AD1DT3) 10-bit A-D1 Data Register4(AD1DT4) 10-bit A-D1 Data Register5(AD1DT5) 10-bit A-D1 Data Register6(AD1DT6) 10-bit A-D1 Data Register7(AD1DT7) 10-bit A-D1 Data Register8(AD1DT8)H'0080 0AA0 H'0080 0AA2 H'0080 0AA4 H'0080 0AA6 H'0080 0AA8 H'0080 0AAA H'0080 0AAC H'0080 0AAE 10-bit A-D1 Data Register9(AD1DT9) 10-bit A-D1 Data Register10(AD1DT10) 10-bit A-D1 Data Register11(AD1DT11) 10-bit A-D1 Data Register12(AD1DT12) 10-bit A-D1 Data Register13(AD1DT13) 10-bit A-D1 Data Register14(AD1DT14) 10-bit A-D1 Data Register15(AD1DT15) Blank areas are reserved for future use. Note: The registers enclosed in the thick frames must always be accessed in halfwords. A-D1 Digital Input Control Register(AD1CHCON)H'0080 0A8E A-D1 Comparate Data Register(AD1CMP) A-D1 Successive Approximation Register(AD1SAR) A-D1 Conversion Speed Control Register (AD1CVSCR) Figure 11.2.3 A-D Converter Related Register Map (3/4) A-D CONVERTERS

11-18 Rev.1.0 H'0080 0AD2 H'0080 0AD4 H'0080 0AD6 H'0080 0AD8 H'0080 0ADA H'0080 0AD0 D0 D7 D8 D15 H'0080 0ADC H'0080 0ADE H'0080 0AE0 H'0080 0AE2 H'0080 0AE4 H'0080 0AE6 H'0080 0AE8 H'0080 0AEA H'0080 0AEC H'0080 0AEE 8-bit A-D1 Data Register0 (AD18DT0) 8-bit A-D1 Data Register1 (AD18DT1) 8-bit A-D1 Data Register2 (AD18DT2) 8-bit A-D1 Data Register3 (AD18DT3) 8-bit A-D1 Data Register4 (AD18DT4) 8-bit A-D1 Data Register5 (AD18DT5) 8-bit A-D1 Data Register6 (AD18DT6) 8-bit A-D1 Data Register9 (AD18DT9) 8-bit A-D1 Data Register10 (AD18DT10) 8-bit A-D1 Data Register11 (AD18DT11) 8-bit A-D1 Data Register12 (AD18DT12) 8-bit A-D1 Data Register13 (AD18DT13) 8-bit A-D1 Data Register14 (AD18DT14) 8-bit A-D1 Data Register15 (AD18DT15) 8-bit A-D1 Data Register7 (AD18DT7) 8-bit A-D1 Data Register8 (AD18DT8) Blank areas are reserved for future use. Address +0 address +1 address Figure 11.2.4 A-D Converter Related Register Map (4/4) A-D CONVERTERS

11-19 Rev.1.0

11.2.1 A-D Single Mode Registers 0

I A-D0 Single Mode Register 0 (AD0SIM0) <Address: H'0080 0080> D 0 123456 D 7 AD0STRG1 AD0STRG0 AD0SSEL AD0SREQ AD0SCMP AD0SSTP AD0SSTT <When reset: H'04> D Bit Name Function R W

0 AD0STRG1 (Note 1) Selects A-D0 hardware trigger

(A-D0 hardware trigger select 1) with D0 and D2 bits D0 D2 0 0: TOM0_6 underflow 0 1: TIN16 input 1 0: TOM0_0-7 enable event (Note 2) 1 1: A-D1 conversion finished

2 AD0STRG0 (Note 1) Selects A-D0 hardware trigger with D0

(A-D0 hardware trigger select 0) and D2 bits (see the column for D0 bit)

3 AD0SSEL 0: Software trigger

(Select A-D0 conversion start trigger) 1: Hardware trigger

4 AD0SREQ 0: A-D0 interrupt request

(Select interrupt request/DMA request) 1: DMA transfer request

5 AD0SCMP 0: A-D0 conversion/comparate in progress –

(A-D0 conversion/comparate complete) 1: A-D0 conversion/comparate completed

6 AD0SSTP 0: No operation 0

(Stop A-D0 conversion) 1: Stops A-D0 conversion

7 AD0SSTT 0: No operation 0

(Start A-D0 conversion) 1: Starts A-D0 conversion Note 1: To select a hardware trigger, use the D0 bit (A-D0 hardware trigger select 1) and D2 bit (A-D0 hardware trigger select 0). Note 2: This refers to TID0 overflow/underflow, TOM0_7 underflow, input on external pin TIN18, TID1 overflow/underflow, or TOM1_7 underflow. (For details, see Chapter 10, "Input/output Timers.") A-D0 Single Mode Register 0 is used to control operation of the A-D0 Converter during single mode (including special mode "Forcibly execute single mode during scan mode operation".) A-D CONVERTERS

11-20 Rev.1.0 I A-D1 Single Mode Register 0 (AD1SIM0) <Address: H'0080 0A80> <When reset: H'04> D Bit Name Function R W

0 AD1STRG1 (Note 1) Selects A-D1 hardware trigger

(A-D1 hardware trigger select 1) with D0 and D2 bits D0 D2 0 0: TOM0_6 underflow 0 1: TIN16 input 1 0: TOM1_6 underflow 1 1: A-D0 conversion finished

2 AD1STRG0 (Note) Selects A-D1 hardware trigger with D0

(A-D1 hardware trigger select 0) and D2 bits (see the column for D0 bit)

3 AD1SSEL 0: Software trigger

(Select A-D1 conversion start trigger) 1: Hardware trigger

4 AD1SREQ 0: A-D1 interrupt request

(Interrupt request) 1: DMA transfer request

5 AD1SCMP 0: A-D1 conversion/comparate in progress –

(A-D1 conversion/comparate complete)1: A-D1 conversion/comparate completed

6 AD1SSTP 0: No operation 0

(Stop A-D1 conversion) 1: Stops A-D1 conversion

7 AD1SSTT 0: No operation 0

(Start A-D1 conversion) 1: Starts A-D1 conversion Note: To select a hardware trigger, use the D0 bit (A-D1 hardware trigger select 1) and D2 bit (A-D1 hardware trigger select 0). D 0 123456 D 7 AD1STRG1 AD1STRG0 AD1SSEL AD1SREQ AD1SCMP AD1SSTP AD1SSTT A-D1 Single Mode Register 0 is used to control operation of the A-D1 Converter during single mode (including special mode "Forcibly execute single mode during scan mode operation".) A-D CONVERTERS

11-21 Rev.1.0 (1) ADnSTRG1 and ADnSTRG0 (A-Dn hardware trigger select) bits (D0, D2) When starting A-D conversion of the A-Dn converter in hardware, these bits select the cause for which to start conversion (TOM0_6 underflow, input on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion for A-D0; TOM0_6 underflow, input on external pin TIN16, TOM1_6 underflow, or completion of A-D0 conversion for A-D1). If software trigger is selected with the ADnSSEL (A-Dn conversion start trigger select) bit, the contents of these bits are ignored. (2) ADnSSEL (A-Dn conversion start trigger select) bit (D3) This bit selects whether to apply the A-Dn conversion start trigger in software or in hardware during single mode. When software trigger is selected, A-D conversion is started by setting the ADnSSTT (A-Dn conversion start) bit to 1. When hardware trigger is selected, A-D conversion is started by the cause of conversion selected with the ADnSTRG0 (hardware trigger select 0) and ADnSTRG1 (hardware trigger select 1) bits. (3) ADnSREQ (A-Dn interrupt request/DMA transfer request select) bit (D4) This bit selects whether to generate an A-Dn conversion interrupt request or a DMA transfer request at completion of A-Dn converter operation in single mode (A-D conversion or comparate). When using neither interrupt nor DMA transfer, select A-Dn conversion interrupt request and mask it with the ICU's A-Dn Converter Interrupt Control Register, or select DMA transfer and disable the DMA transfer to be started at completion of A-Dn conversion with the DMAn Channel Control Register. (4) ADnSCMP (A-Dn conversion/comparate complete) bit (D5) This is a read-only bit, and is 1 when reset. This bit is 0 when the A-Dn converter is operating in single mode (A-D conversion or comparate) and set to 1 when the operation is completed. It also is set to 1 when A-D convert or comparate operation is forcibly terminated by setting the ADnSSTT (A-Dn conversion stop) bit to 1 during A-D conversion or comparate. (5) ADnSSTP (A-Dn conversion stop) bit (D6) The A-Dn converter operating in single mode (A-D conversion or comparate) can be stopped by setting this bit to 1 while the operation is in progress. Manipulation of this bit is ignored while the converter when in single mode remains idle or is operating in scan mode. Operation is stopped immediately after writing to this bit, and when the content of the "A-Dn Successive Approximation Register" is read after stopping the operation, it shows an intermediate value that was in the middle of conversion. (No transfers to the A-Dn Data Register are performed.) A-D CONVERTERS

11-22 Rev.1.0 If the A-Dn conversion start and A-Dn conversion stop bits are set to 1 simultaneously, the latter has priority so that the A-Dn conversion is stopped. If this bit is set to 1 while single mode operation in special mode "Forcibly execute single mode during scan mode operation" is under way, only single mode conversion stops and scan mode operation restarts. (6) ADnSSTT (A-Dn conversion start) bit (D7) A-D conversion of the A-Dn converter is started by setting this bit to 1 while software trigger has been selected with the ADnSSEL (A-Dn conversion start trigger select) bit. If the A-Dn conversion start and A-Dn conversion stop bits are set to 1 simultaneously, the latter has priority so that the A-Dn conversion is stopped. When this bit is set to 1 during single mode conversion, special operation mode "Restart conversion" is assumed, so that conversion in single mode restarts. When this bit is set to 1 during A-D conversion in scan mode, special operation mode "Forcibly execute single mode during scan mode operation" is assumed, so that the channel being converted in scan mode is canceled and single mode conversion is performed. When single mode conversion finishes, A-D conversion in scan mode restarts from the canceled channel. A-D CONVERTERS

11-23 Rev.1.0

11.2.2 A-D Single Mode Registers 1

I A-D0 Single Mode Register 1 (AD0SIM1) <Address: H'0080 0081> D 8 9 1 01 11 21 31 4 D 1 5 AD0SMSL AD0SSPD AN0SEL <When reset: H'00> D Bit Name Function R W

8 AD0SMSL 0: A-D0 conversion mode

(Select A-D0 conversion mode) 1: Comparator mode

9 AD0SSPD (Note 1) 0: Normal

(Select A-D0 conversion speed) 1: Double speed 10,11 No functions assigned 0 12-15 AN0SEL (Note 2) 0000: Selects AD0IN0 (Select analog input pin) 0001: Selects AD0IN1 0010: Selects AD0IN2 0011: Selects AD0IN3 0100: Selects AD0IN4 0101: Selects AD0IN5 0110: Selects AD0IN6 0111: Selects AD0IN7 1000: Selects AD0IN8 1001: Selects AD0IN9 1010: Selects AD0IN10 1011: Selects AD0IN11 1100: Selects AD0IN12 1101: Selects AD0IN13 1110: Selects AD0IN14 1111: Selects AD0IN15 W= : Writing 0 only is effective. Writing 1 to these bits is unaccepted, the device operation cannot be guaranteed. Note 1: Because the A-D0 conversion speed is determined by a combined use of this AD0SSPD bit and the A-D0 Conversion Speed Control Register AD0CVSD bit, make sure the AD0SSPD and AD0CVSD bits both are set. Note 2: When AD0IN8-AD0IN15 are selected, the A-D0 Digital Input Control Register needs to be set. A-D0 Single Mode Register 1 is used to control operation of the A-D0 Converter during single mode (including special mode "Forcibly execute single mode during scan mode operation".) A-D CONVERTERS

11-24 Rev.1.0 I A-D1 Single Mode Register 1 (AD1SIM1) <Address: H'0080 0A81> <When reset: H'00> D Bit Name Function R W

8 AD1SMSL 0: A-D1 conversion mode

(Select A-D1 conversion mode) 1: Comparator mode

9 AD1SSPD (Note 1) 0: Normal

(Select A-D1 conversion speed) 1: Double speed 10,11 No functions assigned 0 12-15 AN1SEL (Note 2) 0000: Selects AD1IN0 (Select analog input pin) 0001: Selects AD1IN1 0010: Selects AD1IN2 0011: Selects AD1IN3 0100: Selects AD1IN4 0101: Selects AD1IN5 0110: Selects AD1IN6 0111: Selects AD1IN7 1000: Selects AD1IN8 1001: Selects AD1IN9 1010: Selects AD1IN10 1011: Selects AD1IN11 1100: Selects AD1IN12 1101: Selects AD1IN13 1110: Selects AD1IN14 1111: Selects AD1IN15 W= : Writing 0 only is effective. Writing 1 to these bits is unaccepted, the device operation cannot be guaranteed. Note 1: Because the A-D1 conversion speed during single mode is determined by a combined use of this AD1SSPD bit and the A-D1 Conversion Speed Control Register AD1CVSD bit, make sure the AD1SSPD and AD1CVSD bits both are set. Note 2: When AD1IN4-AD1IN15 are selected, the A-D1 Digital Input Control Register needs to be set. A-D1 Single Mode Register 1 is used to control operation of the A-D1 Converter during single mode (including special mode "Forcibly execute single mode during scan mode operation".) D 8 9 1 01 11 21 31 4 D 1 5 AD1SMSL AD1SSPD AN1SEL A-D CONVERTERS

11-25 Rev.1.0 (1) ADnSMSL (A-Dn conversion mode select) bit (D8) This bit selects A-D conversion mode when the A-Dn converter is operating in single mode. Setting this bit to 0 selects A-D conversion mode; setting this bit to 1 selects comparator mode. (2) ADnSSPD (A-Dn conversion speed select) bit (D9) This bit selects the A-D conversion speed when the A-Dn converter is operating in single mode. Setting this bit to 0 selects normal speed; setting this bit to 1 selects double speed. Note: Because the A-Dn conversion speed during single mode is determined by a combined use of this ADnSSPD bit and the A-Dn Conversion Speed Control Register ADnCVSD bit, make sure the ADnSSPD and ADnCVSD bits both are set. (3) ANnSEL (analog input pin select) bits (D12-D15) These bits select an analog input pin when the A-Dn converter is operating in single mode. The channel selected with this bit is the target channel on which A-D conversion or comparate operation is performed. When read, this bit shows the value that has been written to it. A-D CONVERTERS

11-26 Rev.1.0

11.2.3 A-D Scan Mode Registers 0

I A-D0 Scan Mode Register 0 (AD0SCM0) <Address: H'0080 0084> D 0 123456 D 7 AD0CTRG1 AD0CMSL AD0CTRG0 AD0CSEL AD0CREQ AD0CCMP AD0CSTP AD0CSTT <When reset: H'04> D Bit Name Function R W

0 AD0CTRG1 (Note 1) Selects A-D0 hardware trigger with

(A-D0 hardware trigger select 1) D0 and D2 bits D0 D2 0 0: TOM0_6 underflow 0 1: TIN16 input 1 0: TOM0_0-7 enable event (Note 2) 1 1: A-D1 conversion finished

1 AD0CMSL 0: Single-shot mode

(Select A-D0 scan mode) 1: Continuous mode

2 AD0CTRG0 (Note 1) Selects A-D0 hardware trigger with D0

(A-D0 hardware trigger select 0) and D2 bits (see the column for D0 bit)

3 AD0CSEL 0: Software trigger

(Select A-D0 conversion start trigger) 1: Hardware trigger

4 AD0CREQ 0: A-D0 interrupt request

(Select interrupt request/DMA request)1: DMA transfer request

5 AD0CCMP 0: A-D0 conversion in progress –

(A-D0 conversion complete) 1: A-D0 conversion completed

6 AD0CSTP 0: No operation 0

(Stop A-D0 conversion) 1: Stops A-D0 conversion

7 AD0CSTT 0: No operation 0

(Start A-D0 conversion) 1: Starts A-D0 conversion Note 1: To select a hardware trigger, use the D0 bit (A-D0 hardware trigger select 1) and D2 bit (A-D0 hardware trigger select 0). Note 2: This refers to TID0 overflow/underflow, TOM0_7 underflow, input on external pin TIN18, TID1 overflow/underflow, or TOM1_7 underflow. (For details, see Chapter 10, "Input/output Timers.") A-D0 Scan Mode Register 0 is used to control operation of the A-D0 Converter during scan mode. A-D CONVERTERS

11-27 Rev.1.0 I A-D1 Scan Mode Register 0 (AD1SCM0) <Address: H'0080 0A84> <When reset: H'04> D Bit Name Function R W

0 AD1CTRG1 (Note 1) Selects A-D1 hardware trigger with

(A-D1 hardware trigger select 1) D0 and D2 bits D0 D2 0 0: TOM0_6 underflow 0 1: TIN16 input 1 0: TOM1_6 underflow 1 1: A-D0 conversion finished

1 AD1CMSL 0: Single-shot mode

(Select A-D1 scan mode) 1: Continuous mode

2 AD1CTRG0 (Note) Selects A-D1 hardware trigger with D0

(A-D1 hardware trigger select 0)and D2 bits (see the column for D0 bit)

3 AD1CSEL 0: Software trigger

(Select A-D1 conversion start trigger) 1: Hardware trigger

4 AD1CREQ 0: A-D1 interrupt request

(interrupt request) 1: DMA transfer request

5 AD1CCMP 0: A-D1 conversion in progress –

(A-D1 conversion complete) 1: A-D1 conversion completed

6 AD1CSTP 0: No operation 0

(Stop A-D1 conversion) 1: Stops A-D1 conversion

7 AD1CSTT 0: No operation 0

(Start A-D1 conversion) 1: Starts A-D1 conversion Note: To select a hardware trigger, use the D0 bit (A-D0 hardware trigger select 1) and D2 bit (A-D0 hardware trigger select 0). A-D1 Scan Mode Register 0 is used to control operation of the A-D1 Converter during scan mode. D 0 123456 D 7 AD1CTRG1 AD1CMSL AD1CTRG0 AD1CSEL AD1CREQ AD1CCMP AD1CSTP AD1CSTT A-D CONVERTERS

11-28 Rev.1.0 (1) ADnCTRG1 and ADnCTRG0 (A-Dn hardware trigger select) bits (D0, D2) When starting A-D conversion of the A-Dn converter in hardware, these bits select the cause for which to start conversion (TOM0_6 underflow, input on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion for A-D0; TOM0_6 underflow, input on external pin TIN16, TOM1_6 underflow, or completion of A-D0 conversion for A-D1). If software trigger is selected with the ADnCSEL (A-Dn conversion start trigger select) bit, the contents of these bits are ignored. (2) ADnCMSL (A-Dn scan mode select) bit (D1) This bit selects the A-Dn converter scan mode between single-shot scan and continuous scan modes. Setting this bit to 0 selects single-shot scan mode, so that A-D conversion of channels selected with the ANnSCAN (scan loop select) bits are performed sequentially, beginning with the channel ADnIN0. When A-D conversion on all selected channels is completed, the convert operation stops. Setting this bit to 1 selects continuous scan mode, so that when operation in single-shot scan mode finishes, A-D conversion is performed from the first channel again. This is repeated until stopped by setting the ADnCSTP (A-Dn conversion stop) bit to 1. (3) ADnCSEL (A-Dn conversion start trigger select) bit (D3) This bit selects whether to apply the A-D conversion start trigger in software or in hardware during scan mode of the A-Dn converter. When software trigger is selected, A-D conversion is started by setting the ADnCSTT (A-Dn conversion start) bit to 1. When hardware trigger is selected, A-D conversion is started by the cause of conversion selected with the ADnCTRG0 (hardware trigger select 0) and ADnCTRG1 (hardware trigger select 1) bits. (4) ADnCREQ (A-Dn interrupt/DMA transfer request select) bit (D4) This bit selects whether to generate an A-Dn conversion interrupt request or a DMA transfer request when one cycle of scan mode operation is finished. When using neither interrupt nor DMA transfer, select A-Dn conversion interrupt request and mask it with the ICU's A-Dn Converter Interrupt Control Register, or select DMA transfer and disable the DMA transfer to be started at completion of A-Dn conversion with the DMAn Channel Control Register. A-D CONVERTERS

11-29 Rev.1.0 (5) ADnCCMP (A-Dn conversion complete) bit (D5) This is a read-only bit, and is 1 when reset. This bit is 0 when scan mode conversion of the A-Dn converter is in progress and set to 1 when single-shot scan mode is completed or when continuous scan mode is stopped by setting the ADnCSTT (A-Dn conversion stop) bit to 1. (6) ADnCSTP (A-Dn conversion stop) bit (D6) Scan mode A-D conversion with the A-Dn converter can be stopped by setting this bit to 1 while operation is under way. This bit is effective for only scan mode operation, and does not affect single mode operation when both single and scan modes are activated in special operation mode. Operation is stopped immediately after writing to this bit and A-C conversion on the channel which is in the middle of conversion is aborted, with no data transferred to the A-D Data Register. If the A-Dn conversion start and A-Dn conversion stop bits are set to 1 simultaneously, the latter has priority so that the A-Dn conversion is stopped. (7) ADnCSTT (A-Dn conversion start) bit (D7) This bit is used to start scan mode of the A-Dn converter in software. Only when software trigger has been selected with the ADnCSEL (A-Dn conversion start trigger select) bit, A-D conversion can be started by setting this bit to 1. If the A-Dn conversion start and A-Dn conversion stop bits are set to 1 simultaneously, the latter has priority so that the A-Dn conversion is stopped. When this bit is set to 1 during scan mode conversion again, special operation mode "Restart conversion" is assumed, so that scan operation restarts according to the contents set by Scan Mode Register 0 and Scan Mode Register 1. When this bit is set to 1 during single mode A-D conversion, special operation mode "Start scan mode after executing single mode" is assumed, so that scan mode operation starts in succession after single mode finishes. A-D CONVERTERS

11-30 Rev.1.0

11.2.4 A-D Scan Mode Registers 1

I A-D0 Scan Mode Register 1 (AD0SCM1) <Address: H'0080 0085> D 8 9 1 01 11 21 31 4 D 1 5 AD0CSPD AN0SCAN <When reset: H'00> D Bit Name Function R W

9 AD0CSPD (Note 1) 0: Normal

(Select A-D0 conversion speed) 1: Double speed 10,11 No functions assigned 0 – 12-15 AN0SCAN (Note 2) <When writing> (Select A-D0 scan loop) B'0000-B'1111 (Channel 0 through channel 15) <When read during conversion> 0000: AD0IN0 being converted 0001: AD0IN1 being converted 0010: AD0IN2 being converted 0011: AD0IN3 being converted 0100: AD0IN4 being converted 0101: AD0IN5 being converted 0110: AD0IN6 being converted 0111: AD0IN7 being converted 1000: AD0IN8 being converted 1001: AD0IN9 being converted 1010: AD0IN10 being converted 1011: AD0IN11 being converted 1100: AD0IN12 being converted 1101: AD0IN13 being converted 1110: AD0IN14 being converted 1111: AD0IN15 being converted Note 1: Because the A-D0 conversion speed during scan mode is determined by a combined use of this AD0CSPD bit and the A-D0 Conversion Speed Control Register AD0CVSD bit, make sure the AD0CSPD and AD0CVSD bits both are set. Note 2: If the scan loop includes any channels AD0IN8-AD0IN15, the AD0 Digital Input Control Register needs to be set. A-D0 Scan Mode Register 1 is used to control operation of the A-D0 Converter during scan mode. A-D CONVERTERS

11-31 Rev.1.0 I A-D1 Scan Mode Register 1 (AD1SCM1) <Address: H'0080 0A85> <When reset: H'00> D Bit Name Function R W

9 AD1CSPD (Note 1) 0: Normal

(Select A-D1 conversion speed) 1: Double speed 10,11 No functions assigned 0 – 12-15 AN1SCAN (Note 2) <When writing> (Select A-D1 scan loop) B'0000-B'1111 (Channel 0 through channel 15) <When read during conversion> 0000: AD1IN0 being converted 0001: AD1IN1 being converted 0010: AD1IN2 being converted 0011: AD1IN3 being converted 0100: AD1IN4 being converted 0101: AD1IN5 being converted 0110: AD1IN6 being converted 0111: AD1IN7 being converted 1000: AD1IN8 being converted 1001: AD1IN9 being converted 1010: AD1IN10 being converted 1011: AD1IN11 being converted 1100: AD1IN12 being converted 1101: AD1IN13 being converted 1110: AD1IN14 being converted 1111: AD1IN15 being converted Note 1: Because the A-D1 conversion speed during scan mode is determined by a combined use of this AD1CSPD bit and the A-D1 Conversion Speed Control Register AD1CVSD bit, make sure the AD1CSPD and AD1CVSD bits both are set. Note 2: If the scan loop includes any channels AD1IN4-AD1IN15, the AD1 Digital Input Control Register needs to be set. A-D1 Scan Mode Register 1 is used to control operation of the A-D1 Converter during scan mode. D 8 9 1 01 11 21 31 4 D 1 5 AD1CSPD AN1SCAN A-D CONVERTERS

11-32 Rev.1.0 (1) ADnCSPD (A-Dn conversion speed select) bit (D9) This bit selects the A-D conversion speed when the A-Dn converter is operating in scan mode. Setting this bit to 0 selects normal speed; setting this bit to 1 selects double speed. Note: Because the A-Dn conversion speed during scan mode is determined by a combined use of this ADnCSPD bit and the A-Dn Conversion Speed Control Register ADnCVSD bit, make sure the ADnCSPD and ADnCVSD bits both are set. (2) ANnSCAN (A-Dn scan loop select) bits (D12-D15) These bits select a range of channels by channel number beginning with the channel ADnIN0 which are to be operated on during scan mode operation with the A-Dn converter. (For details about the scan loop configuration by specified channel numbers, see Table 11.1.2.) When the ANnSCAN (A-Dn scan loop select) bits are read out during scan operation, they serve as status bits indicating the channel being converted. When read during single mode, these bits always show the value "B'0000." If these bits are read when the A-D conversion is stopped by setting the Scan Mode Register 0 ADnCSTP (A-Dn conversion stop) bit to 1, they show the value of the channel that has been canceled of A-D convert operation. Also, when read during single mode conversion in special operation mode "Forcibly execute single mode during scan mode operation," they show the value of the channel that has been canceled of A-D convert operation in the middle of scan. A-D CONVERTERS

11-33 Rev.1.0

11.2.5 A-D Conversion Speed Control Registers

I A-D0 Conversion Speed Control Register (AD0CVSCR) <Address: H'0080 0087> D 8 9 1 01 11 21 31 4 D 1 5 AD0CVSD <When reset: H'00> D Bit Name Function R W 8-14 No functions assigned 0 –

15 AD0CVSD (Note) 0: Low speed mode

(Control A-D0 conversion seed) 1: High speed mode Note: The A-D0 conversion speed is determined by a combined use of this AD0CVSD bit and the A-D0 Single Mode Register 1 AD0SSPD bit when operating in single mode, or a combined use of this AD0CVSD bit and the A-D0 Scan Mode Register 1 AD0CSPD bit when operating in scan mode. Be sure to set the AD0CVSD and AD0SSPD bits during single mode, or the AD0CVSD and AD0CSPD bits during scan mode. I A-D1 Conversion Speed Control Register (AD1CVSCR) <Address: H'0080 0A87> <When reset: H'00> D Bit Name Function R W 8-14 No functions assigned 0 –

15 AD1CVSD (Note) 0: Low speed mode

(Control A-D1 conversion seed) 1: High speed mode Note: The A-D1 conversion speed is determined by a combined use of this AD1CVSD bit and the A-D1 Single Mode Register 1 AD1SSPD bit when operating in single mode, or a combined use of this AD1CVSD bit and the A-D1 Scan Mode Register 1 AD1CSPD bit when operating in scan mode. Be sure to set the AD1CVSD and AD1SSPD bits during single mode, or the AD1CVSD and AD1CSPD bits during scan mode. D 8 9 1 01 11 21 31 4 D 1 5 AD1CVSD A-D CONVERTERS

11-34 Rev.1.0 (1) ADnCSPD (A-Dn conversion speed select) bit (D15) This bit controls the A-D conversion speed of the A-Dn converter during single or scan mode. Setting this bit to 0 selects low speed mode; setting this bit to 1 selects high speed mode. Note: The A-Dn conversion speed is determined by a combined use of this ADnCVSD bit and the A-Dn Single Mode Register 1 ADnSSPD bit when operating in single mode, or a combined use of this ADnCVSD bit and the A-Dn Scan Mode Register 1 ADnCSPD bit when operating in scan mode. Be sure to set the ADnCVSD and ADnSSPD bits during single mode, or the ADnCVSD and ADnCSPD bits during scan mode. A-D CONVERTERS

11-35 Rev.1.0

11.2.6 A-D Digital Input Control Registers

I A-D0 Digital Input Control Register (AD0CHCON) <Address: H'0080 008E> <When reset: H'00> D Bit Name Function R W 0-7 No functions assigned (Note 1) 8-15 AD0CH8CN-AD0CH15CN 0: Disables input to AD0CHnCN (AD0 channel 8-15 input enable bit) 1: Enables input to AD0CHnCN Note 1: The D0-D7 bits are blank bits. When read, they show the values written to them. Note 2: The D8-D15 bits correspond one for one to channels 8 through channel 15. The analog inputs AD0IN8-AD0IN15 to the A-D0 Converter may be used to monitor input ports or internal peripheral I/O pins. When using the analog input pins AD0IN8-AD0IN15, set any bit D8- D15 to 1 that corresponds to the analog input pin used. However, the analog inputs AD0IN8-AD0IN15 do not have the conversion accuracy comparable to that of the dedicated analog input pins AD0IN0-AD0IN7. I A-D1 Digital Input Control Register (AD1CHCON) <Address: H'0080 0A8E> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD1C H12CN AD1C H11CN AD1C H9CN AD1C H8CN AD1C H15CN AD1C H14CN AD1C H13CN AD1C H10CN AD1C H6CN AD1C H7CN D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD0C H12CN AD0C H11CN AD0C H9CN AD0C H8CN AD0C H15CN AD0C H14CN AD0C H13CN AD0C H10CN <When reset: H'00> D Bit Name Function R W 0-5 No functions assigned (Note 2) 6-15 AD1CH8CN-AD1CH15CN 0: Disables input to AD1CHnCN (AD1 channel 6-15 input enable bit) 1: Enables input to AD1CHnCN Note 1: The D0-D5 bits are blank bits. When read, they show the values written to them. Note 2: The D6-D15 bits correspond one for one to channels 6 through channel 15. The analog inputs AD1IN4-AD1IN15 to the A-D1 Converter may be used to monitor input ports or internal peripheral I/O pins. When using the analog input pins AD1IN6-AD1IN15, set any bit D6- D15 to 1 that corresponds to the analog input pin used. However, the analog inputs AD1IN4-AD1IN15 do not have the conversion accuracy comparable to that of the dedicated analog input pins AD1IN0-AD1IN3. A-D CONVERTERS

11-36 Rev.1.0 D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD0SAR

11.2.7 A-D Successive Approximation Registers

I A-D0 Successive Approximation Register (AD0SAR) <Address: H'0080 0088> <When reset: indeterminate> D Bit Name Function R W 0-5 No functions assigned 0 – 6-15 AD0SAR  A-D0 successive approximation value (A-D0 successive approximation (A-D conversion mode) value/comparison value)  Comparison value (comparator mode) Note: This register must always be accessed in halfwords. The A-D0 Successive Approximation Register (AD0SAR) is used to read the conversion result of the A-D0 Converter when operating in A-D conversion mode or write a comparison value when operating in comparator mode. In A-D conversion mode, the A-D conversion is performed based on the successive approximation method. In this method, the reference voltage VREF and analog input voltages are compared bitwise sequentially beginning with the most significant bit, and the result is set in the A-D0 Successive Approximation Register (AD0SAR)'s each corresponding bit (D6-D15). When the A-D conversion finishes, the value of this register is transferred to the 10-bit A-D0 Data Register (AD0DTn) corresponding to the converted channel. When this register is read in the middle of A-D conversion, it shows an intermediate result of conversion. In comparator mode, this register has a comparison value (the comparison voltage to "comparate") written in it. Comparate operation with the analog input pins set with Single Mode Register 1 is started upon writing to this register. When the comparate operation finishes, the result is stored in the A-D0 Comparate Data Register (AD0CMP). The comparison value written to the A-D0 Successive Approximation Register (AD0SAR) during comparator mode is calculated by the equation below. A-D CONVERTERS Comparison value = H' 3FF × Comparison voltage to comparate [V] VREF0 input voltage [V]

11-37 Rev.1.0 I A-D1 Successive Approximation Register (AD1SAR) <Address: H'0080 0A88> <When reset: indeterminate> D Bit Name Function R W 0-5 No functions assigned 0 – 6-15 AD1SAR  A-D successive approximation value (A-D1 successive approximation (A-D conversion mode) value/comparison value)  Comparison value (comparator mode) Note: This register must always be accessed in halfwords. The A-D1 Successive Approximation Register (AD1SAR) is used to read the conversion result of the A-D1 Converter when operating in A-D conversion mode or write a comparison value when operating in comparator mode. In A-D conversion mode, the A-D conversion is performed based on the successive approximation method. In this method, the reference voltage VREF and analog input voltages are compared bitwise sequentially beginning with the most significant bit, and the result is set in the A-D1 Successive Approximation Register (AD1SAR)'s each corresponding bit (D6-D15). When the A-D conversion finishes, the value of this register is transferred to the 10-bit A-D1 Data Register (AD1DTn) corresponding to the converted channel. When this register is read in the middle of A-D conversion, it shows an intermediate result of conversion. In comparator mode, this register has a comparison value (the comparison voltage to "comparate") written in it. Comparate operation with the analog input pins set with Single Mode Register 1 is started upon writing to this register. When the comparate operation finishes, the result is stored in the A-D1 Comparate Data Register (AD1CMP). The comparison value written to the A-D1 Successive Approximation Register (AD1SAR) during comparator mode is calculated by the equation below. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD1SAR A-D CONVERTERS Comparison value = H' 3FF × Comparison voltage to comparate [V] VREF1 input voltage [V]

11-38 Rev.1.0

11.2.8 A-D Comparate Data Registers

I A-D0 Comparate Data Register (AD0CMP) <Address: H'0080 008C> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD0 CMP12 AD0 CMP11 AD0 CMP9 AD0 CMP8 AD0 CMP7 AD0 CMP5 AD0 CMP4 AD0 CMP3 AD0 CMP2 AD0 CMP1 AD0 CMP0 AD0 CMP15 AD0 CMP14 AD0 CMP13 AD0 CMP10 AD0 CMP6 <When reset: indeterminate> D Bit Name Function R W 0-15 AD0CMP0 AD0CMP15 0: Analog input voltage > comparison voltage– (A-D0 comparate result flag) 1: Analog input voltage < comparison voltage Note 1: This register must always be accessed in halfwords. Note 2: During comparator mode, each bit of this register corresponds to channel 0 through channel 15. When comparator mode is selected with A-D0 Single Mode Register 1 AD0SMSL (A-D0 conversion mode select) bit, the selected analog input value and the value written to the A-D0 Successive Approximation Register are compared and the result is stored in this register's corresponding bit. The result flag is 0 when the analog input voltage > comparison voltage, or 1 when the analog input voltage < comparison voltage. A-D CONVERTERS

11-39 Rev.1.0 I A-D1 Comparate Data Register (AD1CMP) <Address: H'0080 0A8C> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD1 CMP12 AD1 CMP11 AD1 CMP9 AD1 CMP8 AD1 CMP7 AD1 CMP5 AD1 CMP4 AD1 CMP3 AD1 CMP2 AD1 CMP1 AD1 CMP0 AD1 CMP15 AD1 CMP14 AD1 CMP13 AD1 CMP10 AD1 CMP6 <When reset: indeterminate> D Bit Name Function R W 0-15 AD1CMP0 AD1CMP15 0: Analog input voltage > comparison voltage– (A-D1 comparate result flag) 1: Analog input voltage < comparison voltage Note 1: This register must always be accessed in halfwords. Note 2: During comparator mode, each bit of this register corresponds to channel 0 through channel 15. When comparator mode is selected with A-D1 Single Mode Register 1 AD1SMSL (A-D1 conversion mode select) bit, the selected analog input value and the value written to the A-D1 Successive Approximation Register are compared and the result is stored in this register's corresponding bit. The result flag is 0 when the analog input voltage > comparison voltage, or 1 when the analog input voltage < comparison voltage. A-D CONVERTERS

11-40 Rev.1.0 11.2.9 10-bit A-D Data Registers I 10-bit A-D0 Data Register 0 (AD0DT0) <Address: H'0080 0090> I 10-bit A-D0 Data Register 1 (AD0DT1) <Address: H'0080 0092> I 10-bit A-D0 Data Register 2 (AD0DT2) <Address: H'0080 0094> I 10-bit A-D0 Data Register 3 (AD0DT3) <Address: H'0080 0096> I 10-bit A-D0 Data Register 4 (AD0DT4) <Address: H'0080 0098> I 10-bit A-D0 Data Register 5 (AD0DT5) <Address: H'0080 009A> I 10-bit A-D0 Data Register 6 (AD0DT6) <Address: H'0080 009C> I 10-bit A-D0 Data Register 7 (AD0DT7) <Address: H'0080 009E> I 10-bit A-D0 Data Register 8 (AD0DT8) <Address: H'0080 00A0> I 10-bit A-D0 Data Register 9 (AD0DT9) <Address: H'0080 00A2> I 10-bit A-D0 Data Register 10 (AD0DT10) <Address: H'0080 00A4> I 10-bit A-D0 Data Register 11 (AD0DT11) <Address: H'0080 00A6> I 10-bit A-D0 Data Register 12 (AD0DT12) <Address: H'0080 00A8> I 10-bit A-D0 Data Register 13 (AD0DT13) <Address: H'0080 00AA> I 10-bit A-D0 Data Register 14 (AD0DT14) <Address: H'0080 00AC> I 10-bit A-D0 Data Register 15 (AD0DT15) <Address: H'0080 00AE> <When reset: indeterminate> D Bit Name Function R W 0-5 No functions assigned 0 – 6-15 AD0DT0-AD0DT15 A-D conversion result – (A-D0 data) Note: These registers must always be accessed in halfwords. In A-D0 Converter single mode, the result of A-D conversion is stored in the 10-bit A-D0 Data Register of the corresponding channel. In single-shot or continuous scan mode, each time A-D conversion on a channel is finished, the content of the A-D0 Successive Approximation Register is transferred to the 10-bit A-D Data Register of the corresponding channel. Each 10-bit A-D Data Register holds the last conversion result until they receive the next conversion result transferred, so that the register content can be read out anytime. A-D CONVERTERS D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD0DT0-AD0DT15

11-41 Rev.1.0 I 10-bit A-D1 Data Register 0 (AD1DT0) <Address: H'0080 0A90> I 10-bit A-D1 Data Register 1 (AD1DT1) <Address: H'0080 0A92> I 10-bit A-D1 Data Register 2 (AD1DT2) <Address: H'0080 0A94> I 10-bit A-D1 Data Register 3 (AD1DT3) <Address: H'0080 0A96> I 10-bit A-D1 Data Register 4 (AD1DT4) <Address: H'0080 0A98> I 10-bit A-D1 Data Register 5 (AD1DT5) <Address: H'0080 0A9A> I 10-bit A-D1 Data Register 6 (AD1DT6) <Address: H'0080 0A9C> I 10-bit A-D1 Data Register 7 (AD1DT7) <Address: H'0080 0A9E> I 10-bit A-D1 Data Register 8 (AD1DT8) <Address: H'0080 0AA0> I 10-bit A-D1 Data Register 9 (AD1DT9) <Address: H'0080 0AA2> I 10-bit A-D1 Data Register 10 (AD1DT10) <Address: H'0080 0AA4> I 10-bit A-D1 Data Register 11 (AD1DT11) <Address: H'0080 0AA6> I 10-bit A-D1 Data Register 12 (AD1DT12) <Address: H'0080 0AA8> I 10-bit A-D1 Data Register 13 (AD1DT13) <Address: H'0080 0AAA> I 10-bit A-D1 Data Register 14 (AD1DT14) <Address: H'0080 0AAC> I 10-bit A-D1 Data Register 15 (AD1DT15) <Address: H'0080 0AAE> <When reset: indeterminate> D Bit Name Function R W 0-5 No functions assigned 0 – 6-15 AD1DT0-AD1DT15 A-D conversion result – (A-D1 data) Note: These registers must always be accessed in halfwords. In A-D1 Converter single mode, the result of A-D conversion is stored in the 10-bit A-D1 Data Register of the corresponding channel. In single-shot or continuous scan mode, each time A-D conversion on a channel is finished, the content of the A-D1 Successive Approximation Register is transferred to the 10-bit A-D Data Register of the corresponding channel. Each 10-bit A-D Data Register holds the last conversion result until they receive the next conversion result transferred, so that the register content can be read out anytime. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 AD1DT0-AD1DT15 A-D CONVERTERS

11-42 Rev.1.0 11.2.10 8-bit A-D Data Registers I 8-bit A-D0 Data Register 0 (AD08DT0) <Address: H'0080 00D1> I 8-bit A-D0 Data Register 1 (AD08DT1) <Address: H'0080 00D3> I 8-bit A-D0 Data Register 2 (AD08DT2) <Address: H'0080 00D5> I 8-bit A-D0 Data Register 3 (AD08DT3) <Address: H'0080 00D7> I 8-bit A-D0 Data Register 4 (AD08DT4) <Address: H'0080 00D9> I 8-bit A-D0 Data Register 5 (AD08DT5) <Address: H'0080 00DB> I 8-bit A-D0 Data Register 6 (AD08DT6) <Address: H'0080 00DD> I 8-bit A-D0 Data Register 7 (AD08DT7) <Address: H'0080 00DF> I 8-bit A-D0 Data Register 8 (AD08DT8) <Address: H'0080 00E1> I 8-bit A-D0 Data Register 9 (AD08DT9) <Address: H'0080 00E3> I 8-bit A-D0 Data Register 10 (AD08DT10) <Address: H'0080 00E5> I 8-bit A-D0 Data Register 11 (AD08DT11) <Address: H'0080 00E7> I 8-bit A-D0 Data Register 12 (AD08DT12) <Address: H'0080 00E9> I 8-bit A-D0 Data Register 13 (AD08DT13) <Address: H'0080 00EB> I 8-bit A-D0 Data Register 14 (AD08DT14) <Address: H'0080 00ED> I 8-bit A-D0 Data Register 15 (AD08DT15) <Address: H'0080 00EF> This A-D data register has the A-D0 Converter's 8-bit conversion result stored in it. In A-D0 Converter single mode, the result of A-D conversion is stored in the 8-bit A-D0 Data Register of the corresponding channel. In single-shot or continuous scan mode, each time A-D conversion on a channel is finished, the content of the A-D0 Successive Approximation Register is transferred to the 8-bit A-D0 Data Register of the corresponding channel. Each 8-bit A-D0 Data Register holds the last conversion result until they receive the next conversion result transferred, so that the register content can be read out anytime. D 8 9 1 01 11 21 31 4 D 1 5 AD08DT0-AD08DT15 <When reset: indeterminate> D Bit Name Function R W 8-15 AD08DT0-AD08DT15 8-bit A-D conversion result – (8-bit A-D0 data) A-D CONVERTERS

11-43 Rev.1.0 I 8-bit A-D1 Data Register 0 (AD18DT0) <Address: H'0080 0AD1> I 8-bit A-D1 Data Register 1 (AD18DT1) <Address: H'0080 0AD3> I 8-bit A-D1 Data Register 2 (AD18DT2) <Address: H'0080 0AD5> I 8-bit A-D1 Data Register 3 (AD18DT3) <Address: H'0080 0AD7> I 8-bit A-D1 Data Register 4 (AD18DT4) <Address: H'0080 0AD9> I 8-bit A-D1 Data Register 5 (AD18DT5) <Address: H'0080 0ADB> I 8-bit A-D1 Data Register 6 (AD18DT6) <Address: H'0080 0ADD> I 8-bit A-D1 Data Register 7 (AD18DT7) <Address: H'0080 0ADF> I 8-bit A-D1 Data Register 8 (AD18DT8) <Address: H'0080 0AE1> I 8-bit A-D1 Data Register 9 (AD18DT9) <Address: H'0080 0AE3> I 8-bit A-D1 Data Register 10 (AD18DT10) <Address: H'0080 0AE5> I 8-bit A-D1 Data Register 11 (AD18DT11) <Address: H'0080 0AE7> I 8-bit A-D1 Data Register 12 (AD18DT12) <Address: H'0080 0AE9> I 8-bit A-D1 Data Register 13 (AD18DT13) <Address: H'0080 0AEB> I 8-bit A-D1 Data Register 14 (AD18DT14) <Address: H'0080 0AED> I 8-bit A-D1 Data Register 15 (AD18DT15) <Address: H'0080 0AEF> This A-D data register has the A-D1 Converter's 8-bit conversion result stored in it. In A-D1 Converter single mode, the result of A-D conversion is stored in the 8-bit A-D1 Data Register of the corresponding channel. In single-shot or continuous scan mode, each time A-D conversion on a channel is finished, the content of the A-D1 Successive Approximation Register is transferred to the 8-bit A-D1 Data Register of the corresponding channel. Each 8-bit A-D1 Data Register holds the last conversion result until they receive the next conversion result transferred, so that the register content can be read out anytime. <When reset: indeterminate> D Bit Name Function R W 8-15 AD18DT0-AD18DT15 8-bit A-D1 conversion result – (8-bit A-D0 data) D 8 9 1 01 11 21 31 4 D 1 5 AD18DT0-AD18DT15 A-D CONVERTERS

11-44 Rev.1.0

11.3 Functional Description of the A-D Converters

11.3.1 How to Find Analog Input Voltages

The A-D converters each use a 10-bit successive approximation method. Therefore, to find the actual analog input voltages from the digital quantities obtained as a result of A-D conversion, use the equation below. The A-D converters each are comprised of 10 bits, so they provide a resolution of 1,024. Because the voltage applied to the VREF pin constitutes the reference voltage for the A-D converter, connect an accurate and stable, constant-voltage power supply to the VREF. Also, separate the analog block power supply and ground (AVCC, AVSS) from those of the digital block and take a sufficient protective measure against noise. For details about the accuracy of conversion, see Section 11.3.5, "Accuracy of A-D Conversion." ADiIN0 ADiIN1 ADiIN2 ADiIN3 ADiIN4 ADiIN5 ADiIN6 ADiIN7 Selector AVSS0 VREF0 10-bit A-Di Successive Approximation Register (ADiSAR) 10-bit A-Di Data Register A-Di Comparate Data Register A-D Control Circuit 10-bit D-A Converter Comparator ADiIN8 ADiIN9 ADiIN10 ADiIN11 ADiIN12 ADiIN13 ADiIN14 ADiIN15 AD0iCMP AD0iDT0-15 Successive approximation method A-D conversion unit AVCC0 Vref VIN i=0, 1 Figure 11.3.1 Block Diagram of the Successive Approximation Method A-D0 Conversion Unit A-D CONVERTERS Analog input voltage [V] =A-D conversion result x VREF input voltage [V] 1024

11-45 Rev.1.0

11.3.2 A-D Conversion of Successive Approximation Method

The A-D converter starts A-D convert operation as initiated by a hardware or software A-D conversion start trigger. One A-D conversion starts, the following operations are executed automatically. (a) During single mode, clear the Single Mode Register 0 A-D conversion/comparate complete bit to 0. During scan mode, clear the Scan Mode Register 0 A-D conversion complete bit to 0. (b) Clear the content of the A-D Successive Approximation Register to H'0000. (c) Set the A-D Successive Approximation Register's most significant bit (D6) to 1. (d) Enter the comparison voltage Vref (Note) from the D-A Converter into the Comparator. (e) Compare the comparison voltage Vref and the analog input voltage VIN. Next, store the comparison result in D6. If Vref < VIN, then D6 = 1 If Vref > VIN, then D6 = 0 (f) Execute the above operations (c) through (e) on all other bits D7-D15. (g) When comparison on D15 finishes, the value stored in the A-D Successive Approximation Register is made the valid A-D conversion result. Figure 11.3.2 Change of A-D Successive Approximation Register Content during A-D Conversion Note: The comparison voltage Vref (the voltage entered from the D-A Converter into the Comparator) is determined according to changes of the content of the A-D Successive Approximation Register. The comparison voltage Vref is calculated by the equation below.

• When the content of the A-D Successive Approximation Register = 0 Vref [V] = 0
• When the content of the A-D Successive Approximation Register = 1 to 1023 Vref [V] = (reference voltage VREF / 1024) x (content of the A-D Successive Approximation Register-0.5) A-D CONVERTERS

D6 7 8 9 10 11 12 13 14 D15 1000000000 n 9 100000000 n 9 n 8 10000000 n9 n8 n7 n6 n5 n4 n3 n2 n1 1 Second comparison Third comparison 10th comparison End of comparison n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 Result of the first comparison Result of the second comparison If Vref > VIN, then nX = 0 If Vref < VIN, then nX = 1 A-D Successive Approximation Register (ADiSAR) i=0,1

11-46 Rev.1.0 The comparison result is stored in the 10-bit A-D Data Registers (AD0DTn or AD1DTn) corresponding to the converted channel. Also, the 8 high-order bits of the A-D conversion result can be obtained by reading the 8-bit A-D Data Registers (AD08DTn or AD18DTn). The following shows how A-D conversion of the successive approximation method is performed in each operation mode. (1) For single mode The convert operation stops when comparison on the A-D Successive Approximation Register D15 bit is completed. The content of the A-D Successive Approximation Register (A-D conversion result) is transferred to the 10-bit A-D Data Registers 0-15 of the converted channel. (2) For single-shot scan mode When comparison on the A-D Successive Approximation Register D15 bit for a specified channel is completed, the content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Registers 0-15 and the convert operations (b) through (g) described above are executed for the next channel to be converted. In single-shot scan mode, convert operation stops when A-D conversion in one specified scan loop is finished. (3) For continuous scan mode When comparison on the A-D Successive Approximation Register D15 bit for a specified channel is completed, the content of the A-D Successive Approximation Register is transferred to the corresponding 10-bit A-D Data Registers 0-15 and the convert operations (b) through (g) described above are executed for the next channel to be converted. In continuous scan mode, convert operations are executed continuously until scan operation is forcibly stopped by setting the A-D conversion stop bit (Scan Mode Register 0 D6 bit) to 1. A-D CONVERTERS

11-47 Rev.1.0

11.3.3 Comparator Operation

When comparator mode (single mode only) is selected, the A-D converter functions as a comparator to compare the comparison voltage set in software and the analog input voltages. Upon writing a comparison value to the Successive Approximation Register, the A-D converter starts "comparating" the analog input voltages selected with the Single Mode Register 1 analog input select bits and the value written to the Successive Approximation Register. Once comparate operation starts, the following operations are executed automatically. (a) Clear the Single Mode Register 0 or Scan Mode Register 0 A-D conversion/comparate complete flag to 0. (b) Enter the comparison voltage Vref (Note) from the D-A Converter into the Comparator. (c) Compare the comparison voltage Vref and the analog input voltage VIN. Next, store the comparison result in the comparate result flag (A-D Comparate Data Register D15 bit). If Vref < VIN, then the comparate result flag = 0 If Vref > VIN, then the comparate result flag = 1 (d) Stop comparate operation after storing the comparison result. The comparison result is stored in the A-D Comparate Data Register (AD0CMP or AD1CMP)'s corresponding bits. Note: The comparison voltage Vref (the voltage entered from the D-A Converter into the Comparator) is determined according to changes of the content of the A-D Successive Approximation Register. The comparison voltage Vref is calculated by the equation below.

• When the content of the A-D Successive Approximation Register = 0 Vref [V] = 0
• When the content of the A-D Successive Approximation Register = 1 to 1023 Vref [V] = (reference voltage VREF / 1024) x (content of the A-D Successive Approximation Register - 0.5) A-D CONVERTERS

11-48 Rev.1.0

11.3.4 Calculating the A-D Conversion Time

The A-D conversion time is expressed by the sum of a dummy cycle time and the actual execution cycle time. The terms needed for calculation of the conversion time are listed below. (a) Start dummy time The time from when the CPU executes an A-D conversion start instruction to when the A-D Converter starts A-D conversion (b) A-D conversion execution cycle time (c) Comparate execution cycle time (d) End dummy time The time from when the A-D Converter finished A-D conversion to when the CPU can stably read out the conversion result from the A-D Data Register. (e) Scan interval dummy time The time during single-shot or continuous scan mode from when the A-D Converter finishes A-D conversion on a channel to when it starts A-D conversion on the next channel A-D conversion time = start dummy time + execution cycle time ( + scan interval dummy time + execution cycle time + scan interval dummy time + execution cycle time + scan interval dummy time ... + execution cycle time) + end dummy time Note: Enclosed in parentheses ( ) are the conversion time for the second and subsequent channels in scan mode. A-D CONVERTERS The equation to calculate the A-D conversion time is as follows:

11-49 Rev.1.0 Start dummy Execution cycle A-D conversion start triggerConvert operation starts Transfer to A-D data register <Scan mode> End dummy Start dummy Execution cycle Execution cycle <Single mode> End Execution cycle End dummy Scan interval dummy (Channel 0) (Channel 1) (Last channel) Scan interval dummy ……… Figure 11.3.3 Conceptual Diagram of A-D Conversion Time Table 11.3.1 Conversion Time in Terms of Clock Periods Unit: BCLK Transfer Start dummy A-D conversionComparate End Scan interval speed (Note 1) (Note 2) (Note 3)execution cycle execution cycledummy dummy (Note 4) Low speed Normal 4 4 4 294 42 1 4 mode Double speed 4 4 4 168 24 1 4 High speed Normal 4 4 4 126 18 1 4 mode Double speed 444 8 4 1 2 1 4 Note 1: When started by a software trigger. Note 2: When started by a hardware trigger. Note 3: When writing to the A-D Successive Approximation Register (comparate mode) Note 4: In only scan operation, the execution time is added up for each channel. A-D CONVERTERS

11-50 Rev.1.0 Table 11.3.2 A-D Conversion Time when Started by Software Trigger (Total Time) Conversion started byConversion speed Conversion mode (Note 1) Conversion time [BCLK] Software trigger Low speed mode: Normal Single mode 299 (Note 2) Single-shot n channels scanned (298 × n)+1 /continuous scan mode Comparator mode 47 Low speed mode: Double Single mode 173 Single-shot n channels scanned (172 × n)+1 /continuous scan mode Comparator mode 29 High speed mode: Normal Single mode 131 Single-shot n channels scanned (130 × n)+1 /continuous scan mode Comparator mode 23 High speed mode: Double Single mode 89 Single-shot n channels scanned (88 × n)+1 /continmuous scan mode Comparator mode 17 Note 1: For single and comparator modes, this refers to the A-D conversion or comparate time needed for one channel. For single-shot and continuous scan modes, this refers to the A-D conversion time needed for one scan loop. Note 2: This refers to the time from when a register write cycle is finished to when an A-D conversion interrupt request is generated. A-D CONVERTERS

11-51 Rev.1.0 Table 11.3.3 A-D Conversion Time when Started by Hardware Trigger (Total Time) Conversion started byConversion speed Conversion mode (Note 1) Conversion time [BCLK] Hardware trigger Low speed mode: Normal Single mode 299 (Note 2) Single-shot n channels scanned (298 × n)+1 /continuous scan mode Comparator mode 47 Low speed mode: Double Single mode 173 Single-shot n channels scanned (172 × n)+1 /continuous scan mode Comparator mode 29 High speed mode: NormalSingle mode 131 Single-shot n channels scanned (130 × n)+1 /continuous scan mode Comparator mode 23 High speed mode: Double Single mode 89 Single-shot n channels scanned (88 × n)+1 /continuous scan mode Comparator mode 17 Note 1: For single and comparator modes, this refers to the A-D conversion or comparate time needed for one channel. For single-shot and continuous scan modes, this refers to the A-D conversion time needed for one scan loop. Note 2: For the A-D0 Converter, this refers to the time from TOM0_6 underflow, input on external pin TIN16, TOM0_0-7 enable event, or completion of A-D1 conversion to when an A-D conversion interrupt request is generated. For the A-D1 Converter, this refers to the time from TOM0_6 underflow, input on external pin TIN16, TOM1_6 underflow, or completion of A-D0 conversion to when an A-D1 conversion interrupt request is generated. A-D CONVERTERS

11-52 Rev.1.0

11.3.5 Definition of the A-D Conversion Accuracy

The accuracy of the A-D Converter is expressed by absolute accuracy. Absolute accuracy refers to the difference, expressed in terms of LSB, between the output code actually obtained by A-D converting the analog input voltage and the output code that can be expected from an A-D converter with ideal characteristics. The analog input voltages used during accuracy measurement are chosen to be the midpoint values of voltage width at which an A-D converter with ideal characteristics will produce the same output code. For example, when VREF0 = 5.12 V, the width of 1 LSB of a 10-bit A-D converter is 5 mV, so that the middle points of analog input voltages are chosen to be 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, 25 mV, and so on. If the absolute accuracy of an A-D converter is said to be +2 LSB, it means that if the input voltage is 25 mV, for example, the actual A-D conversion result is in the range of H'003 to H'007, whereas the output code that can be expected from an ideal A-D converter is H'005. Note that absolute accuracy includes a zero error and full-scale error. Although when actually using the A-D Converter, the analog input voltages are in the range of AVSS0 to VREF0, excessively lowering the VREF0 voltage requires caution because resolution may be degraded. Note also that output codes for analog input voltages from VREF0 to AVCC0 are always H'3FF. Figure 11.3.4 Ideal A-D Conversion Characteristics Relative to Analog Input Voltages of a 10-bit A-D Converter A-D CONVERTERS H'000 H'001 H'002 H'003 H'3FE H'3FF A-D conversion result (hexadecimal) → Analog input voltage [V] VREF 1024 ×1 Ideal A-D conversion characteristic A-D conversion characteristic with infinite resolution

0 VREF

1024 ×2 VREF 1024 ×3 VREF 1024 ×1022 VREF 1024 ×1023 VREF 1024 ×1024

11-53 Rev.1.0 H'000 H'001 H'002 H'003 H'004 H'005 H'006 Output code (hexadecimal) → Analog input voltage [mV] Ideal A-D conversion characteristic A-D conversion characteristic with infinite resolution 5 1 01 52 02 53 03 54 04 55 05 5 H'007 H'008 H'009 H'00A H'00B +2 LSB –2 LSB Figure 11.3.5 Absolute Accuracy of the A-D Converter A-D CONVERTERS

11-54 Rev.1.0

11.4 Precautions on Using the A-D Converters

• Forcible termination during scan operation If A-D conversion is forcibly stopped during scan mode operation by setting the A-D conversion stop bit (AD0CSTP or AD1CSTP) to 1 and the A-D data register for the channel in the middle of conversion is read, the data obtained by this read is the last conversion result that was transferred to the register before being forcibly stopped.
• Modification of A-D converter related registers The A-D Conversion Interrupt Control Register (except for the A-D conversion stop bit), each mode register, and A-D Successive Approximation Register can only be modified while A-D conversion is not in operation. Otherwise, restart A-D conversion after modifying the register contents. If any register is modified during A-D conversion, the conversion result cannot be guaranteed.
• Handling of analog input signals The A-D Converter described here does not contain a sample-and-hold circuit. Therefore, make sure the analog input levels are fixed during A-D conversion.
• Timing at which to read the A-D conversion complete bit If it is necessary to read the A-D conversion complete bit (Single Mode Register 0 D5 bit or Scan Mode Register 0 D5 bit) immediately after starting A-D conversion, be sure to insert a NOP instruction, etc. to adjust the timing for one cycle before reading the bit.
• Rated value of absolute accuracy The rated value of absolute accuracy is that of the microcomputer's own as a single unit which can be exhibited when the microcomputer is used in an environment where it may not be affected by the power supply wiring or noise on the board. When designing the board, pay careful attention to its layout by, for example, separating AVCC0, AVSS0, and VREF0 from other digital block power supplies, or by making analog input pins unsusceptible to influences from other digital signal lines (e.g., noise). A-D CONVERTERS

12.1 Outline of Serial I/O

12.2 Serial I/O Related

12.3 Transmit Operation in CSIO

12.4 Receive Operation in CSIO

12.5 Precautions on Using CSIO

12.6 Transmit Operation in UART

12.7 Receive Operation in UART

12.8 Fixed Period Clock Output

12.9 Precautions on Using

12-2 Rev.1.0 SERIAL I/O The 32172/32173 contains a total of eight serial I/O channels, SIO0 through SIO7. Serial channels SIO0, SIO1, SIO4, and SIO5 can be selected between CSIO mode (clock-synchronous serial I/O) and UART mode (asynchronous serial I/O). SIO2, SIO3, SIO6, and SIO7 are used in UART mode only.

• CSIO mode (clock-synchronous serial I/O) The communication performed in this mode is synchronized to the transfer clock, using the same clock on both transmit and receive sides. Data are transferred in a fixed length of 8 bits.
• UART mode (asynchronous serial I/O) The communication performed in this mode is asynchronous. The transfer data length can be selected from 7, 8, or 9 bits. Serial I/Os 0-7 each have transmit DMA and receive DMA transfer requests. Through a combined use with the internal DMA, they allow for fast serial communication, and help to reduce the data communication load on the CPU. Serial I/Os are outlined below.

12-3 Rev.1.0 Table 12.1.1 Outline of Serial I/O Item Content Number of channels CSIO/UART: 4 channels (SIO0,SIO1,SIO4,SIO5) UART-only : 4 channels (SIO2,SIO3,SIO6,SIO7) Clock During CSIO mode : Internal clock or external clock selectable (Note 1) During UART mode : Internal clock only Transfer mode Transmit half-duplex, receive half-duplex, transmit/receive full-duplex BRG count source f(BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (when internal peripheral clock is selected) (Note 2) f(BCLK): Internal peripheral clock operating frequency Data format CSIO mode : Data length = 8 bits (fixed) Order of transfer = LSB first (fixed) UART mode : Start bit = 1 bit Character length = 7, 8, or 9 bits Parity bit = With or without (odd/even selectable) Stop bit = 1 or 2 bits Order of transfer: LSB first (fixed) Baud rate CSIO mode : 152 bits/second to 2 Mbits/second (when f(BCLK) = 20 MHz) UART mode : 19 bits/second to 156 Kbits/second (when f(BCLK) = 20 MHz) Error detection CSIO mode : Overrun error only UART mode : Overrun, parity, and framing errors (Any error if occurs is indicated by an errorsum bit) Fixed period clock When using SIO0, SIO1, SIO4, or SIO5 in UART mode, this function outputs a output function divided-by-2 clock of BRG from the SCLK pin. Note 1: During CSIO mode, the maximum input frequency of an external clock is f(BCLK) divided by 16. Note 2: If f(BCLK) is selected for the BRG count source, the BRG set value is subject to limitations. SERIAL I/O

12-4 Rev.1.0 Table 12.1.2 Interrupt Request Generation Functions of Serial I/O Serial I/O interrupt request Interrupt source on ICU SIO0 transmit buffer empty interrupt SIO0 transmit interrupt SIO0 receive complete or receive error interrupt SIO0 receive interrupt (selectable) SIO1 transmit buffer empty interrupt SIO1 transmit interrupt SIO1 receive complete or receive error interrupt SIO1 receive interrupt (selectable) SIO2 transmit buffer empty interrupt SIO2,3 Transmit/Receive Interrupt (Group Interrupt) SIO2 receive complete or receive error interrupt SIO2,3 Transmit/Receive Interrupt (Group Interrupt) (selectable) SIO3 transmit buffer empty interrupt SIO2,3 Transmit/Receive Interrupt (Group Interrupt) SIO3 receive complete or receive error interrupt SIO2,3 Transmit/Receive Interrupt (Group Interrupt) (selectable) SIO4 transmit buffer empty interrupt SIO4 transmit interrupt SIO4 receive complete or receive error interrupt SIO4 receive interrupt (selectable) SIO5 transmit buffer empty interrupt SIO5 transmit interrupt SIO5 receive complete or receive error interrupt SIO5 receive interrupt (selectable) SIO6 transmit buffer empty interrupt SIO6,7 Transmit/Receive Interrupt (Group Interrupt) SIO6 receive complete or receive error interrupt SIO6,7 Transmit/Receive Interrupt (Group Interrupt) (selectable) SIO7 transmit buffer empty interrupt SIO6,7 Transmit/Receive Interrupt (Group Interrupt) SIO7 receive complete or receive error interrupt SIO6,7 Transmit/Receive Interrupt (Group Interrupt) (selectable) SERIAL I/O

12-5 Rev.1.0 Table 12.1.3 DMA Transfer Request Generation Functions of Serial I/O Serial I/O DMA transfer request DMA input channel SIO0 transmit buffer empty Channel 3 SIO0 receive complete Channel 4 SIO1 transmit buffer empty Channel 6 SIO1 receive complete Channel 3 SIO2 transmit buffer empty Channels 0 and 7 SIO2 receive complete Channel 5 SIO3 transmit buffer empty Channels 4 and 9 SIO3 receive complete Channel 8 SIO4 transmit buffer empty Channel 5 SIO4 receive complete Channel 1 SIO5 transmit buffer empty Channel 7 SIO5 receive complete Channel 2 SIO6 transmit buffer empty Channel 8 SIO6 receive complete Channel 6 SIO7 transmit buffer empty Channel 0 SIO7 receive complete Channel 9 SERIAL I/O

12-6 Rev.1.0 SCLKI0/ SCLKO0 BCLK, BCLK/8, BCLK/32, BCLK/256 Baud Rate Generator (BRG) BCLK (Set value + 1) Internal data bus CSIO mode When internal clock is selected When UART mode is selected CSIO mode UART mode When internal clock is selected Clock Divider RXD0 TXD0 Receive interrupt SIO0 Transmit Buffer Register SIO0 Transmit Shift Register Receive DMA transfer request Transmit interrupt Transmit DMA transfer request To DMA3SIO0 Receive Shift Register SIO0 Receive Buffer Register When external clock is selected Note 1: When BCLK is selected, the BRG set value is subject to limitations. Note 2: SIO2 and SIO3 do not have the SCLKI/SCLKO functions. SCLKI1/ SCLKO1 To DMA6 To Interrup Controller To Interrup Controller SIO0 SIO1 SIO2 RXD1 TXD1 SIO1 Transmit Shift Register SIO1 Receive Shift Register To DMA0, 7RXD2 TXD2 Transmit/ Receive Control Circuit SIO2 Transmit Shift Register SIO2 Receive Shift Register Receive interrupt Receive DMA transfer request Transmit interrupt Transmit DMA transfer request Receive interrupt Receive DMA transfer request Transmit interrupt Transmit DMA transfer request To Interrupt Controller To DMA5 To DMA3 To DMA4 SIO3 To DMA4, 9RXD3 TXD3 SIO3 Transmit Shift Register SIO3 Receive Shift Register Receive interrupt Receive DMA transfer request Transmit interrupt Transmit DMA transfer request To DMA8 Transmit/ Receive Control Circuit Transmit/ Receive Control Circuit Transmit/ Receive Control Circuit Figure 12.1.1 Block Diagram of SIO0-SIO3 SERIAL I/O

12-7 Rev.1.0 Internal data bus Note 1: When BCLK is selected, the BRG set value is subject to limitations. Note 2: SIO6 and SIO7 do not have the SCLKI/SCLKO functions. SCLKI4 To DMA5 To Interrupt Controller SIO4 SIO6 RXD4 TXD4 Transmit/ Receive Control Circuit SIO4 Transmit Shift Register SIO4 Receive Shift Register To DMA8RXD6 TXD6 SIO6 Transmit Shift Register SIO6 Receive Shift Register Receive interrupt Receive DMA transfer request Transmit interrupt Transmit DMA transfer request Receive interrupt Receive DMA transfer request Transmit interrupt Transmit DMA transfer request To DMA6 To DMA1 SIO7 To DMA0RXD7 TXD7 SIO7 Transmit Shift Register SIO7 Receive Buffer Register Receive interrupt Receive DMA transfer request Transmit interrupt Transmit DMA transfer request To DMA9 SCLKI5 To DMA7 To Interrupt Controller To Interrupt Controller SIO5 RXD5 TXD5 SIO5 Transmit Shift Register SIO5 Receive Shift Register Receive interrupt Receive DMA transfer request Transmit interrupt Transmit DMA transfer request To DMA2 SCLKO4 SCLKO5 Transmit/ Receive Control Circuit Transmit/ Receive Control Circuit Transmit/ Receive Control Circuit Figure 12.1.2 Block Diagram of SIO4-SIO7 SERIAL I/O

12-8 Rev.1.0

12.2 Serial I/O Related Registers

A serial I/O related register map is shown below. Figure 12.2.1 Serial I/O Related Register Map (1/2) SERIAL I/O H'0080 0100 H'0080 0102 H'0080 0110 H'0080 0112 H'0080 0114 Address D0 D7 +0 address +1 address D8 D15 H'0080 0116 SIO23 Interrupt Status Register (SI23STAT) SIO03 Interrupt Mask Register (SI03MASK) SIO03 Receive Interrupt Cause Select Register (SI03SEL) SIO0 Transmit Control Register (S0TCNT) SIO0 Transmit/Receive Mode Register (S0MOD) SIO0 Transmit Buffer Register (S0TXB) SIO0 Receive Buffer Register (S0RXB) SIO0 Receive Control Register (S0RCNT) SIO0 Baud Rate Register (S0BAUR) SIO1 Transmit Control Register (S1TCNT) SIO1 Transmit/Receive Mode Register (S1MOD) SIO0 Transmit Buffer Register (S1TXB) SIO0 Receive Buffer Register (S1RXB) SIO1 Receive Control Register (S1RCNT) SIO0 Baud Rate Register (S1BAUR) SIO2 Transmit Control Register (S2TCNT) SIO2 Transmit/Receive Mode Register (S2MOD) SIO2 Transmit Buffer Register (S2TXB) SIO2 Receive Buffer Register (S2RXB) SIO2 Receive Control Register (S2RCNT) SIO2 Baud Rate Register (S2BAUR) SIO3 Transmit Control Register (S3TCNT) SIO3 Transmit/Receive Mode Register (S3MOD) SIO3 Transmit Buffer Register (S3TXB) SIO3 Receive Buffer Register (S3RXB) SIO3 Receive Control Register (S3RCNT) SIO3 Baud Rate Register (S3BAUR) H'0080 0120 H'0080 0122 H'0080 0124 H'0080 0126 H'0080 0130 H'0080 0132 H'0080 0134 H'0080 0136 H'0080 0140 H'0080 0142 H'0080 0144 H'0080 0146 SIO67 Interrupt Status Register (SI67STAT) SIO47 Interrupt Mask Register (SI47MASK)H'0080 0A00 SIO47 Receive Interrupt Cause Select Register (SI47SEL)H'0080 0A02 Blank areas are reserved for future use.

12-9 Rev.1.0 H'0080 0A20 H'0080 0A22 H'0080 0A26 H'0080 0A34 H'0080 0A30 Address D0 D7 +0 address +1 address D8 D15 H'0080 0A32 H'0080 0A36 SIO5 Transmit Control Register (S5TCNT) SIO0 Transmit/Receive Mode Register (S5MOD) SIO5 Receive Control Register (S5RCNT) SIO5 Baud Rate Register (S5BAUR) SIO6 Receive Control Register (S6RCNT) SIO6 Baud Rate Register (S6BAUR) Blank areas are reserved for future use. SIO5 Transmit Buffer Register (S5TXB) SIO5 Receive Buffer Register (S5RXB) SIO6 Transmit Buffer Register (S6TXB) SIO6 Receive Buffer Register (S6RXB) SIO6Transmit/Receive Mode Register (S6MOD) SIO6 Transmit Control Register (S6TCNT) SIO7 Receive Control Register (S7RCNT) SIO7 Baud Rate Register (S7BAUR) SIO7 Receive Buffer Register (S7RXB) SIO7 Transmit/Receive Mode Register (S7MOD) SIO7 Transmit Control Register (S7TCNT) H'0080 0A24 SIO7 Transmit Buffer Register (S7TXB) H'0080 0A44 H'0080 0A40 H'0080 0A42 H'0080 0A46 H'0080 0A10 H'0080 0A12 H'0080 0A16 H'0080 0A14 SIO4 Transmit Control Register (S4TCNT) SIO4 Transmit/Receive Mode Register (S4MOD) SIO4Transmit Buffer Register (S4TXB) SIO4 Receive Buffer Register (S4RXB) SIO4 Receive Control Register (S4RCNT) SIO4 Baud Rate Register (S4BAUR) Figure 12.2.2 Serial I/O Related Register Map (2/2) SERIAL I/O

12-10 Rev.1.0

12.2.1 SIO Interrupt Related Registers

(1) Selecting interrupt sources The interrupt signals output from each SIO to the ICU (Interrupt Controller) consist of transmit and receive interrupts. Transmit interrupts are generated when the transmit buffer is empty. Receive interrupts can be selected between receive complete and receive error interrupts by using the Receive Interrupt Source Select Register (SI03SEL or SI47SEL). Note 1: Any interrupt signal can only be generated by enabling the TEN (Transmit Enable) or REN (Receive Enable) bit for its corresponding SIO and then enabling the interrupt with the SIO Interrupt Mask Register. Note 2: SIO2 and SIO3 together comprise one group interrupt, so do SIO6 and SIO7. (2) Notes on transmit interrupts A transmit interrupt is generated by enabling its corresponding TEN (Transmit Enable) bit while the SIO Interrupt Mask Register is enabled for interrupts. (3) Regarding DMA transfer requests from SIO Each SIO can generate transmit DMA transfer and receive-complete DMA transfer requests. These DMA transfer requests can be generated by enabling the corresponding TEN (Transmit Enable) or TEN (Receive Enable) bit for the SIO concerned. When using DMA transfers to communicate with the microcomputer, please be sure to set up DMA before enabling the TEN and REN bits. If a receive error occurs, no receive-complete DMA transfer requests are generated.

• Transmit DMA transfer requests This DMA transfer request is generated when the transmit buffer is empty while the TEN bit is enabled. Figure 12.2.3 Transmit DMA Transfer Request SERIAL I/O

(Transmit enable bit) TBE (Transmit buffer empty bit) Transmit DMA transfer re quest

12-11 Rev.1.0

• Receive-complete DMA transfer requests This DMA transfer request is generated when the receive buffer is full. Figure 12.2.4 Receive-complete DMA Transfer Request SERIAL I/O

Note: If a receive error occurs, no receive-complete DMA transfer requests are generated. RFIN (Receive complete bit)

12-12 Rev.1.0

12.2.2 SIO Interrupt Control Registers

I SIO23 Interrupt Status Register (SI23STAT) <Address: H'0080 0100> D 0 123456 D 7 IRQT2 IRQR2 IRQT3 IRQR3 <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 –

4 IRQT2 (SIO2 transmit-complete 0: Interrupt not requested

interrupt request status bit) 1: Interrupt requested

5 IRQR2 (SIO2 receive interrupt 0: Interrupt not requested

request status bit) 1: Interrupt requested

6 IRQT3 (SIO3 transmit-complete 0: Interrupt not requested

interrupt request status bit) 1: Interrupt requested

7 IRQR3 (SIO3 receive interrupt 0: Interrupt not requested

request status bit) 1: Interrupt requested W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. Transmit/receive interrupt requests from SIO2 and SIO3 are described below. [Setting the interrupt request status bit] The interrupt request status bit is set in hardware, and cannot be set in software. [Clearing the interrupt request status bit] The interrupt request status bit is cleared by writing 0 in software. Note: If the status bit is set in hardware at the same time it is cleared in software, the former has priority so that the status bit is set. When writing to the SIO Interrupt Request Status Register, be sure to write 0 for the bits to be cleared and 1 for all other bits. Writing 1 in software does not affect any bit of this register, the bit retains the value it had before writing. SERIAL I/O

12-13 Rev.1.0 I SIO67 Interrupt Status Register (SI67STAT) <Address: H'0080 0A00> <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 –

4 IRQT6 (SIO6 transmit-complete 0: Interrupt not requested

interrupt request status bit) 1: Interrupt requested

5 IRQR6 (SIO6 receive interrupt 0: Interrupt not requested

request status bit) 1: Interrupt requested

6 IRQT7 (SIO7 transmit-complete 0: Interrupt not requested

interrupt request status bit) 1: Interrupt requested

7 IRQR7 (SIO7 receive interrupt 0: Interrupt not requested

request status bit) 1: Interrupt requested W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. Transmit/receive interrupt requests from SIO6 and SIO7 are described below. [Setting the interrupt request status bit] The interrupt request status bit is set in hardware, and cannot be set in software. [Clearing the interrupt request status bit] The interrupt request status bit is cleared by writing 0 in software. Note: If the status bit is set in hardware at the same time it is cleared in software, the former has priority so that the status bit is set. When writing to the SIO Interrupt Request Status Register, be sure to write 0 for the bits to be cleared and 1 for all other bits. Writing 1 in software does not affect any bit of this register, the bit retains the value it had before writing. IRQT6 IRQR6 IRQT7 IRQR7 D 0 123456 D 7 SERIAL I/O

12-14 Rev.1.0 I SIO03 Interrupt Mask Register (SI03MASK) <Address: H'0080 0101> D 8 9 1 01 11 21 31 4 D 1 5 T0MASK R0MASK T1MASK R1MASK T2MASK R2MASK T3MASK R3MASK <When reset: H'00> D Bit Name Function R W

8 T0MASK (SIO0 transmit 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

9 R0MASK (SIO0 receive 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

10 T1MASK (SIO1 transmit 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

11 R1MASK (SIO1 receive 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

12 T2MASK (SIO2 transmit 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

13 R2MASK (SIO2 receive 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

14 T3MASK (SIO3 transmit 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

15 R3MASK (SIO3 receive 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request This register controls interrupt requests sent from each SIO by enabling or disabling them. An interrupt request from any SIO is enabled by setting its corresponding interrupt mask bit to 1. SERIAL I/O

12-15 Rev.1.0 I SIO47 Interrupt Mask Register (SI47MASK) <Address: H'0080 0A01> <When reset: H'00> D Bit Name Function R W

8 T4MASK (SIO4 transmit 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

9 R4MASK (SIO4 receive 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

10 T5MASK (SIO5 transmit 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

11 R5MASK (SIO5 receive 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

12 T6MASK (SIO6 transmit 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

13 R6MASK (SIO6 receive 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

14 T7MASK (SIO7 transmit 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request

15 R7MASK (SIO7 receive 0: Masks (disables) interrupt request

interrupt mask bit) 1: Enables interrupt request This register controls interrupt requests sent from each SIO by enabling or disabling them. An interrupt request from any SIO is enabled by setting its corresponding interrupt mask bit to 1. D 8 9 1 01 11 21 31 4 D 1 5 T4MASK R4MASK T5MASK R5MASK T6MASK R6MASK T7MASK R7MASK SERIAL I/O

12-16 Rev.1.0 I SIO03 Receive Interrupt Cause Select Register (SI03SEL) <Address: H'0080 0102> D 0 123456 D 7 ISR0 ISR1 ISR2 ISR3 <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 –

4 ISR0 0: Receive complete interrupt

(SIO0 receive interrupt cause select bit) 1: Receive error interrupt

5 ISR1 0: Receive complete interrupt

(SIO1 receive interrupt cause select bit) 1: Receive error interrupt

6 ISR2 0: Receive complete interrupt

(SIO2 receive interrupt cause select bit) 1: Receive error interrupt

7 ISR3 0: Receive complete interrupt

(SIO3 receive interrupt cause select bit) 1: Receive error interrupt This register selects the cause of interrupt generated at completion of receive operation. [When set to 0] Setting this bit to 0 selects Receive complete interrupt (receive buffer full). A receive complete interrupt is generated even when an error occurred when receiving data (except for an overrun error). [When set to 1] Setting this bit to 1 selects Receive error interrupt. Following are detected for receive errors:

• CSIO mode : Overrun error
• UART mode : Overrun, parity, and framing errors SERIAL I/O

12-17 Rev.1.0 I SIO47 Receive Interrupt Cause Select Register (SI47SEL) <Address: H'0080 0A02> <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 –

4 ISR4 0: Receive complete interrupt

(SIO4 receive interrupt cause select bit) 1: Receive error interrupt

5 ISR5 0: Receive complete interrupt

(SIO5 receive interrupt cause select bit) 1: Receive error interrupt

6 ISR6 0: Receive complete interrupt

(SIO6 receive interrupt cause select bit) 1: Receive error interrupt

7 ISR7 0: Receive complete interrupt

(SIO7 receive interrupt cause select bit) 1: Receive error interrupt This register selects the cause of interrupt generated at completion of receive operation. [When set to 0] Setting this bit to 0 selects Receive complete interrupt (receive buffer full). A receive complete interrupt is generated even when an error occurred when receiving data (except for an overrun error). [When set to 1] Setting this bit to 1 selects Receive error interrupt. Following are detected for receive errors:

• CSIO mode : Overrun error
• UART mode : Overrun, parity, and framing errors D 0 123456 D 7 ISR4 ISR5 ISR6 ISR7 SERIAL I/O

12-18 Rev.1.0 SIO2,3 transmit/receive interrupt Data bus IRQT2 F/F T2MASK F/Fb12 IRQR2 F/F R2MASK F/Fb13 IRQT3 F/F T3MASK F/Fb14 IRQR3 F/F R3MASK F/Fb15 (Level) 4-source inputs <SI23STAT: H'0080 0100> TXD2 TXD3 <SI03MASK: H'0080 0101> F/F ISR2 RXD2 receive complete RXD2 receive error F/F ISR3 RXD3 receive complete RXD3 receive error Figure 12.2.5 Block Diagram of SIO2, 3 Transmit/Receive Interrupts Figure 12.2.6 Block Diagram of SIO6, 7 Transmit/Receive Interrupts SERIAL I/O SIO6,7 transmit/receive interrupt Data bus IRQT6 F/F T6MASK F/Fb12 IRQR6 F/F R6MASK F/Fb13 IRQT7 F/F T7MASK F/Fb14 IRQR7 F/F R7MASK F/Fb15 (Level) 4-source inputs <SI67STAT: H'0080 0A00> TXD6 TXD7 <SI47MASK: H'0080 0A01> F/F ISR6 RXD6 receive complete RXD6 receive error F/F ISR7 RXD7 receive complete RXD7 receive error

12-19 Rev.1.0

12.2.3 SIO Transmit Control Registers

I SIO0 Transmit Control Register (S0TCNT) <Address: H'0080 0110> I SIO1 Transmit Control Register (S1TCNT) <Address: H'0080 0120> I SIO2 Transmit Control Register (S2TCNT) <Address: H'0080 0130> I SIO3 Transmit Control Register (S3TCNT) <Address: H'0080 0140> I SIO4 Transmit Control Register (S4TCNT) <Address: H'0080 0A10> I SIO5 Transmit Control Register (S5TCNT) <Address: H'0080 0A20> I SIO6 Transmit Control Register (S6TCNT) <Address: H'0080 0A30> I SIO7 Transmit Control Register (S7TCNT) <Address: H'0080 0A40> D 0 123456 D 7 CDIV TSTAT TBE TEN <When reset: H'12> D Bit Name Function R W 0,1 No functions assigned 0 – 2,3 CDIV D2 D3 (BRG count source select bit) 0 0: Selects f(BCLK) 0 1: Selects divided-by-8 clock of f(BCLK) 1 0: Selects divided-by-32 clock of f(BCLK) 1 1: Selects divided-by-256 clock of f(BCLK)

5 TSTAT 0: Transmission idle & no data exist –

(Transmit status bit) in transmit buffer register 1: Transmission in progress or data exist in transmit buffer register

6 TBE 0: Data exist in transmit buffer register –

(Transmit buffer empty bit) 1: No data exist in transmit buffer register

7 TEN 0: Disables transmission

(Transmit enable bit) 1: Enables transmission SERIAL I/O

12-20 Rev.1.0 (1) CDIV (baud rate generator count source select) bits (D2, D3) These bits select the count source for the Baud Rate Generator (BRG). Note: If f(BCLK) is selected for the BRG count source, the BRG must be set in such a way that the baud rate will not exceed the maximum transfer rate. For details, see the section where the BRG Register is discussed. (2) TSTAT (transmit status) bit (D5) [Set condition] This bit is set to 1 by writing to the Transmit Buffer Register when transmission is enabled. [Clear condition] This bit is cleared to 0 when transmission remains idle (no data exists in the Transmit Shift Register) nor does data exist in the Transmit Buffer Register. It also is cleared upon clearing the transmit enable bit. (3) TBE (transmit buffer empty) bit (D6) [Set condition] This bit is set to 1 when data is transferred from the Transmit Buffer Register to the Transmit Shift Register, with the Transmit Buffer Register thereby emptied. It also is set by clearing the transmit enable bit. [Clear condition] This bit is cleared to 0 by writing data to the lower byte of the Transmit Buffer Register while transmission is enabled (TEN = 1). (4) TEN (transmit enable) bit (D7) Setting this bit to 1 enables the SIO for transmission; clearing this bit to 0 disables the SIO against transmission. The SIO stops sending data when this bit is cleared to 0 during transmission. SERIAL I/O

12-21 Rev.1.0

12.2.4 SIO Transmit/Receive Mode Registers

I SIO0 Transmit/Receive Mode Registers (S0MOD) <Address: H'0080 0111> I SIO1 Transmit/Receive Mode Registers (S1MOD) <Address: H'0080 0121> I SIO2 Transmit/Receive Mode Registers (S2MOD) <Address: H'0080 0131> I SIO3 Transmit/Receive Mode Registers (S3MOD) <Address: H'0080 0141> I SIO4 Transmit/Receive Mode Registers (S4MOD) <Address: H'0080 0A11> I SIO5 Transmit/Receive Mode Registers (S5MOD) <Address: H'0080 0A21> I SIO6 Transmit/Receive Mode Registers (S6MOD) <Address: H'0080 0A31> I SIO7 Transmit/Receive Mode Registers (S7MOD) <Address: H'0080 0A41> D 8 9 1 01 11 21 31 4 D 1 5 SMOD CKS STB PSEL PEN SEN <When reset: 00> D Bit Name Function R W 8-10 SMOD D8 D9 D10 (Serial I/O mode select bit) 0 0 0 : 7-bit UART (Note 1) 0 0 1 : 8-bit UART 0 1 X : 9-bit UART

1 X X : 8-bit clock synchronized serial I/O

11 CKS (internal/external clock 0: Internal clock

select bit) 1: External clock (Note 2)

12 STB (stop bit length select bit, 0: 1 stop bit

UART mode only) 1: 2 stop bits (Note 3)

13 PSEL (odd/even parity select bit, 0: Odd parity

UART mode only) 1: Even parity (Note 3)

14 PEN (parity enable bit, 0: Disables parity

UART mode only) 1: Enables parity (Note 3)

15 SEN (sleep select bit, 0: Disables sleep function

UART mode only) 1: Enables sleep function (Note 3) Note 1: For SIO2 and 3, the D8 bit is fixed to 0 in hardware. The 8 bit cannot be set to 1 (to select clock synchronized serial I/O). Note 2: When UART mode selected, this bit has no effect. Note 3: When clock synchronized mode selected, D12-D15 have no effect. SERIAL I/O

12-22 Rev.1.0 The SIO Transmit/Receive Mode Registers consist of the bits to select serial I/O operation mode, data format, and the function to be used during communication. The SIO Transmit/Receive Mode Registers must always be set before serial I/O starts operation. To modify the register contents after the SIO started sending or receiving, check to see that the transmit or receive operation is completed and disable transmit/receive operations (by clearing the SIO Transmit Control Register transmit enable bit and the SIO Receive Control Register receive enable bit to 0) before setting the register. (1) SMOD (serial I/O mode select) bits (D8-D10) These bits select serial I/O operation mode. (2) CKS (internal/external clock select) bit (D11) This bit is effective when CSIO mode is selected. When UART mode is selected, this bit has no effect and the SIO operates with an internal clock. (3) STB (stop bit length select) bit (D12) This bit is effective when in UART mode. Use this bit to select the length of the stop bit that indicates the end of the transmit data. Setting this bit to 0 selects one stop bit; setting this bit to 1 selects two stop bits. During clock synchronized mode, the content of this bit has no effect. (4) PSEL (odd/even parity select) bit (D13) This bit is effective when in UART mode. When parity is enabled (D14 = 1), use this bit to select the parity attribute (odd or even). Setting this bit to 0 selects odd parity; setting this bit to 1 selects even parity. When parity is disabled (D14 = 0) and when in clock synchronized mode, the content of this bit has no effect. (5) PEN (parity enable) bit (D14) This bit is effective when in UART mode. Setting this bit to 1 enables parity, so that a parity bit is added immediately after the data bits of transmit data. When receiving data, the received data is checked for parity. The parity bit added to the transmit data is automatically determined to be to 0 or 1 so that the attribute of the result derived by adding the number of 1's in the data bits and the content of the parity bit matches the attribute selected with the odd/even parity select bit (D13). Figure 12.2.4 shows an example of a data format where parity is enabled. (6) SEN (sleep select) bit (D15) This bit is effective when in UART mode. When the sleep function is enabled by setting this bit to 1, data is latched into the UART Receive Buffer Register only when the most significant bit (MSB) of the received data = 1. SERIAL I/O

12-23 Rev.1.0 When it matches the attribute of the selected parity, PAR = 0 is added.

• When sending D7 D6 D5 D4 D3 D2 D1 D0 PAR SPST Attribute of D7 + D6 +···+ D0 When it does not match the attribute of the selected parity, PAR = 1 is added. LSB MSB
• When receiving D7 D6 D5 D4 D3 D2 D1 D0 PAR SPST LSB MSB If the result of D7 + D6 +···+ D0 + PAR does not match he attribute of the selected parity, a parity error is assumed. Note 1: The data format shown above is an example for 8-bit UART mode. Note 2: The data bit number (Dn) above only indicates a sequence of data, and does not represent the bit number (Dn) in the register. D8 D7 D6 D5 D4 D3 D2 D1 PAR SPST D0 Note 1 Note 2
• 9-bit UART mode D7 D6 D5 D4 D3 D2 D1 D0 PAR SPST Note 1 Note 2
• 8-bit UART mode D6 D5 D4 D3 D2 D1 D0 PAR SPST Note 1 Note 2
• 7-bit UART mode D7 D6 D5 D4 D3 D2 D1• Clock synchronized mode D0 Note 1: The parity bit can be chosen to be or not to be included. Note 2: The stop bit length can be selected between one bit or two bits. Direction of transfer ST:Start Bit PAR: Parity Bit :Equivalent to one frame D: Data Bit SP: Stop Bit When the attribute (odd or even) represented by the number of 1's in the data bits matches that of the selected parity, the SIO adds a parity bit which is 0 to the transmit data. When the attribute represented by the number of 1's in the data bits does not match that of the selected parity, the SIO adds a parity bit which is 1 to the transmit data. The received data is checked for parity to see if the number of 1's in the data and parity bits matches the attribute (odd or even) of the parity (parity check). Figure 12.2.7 Data Format where Parity is Enabled SERIAL I/O

12-24 Rev.1.0

12.2.5 SIO Transmit Buffer Registers

I SIO0 Transmit Buffer Register (S0TXB) <Address: H'0080 0112> I SIO1 Transmit Buffer Register (S1TXB) <Address: H'0080 0122> I SIO2 Transmit Buffer Register (S2TXB) <Address: H'0080 0132> I SIO3 Transmit Buffer Register (S3TXB) <Address: H'0080 0142> I SIO4 Transmit Buffer Register (S4TXB) <Address: H'0080 0A12> I SIO5 Transmit Buffer Register (S5TXB) <Address: H'0080 0A22> I SIO6 Transmit Buffer Register (S6TXB) <Address: H'0080 0A32> I SIO7 Transmit Buffer Register (S7TXB) <Address: H'0080 0A42> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TDATA <When reset: indeterminate> D Bit Name Function R W 0-6 No functions assigned ? 7-15 TDATA Set transmit data. ? (Transmit data) R = ?: Indeterminate when read The SIO Transmit Buffer Registers are used to set transmit data. These registers are a write-only register, so that the register contents cannot be read out. When setting transmit data in this register, make sure the data is LSB-aligned, and that the data is written to D9-D15 for 7-bit data (UART mode only), D8-D15 for 8-bit data, or D7-D15 for 9-bit data (UART mode only). Before writing transmit data to this register, be sure to enable the Transmit Control Register TEN (transmit enable) bit (by setting it to 1). Writing to this register while the TEN bit is disabled (= 0) has no effect. When data is written to the Transmit Buffer Register while the SIO is enabled for transmission, the data is transferred from the SIO Transmit Buffer Register to the SIO Transmit Shift Register, upon which the serial I/O status transmitting the data. Note: When sending 7 or 8-bit data, the register can be accessed bytewise. SERIAL I/O

12-25 Rev.1.0

12.2.6 SIO Receive Buffer Registers

I SIO0 Receive Buffer Register (S0RXB) <Address: H'0080 0114> I SIO1 Receive Buffer Register (S1RXB) <Address: H'0080 0124> I SIO2 Receive Buffer Register (S2RXB) <Address: H'0080 0134> I SIO3 Receive Buffer Register (S3RXB) <Address: H'0080 0144> I SIO4 Receive Buffer Register (S4RXB) <Address: H'0080 0A14> I SIO5 Receive Buffer Register (S5RXB) <Address: H'0080 0A24> I SIO6 Receive Buffer Register (S6RXB) <Address: H'0080 0A34> I SIO7 Receive Buffer Register (S7RXB) <Address: H'0080 0A44> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 RDATA <When reset: indeterminate> D Bit Name Function R W 0-6 No functions assigned 0 – 8-15 RDATA Stores received data. – (Receive data) The SIO Receive Buffer Registers are used to store the received data. When the SIO finishes receiving data, the received data is transferred from the SIO Receive Shift Register to the SIO Receive Buffer Register. The SIO Receive Buffer Registers are a read-only register. For 7-bit data (UART mode only), the data are set in D9-D15, with D8 and D7 always set to 0. For 8-bit data, the data are set in D8-D15, with D7 always set to 0. If after completion of reception, the SIO finishes receiving the next data before reading out the content of the SIO Receive Buffer Register, an overrun error occurs and the subsequently received data will not be stored in the Receive Buffer Register. To restart reception normally, clear the Receive Control Register REN (receive enable) bit to 0. Note: When receiving 7 or 8-bit data, the register can be accessed bytewise. SERIAL I/O

12-26 Rev.1.0

12.2.7 SIO Receive Control Registers

I SIO0 Receive Control Register (S0RCNT) <Address: H'0080 0116> I SIO1 Receive Control Register (S1RCNT) <Address: H'0080 0126> I SIO2 Receive Control Register (S2RCNT) <Address: H'0080 0136> I SIO3 Receive Control Register (S3RCNT) <Address: H'0080 0146> I SIO4 Receive Control Register (S4RCNT) <Address: H'0080 0A16> I SIO5 Receive Control Register (S5RCNT) <Address: H'0080 0A26> I SIO6 Receive Control Register (S6RCNT) <Address: H'0080 0A36> I SIO7 Receive Control Register (S7RCNT) <Address: H'0080 0A46> D 0 123456 D 7 RSTAT RFIN REN OVR PTY FLM ERS <When reset: H'00> D Bit Name Function R W

1 RSTAT 0: Not receiving (idle) –

(Receive status bit) 1: Receiving data

2 RFIN 0: No data exist in the receive buffer –

(Receive finished bit) register 1: Data exist in the receive buffer register

3 REN 0: Disables reception

(Receive enable bit) 1: Enables reception

4 OVR 0: No overrun error –

(Overrun error bit) 1: Overrun error occurred

5 PTY (Parity error bit, 0: No parity error –

UART mode only) 1: Parity error occurred

6 FLM (Framing error bit, 0: No framing error –

UART mode only) 1: Framing error occurred

7 ERS (Errorsum bit) 0: No error –

1: Error occurred SERIAL I/O

12-27 Rev.1.0 (1) RSTAT (Receive status) bit (D1) [Set condition] This bit is set to 1 by starting receive operation. When this bit is 1, it means that the SIO is receiving data. [Clear condition] This bit is cleared upon completion of receive operation or by clearing the REN (receive enable) bit to 0. (2) RFIN (Receive finished) bit (D2) [Set condition] This bit is set to 1 when all data bits, after being prepared in the Receive Shift Register, are transferred from that register to the Receive Buffer Register. [Clear condition] This bit is cleared upon reading out the lower byte from the Receive Buffer Register or by clearing the REN (receive enable) bit. However, if an overrun error occurs, this bit cannot be cleared by reading out the lower byte from the Receive Buffer Register. In this case, clear the REN (receive enable) bit to 0. (3) REN (Receive enable) bit (D3) Setting this bit to 1 enables the SIO for reception; setting this bit to 0 disables the SIO against reception while at the same initializing the receiver unit. Pursuant to this bit manipulation, the receive status flag and receive finished flag bits, as well as the overrun error, framing error, parity error, and errorsum flags all are cleared to 0. If the receive enable bit is cleared to 0 while receiving data, the receive operation stops immediately. (4) OVR (Overrun error) bit (D4) [Set condition] This bit is set to 1 when all bits of the next received data have been prepared in the Receive Shift Register while the previously received data still exists in the Receive Buffer Register. The newly received data is not transferred from the Receive Shift Register to the Receive Buffer Register. Although receive operation continues even when the overrun error flag = 1, the received data is not stored in the Receive Buffer Register. To restart reception normally, this bit needs to be cleared. [Clear condition] This bit can only be cleared by clearing the REN (receive enable) bit to 0. SERIAL I/O

12-28 Rev.1.0 (5) PTY (Parity error) bit (D5) This bit is effective in only UART mode. It is fixed to 0 during CSIO mode. [Set condition] This bit is set to 1 when while the SIO Transmit/Receive Mode Register PEN (parity enable/disable) bit is enabled, the parity (even/odd) of the received data does not match the one selected with the said register's PSEL (parity select) bit. [Clear condition] This bit is cleared upon reading out the lower byte from the SIO Receive Buffer Register or by clearing the SIO Receive Control Register REN (receive enable) bit. However, if an overrun error occurs, this bit cannot be cleared by reading out the lower byte from the Receive Buffer Register. In this case, clear the REN (receive enable) bit to 0. (6) FLM (Framing error) bit (D6) This bit is effective in only UART mode. It is fixed to 0 during CSIO mode. [Set condition] This bit is set to 1 when the number of received bits does not match the one selected with the SIO Transmit/Receive Mode Register. [Clear condition] This bit is cleared upon reading out the lower byte from the SIO Receive Buffer Register or by clearing the SIO Receive Control Register REN (receive enable) bit. (7) ERS (Errorsum) bit (D7) [Set condition] This bit is set to 1 when any error-whether an overrun, framing, or parity error-occurs before reception is completed. [Clear condition] For overrun errors, this bit can be cleared by clearing the REN (receive enable) bit to 0. For all other errors, this bit is cleared upon reading out the lower byte from the SIO Receive Buffer Register or by clearing the SIO Receive Control Register REN (receive enable) bit. SERIAL I/O

12-29 Rev.1.0

12.2.8 SIO Baud Rate Registers

I SIO0 Baud Rate Register (S0BAUR) <Address: H'0080 0117> I SIO1 Baud Rate Register (S1BAUR) <Address: H'0080 0127> I SIO2 Baud Rate Register (S2BAUR) <Address: H'0080 0137> I SIO3 Baud Rate Register (S3BAUR) <Address: H'0080 0147> I SIO4 Baud Rate Register (S4BAUR) <Address: H'0080 0A17> I SIO5 Baud Rate Register (S5BAUR) <Address: H'0080 0A27> I SIO6 Baud Rate Register (S6BAUR) <Address: H'0080 0A37> I SIO7 Baud Rate Register (S7BAUR) <Address: H'0080 0A47> D 8 9 1 01 11 21 31 4 D 1 5 BRG <When reset: indeterminate> D Bit Name Function R W 8-15 BRG The baud rate count source selected (Baud rate divide value) with the SIO Mode Register is divided by (n +1) where n = BRG divide value set here. BRG (Baud rate divide value) (D8-D15) The SIO Baud Rate Registers are used to divide the baud rate count source selected with the SIO Mode Register by (n + 1) where n is the BRG value that is set with this register. In the initial state, the BRG value is indeterminate, so always be sure to set the divide value with this register before using serial I/O. The value written to the BRG register while sending or receiving data becomes effective beginning with the next cycle after the BRG counter finished counting. When using an internal clock in CSIO mode (i.e., producing SCLKO output signal), the internal BCLK is first divided by the clock divider and the resulting clock frequency is divided by (n + 1) where n = BRG set value and is further divided by 2 to produce the transmit/receive shift clock. When using an external clock in CSIO mode, the BRG is not used (transmit/receive operations are synchronized to an externally sourced clock). In UART mode, the internal BCLK is first divided by the clock divider and the resulting clock SERIAL I/O

12-30 Rev.1.0 frequency is divided by (n + 1) where n = BRG set value and is further divided by 16 to produce the transmit/receive shift clock. When using SIO0, SIO1, SIO4, or SIO5 in UART mode, the SIO's corresponding port (P84, P87, P65, or P66) may be changed to the SCLKO pin, so that a divided-by-2 clock of BRG output is generated. When using an internal clock (internal clock CSIO mode or UART mode) with f(BCLK) selected for the BRG count source, the BRG value set with this register requires caution. During CSIO mode, make sure the transfer speed will not exceed 2 Mbits/second; during UART mode, make sure the BRG value is equal to or greater than 7. SERIAL I/O

12-31 Rev.1.0 SERIAL I/O

12.3 Transmit Operation in CSIO Mode

12.3.1 Setting the CSIO Baud Rate

The baud rate (data transfer rate) in CSIO mode is determined by a transmit/receive shift clock. The clock source from which to generate the transmit/receive shift clock is selected from the internal clock f(BCLK) or external clock. The CKS (internal/external clock select) bit (SIO Transmit/Receive Mode Register D11 bit) is used to select the clock source. The equation by which to calculate the transmit/receive baud rate values differs with the selected clock source, whether internal or external. (1) When internal clock is selected in CSIO mode When the internal clock is selected, f(BCLK) is divided by the clock divider before being fed into the baud rate generator (BRG). The clock divider's divide-by value is selected from 1, 8, 32, or 256 by using the CDIV (baud rate generator count source select) bits (Transmit Control Register D2, D3 bits). The baud rate generator divides the clock divider output by (baud rate register set value + 1) and then by 2, which results in generating a transmit/receive shift clock. When the internal clock is selected in CSIO mode, the baud rate is calculated using the equation below. 1 (BCLK) Baud rate = [bps] Clock divider's divide-by value × (baud rate register set value + 1) × 2 Baud rate register set value = H'00 to H'FF (Note) Clock divider's divide-by value = 1, 8, 32, or 256 Note: If the divide-by value selected for the baud rate generator count source is "1" (i.e., f(BCLK) itself), make sure the baud rate register value you set does not exceed 2 Mbps. (2) When external clock is selected in CSIO mode In this case, the baud rate generator is not used; instead, the input clock from the SCLKI pin serves directly as CSIO transmit/receive shift clock. The maximum frequency of the SCLKI pin input clock is 1/16 of f(BCLK). Baud rate = SCLKI pin input clock [bps]

12-32 Rev.1.0

12.3.2 Initial Settings for CSIO Transmission

To transmit data in CSIO mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register

• Set the register to CSIO mode
• Select the internal or an external clock (2) Setting SIO Transmit Control Register
• Select the clock divider's divide-by ratio (when internal clock selected) (3) Setting SIO Baud Rate Register When the internal clock is selected, set a baud rate generator value. (Refer to Section 12.3.1, "Setting the CSIO Baud Rate.") (4) Setting SIO Interrupt Mask Register
• Enable or disable the transmit buffer empty interrupt (SIO Interrupt Mask Register) (5) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) When you use a transmit buffer empty interrupt during transmission, set its priority level. (6) Setting DMAC When you issue DMA transfer requests to the internal DMAC when the transmit buffer is empty, set the DMAC. (Refer to Chapter 9, "DMAC.") (7) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.") SERIAL I/O

12-33 Rev.1.0 SERIAL I/O Figure 12.3.1 Procedure for CSIO Transmit Initialization Note 1 : This is necessary when you use the internal clock. Note 2 : When you selected the internal clock and a divide-by ratio = 1, you are subject to limitations that the baud rate generator must be set not to exceed 2 Mbps. Set SIO Transmit/Receive Mode Register Initial settings for CSIO transmission

• Set register to CSIO mode
• Select internal or external clock (When using DMAC)Set DMAC (When using interrupt)Set the Interrupt Controller
• Enable/disable transmit buffer empty interrupt Set SIO Interrupt Mask Register
• Divide-by ratio H'00 to H'FF (Note 2) Set SIO Baud Rate Register
• Select clock divider's divide-by ratio (Note 1) Set SIO Transmit Control Register Set input/output port Operation Mode Register Serial I/O related registers Initial settings for CSIO transmission finished

12-34 Rev.1.0 SERIAL I/O

12.3.3 Starting CSIO Transmission

When all of the following transmit conditions are met after you finished initialization, the serial I/O starts transmit operation. (1) Transmit conditions when CSIO mode internal clock is selected

• The SIO Control Register's transmit enable bit is set to 1.
• Transmit data (8 bits) is written to the lower byte of the SIO Transmit Buffer Register (transmit buffer empty bit = 0). (2) Transmit conditions when CSIO mode external clock is selected
• The SIO Control Register 0's transmit enable bit is set to 1.
• Transmit data is written to the lower byte of the SIO Transmit Buffer Register (transmit buffer empty bit = 0).
• A falling edge of transmit clock on the SCLKI pin is detected. Note 1: While the transmit enable bit is cleared to 0, writes to the transmit buffer register are ignored. Always be sure to set the transmit enable bit to 1 before you write to the transmit buffer register. Note 2: When the internal clock is selected, a write to the lower byte of the transmit buffer register in Note 1 above triggers a start of transmission. Note 3: The transmit status bit is set to 1 at the time data is set in the lower byte of the SIO Transmit Buffer Register. When transmission starts, the serial I/O transmits data following the procedure below.
• Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register.
• Set the transmit buffer empty bit to 1. (Note)
• Start sending data synchronously with the shift clock beginning with the LSB. Note: A transmit buffer empty interrupt request and/or a DMA transfer request can be generated when the transmit buffer is emptied.

12.3.4 Successive CSIO Transmission

Once data is transferred from the transmit buffer register to the transmit shift register, the next data can be written to the transmit buffer register even when transmission of the preceding data is not completed. When the next data is written to the transmit buffer before completion of the preceding data transmission, the preceding and the next data are successively transmitted. To see if data has been transferred from the transmit buffer register to the transmit shift register, check the SIO Status Register's transmit buffer empty flag.

12-35 Rev.1.0 SERIAL I/O

12.3.5 Processing at End of CSIO Transmission

When data transmission is completed, the following operation is automatically performed in hardware. (1) When not transmitting successively

• The transmit status bit is set to 0. (2) When transmitting successively
• When transmission of the last data in a consecutive data train is completed, the transmit status bit is set to 0.

12.3.6 Transmit Interrupt

If a transmit buffer empty interrupt has been enabled by the SIO Interrupt Mask Register, a transmit buffer empty interrupt is generated at the time data is transferred from the transmit buffer register to the transmit shift register. Also, a transmit buffer empty interrupt is generated when the TEN (transmit enable) bit is set to 1 (enabled after being disabled) while a transmit buffer empty interrupt has been enabled. You must set the Interrupt Controller (ICU) before you can use transmit interrupts.

12.3.7 Transmit DMA Transfer Request

When data has been transferred from the transmit buffer register to the transmit shift register, a transmit DMA transfer request for the corresponding SIO channel is ouput to the DMAC. This transfer request is also output when the TEN (transmit enable) bit is set to 1 (enabled after being disabled). You must set the Interrupt Controller (ICU) before you can transmit data using DMA transfers.

12-36 Rev.1.0 SERIAL I/O Figure 12.3.2 Transmit Operation during CSIO Mode (Hardware Processing) Note : This applies when transmit interrupt has been enabled by SIO Interrupt Mask Register. The following processing is automatically executed in hardware

• Transfer content of transmit buffer to transmit shift register
• Set transmit buffer empty bit to 1 Transmit data Y (Successive transmission) Transmit conditions met? Y N N Clear transmit status bit to 0 Transmit DMA transfer request Transmit interrupt request (Note) CSIO transmit operation starts CSIO transmit operation completed Transmit conditions met?

12-37 Rev.1.0 SERIAL I/O Figure 12.3.3 Example of CSIO Transmission (Transmitted Only Once, with Transmit Interrupt Used) Note 1 : Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit Note 2 : When transmit interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3 : The Interrupt Controller IVECT register is read or "SIO Transmit Interrupt Control Register" interrupt request bit cleared Note 4 : Transmit interrupt request is generated when transmission is enabled. Note 5 : Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied.

12.3.8 Typical CSIO Transmit Operation

The following shows a typical transmit operation in CSIO mode. : Processing by software : Interrupt generation Internal clock selected External clock selected <CSIO on receive side> SCLKO TXD SCLKI RX D Transmit clock (SCLKO ) Set Write to transmit buffer register Transmit buffer empty bit Transmit enable bit Cleared Transmit status bit D7 D6 D5 D4 D3 D2 D1 D0TX D SIO transmit interrupt (Note 1) Transmit interrupt (Note 4) Interrupt request accepted Content of transmit buffer register transferred to transmit shift registe r Cleared by completion of transmissio n Set by a write to transmit buffer (Note 2) (Note 3) <CSIO on transmit side> <CSIO on transmit side> Transmit interrupt (Note 5

12-38 Rev.1.0 SERIAL I/O Figure 12.3.4 Example of CSIO Transmission (Successive Transmission, with Transmit Buffer Empty and Transmit Finished Interrupts Used) Note 1 : Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit Note 2 : When transmit interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3 : Transmit interrupt request is generated when transmission is enabled. Note 4 : Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. : Interrupt generation First data Next data (Note 2) (Note 3) (Note 2) Upon transmit buffer empty interrupt, next data is written (First data) (Next data) (Note 4) : Processing by software Internal clock selected External clock selected <CSIO on receive side> SCLKO TXD SCLKI RXD Transmit clock (SCLKO) Set Transmit buffer empty bit Transmit enable bit Cleared Transmit status bit D7 D6 D5 D0 D7 D6 D5 D0TXD SIO transmit interrupt (Note 1) <CSIO on transmit side> <CSIO on transmit side> Write to transmit buffer register Write to transmit buffer register

12-39 Rev.1.0 SERIAL I/O

12.4 Receive Operation in CSIO Mode

12.4.1 Initial Settings for CSIO Reception

To receive data in CSIO mode, initialize the serial I/O following the procedure described below. Note, however, that because the receive shift clock is derived from operation of the transmit circuit, you need to execute transmit operation even when you only want to receive data. (1) Setting SIO Transmit/Receive Mode Register

• Set the register to CSIO mode
• Select the internal or an external clock (2) Setting SIO Transmit Control Register
• Select the clock divider's divide-by ratio (when internal clock selected) (3) Setting SIO Baud Rate Register When the internal clock is selected, set a baud rate generator value. (Refer to Section 12.3.1, "Setting the CSIO Baud Rate.") (4) Setting SIO Interrupt Mask Register
• Enable or disable the transmit buffer empty interrupt (SIO Interrupt Mask Register)
• Select the cause of receive interrupt (receive finished/error) (Cause of Receive Interrupt Select Register) (5) Setting SIO Receive Control Register Set the receive enable bit (6) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) When you use a transmit interrupt or receive interrupt during transmission/reception, set its priority level. (7) Setting the DMAC When you generate a DMA transfer request to the internal DMAC when the transmit buffer is empty or transmission is completed, set the DMAC. (Refer to Chapter 9, "DMAC.")

12-40 Rev.1.0 Figure 12.4.1 Procedure for CSIO Receive Initialization Note 1 : This is necessary when you use the internal clock. Note 2 : When you selected the internal clock and a divide-by ratio = 1, you are subject to limitations that the baud rate generator must be set not to exceed 2 Mbps. (8) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.") SERIAL I/O Set SIO Transmit/Receive Mode Register Initial settings for CSIO reception

• Set to CSIO mode
• Select internal or external clock (When using DMAC)Set DMAC (When using interrupt)Set the Interrupt Controller
• Enable/disable transmit buffer empty interrupt Set SIO Interrupt Mask Register
• Divide-by ratio H'00 to H'FF (Note 2) Set SIO Baud Rate Register
• Select clock divider's divide-by ratio (Note 1) Set SIO Transmit Control Register Set input/output port Operation Mode Register Serial I/O related registers Initial settings for CSIO reception finished
• Set receive enable bitSet SIO Receive Control Register

12-41 Rev.1.0 SERIAL I/O

12.4.2 Starting CSIO Reception

When all of the following receive conditions are met after you finished initialization, the serial I/O starts receive operation. (1) Receive conditions when CSIO mode internal clock is selected

• The SIO Receive Control Register's receive enable bit is set to 1.
• Transmit conditions are met. (Refer to Section 12.3.3, "Starting CSIO Transmission.") (2) Receive conditions when CSIO mode external clock is selected
• The SIO Receive Control Register's receive enable bit is set to 1.
• Transmit conditions are met. (Refer to Section 12.3.3, "Starting CSIO Transmission.") Note: The receive status bit is set to 1 at the time dummy data is set in the lower byte of the SIO Transmit Buffer Register. When the above conditions are met, the serial I/O starts receiving 8-bit serial data (LSB first) synchronously with the receive shift clock.

12.4.3 Processing at End of CSIO Reception

When data reception is completed, the following operation is automatically performed in hardware. (1) When reception is completed normally The receive-finished (receive buffer full) bit is set to 1. Note 1: If a receive-finished (receive buffer full) interrupt has been enabled, an interrupt request is generated. Note 2: A DMA transfer request is generated. (2) When error occurs during reception When an error (only overrun error in CSIO mode) occurs during reception, the overrun error bit and receive sum bit are set to 1. Note 1: If a receive-finished interrupt has been selected (by SIO Cause of Receive Interrupt Select Register), neither a receive-finished interrupt request nor a DMA transfer request is generated. Note 2: If a receive error interrupt has been selected (by SIO Cause of Receive Interrupt Select Register), a receive error interrupt request is generated when interrupt requests are enabled. No DMA transfer requests are generated.

12-42 Rev.1.0 Figure 12.4.2 Receive Operation during CSIO Mode (Hardware Processing) SERIAL I/O

12.4.4 About Successive Reception

When the following conditions are met at completion of data reception, data may be received successively.

• The receive enable bit is set to 1.
• Transmit conditions are met.
• No overrun error has occurred. Receive data Set SIO Receive Control Register's receive-finished bit to 1 Store received data in Receive Buffer Register Set SIO Receive Control Register's overrun error and receive sum error bits to 1 Overrun error? Receive conditions met? Y N CSIO receive operation starts N Y CSIO receive operation completed

12-43 Rev.1.0 SERIAL I/O

12.4.5 Flags Indicating the Status of CSIO Receive Operation

Following flags are available that indicate the status of receive operation in CSIO mode.

• SIO Receive Control Register receive status bit
• SIO Receive Control Register receive-finished bit
• SIO Receive Control Register receive error bit
• SIO Receive Control Register overrun error bit After reception is completed, you may read out the content of the SIO Receive Buffer Register, but if the serial I/O finishes receiving the next data before you read, an overrun error occurs. In this case, the data received thereafter is not transferred to the SIO Receive Buffer Register. To restart reception, temporarily clear the receive enable bit to 0 and initialize the receive control block before you restart. The said receive enable bit can be cleared, when there are no receive errors(note) encountered, by reading the lower byte from the SIO Receive Buffer Register or clearing the REN (receive enable) bit. If any receive error has occurred, it can only be cleared by clearing the REN (receive enable) bit, and cannot be cleared by reading the lower byte from the SIO Receive Buffer Register. Note: Overrun error is the only error that can be detected during reception in CSIO mode.

12-44 Rev.1.0 SERIAL I/O Figure 12.4.3 Example of CSIO Reception (When Received Normally)

12.4.6 Typical CSIO Receive Operation

The following shows a typical receive operation in CSIO mode. Note 1 : Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit Note 2 : When receive-finished interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3 : The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register" interrupt request bit cleared SIO receive interrupt (Note 1) (When receive-finished interrupt is selected) Clock stopped Automatically cleared for each receive operation performed Receive-finished bit Read from receive buffer (When receive error interrupt is selected) Receive-finished interrupt (Note 2) Interrupt request accepted (Note 3) No interrupt request Internal clock selected External clock selected <CSIO on transmit side> SCLKO RXD SCLKI TXD Receive clock (SCLKI) Set Receive enable bit Cleared Receive status bit <CSIO on receive side> <CSIO on receive side> Set by a write to transmit buffer D7 D6 D5 D4 D3 D2 D1 D0RXD : Processing by software : Interrupt generation

12-45 Rev.1.0 SERIAL I/O Figure 12.4.4 Example of CSIO Reception (When Overrun Error Occurred) Note 1 : Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit Note 2 : When receive-finished interrupt is enabled Note 3 : When receive error interrupt is enabled Note 4 : Receive enable bit cleared Note 5 : The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register" interrupt request bit cleared First data reception completed Overrun error bit Receive buffer not read during this interval Overrun error bit cleared (Note 4) Receive error interrupt (Note 3) Internal clock selected External clock selected <CSIO on transmit side> SCLKO RXD SCLKI TXD Transmit clock (SCLKO) Set Receive enable bit <CSIO on receive side> <CSIO on receive side> Cleared D7 D6 D0 D7 D6 D0RXD Set SIO receive interrupt (Note 1) (When receive-finished interrupt is selected) (When receive error interrupt is selected) Receive-finished interrupt (Note 2) Interrupt request accepted (Note 5) Interrupt request accepted (Note 5) : Processing by software : Interrupt generation Next data reception completed Receive-finished bit

12-46 Rev.1.0 SERIAL I/O

12.5 Precautions on Using CSIO Mode

• Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register's BRG count source select bit must always be set when not operating. When transmitting or receiving data, be sure to check that transmission and/or reception under way has been completed and clear the transmit and receive enable bits before you set the registers.
• Settings of Baud Rate (BRG) Register If you selected f(BCLK) with the BRG clock source select bit, make sure the BRG register value you set does not exceed 2 Mbps.
• About successive transmission To transmit multiple data successively, set the next transmit data in the SIO Transmit Buffer Register before transmission of the preceding data is completed.
• About reception Because during CSIO mode the receive shift clock is derived from operation of the transmit circuit, you need to execute transmit operation (by sending dummy data) even when you only want to receive data. In this case, note that if the port function is set for TXD pin (by setting the operation mode register to 1), dummy data is actually output from the pin.
• About successive reception To receive multiple data successively, set data (dummy data) in the SIO Transmit Buffer Register before the transmitter starts sending data.
• Transmit/receive operations using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before you start serial communication.
• About the receive-finished bit If a receive error (overrun error) occurs, the receive-finished bit cannot be cleared by reading out the receive buffer register. In this case, it can only be cleared by clearing the receive enable bit.

12-47 Rev.1.0 SERIAL I/O

• About overrun error If all bits of the next receive data are received in the SIO Receive Shift Register before you read out the SIO Receive Buffer Register (an overrun error occurs), the receive data is not stored in the Receive Buffer Register and the Receive Buffer Register retains the previously received data. Thereafter, although receive operation is continued, no receive data is stored in the Receive Buffer Register (the receive status bit = 1). To restart reception normally, you need to temporarily clear the receive enable bit before you restart. This is the only way you can clear the overrun error flag.
• About DMA transfer request generation during SIO transmission If the Transmit Buffer Register becomes empty (the transmit buffer empty flag = 1) while the transmit enable bit is set to 1 (transmit enabled), an SIO transmit buffer empty DMA transfer request is generated.
• About DMA transfer request generation during SIO reception When the receive-finished bit is set to 1 (the receive buffer register full), a receive-finished DMA transfer request is generated. However, if an overrun error has occurred, this DMA transfer request is not generated.

12-48 Rev.1.0 SERIAL I/O

12.6 Transmit Operation in UART Mode

12.6.1 Setting the UART Baud Rate

The baud rate (data transfer rate) during UART mode is determined by a transmit/receive shift clock. In UART mode, the source for this transmit/receive shift clock is always the internal clock regardless of how the internal/external clock select bit (SIO Transmit/Receive Mode Register bit D11) is set. (1) Calculating the UART mode baud rate After being divided by the clock divider, f(BCLK) is fed into the Baud Rate Generator (BRG), after which it is further divided by 16 to produce a transmit/receive shift clock. The clock divider's divide-by value is selected from 1, 8, 32, or 256(note) using the SIO Transmit Control Register's CDIV (baud rate generator count source select) bits (D2, D3). The Baud Rate Generator divides the clock it received from the clock divider by (baud rate register set value + 1) and further divides the resulting clock by 16 to produce a transmit/receive shift clock. During UART mode (in which the internal clock is always used), the baud rate is calculated using the equation below. 1 (BCLK) Baud rate = [bps] Clock divider's divide-by value × (baud rate register set value + 1) × 16 Baud rate register set value = H'00 to H'FF (Note) Clock divider's divide-by value = 1, 8, 32, or 256 Note: If the divide-by value selected for the baud rate generator count source is "1" (i.e., f(BCLK) itself), make sure the baud rate register value you set is equal to or greater than 7.

12-49 Rev.1.0 SERIAL I/O

12.6.2 UART Transmit/Receive Data Formats

The transmit/receive data format during UART mode is determined by setting the SIO Transmit/ Receive Mode Register. Shown below is the transmit/receive data format that can be used in UART mode. Figure 12.6.1 Example of Transmit/Receive Data Format in UART Mode Table 12.6.1 Transfer Data in UART Mode Bit Name Content ST (start bit) Indicates the beginning of data transmission. This is a low signal of a one bit duration, which is added immediately before the transmit data. D0-D8 (character bits) Transmit/receive data transferred via serial I/O. In UART mode, data in 7, 8, or 9 bits can be transmitted/received. PAR (parity bit) Added to the transmit/receive characters. When parity is enabled, parity is automatically set in such a way that the number of 1's in characters including the parity bit itself is always even or odd as selected by the even/odd parity select bit. SP (stop bit) Indicates the end of data transmission, and is added immediately after characters (or if parity enabled, immediately after the parity bit). The stop bit can be chosen to be one bit or two bits long. ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP SP LSB MSB ST Parity bitStop bitStart bit Data bits (8 bits) Transmit data Next data

12-50 Rev.1.0 Figure 12.6.2 Selectable Data Formats during UART Mode Note 1 : The high-order bits of the SIO Receive Buffer Register's selected character bits are fixed to 0. Note 2 : The data bit numbers (Dn) above indicate bit numbers in a data list, and not the register bit numbers (Dn). SERIAL I/O ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP LSB MS B Start bit Character (data) bits Parity bit Stop bit D0 D7 D8 D1 5 SIO Transmit Buffer Register SIO Receive Buffer Register ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 PAR SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP SP ST D7 D6 D5 D4 D3 D2 D1 D0 SP LSB MSB ST D7 D6 D5 D4 D3 D2 D1 PAR SP SP ST D7 D6 D5 D4 D3 D2 D1 PAR SP ST D7 D6 D5 D4 D3 D2 D1 SP SP ST D7 D6 D5 D4 D3 D2 D1 SP LSB MSB 8-bit characters 7-bit characters ST : D0 - D7 : PAR : SP : 9-bit characters 8-bit characters 7-bit characters

12-51 Rev.1.0 SERIAL I/O

12.6.3 Initial Settings for UART Transmission

To transmit data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register

• Set the register to UART mode
• Set parity (when enabled, select odd/even)
• Set stop bit length
• Set character length Note: During UART mode, settings of the internal/external clock select bit have no effect (only the internal clock is useful). (2) Setting SIO Transmit Control Register
• Select the clock divider's divide-by ratio. (3) Setting SIO Baud Rate Register Set a baud rate generator value. (Refer to Section 12.6.1, "Setting the UART Baud Rate.") (4) Setting SIO Interrupt Mask Register
• Enable or disable SIO transmit interrupt. (5) Setting the Interrupt Controller (SIO Transmit Interrupt Control Register) When you use a transmit interrupt, set its priority level. (6) Setting DMAC When you issue DMA transfer requests to the internal DMAC when the transmit buffer is empty, set the DMAC. (Refer to Chapter 9, "DMAC.") (7) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.")

12-52 Rev.1.0 Figure 12.6.3 Procedure for UART Transmit Initialization Note : When you selected f(BCLK) for the BRG count source (CDVI), you are subject to limitations that the baud rate register value you set must be equal to or greater than 7. SERIAL I/O Set SIO Transmit/Receive Mode Register Initial settings for UART transmission

• Set register to UART mode
• Set parity (when enabled, select odd/even) (When using DMAC)Set DMAC related registers (When using interrupt) Set the Interrupt Controller • Enable/disable transmit interrupt Set SIO Interrupt Related Registers
• Divide-by ratio H'00 to H'FF (Note)Set SIO Baud Rate Register
• Select clock divider's divide-by ratioSet SIO Transmit Control Register Set input/output port Operation Mode Register Serial I/O related register s Initial settings for UART transmission finished
• Set stop bit length
• Set character length

12-53 Rev.1.0 SERIAL I/O

12.6.4 Starting UART Transmission

When all of the following transmit conditions are met after you finished initialization, the serial I/O starts transmit operation.

• The SIO Transmit Control Register's TEN (transmit enable) bit is set to 1. (Note)
• Transmit data is written to the SIO Transmit Buffer Register (transmit buffer empty bit = 0). Note: While the transmit enable bit is cleared to 0, writes to the transmit buffer are ignored. Always be sure to set the transmit enable bit to 1 before you write to the transmit buffer register. When transmission starts, the serial I/O transmits data following the procedure below.
• Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register.
• Set the transmit buffer empty bit to 1. (Note)
• Start sending data synchronously with the shift clock beginning with the LSB. Note : A transmit buffer empty interrupt request and/or a DMA transfer request can be generated when the transmit buffer is emptied.

12.6.5 Successive UART Transmission

Once data is transferred from the transmit buffer register to the transmit shift register, the next data can be written to the transmit buffer register even when transmission of the preceding data is not completed. When the next data is written to the transmit buffer before completion of the preceding data transmission, the preceding and the next data are successively transmitted. To see if data has been transferred from the transmit buffer register to the transmit shift register, check the SIO Transmit Control Register's transmit buffer empty flag.

12-54 Rev.1.0 SERIAL I/O

12.6.6 Processing at End of UART Transmission

When data transmission is completed, the following operation is automatically performed in hardware. (1) When not transmitting successively

• The transmit status bit is set to 0. (2) When transmitting successively
• When transmission of the last data in a consecutive data train is completed, the transmit status bit is set to 0.

12.6.7 Transmit Interrupt

If a transmit buffer empty interrupt has been enabled by the SIO Interrupt Mask Register, a transmit buffer empty interrupt is generated at the time data is transferred from the transmit buffer register to the transmit shift register. Also, a transmit buffer empty interrupt is generated when the TEN (transmit enable) bit is set to 1 (enabled after being disabled) while a transmit buffer empty interrupt has been enabled. You must set the Interrupt Controller (ICU) before you can use transmit interrupts.

12.6.8 Transmit DMA Transfer Request

When data has been transferred from the transmit buffer register to the transmit shift register, a transmit DMA transfer request for the corresponding SIO channel is ouput to the DMAC. This transfer request is also output when the TEN (transmit enable) bit is set to 1 (enabled after being disabled). You must set the Interrupt Controller (ICU) before you can transmit data using DMA transfers.

12-55 Rev.1.0 SERIAL I/O Figure 12.6.4 Transmit Operation during UART Mode (Hardware Processing) Note : This applies when transmit interrupt has been enabled by SIO Interrupt Mask Register. The following processing is automatically executed in hardware

• Transfer content of transmit buffer to transmit shift register
• Set transmit buffer empty bit to 1 Transmit data Y (Successive transmission) Transmit conditions met? Y N N Clear transmit status bit to 0 Transmit DMA transfer request Transmit interrupt request (Note) UART transmit operation starts UART transmit operation completed Transmit conditions met?

12-56 Rev.1.0 SERIAL I/O Figure 12.6.5 Example of UART Transmission (Transmitted Only Once, with Transmit Interrupt Used)

12.6.9 Typical UART Transmit Operation

The following shows a typical transmit operation in CSIO mode. Note 1 : Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit Note 2 : When transmit-finished interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3 : The Interrupt Controller IVECT register is read or "SIO Transmit Interrupt Control Register" interrupt request bit cleared Note 4 : Transmit interrupt request is generated when transmission is enabled. Note 5 : Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. : Processing by software : Interrupt generation <UART on receive side> TXD RX D Set Write to transmit buffer register Transmit buffer empty bit Transmit enable bit Cleared Transmit status bit ST D7 D6 D0 PAR ST STTX D SIO transmit interrupt (Note 1) Transmit interrupt (Note 4) Interrupt request accepted Transferred from transmit buffer to transmit shift register (transmission starts) (Note 2) (Note 3) <UART on transmit side> <UART on transmit side> Transmit interrupt (Note 5) Cleared

12-57 Rev.1.0 SERIAL I/O Figure 12.6.6 Example of UART Transmission (Successive Transmission, with Transmit Interrupt Used) Note 1 : Change of the Interrupt Controller "SIO Transmit Interrupt Control Register" interrupt request bit Note 2 : When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3 : The Interrupt Controller IVECT register is read or "SIO Transmit Interrupt Control Register" interrupt request bit cleared Note 4 : Transmit interrupt request is generated when transmission is enabled. Note 5 : Even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied. : Interrupt generation First data Next data (Note 2) (Note 4) (Note 2) Upon transmit interrupt, next data is written (First data) (Next data) (Note 5) : Processing by software <UART on receive side> TXD RXD Set Transmit buffer empty bit Transmit enable bit Cleared Transmit status bit D7ST D0 D7 SP D0TXD SIO transmit interrupt (Note 1) <UART on transmit side> <UART on transmit side> Write to transmit buffer register Write to transmit buffer register Transferred from transmit buffer to transmit shift register (transmission starts) Cleared when transmission of last data is completed SP ST Interrupt request accepted(Note 3)

12-58 Rev.1.0 SERIAL I/O

12.7 Receive Operation in UART Mode

12.7.1 Initial Settings for UART Reception

To receive data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register

• Set the register to UART mode
• Set parity (when enabled, select odd/even)
• Set stop bit length
• Set character length Note : During UART mode, settings of the internal/external clock select bit have no effect (only the internal clock is useful). (2) Setting SIO Transmit Control Register
• Select the clock divider's divide-by ratio. (3) Setting SIO Baud Rate Register Set a baud rate generator value. (Refer to Section 12.6.1, "Setting the UART Baud Rate.") (4) Setting SIO interrupt related registers
• Cause of Receive Interrupt Select Register Select the cause of receive interrupt (receive finished/receive error)
• Interrupt Mask Register Enable/disable receive interrupts (5) Setting the Interrupt Controller When you use interrupts during reception, set its priority level. (6) Setting DMAC When you issue DMA transfer requests to the internal DMAC when reception is completed, set the DMAC. (Refer to Chapter 9, "DMAC.") (7) Selecting pin functions Because the serial I/O related pins serve dual purposes (shared with input/output ports), set pin functions. (Refer to Chapter 8, "Input/Output Ports and Pin Functions.")

12-59 Rev.1.0 SERIAL I/O Figure 12.7.1 Procedure for UART Receive Initialization Note : When you selected the clock divider's divide-by ratio = 1, you are subject to limitations that the baud rate register value you set must be equal to or greater than 7. Set SIO Transmit/Receive Mode Register Initial settings for UART reception

• Set register to UART mode
• Set parity (when enabled, select odd/even) (When using DMAC)Set DMAC related registers (When using interrupt)Set the interrupt controller SIO Receive Interrupt Control Register Set SIO Interrupt Related Registers
• Divide-by ratio H'00 to H'FF (Note)Set SIO Baud Rate Register
• Select clock divider's divide-by ratioSet SIO Transmit Control Register Set input/output port Operation Mode Register Serial I/O related register s Initial settings for UART reception finished
• Set stop bit length
• Set character length
• Cause of Receive Interrupt Select Register (receive finished/receive error)
• Interrupt Mask Register (enable/disable receive interrupts)

12-60 Rev.1.0 SERIAL I/O

12.7.2 Starting UART Reception

When all of the following receive conditions are met after you finished initialization, the serial I/O starts receive operation.

• The SIO Receive Control Register's receive enable bit is set to 1
• Start bit (falling edge signal) is applied to the RXD pin When the above conditions are met, the serial I/O enters UART receive operation. However, if the start bit when checked again at the first rise of the internal receive shift clock is detected high for reason of noise, etc., the serial I/O stops receive operation and waits for the start bit again.

12.7.3 Processing at End of UART Reception

When data reception is completed, the following operation is automatically performed in hardware. (1) When reception is completed normally The receive-finished (receive buffer full) bit is set to 1. Note 1: If a receive-finished (receive buffer full) interrupt has been enabled, an interrupt request is generated. Note 2: A DMA transfer request is generated. (2) When error occurs during reception When an error occurs during reception, the corresponding error bit (OE, FE, or PE) and the receive sum bit are set to 1. Note 1: If a receive-finished interrupt has been selected (by SIO Cause of Receive Interrupt Select Register), a receive-finished interrupt request is generated when interrupt requests are enabled. However, if an overrun error has occurred, this interrupt is not generated. Note 2: If a receive error interrupt has been selected (by SIO Cause of Receive Interrupt Select Register), a receive error interrupt request is generated when interrupt requests are enabled. Note 3: No DMA transfer requests are generated.

12-61 Rev.1.0 SERIAL I/O Figure 12.7.2 Receive Operation during UART Mode (Hardware Processing) Receive data Y Transfer data from SIO Receive Shift Register to SIO Receive Buffer Register Set SIO Receive Control Register's receive-finished bit to 1 Set receive status bit to 1 Overrun error? Parity error or framing error? Start bit detected normally? Set SIO Receive Control Register's overrun error bit and error sum bit to 1 Set SIO Receive Control Register's corresponding error bit and receive error sum bit to 1 N UART reception completed The following processing is automatically executed in hardware Transmit conditions met? Y N UART receive operation starts Y N N Y

12-62 Rev.1.0 SERIAL I/O Figure 12.7.3 Example of UART Reception (When Received Normally)

12.7.4 Typical UART Receive Operation

The following shows a typical receive operation in UART mode. Note 1 : Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit Note 2 : When receive-finished interrupt is enabled (DMA transfer can also be requested at the same timing) Note 3 : The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register" interrupt request bit cleared SIO receive interrupt (Note 1) (When receive-finished interrupt is selected) Automatically cleared for each receive operation performed Receive-finished bit Read from receive buffer (When receive error interrupt is selected) Receive-finished interrupt (Note 2) Interrupt request accepted (Note 3) No interrupt request Internal clock selected <UART on transmit side> RXD TXD Set Receive enable bit (SIO Receive Control Register) Cleared Receive status bit <UART on receive side> <UART on receive side> : Processing by software : Interrupt generation ST D7 D6 D0 PAR SP SPRXD

12-63 Rev.1.0 SERIAL I/O Figure 12.7.4 Example of UART Reception (When Overrun Error Occurred) Note 1 : Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit Note 2 : When receive-finished interrupt is enabled Note 3 : When receive error interrupt is enabled Note 4 : This is done by clearing the receive enable bit to 0. Note 5 : The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register" interrupt request bit cleared First data reception completed Overrun error bit Receive buffer not read during this interval Overrun error bit cleared (Note 4) Receive error interrupt (Note 3) <UART on transmit side> RXD TXD Set <UART on receive side> <UART on receive side> ST D7 SP ST D7 SPRXD Set SIO receive interrupt (Note 1) (When receive-finished interrupt is selected) (When receive error interrupt is selected) Receive-finished interrupt (Note 2) Interrupt request accepted (Note 5) Interrupt request accepted (Note 5) : Processing by software : Interrupt generation Next data reception completed (Note 5) Receive enable bit (SIO Receive Control Register) Receive-finished bit

12-64 Rev.1.0 SERIAL I/O

12.8 Fixed Period Clock Output Function

When using SIO0, SIO1, SIO4 or SIO5 in UART mode, you can choose the relevant port (P84, P87, P65 or P66) to function as the SCLKO0, SCLKO1, SCLKO4 or SCLKO5 pin. In this way, a clock derived from BRG output by dividing it by 2 can be output from the SCLKO pin. Note: This clock is output all the time, not just during data transfer. Figure 12.8.1 Example of Fixed Period Clock Output SCLKO TXD RXD Clock output to peripheral circuits UART transmit/receive ST SP Data ST SP Data 50% 50 % BRG period Internal BRG output SCLKO output 1. Configuration when using BRG/2 clock 2. Operation timing

12-65 Rev.1.0 SERIAL I/O

12.9 Precautions on Using UART Mode

• Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register's BRG count source select bit must always be set when not operating. When transmitting or receiving data, be sure to check that transmission and/or reception under way has been completed and clear the transmit and receive enable bits before you set the registers.
• Settings of Baud Rate (BRG) Register If you selected f(BCLK) with the BRG clock source select bit, make sure the BRG register value you set is equal to or greater than 7. The value written to the SIO Baud Rate Register becomes effective beginning with the next period after the BRG counter finished counting. However, when transmit and receive operations are disabled, the register value can be changed at the same time you write to the register.
• Transmit/receive operations using DMA To transmit/receive data in DMA request mode, enable the DMAC to accept transfer requests (by setting the DMA Mode Register) before you start serial communication.
• About overrun error If all bits of the next receive data are received in the SIO Receive Shift Register before you read out the SIO Receive Buffer Register (an overrun error occurs), the receive data is not stored in the Receive Buffer Register and the Receive Buffer Register retains the previously received data. Once an overrun error occurs, no receive data is stored in the Receive Buffer Register although receive operation is continued. To restart reception normally, you need to temporarily clear the receive enable bit before you restart. This is the only way you can clear the overrun error flag.

12-66 Rev.1.0 SERIAL I/O

• Flags indicating the status of UART receive operation Following flags are available that indicate the status of receive operation during UART mode.
• SIO Receive Control Register receive status bit
• SIO Receive Control Register receive-finished bit
• SIO Receive Control Register receive error sum bit
• SIO Receive Control Register overrun error bit
• SIO Receive Control Register parity error bit
• SIO Receive Control Register framing error bit The manner in which the receive-finished bit and various error bit flags are cleared varies depending on whether an overrun error has occurred or not, as described below. [When no overrun error has occurred] Said bits can be cleared by reading the lower byte from the receive buffer register or clearing the receive enable bit to 0. [When an overrun error has occurred] Said bits can only be cleared by clearing the receive enable bit to 0.

13.1 Outline of the CAN

13.2 CAN Module Related

13.3 CAN Protocol

13.4 Initialization of the CAN

13.5 Transmitting Data Frames

13.6 Receiving Data Frames

13.7 Transmitting Remote

13.8 Receiving Remove Frames

13-2 Rev.1.0 Table 13.1.1 Outline of the CAN Modules Item Content Protocol CAN Specification 2.0B active Number of message slots 16 slots (14 global slots and two local slots) x 2 Polarity 0: Dominant 1: Recessive Acceptance filter Global mask: one mask x 2 Local mask: two masks x 2 Baud rate 1 Time quantum (Tq) = (BRP + 1) / CPU clock (Note) (BRP: baud rate prescaler set value) Baud rate = 1 … Max 1 Mbps Tq period x number of Tq's in one bit BRP : 1-255 (0: disable) Number of Tq's in one bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 Propagation Segment : 1-8Tq Phase Segment 1 : 1-8Tq Phase Segment 2 : 2-8Tq (IPT = 2) Remote frame automatic The message slot that received a remote frame automatically to send a data frame. response function Time stamp function This time stamp function is based on a 16-bit counter. The count period can be setto divide-by-1, 2, 3, or 4 with respect to the CAN bus bit period as the fundamental period. BasicCAN mode BasicCAN function is materialized using two local slots. Transmit abort function Transmit request can be canceled. Loopback function The data transmitted by CAN module itself is received. Return bus-off function Forcibly placed into error active mode after clearing the error counter. Note: The maximum allowable error of oscillation depends on the system configuration (bus length, communication rate, CAN bus transceiver, sampling position, and bit configuration). CAN MODULES

13.1 Outline of the CAN Modules

The 32172/32173 contains two Full CAN modules (CAN0 and CAN1) compliant with CAN (Controller Area Network) Specification 2.0B active. CAN0 and CAN1 each have 16 message slots and three mask registers. Making use of these message slots and mask registers helps to reduce data processing load on the CPU. The Full CAN modules are outlined below.

13-3 Rev.1.0 ADDRESS SPACE

13.1 Outline of the Address Space

Table 13.1.2 Interrupt Generating Functions of the CAN Modules CAN module interrupt source ICU interrupt source CAN0 transmit complete interrupt CAN0 transmit/receive & error interrupt CAN0 receive complete interrupt CAN0 transmit/receive & error interrupt CAN0 bus error interrupt CAN0 transmit/receive & error interrupt CAN0 error-passive interrupt CAN0 transmit/receive & error interrupt CAN0 bus-off interrupt CAN0 transmit/receive & error interrupt CAN1 transmit complete interrupt CAN1 transmit/receive & error interrupt CAN1 receive complete interrupt CAN1 transmit/receive & error interrupt CAN1 bus error interrupt CAN1 transmit/receive & error interrupt CAN1 error-passive interrupt CAN1 transmit/receive & error interrupt CAN1 bus-off interrupt CAN1 transmit/receive & error interrupt

13-4 Rev.1.0 CTX0 CRX0 CAN0 Protocol Controller 2.0B active CAN0 Message Slot 0-15 Control Register CAN0 Global Mask Register CAN0 Local Mask Register A CAN0 Local Mask Register B CAN0 Extended ID Register Message Memory Acceptance Filtering 16-bit Timer CAN0 Time stamp Register CAN0 Configuration Register CAN0 Slot Status Register CAN0 Slot Interrupt Control Register CAN0 REC Register CAN0 TEC Register CAN0 Error Interrupt Control Register Interrupt Control Circuit CAN0 transmit/receive & error interrupt Data bus (1) Message ID (2) Data length code (3) Message data (4) Time stamp CAN0 Status Register CAN0 Control Register CTX1 CRX1 CAN1 Protocol Controller 2.0B active CAN1 Message Slot 0-15 Control Register CAN1 Global Mask Register CAN1 Local Mask Register A CAN1 Local Mask Register B CAN1 Extended ID Register Message Memory Acceptance Filtering 16-bit Timer CAN1 Time stamp Register CAN1 Configuration Register CAN1 Slot Status Register CAN1 Slot Interrupt Control Register CAN1 REC Register CAN1 TEC Register CAN1 Error Interrupt Control Register Interrupt Control Circuit CAN1 transmit/receive & error interrupt Data bus (1) Message ID (2) Data length code (3) Message data (4) Time stamp CAN1 Status Register CAN1 Control Register Figure 13.1.1 Block Diagram of the CAN Modules CAN MODULES

13-5 Rev.1.0

13.2 CAN Module Related Registers

A CAN module related register map is shown below. Figure 13.2.1 CAN Module Related Register Map (1/8) CAN MODULES +0 address +1 address D0 D7 D8 D15 H'0080 1034 H'0080 1032 H'0080 1038 H'0080 1036 H'0080 103C H'0080 103A H'0080 1054 Address H'0080 1058 H'0080 1056 H'0080 1052 H'0080 105A CAN0 Configuration Register(CAN0CONF) CAN0 Global Mask Register Standard ID0(C0GMSKS0) CAN0 Local Mask Register A Standard ID0(C0LMSKAS0) H'0080 1000 H'0080 1002 H'0080 1004 H'0080 1008 H'0080 100A H'0080 1010 H'0080 100E H'0080 1006 H'0080 1028 H'0080 102C H'0080 1030 H'0080 102E H'0080 102A H'0080 105C H'0080 100C H'0080 1050 CAN0 Control Register(CAN0CNT) CAN0 Extended ID Register(CAN0EXTID) CAN0 Time stamp Count Register(CAN0TSTMP) CAN0 Slot Interrupt Status Register(CAN0SLIST) CAN0 Message Slot 3 Control Register(C0MSL3CNT)CAN0 Message Slot 2 Control Register(C0MSL2CNT) CAN0 Message Slot 4 Control Register(C0MSL4CNT) CAN0 Status Register(CAN0STAT) CAN0 Receive Error Count Register(CAN0REC) CAN0 Transmit Error Count Register(CAN0TEC) CAN0 Message Slot 0 Control Register(C0MSL0CNT) CAN0 Message Slot 1 Control Register(C0MSL1CNT) CAN0 Message Slot 5 Control Register(C0MSL5CNT) CAN0 Message Slot 7 Control Register(C0MSL7CNT) CAN0 Message Slot 9 Control Register(C0MSL9CNT) CAN0 Message Slot 11 Control Register(C0MSL11CNT) CAN0 Message Slot 13 Control Register(C0MSL13CNT) CAN0 Message Slot 15 Control Register(C0MSL15CNT) CAN0 Message Slot 6 Control Register(C0MSL6CNT) CAN0 Message Slot 8 Control Register(C0MSL8CNT) CAN0 Message Slot 10 Control Register(C0MSL10CNT) CAN0 Message Slot 12 Control Register(C0MSL12CNT) CAN0 Message Slot 14 Control Register(C0MSL14CNT) H'0080 1012 CAN0 Error Interrupt Status Register(CAN0ERIST)CAN0 Error Interrupt Mask Register(CAN0ERIMK)H'0080 1014 H'0080 1016 CAN0 Baud Rate Prescaler(CAN0BRP) H'0080 105E CAN0 Global Mask Register Standard ID1(C0GMSKS1) CAN0 Global Mask Register Extended ID0(C0GMSKE0) CAN0 Global Mask Register Extended ID1(C0GMSKE1) CAN0 Global Mask Register Extended ID2(C0GMSKE2) CAN0 Local Mask Register A Standard ID1(C0LMSKAS1) CAN0 Local Mask Register A Extended ID0(C0LMSKAE0) CAN0 Local Mask Register A Extended ID1(C0LMSKAE1) CAN0 Local Mask Register A Extended ID2(C0LMSKAE2) CAN0 Local Mask Register B Standard ID0(C0LMSKAS0) CAN0 Local Mask Register B Standard ID1(C0LMSKAS1) CAN0 Local Mask Register B Extended ID0(C0LMSKAE0) CAN0 Local Mask Register B Extended ID1(C0LMSKAE1) CAN0 Local Mask Register B Extended ID2(C0LMSKAE2) Blank areas are reserved for future use. CAN0 Slot Interrupt Mask Register(CAN0SLIMK)

13-6 Rev.1.0 +0 address +1 address D0 D7 D8 D15 Address H'0080 1102 H'0080 1104 H'0080 110C H'0080 110E H'0080 1112 H'0080 1114 H'0080 1116 H'0080 1110 H'0080 1108 H'0080 1106 H'0080 110A CAN0 Message Slot 0 Extended ID0(C0MSL0EID0) CAN0 Message Slot 0 Extended ID2(C0MSL0EID2) CAN0 Message Slot 0 Data 0(C0MSL0DT0) CAN0 Message Slot 0 Data 2(C0MSL0DT2) CAN0 Message Slot 0 Data 4(C0MSL0DT4) CAN0 Message Slot 0 Extended ID1(C0MSL0EID1) CAN0 Message Slot 0 Data Length Register(C0MSL0DLC) CAN0 Message Slot 0 Data 1(C0MSL0DT1) CAN0 Message Slot 0 Data 3(C0MSL0DT3) CAN0 Message Slot 0 Data 5(C0MSL0DT5) CAN0 Message Slot 0 Data 6(C0MSL0DT6) CAN0 Message Slot 0 Data 7(C0MSL0DT7) CAN0 Message Slot 0 Time stamp(C0MSL0TSP) H'0080 1118 H'0080 111A H'0080 111E H'0080 1120 H'0080 1122 H'0080 1126 H'0080 1128 H'0080 112E H'0080 112C H'0080 1124 H'0080 112A H'0080 111C H'0080 1130 H'0080 1132 H'0080 1136 H'0080 1138 H'0080 113E H'0080 113C H'0080 1134 H'0080 113A H'0080 1140 H'0080 1142 H'0080 1146 H'0080 1148 H'0080 114E H'0080 114C H'0080 1144 H'0080 114A H'0080 1150 H'0080 1152 H'0080 1100 CAN0 Message Slot 0 Standard ID1(C0MSL0SID1)CAN0 Message Slot 0 Standard ID0(C0MSL0SID0) CAN0 Message Slot 1 Extended ID0(C0MSL1EID0) CAN0 Message Slot 1 Extended ID2(C0MSL1EID2) CAN0 Message Slot 1 Data 0(C0MSL1DT0) CAN0 Message Slot 1 Data 2(C0MSL1DT2) CAN0 Message Slot 1 Data 4(C0MSL1DT4) CAN0 Message Slot 1 Extended ID1(C0MSL1EID1) CAN0 Message Slot 1 Data Length Register(C0MSL1DLC) CAN0 Message Slot 1 Data 1(C0MSL1DT1) CAN0 Message Slot 1 Data 3(C0MSL1DT3) CAN0 Message Slot 1 Data 5(C0MSL1DT5) CAN0 Message Slot 1 Data 6(C0MSL1DT6) CAN0 Message Slot 1 Data 7(C0MSL1DT7) CAN0 Message Slot 1 Time stamp(C0MSL1TSP) CAN0 Message Slot 1 Standard ID1(C0MSL1SID1)CAN0 Message Slot 1 Standard ID0(C0MSL1SID0) CAN0 Message Slot 2 Extended ID0(C0MSL2EID0) CAN0 Message Slot 2 Extended ID2(C0MSL2EID2) CAN0 Message Slot 2 Data 0(C0MSL2DT0) CAN0 Message Slot 2 Data 2(C0MSL2DT2) CAN0 Message Slot 2 Data 4(C0MSL2DT4) CAN0 Message Slot 2 Extended ID1(C0MSL2EID1) CAN0 Message Slot 2 Data Length Register(C0MSL2DLC) CAN0 Message Slot 2 Data 1(C0MSL2DT1) CAN0 Message Slot 2 Data 3(C0MSL2DT3) CAN0 Message Slot 2 Data 5(C0MSL2DT5) CAN0 Message Slot 2 Data 6(C0MSL2DT6) CAN0 Message Slot 2 Data 7(C0MSL2DT7) CAN0 Message Slot 2 Time stamp(C0MSL2TSP) CAN0 Message Slot 2 Standard ID1(C0MSL2SID1)CAN0 Message Slot 2 Standard ID0(C0MSL2SID0) CAN0 Message Slot 3 Extended ID0(C0MSL3EID0) CAN0 Message Slot 3 Extended ID2(C0MSL3EID2) CAN0 Message Slot 3 Data 0(C0MSL3DT0) CAN0 Message Slot 3 Data 2(C0MSL3DT2) CAN0 Message Slot 3 Data 4(C0MSL3DT4) CAN0 Message Slot 3 Extended ID1(C0MSL3EID1) CAN0 Message Slot 3 Data Length Register(C0MSL3DLC) CAN0 Message Slot 3 Data 1(C0MSL3DT1) CAN0 Message Slot 3 Data 3(C0MSL3DT3) CAN0 Message Slot 3 Data 5(C0MSL3DT5) CAN0 Message Slot 3 Data 6(C0MSL3DT6) CAN0 Message Slot 3 Data 7(C0MSL3DT7) CAN0 Message Slot 3 Time stamp(C0MSL3TSP) CAN0 Message Slot 3 Standard ID1(C0MSL3SID1)CAN0 Message Slot 3 Standard ID0(C0MSL3SID0) CAN0 Message Slot 4 Extended ID0(C0MSL4EID0) CAN0 Message Slot 4 Extended ID2(C0MSL4EID2) CAN0 Message Slot 4 Data 0(C0MSL4DT0) CAN0 Message Slot 4 Data 2(C0MSL4DT2) CAN0 Message Slot 4 Data 4(C0MSL4DT4) CAN0 Message Slot 4 Extended ID1(C0MSL4EID1) CAN0 Message Slot 4 Data Length Register(C0MSL4DLC) CAN0 Message Slot 4 Data 1(C0MSL4DT1) CAN0 Message Slot 4 Data 3(C0MSL4DT3) CAN0 Message Slot 4 Data 5(C0MSL4DT5) CAN0 Message Slot 4 Data 6(C0MSL4DT6) CAN0 Message Slot 4 Data 7(C0MSL4DT7) CAN0 Message Slot 4 Time stamp(C0MSL4TSP) CAN0 Message Slot 4 Standard ID1(C0MSL4SID1)CAN0 Message Slot 4 Standard ID0(C0MSL4SID0) CAN0 Message Slot 5 Extended ID0(C0MSL5EID0) CAN0 Message Slot 5 Extended ID1(C0MSL5EID1) CAN0 Message Slot 5 Standard ID1(C0MSL5SID1)CAN0 Message Slot 5 Standard ID0(C0MSL5SID0) Blank areas are reserved for future use. Figure 13.2.2 CAN Module Related Register Map (2/8) CAN MODULES

13-7 Rev.1.0 D0 D7 D8 D15 H'0080 1156 H'0080 1158 H'0080 115E H'0080 115C H'0080 1154 H'0080 115A H'0080 1160 H'0080 1162 H'0080 1166 H'0080 1168 H'0080 116E H'0080 116C H'0080 1164 H'0080 116A H'0080 1170 H'0080 1172 H'0080 1176 H'0080 1174 H'0080 117A H'0080 117C H'0080 117E H'0080 1182 H'0080 1184 H'0080 118A H'0080 1188 H'0080 1180 H'0080 1186 H'0080 1178 H'0080 118C H'0080 118E H'0080 1192 H'0080 1194 H'0080 119A H'0080 1198 H'0080 1190 H'0080 1196 H'0080 119C H'0080 119E H'0080 11A2 H'0080 11A4 H'0080 11A0 H'0080 11A6 +0 address +1 addressAddress CAN0 Message Slot 9 Extended ID0(C0MSL9EID0) CAN0 Message Slot 9 Extended ID2(C0MSL9EID2) CAN0 Message Slot 9 Data 0(C0MSL9DT0) CAN0 Message Slot 9 Data 2(C0MSL9DT2) CAN0 Message Slot 9 Data 4(C0MSL9DT4) CAN0 Message Slot 9 Extended ID1(C0MSL9EID1) CAN0 Message Slot 9 Data Length Register(C0MSL9DLC) CAN0 Message Slot 9 Data 1(C0MSL9DT1) CAN0 Message Slot 9 Data 3(C0MSL9DT3) CAN0 Message Slot 9 Data 5(C0MSL9DT5) CAN0 Message Slot 9 Data 6(C0MSL9DT6) CAN0 Message Slot 9 Data 7(C0MSL9DT7) CAN0 Message Slot 9 Time stamp(C0MSL9TSP) CAN0 Message Slot 9 Standard ID1(C0MSL9SID1)CAN0 Message Slot 9 Standard ID0(C0MSL9SID0) CAN0 Message Slot 10 Extended ID0(C0MSL10EID0) CAN0 Message Slot 10 Extended ID2(C0MSL10EID2) CAN0 Message Slot 10 Data 0(C0MSL10DT0) CAN0 Message Slot 10 Extended ID1(C0MSL10EID1) CAN0 Message Slot 10 Data Length Register(C0MSL10DLC) CAN0 Message Slot 10 Data 1(C0MSL10DT1) CAN0 Message Slot 10 Standard ID1(C0MSL10SID1)CAN0 Message Slot 10 Standard ID0(C0MSL10SID0) CAN0 Message Slot 8 Extended ID0(C0MSL8EID0) CAN0 Message Slot 8 Extended ID2(C0MSL8EID2) CAN0 Message Slot 8 Data 0(C0MSL8DT0) CAN0 Message Slot 8 Data 2(C0MSL8DT2) CAN0 Message Slot 8 Data 4(C0MSL8DT4) CAN0 Message Slot 8 Extended ID1(C0MSL8EID1) CAN0 Message Slot 8 Data Length Register(C0MSL8DLC) CAN0 Message Slot 8 Data 1(C0MSL8DT1) CAN0 Message Slot 7 Data 1(C0MSL7DT1) CAN0 Message Slot 8 Data 3(C0MSL8DT3) CAN0 Message Slot 8 Data 5(C0MSL8DT5) CAN0 Message Slot 8 Data 6(C0MSL8DT6) CAN0 Message Slot 8 Data 7(C0MSL8DT7) CAN0 Message Slot 8 Time stamp(C0MSL8TSP) CAN0 Message Slot 8 Standard ID1(C0MSL8SID1)CAN0 Message Slot 8 Standard ID0(C0MSL8SID0) CAN0 Message Slot 7 Extended ID0(C0MSL7EID0) CAN0 Message Slot 7 Extended ID2(C0MSL7EID2) CAN0 Message Slot 7 Data 0(C0MSL7DT0) CAN0 Message Slot 7 Data 2(C0MSL7DT2) CAN0 Message Slot 7 Data 4(C0MSL7DT4) CAN0 Message Slot 7 Extended ID1(C0MSL7EID1) CAN0 Message Slot 7 Data Length Register(C0MSL7DLC) CAN0 Message Slot 7 Data 3(C0MSL7DT3) CAN0 Message Slot 7 Data 5(C0MSL7DT5) CAN0 Message Slot 7 Data 6(C0MSL7DT6) CAN0 Message Slot 7 Data 7(C0MSL7DT7) CAN0 Message Slot 7 Time stamp(C0MSL7TSP) CAN0 Message Slot 7 Standard ID1(C0MSL7SID1)CAN0 Message Slot 7 Standard ID0(C0MSL7SID0) CAN0 Message Slot 6 Data 1(C0MSL6DT1) CAN0 Message Slot 6 Extended ID0(C0MSL6EID0) CAN0 Message Slot 6 Extended ID2(C0MSL6EID2) CAN0 Message Slot 6 Data 0(C0MSL6DT0) CAN0 Message Slot 6 Data 2(C0MSL6DT2) CAN0 Message Slot 6 Data 4(C0MSL6DT4) CAN0 Message Slot 6 Extended ID1(C0MSL6EID1) CAN0 Message Slot 6 Data Length Register(C0MSL6DLC) CAN0 Message Slot 6 Data 3(C0MSL6DT3) CAN0 Message Slot 6 Data 5(C0MSL6DT5) CAN0 Message Slot 6 Data 6(C0MSL6DT6) CAN0 Message Slot 6 Data 7(C0MSL6DT7) CAN0 Message Slot 6 Time stamp(C0MSL6TSP) CAN0 Message Slot 5 Data 1(C0MSL5DT1) CAN0 Message Slot 5 Extended ID2(C0MSL5EID2) CAN0 Message Slot 5 Data 0(C0MSL5DT0) CAN0 Message Slot 5 Data 2(C0MSL5DT2) CAN0 Message Slot 5 Data 4(C0MSL5DT4) CAN0 Message Slot 5 Data Length Register(C0MSL5DLC) CAN0 Message Slot 5 Data 3(C0MSL5DT3) CAN0 Message Slot 5 Data 5(C0MSL5DT5) CAN0 Message Slot 5 Data 6(C0MSL5DT6) CAN0 Message Slot 5 Data 7(C0MSL5DT7) CAN0 Message Slot 5 Time stamp(C0MSL5TSP) CAN0 Message Slot 6 Standard ID1(C0MSL6SID1)CAN0 Message Slot 6 Standard ID0(C0MSL6SID0) Blank areas are reserved for future use. Figure 13.2.3 CAN Module Related Register Map (3/8) CAN MODULES

13-8 Rev.1.0 D0 D7 D8 D15 H'0080 11AA H'0080 11A8 H'0080 11AC H'0080 11AE H'0080 11B2 H'0080 11BC H'0080 11BA H'0080 11B8 H'0080 11B0 H'0080 11B6 H'0080 11BE H'0080 11C2 H'0080 11C4 H'0080 11CA H'0080 11C8 H'0080 11C0 H'0080 11C6 H'0080 11CE H'0080 11D2 H'0080 11D0 H'0080 11D6 H'0080 11D8 H'0080 11DA H'0080 11DE H'0080 11E0 H'0080 11E6 H'0080 11E4 H'0080 11DC H'0080 11E2 H'0080 11D4 H'0080 11E8 H'0080 11EA H'0080 11EE H'0080 11F0 H'0080 11F6 H'0080 11F4 H'0080 11EC H'0080 11F2 H'0080 11F8 H'0080 11FA H'0080 11FE H'0080 11FC H'0080 11CC H'0080 11B4 +0 address +1 addressAddress CAN0 Message Slot 11 Extended ID0(C0MSL11EID0) CAN0 Message Slot 11 Extended ID2(C0MSL11EID2) CAN0 Message Slot 11 Data 0(C0MSL11DT0) CAN0 Message Slot 11 Data 2(C0MSL11DT2) CAN0 Message Slot 11 Data 4(C0MSL11DT4) CAN0 Message Slot 11 Extended ID1(C0MSL11EID1) CAN0 Message Slot 11 Data Length Register(C0MSL11DLC) CAN0 Message Slot 11 Data 1(C0MSL11DT1) CAN0 Message Slot 11 Data 3(C0MSL11DT3) CAN0 Message Slot 11 Data 5(C0MSL11DT5) CAN0 Message Slot 11 Data 6(C0MSL11DT6) CAN0 Message Slot 11 Data 7(C0MSL11DT7) CAN0 Message Slot 11 Time stamp(C0MSL11TSP) CAN0 Message Slot 10 Data 2(C0MSL10DT2) CAN0 Message Slot 10 Data 4(C0MSL10DT4) CAN0 Message Slot 10 Data 3(C0MSL10DT3) CAN0 Message Slot 10 Data 5(C0MSL10DT5) CAN0 Message Slot 10 Data 6(C0MSL10DT6) CAN0 Message Slot 10 Data 7(C0MSL10DT7) CAN0 Message Slot 10 Time stamp(C0MSL10TSP) CAN0 Message Slot 11 Standard ID1(C0MSL11SID1)CAN0 Message Slot 11 Standard ID0(C0MSL11SID0) CAN0 Message Slot 12 Extended ID0(C0MSL12EID0) CAN0 Message Slot 12 Extended ID2(C0MSL12EID2) CAN0 Message Slot 12 Data 0(C0MSL12DT0) CAN0 Message Slot 12 Data 2(C0MSL12DT2) CAN0 Message Slot 12 Data 4(C0MSL12DT4) CAN0 Message Slot 12 Extended ID1(C0MSL12EID1) CAN0 Message Slot 12 Data Length Register(C0MSL12DLC) CAN0 Message Slot 12 Data 1(C0MSL12DT1) CAN0 Message Slot 12 Data 3(C0MSL12DT3) CAN0 Message Slot 12 Data 5(C0MSL12DT5) CAN0 Message Slot 12 Data 6(C0MSL12DT6) CAN0 Message Slot 12 Data 7(C0MSL12DT7) CAN0 Message Slot 12 Time stamp(C0MSL12TSP) CAN0 Message Slot 12 Standard ID1(C0MSL12SID1)CAN0 Message Slot 12 Standard ID0(C0MSL12SID0) CAN0 Message Slot 13 Extended ID0(C0MSL13EID0) CAN0 Message Slot 13 Extended ID2(C0MSL13EID2) CAN0 Message Slot 13 Data 0(C0MSL13DT0) CAN0 Message Slot 13 Data 2(C0MSL13DT2) CAN0 Message Slot 13 Data 4(C0MSL13DT4) CAN0 Message Slot 13 Extended ID1(C0MSL13EID1) CAN0 Message Slot 13 Data Length Register(C0MSL13DLC) CAN0 Message Slot 13 Data 1(C0MSL13DT1) CAN0 Message Slot 13 Data 3(C0MSL13DT3) CAN0 Message Slot 13 Data 5(C0MSL13DT5) CAN0 Message Slot 13 Data 6(C0MSL13DT6) CAN0 Message Slot 13 Data 7(C0MSL13DT7) CAN0 Message Slot 13 Time stamp(C0MSL13TSP) CAN0 Message Slot 13 Standard ID1(C0MSL13SID1)CAN0 Message Slot 13 Standard ID0(C0MSL13SID0) CAN0 Message Slot 14 Extended ID0(C0MSL14EID0) CAN0 Message Slot 14 Extended ID2(C0MSL14EID2) CAN0 Message Slot 14 Data 0(C0MSL14DT0) CAN0 Message Slot 14 Data 2(C0MSL14DT2) CAN0 Message Slot 14 Data 4(C0MSL14DT4) CAN0 Message Slot 14 Extended ID1(C0MSL14EID1) CAN0 Message Slot 14 Data Length Register(C0MSL14DLC) CAN0 Message Slot 14 Data 1(C0MSL14DT1) CAN0 Message Slot 14 Data 3(C0MSL14DT3) CAN0 Message Slot 14 Data 5(C0MSL14DT5) CAN0 Message Slot 14 Data 6(C0MSL14DT6) CAN0 Message Slot 14 Data 7(C0MSL14DT7) CAN0 Message Slot 14 Time stamp(C0MSL14TSP) CAN0 Message Slot 14 Standard ID1(C0MSL14SID1)CAN0 Message Slot 14 Standard ID0(C0MSL14SID0) CAN0 Message Slot 15 Extended ID0(C0MSL15EID0) CAN0 Message Slot 15 Extended ID2(C0MSL15EID2) CAN0 Message Slot 15 Data 0(C0MSL15DT0) CAN0 Message Slot 15 Data 2(C0MSL15DT2) CAN0 Message Slot 15 Data 4(C0MSL15DT4) CAN0 Message Slot 15 Extended ID1(C0MSL15EID1) CAN0 Message Slot 15 Data Length Register(C0MSL15DLC) CAN0 Message Slot 15 Data 1(C0MSL15DT1) CAN0 Message Slot 15 Data 3(C0MSL15DT3) CAN0 Message Slot 15 Data 5(C0MSL15DT5) CAN0 Message Slot 15 Data 6(C0MSL15DT6) CAN0 Message Slot 15 Data 7(C0MSL15DT7) CAN0 Message Slot 15 Time stamp(C0MSL15TSP) CAN0 Message Slot 15 Standard ID1(C0MSL15SID1)CAN0 Message Slot 15 Standard ID0(C0MSL15SID0) Blank areas are reserved for future use. Figure 13.2.4 CAN Module Related Register Map (4/8) CAN MODULES

13-9 Rev.1.0 +0 address +1 address D0 D7 D8 D15 Address CAN1 Configuration Register(CAN1CONF) CAN1 Global Mask Register Standard ID0(C1GMSKS0) CAN1 Local Mask Register A Standard ID0(C1LMSKAS0) CAN1 Control Register(CAN1CNT) CAN1 Extended ID Register(CAN1EXTID) CAN1 Time stamp Count Register(CAN1TSTMP) CAN1 Slot Interrupt Status Register(CAN1SLIST) CAN1 Message Slot 3 Control Register(C1MSL3CNT)CAN1 Message Slot 2 Control Register(C1MSL2CNT) CAN1 Message Slot 4 Control Register(C1MSL4CNT) CAN1 Status Register(CAN1STAT) CAN1 Receive Error Count Register(CAN1REC) CAN1 Transmit Error Count Register(CAN1TEC) CAN1 Message Slot 0 Control Register(C1MSL0CNT) CAN1 Message Slot 1 Control Register(C1MSL1CNT) CAN1 Message Slot 5 Control Register(C1MSL5CNT) CAN1 Message Slot 7 Control Register(C1MSL7CNT) CAN1 Message Slot 9 Control Register(C1MSL9CNT) CAN1 Message Slot 11 Control Register(C1MSL11CNT) CAN1 Message Slot 13 Control Register(C1MSL13CNT) CAN1 Message Slot 15 Control Register(C1MSL15CNT) CAN1 Message Slot 6 Control Register(C1MSL6CNT) CAN1 Message Slot 8 Control Register(C1MSL8CNT) CAN1 Message Slot 10 Control Register(C1MSL10CNT) CAN1 Message Slot 12 Control Register(C1MSL12CNT) CAN1 Message Slot 14 Control Register(C1MSL14CNT) CAN1 Error Interrupt Status Register(CAN1ERIST)CAN1 Error Interrupt Mask Register(CAN1ERIMK) CAN1 Baud Rate Prescaler(CAN1BRP) CAN1 Global Mask Register Standard ID1(C1GMSKS1) CAN1 Global Mask Register Extended ID0(C1GMSKE0) CAN1 Global Mask Register Extended ID1(C1GMSKE1) CAN1 Global Mask Register Extended ID2(C1GMSKE2) CAN1 Local Mask Register A Standard ID1(C1LMSKAS1) CAN1 Local Mask Register A Extended ID0(C1LMSKAE0) CAN1 Local Mask Register A Extended ID1(C1LMSKAE1) CAN1 Local Mask Register A Extended ID2(C1LMSKAE2) CAN1 Local Mask Register B Standard ID0(C1LMSKAS0) CAN1 Local Mask Register B Standard ID1(C1LMSKAS1) CAN1 Local Mask Register B Extended ID0(C1LMSKAE0) CAN1 Local Mask Register B Extended ID1(C1LMSKAE1) CAN1 Local Mask Register B Extended ID2(C1LMSKAE2) Blank areas are reserved for future use. CAN1 Slot Interrupt Mask Register(CAN1SLIMK) H'0080 1434 H'0080 1432 H'0080 1438 H'0080 1436 H'0080 143C H'0080 143A H'0080 1454 H'0080 1458 H'0080 1456 H'0080 1452 H'0080 145A H'0080 1400 H'0080 1402 H'0080 1404 H'0080 1408 H'0080 140A H'0080 1410 H'0080 140E H'0080 1406 H'0080 1428 H'0080 142C H'0080 1430 H'0080 142E H'0080 142A H'0080 145C H'0080 140C H'0080 1450 H'0080 1412 H'0080 1414 H'0080 1416 H'0080 145EFigure 13.2.5 CAN Module Related Register Map (5/8) CAN MODULES

13-10 Rev.1.0 +0 address +1 address D0 D7 D8 D15 Address CAN1 Message Slot 0 Extended ID0(C1MSL0EID0) CAN1 Message Slot 0 Extended ID2(C1MSL0EID2) CAN1 Message Slot 0 Data 0(C1MSL0DT0) CAN1 Message Slot 0 Data 2(C1MSL0DT2) CAN1 Message Slot 0 Data 4(C1MSL0DT4) CAN1 Message Slot 0 Extended ID1(C1MSL0EID1) CAN1 Message Slot 0 Data Length Register(C1MSL0DLC) CAN1 Message Slot 0 Data 1(C1MSL0DT1) CAN1 Message Slot 0 Data 3(C1MSL0DT3) CAN1 Message Slot 0 Data 5(C1MSL0DT5) CAN1 Message Slot 0 Data 6(C1MSL0DT6) CAN1 Message Slot 0 Data 7(C1MSL0DT7) CAN1 Message Slot 0 Time stamp(C1MSL0TSP) CAN1 Message Slot 0 Standard ID1(C1MSL0SID1)CAN1 Message Slot 0 Standard ID0(C1MSL0SID0) CAN1 Message Slot 1 Extended ID0(C1MSL1EID0) CAN1 Message Slot 1 Extended ID2(C1MSL1EID2) CAN1 Message Slot 1 Data 0(C1MSL1DT0) CAN1 Message Slot 1 Data 2(C1MSL1DT2) CAN1 Message Slot 1 Data 4(C1MSL1DT4) CAN1 Message Slot 1 Extended ID1(C1MSL1EID1) CAN1 Message Slot 1 Data Length Register(C1MSL1DLC) CAN1 Message Slot 1 Data 1(C1MSL1DT1) CAN1 Message Slot 1 Data 3(C1MSL1DT3) CAN1 Message Slot 1 Data 5(C1MSL1DT5) CAN1 Message Slot 1 Data 6(C1MSL1DT6) CAN1 Message Slot 1 Data 7(C1MSL1DT7) CAN1 Message Slot 1 Time stamp(C1MSL1TSP) CAN1 Message Slot 1 Standard ID1(C1MSL1SID1)CAN1 Message Slot 1 Standard ID0(C1MSL1SID0) CAN1 Message Slot 2 Extended ID0(C1MSL2EID0) CAN1 Message Slot 2 Extended ID2(C1MSL2EID2) CAN1 Message Slot 2 Data 0(C1MSL2DT0) CAN1 Message Slot 2 Data 2(C1MSL2DT2) CAN1 Message Slot 2 Data 4(C1MSL2DT4) CAN1 Message Slot 2 Extended ID1(C1MSL2EID1) CAN1 Message Slot 2 Data Length Register(C1MSL2DLC) CAN1 Message Slot 2 Data 1(C1MSL2DT1) CAN1 Message Slot 2 Data 3(C1MSL2DT3) CAN1 Message Slot 2 Data 5(C1MSL2DT5) CAN1 Message Slot 2 Data 6(C1MSL2DT6) CAN1 Message Slot 2 Data 7(C1MSL2DT7) CAN1 Message Slot 2 Time stamp(C1MSL2TSP) CAN1 Message Slot 2 Standard ID1(C1MSL2SID1)CAN1 Message Slot 2 Standard ID0(C1MSL2SID0) CAN1 Message Slot 3 Extended ID0(C1MSL3EID0) CAN1 Message Slot 3 Extended ID2(C1MSL3EID2) CAN1 Message Slot 3 Data 0(C1MSL3DT0) CAN1 Message Slot 3 Data 2(C1MSL3DT2) CAN1 Message Slot 3 Data 4(C1MSL3DT4) CAN1 Message Slot 3 Extended ID1(C1MSL3EID1) CAN1 Message Slot 3 Data Length Register(C1MSL3DLC) CAN1 Message Slot 3 Data 1(C1MSL3DT1) CAN1 Message Slot 3 Data 3(C1MSL3DT3) CAN1 Message Slot 3 Data 5(C1MSL3DT5) CAN1 Message Slot 3 Data 6(C1MSL3DT6) CAN1 Message Slot 3 Data 7(C1MSL3DT7) CAN1 Message Slot 3 Time stamp(C1MSL3TSP) CAN1 Message Slot 3 Standard ID1(C1MSL3SID1)CAN1 Message Slot 3 Standard ID0(C1MSL3SID0) CAN1 Message Slot 4 Extended ID0(C1MSL4EID0) CAN1 Message Slot 4 Extended ID2(C1MSL4EID2) CAN1 Message Slot 4 Data 0(C1MSL4DT0) CAN1 Message Slot 4 Data 2(C1MSL4DT2) CAN1 Message Slot 4 Data 4(C1MSL4DT4) CAN1 Message Slot 4 Extended ID1(C1MSL4EID1) CAN0 Message Slot 4 Data Length Register(C1MSL4DLC) CAN1 Message Slot 4 Data 1(C1MSL4DT1) CAN1 Message Slot 4 Data 3(C1MSL4DT3) CAN1 Message Slot 4 Data 5(C1MSL4DT5) CAN1 Message Slot 4 Data 6(C1MSL4DT6) CAN1 Message Slot 4 Data 7(C1MSL4DT7) CAN1 Message Slot 4 Time stamp(C1MSL4TSP) CAN1 Message Slot 4 Standard ID1(C1MSL4SID1)CAN1 Message Slot 4 Standard ID0(C1MSL4SID0) CAN1 Message Slot 5 Extended ID0(C1MSL5EID0) CAN1 Message Slot 5 Extended ID1(C1MSL5EID1) CAN1 Message Slot 5 Standard ID1(C1MSL5SID1)CAN1 Message Slot 5 Standard ID0(C1MSL5SID0) Blank areas are reserved for future use. H'0080 1502 H'0080 1504 H'0080 150C H'0080 150E H'0080 1512 H'0080 1514 H'0080 1516 H'0080 1510 H'0080 1508 H'0080 1506 H'0080 150A H'0080 1518 H'0080 151A H'0080 151E H'0080 1520 H'0080 1522 H'0080 1526 H'0080 1528 H'0080 152E H'0080 152C H'0080 1524 H'0080 152A H'0080 151C H'0080 1530 H'0080 1532 H'0080 1536 H'0080 1538 H'0080 153E H'0080 153C H'0080 1534 H'0080 153A H'0080 1540 H'0080 1542 H'0080 1546 H'0080 1548 H'0080 154E H'0080 154C H'0080 1544 H'0080 154A H'0080 1550 H'0080 1552 H'0080 1500 Figure 13.2.6 CAN Module Related Register Map (6/8) CAN MODULES

13-11 Rev.1.0 D0 D7 D8 D15 +0 address +1 addressAddress CAN1 Message Slot 9 Extended ID0(C1MSL9EID0) CAN1 Message Slot 9 Extended ID2(C1MSL9EID2) CAN1 Message Slot 9 Data 0(C1MSL9DT0) CAN1 Message Slot 9 Data 2(C1MSL9DT2) CAN1 Message Slot 9 Data 4(C1MSL9DT4) CAN1 Message Slot 9 Extended ID1(C1MSL9EID1) CAN1 Message Slot 9 Data Length Register(C1MSL9DLC) CAN1 Message Slot 9 Data 1(C1MSL9DT1) CAN1 Message Slot 9 Data 3(C1MSL9DT3) CAN1 Message Slot 9 Data 5(C1MSL9DT5) CAN1 Message Slot 9 Data 6(C1MSL9DT6) CAN1 Message Slot 9 Data 7(C1MSL9DT7) CAN1 Message Slot 9 Time stamp(C1MSL9TSP) CAN1 Message Slot 9 Standard ID1(C1MSL9SID1)CAN1 Message Slot 9 Standard ID0(C1MSL9SID0) CAN1 Message Slot 10 Extended ID0(C1MSL10EID0) CAN1 Message Slot 10 Extended ID2(C1MSL10EID2) CAN1 Message Slot 10 Data 0(C1MSL10DT0) CAN1 Message Slot 10 Extended ID1(C1MSL10EID1) CAN1 Message Slot 10 Data Length Register(C1MSL10DLC) CAN1 Message Slot 10 Data 1(C1MSL10DT1) CAN1 Message Slot 10 Standard ID1(C1MSL10SID1)CAN1 Message Slot 10 Standard ID0(C1MSL10SID0) CAN1 Message Slot 8 Extended ID0(C1MSL8EID0) CAN1 Message Slot 8 Extended ID2(C1MSL8EID2) CAN1 Message Slot 8 Data 0(C1MSL8DT0) CAN1 Message Slot 8 Data 2(C1MSL8DT2) CAN1 Message Slot 8 Data 4(C1MSL8DT4) CAN1 Message Slot 8 Extended ID1(C1MSL8EID1) CAN1 Message Slot 8 Data Length Register(C1MSL8DLC) CAN1 Message Slot 8 Data 1(C1MSL8DT1) CAN1 Message Slot 7 Data 1(C1MSL7DT1) CAN1 Message Slot 8 Data 3(C1MSL8DT3) CAN1 Message Slot 8 Data 5(C1MSL8DT5) CAN1 Message Slot 8 Data 6(C1MSL8DT6) CAN1 Message Slot 8 Data 7(C1MSL8DT7) CAN1 Message Slot 8 Time stamp(C1MSL8TSP) CAN1 Message Slot 8 Standard ID1(C1MSL8SID1)CAN1 Message Slot 8 Standard ID0(C1MSL8SID0) CAN1 Message Slot 7 Extended ID0(C1MSL7EID0) CAN1 Message Slot 7 Extended ID2(C1MSL7EID2) CAN1 Message Slot 7 Data 0(C1MSL7DT0) CAN1 Message Slot 7 Data 2(C1MSL7DT2) CAN1 Message Slot 7 Data 4(C1MSL7DT4) CAN1 Message Slot 7 Extended ID1(C1MSL7EID1) CAN1 Message Slot 7 Data Length Register(C1MSL7DLC) CAN1 Message Slot 7 Data 3(C1MSL7DT3) CAN1 Message Slot 7 Data 5(C1MSL7DT5) CAN1 Message Slot 7 Data 6(C1MSL7DT6) CAN1 Message Slot 7 Data 7(C1MSL7DT7) CAN1 Message Slot 7 Time stamp(C1MSL7TSP) CAN1 Message Slot 7 Standard ID1(C1MSL7SID1)CAN1 Message Slot 7 Standard ID0(C1MSL7SID0) CAN1 Message Slot 6 Data 1(C1MSL6DT1) CAN1 Message Slot 6 Extended ID0(C1MSL6EID0) CAN1 Message Slot 6 Extended ID2(C1MSL6EID2) CAN1 Message Slot 6 Data 0(C1MSL6DT0) CAN1 Message Slot 6 Data 2(C1MSL6DT2) CAN1 Message Slot 6 Data 4(C1MSL6DT4) CAN1 Message Slot 6 Extended ID1(C1MSL6EID1) CAN1 Message Slot 6 Data Length Register(C1MSL6DLC) CAN1 Message Slot 6 Data 3(C1MSL6DT3) CAN1 Message Slot 6 Data 5(C1MSL6DT5) CAN1 Message Slot 6 Data 6(C1MSL6DT6) CAN1 Message Slot 6 Data 7(C1MSL6DT7) CAN1 Message Slot 6 Time stamp(C1MSL6TSP) CAN1 Message Slot 5 Data 1(C1MSL5DT1) CAN1 Message Slot 5 Extended ID2(C1MSL5EID2) CAN1 Message Slot 5 Data 0(C1MSL5DT0) CAN1 Message Slot 5 Data 2(C1MSL5DT2) CAN1 Message Slot 5 Data 4(C1MSL5DT4) CAN1 Message Slot 5 Data Length Register(C1MSL5DLC) CAN1 Message Slot 5 Data 3(C1MSL5DT3) CAN1 Message Slot 5 Data 5(C1MSL5DT5) CAN1 Message Slot 5 Data 6(C1MSL5DT6) CAN1 Message Slot 5 Data 7(C1MSL5DT7) CAN1 Message Slot 5 Time stamp(C1MSL5TSP) CAN1 Message Slot 6 Standard ID1(C1MSL6SID1)CAN1 Message Slot 6 Standard ID0(C1MSL6SID0) Blank areas are reserved for future use. H'0080 1556 H'0080 1558 H'0080 155E H'0080 155C H'0080 1554 H'0080 155A H'0080 1560 H'0080 1562 H'0080 1566 H'0080 1568 H'0080 156E H'0080 156C H'0080 1564 H'0080 156A H'0080 1570 H'0080 1572 H'0080 1576 H'0080 1574 H'0080 157A H'0080 157C H'0080 157E H'0080 1582 H'0080 1584 H'0080 158A H'0080 1588 H'0080 1580 H'0080 1586 H'0080 1578 H'0080 158C H'0080 158E H'0080 1592 H'0080 1594 H'0080 159A H'0080 1598 H'0080 1590 H'0080 1596 H'0080 159C H'0080 159E H'0080 15A2 H'0080 15A4 H'0080 15A0 H'0080 15A6 Figure 13.2.7 CAN Module Related Register Map (7/8) CAN MODULES

13-12 Rev.1.0 D0 D7 D8 D15 +0 address +1 addressAddress CAN1 Message Slot 11 Extended ID0(C1MSL11EID0) CAN1 Message Slot 11 Extended ID2(C1MSL11EID2) CAN1 Message Slot 11 Data 0(C1MSL11DT0) CAN1 Message Slot 11 Data 2(C1MSL11DT2) CAN1 Message Slot 11 Data 4(C1MSL11DT4) CAN1 Message Slot 11 Extended ID1(C1MSL11EID1) CAN1 Message Slot 11 Data Length Register(C1MSL11DLC) CAN1 Message Slot 11 Data 1(C1MSL11DT1) CAN1 Message Slot 11 Data 3(C1MSL11DT3) CAN1 Message Slot 11 Data 5(C1MSL11DT5) CAN1 Message Slot 11 Data 6(C1MSL11DT6) CAN1 Message Slot 11 Data 7(C1MSL11DT7) CAN1 Message Slot 11 Time stamp(C1MSL11TSP) CAN1 Message Slot 10 Data 2(C1MSL10DT2) CAN1 Message Slot 10 Data 4(C1MSL10DT4) CAN1 Message Slot 10 Data 3(C1MSL10DT3) CAN1 Message Slot 10 Data 5(C1MSL10DT5) CAN1 Message Slot 10 Data 6(C1MSL10DT6) CAN1 Message Slot 10 Data 7(C1MSL10DT7) CAN1 Message Slot 10 Time stamp(C1MSL9TSP) CAN1 Message Slot 11 Standard ID1(C1MSL11SID1)CAN1 Message Slot 11 Standard ID0(C1MSL11SID0) CAN1 Message Slot 12 Extended ID0(C1MSL12EID0) CAN1 Message Slot 12 Extended ID2(C1MSL12EID2) CAN1 Message Slot 12 Data 0(C1MSL12DT0) CAN1 Message Slot 12 Data 2(C1MSL12DT2) CAN1 Message Slot 12 Data 4(C1MSL12DT4) CAN1 Message Slot 12 Extended ID1(C1MSL12EID1) CAN1 Message Slot 12 Data Length Register(C1MSL12DLC) CAN1 Message Slot 12 Data 1(C1MSL12DT1) CAN1 Message Slot 12 Data 3(C1MSL12DT3) CAN1 Message Slot 12 Data 5(C1MSL12DT5) CAN1 Message Slot 12 Data 6(C1MSL12DT6) CAN1 Message Slot 12 Data 7(C1MSL12DT7) CAN1 Message Slot 12 Time stamp(C1MSL12TSP) CAN1 Message Slot 12 Standard ID1(C1MSL12SID1)CAN1 Message Slot 12 Standard ID0(C1MSL12SID0) CAN1 Message Slot 13 Extended ID0(C1MSL13EID0) CAN1 Message Slot 13 Extended ID2(C1MSL13EID2) CAN1 Message Slot 13 Data 0(C1MSL13DT0) CAN1 Message Slot 13 Data 2(C1MSL13DT2) CAN1 Message Slot 13 Data 4(C1MSL13DT4) CAN1 Message Slot 13 Extended ID1(C1MSL13EID1) CAN1 Message Slot 13 Data Length Register(C1MSL13DLC) CAN1 Message Slot 13 Data 1(C1MSL13DT1) CAN1 Message Slot 13 Data 3(C1MSL13DT3) CAN1 Message Slot 13 Data 5(C1MSL13DT5) CAN1 Message Slot 13 Data 6(C1MSL13DT6) CAN1 Message Slot 13 Data 7(C1MSL13DT7) CAN1 Message Slot 13 Time stamp(C1MSL13TSP) CAN1 Message Slot 13 Standard ID1(C1MSL13SID1)CAN1 Message Slot 13 Standard ID0(C1MSL13SID0) CAN1 Message Slot 14 Extended ID0(C1MSL14EID0) CAN1 Message Slot 14 Extended ID2(C1MSL14EID2) CAN1 Message Slot 14 Data 0(C1MSL14DT0) CAN1 Message Slot 14 Data 2(C1MSL14DT2) CAN1 Message Slot 14 Data 4(C1MSL14DT4) CAN1 Message Slot 14 Extended ID1(C1MSL14EID1) CAN1 Message Slot 14 Data Length Register(C1MSL14DLC) CAN1 Message Slot 14 Data 1(C1MSL14DT1) CAN1 Message Slot 14 Data 3(C1MSL14DT3) CAN1 Message Slot 14 Data 5(C1MSL14DT5) CAN1 Message Slot 14 Data 6(C1MSL14DT6) CAN1 Message Slot 14 Data 7(C1MSL14DT7) CAN1 Message Slot 14 Time stamp(C1MSL14TSP) CAN1 Message Slot 14 Standard ID1(C1MSL14SID1)CAN1 Message Slot 14 Standard ID0(C1MSL14SID0) CAN1 Message Slot 15 Extended ID0(C1MSL15EID0) CAN1 Message Slot 15 Extended ID2(C1MSL15EID2) CAN1 Message Slot 15 Data 0(C1MSL15DT0) CAN1 Message Slot 15 Data 2(C1MSL15DT2) CAN1 Message Slot 15 Data 4(C1MSL15DT4) CAN1 Message Slot 15 Extended ID1(C1MSL15EID1) CAN1 Message Slot 15 Data Length Register(C1MSL15DLC) CAN1 Message Slot 15 Data 1(C1MSL15DT1) CAN1 Message Slot 15 Data 3(C1MSL15DT3) CAN1 Message Slot 15 Data 5(C1MSL15DT5) CAN1 Message Slot 15 Data 6(C1MSL15DT6) CAN1 Message Slot 15 Data 7(C1MSL15DT7) CAN1 Message Slot 15 Time stamp(C1MSL15TSP) CAN1 Message Slot 15 Standard ID1(C1MSL15SID1)CAN1 Message Slot 15 Standard ID0(C1MSL15SID0) Blank areas are reserved for future use. H'0080 15AA H'0080 15A8 H'0080 15AC H'0080 15AE H'0080 15B2 H'0080 15BC H'0080 15BA H'0080 15B8 H'0080 15B0 H'0080 15B6 H'0080 15BE H'0080 15C2 H'0080 15C4 H'0080 15CA H'0080 15C8 H'0080 15C0 H'0080 15C6 H'0080 15CE H'0080 15D2 H'0080 15D0 H'0080 15D6 H'0080 15D8 H'0080 15DA H'0080 15DE H'0080 15E0 H'0080 15E6 H'0080 15E4 H'0080 15DC H'0080 15E2 H'0080 15D4 H'0080 15E8 H'0080 15EA H'0080 15EE H'0080 15F0 H'0080 15F6 H'0080 15F4 H'0080 15EC H'0080 15F2 H'0080 15F8 H'0080 15FA H'0080 15FE H'0080 3FFE H'0080 15FC H'0080 15CC H'0080 15B4 Figure 13.2.8 CAN Module Related Register Map (8/8) CAN MODULES

13-13 Rev.1.0

13.2.1 CAN Control Registers

I CAN0 Control Register (CAN0CNT) <Address: H'0080 1000> I CAN1 Control Register (CAN1CNT) <Address: H'0080 1400> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 RBO TSR TSP FRST BCM LBM RST <When reset: H'0011> D Bit Name Function R W 0-3 No functions assigned 0 –

4 RBO 0 : Enables normal operation

(Return bus off) 1: Requests clearing of error counter

5 TSR 0: Enables count operation

(Time stamp counter reset)1: Initializes count (by setting H'0000) 6-7 TSP D6 D7 (Time stamp prescaler) 0 0: Selects CAN bus bit clock 0 1: Selects divide-by-2 of CAN bus bit clock 1 0: Selects divide-by-3 of CAN bus bit clock 1 1: Selects divide-by-4 of CAN bus bit clock 8-9 No functions assigned 0 – 10 No functions assigned (Always set this bit to 0.) 0 –

11 FRST 0: Negates reset

(Forcible reset) 1: Forcibly reset

12 BCM 0: Disables BasicCAN function

(BasicCAN mode) 1: Enables BasicCAN mode

13 No functions assigned 0 –

14 LBM 0: Disables loopback function

(Loopback mode) 1: Enables loopback function

15 RST 0: Negates reset

(CAN reset) 1: Requests reset W= : Only writing 1 is effective. Automatically cleared to 0 in hardware. CAN MODULES

13-14 Rev.1.0 (1) RBO (Return bus off) bit (D4) The receive error counter (CANREC)/transmit error counter (CANTEC) can be cleared by setting this bit to 1, thereby placing the CAN module forcibly in an error active state. This bit is automatically cleared when an error active state is entered. Note: After the error counters are cleared, the CAN module becomes ready to communicate when 11 consecutive recessive bits are detected on the CAN bus. (2) TSR (Time stamp counter reset) bit (D5) Setting this bit to 1 clears the value of the CAN Time stamp Count Register (CANTSTMP) to H'0000. This bit is automatically cleared after the CAN Time stamp Count Register (CANTSTMP) has its value cleared to H'0000. (3) TSP (Time stamp prescaler) bits (D6, D7) These bits select the count clock source for the time stamp counter. Note: Do not alter the value set with these TSP bits while the CAN module is operating (CAN Status Register CRS bit = 0). (4) FRST (Forcible reset) bit (D11) Setting this bit to 1 disconnects the CAN module from the CAN bus regardless of whether the CAN module is communicating or not, with its protocol control unit reset. Note 1: For CAN communication to be performed, the FRST and RST bits must be cleared to 0. Note 2: If the FRST bit is set to 1 during communication, outputs at the CTX0 and CTX1 pins become held high from that time on. Therefore, setting this bit to 1 while the CAN module is sending a frame may cause a CAN bus error. Note 3: The CAN Message Slot Control Register's transmit/receive request is not cleared by setting the FRST or RST bit. CAN MODULES

13-15 Rev.1.0 (5) BCM (BasicCAN mode) bit (D12) The CAN module can be run in BasicCA N mode by setting this bit to 1.

• Operation during BasicCAN mode In BasicCAN mode, two local slots-slots 14 and 15 -are used as double buffers, and receive frames that are found matching to the ID by acceptance filtering are stored alternately in slots 14 and 15. Used for this acceptance filtering when slot 14 is active (next receive frame to be stored in slot 14) are the ID set for slot 14 and local mask A, and those used when slot 15 is active are the ID set for slot 15 and local mask B. Two types of frames-data frame and remote frame-can be received in this mode. By using the same ID and setting the same value in mask registers for the two slots, the possibility of a message-lost trouble when, for example, receiving frames which have many IDs can be reduced.
• Procedure for entering BasicCAN mode Make the following settings during initialization. (a) Set the IDs of slots 14 and 15 and Local Mask Registers A and B. (We recommend setting the same value) (b) Set the type of frame to be handled with slots 14 and 15 (standard or extended) in the CAN Extended ID Register. (We recommend setting the same type) (c) Set the Message Slot Control Registers for slots 14 and 15 to receive data frames. (d) Set the BCM bit to 1. Note 1: Do not alter the value set with the BCM bit while the CAN module is operating (CAN Status Register CRS bit = 0). Note 2: Slot 14 is the first slot to become active after clearing the RST bit. Note 3: Even during BasicCAN mode, slot 0 through slot 13 can be used in the same way as when operating normally. (6) LBM (Loopback mode) bit (D14) When the LBM bit is set, if any receive slot exists whose ID matches that of a frame the CAN module itself transmitted, then the frame can be received. Note 1: ACK is not returned for frames the CAN module itself transmitted. Note 2: Do not alter the value set with the LBM bit while the CAN module is operating (CAN Status Register CRS bit = 0). CAN MODULES

13-16 Rev.1.0 (7) RST (CAN reset) bit (D15) When the RST bit is cleared to 0, the CAN module is connected to the CAN bus and becomes possible to communicate after detecting 11 consecutive recessive bits. Also, the CAN Time stamp Count Register thereby starts counting. When this bit is set to 1, the protocol control unit is reset and disconnected from the CAN bus after sending frames from slots which have had transmit requests set. All frames received during this time are processed normally. Note 1: No new transmit requests can be set from when the CAN Status Register CRS bit is set to 1 after setting the RST bit to 1 till when the protocol control unit is reset. Note 2: When the protocol control unit is reset by setting the RST bit to 1, the CAN Time stamp Count Register and CAN Transmit/Receive Error Count Register are initialized to 0. Note 3: For CAN communication to be performed, the FRST and RST bits must be cleared to 0. CAN MODULES

13-17 Rev.1.0

13.2.2 CAN Status Registers

I CAN0 Status Register (CAN0STAT) <Address: H'0080 1002> I CAN1 Status Register (CAN1STAT) <Address: H'0080 1402> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 BOS EPS CBS BCS 0 LBS CRS RSB TSB RSC TSC MSN <When reset: H'0100> D Bit Name Function R W

1 BOS 0: Not bus off –

(Bus-off status) 1: Bus-off state

2 EPS 0: Not error passive –

(Error passive status) 1: Error passive state

3 CBS 0: No error occurred –

(CAN bus error) 1: Error occurred

4 BCS 0: Normal mode –

(BasicCAN status) 1: BasicCAN mode

5 No functions assigned 0 –

6 LBS 0: Normal mode –

(Loopback status) 1: Loopback mode

7 CRS 0: Operating –

(CAN reset status) 1: Reset state

8 RSB 0: Nor receiving –

(Receive status) 1: Receiving

9 TSB 0: Not transmitting –

(Transmit status) 1: Transmitting

10 RSC 0: Reception not completed –

(Receive complete status) 1: Reception completed

11 TSC 0: Transmission not completed –

(Transmit complete status) 1: Transmission completed CAN MODULES

13-18 Rev.1.0 D Bit Name Function R W 12-15 MSN Message slot number which has had (Message slot number) transmission/reception completed – 0000: Slot 0 0001: Slot 1 0010: Slot 2 0011: Slot 3 0100: Slot 4 0101: Slot 5 0110: Slot 6 0111: Slot 7 1000: Slot 8 1001: Slot 9 1010: Slot 10 1011: Slot 11 1100: Slot 12 1101: Slot 13 1110: Slot 14 1111: Slot 15 (1) BOS (Bus-off status) bit (D1) When the BOS bit = 1, it means that the CAN module is in a bus-off state. [Set condition] This bit is set to 1 when the value of the Transmit Error Count Register exceeds 255, with the CAN module in a bus-off state. [Clear condition] This bit is cleared when the CAN module returns from the bus-off state. (2) EPS (Error passive status) bit (D2) When the EPS bit = 1, it means that the CAN module is in a error-passive state. [Set condition] This bit is set to 1 when the value of the Transmit or Receive Error Count Register exceeds 127, with the CAN module in an error-passive state. [Clear condition] This bit is cleared when the CAN module returns from the error-passive state. CAN MODULES

13-19 Rev.1.0 (3) CBS (CAN bus error) bit (D3) [Set condition] This bit is set to 1 when an error on the CAN bus is detected. [Clear condition] This bit is cleared when the CAN module finished transmitting or receiving normally. (4) BCS (BasicCAN status) bit (D4) When the BCS bit = 1, it means that the CAN module is operating in BasicCAN mode. [Set condition] This bit is set to 1 when the CAN module is operating in BasicCAN mode. Requirements for operation in BasicCAN mode

• The CAN Control Register BCM bit must be set to 1.
• Slots 14 and 15 must both be set for data frame reception. [Clear condition] This bit is cleared by clearing the BCM bit to 0. (5) LBS (Loopback status) bit (D6) When the LBS bit = 1, it means that the CAN module is operating in loopback mode. [Set condition] This bit is set to 1 by setting the CAN Control Register LBM (loopback mode) bit to 1. [Clear condition] This bit is cleared by clearing the LBM bit to 0. (6) CRS (CAN reset status) bit (D7) When the CRS bit = 1, it means that the CAN module's protocol control unit is in a reset state. [Set condition] This bit is set to 1 when CAN module's protocol control unit is in a reset state. [Clear condition] This bit is cleared by clearing the CAN Control Register RST (CAN reset) bit to 0. CAN MODULES

13-20 Rev.1.0 (7) RSB (Receive status) bit (D8) [Set condition] This bit is set to 1 when the CAN module is operating as a receive node. [Clear condition] This bit is cleared when the CAN module starts operating as a transmit node or goes to a bus-idle state. (8) TSB (Transmit status) bit (D9) [Set condition] This bit is set to 1 when the CAN module is operating as a transmit node. [Clear condition] This bit is cleared when the CAN module starts operating as a receive node or goes to a bus-idle state. (9) RSC (Receive complete status) bit (D10) [Set condition] This bit is set to 1 when the CAN module finished receiving data normally (regardless of whether there is any receive slot that satisfies receive conditions). [Clear condition] This bit is cleared when the CAN module finished transmitting data normally. (10) TSC (Transmit complete status) bit (D11) [Set condition] This bit is set to 1 when the CAN module finished transmitting data normally. [Clear condition] This bit is cleared when the CAN module finished receiving data normally. (11) MSN (Message slot number) bits (D12-D15) When the CAN module finished transmitting data or finished storing the received data in a slot, these bits show the relevant slot number. The MSN bits cannot be cleared to 0 in software. CAN MODULES

13-21 Rev.1.0

13.2.3 CAN Extended ID Registers

I CAN0 Extended ID Register (CAN0EXTID) <Address: H'0080 1004> I CAN1 Extended ID Register (CAN1EXTID) <Address: H'0080 1404> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 IDE0 IDE1 IDE2 IDE3 IDE4 IDE5 IDE6 IDE7 IDE8 IDE9 IDE10 IDE11 IDE12 IDE13 IDE14 IDE15 <When reset: H'0000> D Bit Name Function R W

0 IDE0 (Extended ID 0) 0: Standard ID format

1 IDE1 (Extended ID 1) 1: Extended ID format

2 IDE2 (Extended ID 2)

3 IDE3 (Extended ID 3)

4 IDE4 (Extended ID 4)

5 IDE5 (Extended ID 5)

6 IDE6 (Extended ID 6)

7 IDE7 (Extended ID 7)

8 IDE8 (Extended ID 8)

9 IDE9 (Extended ID 9)

10 IDE10 (Extended ID 10)

11 IDE11 (Extended ID 11)

12 IDE12 (Extended ID 12)

13 IDE13 (Extended ID 13)

14 IDE14 (Extended ID 14)

15 IDE15 (Extended ID 15)

Each bit in this register selects the type of frame handled by the corresponding message slot. Setting this bit to 0 selects the Standard ID format. Setting this bit to 1 selects the Extended ID format. Note: Settings of each bit of this register can only be changed when the corresponding slot dose not have transmit or receive requests set. CAN MODULES

13-22 Rev.1.0

13.2.4 CAN Configuration Registers

I CAN0 Configuration Register (CAN0CONF) <Address: H'0080 1006> I CAN1 Configuration Register (CAN1CONF) <Address: H'0080 1406> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 SJW PH2 PH1 PRB SAM <When reset: H'0000> D Bit Name Function R W 0-1 SJW Sets reSynchronization Jump Width (reSynchronization Jump Width) 00 : SJW = 1Tq 01 : SJW = 2Tq 10 : SJW = 3Tq 11 : SJW = 4Tq 2-4 PH2 Sets Phase Segment2 (Phase Segment2) 000 : Settings inhibited 001 : Phase Segment2 = 2Tq 010 : Phase Segment2 = 3Tq 011 : Phase Segment2 = 4Tq 100 : Phase Segment2 = 5Tq 101 : Phase Segment2 = 6Tq 110 : Phase Segment2 = 7Tq 111 : Phase Segment2 = 8Tq Note 1: Do not modify the CAN Configuration Register (CAN0CONF or CAN1CONF) while the CAN module is operating (CAN Status Register CRS bit = 0). Note 2: The bit configuration in this register must be set to meet the conditions below.

• Number of Tq's in one bit: 8 to 25 Tq's
• SJW min(Phase Segment1,Phase Segment2)
• Phase Segment2=max(Phase Segment1,IPT) However, IPT = 2 for the M32R/E's internal CAN modules. Note that min ( ) is the function that returns a smaller value, whereas max ( ) is the function that returns the maximum value. CAN MODULES

13-23 Rev.1.0 <When reset: H'0000> D Bit Name Function R W 5-7 PH1 Sets Phase Segment1 (Phase Segment1) 000 : Phase Segment1 = 1Tq 001 : Phase Segment1 = 2Tq 010 : Phase Segment1 = 3Tq 011 : Phase Segment1 = 4Tq 100 : Phase Segment1 = 5Tq 101 : Phase Segment1 = 6Tq 110 : Phase Segment1 = 7Tq 111 : Phase Segment1 = 8Tq 8-10 PRB Sets Propagation Segment (Propagation Segment) 000 : Propagation Segment = 1Tq 001 : Propagation Segment = 2Tq 010 : Propagation Segment = 3Tq 011 : Propagation Segment = 4Tq 100 : Propagation Segment = 5Tq 101 : Propagation Segment = 6Tq 110 : Propagation Segment = 7Tq 111 : Propagation Segment = 8Tq

11 SAM 0: Samples once

(Sampling times) 1: Samples three times 12-15 No functions assigned 0 – (1) SJW bits (D0-D1) These bits set the width of "reSynchronization Jump Width." (2) PH2 bits (D2-D4) These bits set the width of "Phase Segment2." Note : For the M32R/E's internal CAN modules, IPT (Information Processing Time) = 2. Because the PH2 bits = 0 after reset, set the width to 2 Tq's or more before using the CAN module. (3) PH1 bits (D5-D7) These bits set the width of "Phase Segment1." (4) PRB bits (D8-D10) These bits set the width of "Propagation Segment." CAN MODULES

13-24 Rev.1.0 (5) SAM bit (D11) This bit sets the number of times each bit is sampled. When SAM = 0, the value sampled at the end of Phase Segment1 is assumed to be the value of the bit. When SAM = 1, the value of the bit is determined by a majority circuit from values sampled at three points-one sampled at the end of Phase Segment1, one sampled before 1Tq, and one sampled before 2 Tq. Baud rate BRP set valueTq period (ns)Number of Tq's in one bitPROP+PH1 PH2 Sampling points 1M bps 3 100 10 7 2 80% 3 100 10 6 3 70% 3 100 10 5 4 60% 4 125 8 5 2 75% 4 125 8 4 3 63% 500K bps 4 125 16 13 2 88% 4 125 16 12 3 81% 4 125 16 11 4 75% 7 200 10 7 2 80% 7 200 10 6 3 70% 7 200 10 5 4 60% 9 250 8 5 2 75% 9 250 8 4 3 63% Table 13.2.1 Example of Bit Timing Settings when CPU Clock = 40 MHz CAN MODULES

13-25 Rev.1.0 D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 CANTSTMP <When reset: H'0000> D Bit Name Function R W 0-15 CANiTSTMP 16-bit counter value – The CAN modules each contain a 16-bit counter. The count period is selected from divide-by-1, 2, 3, or 4 of the CAN bus bit period using the CAN Control Register (CANCNT)'s TSP (timestamp prescaler) bits. The count register value is captured at completion of transmission/reception and the captured value is stored in a message slot. The counter is made to start counting by clearing the CAN Control Register (CANCNT)'s RST bit to 0. Note 1: The protocol control unit is reset and the counter is initialized to H'0000, by setting the CAN Control Register (CAN0CNT)'s RST (CAN reset) bit to 1. Also, the count register can be initialized to H'0000 while the CAN module is operating by setting the TSR (time stamp counter reset) bit to 1. Note 2: During loopback mode, if any ID-matching slot exists, the CAN module stores the time stamp value in the corresponding slot when it finished receiving. (No time stamp value is stored this way when the CAN module finished transmitting.) CAN MODULES

13.2.5 CAN Time stamp Count Registers

I CAN0 Time stamp Count Register (CAN0TSTMP) <Address: H'0080 1008> I CAN1 Time stamp Count Register (CAN1TSTMP) <Address: H'0080 1408>

13-26 Rev.1.0

13.2.6 CAN Error Count Registers

I CAN0 Receive Error Count Register (CAN0REC) <Address: H'0080 100A> I CAN1 Receive Error Count Register (CAN1REC) <Address: H'0080 140A> D 0 123456 D 7 REC <When reset: H'00> D Bit Name Function R W 0-7 REC Receive error count value – (Receive error counter) When in an error-active/error-passive state, the receive error count value is stored in this register. The counter counts down during normal reception and counts up when an error occurs. When reception is completed normally while REC 128 (error passive), REC is set to 127. When in a bus-off state, an indeterminate value is stored in this register. The register value is reset to H'00 upon returning to an error-active state. I CAN0 Transmit Error Count Register (CAN0TEC) <Address: H'0080 100B> I CAN1 Transmit Error Count Register (CAN1TEC) <Address: H'0080 140B> When in an error-active/error-passive state, the transmit error count value is stored in this register. The counter counts down during normal transmission and counts up when an error occurs. When in a bus-off state, an indeterminate value is stored in this register. The register value is reset to H'00 upon returning to an error-active state. D 8 9 1 01 11 21 31 4 D 1 5 TEC <When reset: H'00> D Bit Name Function R W 8-15 TEC Transmit error count value – (Transmit error counter) CAN MODULES

13-27 Rev.1.0

13.2.7 CAN Baud Rate Prescalers

I CAN0 Baud Rate Prescaler (CAN0BRP) <Address: H'0080 1016> I CAN1 Baud Rate Prescaler (CAN1BRP) <Address: H'0080 1416> D 0 123456 D 7 CANBRP <When reset: H'01> D Bit Name Function R W 0-7 BRP Selects a baud rate prescaler value This register is used to set the CAN module Tq period. The CAN baud rate is determined by (Tq period x number of Tq's in one bit). Tq period = (CANBRP + 1) / CPU clock 1CAN transfer baud rate = Tq period x number of Tq's in one bit Number of Tq's in one bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 Note 1: Setting H'00 (divide by 1) is inhibited. Note 2: Do not modify the CAN Baud Rate Prescaler (CAN0BRP or CAN1BRP) while the CAN module is operating (CAN Status Register CRS bit = 0). CAN MODULES

13-28 Rev.1.0

13.2.8 CAN Interrupt Related Registers

I CAN0 Slot Interrupt Status Register (CAN0SLIST) <Address: H'0080 100C> I CAN1 Slot Interrupt Status Register (CAN1SLIST) <Address: H'0080 140C> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 SSB0 SSB1 SSB2 SSb3 SSB4 SSB5 SSB6 SSB7 SSB8 SSB9 SSB10SSB11 SSB12SSB13SSB14 SSB15 <When reset: H'0000> D Bit Name Function R W

0 SSB0 (Slot 0 interrupt request status) 0: Interrupt not requested

1 SSB1 (Slot 1 interrupt request status) 1: Interrupt requested

2 SSB2 (Slot 2 interrupt request status)

3 SSB3 (Slot 3 interrupt request status)

4 SSB4 (Slot 4 interrupt request status)

5 SSB5 (Slot 5 interrupt request status)

6 SSB6 (Slot 6 interrupt request status)

7 SSB7 (Slot 7 interrupt request status)

8 SSB8 (Slot 8 interrupt request status)

9 SSB9 (Slot 9 interrupt request status)

10 SSB10 (Slot 10 interrupt request status)

11 SSB11 (Slot 11 interrupt request status)

12 SSB12 (Slot 12 interrupt request status)

13 SSB13 (Slot 13 interrupt request status)

14 SSB14 (Slot 14 interrupt request status)

15 SSB15 (Slot 15 interrupt request status)

W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. CAN MODULES

13-29 Rev.1.0 When using CAN interrupts, it is possible to know which slot has requested an interrupt by inspecting this register.

• Slots set for transmission The status bit is set to 1 when transmission is completed. This bit is cleared by writing 0 in software.
• Slots set for reception The status bit is set to 1 when the CAN module finished receiving and finished storing the received message in the message slot. This bit is cleared by writing 0 in software. When writing to the CAN Slot Interrupt Status Register, be sure to write 0 for the bits to be cleared and 1 for all other bits. Writing 1 in software does not affect any bit of this register, the bit retains the value it had before writing. Note 1: For remote frame receive slots with the automatic answering function enabled, the status is set after receiving a remote frame and again after sending a data frame. Note 2: For remote frame transmit slots, the status is set after having transmitted a remote frame and again after having received a data frame. Note 3: If the status bit is set upon occurrence of an interrupt request at the same time it is cleared in software, the former has priority so that the status bit is set. CAN MODULES

13-30 Rev.1.0 I CAN0 Slot Interrupt Mask Register (CAN0SLIMK) <Address: H'0080 1010> I CAN1 Slot Interrupt Mask Register (CAN1SLIMK) <Address: H'0080 1410> D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 IRB0 IRB1 IRB2 IRB3 IRB4 IRB5 IRB6 IRB7 IRB8 IRB9 IRB10 IRB11 IRB12 IRB13 IRB14 IRB15 <When reset: H'0000> D Bit Name Function R W

0 IRB0 (Slot 0 interrupt request mask) 0: Masks (disables) interrupt request

1 IRB1 (Slot 1 interrupt request mask) 1: Enables interrupt request

2 IRB2 (Slot 2 interrupt request mask)

3 IRB3 (Slot 3 interrupt request mask)

4 IRB4 (Slot 4 interrupt request mask)

5 IRB5 (Slot 5 interrupt request mask)

6 IRB6 (Slot 6 interrupt request mask)

7 IRB7 (Slot 7 interrupt request mask)

8 IRB8 (Slot 8 interrupt request mask)

9 IRB9 (Slot 9 interrupt request mask)

10 IRB10 (Slot 10 interrupt request mask)

11 IRB11 (Slot 11 interrupt request mask)

12 IRB12 (Slot 12 interrupt request mask)

13 IRB13 (Slot 13 interrupt request mask)

14 IRB14 (Slot 14 interrupt request mask)

15 IRB15 (Slot 15 interrupt request mask)

This register is used to enable or disable interrupt requests generated upon completion of data transmission/reception by each slot. Setting the IRBn (n=0-15) bit for any slot to 1 enables the interrupt requests generated upon completion of data transmission/reception by that slot. Check the CAN Slot Interrupt Status Register (CANSLIST) to see which slot has generated the interrupt request. CAN MODULES

13-31 Rev.1.0 I CAN0 Error Interrupt Status Register (CAN0ERIST) <Address: H'0080 1014> I CAN1 Error Interrupt Status Register (CAN1ERIST) <Address: H'0080 1414> D 0 123456 D 7 EIS PIS OIS <When reset: H'00> D Bit Name Function R W 0-4 No functions assigned 0 –

5 EIS 0: Interrupt not requested

(CAN bus error interrupt status) 1: Interrupt requested

6 PIS

(Error passive interrupt status)

7 OIS

(Bus off interrupt status) W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. When using CAN interrupts, checking this register will help to find the cause of interrupt if the interrupt has been generated due to an error. (1) EIS (CAN bus error interrupt status) bit (D5) This bit is set to 1 when a communication error is detected. This bit can be cleared by writing 0 in software. (2) PIS (Error passive interrupt status) bit (D6) This bit is set to 1 when the CAN module goes to an error-passive state. This bit can be cleared by writing 0 in software. (3) OIS (Bus off interrupt status) bit (D7) This bit is set to 1 when the CAN module goes to a bus-off state. This bit can be cleared by writing 0 in software. When writing to the CAN Error Interrupt Status Register, be sure to write 0 for the bits to be cleared and 1 for all other bits. Writing 1 in software does not affect any bit of this register, the bit retains the value it had before writing. CAN MODULES

13-32 Rev.1.0 I CAN0 Error Interrupt Mask Register (CAN0ERIMK) <Address: H'0080 1015> I CAN1 Error Interrupt Mask Register (CAN1ERIMK) <Address: H'0080 1415> D 8 9 1 01 11 21 31 4 D 1 5 EIM PIM OIM <When reset: H'00> D Bit Name Function R W 8-12 No functions assigned 0 –

13 EIM 0: Masks (disables) interrupt request

(CAN bus error interrupt mask) 1: Enables interrupt request

14 PIMm

(Error passive interrupt mask)

15 OIM

(Bus off interrupt mask) (1) EIM (CAN bus error interrupt mask) bit (D5) This bit enables or disables the interrupt request generated by occurrence of a CAN bus error. Setting this bit to 1 enables CAN bus error interrupt request. (2) PIM (Error passive interrupt mask) bit (D6) This bit enables or disables the interrupt request generated by transition of the CAN module status to an error-passive state. Setting this bit to 1 enables an error-passive interrupt request. (3) OIM (Bus off interrupt mask) bit (D7) This bit enables or disables the interrupt request generated by transition of the CAN module status to a bus-off state. Setting this bit to 1 enables a bus-off interrupt request. CAN MODULES

13-33 Rev.1.0 CAN0 transmit/receive & error interrupt Data bus IRB0 F/F SSB0 F/Fb0 IRB1 F/F SSB1 F/Fb1 IRB2 F/F SSB2 F/Fb2 IRB3 F/F SSB3 F/Fb3 IRB4 F/F SSB4 F/Fb4 (Level) 19-source inputs CAN0SLIST <H'0080 100C> CAN0SLIMK <H'0080 1010> Slot 0 transmit/receive complete IRB5 F/F SSB5 F/Fb5 IRB6 F/F SSB6 F/Fb6 IRB7 F/F To 11 other input sources in the next page F/Fb7 SSB7 Slot 1 transmit/receive complete Slot 2 transmit/receive complete Slot 3 transmit/receive complete Slot 4 transmit/receive complete Slot 5 transmit/receive complete Slot 6 transmit/receive complete Slot 7 transmit/receive complete Figure 13.2.9 Block Diagram of CAN0 Transmit/Receive & Error Interrupts (1/3) CAN MODULES

13-34 Rev.1.0 IRB8 F/F SSB8 F/Fb8 IRB9 F/F SSB9 F/Fb9 b10 IRB10 F/F SSB10 F/Fb10 b11 IRB11 F/F SSB11 F/Fb11 b12 IRB12 F/F SSB12 F/Fb12 CAN0SLIST <H'0080 100C> CAN0SLIMK <H'0080 1010> b13 IRB13 F/F SSB13 F/Fb13 b14 IRB14 F/F SSB14 F/Fb14 b15 IRB15 F/F F/Fb15 SSB15 To the preceding page Data bus (Level) 19-source inputs Slot 8 transmit/receive complete To 3 other input sources in the next page Slot 9 transmit/receive complete Slot 10 transmit/receive complete Slot 11 transmit/receive complete Slot 12 transmit/receive complete Slot 13 transmit/receive complete Slot 14 transmit/receive complete Slot 15 transmit/receive complete Figure 13.2.10 Block Diagram of CAN0 Transmit/Receive & Error Interrupts (2/3) CAN MODULES

13-35 Rev.1.0 EIM F/F EIS F/Fb13 PIM F/F PIS F/Fb14 OIM F/F OIS F/Fb15 CAN0ERIST <H'0080 1014> CAN0ERIMK <H'0080 1015> CAN bus error occurs Goes to error-passive state Goes to bus-off state To the preceding page Data bus (Level) 19-source inputs Figure 13.2.11 Block Diagram of CAN0 Transmit/Receive & Error Interrupts (3/3) CAN MODULES

13-36 Rev.1.0 IRB0 F/F SSB0 F/Fb0 IRB1 F/F SSB1 F/Fb1 IRB2 F/F SSB2 F/Fb2 IRB3 F/F SSB3 F/Fb3 IRB4 F/F SSB4 F/Fb4 CAN1SLIST <H'0080 140C> CAN1SLIMK <H'0080 1410> IRB5 F/F SSB5 F/Fb5 IRB6 F/F SSB6 F/Fb6 IRB7 F/F F/Fb7 SSB7 CAN1 transmit/receive & error interrupt Data bus (Level) 19-source inputs Slot 0 transmit/receive complete To 11 other input sources in the next page Slot 1 transmit/receive complete Slot 2 transmit/receive complete Slot 3 transmit/receive complete Slot 4 transmit/receive complete Slot 5 transmit/receive complete Slot 6 transmit/receive complete Slot 7 transmit/receive complete Figure 13.2.12 Block Diagram of CAN1 Transmit/Receive & Error Interrupts (1/3) CAN MODULES

13-37 Rev.1.0 IRB8 F/F SSB8 F/Fb8 IRB9 F/F SSB9 F/Fb9 b10 IRB10 F/F SSB10 F/Fb10 b11 IRB11 F/F SSB11 F/Fb11 b12 IRB12 F/F SSB12 F/Fb12 CAN1SLIST <H'0080 140C> CAN1SLIMK <H'0080 1410> b13 IRB13 F/F SSB13 F/Fb13 b14 IRB14 F/F SSB14 F/Fb14 b15 IRB15 F/F F/Fb15 SSB15 To the preceding page Data bus (Level) 19-source inputs Slot 8 transmit/receive complete To 3 other input sources in the next page Slot 9 transmit/receive complete Slot 10 transmit/receive complete Slot 11 transmit/receive complete Slot 12 transmit/receive complete Slot 13 transmit/receive complete Slot 14 transmit/receive complete Slot 15 transmit/receive complete Figure 13.2.13 Block Diagram of CAN1 Transmit/Receive & Error Interrupts (2/3) CAN MODULES

13-38 Rev.1.0 Figure 13.2.14 Block Diagram of CAN1 Transmit/Receive & Error Interrupts (3/3) EIM F/F EIS F/Fb13 PIM F/F PIS F/Fb14 OIM F/F OIS F/Fb15 CAN1ERIST <H'0080 1414> CAN1ERIMK <H'0080 1415> CAN bus error occurs Goes to error-passive state Goes to bus-off state To the preceding page Data bus (Level) 19-source inputs CAN MODULES

13-39 Rev.1.0

13.2.9 CAN Mask Registers

I CAN0 Global Mask Register Standard ID0 (C0GMSKS0) <Address: H'0080 1028> I CAN0 Local Register A Standard ID0 (C0LMSKAS0) <Address: H'0080 1030> I CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0) <Address: H'0080 1038> I CAN1 Global Mask Register Standard ID0 (C1GMSKS0) <Address: H'0080 1428> I CAN1 Local Register A Standard ID0 (C1LMSKAS0) <Address: H'0080 1430> I CAN1 Local Mask Register B Standard ID0 (C1LMSKBS0) <Address: H'0080 1438> D 0 123456 D 7 SID0M SID1M SID2M SID3M SID4M <When reset: H'00> D Bit Name Function R W 0-2 No functions assigned 0 – 3-7 SID0M-SID4M 0: ID not checked (Standard ID0 to standard ID4) 1: ID checked I CAN0 Global Mask Register Standard ID1 (C0GMSKS1) <Address: H'0080 1029> I CAN0 Local Register A Standard ID1 (C0LMSKAS1) <Address: H'0080 1031> I CAN0 Local Mask Register B Standard ID1 (C0LMSKBS1) <Address: H'0080 1039> I CAN1 Global Mask Register Standard ID1 (C1GMSKS1) <Address: H'0080 1429> I CAN1 Local Register A Standard ID1 (C1LMSKAS1) <Address: H'0080 1431> I CAN1 Local Mask Register B Standard ID1 (C1LMSKBS1) <Address: H'0080 1439> <When reset: H'00> D Bit Name Function R W 8-9 No functions assigned 0 – 10-15 SID5M-SID10M 0: ID not checked (Standard ID5 to standard ID10) 1: ID checked D 8 9 1 01 11 21 31 4 D 1 5 SID5M SID6M SID7M SID8M SID9M SID10M CAN MODULES

13-40 Rev.1.0 Three mask registers are used in acceptance filtering: Global Mask Register, Local Mask Register A, and Local Mask Register B. The Global Mask Register is used for message slots 0-13, while the Local Mask Registers A and B respectively are used for slots 14 and 15.

• When any bit in this register is set to 0, the corresponding ID bit is masked during acceptance filtering (so that the ID is assumed to have matched).
• When any bit in this register is set to 1, the corresponding ID bit is compared with the received ID during acceptance filtering. If it matches the ID set for the message slot, the received data is stored in that slot. Note 1: SID0M corresponds to the MSB of the standard ID. Note 2: The Global Mask Register can only be modified when none of the slots 0-13 has receive requests set. Note 3: The Local Mask Register A can only be modified when slot 14 does not have receive requests set. Note 4: The Local Mask Register B can only be modified when slot 15 does not have receive requests set. CAN MODULES

13-41 Rev.1.0 I CAN0 Global Mask Register Extended ID0 (C0GMSKE0) <Address: H'0080 102A> I CAN0 Local Register A Extended ID0 (C0LMSKAE0) <Address: H'0080 1032> I CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) <Address: H'0080 103A> I CAN1 Global Mask Register Extended ID0 (C1GMSKE0) <Address: H'0080 142A> I CAN1 Local Register A Extended ID0 (C1LMSKAE0) <Address: H'0080 1432> I CAN1 Local Mask Register B Extended ID0 (C1LMSKBE0) <Address: H'0080 143A> D 0 123456 D 7 EID0M EID1M EID2M EID3M <When reset: H'00> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 EID0M-EID3M 0: ID not checked (Extended ID0 to extended ID3) 1: ID checked I CAN0 Global Mask Register Extended ID1 (C0GMSKE1) <Address: H'0080 102B> I CAN0 Local Register A Extended ID1 (C0LMSKAE1) <Address: H'0080 1033> I CAN0 Local Mask Register B Extended ID1 (C0LMSKBE1) <Address: H'0080 103B> I CAN1 Global Mask Register Extended ID1 (C1GMSKE1) <Address: H'0080 142B> I CAN1 Local Register A Extended ID1 (C1LMSKAE1) <Address: H'0080 1433> I CAN1 Local Mask Register B Extended ID1 (C1LMSKBE1) <Address: H'0080 143B> D 8 9 1 01 11 21 31 4 D 1 5 EID4M EID5M EID6M EID7M EID8M EID9M EID10M EID11M <When reset: H'00> D Bit Name Function R W 8-15 EID4M-EID11M 0: ID not checked (Standard ID4 to standard ID11) 1: ID checked CAN MODULES

13-42 Rev.1.0 I CAN0 Global Mask Register Extended ID2 (C0GMSKE2) <Address: H'0080 102C> I CAN0 Local Register A Extended ID2 (C0LMSKAE2) <Address: H'0080 1034> I CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2) <Address: H'0080 103C> I CAN1 Global Mask Register Extended ID2 (C1GMSKE2) <Address: H'0080 142C> I CAN1 Local Register A Extended ID2 (C1LMSKAE2) <Address: H'0080 1434> I CAN1 Local Mask Register B Extended ID2 (C1LMSKBE2) <Address: H'0080 143C> D 0 123456 D 7 EID12M EID13M EID14M EID15M EID16M EID17M <When reset: H'00> D Bit Name Function R W 0,1 No functions assigned 0 – 2-7 EID12M-EID17M 0: ID not checked (Extended ID12 to extended ID17) 1: ID checked Three mask registers are used in acceptance filtering: Global Mask Register, Local Mask Register A, and Local Mask Register B. The Global Mask Register is used for message slots 0-13, while the Local Mask Registers A and B respectively are used for slots 14 and 15.

• When any bit in this register is set to 0, the corresponding ID bit is masked during acceptance filtering (so that the ID is assumed to have matched).
• When any bit in this register is set to 1, the corresponding ID bit is compared with the received ID during acceptance filtering. If it matches the ID set for the message slot, the received data is stored in that slot. Note 1: EID0M corresponds to the MSB of the extended ID. Note 2: The Global Mask Register can only be modified when none of the slots 0-13 has receive requests set. Note 3: The Local Mask Register A can only be modified when slot 14 does not have receive requests set. Note 4: The Local Mask Register B can only be modified when slot 15 does not have receive requests set. CAN MODULES

13-43 Rev.1.0

13.2.10 CAN Message Slot Control Registers

I CAN0 Message Slot 0 Control Register (C0MSL0CNT) <Address: H'0080 1050> I CAN0 Message Slot 1 Control Register (C0MSL1CNT) <Address: H'0080 1051> I CAN0 Message Slot 2 Control Register (C0MSL2CNT) <Address: H'0080 1052> I CAN0 Message Slot 3 Control Register (C0MSL3CNT) <Address: H'0080 1053> I CAN0 Message Slot 4 Control Register (C0MSL4CNT) <Address: H'0080 1054> I CAN0 Message Slot 5 Control Register (C0MSL5CNT) <Address: H'0080 1055> I CAN0 Message Slot 6 Control Register (C0MSL6CNT) <Address: H'0080 1056> I CAN0 Message Slot 7 Control Register (C0MSL7CNT) <Address: H'0080 1057> I CAN0 Message Slot 8 Control Register (C0MSL8CNT) <Address: H'0080 1058> I CAN0 Message Slot 9 Control Register (C0MSL9CNT) <Address: H'0080 1059> I CAN0 Message Slot 10 Control Register (C0MSL10CNT) <Address: H'0080 105A> I CAN0 Message Slot 11 Control Register (C0MSL11CNT) <Address: H'0080 105B> I CAN0 Message Slot 12 Control Register (C0MSL12CNT) <Address: H'0080 105C> I CAN0 Message Slot 13 Control Register (C0MSL13CNT) <Address: H'0080 105D> I CAN0 Message Slot 14 Control Register (C0MSL14CNT) <Address: H'0080 105E> I CAN0 Message Slot 15 Control Register (C0MSL15CNT) <Address: H'0080 105F> I CAN1 Message Slot 0 Control Register (C1MSL0CNT) <Address: H'0080 1450> I CAN1 Message Slot 1 Control Register (C1MSL1CNT) <Address: H'0080 1451> I CAN1 Message Slot 2 Control Register (C1MSL2CNT) <Address: H'0080 1452> I CAN1 Message Slot 3 Control Register (C1MSL3CNT) <Address: H'0080 1453> I CAN1 Message Slot 4 Control Register (C1MSL4CNT) <Address: H'0080 1454> I CAN1 Message Slot 5 Control Register (C1MSL5CNT) <Address: H'0080 1455> I CAN1 Message Slot 6 Control Register (C1MSL6CNT) <Address: H'0080 1456> I CAN1 Message Slot 7 Control Register (C1MSL7CNT) <Address: H'0080 1457> I CAN1 Message Slot 8 Control Register (C1MSL8CNT) <Address: H'0080 1458> I CAN1 Message Slot 9 Control Register (C1MSL9CNT) <Address: H'0080 1459> I CAN1 Message Slot 10 Control Register (C1MSL10CNT) <Address: H'0080 145A> I CAN1 Message Slot 11 Control Register (C1MSL11CNT) <Address: H'0080 145B> I CAN1 Message Slot 12 Control Register (C1MSL12CNT) <Address: H'0080 145C> I CAN1 Message Slot 13 Control Register (C1MSL13CNT) <Address: H'0080 145D> I CAN1 Message Slot 14 Control Register (C1MSL14CNT) <Address: H'0080 145E> I CAN1 Message Slot 15 Control Register (C1MSL15CNT) <Address: H'0080 145F> CAN MODULES

13-44 Rev.1.0 D 0 ( D 8 ) 123456 D 7 (D15) TR RR RM RL RA ML TRSTAT TRFIN <When reset: H'00> D Bit Name Function R W

0 TR 0: Does not use the message slot as a transmit

(Transmit request) slot 1: Uses the message slot as a transmit slot

1 RR 0: Does not use the message slot as a receive

(Receive request) slot 1: Uses the message slot as a receive slot

2 RM 0: Transmit/receives data frame

(Remote) 1: Transmit/receives remote frame

3 RL 0: Enables automatic answering for remote

(Automatic answering frame disable) 1: Disables automatic answering for remote frame

4 RA BasicCAN mode –

(Remote active) 0: Data frame receive (status) 1: Remote frame receive (status) Normal mode 0: Data frame 1: Remote frame

5 ML 0: No messages lost

(Message lost) 1: Messages lost

6 TRSTAT For transmit slots –

(Transmit/receive status) 0: Not transmitting (idle) 1: Transmit request accepted For receive slots 0: Not receiving (idle) 1: Storing the received data

7 TRFIN For transmit slots

(Transmit/receive 0: Not transmitted yet finished) 1: Finished transmitting For receive slots 0: Not received yet 1: Finished receiving W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. CAN MODULES Note 1: Do not write to this register while the CAN module is in a reset state (CANCNT register FRST or RST bit is set). If a transmit/receive request is written to the register while in this state, the CAN module may perform transmission or reception at unexpected timing. Note 2: If there is a data/remote frame transmit request for multiple slots, the slot with the smallest slot number has priority and a frame is transmitted from that slot. If there is a data/remote frame receive request for multiple slots, the slot with the smallest slot number among those that satisfy receive conditions has priority and a frame is received in that slot.

13-45 Rev.1.0 (1) TR (Transmit request) bit (D0) Set this bit to 1 when using the message slot as a transmit slot. Set this bit to 0 when using the message slot as a data frame or remote frame receive slot. (2) RR (Receive request) bit (D1) Set this bit to 1 when using the message slot as a receive slot. Set this bit to 0 when using the message slot as a data frame or remote frame transmit slot. If both the TR (Transmit request) and RR (Receive request) bits are set to 1, device operation is instable. (3) RM (Remote) bit (D2) Set this bit to 1 when using the message slot to handle remote frames. The message slot may be set to handle remote frames in following two ways.

• Set for remote frame transmission The data stored in the message slot is transmitted as a remote frame. When transmission is finished, the slot automatically changes to a data frame receive slot. However, if a data frame is received before the CAN module finished sending the remote frame, the received data is stored in the message slot and the remote frame is not transmitted.
• Set for remote frame reception The message slot receives a remote frame. The processing performed after reception depends on how the RL (Automatic answering disable) bit is set. (4) RL (Automatic answering disable) bit (D3) This bit is effective when the message slot has been set as a remote frame receive slot. It selects the processing to be performed after receiving a remote frame. Setting this bit to 0 enables automatic answering so that after receiving a remote frame, the message slot automatically changes to a transmit slot and the data stored in it is transmitted as a data frame. When this bit is set to 1, the message slot becomes inactive after receiving a remote frame. Note: This bit must always be set to 0 unless the message slot is set for remote frame reception. CAN MODULES

13-46 Rev.1.0 (5) RA (Remote active) bit (D4) This bit functions differently between slots 0-13 and slots 14 and 15.

• Slots 0-13 For slots which have been set for remote frame transmission (reception), this bit is set to 1. Then when remote frame transmission (or reception) is completed, the bit is cleared to 0.
• Slots 14 and 15 For these slots, the bit functions differently depending on how the CAN Control Register BCM (BasicCAN mode) bit is set. When BCM = 0 (normal mode) : If the slot has been set to transmit (or receive) a remote frame, this bit is set to 1. When BCM = 1 (BasicCAN mode) : This bit shows which type of frame has been received. When in BasicCAN mode, either slot 14 or 15 stores the received data regardless of whether it is a data frame or a remote frame. When RA = 0, it means that the frame stored in the slot is a data frame; when RA = 1, it means that the frame stored in the slot is a remote frame. (6) ML (Message lost) bit (D5) This bit is effective for receive slots. It is set to 1 when the received data stored in the message slot is overwritten by receive operation before being read out. This bit is cleared by writing 0 in software. (7) TRSTAT (Transmit/receive status) bit (D6) This bit indicates that transmission or reception is in progress and the CAN module is accessing the message slot. This bit is set to 1 when the message slot is being accessed or set to 0 when not accessed.
• For transmit slots This bit is set to 1 when a transmit request for the message slot has been accepted, and is cleared to 0 when arbitration fails, a CAN bus error occurs, or transmission finishes.
• For receive slots This bit is set to 1 when reception is in progress and the CAN module is storing the received data in the message slot. Note that the value read out from the message slot while this bit = 1 is indeterminate. CAN MODULES

13-47 Rev.1.0 (8) TRFIN (Transmit/receive finished) bit (D7) This bit indicates that the CAN module has finished transmitting or receiving data.

• For transmit slots This bit is set to 1 when the CAN module finishes sending data from the message slot. This bit is cleared by writing 0 in software. However, this bit cannot be cleared while the TRSTAT (transmit/receive status) bit remains 1.
• For receive slots This bit is set to 1 when the CAN module finished receiving the data normally that is to be stored in the message slot. This bit is cleared by writing 0 in software. However, this bit cannot be cleared while the TRSTAT (transmit/receive status) bit remains 1. Note: Before reading the received data from the message slot, be sure to clear the TRFIN (transmit/receive finished) bit. If the TRFIN (transmit/receive finished) bit remains set after readout, it means that new received data was stored in the message slot while being read out, and that the read data contains an indeterminate value. In such a case, discard the read data and clear the TRFIN (transmit/receive finished) bit before performing read operation again. CAN MODULES

13-48 Rev.1.0

13.2.11 CAN Message Slots

I CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) <Address: H'0080 1100> I CAN0 Message Slot 1 Standard ID0 (C0MSL1SID0) <Address: H'0080 1110> I CAN0 Message Slot 2 Standard ID0 (C0MSL2SID0) <Address: H'0080 1120> I CAN0 Message Slot 3 Standard ID0 (C0MSL3SID0) <Address: H'0080 1130> I CAN0 Message Slot 4 Standard ID0 (C0MSL4SID0) <Address: H'0080 1140> I CAN0 Message Slot 5 Standard ID0 (C0MSL5SID0) <Address: H'0080 1150> I CAN0 Message Slot 6 Standard ID0 (C0MSL6SID0) <Address: H'0080 1160> I CAN0 Message Slot 7 Standard ID0 (C0MSL7SID0) <Address: H'0080 1170> I CAN0 Message Slot 8 Standard ID0 (C0MSL8SID0) <Address: H'0080 1180> I CAN0 Message Slot 9 Standard ID0 (C0MSL9SID0) <Address: H'0080 1190> I CAN0 Message Slot 10 Standard ID0 (C0MSL10SID0) <Address: H'0080 11A0> I CAN0 Message Slot 11 Standard ID0 (C0MSL11SID0) <Address: H'0080 11B0> I CAN0 Message Slot 12 Standard ID0 (C0MSL12SID0) <Address: H'0080 11C0> I CAN0 Message Slot 13 Standard ID0 (C0MSL13SID0) <Address: H'0080 11D0> I CAN0 Message Slot 14 Standard ID0 (C0MSL14SID0) <Address: H'0080 11E0> I CAN0 Message Slot 15 Standard ID0 (C0MSL15SID0) <Address: H'0080 11F0> I CAN1 Message Slot 0 Standard ID0 (C1MSL0SID0) <Address: H'0080 1500> I CAN1 Message Slot 1 Standard ID0 (C1MSL1SID0) <Address: H'0080 1510> I CAN1 Message Slot 2 Standard ID0 (C1MSL2SID0) <Address: H'0080 1520> I CAN1 Message Slot 3 Standard ID0 (C1MSL3SID0) <Address: H'0080 1530> I CAN1 Message Slot 4 Standard ID0 (C1MSL4SID0) <Address: H'0080 1540> I CAN1 Message Slot 5 Standard ID0 (C1MSL5SID0) <Address: H'0080 1550> I CAN1 Message Slot 6 Standard ID0 (C1MSL6SID0) <Address: H'0080 1560> I CAN1 Message Slot 7 Standard ID0 (C1MSL7SID0) <Address: H'0080 1570> I CAN1 Message Slot 8 Standard ID0 (C1MSL8SID0) <Address: H'0080 1580> I CAN1 Message Slot 9 Standard ID0 (C1MSL9SID0) <Address: H'0080 1590> I CAN1 Message Slot 10 Standard ID0 (C1MSL10SID0) <Address: H'0080 15A0> I CAN1 Message Slot 11 Standard ID0 (C1MSL11SID0) <Address: H'0080 15B0> I CAN1 Message Slot 12 Standard ID0 (C1MSL12SID0) <Address: H'0080 15C0> I CAN1 Message Slot 13 Standard ID0 (C1MSL13SID0) <Address: H'0080 15D0> I CAN1 Message Slot 14 Standard ID0 (C1MSL14SID0) <Address: H'0080 15E0> I CAN1 Message Slot 15 Standard ID0 (C1MSL15SID0) <Address: H'0080 15F0> CAN MODULES

13-49 Rev.1.0 D 0 123456 D 7 SID0 SID1 SID2 SID3 SID4 <When reset: indeterminate> D Bit Name Function R W 0-2 No functions assigned 0 – 3-7 SID0-SID4 Standard ID0 to standard ID4 (Standard ID0 to standard ID4) These registers comprise a transmit frame/receive frame memory space. CAN MODULES

13-50 Rev.1.0 I CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) <Address: H'0080 1101> I CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1) <Address: H'0080 1111> I CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1) <Address: H'0080 1121> I CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1) <Address: H'0080 1131> I CAN0 Message Slot 4 Standard ID1 (C0MSL4SID1) <Address: H'0080 1141> I CAN0 Message Slot 5 Standard ID1 (C0MSL5SID1) <Address: H'0080 1151> I CAN0 Message Slot 6 Standard ID1 (C0MSL6SID1) <Address: H'0080 1161> I CAN0 Message Slot 7 Standard ID1 (C0MSL7SID1) <Address: H'0080 1171> I CAN0 Message Slot 8 Standard ID1 (C0MSL8SID1) <Address: H'0080 1181> I CAN0 Message Slot 9 Standard ID1 (C0MSL9SID1) <Address: H'0080 1191> I CAN0 Message Slot 10 Standard ID1 (C0MSL10SID1) <Address: H'0080 11A1> I CAN0 Message Slot 11 Standard ID1 (C0MSL11SID1) <Address: H'0080 11B1> I CAN0 Message Slot 12 Standard ID1 (C0MSL12SID1) <Address: H'0080 11C1> I CAN0 Message Slot 13 Standard ID1 (C0MSL13SID1) <Address: H'0080 11D1> I CAN0 Message Slot 14 Standard ID1 (C0MSL14SID1) <Address: H'0080 11E1> I CAN0 Message Slot 15 Standard ID1 (C0MSL15SID1) <Address: H'0080 11F1> I CAN1 Message Slot 0 Standard ID1 (C1MSL0SID1) <Address: H'0080 1501> I CAN1 Message Slot 1 Standard ID1 (C1MSL1SID1) <Address: H'0080 1511> I CAN1 Message Slot 2 Standard ID1 (C1MSL2SID1) <Address: H'0080 1521> I CAN1 Message Slot 3 Standard ID1 (C1MSL3SID1) <Address: H'0080 1531> I CAN1 Message Slot 4 Standard ID1 (C1MSL4SID1) <Address: H'0080 1541> I CAN1 Message Slot 5 Standard ID1 (C1MSL5SID1) <Address: H'0080 1551> I CAN1 Message Slot 6 Standard ID1 (C1MSL6SID1) <Address: H'0080 1561> I CAN1 Message Slot 7 Standard ID1 (C1MSL7SID1) <Address: H'0080 1571> I CAN1 Message Slot 8 Standard ID1 (C1MSL8SID1) <Address: H'0080 1581> I CAN1 Message Slot 9 Standard ID1 (C1MSL9SID1) <Address: H'0080 1591> I CAN1 Message Slot 10 Standard ID1 (C1MSL10SID1) <Address: H'0080 15A1> I CAN1 Message Slot 11 Standard ID1 (C1MSL11SID1) <Address: H'0080 15B1> I CAN1 Message Slot 12 Standard ID1 (C1MSL12SID1) <Address: H'0080 15C1> I CAN1 Message Slot 13 Standard ID1 (C1MSL13SID1) <Address: H'0080 15D1> I CAN1 Message Slot 14 Standard ID1 (C1MSL14SID1) <Address: H'0080 15E1> I CAN1 Message Slot 15 Standard ID1 (C1MSL15SID1) <Address: H'0080 15F1> CAN MODULES

13-51 Rev.1.0 D 8 9 1 01 11 21 31 4 D 1 5 SID5 SID6 SID7 SID8 SID9 SID10 <When reset: indeterminate> D Bit Name Function R W 8,9 No functions assigned 0 – 10-15 SID5-SID10 Standard ID5 to standard ID10 (Standard ID5 to standard ID10) These registers comprise a transmit frame/receive frame memory space. CAN MODULES

13-52 Rev.1.0 I CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) <Address: H'0080 1102> I CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0) <Address: H'0080 1112> I CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0) <Address: H'0080 1122> I CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0) <Address: H'0080 1132> I CAN0 Message Slot 4 Extended ID0 (C0MSL4EID0) <Address: H'0080 1142> I CAN0 Message Slot 5 Extended ID0 (C0MSL5EID0) <Address: H'0080 1152> I CAN0 Message Slot 6 Extended ID0 (C0MSL6EID0) <Address: H'0080 1162> I CAN0 Message Slot 7 Extended ID0 (C0MSL7EID0) <Address: H'0080 1172> I CAN0 Message Slot 8 Extended ID0 (C0MSL8EID0) <Address: H'0080 1182> I CAN0 Message Slot 9 Extended ID0 (C0MSL9EID0) <Address: H'0080 1192> I CAN0 Message Slot 10 Extended ID0 (C0MSL10EID0) <Address: H'0080 11A2> I CAN0 Message Slot 11 Extended ID0 (C0MSL11EID0) <Address: H'0080 11B2> I CAN0 Message Slot 12 Extended ID0 (C0MSL12EID0) <Address: H'0080 11C2> I CAN0 Message Slot 13 Extended ID0 (C0MSL13EID0) <Address: H'0080 11D2> I CAN0 Message Slot 14 Extended ID0 (C0MSL14EID0) <Address: H'0080 11E2> I CAN0 Message Slot 15 Extended ID0 (C0MSL15EID0) <Address: H'0080 11F2> I CAN1 Message Slot 0 Extended ID0 (C1MSL0EID0) <Address: H'0080 1502> I CAN1 Message Slot 1 Extended ID0 (C1MSL1EID0) <Address: H'0080 1512> I CAN1 Message Slot 2 Extended ID0 (C1MSL2EID0) <Address: H'0080 1522> I CAN1 Message Slot 3 Extended ID0 (C1MSL3EID0) <Address: H'0080 1532> I CAN1 Message Slot 4 Extended ID0 (C1MSL4EID0) <Address: H'0080 1542> I CAN1 Message Slot 5 Extended ID0 (C1MSL5EID0) <Address: H'0080 1552> I CAN1 Message Slot 6 Extended ID0 (C1MSL6EID0) <Address: H'0080 1562> I CAN1 Message Slot 7 Extended ID0 (C1MSL7EID0) <Address: H'0080 1572> I CAN1 Message Slot 8 Extended ID0 (C1MSL8EID0) <Address: H'0080 1582> I CAN1 Message Slot 9 Extended ID0 (C1MSL9EID0) <Address: H'0080 1592> I CAN1 Message Slot 10 Extended ID0 (C1MSL10EID0) <Address: H'0080 15A2> I CAN1 Message Slot 11 Extended ID0 (C1MSL11EID0) <Address: H'0080 15B2> I CAN1 Message Slot 12 Extended ID0 (C1MSL12EID0) <Address: H'0080 15C2> I CAN1 Message Slot 13 Extended ID0 (C1MSL13EID0) <Address: H'0080 15D2> I CAN1 Message Slot 14 Extended ID0 (C1MSL14EID0) <Address: H'0080 15E2> I CAN1 Message Slot 15 Extended ID0 (C1MSL15EID0) <Address: H'0080 15F2> CAN MODULES

13-53 Rev.1.0 D 0 123456 D 7 EID0 EID1 EID2 EID3 <When reset: indeterminate> D Bit Name Function R W 0-3 No functions assigned 0 – 4-7 EID0-EID3 Extended ID0 to extended ID3 (Extended ID0 to extended ID3) These registers comprise a transmit frame/receive frame memory space. Note: For receive slots whose frame type has been chosen to be the standard ID format, the values written to their EID bits when storing the received data are indeterminate. CAN MODULES

13-54 Rev.1.0 I CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) <Address: H'0080 1103> I CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1) <Address: H'0080 1113> I CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1) <Address: H'0080 1123> I CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1) <Address: H'0080 1133> I CAN0 Message Slot 4 Extended ID1 (C0MSL4EID1) <Address: H'0080 1143> I CAN0 Message Slot 5 Extended ID1 (C0MSL5EID1) <Address: H'0080 1153> I CAN0 Message Slot 6 Extended ID1 (C0MSL6EID1) <Address: H'0080 1163> I CAN0 Message Slot 7 Extended ID1 (C0MSL7EID1) <Address: H'0080 1173> I CAN0 Message Slot 8 Extended ID1 (C0MSL8EID1) <Address: H'0080 1183> I CAN0 Message Slot 9 Extended ID1 (C0MSL9EID1) <Address: H'0080 1193> I CAN0 Message Slot 10 Extended ID1 (C0MSL10EID1) <Address: H'0080 11A3> I CAN0 Message Slot 11 Extended ID1 (C0MSL11EID1) <Address: H'0080 11B3> I CAN0 Message Slot 12 Extended ID1 (C0MSL12EID1) <Address: H'0080 11C3> I CAN0 Message Slot 13 Extended ID1 (C0MSL13EID1) <Address: H'0080 11D3> I CAN0 Message Slot 14 Extended ID1 (C0MSL14EID1) <Address: H'0080 11E3> I CAN0 Message Slot 15 Extended ID1 (C0MSL15EID1) <Address: H'0080 11F3> I CAN1 Message Slot 0 Extended ID1 (C1MSL0EID1) <Address: H'0080 1503> I CAN1 Message Slot 1 Extended ID1 (C1MSL1EID1) <Address: H'0080 1513> I CAN1 Message Slot 2 Extended ID1 (C1MSL2EID1) <Address: H'0080 1523> I CAN1 Message Slot 3 Extended ID1 (C1MSL3EID1) <Address: H'0080 1533> I CAN1 Message Slot 4 Extended ID1 (C1MSL4EID1) <Address: H'0080 1543> I CAN1 Message Slot 5 Extended ID1 (C1MSL5EID1) <Address: H'0080 1553> I CAN1 Message Slot 6 Extended ID1 (C1MSL6EID1) <Address: H'0080 1563> I CAN1 Message Slot 7 Extended ID1 (C1MSL7EID1) <Address: H'0080 1573> I CAN1 Message Slot 8 Extended ID1 (C1MSL8EID1) <Address: H'0080 1583> I CAN1 Message Slot 9 Extended ID1 (C1MSL9EID1) <Address: H'0080 1593> I CAN1 Message Slot 10 Extended ID1 (C1MSL10EID1) <Address: H'0080 15A3> I CAN1 Message Slot 11 Extended ID1 (C1MSL11EID1) <Address: H'0080 15B3> I CAN1 Message Slot 12 Extended ID1 (C1MSL12EID1) <Address: H'0080 15C3> I CAN1 Message Slot 13 Extended ID1 (C1MSL13EID1) <Address: H'0080 15D3> I CAN1 Message Slot 14 Extended ID1 (C1MSL14EID1) <Address: H'0080 15E3> I CAN1 Message Slot 15 Extended ID1 (C1MSL15EID1) <Address: H'0080 15F3> CAN MODULES

13-55 Rev.1.0 D 8 9 1 01 11 21 31 4 D 1 5 EID4 EID5 EID6 EID7 EID8 EID9 EID10 EID11 <When reset: indeterminate> D Bit Name Function R W 8-15 EID4-EID11 Extended ID4 to extended ID11 (Extended ID4 to extended ID11) These registers comprise a transmit frame/receive frame memory space. Note: For receive slots whose frame type has been chosen to be the standard ID format, the values written to their EID bits when storing the received data are indeterminate. CAN MODULES

13-56 Rev.1.0 I CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) <Address: H'0080 1104> I CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2) <Address: H'0080 1114> I CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2) <Address: H'0080 1124> I CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2) <Address: H'0080 1134> I CAN0 Message Slot 4 Extended ID2 (C0MSL4EID2) <Address: H'0080 1144> I CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) <Address: H'0080 1154> I CAN0 Message Slot 6 Extended ID2 (C0MSL6EID2) <Address: H'0080 1164> I CAN0 Message Slot 7 Extended ID2 (C0MSL7EID2) <Address: H'0080 1174> I CAN0 Message Slot 8 Extended ID2 (C0MSL8EID2) <Address: H'0080 1184> I CAN0 Message Slot 9 Extended ID2 (C0MSL9EID2) <Address: H'0080 1194> I CAN0 Message Slot 10 Extended ID2 (C0MSL10EID2) <Address: H'0080 11A4> I CAN0 Message Slot 11 Extended ID2 (C0MSL11EID2) <Address: H'0080 11B4> I CAN0 Message Slot 12 Extended ID2 (C0MSL12EID2) <Address: H'0080 11C4> I CAN0 Message Slot 13 Extended ID2 (C0MSL13EID2) <Address: H'0080 11D4> I CAN0 Message Slot 14 Extended ID2 (C0MSL14EID2) <Address: H'0080 11E4> I CAN0 Message Slot 15 Extended ID2 (C0MSL15EID2) <Address: H'0080 11F4> I CAN1 Message Slot 0 Extended ID2 (C1MSL0EID2) <Address: H'0080 1504> I CAN1 Message Slot 1 Extended ID2 (C1MSL1EID2) <Address: H'0080 1514> I CAN1 Message Slot 2 Extended ID2 (C1MSL2EID2) <Address: H'0080 1524> I CAN1 Message Slot 3 Extended ID2 (C1MSL3EID2) <Address: H'0080 1534> I CAN1 Message Slot 4 Extended ID2 (C1MSL4EID2) <Address: H'0080 1544> I CAN1 Message Slot 5 Extended ID2 (C1MSL5EID2) <Address: H'0080 1554> I CAN1 Message Slot 6 Extended ID2 (C1MSL6EID2) <Address: H'0080 1564> I CAN1 Message Slot 7 Extended ID2 (C1MSL7EID2) <Address: H'0080 1574> I CAN1 Message Slot 8 Extended ID2 (C1MSL8EID2) <Address: H'0080 1584> I CAN1 Message Slot 9 Extended ID2 (C1MSL9EID2) <Address: H'0080 1594> I CAN1 Message Slot 10 Extended ID2 (C1MSL10EID2) <Address: H'0080 15A4> I CAN1 Message Slot 11 Extended ID2 (C1MSL11EID2) <Address: H'0080 15B4> I CAN1 Message Slot 12 Extended ID2 (C1MSL12EID2) <Address: H'0080 15C4> I CAN1 Message Slot 13 Extended ID2 (C1MSL13EID2) <Address: H'0080 15D4> I CAN1 Message Slot 14 Extended ID2 (C1MSL14EID2) <Address: H'0080 15E4> I CAN1 Message Slot 15 Extended ID2 (C1MSL15EID2) <Address: H'0080 15F4> CAN MODULES

13-57 Rev.1.0 D 0 123456 D 7 EID12 EID13 EID14 EID15 EID16 EID17 <When reset: indeterminate> D Bit Name Function R W 0,1 No functions assigned 0 – 2-7 EID12-EID17 Extended ID12 to extended ID17 (Extended ID12 to extended ID17) These registers comprise a transmit frame/receive frame memory space. Note: For receive slots whose frame type has been chosen to be the standard ID format, the values written to their EID bits when storing the received data are indeterminate. CAN MODULES

13-58 Rev.1.0 I CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) <Address: H'0080 1105> I CAN0 Message Slot 1 Data Length Register (C0MSL1DLC) <Address: H'0080 1115> I CAN0 Message Slot 2 Data Length Register (C0MSL2DLC) <Address: H'0080 1125> I CAN0 Message Slot 3 Data Length Register (C0MSL3DLC) <Address: H'0080 1135> I CAN0 Message Slot 4 Data Length Register (C0MSL4DLC) <Address: H'0080 1145> I CAN0 Message Slot 5 Data Length Register (C0MSL5DLC) <Address: H'0080 1155> I CAN0 Message Slot 6 Data Length Register (C0MSL6DLC) <Address: H'0080 1165> I CAN0 Message Slot 7 Data Length Register (C0MSL7DLC) <Address: H'0080 1175> I CAN0 Message Slot 8 Data Length Register (C0MSL8DLC) <Address: H'0080 1185> I CAN0 Message Slot 9 Data Length Register (C0MSL9DLC) <Address: H'0080 1195> I CAN0 Message Slot 10 Data Length Register (C0MSL10DLC) <Address: H'0080 11A5> I CAN0 Message Slot 11 Data Length Register (C0MSL11DLC) <Address: H'0080 11B5> I CAN0 Message Slot 12 Data Length Register (C0MSL12DLC) <Address: H'0080 11C5> I CAN0 Message Slot 13 Data Length Register (C0MSL13DLC) <Address: H'0080 11D5> I CAN0 Message Slot 14 Data Length Register (C0MSL14DLC) <Address: H'0080 11E5> I CAN0 Message Slot 15 Data Length Register (C0MSL15DLC) <Address: H'0080 11F5> I CAN1 Message Slot 0 Data Length Register (C1MSL0DLC) <Address: H'0080 1505> I CAN1 Message Slot 1 Data Length Register (C1MSL1DLC) <Address: H'0080 1515> I CAN1 Message Slot 2 Data Length Register (C1MSL2DLC) <Address: H'0080 1525> I CAN1 Message Slot 3 Data Length Register (C1MSL3DLC) <Address: H'0080 1535> I CAN1 Message Slot 4 Data Length Register (C1MSL4DLC) <Address: H'0080 1545> I CAN1 Message Slot 5 Data Length Register (C1MSL5DLC) <Address: H'0080 1555> I CAN1 Message Slot 6 Data Length Register (C1MSL6DLC) <Address: H'0080 1565> I CAN1 Message Slot 7 Data Length Register (C1MSL7DLC) <Address: H'0080 1575> I CAN1 Message Slot 8 Data Length Register (C1MSL8DLC) <Address: H'0080 1585> I CAN1 Message Slot 9 Data Length Register (C1MSL9DLC) <Address: H'0080 1595> I CAN1 Message Slot 10 Data Length Register (C1MSL10DLC) <Address: H'0080 15A5> I CAN1 Message Slot 11 Data Length Register (C1MSL11DLC) <Address: H'0080 15B5> I CAN1 Message Slot 12 Data Length Register (C1MSL12DLC) <Address: H'0080 15C5> I CAN1 Message Slot 13 Data Length Register (C1MSL13DLC) <Address: H'0080 15D5> I CAN1 Message Slot 14 Data Length Register (C1MSL14DLC) <Address: H'0080 15E5> I CAN1 Message Slot 15 Data Length Register (C1MSL15DLC) <Address: H'0080 15F5> CAN MODULES

13-59 Rev.1.0 D 8 9 1 01 11 21 31 4 D 1 5 DLC0 DLC1 DLC2 DLC3 <When reset: indeterminate> D Bit Name Function R W 8-11 No functions assigned 0 – 12-15 DLC0-DLC3 0 0 0 0 : 0 byte (Set data length) 0 0 0 1 : 1 byte 0 0 1 0 : 2 byte 0 0 1 1 : 3 byte 0 1 0 0 : 4 byte 0 1 0 1 : 5 byte 0 1 1 0 : 6 byte 0 1 1 1 : 7 byte 1 × × × : 8 byte These registers comprise a transmit frame/receive frame memory space. When transmitting, these registers are used to set the transmit data length. When receiving, the receive DLC is stored in these registers. CAN MODULES

13-60 Rev.1.0 I CAN0 Message Slot 0 Data 0 (C0MSL0DT0) <Address: H'0080 1106> I CAN0 Message Slot 1 Data 0 (C0MSL1DT0) <Address: H'0080 1116> I CAN0 Message Slot 2 Data 0 (C0MSL2DT0) <Address: H'0080 1126> I CAN0 Message Slot 3 Data 0 (C0MSL3DT0) <Address: H'0080 1136> I CAN0 Message Slot 4 Data 0 (C0MSL4DT0) <Address: H'0080 1146> I CAN0 Message Slot 5 Data 0 (C0MSL5DT0) <Address: H'0080 1156> I CAN0 Message Slot 6 Data 0 (C0MSL6DT0) <Address: H'0080 1166> I CAN0 Message Slot 7 Data 0 (C0MSL7DT0) <Address: H'0080 1176> I CAN0 Message Slot 8 Data 0 (C0MSL8DT0) <Address: H'0080 1186> I CAN0 Message Slot 9 Data 0 (C0MSL9DT0) <Address: H'0080 1196> I CAN0 Message Slot 10 Data 0 (C0MSL10DT0) <Address: H'0080 11A6> I CAN0 Message Slot 11 Data 0 (C0MSL11DT0) <Address: H'0080 11B6> I CAN0 Message Slot 12 Data 0 (C0MSL12DT0) <Address: H'0080 11C6> I CAN0 Message Slot 13 Data 0 (C0MSL13DT0) <Address: H'0080 11D6> I CAN0 Message Slot 14 Data 0 (C0MSL14DT0) <Address: H'0080 11E6> I CAN0 Message Slot 15 Data 0 (C0MSL15DT0) <Address: H'0080 11F6> I CAN1 Message Slot 0 Data 0 (C1MSL0DT0) <Address: H'0080 1506> I CAN1 Message Slot 1 Data 0 (C1MSL1DT0) <Address: H'0080 1516> I CAN1 Message Slot 2 Data 0 (C1MSL2DT0) <Address: H'0080 1526> I CAN1 Message Slot 3 Data 0 (C1MSL3DT0) <Address: H'0080 1536> I CAN1 Message Slot 4 Data 0 (C1MSL4DT0) <Address: H'0080 1546> I CAN1 Message Slot 5 Data 0 (C1MSL5DT0) <Address: H'0080 1556> I CAN1 Message Slot 6 Data 0 (C1MSL6DT0) <Address: H'0080 1566> I CAN1 Message Slot 7 Data 0 (C1MSL7DT0) <Address: H'0080 1576> I CAN1 Message Slot 8 Data 0 (C1MSL8DT0) <Address: H'0080 1586> I CAN1 Message Slot 9 Data 0 (C1MSL9DT0) <Address: H'0080 1596> I CAN1 Message Slot 10 Data 0 (C1MSL10DT0) <Address: H'0080 15A6> I CAN1 Message Slot 11 Data 0 (C1MSL11DT0) <Address: H'0080 15B6> I CAN1 Message Slot 12 Data 0 (C1MSL12DT0) <Address: H'0080 15C6> I CAN1 Message Slot 13 Data 0 (C1MSL13DT0) <Address: H'0080 15D6> I CAN1 Message Slot 14 Data 0 (C1MSL14DT0) <Address: H'0080 15E6> I CAN1 Message Slot 15 Data 0 (C1MSL15DT0) <Address: H'0080 15F6> CAN MODULES

13-61 Rev.1.0 D 0 123456 D 7 CMSLnDT0 <When reset: indeterminate> D Bit Name Function R W 0-7 CMSLnDT0 Message slot n data 0 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note 1: For receive slots, if the data length (DLC value) = 0 when storing a data frame, an indeterminate value is written to the register. Note 2: The first byte in the CAN frame data field corresponds to message slot n data 0. The data is transmitted and received beginning with the MSB side of the register. CAN MODULES

13-62 Rev.1.0 I CAN0 Message Slot 0 Data 1 (C0MSL0DT1) <Address: H'0080 1107> I CAN0 Message Slot 1 Data 1 (C0MSL1DT1) <Address: H'0080 1117> I CAN0 Message Slot 2 Data 1 (C0MSL2DT1) <Address: H'0080 1127> I CAN0 Message Slot 3 Data 1 (C0MSL3DT1) <Address: H'0080 1137> I CAN0 Message Slot 4 Data 1 (C0MSL4DT1) <Address: H'0080 1147> I CAN0 Message Slot 5 Data 1 (C0MSL5DT1) <Address: H'0080 1157> I CAN0 Message Slot 6 Data 1 (C0MSL6DT1) <Address: H'0080 1167> I CAN0 Message Slot 7 Data 1 (C0MSL7DT1) <Address: H'0080 1177> I CAN0 Message Slot 8 Data 1 (C0MSL8DT1) <Address: H'0080 1187> I CAN0 Message Slot 9 Data 1 (C0MSL9DT1) <Address: H'0080 1197> I CAN0 Message Slot 10 Data 1 (C0MSL10DT1) <Address: H'0080 11A7> I CAN0 Message Slot 11 Data 1 (C0MSL11DT1) <Address: H'0080 11B7> I CAN0 Message Slot 12 Data 1 (C0MSL12DT1) <Address: H'0080 11C7> I CAN0 Message Slot 13 Data 1 (C0MSL13DT1) <Address: H'0080 11D7> I CAN0 Message Slot 14 Data 1 (C0MSL14DT1) <Address: H'0080 11E7> I CAN0 Message Slot 15 Data 1 (C0MSL15DT1) <Address: H'0080 11F7> I CAN1 Message Slot 0 Data 1 (C1MSL0DT1) <Address: H'0080 1507> I CAN1 Message Slot 1 Data 1 (C1MSL1DT1) <Address: H'0080 1517> I CAN1 Message Slot 2 Data 1 (C1MSL2DT1) <Address: H'0080 1527> I CAN1 Message Slot 3 Data 1 (C1MSL3DT1) <Address: H'0080 1537> I CAN1 Message Slot 4 Data 1 (C1MSL4DT1) <Address: H'0080 1547> I CAN1 Message Slot 5 Data 1 (C1MSL5DT1) <Address: H'0080 1557> I CAN1 Message Slot 6 Data 1 (C1MSL6DT1) <Address: H'0080 1567> I CAN1 Message Slot 7 Data 1 (C1MSL7DT1) <Address: H'0080 1577> I CAN1 Message Slot 8 Data 1 (C1MSL8DT1) <Address: H'0080 1587> I CAN1 Message Slot 9 Data 1 (C1MSL9DT1) <Address: H'0080 1597> I CAN1 Message Slot 10 Data 1 (C1MSL10DT1) <Address: H'0080 15A7> I CAN1 Message Slot 11 Data 1 (C1MSL11DT1) <Address: H'0080 15B7> I CAN1 Message Slot 12 Data 1 (C1MSL12DT1) <Address: H'0080 15C7> I CAN1 Message Slot 13 Data 1 (C1MSL13DT1) <Address: H'0080 15D7> I CAN1 Message Slot 14 Data 1 (C1MSL14DT1) <Address: H'0080 15E7> I CAN1 Message Slot 15 Data 1 (C1MSL15DT1) <Address: H'0080 15F7> CAN MODULES

13-63 Rev.1.0 D 8 9 1 01 11 21 31 4 D 1 5 CMSLnDT1 <When reset: indeterminate> D Bit Name Function R W 8-15 CMSLnDT1 Message slot n data 1 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 1 or less when storing a data frame, an indeterminate value is written to the register. CAN MODULES

13-64 Rev.1.0 I CAN0 Message Slot 0 Data 2 (C0MSL0DT2) <Address: H'0080 1108> I CAN0 Message Slot 1 Data 2 (C0MSL1DT2) <Address: H'0080 1118> I CAN0 Message Slot 2 Data 2 (C0MSL2DT2) <Address: H'0080 1128> I CAN0 Message Slot 3 Data 2 (C0MSL3DT2) <Address: H'0080 1138> I CAN0 Message Slot 4 Data 2 (C0MSL4DT2) <Address: H'0080 1148> I CAN0 Message Slot 5 Data 2 (C0MSL5DT2) <Address: H'0080 1158> I CAN0 Message Slot 6 Data 2 (C0MSL6DT2) <Address: H'0080 1168> I CAN0 Message Slot 7 Data 2 (C0MSL7DT2) <Address: H'0080 1178> I CAN0 Message Slot 8 Data 2 (C0MSL8DT2) <Address: H'0080 1188> I CAN0 Message Slot 9 Data 2 (C0MSL9DT2) <Address: H'0080 1198> I CAN0 Message Slot 10 Data 2 (C0MSL10DT2) <Address: H'0080 11A8> I CAN0 Message Slot 11 Data 2 (C0MSL11DT2) <Address: H'0080 11B8> I CAN0 Message Slot 12 Data 2 (C0MSL12DT2) <Address: H'0080 11C8> I CAN0 Message Slot 13 Data 2 (C0MSL13DT2) <Address: H'0080 11D8> I CAN0 Message Slot 14 Data 2 (C0MSL14DT2) <Address: H'0080 11E8> I CAN0 Message Slot 15 Data 2 (C0MSL15DT2) <Address: H'0080 11F8> I CAN1 Message Slot 0 Data 2 (C1MSL0DT2) <Address: H'0080 1508> I CAN1 Message Slot 1 Data 2 (C1MSL1DT2) <Address: H'0080 1518> I CAN1 Message Slot 2 Data 2 (C1MSL2DT2) <Address: H'0080 1528> I CAN1 Message Slot 3 Data 2 (C1MSL3DT2) <Address: H'0080 1538> I CAN1 Message Slot 4 Data 2 (C1MSL4DT2) <Address: H'0080 1548> I CAN1 Message Slot 5 Data 2 (C1MSL5DT2) <Address: H'0080 1558> I CAN1 Message Slot 6 Data 2 (C1MSL6DT2) <Address: H'0080 1568> I CAN1 Message Slot 7 Data 2 (C1MSL7DT2) <Address: H'0080 1578> I CAN1 Message Slot 8 Data 2 (C1MSL8DT2) <Address: H'0080 1588> I CAN1 Message Slot 9 Data 2 (C1MSL9DT2) <Address: H'0080 1598> I CAN1 Message Slot 10 Data 2 (C1MSL10DT2) <Address: H'0080 15A8> I CAN1 Message Slot 11 Data 2 (C1MSL11DT2) <Address: H'0080 15B8> I CAN1 Message Slot 12 Data 2 (C1MSL12DT2) <Address: H'0080 15C8> I CAN1 Message Slot 13 Data 2 (C1MSL13DT2) <Address: H'0080 15D8> I CAN1 Message Slot 14 Data 2 (C1MSL14DT2) <Address: H'0080 15E8> I CAN1 Message Slot 15 Data 2 (C1MSL15DT2) <Address: H'0080 15F8> CAN MODULES

13-65 Rev.1.0 D 0 123456 D 7 CMSLnDT2 <When reset: indeterminate> D Bit Name Function R W 0-7 CMSLnDT2 Message slot n data 2 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 2 or less when storing a data frame, an indeterminate value is written to the register. CAN MODULES

13-66 Rev.1.0 I CAN0 Message Slot 0 Data 3 (C0MSL0DT3) <Address: H'0080 1109> I CAN0 Message Slot 1 Data 3 (C0MSL1DT3) <Address: H'0080 1119> I CAN0 Message Slot 2 Data 3 (C0MSL2DT3) <Address: H'0080 1129> I CAN0 Message Slot 3 Data 3 (C0MSL3DT3) <Address: H'0080 1139> I CAN0 Message Slot 4 Data 3 (C0MSL4DT3) <Address: H'0080 1149> I CAN0 Message Slot 5 Data 3 (C0MSL5DT3) <Address: H'0080 1159> I CAN0 Message Slot 6 Data 3 (C0MSL6DT3) <Address: H'0080 1169> I CAN0 Message Slot 7 Data 3 (C0MSL7DT3) <Address: H'0080 1179> I CAN0 Message Slot 8 Data 3 (C0MSL8DT3) <Address: H'0080 1189> I CAN0 Message Slot 9 Data 3 (C0MSL9DT3) <Address: H'0080 1199> I CAN0 Message Slot 10 Data 3 (C0MSL10DT3) <Address: H'0080 11A9> I CAN0 Message Slot 11 Data 3 (C0MSL11DT3) <Address: H'0080 11B9> I CAN0 Message Slot 12 Data 3 (C0MSL12DT3) <Address: H'0080 11C9> I CAN0 Message Slot 13 Data 3 (C0MSL13DT3) <Address: H'0080 11D9> I CAN0 Message Slot 14 Data 3 (C0MSL14DT3) <Address: H'0080 11E9> I CAN0 Message Slot 15 Data 3 (C0MSL15DT3) <Address: H'0080 11F9> I CAN1 Message Slot 0 Data 3 (C1MSL0DT3) <Address: H'0080 1509> I CAN1 Message Slot 1 Data 3 (C1MSL1DT3) <Address: H'0080 1519> I CAN1 Message Slot 2 Data 3 (C1MSL2DT3) <Address: H'0080 1529> I CAN1 Message Slot 3 Data 3 (C1MSL3DT3) <Address: H'0080 1539> I CAN1 Message Slot 4 Data 3 (C1MSL4DT3) <Address: H'0080 1549> I CAN1 Message Slot 5 Data 3 (C1MSL5DT3) <Address: H'0080 1559> I CAN1 Message Slot 6 Data 3 (C1MSL6DT3) <Address: H'0080 1569> I CAN1 Message Slot 7 Data 3 (C1MSL7DT3) <Address: H'0080 1579> I CAN1 Message Slot 8 Data 3 (C1MSL8DT3) <Address: H'0080 1589> I CAN1 Message Slot 9 Data 3 (C1MSL9DT3) <Address: H'0080 1599> I CAN1 Message Slot 10 Data 3 (C1MSL10DT3) <Address: H'0080 15A9> I CAN1 Message Slot 11 Data 3 (C1MSL11DT3) <Address: H'0080 15B9> I CAN1 Message Slot 12 Data 3 (C1MSL12DT3) <Address: H'0080 15C9> I CAN1 Message Slot 13 Data 3 (C1MSL13DT3) <Address: H'0080 15D9> I CAN1 Message Slot 14 Data 3 (C1MSL14DT3) <Address: H'0080 15E9> I CAN1 Message Slot 15 Data 3 (C1MSL15DT3) <Address: H'0080 15F9> CAN MODULES

13-67 Rev.1.0 D 8 9 1 01 11 21 31 4 D 1 5 CMSLnDT3 <When reset: indeterminate> D Bit Name Function R W 8-15 CMSLnDT3 Message slot n data 3 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 3 or less when storing a data frame, an indeterminate value is written to the register. CAN MODULES

13-68 Rev.1.0 I CAN0 Message Slot 0 Data 4 (C0MSL0DT4) <Address: H'0080 110A> I CAN0 Message Slot 1 Data 4 (C0MSL1DT4) <Address: H'0080 111A> I CAN0 Message Slot 2 Data 4 (C0MSL2DT4) <Address: H'0080 112A> I CAN0 Message Slot 3 Data 4 (C0MSL3DT4) <Address: H'0080 113A> I CAN0 Message Slot 4 Data 4 (C0MSL4DT4) <Address: H'0080 114A> I CAN0 Message Slot 5 Data 4 (C0MSL5DT4) <Address: H'0080 115A> I CAN0 Message Slot 6 Data 4 (C0MSL6DT4) <Address: H'0080 116A> I CAN0 Message Slot 7 Data 4 (C0MSL7DT4) <Address: H'0080 117A> I CAN0 Message Slot 8 Data 4 (C0MSL8DT4) <Address: H'0080 118A> I CAN0 Message Slot 9 Data 4 (C0MSL9DT4) <Address: H'0080 119A> I CAN0 Message Slot 10 Data 4 (C0MSL10DT4) <Address: H'0080 11AA> I CAN0 Message Slot 11 Data 4 (C0MSL11DT4) <Address: H'0080 11BA> I CAN0 Message Slot 12 Data 4 (C0MSL12DT4) <Address: H'0080 11CA> I CAN0 Message Slot 13 Data 4 (C0MSL13DT4) <Address: H'0080 11DA> I CAN0 Message Slot 14 Data 4 (C0MSL14DT4) <Address: H'0080 11EA> I CAN0 Message Slot 15 Data 4 (C0MSL15DT4) <Address: H'0080 11FA> I CAN1 Message Slot 0 Data 4 (C1MSL0DT4) <Address: H'0080 150A> I CAN1 Message Slot 1 Data 4 (C1MSL1DT4) <Address: H'0080 151A> I CAN1 Message Slot 2 Data 4 (C1MSL2DT4) <Address: H'0080 152A> I CAN1 Message Slot 3 Data 4 (C1MSL3DT4) <Address: H'0080 153A> I CAN1 Message Slot 4 Data 4 (C1MSL4DT4) <Address: H'0080 154A> I CAN1 Message Slot 5 Data 4 (C1MSL5DT4) <Address: H'0080 155A> I CAN1 Message Slot 6 Data 4 (C1MSL6DT4) <Address: H'0080 156A> I CAN1 Message Slot 7 Data 4 (C1MSL7DT4) <Address: H'0080 157A> I CAN1 Message Slot 8 Data 4 (C1MSL8DT4) <Address: H'0080 158A> I CAN1 Message Slot 9 Data 4 (C1MSL9DT4) <Address: H'0080 159A> I CAN1 Message Slot 10 Data 4 (C1MSL10DT4) <Address: H'0080 15AA> I CAN1 Message Slot 11 Data 4 (C1MSL11DT4) <Address: H'0080 15BA> I CAN1 Message Slot 12 Data 4 (C1MSL12DT4) <Address: H'0080 15CA> I CAN1 Message Slot 13 Data 4 (C1MSL13DT4) <Address: H'0080 15DA> I CAN1 Message Slot 14 Data 4 (C1MSL14DT4) <Address: H'0080 15EA> I CAN1 Message Slot 15 Data 4 (C1MSL15DT4) <Address: H'0080 15FA> CAN MODULES

13-69 Rev.1.0 D 0 123456 D 7 CMSLnDT4 <When reset: indeterminate> D Bit Name Function R W 0-7 CMSLnDT4 Message slot n data 4 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 4 or less when storing a data frame, an indeterminate value is written to the register. CAN MODULES

13-70 Rev.1.0 I CAN0 Message Slot 0 Data 5 (C0MSL0DT5) <Address: H'0080 110B> I CAN0 Message Slot 1 Data 5 (C0MSL1DT5) <Address: H'0080 111B> I CAN0 Message Slot 2 Data 5 (C0MSL2DT5) <Address: H'0080 112B> I CAN0 Message Slot 3 Data 5 (C0MSL3DT5) <Address: H'0080 113B> I CAN0 Message Slot 4 Data 5 (C0MSL4DT5) <Address: H'0080 114B> I CAN0 Message Slot 5 Data 5 (C0MSL5DT5) <Address: H'0080 115B> I CAN0 Message Slot 6 Data 5 (C0MSL6DT5) <Address: H'0080 116B> I CAN0 Message Slot 7 Data 5 (C0MSL7DT5) <Address: H'0080 117B> I CAN0 Message Slot 8 Data 5 (C0MSL8DT5) <Address: H'0080 118B> I CAN0 Message Slot 9 Data 5 (C0MSL9DT5) <Address: H'0080 119B> I CAN0 Message Slot 10 Data 5 (C0MSL10DT5) <Address: H'0080 11AB> I CAN0 Message Slot 11 Data 5 (C0MSL11DT5) <Address: H'0080 11BB> I CAN0 Message Slot 12 Data 5 (C0MSL12DT5) <Address: H'0080 11CB> I CAN0 Message Slot 13 Data 5 (C0MSL13DT5) <Address: H'0080 11DB> I CAN0 Message Slot 14 Data 5 (C0MSL14DT5) <Address: H'0080 11EB> I CAN0 Message Slot 15 Data 5 (C0MSL15DT5) <Address: H'0080 11FB> I CAN1 Message Slot 0 Data 5 (C1MSL0DT5) <Address: H'0080 150B> I CAN1 Message Slot 1 Data 5 (C1MSL1DT5) <Address: H'0080 151B> I CAN1 Message Slot 2 Data 5 (C1MSL2DT5) <Address: H'0080 152B> I CAN1 Message Slot 3 Data 5 (C1MSL3DT5) <Address: H'0080 153B> I CAN1 Message Slot 4 Data 5 (C1MSL4DT5) <Address: H'0080 154B> I CAN1 Message Slot 5 Data 5 (C1MSL5DT5) <Address: H'0080 155B> I CAN1 Message Slot 6 Data 5 (C1MSL6DT5) <Address: H'0080 156B> I CAN1 Message Slot 7 Data 5 (C1MSL7DT5) <Address: H'0080 157B> I CAN1 Message Slot 8 Data 5 (C1MSL8DT5) <Address: H'0080 158B> I CAN1 Message Slot 9 Data 5 (C1MSL9DT5) <Address: H'0080 159B> I CAN1 Message Slot 10 Data 5 (C1MSL10DT5) <Address: H'0080 15AB> I CAN1 Message Slot 11 Data 5 (C1MSL11DT5) <Address: H'0080 15BB> I CAN1 Message Slot 12 Data 5 (C1MSL12DT5) <Address: H'0080 15CB> I CAN1 Message Slot 13 Data 5 (C1MSL13DT5) <Address: H'0080 15DB> I CAN1 Message Slot 14 Data 5 (C1MSL14DT5) <Address: H'0080 15EB> I CAN1 Message Slot 15 Data 5 (C1MSL15DT5) <Address: H'0080 15FB> CAN MODULES

13-71 Rev.1.0 D 8 9 1 01 11 21 31 4 D 1 5 CMSLnDT5 <When reset: indeterminate> D Bit Name Function R W 8-15 CMSLnDT5 Message slot n data 5 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 5 or less when storing a data frame, an indeterminate value is written to the register. CAN MODULES

13-72 Rev.1.0 I CAN0 Message Slot 0 Data 6 (C0MSL0DT6) <Address: H'0080 110C> I CAN0 Message Slot 1 Data 6 (C0MSL1DT6) <Address: H'0080 111C> I CAN0 Message Slot 2 Data 6 (C0MSL2DT6) <Address: H'0080 112C> I CAN0 Message Slot 3 Data 6 (C0MSL3DT6) <Address: H'0080 113C> I CAN0 Message Slot 4 Data 6 (C0MSL4DT6) <Address: H'0080 114C> I CAN0 Message Slot 5 Data 6 (C0MSL5DT6) <Address: H'0080 115C> I CAN0 Message Slot 6 Data 6 (C0MSL6DT6) <Address: H'0080 116C> I CAN0 Message Slot 7 Data 6 (C0MSL7DT6) <Address: H'0080 117C> I CAN0 Message Slot 8 Data 6 (C0MSL8DT6) <Address: H'0080 118C> I CAN0 Message Slot 9 Data 6 (C0MSL9DT6) <Address: H'0080 119C> I CAN0 Message Slot 10 Data 6 (C0MSL10DT6) <Address: H'0080 11AC> I CAN0 Message Slot 11 Data 6 (C0MSL11DT6) <Address: H'0080 11BC> I CAN0 Message Slot 12 Data 6 (C0MSL12DT6) <Address: H'0080 11CC> I CAN0 Message Slot 13 Data 6 (C0MSL13DT6) <Address: H'0080 11DC> I CAN0 Message Slot 14 Data 6 (C0MSL14DT6) <Address: H'0080 11EC> I CAN0 Message Slot 15 Data 6 (C0MSL15DT6) <Address: H'0080 11FC> I CAN1 Message Slot 0 Data 6 (C1MSL0DT6) <Address: H'0080 150C> I CAN1 Message Slot 1 Data 6 (C1MSL1DT6) <Address: H'0080 151C> I CAN1 Message Slot 2 Data 6 (C1MSL2DT6) <Address: H'0080 152C> I CAN1 Message Slot 3 Data 6 (C1MSL3DT6) <Address: H'0080 153C> I CAN1 Message Slot 4 Data 6 (C1MSL4DT6) <Address: H'0080 154C> I CAN1 Message Slot 5 Data 6 (C1MSL5DT6) <Address: H'0080 155C> I CAN1 Message Slot 6 Data 6 (C1MSL6DT6) <Address: H'0080 156C> I CAN1 Message Slot 7 Data 6 (C1MSL7DT6) <Address: H'0080 157C> I CAN1 Message Slot 8 Data 6 (C1MSL8DT6) <Address: H'0080 158C> I CAN1 Message Slot 9 Data 6 (C1MSL9DT6) <Address: H'0080 159C> I CAN1 Message Slot 10 Data 6 (C1MSL10DT6) <Address: H'0080 15AC> I CAN1 Message Slot 11 Data 6 (C1MSL11DT6) <Address: H'0080 15BC> I CAN1 Message Slot 12 Data 6 (C1MSL12DT6) <Address: H'0080 15CC> I CAN1 Message Slot 13 Data 6 (C1MSL13DT6) <Address: H'0080 15DC> I CAN1 Message Slot 14 Data 6 (C1MSL14DT6) <Address: H'0080 15EC> I CAN1 Message Slot 15 Data 6 (C1MSL15DT6) <Address: H'0080 15FC> CAN MODULES

13-73 Rev.1.0 D 0 123456 D 7 CMSLnDT6 <When reset: indeterminate> D Bit Name Function R W 0-7 CMSLnDT6 Message slot n data 6 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 6 or less when storing a data frame, an indeterminate value is written to the register. CAN MODULES

13-74 Rev.1.0 I CAN0 Message Slot 0 Data 7 (C0MSL0DT7) <Address: H'0080 110D> I CAN0 Message Slot 1 Data 7 (C0MSL1DT7) <Address: H'0080 111D> I CAN0 Message Slot 2 Data 7 (C0MSL2DT7) <Address: H'0080 112D> I CAN0 Message Slot 3 Data 7 (C0MSL3DT7) <Address: H'0080 113D> I CAN0 Message Slot 4 Data 7 (C0MSL4DT7) <Address: H'0080 114D> I CAN0 Message Slot 5 Data 7 (C0MSL5DT7) <Address: H'0080 115D> I CAN0 Message Slot 6 Data 7 (C0MSL6DT7) <Address: H'0080 116D> I CAN0 Message Slot 7 Data 7 (C0MSL7DT7) <Address: H'0080 117D> I CAN0 Message Slot 8 Data 7 (C0MSL8DT7) <Address: H'0080 118D> I CAN0 Message Slot 9 Data 7 (C0MSL9DT7) <Address: H'0080 119D> I CAN0 Message Slot 10 Data 7 (C0MSL10DT7) <Address: H'0080 11AD> I CAN0 Message Slot 11 Data 7 (C0MSL11DT7) <Address: H'0080 11BD> I CAN0 Message Slot 12 Data 7 (C0MSL12DT7) <Address: H'0080 11CD> I CAN0 Message Slot 13 Data 7 (C0MSL13DT7) <Address: H'0080 11DD> I CAN0 Message Slot 14 Data 7 (C0MSL14DT7) <Address: H'0080 11ED> I CAN0 Message Slot 15 Data 7 (C0MSL15DT7) <Address: H'0080 11FD> I CAN1 Message Slot 0 Data 7 (C1MSL0DT7) <Address: H'0080 150D> I CAN1 Message Slot 1 Data 7 (C1MSL1DT7) <Address: H'0080 151D> I CAN1 Message Slot 2 Data 7 (C1MSL2DT7) <Address: H'0080 152D> I CAN1 Message Slot 3 Data 7 (C1MSL3DT7) <Address: H'0080 153D> I CAN1 Message Slot 4 Data 7 (C1MSL4DT7) <Address: H'0080 154D> I CAN1 Message Slot 5 Data 7 (C1MSL5DT7) <Address: H'0080 155D> I CAN1 Message Slot 6 Data 7 (C1MSL6DT7) <Address: H'0080 156D> I CAN1 Message Slot 7 Data 7 (C1MSL7DT7) <Address: H'0080 157D> I CAN1 Message Slot 8 Data 7 (C1MSL8DT7) <Address: H'0080 158D> I CAN1 Message Slot 9 Data 7 (C1MSL9DT7) <Address: H'0080 159D> I CAN1 Message Slot 10 Data 7 (C1MSL10DT7) <Address: H'0080 15AD> I CAN1 Message Slot 11 Data 7 (C1MSL11DT7) <Address: H'0080 15BD> I CAN1 Message Slot 12 Data 7 (C1MSL12DT7) <Address: H'0080 15CD> I CAN1 Message Slot 13 Data 7 (C1MSL13DT7) <Address: H'0080 15DD> I CAN1 Message Slot 14 Data 7 (C1MSL14DT7) <Address: H'0080 15ED> I CAN1 Message Slot 15 Data 7 (C1MSL15DT7) <Address: H'0080 15FD> CAN MODULES

13-75 Rev.1.0 D 8 9 1 01 11 21 31 4 D 1 5 CMSLnDT7 <When reset: indeterminate> D Bit Name Function R W 0-7 CMSLnDT7 Message slot n data 7 n = 0-15 These registers comprise a transmit frame/receive frame memory space. Note: For receive slots, if the data length (DLC value) = 7 or less when storing a data frame, an indeterminate value is written to the register. CAN MODULES

13-76 Rev.1.0 I CAN0 Message Slot 0 Time stamp (C0MSL0TSP) <Address: H'0080 110E> I CAN0 Message Slot 1 Time stamp (C0MSL1TSP) <Address: H'0080 111E> I CAN0 Message Slot 2 Time stamp (C0MSL2TSP) <Address: H'0080 112E> I CAN0 Message Slot 3 Time stamp (C0MSL3TSP) <Address: H'0080 113E> I CAN0 Message Slot 4 Time stamp (C0MSL4TSP) <Address: H'0080 114E> I CAN0 Message Slot 5 Time stamp (C0MSL5TSP) <Address: H'0080 115E> I CAN0 Message Slot 6 Time stamp (C0MSL6TSP) <Address: H'0080 116E> I CAN0 Message Slot 7 Time stamp (C0MSL7TSP) <Address: H'0080 117E> I CAN0 Message Slot 8 Time stamp (C0MSL8TSP) <Address: H'0080 118E> I CAN0 Message Slot 9 Time stamp (C0MSL9TSP) <Address: H'0080 119E> I CAN0 Message Slot 10 Time stamp (C0MSL10TSP) <Address: H'0080 11AE> I CAN0 Message Slot 11 Time stamp (C0MSL11TSP) <Address: H'0080 11BE> I CAN0 Message Slot 12 Time stamp (C0MSL12TSP) <Address: H'0080 11CE> I CAN0 Message Slot 13 Time stamp (C0MSL13TSP) <Address: H'0080 11DE> I CAN0 Message Slot 14 Time stamp (C0MSL14TSP) <Address: H'0080 11EE> I CAN0 Message Slot 15 Time stamp (C0MSL15TSP) <Address: H'0080 11FE> I CAN1 Message Slot 0 Time stamp (C1MSL0TSP) <Address: H'0080 150E> I CAN1 Message Slot 1 Time stamp (C1MSL1TSP) <Address: H'0080 151E> I CAN1 Message Slot 2 Time stamp (C1MSL2TSP) <Address: H'0080 152E> I CAN1 Message Slot 3 Time stamp (C1MSL3TSP) <Address: H'0080 153E> I CAN1 Message Slot 4 Time stamp (C1MSL4TSP) <Address: H'0080 154E> I CAN1 Message Slot 5 Time stamp (C1MSL5TSP) <Address: H'0080 155E> I CAN1 Message Slot 6 Time stamp (C1MSL6TSP) <Address: H'0080 156E> I CAN1 Message Slot 7 Time stamp (C1MSL7TSP) <Address: H'0080 157E> I CAN1 Message Slot 8 Time stamp (C1MSL8TSP) <Address: H'0080 158E> I CAN1 Message Slot 9 Time stamp (C1MSL9TSP) <Address: H'0080 159E> I CAN1 Message Slot 10 Time stamp (C1MSL10TSP) <Address: H'0080 15AE> I CAN1 Message Slot 11 Time stamp (C1MSL11TSP) <Address: H'0080 15BE> I CAN1 Message Slot 12 Time stamp (C1MSL12TSP) <Address: H'0080 15CE> I CAN1 Message Slot 13 Time stamp (C1MSL13TSP) <Address: H'0080 15DE> I CAN1 Message Slot 14 Time stamp (C1MSL14TSP) <Address: H'0080 15EE> I CAN1 Message Slot 15 Time stamp (C1MSL15TSP) <Address: H'0080 15FE> CAN MODULES

13-77 Rev.1.0 D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 CMSLnTSP <When reset: indeterminate> D Bit Name Function R W 0-15 CMSLnTSP Message slot n time stamp n = 0-15 These registers comprise a transmit frame/receive frame memory space. When transmission/ reception is completed, the value of the CAN Time stamp Count Register is stored in this register. CAN MODULES

13-78 Rev.1.0

13.3.1 CAN Protocol Frames

Following four types of frames are handled by CAN protocol: (1) Data frame (2) Remote frame (3) Error frame (4) Overload frame Each frame is separated by an interframe space. SOF Arbitration field Control field Data field CRC field ACK field EOF 11 1 6 0~64 16 2 7 11 1 1 1 18 6 0~64 16 2 7 SOF Arbitration field Control field CRC field ACK field EOF 11 1 6 16 2 7 11 1 1 1 18 6 16 2 7 Data frame Remote frame Standard format Standard format Extended format The digit in each field denotes the number of bits. Extended format Figure 13.3.1 CAN Protocol Frames (1) CAN MODULES

13-79 Rev.1.0 Error flag Error delimiter Interframe space or overload flag 6~12 8 Overload flag Overload delimiter 6~12 8 Interframe space or overload flag Error frame Overload frame Interfame space Intermission Bus idle SOF of the next frame For error-active state 3 0~ Suspend transmission For error-passive state 3 8 0~ SOF of the next frame Bus idle Intermission The digit in each field denotes the number of bits. Figure 13.3.2 CAN Protocol Frames (2) CAN MODULES

13-80 Rev.1.0 Transmit error counter > 255 Transmit error counter ≥ 128 or Receive error counter ≥ 128 Transmit error counter < 128 and Receive error counter < 128 11 consecutive recessive bits detected on CAN bus 128 times or reset in software Error-active state Error-passive state Bus-off state Initial setting Figure 13.3.3 CAN Controller Error Status The CAN Controller assumes one of the following three error states depending on the Transmit Error Counter and Receive Error Counter values. (1) Error-active state

• This state is assumed when almost no errors have occurred.
• When an error is detected, the CAN Controller sends an active-error flag.
• The CAN Controller is in this state immediately after initialization. (2) Error-passive state
• This state is assumed when many errors have occurred.
• When an error is detected, the CAN Controller sends a passive-error flag. (3) Bus-off state
• This state is assumed when a large number of errors have occurred.
• The CAN module cannot communicate with any other node until it returns to an active-error state. CAN MODULES

Status of Unit Error Transmit Error Counter Receive Error Counter Error-active state 0-127 and 0-127 Error-passive state 128-255 or 128 and over Bus-off state 256 and over –

13-81 Rev.1.0

13.4 Initialization of the CAN Module

13.4.1 Initializing the CAN Module

Before performing communication, set up the CAN module following the procedure described below. (1) Selecting pin functions The CAN transmit data output pins (CTX0 and CTX1) are shared with input/output ports performing dual functions. Therefore, select the function of these pins. (See Chapter 8, "Input/ Output Ports and Pin Functions.") (2) Setting the Interrupt Controller (ICU) When using CAN module interrupts, set their interrupt priority level with the Interrupt Controller. (3) Setting the CAN Error Interrupt Mask and CAN Slot Interrupt Mask Registers When using CAN bus-error, CAN error-passive, or CAN bus-off interrupts or CAN slot interrupt, enable the desired interrupt requests by setting the corresponding mask bits to 1. (4) Setting the bit timing and sampling times Using the CAN Configuration Register and CAN Baud Rate Prescaler, set the bit timing and the number of times the CAN bus is sampled. ➀ Setting the bit timing Determine the period Tq that constitutes the basis of bit timing, as well as the configuration of Propagation Segment, Phase Segment1, and Phase Segment2, and reSynchronization Jump Width. Tq = (CANBRP + 1) / CPU clock The baud rate is determined depending on the number of Tq's that comprise one bit. The baud rate is calculated by the equation below Baud rate (bps) = Tq period x number of Tq's in one bit Number of Tq's in one bit = Synchronization Segment + Propagation Segment + Phase Segment 1 + Phase Segment 2 CAN MODULES

13-82 Rev.1.0 ➁ Setting the number of sampling times Select the number of times the CAN bus is sampled. This can be chosen to "sample once" or "sample three times."

• When chosen to sample once, the value sampled at the end of Phase Segment1 is assumed to be the value of the bit.
• When chosen to sample three times, the bus is sampled at three points-the first sampling point and 1 Tq and 2 Tq's before that, and the sampled values are resolved by majority logic to determine the value of the bit. (5) Setting the ID Mask Registers Set values in the ID mask registers used in acceptance filtering of the received message (Global Mask Register and Local Mask Registers A and B). (6) Settings when operating in BasicCAN mode
• Set the CAN Extended ID Register IDE14 and IDE15 bits. (Setting the same value for both is recommended.)
• Set the ID in message slots 14 and 15.
• Set the Message Control Registers 14 and 15 to receive a data frame (H'40). (7) Setting CAN module operation mode Using the CAN Control Register (CANCNT), select operation mode of the CAN module (BasicCAN or loopback mode) and the clock source for the time stamp counter. (8) Releasing the CAN module from reset After initial settings in (1) through (7) above, clear the CAN Control Register (CANCNT)'s forcible reset (FRST) and reset (RST) bits to 0. Then, after detecting 11 consecutive recessive bits on the CAN bus, the CAN module becomes ready to communicate. Synchronization Segment Propagation Segment Phase Segment1 Phase Segment2 (1)(2)(3) Sampling Point 1Tq

1 Bit

• This diagram shows bit timing when one bit is comprised of 8 Tq's.
• When chosen to sample once, the value sampled at Sampling Point (1) is assumed to be the value of the bit.
• When chosen to sample three times, the CAN bus values sampled at Sampling Points (1), (2), and (3) are resolved by majority logic to determine the value of the bit. Figure 13.4.1 Example of Bit Timing CAN MODULES

13-83 Rev.1.0 CAN module initialization Set input/output port operation mode register Set interrupt controller Set CAN related interrupt mask registers Set CAN configuration register Set ID mask registers Set CAN operation mode Negate CAN reset CAN module initialization completed Set interrupt priority level

• Set bit timing (baud rate)
• Set sampling times Set ID mask bit Settings of CAN error interrupt mask registers
• Enable/disable CAN bus-error interrupt
• Enable/disable CAN error-passive interrupt
• Enable/disable CAN bus-off interrupt Settings of CAN slot interrupt mask registers
• Enable/disable transmit/receive- complete interrupt for each slot Settings for loopback mode Settings for BasicCAN mode
• Set CAN extended ID register
• Set ID in message slots 14 and 15
• Set message slot control registers Release CAN mode from reset
• Clear CAN control register (CANCNT) FRST and RST bits Figure 13.4.2 CAN Module Initialization CAN MODULES

13-84 Rev.1.0

13.4.2 CAN Timing

The CAN modules incorporated in the M32R/E sample the asynchronous input signal on the CRX pin with a Tq clock period that is the base clock. The sampled signal is assumed to be the CAN bus value. Operation timing is shown below. 1Tq Timing delay of maximum 1 Tq Internal Tq signal CRX pin Internal CRX signal Figure 13.4.3 Operation Timing CAN MODULES

13-85 Rev.1.0

13.5.1 Data Frame Transmission Procedure

The following shows the procedure for transmitting a data frame. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the message slot from which to transmit by writing H'00 to the register. (2) Verifying that transmission is idle Read the initialized CAN Message Slot Control Register and inspect the TRSTAT (transmit/ receive status) bit to see that transmission has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot. Therefore, wait until the bit is cleared to 0. (3) Setting transmit data Set the transmit ID and transmit data in the message slot. (4) Setting the extended ID register Set the extended ID register's corresponding bit to 0 when the data needs to be transmitted as a standard frame or 1 when the data needs to be transmitted as an extension frame. (5) Setting the CAN Message Slot Control Register Set the CAN Message Slot Control Register TR (transmit request) bit to 1 by writing H'80(Note) to the register. Note: When transmitting a data frame, always be sure to write H'80 to this register. CAN MODULES

13-86 Rev.1.0 Data frame transmission procedure Initialize CAN message slot control register Set ID and data in message slot Set extended ID register Set CAN message slot control register Settings completed Write H'00 Standard ID or extended ID Write H'80 (transmit request) Read CAN message slot control registerTRSTAT bit = 0 YES NO Verify that transmission is idle Figure 13.5.1 Procedure for Transmitting a Data Frame CAN MODULES

13-87 Rev.1.0

13.5.2 Data Frame Transmit Operation

The following describes how data frame transmit operation is performed. All these operations are automatically performed in hardware. (1) Selecting a transmit frame The CAN module checks slots for which there is a transmit request (including remote frame transmit slots) every intermission to determine the frame to transmit. If multiple transmit slots exist, frames are transmitted beginning with the slot that has the smallest slot number. (2) Transmitting a data frame When the transmit slot is determined, the CAN module starts transmitting the data frame from the slot after setting its corresponding CAN Message Slot Control Register's TRSTAT (transmit/ receive status) bit to 1. (3) If failed in CAN bus arbitration or a CAN bus error occurs If the CAN module loses in CAN bus arbitration or encounters a CAN bus error in the middle of transmission, it clears the CAN Message Slot Control Register's TRSTAT (transmit/receive status) bit to 0. If the transmit abort function for the slot has been enabled, the transmit abort request is accepted and the message slot is freed, allowing for write to the slot. (4) Completing data frame transmission When the CAN module finishes transmitting the data frame, the CAN Message Slot Control Register's TRFIN (transmit/receive finished) bit and the CAN Slot Interrupt Status Register are set to 1. Also, the time stamp count value at completion of transmission is written to the CAN Message Slot Time stamp Register (CMSLnTSP), thereby completing the transmit operation. If CAN slot interrupt has been enabled, an interrupt is generated upon completion of the transmit operation. The slot which has had transmission completed becomes inactive and remains idle until new settings are made for it in software. CAN MODULES

13-88 Rev.1.0 B'1000 0010 B'0000 0001 (Note) B'1000 0001 B'0000 0000 (Note) B'1000 0000 Write H'80 Transmit abort Accept transmit request Note: When in this state, the message slot can be accessed for write. Transmit abort Failed in arbitration or CAN bus error occursAccept transmit request Transmit abort Finish transmitting Transm it abort Finish transm itting Transmit wait state B'0000 0010 Failed in arbitration or CAN bus error occurs Figure 13.5.2 Operation of the CAN Message Slot Control Register during Data Frame Transmission

13.5.3 Transmit Abort Function

The transmit abort function is used to cancel a transmit request that has once been set. This is accomplished by writing H'0F to the CAN Message Slot Control Register for the slot whose transmit request is to be canceled. When transmit abort is accepted, the CAN module clears the CAN Message Slot Control Register TRSTAT (transmit/receive status) bit to 0, with the message slot thereby allowed for write. The following lists the conditions under which transmit abort is accepted. [Conditions]

• When the target message is waiting for transmission
• When a CAN bus error occurs during transmission
• When the CAN module loses in bus arbitration CAN MODULES

13-89 Rev.1.0

13.6.1 Data Frame Reception Procedure

The following describes the procedure for receiving a data frame. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the message slot in which to receive by writing H'00 to the register. (2) Verifying that reception is idle Read the initialized CAN Message Slot Control Register and inspect the TRSTAT (transmit/ receive status) bit to see that reception has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot. Therefore, wait until the bit is cleared to 0. (3) Setting the ID Set the ID desired to be received in the message slot. (4) Setting the extended ID register Set the extended ID register's corresponding bit to 0 when it is desired to receive a standard frame or 1 when it is desired to receive an extension frame. (5) Setting the CAN Message Slot Control Register Set the CAN Message Slot Control Register RR (receive request) bit to 1 by writing H'40 to the register. CAN MODULES

13-90 Rev.1.0 Data frame reception procedure Initialize CAN message slot control register Set ID in message slot Set extended ID register Set CAN message slot control register Settings completed Write H'00 Standard ID or extended ID Write H'40 (receive request) Read CAN message slot control registerTRSTAT bit = 0 YES NO Verify that reception is idle Figure 13.6.1 Procedure for Receiving a Data Frame CAN MODULES

13-91 Rev.1.0

13.6.2 Data Frame Receive Operation

The following describes how data frame receive operation is performed. All these operations are automatically performed in hardware. (1) Acceptance filtering When data reception is completed, the CAN module searches for slots sequentially from slot 0 (up to slot 15) that meet the receive conditions and are therefore eligible for the received message. The following shows the receive conditions for the slots that have been set to receive a data frame. [Conditions]

• The received frame is a data frame.
• The received ID and the slot ID are the same, with the ID mask register bits set to 0 being ignored as "Don't care."
• The standard and extended frame types are the same. Note: When in BasicCAN mode, slots 14 and 15, even when set to receive a data frame, can receive a remote frame too. (2) When the receive conditions are met When the receive conditions described in (1) above are met, the CAN module sets the CAN Message Slot Control Register's TRSTAT (transmit/receive status) and TRFIN (transmit/receive finished) bits to 1 and at the same time writes the received data to the message slot. If the TRFIN (transmit/receive finished) bit is already 1 at this time, the ML (message lost) bit also is set to 1, indicating that the message slot has been overwritten. The message slot has all of its ID and DLC fields overwritten, with an indeterminate value written to its unused area (e.g., the extended ID field when set for standard frame or an unused data field). In addition, the time stamp count value at the time of message reception is written along with the received data to the CAN Message Slot Time stamp Register (CMSLnTSP). When the CAN module finishes writing to the message slot, it sets the CAN slot interrupt status bit to 1. If the slot has been enabled for interrupt, it generates an interrupt and waits for the next reception. (3) When the receive conditions are not met The CAN module discards the received frame and goes to the next transmit or receive operation. It does not write to the message slot. CAN MODULES

13-92 Rev.1.0 B'0100 0011 B'0000 0001 B'0100 0001 B'0000 0000 B'0100 0000 Clear receive requestSet receive request Store received dataStore received data Clear receive request Finish storing received data Finish storing received data Clear receive request B'0000 0011 B'0100 0111 Store received data B'0100 0101 Finish storing received data Clear receive request Clear receive request B'0000 0111 Finish storing received data Clear receive requestClear receive request B'0000 0101 Finish storing received data Clear receive request Clear receive request Store received data Wait for received data Wait for received data Finish storing received data Finish storing received data CPU read CPU read Figure 13.6.2Operation of the CAN Message Slot Control Register during Data Frame Reception CAN MODULES

13-93 Rev.1.0

13.6.3 Reading Out a Received Data Frame

The following shows the procedure for reading a received data frame from the slot. (1) Clearing the TRFIN (transmit/receive finished) bit Clear the CAN Message Slot Control Register (CMSLnCNT)'s TRFIN (transmit/receive finished) bit to 0 by writing H'4E, H'40, or H'00 to the register. The table below describes the slot operation after this write. Value written to CMSLnCNT Slot operation after writing H'4E Operates as a data frame receive slot. Whether the slot has been overwritten can be verified by inspecting the ML bit. H'40 Operates as a data frame receive slot. Whether the slot has been overwritten can be verified by inspecting the ML bit. H'00 Stops transmit/receive operation. Note 1: If the slot needs to be checked for message lost by inspecting the ML bit, clear the TRFIN bit by writing H'4E to the register. Note 2: If the TRFIN bit is cleared by writing H'4E, H'40, or H'00 to the register, it is possible that new data will be stored in the slot while reading the received data from it. (2) Reading out from the message slot Read the received data from the message slot. (3) Checking the TRFIN (transmit/receive finished) bit Read the CAN Message Slot Control Register to check the TRFIN (transmit/receive finished) bit. ➀ When the TRFIN (transmit/receive finished) bit = 1 It means that new data has been stored in the slot while reading out from it in (2) above. In this case, because the data read out in (2) contains an indeterminate value, redo from step (1), clearing the TRFIN (transmit/receive finished) bit. ➁ When the TRFIN (transmit/receive finished) bit = 0 It means that the received data has been read out normally. CAN MODULES

13-94 Rev.1.0 Reading out received data Clear TRFIN bit to 0 Read data from message slot Finished reading out received data Read CAN message slot control register TRFIN bit = 0 YES NO Write H'4E, H'40, or H'00 Figure 13.6.3 Procedure for Reading Out Received Data CAN MODULES

13-95 Rev.1.0

13.7 Transmitting Remote Frames

13.7.1 Remote Frame Transmission Procedure

The following shows the procedure for transmitting a remote frame. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the message slot from which to transmit by writing H'00 to the register. (2) Verifying that transmission is idle Read the initialized CAN Message Slot Control Register and inspect the TRSTAT (transmit/ receive status) bit to see that transmission has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot. Therefore, wait until the bit is cleared to 0. (3) Setting the transmit ID Set the ID to be transmitted in the message slot. (4) Setting the extended ID register Set the extended ID register's corresponding bit to 0 when it needs to be transmitted as a standard frame or 1 when it needs to be transmitted as an extension frame. (5) Setting the CAN Message Slot Control Register Set the CAN Message Slot Control Register TR (transmit request) and RM (remote) bits to 1 by writing H'A0 to the register. CAN MODULES

13-96 Rev.1.0 Remote frame transmission procedure Initialize CAN message slot control register Set ID in message slot Set extended ID register Set CAN message slot control register Settings completed Write H'00 Standard ID or extended ID Write H'A0 (transmit request, remote) Read CAN message slot control registerTRSTAT bit = 0 YES NO Verify that transmission is idle Figure 13.7.1 Procedure for Transmitting a Remote Frame CAN MODULES

13-97 Rev.1.0

13.7.2 Remote Frame Transmit Operation

The following describes how remote frame transmit operation is performed. All these operations are automatically performed in hardware. (1) Setting the RA (remote active) bit The RA (remote active) bit that indicates that the slot is selected to handle a remote frame is set to 1 at the same time the data H'A0 (transmit request, remote) is written to the CAN Message Slot Control Register. (2) Selecting a transmit frame The CAN module checks slots for which there is a transmit request (including data frame transmit slots) every intermission to determine the frame to transmit. If multiple transmit slots exist, frames are transmitted beginning with the slot that has the smallest slot number. (3) Transmitting a remote frame When the transmit slot is determined, the CAN module starts transmitting the remote frame from the slot after setting its corresponding CAN Message Slot Control Register's TRSTAT (transmit/ receive status) bit to 1. (4) If failed in CAN bus arbitration or a CAN bus error occurs If the CAN module loses in CAN bus arbitration or encounters a CAN bus error in the middle of transmission, it clears the CAN Message Slot Control Register's TRSTAT (transmit/receive status) bit to 0. If the transmit abort function for the slot has been enabled, the transmit abort request is accepted and the message slot is freed, allowing for write to the slot. (5) Completing remote frame transmission When the CAN module finishes transmitting the remote frame, the time stamp count value at completion of transmission is stored in the CAN Message Slot Time stamp Register (CMSLnTSP) and the CAN Message Slot Control Register's RA (remote active) bit is cleared to 0. Also, the CAN slot interrupt status bit is set to 1 by completion of transmission, while the CAN Message Slot Control Register's TRFIN (transmit/receive finished) bit remains intact (this bit is not set to 1). If CAN slot interrupt has been enabled, an interrupt is generated upon completion of the transmit operation. (6) Data frame reception When remote frame transmission is completed, the slot automatically becomes to function as a data frame receive slot. CAN MODULES

13-98 Rev.1.0 (7) Acceptance filtering When data reception is completed, the CAN module searches for slots sequentially from slot 0 (up to slot 15) that meet the receive conditions and are therefore eligible for the received message. The following shows the receive conditions for the slots that have been set to receive a data frame. [Conditions]

• The received frame is a data frame.
• The received ID and the slot ID are the same, with the ID mask register bits set to 0 being ignored as "Don't care."
• The standard and extended frame types are the same. Note: When in BasicCAN mode, slots 14 and 15 cannot be used as transmit slots. (8) When the receive conditions are met When the receive conditions described in (7) above are met, the CAN module sets the CAN Message Slot Control Register's TRSTAT (transmit/receive status) and TRFIN (transmit/receive finished) bits to 1 and at the same time writes the received data to the message slot. If the TRFIN (transmit/receive finished) bit is already 1 at this time, the ML (message lost) bit also is set to 1, indicating that the message slot has been overwritten. The message slot has all of its ID and DLC fields overwritten, with an indeterminate value written to its unused area (e.g., the extended ID field when set for standard frame or an unused data field). In addition, the time stamp count value at the time of message reception is written along with the received data to the CAN Message Slot Time stamp Register (CMSLnTSP). When the CAN module finishes writing to the message slot, it sets the CAN slot interrupt status bit to 1. If the slot has been enabled for interrupt, it generates an interrupt and waits for the next frame to receive. Note: If the CAN module receives a data frame before transmitting the remote frame, it stores the received data frame and does not transmit the remote frame. (9) When the receive conditions are not met The CAN module discards the received frame and goes to the next transmit or receive operation. It does not write to the message slot. CAN MODULES

13-99 Rev.1.0 B'0000 0000 B'0000 0000 Store the received data Failed in bus arbitration or C AN bus error occurs Clear transm it request B'0000 1010 B'1010 0011 Store the received data Clear transmit request B'0000 0011 B'0000 0001 Wait for the data to receive Finish sending a remote frame CPU read B'1010 0101 B'1010 1000 B'1010 1010 Finish storing the received data Clear receive request Store the received data Clear receive request Store the received data Clear receive request Finish storing the received data B'1010 0001 Store the received data B'1010 0111B'0000 0111 B'0000 0101 Finish storing the received data Finish storing the received data Store the received data Finish sending a remote frame B'1010 0000 Wait for the data to receive B'1010 1011 B'0000 1011 Clear transmit request B'0000 0001 Finish storing the received dataFinish storing the received data B'0000 1000 CAN bus error occurs Finish storing the received data Clear receive request Figure 13.7.2 Operation of the CAN Message Slot Control Register during Remote Frame Transmission CAN MODULES

13-100 Rev.1.0

13.7.3 Reading Out a Received Data Frame When Set for Remote Frame Transmission

The following shows the procedure for reading a received data frame from the slot when it is set for remote frame transmission. (1) Clearing the TRFIN (transmit/receive finished) bit Clear the CAN Message Slot Control Register (CMSLnCNT)'s TRFIN (transmit/receive finished) bit to 0 by writing H'AE or H'00 to the register. The table below describes the slot operation after this write. Value written to CMSLnCNT Slot operation after writing H'AE Operates as a data frame receive slot. Whether the slot has been overwritten can be verified by inspecting the ML bit. H'00 Stops transmit/receive operation. Note 1: If the slot needs to be checked for message lost by inspecting the ML bit, clear the TRFIN bit by writing H'AE to the register. Note 2: If the TRFIN bit is cleared by writing H'AE or H'00 to the register, it is possible that new data will be stored in the slot while reading the received data from it. Note 3: The received data frame cannot be read out if the TRFIN bit is cleared by writing H'A0 to the register. In this case, the slot is set to transmit a remote frame. (2) Reading out from the message slot Read the received data from the message slot. (3) Checking the TRFIN (transmit/receive finished) bit Read the CAN Message Slot Control Register to check the TRFIN (transmit/receive finished) bit. ➀ When the TRFIN (transmit/receive finished) bit = 1 It means that new data has been stored in the slot while reading out from it in (2) above. In this case, because the data read out in (2) contains an indeterminate value, redo from step (1), clearing the TRFIN (transmit/receive finished) bit. ➁ When the TRFIN (transmit/receive finished) bit = 0 It means that the received data has been read out normally. CAN MODULES

13-101 Rev.1.0 Reading out received data Clear TRFIN bit to 0 Read data from message slot Finished reading out received data Read CAN message slot control register TRFIN bit = 0 YES NO Write H'AE or H'00 Figure 13.7.3Procedure for Reading Out Received Data When Set for Remote Frame Transmission CAN MODULES

13-102 Rev.1.0

13.8 Receiving Remote Frames

13.8.1 Remote Frame Reception Procedure

The following describes the procedure for receiving a remote frame. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the message slot in which to receive by writing H'00 to the register. (2) Verifying that reception is idle Read the initialized CAN Message Slot Control Register and inspect the TRSTAT (transmit/ receive status) bit to see that reception has stopped and remains idle. If this bit = 1, it means that the CAN module is accessing the message slot. Therefore, wait until the bit is cleared to 0. (3) Setting the ID Set the ID desired to be received in the message slot. (4) Setting the extended ID register Set the extended ID register's corresponding bit to 0 when it is desired to receive a standard frame or 1 when it is desired to receive an extension frame. (5) Setting the CAN Message Slot Control Register ➀ When remote frame reception needs to be automatically answered (data frame transmission) Set the CAN Message Slot Control Register RR (receive request) and RM (remote) bits to 1 by writing H'60 to the register. ➁ When remote frame reception does not need to be automatically answered Set the CAN Message Slot Control Register RR (receive request), RM (remote), and RL (automatic answering enable) bits to 1 by writing H'70 to the register. Note:When in BasicCAN mode, although slots 14 and 15 can receive a remote frame, they cannot be set to automatically answer the received remote frame. CAN MODULES

13-103 Rev.1.0 Remote frame reception procedure Initialize CAN message slot control register Set ID in message slot Set extended ID register Set CAN message slot control register Settings completed Write H'00 Standard ID or extended ID Write H'60 (receive request, remote, automatic answering enabled) Write H'70 (receive request, remote, automatic answering disabled) Read CAN message slot control register TRSTAT bit = 0 YES NO Verify that reception is idle Figure 13.8.1 Procedure for Receiving a Remote Frame CAN MODULES

13-104 Rev.1.0

13.8.2 Remote Frame Receive Operation

The following describes how remote frame receive operation is performed. All these operations are automatically performed in hardware. (1) Setting the RA (remote active) bit The RA (remote active) bit that indicates that the slot is selected to handle a remote frame is set to 1 at the same time the data H'60 (receive request, remote) or H'70 (receive request, remote, automatic answering disabled) is written to the CAN Message Slot Control Register. (2) Acceptance filtering When data reception is completed, the CAN module searches for slots sequentially from slot 0 (up to slot 15) that meet the receive conditions and are therefore eligible for the received message. The following shows the receive conditions for the slots that have been set to receive a remote frame. [Conditions]

• The received frame is a remote frame.
• The received ID and the slot ID are the same, with the ID mask register bits set to 0 being ignored as "Don't care."
• The standard and the extended frames are of the same type. (3) When the receive conditions are met When the receive conditions described in (2) above are met, the CAN module sets the CAN Message Slot Control Register's TRSTAT (transmit/receive status) and TRFIN (transmit/receive finished) bits to 1 and at the same time writes the received data to the message slot. In addition, the time stamp count value at the time of message reception is written along with the received data to the CAN Message Slot Time stamp Register (CMSLnTSP). When the CAN module finishes writing to the message slot, it sets the CAN slot interrupt status bit to 1. If the slot has been enabled for interrupt, it generates an interrupt and waits for the next reception. Note 1: The message slot has the ID field and the DLC value written to it. Note 2: When the standard format is selected, the slot has an indeterminate value written to its extended ID area. Note 3: The data field is not accessed for write. Note 4: The RA and TRFIN bits are cleared to 0 after writing to the received remote frame data to the slot. (4) When the receive conditions are not met The CAN module discards the received data and waits for the next frame to receive. It does not write to the message slot. CAN MODULES

13-105 Rev.1.0 (5) Operation after receiving a remote frame The operation to be performed for the slot after receiving a remote frame differs depending on whether automatic answering is enabled or not. ➀ When automatic answering is disabled The slot which finished receiving data becomes inactive and remains idle (neither transmitting nor receiving) until new settings are made for it in software. ➁ When automatic answering is enabled After receiving a remote frame, the slot automatically changes to a data frame transmit slot, performing the transmit processing described below. In this case, the data to be transmitted conforms to the ID and DLC of the received remote frame.

• Selecting a transmit frame The CAN module checks slots for which there is a transmit request (including remote frame transmit slots) every intermission to determine the frame to transmit. If multiple transmit slots exist, frames are transmitted beginning with the slot that has the smallest slot number.
• Transmitting a data frame When the transmit slot is determined, the CAN module starts transmitting the data frame from the slot after setting its corresponding CAN Message Slot Control Register's TRSTAT (transmit/receive status) bit to 1.
• If failed in CAN bus arbitration or a CAN bus error occurs If the CAN module loses in CAN bus arbitration or encounters a CAN bus error in the middle of transmission, it clears the CAN Message Slot Control Register's TRSTAT (transmit/receive status) bit to 0. If the transmit abort function for the slot has been enabled, the transmit abort request is accepted and the message slot is freed, allowing for write to the slot.
• Completing data frame transmission When the CAN module finishes transmitting the data frame, the CAN Message Slot Control Register's TRFIN (transmit/receive finished) bit and the CAN Slot Interrupt Status Register are set to 1. Also, the time stamp count value at completion of transmission is written to the CAN Message Slot Time stamp Register (CMSLnTSP), thereby completing the transmit operation. If CAN slot interrupt has been enabled, an interrupt is generated upon completion of the transmit operation. The slot which has had transmission completed becomes inactive and remains idle until new settings are made for it in software. CAN MODULES

13-106 Rev.1.0 B'0000 0000 B'0000 0000 Clear receive request B'0000 1010 B'0110 0010 Store the received data Clear receive request B'0000 0010 B'0000 0001 Finish storing the received data B'0110 1000 B'0110 1011 Finish storing the received data Clear receive request B'0110 0001 B'0110 0000 B'0111 1000 B'0000 1010 B'0000 0000 Wait for reception Transmit data frame Clear receive request Finish transmitting data frame Finish transmitting data frame Transmit data frame Finish storing the received data Store the received data B'0111 1010 Store the received data B'0111 0000 Finish storing the received data Finish storing the receiveddata Clear receiverequest Store the received data Clear receive request Write H'60 (automatic answering enabled) Write H'70 (automatic answering disabled) Figure 13.8.2 Operation of the CAN Message Slot Control Register during Remote Frame Reception CAN MODULES

14.1 Outline of the Real-Time

Debugger (RTD)

14.2 Pin Function of the RTD

14.3 Functional Description of

14.4 Typical Connection with the

DEBUGGER (RTD)

14-2 Rev.1.0

14.1 Outline of the Real-Time Debugger (RTD)

The Real-Time Debugger (RTD) is a serial I/O through which to read or write to the internal RAM's entire area using commands from outside the microprocessor. Because data transfers between the RTD and internal RAM are performed using an internal dedicated bus independently of the M32R CPU, operation can be controlled without having the stop the M32R CPU. Table 14.1.1 Outline of the Real-Time Debugger (RTD) Item Content Transfer method Clock-synchronized serial I/O Generation of transfer clock Generated by external host RAM access area Entire area of internal RAM (controlled by A16-A29) Transmit/receive data length 32 bits (fixed) Bit transfer sequence LSB first Maximum transfer rate 2 Mbits/second Input/output pins 4 lines (RTDTXD, RTDRXD, RTDACK, RTDCLK) Number of commands Following five functions

• Monitors continuously
• Outputs real-time RAM contents
• Forcibly rewrites RAM contents (with verify)
• Recovers from runaway
• Requests RTD interrupt REAL-TIME DEBUGGER (RTD)

Figure 14.1.1 Block Diagram of the Real-Time Debugger (RTD) Control circuit Command Data RTD control circuit Entire RAM area CPU Address Data Bus switching circuit RTDCLK RTDACK RTDTXD RTDRXD Address Data Data Address

14-3 Rev.1.0 REAL-TIME DEBUGGER (RTD) Pin functions of the RTD are shown below. Table 14.2.1 Pin Function of the RTD Pin Name Type Function RTDTXD Output RTD serial data output RTDRXD Input RTD serial data input RTDACK Output Outputs a low-level pulse synchronously with the beginning clock edge of the output data word. The width of the low-level pulse thus output indicates the type of instruction/data that the RTD received. 1 clock period : VER (continuous monitor) command 1 clock period : VEI (RTD interrupt request) command 2 clock periods : RDR (real-time RAM content output) command 3 clock periods : WRR (RAM content forcible rewrite) command or the data to rewrite 4 clock periods or more : RCV (recover frorunaway)command RTDCLK Input RTD transfer clock input

14-4 Rev.1.0

14.3 Functional Description of the RTD

14.3.1 Outline of RTD Operation

Operation of the RTD is specified by a command entered from devices external to the chip. A command is specified in bits 16-19(note 1) of the RTD receive data. Table 14.3.1 RTD Commands RTD Receive Data Command Mnemonic RTD Function b19 b18 b17 b16 0 0 0 0 VER (VERify) Continuous monitor 0 1 0 0 0 1 0 1 0 1 1 0 VEI (VErify Interrupt request) RTD interrupt request 0 0 1 0 RDR (ReaD RAM) Real-time RAM content output 0 0 1 1 WRR (WRite RAM) RAM content forcibly rewrite (with verify) 1 1 1 1 RCV (ReCoVer) Recover from runaway (Note 2, Note 3) 0 0 0 1 System reserved (use inhibited) ↑ (Note 1) Note 1: Bit 19 of RTD receive data is not actually stored in the command register and except for the RCV command, is handled as "Don't Care" bit. (Bits 16-18 are effective for the command specified.) Note 2: The RCV command must always be transmitted twice in succession. Note 3: For the RCV command, all bits, not just bits 16-19, (i.e., bits 0-15 and bits 20-31) must be set to 1. REAL-TIME DEBUGGER (RTD)

14-5 Rev.1.0 REAL-TIME DEBUGGER (RTD)

14.3.2 Operation of RDR (Real-time RAM Content Output)

When the RDR (real-time RAM content output) command is issued, the RTD is made possible to transfer the contents of the internal RAM to external devices without causing the CPU's internal bus to stop. Because the RTD reads data from the internal RAM while no transfers are being performed between the CPU and internal RAM, no extra load is levied on the CPU. The address to be read from the internal RAM can only be specified on 32-bit word boundaries. (The two low-order address bits specified by a command are ignored.) Note also that data are read out in units of 32 bits as transferred from the internal RAM to an external device. Figure 14.3.1 RDR Command Data Format Figure 14.3.2 Operation of the RDR Command Note: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Note: (An) = Specified address D (An) = Data at specified address (An) X 0 0 1 0 19 18 17 16 X X 14 13 12 1 A16 X A17A28A29 Command (RDR ) Specified address (MSB side)(LSB side) 32 clock periods 32 clock periods 32 clock periods 32 clock periods RDR (A1) RDR (A2) RDR (A3) D (A1) D (A2) 2 clock periods RTDCLK RTDRXD RTDTXD RTDACK

14-6 Rev.1.0 REAL-TIME DEBUGGER (RTD) Figure 14.3.3 Read Data Transfer Format Note: The read data is transferred LSB-first. D31 D30 Read data (Note) RTDTXD (MSB side)(LSB side)

14-7 Rev.1.0 REAL-TIME DEBUGGER (RTD)

14.3.3 Operation of WRR (RAM Content Forcible Rewrite)

When the WRR (RAM content forcible rewrite) command is issued, the RTD forcibly rewrites the contents of the internal RAM without causing the CPU's internal bus to stop. Because the RTD writes data to the internal RAM while no transfers are being performed between the CPU and internal RAM, no extra load is levied on the CPU. The address to be read from the internal RAM can only be specified on 32-bit word boundaries. (The two low-order address bits specified by a command are ignored.) Note also that data are written to the internal RAM in units of 32 bits. The external host should transmit the command and address in the first frame and then the write data in the second frame. The timing at which the RTD writes to the internal RAM occurs in the third frame after receiving the write data. Figure 14.3.4 WRR Command Data Format Note 1: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Note 2: The specified address and write data are transferred LSB-first. X 0 0 1 1 19 18 17 16 X X 14 13 12 1 A16 X A17A28A29 Command (WRR) Specified address (MSB side)(LSB side) D31 D30 Write data (Note) (MSB side)(LSB side) a) First frame b) Second frame

14-8 Rev.1.0 REAL-TIME DEBUGGER (RTD) Figure 14.3.5 Operation of the WRR Command The RTD reads out data from the specified address before writing to the internal RAM and again reads out from the same address immediately after writing to the internal RAM (this helps to verify the data written to the internal RAM). The read data is output at the timing shown below. Note: (An) = Specified address D (An) = Data at specified address (An) D (A1) Verify value after write WRR (A1) (A1) Write data RTDCLK RTDRXD RTDTXD RTDACK WRR (A2) (A2) Write data D (A1) Read value before write 32 clock periods 32 clock periods 32 clock periods 32 clock periods 3 clock periods

14-9 Rev.1.0 REAL-TIME DEBUGGER (RTD)

14.3.4 Operation of VER (Continuous Monitor)

When the VER (continuous monitor) command is issued, the RTD outputs data from the address that has been accessed by the instruction (either read or write) immediately before receiving the VER command. Figure 14.3.6 VER (Continuous Monitor) Command Data Format Figure 14.3.7 Operation of the VER (Continuous Monitor) Command Note: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Note 1: WRR command can also be used. Note 2: (An) = Specified address D (An) = Data at specified address (An) X0 0 0 0 19 18 17 16 X 15 0 X (MSB side)(LSB side) X Command (VER) RDR (A1) VER RTDCLK RTDRXD RTDTXD RTDACK D (A1) Read value (Note 2) D (A1) Latest read value (Note 1) VER 32 clock periods 32 clock periods 32 clock periods 32 clock periods 2 clock periods

14-10 Rev.1.0 REAL-TIME DEBUGGER (RTD)

14.3.5 Operation of VEI (Interrupt Request)

When the VEI (interrupt request) command is issued, the RTD outputs data from the address that has been accessed by the instruction (either read or write) immediately before receiving the VEI command. Figure 14.3.8 VEI (Interrupt Request) Command Data Format Figure 14.3.9 Operation of the VEI (Interrupt Request) Command Note: X = Don't Care (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.) Note 1: WRR command can also be used. Note 2: (An) = Specified address D (An) = Data at specified address (An) X0 1 1 0 19 18 17 16 X 15 0 X (MSB side)(LSB side) X VEI (interrupt request generation) command (Note) (Note) RTD interrupt RDR (A1) VEI RTDCLK RTDRXD RTDTXD RTDACK D (A1) Read value (Note 2) (Note 1) 32 clock periods 32 clock periods 32 clock periods 32 clock periods 2 clock periods D (A1) Read value (Note 2) RTD interrupt request

14-11 Rev.1.0 REAL-TIME DEBUGGER (RTD)

14.3.6 Operation of RCV (Recover from Runaway)

When the RTD runs out of control, the RCV (recover from runway) command can be issued to forcibly recover from the runaway condition without having to reset the system. The RCV command must always be issued twice in succession. Also, any command issued subsequently after the RCV command must have its bits 20-31 all set to 1. Figure 14.3.10 RCV Command Data Format Note: All of 32 data bits are 1's. The RCV command must always be issued twice in succession. Note: The next command following the RCV command must have its bits 20-31 all set to 1. Figure 14.3.11 Operation of the RCV Command 11 1 1 1 19 18 17 16 15 0 (MSB side)(LSB side) Command (RCV) (Note) (Note) RCV RCV command stored here RTDCLK RTDRXD RTDTXD RTDACK RCV Bits 20-31 D (A1)Indeterminate data during runway condition Indeterminate value during runway condition Next command following the RCV command 1• • • 1 RDR (A1) 32 clock periods 32 clock periods 32 clock periods 32 clock periods 2 clock periods 2 clock periods

14-12 Rev.1.0 REAL-TIME DEBUGGER (RTD) Figure 14.3.12 Method for Setting Addresses in Real-Time Debugger

14.3.7 Method to Set a Specified Address when Using the RTD

When using the Real-Time Debugger (RTD), you can set low-order 16-bit addresses of the internal RAM area. Because the internal RAM area is located in a 48 KB area ranging from H'0080 4000 to H'0080 FFFF, you can set low-order 16-bit addresses of that area. However, access to any locations other than the area where the RAM resides is inhibited. Note also that two least significant address bits, A31 and A30, are always 0's because data are read and written to the internal RAM in a fixed length of 32 bits. SFR 16KB H'0080 0000 H'0080 4000 Memory map H'0080 FFFF XX A29 - A16 H'0080 4000~H'0080 FFFF

• • • RAM areaonly can be specified

14-13 Rev.1.0 REAL-TIME DEBUGGER (RTD) Figure 14.3.13 Command Transfer to the RTD after System Reset Note: (An) = Specified address D (An) = Data at specified address (An)

14.3.8 Resetting the RTD

The RTD is reset by applying a system rest (i.e., by entering the RESET signal). The status of the RTD related output pins after a system reset are shown below. Table 14.3.2 RTD Pin State after System Reset Pin Name State RTDACK High-level output RTDTXD High-level output The first command transfer to the RTD after it was reset is initiated by transferring data to the RTDRXD pin synchronously with falling edges of RTDCLK. Don't Care RDR (A1) RTDCLK RTDRXD RTDTXD RTDACK RESET System reset "H" RDR (A2) 0000 0000 0000 0000 D (A2) "H" D (A1) 32 clock periods 32 clock periods 32 clock periods 32 clock periods

14-14 Rev.1.0 REAL-TIME DEBUGGER (RTD)

14.4 Typical Connection with the Host

Figure 14.4.1 Connecting the RTD and Host Note: In this example, the RTDACK level is checked between transfer frames. The host uses a serial synchronous interface to transfer data. The clock for synchronous is generated by the host. An example for connecting the RTD and host is shown below. RTDRXD RTDTXD RTDCLK RTDACK M32R/E Host microprocessor RXD TXD SCLK PORT(Note)

14-15 Rev.1.0 REAL-TIME DEBUGGER (RTD) The RTD communication for a fixed length of 32 bits per frame generally is performed in four operations sending 8 bits at a time, because most serial interfaces transfer data in units of 8 bits. The RTDACK signal is used to verify that communication is performed normally. After transmitting a command, the RTDACK signal is pulled low, making it possible to verify the communication status. When issuing the VER command, the RTDACK signal goes low for only one clock period. Therefore, after sending 32 bits in one frame, turn off RTDCLK output and check whether RTDACK is low. If RTDACK is low, you know that the RTD is communicating normally. If you want to identify the type of transmitted command by the width of RTDACK, use the 32171's internal measurement timer (to count RTDCLK pulses while RTDACK is low) or create a dedicated circuit. Figure 14.4.2 Typical Operation for Communication with the Host (when Issuing VER Command) Transfer of next frame (8 bits) Check the RTDACK signal L level. RTDCLK RTDRXD RTDTXD RTDACK Transfer of 1 frame (32 bits) (8 bits) (8 bits)

14-16 Rev.1.0 REAL-TIME DEBUGGER (RTD)

• This is a blank page.*

15.1 Outline of the PD Module

15.2 PD Module Related Regis

15.3 Initialization for PD Sensor

15.4 Precautions on Using the PD

15-2 Rev.1.0 The 32172/32173 contains eight channels of event counters that can be used as a dedicated interface circuit for PD (Phase Digital) sensors. Combined with PD sensors, the PD module can perform predictive computations at high speed that are required during position detection. Note:For the PD module to be used in combination with PD sensors, an external circuit is required separately. PD MODULE Table 15.1.1 Outline of the PD Module Item Content TPD 16-bit input measure timer (up-counter) One of two modes can be selected in software:

• PD sensor support mode Operates corresponding to input from PD sensors.
• Normal mode Operates as a free-running up-counter. TEPiP 16-bit input related timer (up-counter) TEPiM One of two modes can be selected in software: (i = 0,1) • Event count mode Counts the number of pulses entered from an external pin
• PD sensor support mode Operates corresponding to input from PD sensors. PD calculation function Performs various calculations corresponding to input from PD sensors and stores the result in a register (2 channels). Table 15.1.2 PD Module Interrupt Generation Function Signal PD module interrupt request source Input to Interrupt Controller (ICU) Sources on ICU name IRQ31 TIN0A input, TIN0B input, PDC input interrupt 8 TIN1A input, TIN1B input, TIN0A error detection, TIN0B error detection, TIN1A error detection, TIN1B error detection IRQ2 PD0_ABD compare match, PDC calculation interrupt 8 PD1_ABD compare match, PD0_PITCH compare match, PD1_PITCH compare match, PD0_ABD&PITCH compare match, PD1_ABD&PITCH compare match, PD0_S error, PD1_S error

15-3 Rev.1.0 Table 15.1.3 PD Module DMA Transfer Request Generation Function DMA transfer request generation function DMA input channel PD0_ABD compare match Channels 1-9 PD0_ABD&PITCH compare match (note) PD1_ABD compare match Channels 1-9 PD1_ABD&PITCH compare match (note) TIN0A input detection Channels 0 TIN0B input detection Channels 2 TIN1A input detection Channels 5 TIN1B input detection Channels 7 Note: Selected using the DMA Transfer Request Source Select Register (DMAREQSL). PD MODULE

15-4 Rev.1.0 PRSA TIN0AS TIN0BS PRS0C PRSB PRS0C clk Reload Register DACNT udf TPDclkCLR TPDMR0 TPDMR1 TPDMR2 TPDMR3 TEP0PclkCLR TEP0Mclk CLR TIN1AS TIN1BS PRS0CPRS1C TPDMR4 TPDMR5 TPDMR6 TPDMR7 TEP1P TEP1M clkCLR PD Channel 0 (Position Calculation Circuit) PD Channel 1 (Position Calculation Circuit) Pnew0 Pold0 Mnew0 Mold0 TIN0AS TIN0BS TIN1AS TIN1BS Internal peripheral clock (BCLK) IRQ31 IRQ31 IRQ31 IRQ31 IRQ31 IRQ2 IRQ31 IRQ2 DRQ26 DRQ21 DRQ22 DRQ23 DRQ24 DRQ25 Pnew1 Pold1 Mnew1 Mold1 R-2R DA0 DPRAM 256 bytes Cap Cap Cap Cap clkCLR Cap Cap Cap Cap Internal peripheral clock (BCLK) Internal peripheral clock (BCLK) Internal peripheral clock (BCLK) DA0 Converter Figure 15.1.1 Block Diagram of the PD Module PD MODULE

15-5 Rev.1.0

15.2 PD Module Related Registers

A PD module related register map is shown below. Figure 15.2.1 PD Module Register Map (1/2) PD MODULE +0 address +1 address D0 D7 D8 D15 H'0080 1808 TPD Counter (TPDCT) TPD Measure Register 0 (TPDMR0) H'0080 180E H'0080 1810 H'0080 1812 H'0080 1814 H'0080 1816 H'0080 181A H'0080 181C H'0080 181E H'0080 1830 H'0080 1832 H'0080 1840 H'0080 1842 H'0080 1844 H'0080 1846 H'0080 184C PD Calculation Interrupt Control Register (PDICR) Position Detection Accuracy Select Register (PDASR) Prescaler Register 0C (PRS0C) Address H'0080 184E H'0080 1860 H'0080 1862 H'0080 1864 H'0080 1866 SMSB Control Register 0 (SMSBCR0) ABD0 Compare Register (ABD0CM) PNEWLT0 Register (PNEWLT0) H'0080 186E H'0080 1872 H'0080 1876 H'0080 1878 H'0080 187A H'0080 1800 H'0080 1806 H'0080 1802 H'0080 1804 Blank areas are reserved for future use. H'0080 1818 H'0080184A H'0080 186A H'0080 186C H'0080 1874 Prescaler Register B (PRSB) TIN Input Processing Control Register (TINPDCR) TIN Interrupt Control Register (TINPDICR)TIN Interrupt Status Register (TINPDIST) TPD Control Register (TPDCR) TPD Measure Register 1 (TPDMR1) TPD Measure Register 2 (TPDMR2) TPD Measure Register 3 (TPDMR3) TPD Measure Register 4 (TPDMR4) TPD Measure Register 5 (TPDMR5) TPD Measure Register 6 (TPDMR6) TPD Measure Register 7 (TPDMR7) H'0080 1848 H'0080 1870 H'0080 1868 PD Calculation Interrupt Status Register (PDIST) TEP0P Control Register (TEP0PCR) TEP0M Control Register (TEP0MCR) TEP0P Counter (TEP0PCT) TEP0M Counter (TEP0MCT) PD0 Data Updating Disable Event Select Register (PDNSEL0R) ABD0 Mask Register (ABD0MK) PICH0 Compare Register (PITCH0CMR) POLDLT0 Register (POLDLT0) MOLDLT0 Register (MOLDLT0) MNEWLT0 Register (MNEWLT0) PSUBLT0 Register (PSUBLT0) MSUBLT0 Register (MSUBLT0) PRLT0 Register (PRLT0) SNEWLT0 Register (SNEWLT0) MRLT0 Register (MRLT0) FDLT0 Register (FDLT0) ABDLT0 Register (ABDLT0) PITCHLT0 Register (PITCHLT0) RSUMLT0 Register (RSUMLT0) SSLT0 Register (SSLT0) PD0 Data Updating Control Register (PDNCNT0R) S Error 0 Detection Range Select Register (SNEW0MK) DMA Transfer Request Source Select Register (DMAREQSL) Note: The registers enclosed in are an intermediate register used for calculations. Do not access these registers for read or write. Prescaler Register A (PRSA) DACNT Reload Register (DACNTRL) DACNT Control Register (DACNTCR) DACNT Counter (DACNT)

15-6 Rev.1.0 +0 address +1 address D0 D7 D8 D15 H'0080 1888 H'0080 188A H'0080 188C H'0080 188E H'0080 18A0 H'0080 18A4 H'0080 18A6 H'0080 18A8 H'0080 18AA H'0080 18AC H'0080 18B0 H'0080 18B2 H'0080 18B4 H'0080 18B6 Address ABDLT1 Register (ABDLT1) H'0080 1880 H'0080 1886 H'0080 1882 H'0080 1884 Blank areas are reserved for future use. H'0080 18A2 Prescaler Register 1C(PRS1C) SMSB Control Register 1(SMSBCR1) TEP1P Control Register (TEP1PCR) TEP1M Control Register (TEP1MCR) SNEWLT1 Register (SNEWLT1) FDLT1 Register (FDLT1) PRLT1 Register (PRLT1) PITCHL1 Register (PITCHLT1) MRLT1 Register (MRTL1) PNEWLT1 Register (PNEWLT1) POLDT1 Register (POLDLT1) MNEWLT1 Register (MNEWLT1) MOLDLT1 Register (MOLDLT1) PSUBLT1 Register (PSUBLT1) MSUBLT1 Register (MSUBLT1) RSUMLT1 Register (RSUMLT1) H'0080 18AE H'0080 18BA TEP1P Counter (TEP1PCT) TEP1M Counter (TEP1MCT) PD1 Data Updating Disable Event Select Register (PDNSEL1R)PD1 Data Updating Control Register (PDNCNT1R) ABD1 Mask Register (ABD1MK) S Error 1 Detection Range Select Register (SNEW1MK) ABD1 Compare Register (ABD1CM) PITCH1 Compare Register (PITCH1CMR) SSLT1 Register (SSLT1) H'0080 18B8 Note: The registers enclosed in are an intermediate register used for calculations. Do not access these registers for read or write. Figure 15.2.2 PD Module Register Map (2/2) PD MODULE

15-7 Rev.1.0

15.2.1 Prescaler Unit

The prescalers PRSA, PRSB, PRS0C, and PRS1C each consist of an 8-bit counter which generates clocks from the internal peripheral clock (20.0 MHz when the CPU clock = 40 MHz) for supply to each timer. The prescaler value is initialized to H'00 when reset. Also when the value of the prescaler register is rewritten, the prescaler starts operating with the new value simultaneously when the prescaler underflows. An value in the range of H'00 to H'FF can be set in the prescaler register. The prescaler's divide ratio is given by the equation below. I Prescaler Register A (PRSA) <Address: H'0080 1800> D 0 123456 D 7 PRSA <When reset: H'00> D Bit Name Function R W 0-7 PRSA Sets the prescaler's divide ratio The Prescaler A generates a count clock for the D-A converter's parameter table address counter (DACNT) from the internal peripheral clock (20.0 MHz when the CPU clock = 40 MHz) by dividing it by an appropriate value. When the value of Prescaler Register A is rewritten while the DACNT is operating, the prescaler starts operating with the newl value simultaneously when the prescaler underflows. The PRSA starts generating a clock after the DACNT Control Register DACNTEN bit is set to 1. DACNT count period = f / (PRSA + 1) Note:When using the module along with PD sensors, the PRSA set value is subject to limitations depending on how the Position Detection Accuracy Select Register is set. PD MODULE Prescaler set value + 1Prescaler divide ratio =

15-8 Rev.1.0 I Prescaler Register B (PRSB) <Address: H'0080 1801> D 8 9 1 01 11 21 31 4 D 1 5 PRSB <When reset: H'00> D Bit Name Function R W 8-15 PRSB Sets the prescaler's divide-by value The Prescaler B generates a count clock for the 16-bit input measure counter (TPDCT) from the internal peripheral clock (20.0 MHz when the CPU clock = 40 MHz) by dividing it by an appropriate value. When the value of Prescaler Register B is rewritten while the DACNT is operating, the prescaler starts operating with the new value simultaneously when the prescaler underflows. The PRSB starts generating a clock after the TPD Control Register TPDEN bit is set to 1. TPD count period = f / (PRSB + 1) Note: When using the TPD Counter (TPDCT) along with PD sensors, make sure the set value of the PRSB is H'00. PD MODULE

15-9 Rev.1.0 I Prescaler Register 0C (PRS0C) <Address: H'0080 1840> I Prescaler Register 1C (PRS1C) <Address: H'0080 1880> <When reset: H'00> D Bit Name Function R W 0-7 PRS0C, PRS1C Sets the prescaler's divide-by value These prescalers generate count clocks for the TEPiP and TEPiM counters from the internal peripheral clock (20.0 MHz when the CPU clock = 40 MHz) by dividing it by an appropriate value. When the value of Prescaler Register 0C or 1C is rewritten while the TEPiP/TEPiM counter is operating, the prescaler starts operating with the new value simultaneously when the prescaler underflows. Note 1: The PRS0C (PRS1C) starts generating a clock after the TEP0P (TEM1P) Control Register TEP0PEN (TEM1PEN) bit is set to 1. Note 2: When using the TEPiP/TEPiM counters along with PD sensors, make sure the set values of the prescalers (PRS0C, PRS1C) are H'00. D 0 123456 D 7 PRS0C, PRS1C PD MODULE

15-10 Rev.1.0

15.2.2 DACNT Reload Register

I DACNT Reload Register (DACNTRL) <Address: H'0080 1802> The DACNT Reload Register is used to reload data into the DACNT Counter. Data is loaded into the DACNT Counter synchronously with the clock cycle in which the counter underflowed. Simply because data is written to the DACNT Reload Register does not mean that the DACNT Counter is loaded with the data. D 0 123456 D 7 DACNTRL <When reset: H'00> D Bit Name Function R W 0-7 DACNTRL 8-bit reload register value PD MODULE

15-11 Rev.1.0

15.2.3 TIN Input Processing Control Register

I TIN Input Processing Control Register (TINPDCR) <Address: H'0080 1803> D 8 9 1 01 11 21 31 4 D 1 5 TIN1BS TIN1AS TIN0BS TIN0AS <When reset: H'00> D Bit Name Function R W 8-9 TIN1BS 00: Input has no effect (Select TIN1BS input processing) 01: Rising edge 10: Falling edge 11: Both edges 10-11 TIN1AS 00: Input has no effect (Select TIN1AS input processing) 01: Rising edge 10: Falling edge 11: Both edges 12-13 TIN0BS 00: Input has no effect (Select TIN0BS input processing) 01: Rising edge 10: Falling edge 11: Both edges 14-15 TIN0AS 00: Input has no effect (Select TIN0AS input processing) 01: Rising edge 10: Falling edge 11: Both edges Use the TIN Input Processing Control Register to select the active edge of the TIN input signal at which to generate the measure, clear, and count source signals for each timer. (1) Input has no effect Input on the TIN pin has no effect, with no signals generated for each timer. (2) Rising edge Signals for each timer are generated upon detecting the rising edge of the TIN pin input signal. (3) Falling edge Signals for each timer are generated upon detecting the falling edge of the TIN pin input signal. (4) Both edges Signals for each timer are generated upon detecting the rising or falling edge of the TIN pin input signal. Note: The pulse width of the TIN pin input signal must be equal to or greater than 3.5 clock periods of the internal peripheral clock. PD MODULE

15-12 Rev.1.0 TIN Count clock Figure 15.2.3 Rising Edge Detection Figure 15.2.4 Falling Edge Detection Figure 15.2.5 Both Edge Detection PD MODULE

15-13 Rev.1.0

15.2.4 TIN Interrupt Control Register

I TIN Interrupt Control Register (TINPDICR) <Address: H'0080 1804> D 0 123456 D 7 TIN1BEIM TIN1AEIM TIN0BEIM TIN0AEIM TIN1BIM TIN1AIM TIN0BIM TIN0AIM <When reset: H'00> D Bit Name Function R W

0 TIN1BEIM (Note) 0: Disables interrupt

1 TIN1AEIM (Note) 1: Enables interrupt

2 TIN0BEIM (Note)

3 TIN0AEIM (Note)

4 TIN1BIM

5 TIN1AIM

6 TIN0BIM

7 TIN0AIM

This register controls disabling/enabling of interrupts for the interrupt requests generated by each TIN input processing circuit. Setting any bit to 1 in this register enables the corresponding TIN input interrupt request. Note: The D0-D3 bits are provided for use with PD sensors. When not using the module along with PD sensors, be sure to write 0 to these bits. PD MODULE

15-14 Rev.1.0

15.2.5 TIN Interrupt Status Register

I TIN Interrupt Status Register (TINPDIST) <Address: H'0080 1805> D 8 9 1 01 11 21 31 4 D 1 5 TIN1BEIS TIN1AEIS TIN0BEIS TIN0AEIS TIN1BIS TIN1AIS TIN0BIS TIN0AIS <When reset: H'00> D Bit Name Function R W

8 TIN1BEIS 0: Interrupt not requested

9 TIN1AEIS 1: Interrupt requested

10 TIN0BEIS

11 TIN0AEIS

12 TIN1BIS

13 TIN1AIS

14 TIN0BIS

15 TIN0AIS

W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. This register indicates whether there is an interrupt request for TIN input from any pin. (1) TIN input detection error interrupt request bits (D8, D9, D10, D11) These bits indicate interrupt requests from PD sensors. * Detailed description being written now. (2) TIN input detection interrupt request bits (D12, D13, D14, D15) These bits are set to 1 when the active edge on the corresponding TIN input pin is detected, thereby indicating that an interrupt has been requested for that input. These bits are cleared by writing 0 in software. PD MODULE

15-15 Rev.1.0 PDC input interrupt IRQ31 Data bus TIN1BEIS F/F TIN1BEIM F/Fb0 TIN1AEIS F/F TIN1AEIS F/Fb1 b10 TIN0BEIS F/F TIN0BEIM F/Fb2 b11 TIN0AEIS F/F TIN0AEIM F/Fb3 b12 TIN1BIS F/F TIN1BIM F/Fb4 (Level) 8-source inputs TINPD1CR <H'0080 1804> TINPD2CR <H'0080 1805> TIN1BEedge TINAE1edge TIN0Bedge TIN0Aedge TIN1Bedge b13 TIN1AIS F/F TIN1AIM F/Fb5 TIN1Aedge b14 TIN0BIS F/F TIN0BIM F/Fb6 TIN0Bedge b15 TIN0AIS F/F TIN0AIM F/Fb7 TIN0Aedge Figure 15.2.6 Block Diagram of the TIN Interrupt Circuit PD MODULE

15-16 Rev.1.0

15.2.6 DACNT Control Register

I DACNT Control Register (DACNTCR) <Address: H'0080 1806> D 0 123456 D 7 DACNTEN <When reset: H'00> D Bit Name Function R W 0-6 No functions assigned 0 –

7 DACNTEN 0: Stops count

(DACNT count enable) 1: Enables count This register controls enabling/disabling of the DACNT Counter to or not to count. When the DACNTEN bit is set to 1, the DACNT Counter starts counting down from its set value synchronously with the count period that has been set with the PRSA. Setting the DACNTEN bit to 0 disables the DACNT Counter, so that it stops counting, with the count value retained. PD MODULE

15-17 Rev.1.0

15.2.7 TPD Control Register

I TPD Control Register (TPDCR) <Address: H'0080 1807> This register selects operation modes of the TPD Counter and controls enabling/disabling of the counter. (1) TPDMD bit (D11) When this bit is set to 1, the TPD Counter (TPDCT) operates in PD sensor support mode. When this bit is set to 0, the TPD Counter (TPDCT) operates as an up-counter in free-running mode. Note 1: Rewriting this bit while the TPD Counter is operating is inhibited. Note 2: When using the counter in PD sensor support mode, make sure the DACNT Control Register (DACNTCR)'s DACNTEN bit and this register's TPDEN bit are set to 1 simultaneously by accessing the registers in halfword. (2) TPDEN bit (D15) When this bit is set to 1, the TPD Counter starts counting up from its set value synchronously with the clock period that has been set with the PRSB. Setting this bit to 0 disables the TPD Counter, so that it stops counting, with the count value retained. D 8 9 1 01 11 21 31 4 D 1 5 TPDMD TPDEN <When reset: H'00> D Bit Name Function R W 8-10 No functions assigned 0 –

11 TPDMD 0: Normal mode

(TPD counter operation mode) 1: PD sensor support mode 12-14 No functions assigned 0 –

15 TPDEN 0: Stops count

(TPD count enable) 1: Enables count PD MODULE

15-18 Rev.1.0

15.2.8 DACNT Counter

I DACNT Counter (DACNT) <Address: H'0080 1808> The DACNT Counter is an 8-bit down-counter which after being enabled, starts counting down from its set value synchronously with the count clock generated by the PRSA. The value of the DACNT Counter comprises the D-A converter's parameter table address value. When the DACNT Counter underflows after reaching the minimum count (DACNT = H'00), it is reloaded with the content of the DACNT Reload Register and restarts counting down from the newly set value. The diagram below shows operation of the DACNT Counter when the DACNT Counter and the DACNT Reload Register respectively have the values H'A0 and H'B0 set as their initial values. D 0 123456 D 7 DACNT <When reset: H'0000> D Bit Name Function R W 0-7 DACNT 8-bit counter value Figure 15.2.7 Example of DACNT Counter Operation PD MODULE H'FF H'00 DACNT Reload Register (DACNT) Counter H'B0 H'A0 DACNT Reload Register set value The counter counts down from the set value of the DACNT Reload Register The counter counts down from its set value Enabled

15-19 Rev.1.0

15.2.9 TPD Counter

I TPD Counter (TPDCT) <Address: H'0080 180E> The TPD Counter is a 16-bit up-counter which after being enabled, starts counting up from its set value synchronously with the count clock generated by the PRSB (free-running counter). The TPD Counter has two operation modes that can be selected with the TPD Control Register TPDMD bit. The following shows a typical operation of the TPD Counter in each mode. (1) Normal mode The TPD Counter operates as a free-running up-counter. Shown below is an example of count operation of the TPD Counter when it is enabled after setting H'6000 in it as its initial value. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 TPDCT <When reset: H'0000> D Bit Name Function R W 0-15 TPDCT 16-bit counter value Figure 15.2.8 Typical Operation of the TPD Counter in Normal Mode (2) PD sensor support mode * Detailed description being written now. PD MODULE H'FFFF H'0000 Counter H'6000 The counter counts up from H'0000 after it overflowed Prescaler B Enabled

15-20 Rev.1.0

15.2.10 TPD Measure Registers

I TPD Measure Register 0 (TPDMR0) <Address: H'0080 1810> I TPD Measure Register 1 (TPDMR1) <Address: H'0080 1812> I TPD Measure Register 2 (TPDMR2) <Address: H'0080 1814> I TPD Measure Register 3 (TPDMR3) <Address: H'0080 1816> I TPD Measure Register 4 (TPDMR4) <Address: H'0080 1818> I TPD Measure Register 5 (TPDMR5) <Address: H'0080 181A> I TPD Measure Register 6 (TPDMR6) <Address: H'0080 181C> I TPD Measure Register 7 (TPDMR7) <Address: H'0080 181E> D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TPDMR0-7 <When reset: H'0000> D Bit Name Function R W 0-15 TPDMR0-7 16-bit measured value The TPD Measure Registers 0, 2, 4, and 6 are used to capture the count value, so that when an event input on any TIN pin is detected, the count value at that point in time is latched into the corresponding measure register. The TPD Measure Registers 1, 3, 5, and 7 are used to capture the values of the TPD Measure Registers 0, 2, 4, and 6, so that when an event input on any TIN pin is detected, the register value at that point in time is latched into the corresponding measure register. Note:Even when the TPD Control Register TPDEN bit = 0 (counting disabled), measure operation is performed should an event occur on any TIN input pin. PD MODULE

15-21 Rev.1.0 The following shows a typical operation of TPD measure inputs. Figure 15.2.9 Example of TPD Operation for Measure Inputs PD MODULE H'A000 H'8000 H'6000 H'4000 TIN0A event occurs TIN0B event occurs TIN1A event occurs TIN1B event occurs TIN1A event occurs TIN1B event occurs TIN0A event occurs TIN0B event occurs TPDMR0 TPDMR1 TPDMR2 TPDMR3 TPDMR4 TPDMR5 TPDMR6 TPDMR7 Enable bit H'FFFF H'0000 TPD counter H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'4000 H'0000 H'6000 H'0000 H'8000 H'0000 H'A000 H'0000 H'A000 H'8000 H'6000 H'A000 H'8000 H'4000 H'6000 H'A000 Enabled

15-22 Rev.1.0

15.2.11 PD Calculation Interrupt Control Register

I PD Calculation Interrupt Control Register (PDICR) <Address: H'0080 1830> This register is used to control enabling/disabling of PD calculation interrupts. When any bit in this register is set to 1, the corresponding interrupt of the PD Interrupt Status Register is enabled. D 0 123456 D 7 APCM1IM SER1IM PCM1IM ACM1IM APCM0IM SER0IM PCM0IM ACM0IM <When reset: H'00> D Bit Name Function R W

0 APCM1IM 0: Disables interrupt

1 SER1IM 1: Enables interrupt

2 PCM1IM

3 ACM1IM

4 APCM0IM

5 SER0IM

6 PCM0IM

7 ACM0IM

15-23 Rev.1.0

15.2.12 PD Calculation Interrupt Status Register

I PD Calculation Interrupt Status Register (PDIST) <Address: H'0080 1831> When using PD calculation interrupts, inspect this register to know which interrupt request has been generated. (1) APCMiIS This bit is set to 1 when the ABDi value and the ABDi Compare Register's set value matched and the PITCHi value and the PITCHi Compare Register's set value also matched. This bit is cleared by writing 0. (2) SERiIS This bit is set to 1 when an S error occurred. * Detailed description about S errors being written now. (3) PCMiIS This bit is set to 1 when the PITCHi value and the PITCHi Compare Register's set value matched. For details about the PITCH compare operation, see the section of this manual where the PITCHi Compare Registers are discussed. This bit is cleared by writing 0. (4) ACMiIS This bit is set to 1 when the ABDi value and the ABDi Compare Register's set value matched. For details about the ABD compare operation, see the section of this manual where the ABDi Compare Registers are discussed. This bit is cleared by writing 0. Note: The mask function may be used for determining whether ABDi comparison matched in (1) and (4) above. For details, see the section of this manual where the ABD Mask Registers are discussed. D 8 9 1 01 11 21 31 4 D 1 5 APCM1IS SER1IS PCM1IS ACM1IS APCM0IS SER0IS PCM0IS ACM0IS <When reset: H'00> D Bit Name Function R W

8 APCM1IS 0: Interrupt not requested

9 SER1IS 1: Interrupt requested

10 PCM1IS

11 ACM1IS

12 APCM0IS

13 SER0IS

14 PCM0IS

15 ACM0IS

W= : Only writing 0 is effective. Writing 1 has no effect, the bit retains the value it had before writing. PD MODULE

15-24 Rev.1.0 PD calculation interrupt IRQ2 Data bus APCM1IS F/F APCM1IM F/Fb0 SER1IS F/F SER1IM F/Fb1 b10 PCM1IS F/F PCM1IM F/Fb2 b11 ACM1IS F/F ACM1IM F/Fb3 b12 APCM0IS F/F APCM0IM F/Fb4 (Level) 8-source inputs PDICR <H'0080 1830> PDIST <H'0080 1831> APCM1edge SER1edge PCM1edge ACM1edge APCM0edge b13 SER0IS F/F SER0IM F/Fb5 b14 PCM0IS F/F PCM0IM F/Fb6 b15 ACM0IS F/F ACM0IM F/Fb7 SER0edge PCM0edge ACM0edge Figure 15.2.10 Block Diagram of PD Circuit Calculation Complete Interrupt PD MODULE

15-25 Rev.1.0

15.2.13 Position Detection Accuracy Select Register

I Position Detection Accuracy Select Register (PDASR) <Address: H'0080 1832> This register is used when operating the module in combination with PD sensors. The PDA bits select the accuracy of position detection. The values set in the Prescalers A and B are determined by the selected accuracy. The table below shows the relationship between these set values and the sine waves generated by D-A conversion. D 0 123456 D 7 PDA <When reset: H'00> D Bit Name Function R W 0-5 No functions assigned 0 – 6-7 PDA 2'b00: 10-bit accuracy (Select position detection 2'b01: 11-bit accuracy accuracy) 2'b10: 12-bit accuracy 2'b11: Use inhibited PD MODULE When fcpu = 40 MHz Sine wave D-A conversion address D-A conversion data table Base count range Resolution count frequency usage range (PRS = H'00) 19.5KHz 5.0MHz (PRS = H'03) H'00 – H'FF (256 data) H'0000 – H'03FF 10bits 9.77KHz 2.5MHz (PRS = H'07) H'00 – H'FF (256 data) H'0000 – H'07FF 11bits 4.88KHz 1.25MHz (PRS = H'0F) H'00 – H'FF (256 data) H'0000 – H'0FFF 12bits When fcpu = 32 MHz Sine wave D-A conversion address D-A conversion data table Base count range Resolution count frequency usage range (PRS = H'00) 15.6KHz 4.0MHz (PRS = H'03) H'00 – H'FF (256 data) H'0000 – H'03FF 10bits 7.81KHz 2.0MHz (PRS = H'07) H'00 – H'FF (256 data) H'0000 – H'07FF 11bits 3.91KHz 1.0MHz (PRS = H'0F) H'00 – H'FF (256 data) H'0000 – H'0FFF 12bits

15-26 Rev.1.0

15.2.14 TEP Control Registers

I TEP0P Control Register (TEP0CR) <Address: H'0080 1842> I TEP1P Control Register (TEP1CR) <Address: H'0080 1882> D 0 123456 D 7 TEP0PM, TEP0PEN, TEP1PM TEP1PEN <When reset: H'00> D Bit Name Function R W 0-2 No functions assigned 0 –

3 TEP0PM, TEP1PM 0: Event count mode

(Operation mode) 1: PD sensor support mode 4-6 No functions assigned 0 –

7 TEP0PEN, TEP1PEN 0: Disables count

(Count enable) 1: Enables count These registers are used to select TEPiP counter operation modes and control enabling/disabling of count. (1) TEPiPM bit Setting this bit to 0 selects event count mode, in which the TEPiP Counter operates as an event counter (up-counter) counting events on the corresponding TIN input pin. Setting this bit to 1 selects PD sensor support mode, in which the TEPiP Counter operates corresponding to input from PD sensors. Note: Rewriting this bit while the TEPiP Counter is operating is inhibited. (2) TEPiPEN bit Setting this bit to 1 enables the TEPiP Counter for counting. When in event count mode, the counter counts up on each TIN event input starting from its set value; when in PD sensor support mode, the counter counts up synchronously with the clock generated by the prescaler (PRS0C or PRS1C). Setting this bit to 0 disables the TEPiP Counter, so that it stops counting, with the count value retained. PD MODULE

15-27 Rev.1.0 <When reset: H'00> D Bit Name Function R W 8-10 No functions assigned 0 –

11 TEP0MM, TEP1MM 0: Event count mode

(Operation mode) 1: PD sensor support mode 12-14 No functions assigned 0 –

15 TEP0MEN, TEP1MEN 0: Disables count

(Count enable) 1: Enables count I TEP0M Control Register (TEP0MCR) <Address: H'0080 1843> I TEP1M Control Register (TEP1MCR) <Address: H'0080 1883> D 8 9 1 01 11 21 31 4 D 1 5 TEP0MM, TEP0MEN, TEP1MM TEP1MEN These registers are used to select TEPiM counter operation modes and control enabling/disabling of count. (1) TEPiMM bit Setting this bit to 0 selects event count mode, in which the TEPiM Counter operates as an event counter (up-counter) counting events on the corresponding TIN input pin. Setting this bit to 1 selects PD sensor support mode, in which the TEPiM Counter operates corresponding to input from PD sensors. Note: Rewriting this bit while the TEPiM Counter is operating is inhibited. (2) TEPiMEN bit Setting this bit to 1 enables the TEPiM Counter for counting. When in event count mode, the counter counts up on each TIN event input starting from its set value; when in PD sensor support mode, the counter counts up synchronously with the clock generated by the prescaler (PRS0C or PRS1C). Setting this bit to 0 disables the TEPiM Counter, so that it stops counting, with the count value retained. PD MODULE

15-28 Rev.1.0 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TEP0P, TEP1P, TEP0M, TEP1M <When reset: H'00> D Bit Name Function R W 0-15 TEP0P 16-bit counter value TEP1P TEP0M TEP1M The TEPiP/TEPiM Counters are a 16-bit up-counter. The TEPiP/TEPiM Counters have two operations that can be selected with the TEPiP/TEPiM Control Register TEPiPEN/TEPiMEN bit. A typical operation of the TEPiP/TEPiM Counters in each mode is shown. PD MODULE

15.2.15 TEP Counters

I TEP0P Counter (TEP0PCT) <Address: H'0080 1844> I TEP1P Counter (TEP1PCT) <Address: H'0080 1884> I TEP0M Counter (TEP0MCT) <Address: H'0080 1846> I TEP1M Counter (TEP1MCT) <Address: H'0080 1886>

15-29 Rev.1.0 (1) Event count mode The counter counts up each time an event input on the corresponding TIN pin is detected. Figure 15.2.11 Event Count Mode (2) PD sensor support mode *Detailed description being written now. PD MODULE A B A+1 B+1 C D C+1 TIN0A event occurs TIN0B event occurs TIN1A event occurs TIN1B event occurs TIN0A event occurs TIN0B event occurs TIN1A event occurs TIN1B event occurs D+1 A+2 B+2 C+3 D+4 TEP0PEN /TEP0MEN TEP1PEN /TEP1MEN TEP0P TEP0M TEP1P TEP1M

15-30 Rev.1.0

15.2.16 PD Data Updating Disable Event Select Registers

I PD0 Data Updating Disable Event Select Register (PDNSEL0R) <Address: H'0080 1848> I PD1 Data Updating Disable Event Select Register (PDNSEL1R) <Address: H'0080 1888> D 0 123456 D 7 PDNSEL0,PDNSEL1 <When reset: H'00> D Bit Name Function R W 0-5 No functions assigned 0 – 6-7 PDNSEL0, PDNSEL1 00: No selection (Select data updating disable event) 01: TOM0_6 timer event 10: TIN16 event input 11: Settings inhibited The PD calculation block always performs calculation based on the latest measured value, but the register in which the calculation result is stored can have its data updated under software control. This register is used to select an event that disables updating of said register data. Consequently, the data stored in the register at the time the selected event occurred can be retained until updating is reenabled. Updating of the register data is enabled by setting the PDi Data Updating Control Register directly in software. (1) No selection (PDNSELi = H'00) When data updating all needs to be enabled/disabled in software, set the PDNSELi bits to '00.' (2) TOM0_6 timer event (PDNSELi = H'01) Data updating is disabled by occurrence of TOM0_6 timer event. (3) TIN16 event input (PDNSELi = H'10) Data updating is disabled by occurrence of TIN16 event input. (4) Settings inhibited (PDNSELi = H'11) Setting the PDNSELi bits to '11' is inhibited. PD MODULE

15-31 Rev.1.0

15.2.17 PD Data Updating Control Registers

I PD0 Data Updating Control Register (PDNCNT0R) <Address: H'0080 1849> I PD1 Data Updating Control Register (PDNCNT1R) <Address: H'0080 1889> D 8 9 1 01 11 21 31 4 D 1 5 PDNCNT0,PDNCNT1 <When reset: H'00> D Bit Name Function R W 8-13 No functions assigned 0 – 14-15 PDNCNT0, PDNCNT1 0: Enables data updating (Data updating enable) 1: Disables data updating This register controls updating of the data stored in the PD calculation result register. [Set conditions]

• The bits in this register can be set by writing 1 in software. This is always possible regardless of how the PDi Data Updating Disable Event Select Register is set.
• When TOM0_6 timer event has been selected with the PDi Data Updating Disable Event Select Register, the bits in this register are set to 1 by occurrence of TOM0_6 timer event. If this timer event occurs at the same time the PDNCNTi bits are cleared to 0 in software, the former has priority (the bit is set).
• When external input has been selected with the PDi Data Updating Disable Event Select Register, the bits in this register are set to 1 by occurrence of external input event. If this external input event occurs at the same time the PDNCNTi bits are cleared to 0 in software, the former has priority (the bit is set). PD MODULE

15-32 Rev.1.0

15.2.18 ABD Mask Registers

I ABD0 Mask Register (ABD0MK) <Address: H'0080 184A> I ABD1 Mask Register (ABD1MK) <Address: H'0080 188A> D 0 123456 D 7 ABD0MK, ABD1MK <When reset: H'00> D Bit Name Function R W 0-7 ABD0MK, ABD1MK 0: Mask (ABD compare match mask) 1: Compare When comparing the ABDiLT Register and ABDi Compare Register values to determine whether they match, this register may be used to mask the low-order bits of the comparison result. When any bit in this register is set to 0, its corresponding bit of the comparison result is handled as "Don't care." The diagram below shows the relationship of bits between the ABDi Mask Register and the ABDiLT Register and ABDi Compare Register. Figure 15.2.12 Data Formats when Comparing Register Values to Determine Matching PD MODULE D0 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12D1 D13 D14 D15 D0 D2 D3 D4 D5 D6 D7D1 D0 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12D1 D13 D14 D15 The corresponding bits can be masked The corresponding bits can be masked These bits are not used for determination These bits are not used for determination ABDi Compare Register ABDi Mask Register ABDiLT Register Cannot be masked

15-33 Rev.1.0

15.2.19 S Error Detection Range Select Registers

I S Error 0 Detection Range Select Register (SNEW0MK) <Address: H'0080 184B> I S Error 1 Detection Range Select Register (SNEW1MK) <Address: H'0080 188B> D 8 9 1 01 11 21 31 4 D 1 5 ABD0MK, ABD1MK <When reset: H'00> D Bit Name Function R W 8-15 SNEW0MK Settings Detection range (Note) SNEW1MK b'00000000 : SS 256, SS -257 (Select S error b'10000000 : SS 128, SS -129 detection range) b'11000000 : SS 64, SS -65 b'11100000 : SS32, SS -33 b'11110000 : SS16, SS -17 b'11111000 : SS8, SS -9 b'11111100 : SS4, SS -5 b'11111110 : SS2, SS -3 b'11111111 : SS1, SS -2 Note: The detection ranges shown here assume the SSLT Register D11 bit is the least significant bit. These registers are used to set the S error detection range.

• About the definition of S error * Detailed description being written now. PD MODULE

15-34 Rev.1.0

15.2.20 ABD Compare Registers

I ABD0 Compare Register (ABD0CM) <Address: H'0080 184C> I ABD1 Compare Register (ABD1CM) <Address: H'0080 188C> D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 ABD0MK, ABD1MK <When reset: H'0000> D Bit Name Function R W 0-3 No functions assigned 0 – 4-5 ABD0CM, ABD1CM 12-bit compare value The value set in this register is compared with the ABDiLT Register value and when they match, an ABD compare match interrupt request is set. At this time, the low-order bits of the comparison result can be masked out as "Don't care" bits by using the ABDi Mask Register. Note 1: When setting the ABDiCM Register, always be sure to set the bits in this register to 0 that correspond to those which are set to 0 in the ABDi Mask Register. Note 2: ABD compare match processing is always performed based on the latest measured value, regardless of how the PDi Data Updating Control Register is set. Note 3: Pay attention to the relationship of bits between the ABDi Mask Register and ABDiLT Register. (For details, see the description of the ABD Mask Register.) PD MODULE

15-35 Rev.1.0

15.2.21 PITCH Compare Registers

I PITCH0 Compare Register (PITCH0CMR) <Address: H'0080 184E> I PITCH1 Compare Register (PITCH1CMR) <Address: H'0080 188E> The value set in this register is compared with the PITCHi Counter Register value and when they match, a PITCH compare match interrupt request is set. Note: PITCH compare match processing is always performed based on the latest measured value, regardless of how the PDi Data Updating Control Register is set. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 PIT0CM, PIT1CM <When reset: H'0000> D Bit Name Function R W 0-15 PIT0CM, PIT1CM 16-bit compare value PD MODULE

15-36 Rev.1.0

15.2.22 FDLT Registers

I FDLT0 Register (FDLT0) <Address: H'0080 1872> I FDLT1 Register (FDLT1) <Address: H'0080 18B2> This register is used to store the value equivalent to a change of position. Note: To read data from this register, access it as signed halfword data. D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 FD0, FD1 <When reset: H'0000> D Bit Name Function R W 0-11 FD0, FD1 12-bit FD value – 12-15 No functions assigned 0 – PD MODULE

15-37 Rev.1.0

15.2.23 PITCHLT Registers

I PITCHLT0 Register (PITCHLT0) <Address: H'0080 1874> I PITCHLT1 Register (PITCHLT1) <Address: H'0080 18B4> <When reset: H'0000> D Bit Name Function R W 0-15 PITCH0, PITCH1 16-bit PITCH counter value Note 1: This register must always be accessed in halfwords. Note 2: When performing predictive calculations, access the PITCHLT and ABDLT Registers wordwise to read out data by using an LD instruction. The PITCH counter value is stored in this register.

• PITCH Counter The PITCHi Counter is an up/down-counter whose count direction is determined by comparing the two high-order bits of the latest and the previous ABDiLTD Register values. The following shows how the up/down direction actually is determined. PD MODULE

New {AB0, AB1} Old {AB0, AB1} Count value LL HH +1 HH LL –1 D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 PITCH0, PITCH1

15-38 Rev.1.0

15.2.24 ABDLT Registers

I ABDLT0 Register (ABDLT0) <Address: H'0080 1876> I ABDLT1 Register (ABDLT1) <Address: H'0080 18B6> The measured position information is stored in the D0-D11 bits of this register. The D12-D15 bits are always 0 when read out. However, it is the D11-D15 bits when 11-bit accuracy is selected or the D10-D15 bits when 10-bit accuracy is selected that are always 0 when read out. D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 ABD0, ABD1 <When reset: H'0000> D Bit Name Function R W 0-15 ABD0, ABD1 12-bit ABD value – Note 1: This register must always be accessed in halfwords. Note 2: When performing predictive calculations, access the PITCHLT and ABDLT Registers wordwise to read out data by using an LD instruction. PD MODULE

15-39 Rev.1.0

15.2.25 RSUMLT Registers

I RSUMLT0 Register (RSUMLT0) <Address: H'0080 1878> I RSUMLT1 Register (RSUMLT1) <Address: H'0080 18B8> This register is used to store the correction factor necessary for predictive calculations. The predictive position I is calculated using the value in this register by the equation below. I = {ABDLT, ABDLT} + (FDLT × RSUMLT) /T Note 1: T = H'1000. Note 2: Access the PITCHLT and ABDLT Registers wordwise to read out data by using an LD instruction. D 0 123456789 1 0 1 1 1 2 1 3 1 4 D 1 5 RSUM0, RSUM1 <When reset: H'0000> D Bit Name Function R W 0-15 RSUM0, RSUM1 16-bit correction factor – Note: This register must always be accessed as signed halfword data PD MODULE

15-40 Rev.1.0

15.2.26 SSLT Registers

I SSLT0 Register (SSLT0) <Address: H'0080 187A> I SSLT1 Register (SSLT1) <Address: H'0080 18BA> This register is used to store the latest value of the SSLT data used for S error judgment. The four low-order bits are 0 when read out. D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 SSLT0, SSLT1 <When reset: H'0000> D Bit Name Function R W 0-11 SSLT0, SSLT1 12-bit SSLT value – 12-15 No functions assigned 0 – Note: This register must always be accessed in halfwords. PD MODULE

15-41 Rev.1.0

15.3 Initialization for PD Sensor Support

When using the PD module in combination with PD sensors, follow the initialization procedure described below to initialize it. (1) Setting the Input/output Port Operation Mode Register The TINA0, TENB0, TINA1, and TENB1 pins are dual-function pins shared with input/output ports each. Therefore, select the function of these pins using the said register. (2) Setting the D-A Converter, Parameter Table, and D-A Control Register To generate sine waves, set the data of the D-A Converter Parameter Table (0-255) in the DA0 Data Registers 0-255. Then set DA0 for continuous mode and enable it for output using the D-A Control Register for the D-A Converter. Note 1: Use all of the D-A Converter Parameter Table (0-255) to define the sine wave. Note 2: For details on how to set the D-A Control Register, see Chapter 16, "D-A Converters." (3) Setting the Position Detection Accuracy Select Register Select the accuracy of position detection from 10-bit through 12-bit resolutions. (4) Setting the Prescalers A and B Use the Prescaler A to set the address count period for the DA0 Data Register. The value to be set in the Prescaler A depends on the selected accuracy of position detection, so set the appropriate value as shown below.

• When 10-bit accuracy is selected: H'03
• When 11-bit accuracy is selected: H'07
• When 12-bit accuracy is selected: H'0F For each of these settings, the sine wave period Fsin is given by the equation below. Fsin = Fcpu/ {2 × (1+PRSA) × 256} (Fcpu: CPU clock frequency) Use the Prescaler B to set the count period of the measure counter TPDCT. Always be sure to set the value H'00 in this register. In this case, the TPDCT count period is Fcpu/2. (5) Setting the DACNT Reload Register Because all of the DA0 Data Registers 0-255 must be used to generate sine waves, set the value H'FF in this register. Each time the DACNT counter underflows, it is reloaded with the content of this register and starts counting down over again. (6) Setting the DACNT Counter Register Set the value H'FF in this register as the DACNT Counter's initial value. Consequently, an analog voltage value corresponding to the value set in DA0 Data Register 255 is output from the DA0 pin. PD MODULE

15-42 Rev.1.0 (7) Setting the PD related registers

• Setting the Prescalers 0C and 1C Always write the value H'00 in these registers.
• Setting the PD0 and PD1 Data Updating Disable Event Select Registers Use these registers to set data-updating disable events.
• Setting the PD0 and PD1 Data Updating Control Registers Use these registers to enable or disable updating of PD data.
• Setting the ABD0 and ABD1 Mask Registers When using the ABD compare match function, select the bits to be masked.
• Setting the S Error 0 and S Error 1 Detection Range Select Registers Use these registers to set the S error detection range.
• Setting the ABD0 and ABD1 Compare Registers When using ABD compare match, set the compare value in these registers.
• Setting the PITCH0 and PITCH1 Compare Registers When using PITCH compare match, set the compare value in these registers. (8) Setting the Interrupt Controller When using PD interrupts, set the priority level of each interrupt. (9) Setting the TIN and PD Interrupt Control Registers Use the TIN Interrupt Control Register to enable or disable TIN related interrupts. Use the PD Interrupt Control Register to enable or disable PD calculation related interrupts. (10) Setting the DACNT and TPD Control Registers Set the DACNT Control Register DACNTEN bit to enable the counter. The DACNT Counter starts counting down, generating sine waves. Set the value H'11 in the TPD Control Register to enable counting in PD sensor support mode. Note: Set these two registers simultaneously by using a STH instruction. PD MODULE

15-43 Rev.1.0 (11) Setting the TEP0P, TEP0M, TEP1P, and TEP1M Control Registers Set the value H'11 in each register to enable counting in PD sensor support mode. Note: Use all of the data tables 0-255 to define the sine wave. (12) Setting the TIN Input Processing Control Register Select rising-edge detection for each TIN input. Figure 15.3.1 PD Sensor Support Initialization Flow PD MODULE Initialization for PD sensor support Set Parameter Table Data and DA Control Register Set Position Detection Accuracy Select Register Set Prescalers A and B Set DACNT Reload Register Set DACNT Register Set the following registers

• Prescalers 0C and 1C PD0,1 Data Updating Disable Event Select Registers
• PD0,1 Data Updating Control Registers
• ABD0,1 Mask Registers S Error 0,1 Detection Range Select Registers
• ABD0,1 Compare Registers
• PITCH0,1 Compare Registers Set Interrupt Controller
• Set TIN and PD Interrupt Control Registers Set TIN Input Processing Control Register Set Input/output Port Operation Mode Register Initialization complete
• Set DACNT and TPD Control Registers
• Set TEP0P , TEP0M, TEP1P , and TEP1M Control Registers G Parameter Table Data Set table data necessary to generate sine wave G DA Control Register Select continuous mode for DA0 and enable its output Select from 10, 11, or 12-bit resolutions G Prescaler A Set H'03 for 10-bit accuracy Set H'07 for 11-bit accuracy Set H'0F for 12-bit accuracy G Set H'00 in Prescaler B Set H'FF in DACNT Reload Register Set H'00 in Prescalers 0C and 1C Set interrupt priority G TIN Interrupt Control Register
• Enable/disable TIN input detection interrupt
• Enable/disable TIN input error detection interrupt G PD Interrupt Control Register
• Enable/disable ABD compare match interrupt
• Enable/disable PITCH compare match interrupt
• Enable/disable S error interrupt Select rising-edge detection Set these registers simultaneously by using STH instruction
• Set TEP0P and TEP0M Control Registers simultaneously by using STH instruction
• Set TEP1P and TEP1M Control Registers simultaneously by using STH instruction

15-44 Rev.1.0

15.4 Precautions on Using the PD Module

• PD calculation processing is always performed based on the latest measured value regardless of how the PDi Data Updating Control Register is set. Therefore, even after disabling data updating, it is possible to read out the calculation result based on the latest event input by altering register settings back again. In no case will event inputs pass undetected even when data updating is disabled.
• When performing predictive calculations, be sure to disable updating of PD data before reading out the FDLT, PITCHLT, ABDLT, and RSUMLT Registers. PD MODULE

16.1 Outline of the D-A Converters

16.2 D-A Converter Related

16.3 Functional Description of the

16-2 Rev.1.0 The 32172/32173 contains two 8-bit D-A converters (D-A0 and D-A1 Converters). D-A conversion is performed in either single mode or continuous mode (D-A0 Converter only). Single mode: The analog values corresponding to the D-A Converter Register (DA0CNV, DA1CNV) values are output from the DA0 and DA1 pins. Continuous mode:The values set in the DA0 Data Register n (n = 0-255) are sequentially converted to produce analog values. (Continuous mode is available for only the D-A0 Converter, and not for the D-A1 Converter.) A Converters. Figure 16.1.3 shows an equivalent circuit of the D-A Converters. D-A CONVERTERS Table 16.1.1 Outline of the D-A Converters Item Content Analog output 2 channels D-A conversion method R-2R method Resolution 8 bits Output voltage 0–VREF Conversion mode Single mode Continuous mode (Note) Parameter table 256-byte parameter table for output use Conversion speed TBD Note: Available for only the D-A0 Converter, and not available for the D-A1 Converter.

16-3 Rev.1.0 D-A0 Conversion Register D-A0 Data Register 0 D-A0 Data Register 255 8-bit R-2R Resistor Ladder DA0ON DA0/(AD1IN4) Internal Data Bus Single mode Continuous mode 256 bytes DA Counter (DACNT)PRSA AD1IN4 PD Module (TPD reset)BCLK 88 8 Figure 16.1.1 Block Diagram of the D-A0 Converter Figure 16.1.2 Block Diagram of the D-A1 Converter D-A CONVERTERS DA1/(AD1IN5) Internal Data Bus AD1IN5 8-bit R-2R Resistor Ladder

16-4 Rev.1.0 "1" "0" 2R 2R 2R 2R 2R 2R 2R 2R RRRRRRR2 R "0" "1" MSB LSB DA0 AVSS VREF D-A0 Conversion Register DA0 analog output enable bit Note 1: This applies to the case where the value of the D-A0 Conversion Register is H'2A. Note 2: This circuit is the same as for the D-A1 Converter. Note 3: When not using the D-A converters, set the D-A Control Register's analog output enable bit (DA0ON, DA1ON) to 0 and write the data H'00 to the D-A Conversion Register (DA0CNV, DA1CNV) to prevent current from flowing into the R-2R resistors. This helps to minimize the unwanted current consumption. Figure 16.1.3 Equivalent Circuit Diagram of the D-A0 Converter D-A CONVERTERS

16-5 Rev.1.0

16.2 D-A Converter Related Registers

A D-A converter related register map is shown below. +0 address +1 address D0 D7 D8 D15Address H'0080 1C7A H'0080 1C78 H'0080 1C7C H'0080 1D00 H'0080 1D0A H'0080 1D08 H'0080 1D06 H'0080 1D04 H'0080 1D0C H'0080 1D10 H'0080 1D12 H'0080 1D18 H'0080 1D16 H'0080 1D0E H'0080 1D14 H'0080 1D1C H'0080 1D20 H'0080 1D1E H'0080 1D24 H'0080 1D26 H'0080 1D28 H'0080 1D2C H'0080 1D2E H'0080 1D34 H'0080 1D32 H'0080 1D2A H'0080 1D30 H'0080 1D22 H'0080 1D36 H'0080 1D38 H'0080 1D3C H'0080 1D3E H'0080 1D44 H'0080 1D42 H'0080 1D3A H'0080 1D40 H'0080 1D46 H'0080 1D48 H'0080 1D4C H'0080 1D4A H'0080 1D1A H'0080 1D02 Blank areas are reserved for future use. D-A0 Conversion Register (DA0CNV) D-A1 Conversion Register (DA1CNV) D-A Control Register (DACR) D-A0 Data Register 0 (DA0DT0) D-A0 Data Register 1 (DA0DT1) D-A0 Data Register 2 (DA0DT2) D-A0 Data Register 4 (DA0DT4) D-A0 Data Register 3 (DA0DT3) D-A0 Data Register 6 (DA0DT6) D-A0 Data Register 5 (DA0DT5) D-A0 Data Register 7 (DA0DT7) D-A0 Data Register 8 (DA0DT8) D-A0 Data Register 9 (DA0DT9) D-A0 Data Register 10 (DA0DT10) D-A0 Data Register 11 (DA0DT11) D-A0 Data Register 12 (DA0DT12) D-A0 Data Register 13 (DA0DT13) D-A0 Data Register 14 (DA0DT14) D-A0 Data Register 15 (DA0DT15) D-A0 Data Register 16 (DA0DT16) D-A0 Data Register 17 (DA0DT17) D-A0 Data Register 18 (DA0DT18) D-A0 Data Register 19 (DA0DT19) D-A0 Data Register 20 (DA0DT20) D-A0 Data Register 21 (DA0DT21) D-A0 Data Register 22 (DA0DT22) D-A0 Data Register 23 (DA0DT23) D-A0 Data Register 24 (DA0DT24) D-A0 Data Register 25 (DA0DT25) D-A0 Data Register 26 (DA0DT26) D-A0 Data Register 27 (DA0DT27) D-A0 Data Register 28 (DA0DT28) D-A0 Data Register 29 (DA0DT29) D-A0 Data Register 30 (DA0DT30) D-A0 Data Register 31 (DA0DT31) D-A0 Data Register 32 (DA0DT32) D-A0 Data Register 33 (DA0DT33) D-A0 Data Register 34 (DA0DT34) D-A0 Data Register 35 (DA0DT35) D-A0 Data Register 36 (DA0DT36) D-A0 Data Register 37 (DA0DT37) D-A0 Data Register 38 (DA0DT38) D-A0 Data Register 39 (DA0DT39) D-A0 Data Register 40 (DA0DT40) D-A0 Data Register 41 (DA0DT41) D-A0 Data Register 42 (DA0DT42) D-A0 Data Register 43 (DA0DT43) D-A0 Data Register 44 (DA0DT44) D-A0 Data Register 45 (DA0DT45) D-A0 Data Register 46 (DA0DT46) D-A0 Data Register 47 (DA0DT47) D-A0 Data Register 48 (DA0DT48) D-A0 Data Register 49 (DA0DT49) D-A0 Data Register 50 (DA0DT50) D-A0 Data Register 51 (DA0DT51) D-A0 Data Register 52 (DA0DT52) D-A0 Data Register 53 (DA0DT53) D-A0 Data Register 54 (DA0DT54) D-A0 Data Register 55 (DA0DT55) D-A0 Data Register 56 (DA0DT56) D-A0 Data Register 63 (DA0DT63)D-A0 Data Register 62 (DA0DT62) D-A0 Data Register 61 (DA0DT61)D-A0 Data Register 60 (DA0DT60) D-A0 Data Register 59 (DA0DT59)D-A0 Data Register 58 (DA0DT58) D-A0 Data Register 57 (DA0DT57) D-A0 Data Register 75 (DA0DT75)D-A0 Data Register 74 (DA0DT74) D-A0 Data Register 73 (DA0DT73)D-A0 Data Register 72 (DA0DT72) D-A0 Data Register 71 (DA0DT71)D-A0 Data Register 70 (DA0DT70) D-A0 Data Register 69 (DA0DT69)D-A0 Data Register 68 (DA0DT68) D-A0 Data Register 64 (DA0DT64) D-A0 Data Register 67 (DA0DT67) D-A0 Data Register 65 (DA0DT65) D-A0 Data Register 66 (DA0DT66) D-A0 Data Register 77 (DA0DT77)D-A0 Data Register 76 (DA0DT76) D-A0 Data Register 79 (DA0DT79)D-A0 Data Register 78 (DA0DT78)H'0080 1D4E H'0080 1808 H'0080 1800 H'0080 1806 H'0080 1802 H'0080 1804 Prescaler Register A (PRSA) DACNT Reload Register (DACNTRL) DACNT Control Register (DACNTCR) DACNT Counter (DACNT) Figure 16.2.1 SFR Area Register Map (1/3) D-A CONVERTERS

16-6 Rev.1.0 +0 address +1 address D0 D7 D8 D15 Address H'0080 1D52 H'0080 1D50 H'0080 1D54 H'0080 1D56 H'0080 1D60 H'0080 1D5E H'0080 1D5C H'0080 1D5A H'0080 1D62 H'0080 1D68 H'0080 1D6A H'0080 1D70 H'0080 1D6E H'0080 1D66 H'0080 1D6C H'0080 1D74 H'0080 1D78 H'0080 1D76 H'0080 1D7C H'0080 1D7E H '0080 1D80 H '0080 1D84 H '0080 1D86 H '0080 1D8C H '0080 1D8A H '0080 1D82 H '0080 1D88 H'0080 1D7A H '0080 1D8E H'0080 1D90 H'0080 1D94 H '0080 1D96 H '0080 1D9C H '0080 1D9A H '0080 1D92 H '0080 1D98 H '0080 1D9E H'0080 1DA0 H'0080 1DA4 H'0080 1DA2 H'0080 1D72 H'0080 1D58 D-A0 Data Register 80 (DA0DT80) D-A0 Data Register 82 (DA0DT82) D-A0 Data Register 84 (DA0DT84) D-A0 Data Register 90 (DA0DT90) D-A0 Data Register 91 (DA0DT91) D-A0 Data Register 92 (DA0DT92) D-A0 Data Register 94 (DA0DT94) D-A0 Data Register 93 (DA0DT93) D-A0 Data Register 96 (DA0DT96) D-A0 Data Register 95 (DA0DT95) D-A0 Data Register 97 (DA0DT97) D-A0 Data Register 98 (DA0DT98) D-A0 Data Register 99 (DA0DT99) D-A0 Data Register 100 (DA0DT100) D-A0 Data Register 101 (DA0DT101) D-A0 Data Register 102 (DA0DT102) D-A0 Data Register 103 (DA0DT103) D-A0 Data Register 104 (DA0DT104) D-A0 Data Register 105 (DA0DT105) D-A0 Data Register 106 (DA0DT106) D-A0 Data Register 107 (DA0DT107) D-A0 Data Register 108 (DA0DT108) D-A0 Data Register 109 (DA0DT109) D-A0 Data Register 110 (DA0DT110) D-A0 Data Register 111 (DA0DT111) D-A0 Data Register 112 (DA0DT112) D-A0 Data Register 113 (DA0DT113) D-A0 Data Register 114 (DA0DT114) D-A0 Data Register 115 (DA0DT115) D-A0 Data Register 116 (DA0DT116) D-A0 Data Register 117 (DA0DT117) D-A0 Data Register 118 (DA0DT118) D-A0 Data Register 119 (DA0DT119) D-A0 Data Register 120 (DA0DT120) D-A0 Data Register 121 (DA0DT121) D-A0 Data Register 122 (DA0DT122) D-A0 Data Register 123 (DA0DT123) D-A0 Data Register 124 (DA0DT124) D-A0 Data Register 125 (DA0DT125) D-A0 Data Register 126 (DA0DT126) D-A0 Data Register 127 (DA0DT127) D-A0 Data Register 128 (DA0DT128) D-A0 Data Register 129 (DA0DT129) D-A0 Data Register 130 (DA0DT130) D-A0 Data Register 131 (DA0DT131) D-A0 Data Register 132 (DA0DT132) D-A0 Data Register 133 (DA0DT133) D-A0 Data Register 134 (DA0DT134) D-A0 Data Register 135 (DA0DT135) D-A0 Data Register 136 (DA0DT136) D-A0 Data Register 137 (DA0DT137) D-A0 Data Register 138 (DA0DT138) D-A0 Data Register 139 (DA0DT139) D-A0 Data Register 140 (DA0DT140) D-A0 Data Register 141 (DA0DT141) D-A0 Data Register 142 (DA0DT142) D-A0 Data Register 143 (DA0DT143) D-A0 Data Register 144 (DA0DT144) D-A0 Data Register 145 (DA0DT145) D-A0 Data Register 146 (DA0DT146) D-A0 Data Register 153 (DA0DT153)D-A0 Data Register 152 (DA0DT152) D-A0 Data Register 151 (DA0DT151)D-A0 Data Register 150 (DA0DT150) D-A0 Data Register 149 (DA0DT149)D-A0 Data Register 148 (DA0DT148) D-A0 Data Register 147 (DA0DT147) D-A0 Data Register 165 (DA0DT165)D-A0 Data Register 164 (DA0DT164) D-A0 Data Register 163 (DA0DT163)D-A0 Data Register 162 (DA0DT162) D-A0 Data Register 161 (DA0DT161)D-A0 Data Register 160 (DA0DT160) D-A0 Data Register 159 (DA0DT159)D-A0 Data Register 158 (DA0DT158) D-A0 Data Register 154 (DA0DT154) D-A0 Data Register 157 (DA0DT157) D-A0 Data Register 155 (DA0DT155) D-A0 Data Register 156 (DA0DT156) D-A0 Data Register 167 (DA0DT167)D-A0 Data Register 166 (DA0DT166) D-A0 Data Register 169 (DA0DT169)D-A0 Data Register 168 (DA0DT168) H'0080 1DA6 H'0080 1DA8 D-A0 Data Register 81 (DA0DT81) D-A0 Data Register 83 (DA0DT83) D-A0 Data Register 85 (DA0DT85) D-A0 Data Register 86 (DA0DT86) D-A0 Data Register 88 (DA0DT88) D-A0 Data Register 87 (DA0DT87) D-A0 Data Register 89 (DA0DT89) H'0080 1D64 Figure 16.2.2 SFR Area Register Map (2/3) D-A CONVERTERS

16-7 Rev.1.0 +0 address +1 address D0 D7 D8 D15 Address H'0080 1DAC H'0080 1DAA H'0080 1DAE H'0080 1DB0 H'0080 1DBA H'0080 1DB8 H'0080 1DB6 H'0080 1DB4 H'0080 1DBC H'0080 1DC2 H'0080 1DC4 H'0080 1DCA H'0080 1DC8 H'0080 1DC0 H'0080 1DC6 H'0080 1DCE H'0080 1DD2 H'0080 1DD0 H'0080 1DD6 H'0080 1DD8 H '0080 1DDA H '0080 1DDE H '0080 1DE0 H '0080 1DE6 H '0080 1DE4 H '0080 1DDC H '0080 1DE2 H'0080 1DD4 H '0080 1DE8 H'0080 1DEA H'0080 1DEE H '0080 1DF0 H '0080 1DF6 H '0080 1DF4 H '0080 1DEC H '0080 1DF2 H '0080 1DF8 H'0080 1DFA H'0080 1DFE H'0080 1DFC H'0080 1DCC H'0080 1DB2 D-A0 Data Register 170 (DA0DT170) D-A0 Data Register 172 (DA0DT172) D-A0 Data Register 174 (DA0DT174) D-A0 Data Register 180 (DA0DT180) D-A0 Data Register 181 (DA0DT181) D-A0 Data Register 182 (DA0DT182) D-A0 Data Register 184 (DA0DT184) D-A0 Data Register 183 (DA0DT183) D-A0 Data Register 186 (DA0DT186) D-A0 Data Register 185 (DA0DT185) D-A0 Data Register 187 (DA0DT187) D-A0 Data Register 188 (DA0DT188) D-A0 Data Register 189 (DA0DT189) D-A0 Data Register 190 (DA0DT190) D-A0 Data Register 191 (DA0DT191) D-A0 Data Register 192 (DA0DT192) D-A0 Data Register 193 (DA0DT193) D-A0 Data Register 194 (DA0DT194) D-A0 Data Register 195 (DA0DT195) D-A0 Data Register 196 (DA0DT196) D-A0 Data Register 197 (DA0DT197) D-A0 Data Register 198 (DA0DT198) D-A0 Data Register 199 (DA0DT199) D-A0 Data Register 200 (DA0DT200) D-A0 Data Register 201 (DA0DT201) D-A0 Data Register 202 (DA0DT202) D-A0 Data Register 203 (DA0DT203) D-A0 Data Register 204 (DA0DT204) D-A0 Data Register 205 (DA0DT205) D-A0 Data Register 206 (DA0DT206) D-A0 Data Register 207 (DA0DT207) D-A0 Data Register 208 (DA0DT208) D-A0 Data Register 209 (DA0DT209) D-A0 Data Register 210 (DA0DT210) D-A0 Data Register 211 (DA0DT211) D-A0 Data Register 212 (DA0DT212) D-A0 Data Register 213 (DA0DT213) D-A0 Data Register 214 (DA0DT214) D-A0 Data Register 215 (DA0DT215) D-A0 Data Register 216 (DA0DT216) D-A0 Data Register 217 (DA0DT217) D-A0 Data Register 218 (DA0DT218) D-A0 Data Register 219 (DA0DT219) D-A0 Data Register 220 (DA0DT220) D-A0 Data Register 221 (DA0DT221) D-A0 Data Register 222 (DA0DT222) D-A0 Data Register 223 (DA0DT223) D-A0 Data Register 224 (DA0DT224) D-A0 Data Register 225 (DA0DT225) D-A0 Data Register 226 (DA0DT226) D-A0 Data Register 227 (DA0DT227) D-A0 Data Register 228 (DA0DT228) D-A0 Data Register 229 (DA0DT229) D-A0 Data Register 230 (DA0DT230) D-A0 Data Register 231 (DA0DT231) D-A0 Data Register 232 (DA0DT232) D-A0 Data Register 233 (DA0DT233) D-A0 Data Register 234 (DA0DT234) D-A0 Data Register 235 (DA0DT235) D-A0 Data Register 236 (DA0DT236) D-A0 Data Register 243 (DA0DT243)D-A0 Data Register 242 (DA0DT242) D-A0 Data Register 241 (DA0DT241)D-A0 Data Register 240 (DA0DT240) D-A0 Data Register 239 (DA0DT239)D-A0 Data Register 238 (DA0DT238) D-A0 Data Register 237 (DA0DT237) D-A0 Data Register 255 (DA0DT255)D-A0 Data Register 254 (DA0DT254) D-A0 Data Register 253 (DA0DT253)D-A0 Data Register 252 (DA0DT252) D-A0 Data Register 251 (DA0DT251)D-A0 Data Register 250 (DA0DT250) D-A0 Data Register 249 (DA0DT249)D-A0 Data Register 248 (DA0DT248) D-A0 Data Register 244 (DA0DT244) D-A0 Data Register 247 (DA0DT247) D-A0 Data Register 245 (DA0DT245) D-A0 Data Register 246 (DA0DT246) D-A0 Data Register 171 (DA0DT171) D-A0 Data Register 173 (DA0DT173) D-A0 Data Register 175 (DA0DT175) D-A0 Data Register 176 (DA0DT176) D-A0 Data Register 178 (DA0DT178) D-A0 Data Register 177 (DA0DT177) D-A0 Data Register 179 (DA0DT179) H'0080 1DBE Figure 16.2.3 SFR Area Register Map (3/3) D-A CONVERTERS

16-8 Rev.1.0

16.2.1 Prescaler Unit

The Prescaler PRSA consists of an 8-bit counter which generates a clock from the internal peripheral clock (20.0 MHz when the CPU clock = 40 MHz) for supply to the DACNT Counter. The prescaler value is initialized to H'00 when reset. Also when the value of the prescaler register is rewritten, the prescaler starts operating with the new value simultaneously when the prescaler underflows. Any value in the range of H'00 to H'FF can be set in the prescaler register. The prescaler's divide ratio is given by the equation below. f Prescaler set value + 1 Prescaler divide ratio = I Prescaler Register A (PRSA) <Address: H'0080 1800> D 0 123456 D 7 PRSA <When reset: H'00> D Bit Name Function R W 0-7 PRSA Sets the prescaler's divide-by value The Prescaler A generates a count clock for the D-A converter's parameter table address counter (DACNT) from the internal peripheral clock (20.0 MHz when the CPU clock = 40 MHz) by dividing it by an appropriate value. When the value of Prescaler Register A is rewritten while the DACNT is operating, the prescaler starts operating with the newly set value simultaneously when it underflows after reaching the minimum count. The PRSA starts generating a clock after the DACNT Control Register DACNTEN bit is set to 1. DACNT count period = f / (PRSA + 1) Note: When using the D-A converter along with PD sensors, the PRSA set value is subject to limitations depending on how the Position Detection Accuracy Select Register is set. D-A CONVERTERS

16-9 Rev.1.0

16.2.2 DACNT Reload Register

I DACNT Reload Register (DACNTRL) <Address: H'0080 1802> D 0 123456 D 7 DACNTRL <When reset: H'00> D Bit Name Function R W 0-7 DACNTRL 8-bit reload register value The DACNT Reload Register is used to reload data into the DACNT Counter. Data is loaded into the DACNT Counter synchronously with the clock cycle in which the counter underflowed. Simply because data is written to the DACNT Reload Register does not mean that the DACNT Counter is loaded with the data. D-A CONVERTERS

16-10 Rev.1.0

16.2.3 DACNT Control Register

I DACNT Control Register (DACNTCR) <Address: H'0080 1806> This register controls enabling/disabling of the DACNT Counter to or not to count. When the DACNTEN bit is set to 1, the DACNT Counter starts counting down from its set value synchronously with the count period that has been set with the PRSA. Setting the DACNTEN bit to 0 disables the DACNT Counter, so that it stops counting, with the count value retained. D 0 123456 D 7 DACNTEN <When reset: H'00> D Bit Name Function R W 0-6 No functions assigned 0 – 1: Enables count D-A CONVERTERS

16-11 Rev.1.0

16.2.4 DACNT Counter

I DACNT Counter (DACNT) <Address: H'0080 1808> The DACNT Counter is an 8-bit down-counter which after being enabled, starts counting down from its set value synchronously with the count clock generated by the PRSA. The value of the DACNT Counter comprises the D-A converter's parameter table address value. When the DACNT Counter underflows after reaching the minimum count (DACNT = H'00), it is reloaded with the content of the DACNT Reload Register and restarts counting down from the newly set value. The diagram below shows operation of the DACNT Counter when the DACNT Counter and the DACNT Reload Register respectively have the values H'A0 and H'B0 set as their initial values. D 0 123456 D 7 DACNT <When reset: H'00> D Bit Name Function R W 0-7 DACNT 8-bit counter value Count clock Enable bit H'FF H'00 DACNT Reload Register (DACNT) Counter H'B0 H'A0 DACNT Reload Register set value The counter counts down from the set value of the DACNT Reload Register The counter counts down from its set value Enabled Figure 16.2.4 Example of DACNT Counter Operation D-A CONVERTERS

16-12 Rev.1.0

16.2.5 D-A Control Register

I D-A Control Register (DACR) <Address: H'0080 1C7C> D 0 123456 D 7 DA0MOD DA1ON DA0ON <When reset: H'00> D Bit Name Function R W 0-4 No functions assigned 0 –

5 DA0MO 0: Single mode

(Select DA0 mode) 1: Continuous mode

6 DA1ON 0: Disables output

(Enable DA1 analog output) 1: Enables output

7 DA0ON

(Enable DA0 analog output) This register is used to select conversion mode of the D-A0 Converter and control whether or not to send the D-A conversion result to the output pin (DA0, DA1). (1) DA0MO (DA0 mode select) bit (D5) This bit selects conversion mode of the D-A0 Converter (single or continuous mode). When DA0MO = 0, single mode is selected; when DA0MO = 1, continuous mode is selected. Note: The D-A1 Converter does not have continuous mode. (This mode is available for only the D-A0 Converter.) (2) DA1ON (DA1 analog output enable) bit (D6) This bit controls whether or not to output the conversion result of the D-A1 Converter. Setting this bit to 1 enables analog output, so that the conversion result is output to the external pin DA1. Setting this bit to 0 disables analog output, so that the conversion result is not output to the external pin DA1. (3) DA0ON (DA0 analog output enable) bit (D7) This bit controls whether or not to output the conversion result of the D-A0 Converter. Setting this bit to 1 enables analog output, so that the conversion result is output to the external pin DA0. Setting this bit to 0 disables analog output, so that the conversion result is not output to the external pin DA0. D-A CONVERTERS

16-13 Rev.1.0

16.2.6 D-A Conversion Registers

I D-A0 Conversion Register (DA0CNV) <Address: H'0080 1C78> I D-A1 Conversion Register (DA1CNV) <Address: H'0080 1C7A> D 0 123456 D 7 DA0CNV, DA1CNV <When reset: H'00> D Bit Name Function R W 0-7 DA0CNV, DA1CNV 8-bit D-A conversion data (single mode) Writing a value (0-255) to the D-A Conversion Register (DA0CNV, DA1CNV) causes D-A conversion to start. The analog voltage V that is output by the D-A converter depends on the value n (n = 0-255) that has been set in the D-A Conversion Register (DA0CNV, DA1CNV). D-A CONVERTERS V = VREF ×

256 Note VREF : reference voltage

n

16-14 Rev.1.0

16.2.7 D-A0 Data Registers

I D-A0 Data Register n (DA0DTn) <Address: H'0080 1D00 to H'0080 1DFF> D 0 123456 D 7 (D8 9 10 11 12 13 14 D15) DA0DTn <When reset: indeterminate> D Bit Name Function R W 0-7 DA0DTn 8-bit D-A conversion data (continuous mode) The D-A0 Data Registers n (n = 0-255) are used for D-A conversion in continuous mode. The values set in the D-A0 Data Registers are sequentially D-A converted and output as analog quantities. D-A CONVERTERS

16-15 Rev.1.0

16.3 Functional Description of the D-A Converters

D-A conversion is performed in either single or continuous mode (the latter for only the D-A0 Converter).

16.3.1 Single Mode

In this mode, an analog value corresponding to the value set in the D-A Conversion Register (DAiCNV) is output from the external pin DAi. Setting a value in the D-A Conversion Register (DAiCNV) causes D-A conversion to start. If the D- A Control Register DAiON bit has been set to 1 (analog output enabled), the converted analog value is output from the external pin DAi. The converter continues generating analog output from the external pin DAi until the DAiON bit is set to 0 (analog output disabled). The output voltage V is determined by the equation given below.16.3.2 Continuous Mode The values set in the D-A0 Data Registers n (n = 0-255) are sequentially converted into analog quantities which are then output from the external pin DA0. Setting a value in the D-A Data Register n causes D-A conversion to start. If the D-A Control Register DA0ON bit (D7) has been set to 1 (analog output enabled), the converted analog value is output from the external pin DA0. The converter continues generating analog output from the external pin DA0 until the DA0ON bit is set to 0 (analog output disabled). D-A CONVERTERS Set value of the D-A conversion register 256 V = VREF × Note VREF : reference voltage

16-16 Rev.1.0 D-A CONVERTERS

17.1 External Bus Interface

17.2 Read/Write Operations

17.3 Bus Arbitration

17.4 Example for Connecting

17-2 Rev.1.0

17.1 External Bus Interface Related Signals

The 32172/32173 has the signals listed below that are associated with the external bus interface. These signals can be used in external extended mode or processor mode. (1) Address The external bus interface outputs 19-bit address (A12-A30) for addressing a 1-Mbyte space. The least significant A31 is not output. In an external write cycle, the external bus interface___ ___ outputs the BHW and BLW signals to indicate the valid byte position on the 16-bit data bus at which to write data. In a read cycle, data is read always in 16 bits and the data at only the valid byte position is transferred. Note: During external extended mode, the A12 and A13 pins are shared with the CS2 and CS3 pins, respectively. Therefore, functions of these pins must be selected with the Port P4 and P22 Peripheral Output Select Register. (In processor mode, these pins always function as A12 and A13.) (2) Chip selects (CS0, CS1, CS2, and CS3) These signals are output in external extended mode or processor mode. The CS0, CS1, CS2,___ and CS3 signals each indicate one of the external extended areas spaced every 2 Mbytes.___ The CS0 signal points to a 2-Mbyte area when in processor mode or a 1-Mbyte area when in external extended mode. (For details, see Chapter 3, "Address Space.") Note: During external extended mode, the A12 and A13 pins are shared with the CS2 and CS3 pins, respectively. Therefore, functions of these pins must be selected with the Port P4 and P22 Peripheral Output Select Register. (In processor mode, these pins always function as A12 and A13, so that the CS2 and CS3 signals are not output.) (3) Read strobe (RD) This signal is output during an external read cycle, indicating the timing at which to read data. This signal is driven high when writing to the bus or accessing the internal function. (4) Byte high write/byte high enable (BHW/BHE) The pin function is changed using the Bus Mode Control Register (BUSMODC). ___ When BUSMOD = 0, Byte High Write (BHW) is selected, indicating that valid data is transferred on the upper byte side (DB0-DB7) of the data bus during external write access. This output is held high during external read and when accessing an internal function. ___ When BUSMOD = 1, Byte High Enable (BHE) is selected, indicating that valid data is transferred on the upper byte side (DB0-DB7) of the data bus during external access. This output is held high when accessing an internal function. EXTERNAL BUS INTERFACE

17-3 Rev.1.0 (5) Byte low write/byte low enable (BLW/BLE) The pin function is changed using the Bus Mode Control Register (BUSMODC). ___ When BUSMOD = 0, Byte Low Write (BLW) is selected, indicating that valid data is transferred on the lower byte side (DB8-DB15) of the data bus during external write access. This output is held high during an external read cycle. ___ When BUSMOD = 1, Byte Low Enable (BLE) is selected, indicating that valid data is transferred on the upper byte side (DB8-DB15) of the data bus during external access. This output is held high when accessing an internal function. (6) Data bus (DB0-DB15) This is a 16-bit data bus used to access an external device. (7) System clock/write (BCLK/WR) The pin function is changed using the Bus Mode Control Register (BUSMODC). When BUSMOD = 0, System Clock (BCLK) is selected, generating the system clock needed for the synchronized design of external devices. When the CPU clock is 40 MHz, a 20 MHz clock is output from BCLK. When not using the BCLK/WR function, this pin can be used as P70 by setting the P7 Operation Mode Register P70MOD bit to 0. ___ BUSMOD = 1, Write (WR) is selected, indicating that valid data is transferred on the data bus during external write access. This output is held high during an external read cycle and when accessing an internal function. ____ (8) Wait (WAIT) When the 32172/32173 started an external bus cycle, it automatically inserts wait cycles while____ the WAIT signal is asserted. For details, see Chapter 18, "Wait Controller." When not using the WAIT function, this pin can be used as P71 by setting the P7 Operation Mode Register P71MOD bit to 0. For external access, one or m ore wait states are always inserted. Therefore, access to an external device incurs at least one wait state (total 2 BCLK cycles). (9) Hold control (HREQ, HACK) A hold state refers to a condition where bus access is halted and all of the bus interface related pins are placed in the high-impedance state. While in a hold state, any external bus master can use the system bus to transfer data.____ A hold state is entered into by pulling the HREQ pin input. After the hold request is accepted, the EXTERNAL BUS INTERFACE

17-4 Rev.1.0 Table 17.1.1 Pin State during Hold Period Pin name Pin state or operation A12-A30, DB0-DB15, CS0, CS1, CS2, CS3,RD, BHW, BLW, BHE, BLE, WRHigh-impedance state ____ HACK Outputs a low Other pins (e.g., ports and timer outputs) Normal operation EXTERNAL BUS INTERFACE ____ HACK pin outputs a low-level signal during hold and while going to a hold state. To return from____ the hold state to a normal operating state, release the HREQ input signal back high. When not using the HREQ and HACK functions, these pins can be used as P72 and P73 by setting the P7 Operation Mode Register P72MOD and P73MOD bits to 0. The table below shows the state of each pin during hold.

17-5 Rev.1.0 (10) Port operation mode register When the CPU is set to operate in external extended or processor mode, ports P0-P4 and P22 have their functions changed to signal pins for external access. When reset, these pins handle port signals. Port P7 has its function changed to signal pins for external access by setting the Port P7 Operation Mode Register and Port P7 Peripheral Output Select Register. I P0 Operation Mode Register (P0MOD) <Address: H'0080 0740> <When reset: H'00> D Bit Name Function R W (Port P00 operation mode) 1: P00 (Port P01 operation mode) 1: P01 (Port P02 operation mode) 1: P02 (Port P03 operation mode) 1: P03 (Port P04 operation mode) 1: P04 (Port P05 operation mode) 1: P05 (Port P06 operation mode) 1: P06 (Port P07 operation mode) 1: P07 Note: Settings made to the P0 Operation Mode Register are effective only when the CPU is operating in external extended mode. D 0 123456 D 7 P00MOD P01MOD P02MOD P03MOD P04MOD P05MOD P06MOD P07MOD EXTERNAL BUS INTERFACE

17-6 Rev.1.0 I P1 Operation Mode Register (P1MOD) <Address: H'0080 0741> <When reset: H'00> D Bit Name Function R W (Port P10 operation mode) 1: P10 (Port P11 operation mode) 1: P11 (Port P12 operation mode) 1: P12 (Port P13 operation mode) 1: P13 (Port P14 operation mode) 1: P14 (Port P15 operation mode) 1: P15 (Port P16 operation mode) 1: P16 (Port P17 operation mode) 1: P17 Note: Settings made to the P1 Operation Mode Register are effective only when the CPU is operating in external extended mode. D 8 9 1 01 11 21 31 4 D 1 5 P10MOD P11MOD P12MOD P13MOD P14MOD P15MOD P16MOD P17MOD EXTERNAL BUS INTERFACE

17-7 Rev.1.0 I P2 Operation Mode Register (P2MOD) <Address: H'0080 0742> <When reset: H'00> D Bit Name Function R W (Port P20 operation mode) 1: P20 (Port P21 operation mode) 1: P21 (Port P22 operation mode) 1: P22 (Port P23 operation mode) 1: P23 (Port P24 operation mode) 1: P24

5 P25MOD 0: A288

(Port P25 operation mode) 1: P25 (Port P26 operation mode) 1: P26 (Port P27 operation mode) 1: P27 Note: Settings made to the P2 Operation Mode Register are effective only when the CPU is operating in external extended mode. D 0 123456 D 7 P20MOD P21MOD P22MOD P23MOD P24MOD P25MOD P26MOD P27MOD EXTERNAL BUS INTERFACE

17-8 Rev.1.0 I P3 Operation Mode Register (P3MOD) <Address: H'0080 0743> <When reset: H'00> D Bit Name Function R W (Port P30 operation mode) 1: P30 (Port P31 operation mode) 1: P31 (Port P32 operation mode) 1: P32 (Port P33 operation mode) 1: P33 (Port P34 operation mode) 1: P34 (Port P35 operation mode) 1: P35 (Port P36 operation mode) 1: P36 (Port P37 operation mode) 1: P37 Note: Settings made to the P3 Operation Mode Register are effective only when the CPU is operating in external extended mode. D 8 9 1 01 11 21 31 4 D 1 5 P30MOD P31MOD P32MOD P33MOD P34MOD P35MOD P36MOD P37MOD EXTERNAL BUS INTERFACE

17-9 Rev.1.0 I P4 Operation Mode Register (P4MOD) <Address: H'0080 0744> Note: Settings made to the P4 Operation Mode Register are effective only when the CPU is operating in external extended mode. D 0 123456 D 7 P41MOD P42MOD P43MOD P44MOD P45MOD P47MOD <When reset: H'00> D Bit Name Function R W 0: BLW/BLE (Port P41 operation mode) 1: P41 0: BHW/BHE (Port P42 operation mode) 1: P42 ____ 0: RD (Port P43 operation mode) 1: P43 0: CS0 (Port P44 operation mode) 1: P44 0: CS1 (Port P45 operation mode) 1: P45 (Port P47 operation mode) 1: P47 EXTERNAL BUS INTERFACE

17-10 Rev.1.0 I P7 Operation Mode Register (P7MOD) <Address: H'0080 0747> <When reset: H'00> D Bit Name Function R W (Port P70 operation mode) ___ 1: BCLK/WR (Port P71 operation mode) ____ 1: WAIT (Port P72 operation mode) ____ 1: HREQ (Port P73 operation mode) ____ 1: HACK/TXD3 (Port P74 operation mode) 1: RTDTXD (Port P75 operation mode) 1: RTDRXD (Port P76 operation mode) 1: RTDACK (Port P77 operation mode) 1: RTDCLK D 8 9 1 01 11 21 31 4 D 1 5 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD EXTERNAL BUS INTERFACE

17-11 Rev.1.0 I P22 Operation Mode Register (P22MOD) <Address: H'0080 0756> Note 1: P221 is a CAN0 input-only pin. Note 2: P225 has its pin function changed depending on how the MOD0 and MOD1 pins are set. Also, because this pin has a debug event function, its use requires caution. Note 3: P222-P224, P226, and P227 are not included. D 0 123456 D 7 P220MOD P225MOD <When reset: H'00> D Bit Name Function R W (Port P220 operation mode) 1: CTX0 1-4 No functions assigned 0 – (Port P225 operation mode) 1: Use inhibited 6-7 No functions assigned 0 – EXTERNAL BUS INTERFACE

17-12 Rev.1.0 I P4 Peripheral Output Select Register (P4SMOD) <Address: H'0080 0764> <When reset: H'00> D Bit Name Function R W 0-5 No functions assigned 0 –

6 P46SMOD 0: A13

(Select port P46 peripheral output) 1: CS3 I P22 Peripheral Output Select Register (P22SMOD) <Address: H'0080 0776> D 0 123456 D 7 P46SMOD D 0 123456 D 7 P225SMOD <When reset: H'00> D Bit Name Function R W 0-4 No functions assigned 0 – (Select port P225 peripheral output) 1: CS2 6-7 No functions assigned 0 – Note: Settings made to the P22 Peripheral Output Select Register are effective only when the CPU is operating in external extended mode. EXTERNAL BUS INTERFACE

17-13 Rev.1.0 (11) Bus Mode Control Register (BUSMODC) The microcomputer contains a function to select between two external bus modes. I Bus Mode Control Register (BUSMODC) <Address: H'0080 077F> <When reset: H'00> D Bit Name Function R W 8-14 No functions assigned 0 –

15 BUSMOD 0: WR signal separate mode

(Bus mode control) 1: Byte enable separate mode D 8 9 1 01 11 21 31 4 D 1 5 BUSMOD This register is used to facilitate memory connections during processor and external extended modes. When the bus mode control (BUSMOD) bit = 0, the WR signal is output separately for each byte__ ___ ___ ____ ____ area. When in this mode, the RD, BHW, BLW, BCLK, and WAIT signals can be used. When connecting memory chips in boot mode, however, the Bus Mode Control Register has no effect, so that the external bus interface operates assuming that the bus mode control (BUSMOD) bit = 0. When the bus mode control (BUSMOD) bit = 1, the byte enable signal is output separately for__ ___ ___ __ ____ each byte area. When in this mode, the RD, BHE, BLE, WR, and WAIT signals can be used. When a WAIT control circuit is configured, timing must be controlled external to the chip because BCLK is not output. CS0, CS1 DB0 – DB15 WAIT RD BHW BLW A14 – A30 DB0 – DB15 WAIT RD WR BHE BLE A14 – A30 BCLK BUSMOD=0 BUSMOD=1 CS0, CS1 A12/CS2 A13/CS3 A12/CS2 A13/CS3 Figure 17.1.1 Pin Functions when Bus Modes are Changed EXTERNAL BUS INTERFACE

17-14 Rev.1.0 (1) When Bus Mode Control Register = 0 (WR signal separate mode) ___ External read/write operations are performed using the address and data buses and the CS0,___ ___ ___ __ ___ ___ ____ __ CS1, CS2, CS3, RD, BHW, BLW, WAIT, and BCLK signals. In an external read cycle, the RD___ ___ signal goes low while the BHW and BLW signals both go high, so that the data at only the necessary byte position is read.___ ___ In an external write cycle, the BHW or BLW signal for the byte position to write is asserted low, allowing data to be written at that position. ____ When an external bus cycle starts, wait states are inserted as long as WAIT remains low.____ Therefore, the WAIT signal must always be held high unless necessary. Note that an external bus cycle, even during the shortest access, has at least one wait state inserted (shortest bus cycle consists of 2 BCLK cycles). Note: CS2 and CS3 can be output in only external extended mode. Figure 17.2.1 Read/Write Operations during Bus-free State/Internal Bus Access EXTERNAL BUS INTERFACE "H" BCLK A12 – A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 – DB15 WAIT RD "H" Hi-z "H" Note: Hi-Z denotes a high-impedance state.

17-15 Rev.1.0 Read (2 cycles) BCLK A12 – A30 CS0, CS1, CS2, CS3 BHW, BLW RD "H" Write (2 cycles) BCLK A12 – A30 BHW, BLW DB0 – DB15 WAIT RD Note: The circles above show the positions at which signals are sampled. "H" "H" DB0 – DB15 WAIT "H" 1 wait state 1 wait state CS0, CS1, CS2, CS3 Read Write Figure 17.2.2 Read/Write Timing (during Shortest External Access) EXTERNAL BUS INTERFACE

17-16 Rev.1.0 Read (4 cycles) BCLK A12 – A30 BHW, BLW DB0 – DB15 WAIT RD "H" (Don't Care) BCLK A12 – A30 BHW, BLW RD Note: The circles above show the positions at which signals are sampled. "H" "L" "H" DB0 – DB15 WAIT (Don't Care) "L" "H" 1 external wait state2 internal wait states 1 external wait state 2 internal wait states Write (4 cycles) CS0, CS1, CS2, CS3 CS0, CS1, CS2, CS3 Read Write Figure 17.2.3 Read/Write Timing (Accessed with 2 Internal + 1 External Wait States) EXTERNAL BUS INTERFACE

17-17 Rev.1.0 (2) When Bus Mode Control Register = 1 (WR signal separate mode) ___ CS1, CS2, CS3, RD, BHE, BLE, WAIT, and WR signals. In an external read cycle, the RD signal___ ___ goes low and the BHE or BLE signal for the byte position to read goes low, so that the data at only the necessary byte position is read.__ ___ ___ In an external write cycle, the WR signal goes low and the BHE or BLE signal for the byte position to write is asserted low, allowing data to be written at the necessary byte position. ____ When an external bus cycle starts, wait states are inserted as long as WAIT remains low.____ Therefore, the WAIT signal must always be held high unless necessary. Note that an external bus cycle, even during the shortest access, has at least one wait state inserted (shortest bus cycle consists of 2 BCLK cycles). When not using the WAIT function, set the P7 Operation Mode Register P71MOD bit to 0. The pin can be used as P71. Note: CS2 and CS3 can be output in only external extended mode. Figure 17.2.4 Read/Write Operations during Bus-free State/Internal Bus Access EXTERNAL BUS INTERFACE "H" BCLK A12 – A30 CS0, CS1, CS2, CS3 DB0 – DB15 WAIT RD "H" Hi-z "H" Note 1: Hi-Z denotes a high-impedance state. Note 2: BCLK is not output. WR BHE, BLE "H"

17-18 Rev.1.0 Read (2 cycles) BCLK A12 – A30 WR RD "H" Write (2 cycles) BCLK A12 – A30 DB0 – DB15 WAIT RD Note 1: The circles above show the positions at which signals are sampled. Note 2: BCLK is not output. "H" "H" DB0 – DB15 WAIT "H" 1 wait state 1 wait state BHE, BLE WR BHE, BLE CS0, CS1, CS2, CS3 CS0, CS1, CS2, CS3 Read Write Figure 17.2.5 Read/Write Timing (during Shortest External Access) EXTERNAL BUS INTERFACE

17-19 Rev.1.0 Read (4 cycles) BCLK A12 – A30 DB0 – DB15 WAIT RD "H" (Don't Care) BCLK A12 – A30 RD Note 1: The circles above show the positions at which signals are sampled. Note 2: BCLK is not output. "H" "L" "H" DB0 – DB15 WAIT (Don't Care) "L" "H" 1 external wait state2 internal wait states 1 external wait state 2 internal wait states Write (4 cycles) WR BHE, BLE WR BHE, BLE CS0, CS1, CS2, CS3 CS0, CS1, CS2, CS3 Read Write Figure 17.2.6 Read/Write Timing (Accessed with 2 Internal + 1 External Wait States) EXTERNAL BUS INTERFACE

17-20 Rev.1.0 (1) When Bus Mode Control Register = 0 (WR signal separate mode) ____ When the input signal at the HREQ pin is asserted low and the hold request is accepted, the CPU____ enters a hold state in which it outputs a low from the HACK pin. During hold, the bus related signals go to a high-impedance state, allowing data transfers to be performed on the system bus.____ To return from the hold state to a normal operating state, release the HREQ input signal back high. Figure 17.3.1 Bus Arbitration Timing EXTERNAL BUS INTERFACE DB0 – DB15 BCLK Bus cycle Idle Goes to hold Hold state Return Next bus cycle Note 1: The circles above show the positions at which signals are sampled. Note 2: Hi-Z denotes a high-impedance state. Note 3: The idle cycle is inserted only when a hold state is entered subsequently after an external read access. HREQ HACK A12 – A30 RD BHW , BLW WAIT Hi-Z Hi-Z Hi-Z Hi-Z CS0, CS1, CS2, CS3

17-21 Rev.1.0 DB0 – DB15 BCLK Hi-Z Bus cycle Idle Goes to hold Hold state Return Next bus cycle Note 1: The circles above show the positions at which signals are sampled. Note 2: Hi-Z denotes a high-impedance state. Note 3: The idle cycle is inserted only when a hold state is entered subsequently after an external read access. HREQ HACK A12 – A30 RD WR BHW , BLW WAIT Hi-Z Hi-Z Hi-Z Hi-Z CS0, CS1, CS2, CS3 (2) When Bus Mode Control Register = 1 (Byte enable separate mode) ____ When the input signal at the HREQ pin is asserted low and the hold request is accepted, the CPU____ enters a hold state in which it outputs a low from the HACK pin. During hold, the bus related signals go to a high-impedance state, allowing data transfers to be performed on the system bus.____ To return from the hold state to a normal operating state, release the HREQ input signal back high. Figure 17.3.2 Bus Arbitration Timing EXTERNAL BUS INTERFACE

17-22 Rev.1.0

17.4 Example for Connecting External Extension Memory

(1) When Bus Mode Control Register = 0 (with two memory blocks connected) Figure 17.4.1 shows a typical connection diagram for the microcomputer when using external extension memory (external extended mode). Figure 17.4.1 Typical Connection of External Extension Memory Using Two Memory Blocks (when BUSMOD = 0) Note: The M32R/E address and data are comprised of bit 0 = MSB and bit 15 = LSB. When connecting external extension memory to the chip, the MSB and the LSB sides must be reversed. EXTERNAL BUS INTERFACE (256KB) Bus wait states can be set to 1 through 4. Normally used for port function. Use WAIT only when four or more wait states are required. H'0000 0000 H'001F FFFF H'0040 0000 H'0020 0000 H'0004 0000 Unused H'0010 0000 External memory area 2M-CS1 area SRAM Flash memory A18 D15 RD CS max1MB A17 D15 RD(D0-D15) CS WR(D0-D7) WR(D8-D15) max512KB*2 (total1MB) M32172F2 A12 A30 D15 RD CS0 CS1 BLW BHW WAIT H'000F FFFF (1MB) Ghost area H'0030 0000 External memory area (1MB) 1M-CS0 area

17-23 Rev.1.0 (2) When Bus Mode Control Register = 0 (with three memory blocks connected) Figure 17.4.2 shows a typical connection diagram for the microcomputer when using external extension memory (external extended mode). Figure 17.4.2 Typical Connection of External Extension Memory Using Three Memory Blocks (when BUSMOD = 0) Note: The M32R/E address and data are comprised of bit 0 = MSB and bit 15 = LSB. When connecting external extension memory to the chip, the MSB and the LSB sides must be reversed. EXTERNAL BUS INTERFACE (256KB) H'0000 0000 H'0020 0000 H'0004 0000 Unused H'0010 0000 2M-CS1 area 32172,32173 A[13:30] D[0:15] RD CS0 CS1 BLW BHW Ghost area H'0028 0000 1M-CS0 area 2M-CS2 area 2M-CS3 area H'0040 0000 Ghost area H'0048 0000 H'0080 0000 H'0060 0000 Unused CS2 CS2 external memory area (512MB) CS1 external memory area (512MB) CS0 external memory area (512MB) Ghost area SRAM Flash memory A17:A0 D[15:0] RD CS max512KB A[16:0] D[15:0] RD(D0-D15) CS WR(D0-D7) WR(D8-D15) max256KB*2 (total512KB) ASIC etc. A[17:0] D[15:0] RD(D0-D15) CS WR(D0-D7) WR(D8-D15) max512KB H'0018 0000 Note 1) Bus wait states can be set to 1 through 4. Note 2) Normally used for port function. Use WAIT only when four or more wait states are required.

17-24 Rev.1.0 (3) When Bus Mode Control Register = 0 (with four memory blocks connected) Figure 17.4.3 shows a typical connection diagram for the microcomputer when using external extension memory (external extended mode). Figure 17.4.3 Typical Connection of External Extension Memory Using four Memory Blocks (when BUSMOD = 0) Note: The M32R/E address and data are comprised of bit 0 = MSB and bit 15 = LSB. When connecting external extension memory to the chip, the MSB and the LSB sides must be reversed. EXTERNAL BUS INTERFACE Note 1) Bus wait states can be set to 1 through 4. Note 2) Normally used for port function. Use WAIT only when four or more wait states are required. Memory mapping Internal flash memory (256KB) H'0000 0000 H'0020 0000 H'0004 0000 Unused H'0010 0000 2M-CS1 area 32172,32173 A[14:30] D[0:15] RD CS0 CS2 BLW BHW Ghost area H'0024 0000 1M-CS0 area 2M-CS2 area 2M-CS3 area H'0040 0000 Ghost area H'0044 0000 H'0080 0000 H'0060 0000 Ghost area H'0064 0000 CS3 external memory area (256KB) CS3 CS1 CS2 external memory area (256MB) CS1 external memory area (256MB) CS0 external memory area (256MB) Ghost area SRAM Flash memory A16:A0 D[15:0] RD CS max256KB A[15:0] D[15:0] RD(D0-D15) CS WR(D0-D7) WR(D8-D15) max128KB*2 (total256KB) ASIC etc. Flash memory A[16:0] D[15:0] RD CS max256KB A[16:0] D[15:0] RD(D0-D15) CS WR(D0-D7) WR(D8-D15) max256KB H'0014 0000

17-25 Rev.1.0 (4) When Bus Mode Control Register = 1 (with two memory blocks connected) Figure 17.4.4 shows a typical connection diagram for the microcomputer when using external extension memory (external extended mode). Figure 17.4.4 Typical Connection of External Extension Memory Using Two Memory Blocks (when BUSMOD = 1) Note: The M32R/E address and data are comprised of bit 0 = MSB and bit 15 = LSB. When connecting external extension memory to the chip, the MSB and the LSB sides must be reversed. EXTERNAL BUS INTERFACE Bus wait states can be set to 1 through 4. WAIT Normally used for port function. Use WAIT only when four or more wait states are required. Flash memory A18 D15 RD CS max1MB A18 D15 RD(D0-D15) CS BHE(D0-D7) BLE(D8-D15) max1MB WR WR(D0-D15) Memory mapping Internal flash memory (256KB) H'0000 0000 H'001F FFFF H'0040 0000 H'0020 0000 H'0004 0000 Unused H'0010 0000 2M-CS1 area H'000F FFFF External memory area (1MB) Ghost area H'0030 0000 (1MB) External memory area (1MB) 1M-CS0 area

17-26 Rev.1.0 (5) When Bus Mode Control Register = 1 using 8/16-bit data bus memory blocks in combination Figure 17.4.3 shows a typical connection diagram for the microcomputer when using an 8-bit data bus memory which is located in the CS0 area and a 16-bit data bus memory which is located in the CS1 area. (External extension memory can only be used in external extended and processor modes). Figure 17.4.5 Typical Connection of External Extension Memory for the M32172 (when BUSMOD = 1 using 8/16-bit Memory Blocks in Combination) Note: The M32R/E address and data are comprised of bit 0 = MSB and bit 15 = LSB. When connecting external extension memory to the chip, the MSB and the LSB sides must be reversed. EXTERNAL BUS INTERFACE (256KB) External memory area (1MB) Memory can be connected with only 2 ns data delay when CL = 50 pF Normally used for port function. Use WAIT only when four or more wait states are required. H'0000 0000 H'0040 0000 H'0020 0000 H'0004 0000 Unused H'0010 0000 1M-CS0 area 2M-CS1 area SRAM 8-bit memory A18 RD CS max1MB A18 D15 BHE CS WR(D0-D15) RD(D0-D15) max1MB M32172F2 A12 A30 D15 RD CS0 CS1 BHE WR WAIT QS32X2245 A B OE BLEBLE A0 8-bit bus area Note: The QS32X2245 is a product from IDT Company. A B Bus wait states can be set to 1 through 4. H'000F FFFF External memory area (1MB) 16-bit bus area H'0030 0000 Ghost area WR

18.1 Outline of the Wait Controller

18.2 Wait Controller Related

18.3 Typical Operation of the Wait

18-2 Rev.1.0 The Wait Controller controls the number of wait cycle inserted in the bus cycle when accessing an external extended area. The Wait Controller is outlined below. WAIT CONTROLLER Table 18.1.1 Outline of the Wait Controller Item Specification Target space Following spaces are controlled depending on operation mode: Single-chip mode : No target space (Settings made to the Wait Controller have no effect) External extended mode : CS0 area (1M Mbytes), CS1 area (2 Mbytes), CS2 area (2 Mbytes), or CS3 area (2 Mbytes) Processor mode : CS0 area (2 Mbytes), CS1 area (2 Mbytes) Number of wait cycles ____ One to four wait cycles set in software + any wait cycles inserted by WAIT pin that can be inserted input (Bus cycle during external access has at least one wait cycle inserted which is the shortest access possible.) In external extended, four chip select signals (CS0, CS1, CS2, and CS3) are output for external extended areas. The four external extended areas corresponding to these four chip select signals respectively are referred to as the CS0, CS1, CS2, and CS3 areas. In processor mode, two chip select signals (CS0 and CS1) are output for external extended areas. The two external extended areas corresponding to these two chip select signals respectively are referred to as the CS0 and CS1 areas.

18-3 Rev.1.0 H'0000 0000 H'0003 FFFF H'0004 0000 Non-CS0 area <Processor mode><External extended mode> Internal ROM area (256 Kbytes) H'001F FFFF H'0020 0000 CS0 area (1 Mbytes) H'000F FFFF H'0010 0000 H'003F FFFF H'0040 0000 External extended area CS2 area (2 Mbytes) CS3 area (2 Mbytes) Reserved area (768 Kbytes) CS1 area (2 Mbytes) CS2 Reserved area (2 Mbytes) CS3 Reserved area (2 Mbytes) CS0 area (2 Mbytes) External extended area H'005F FFFF H'0060 0000 H'007F FFFF CS1 area (2 Mbytes) Figure 18.1.1 Address Map of the CS0 through CS3 Areas When accessing an external extended area, the Wait Controller controls the number of wait cycles to be inserted in the bus cycle by checking the number of wait cycles set in software and those set____ by an input signal from the WAIT pin. The number of wait cycles that can be controlled by software is 1 to 4. (External access incurs at least one wait cycle which is the shortest bus cycle possible.) ____ If the WAIT pin input remains low in the last cycle of the internal wait state set by software, the wait____ cycle is extended. Then when the WAIT pin input is released back high, the wait cycle is terminated and the next new bus cycle occurs. WAIT CONTROLLER

18-4 Rev.1.0 Table 18.1.2 Number of Wait Cycles That Can Be Set by the Wait Controller during External Extended Mode Valid chip External Address Number of wait cycles inserted select signal extended area CS0 , CS1 CS0 area H'0010 0000–H'001F FFFF One to four wait cycles inserted by setting in____ software + any wait cycles inserted by WAIT pin input (Software settings have priority, however.) CS1 area H'0020 0000–H'002F FFFF (Note 1) CS0 , CS1, CS2 CS0 area H'0010 0000–H'0017 FFFF (Note 2) CS1 area H'0020 0000–H'0027 FFFF (Note 3) CS2 area H'0040 0000–H'0047 FFFF (Note 4) CS0 , CS1, CS3 CS0 area H'0010 0000–H'0013 FFFF, H'0018 0000–H'001B FFFF (Note 5) CS1 area H'0020 0000–H'0023 FFFF, H'0028 0000–H'002B FFFF (Note 6) CS3 area H'0060 0000–H'0063 FFFF H'0068 0000–H'006B FFFF (Note 7) CS0 , CS1, CS2, CS0 area H'0010 0000–H'0013 FFFF CS3 (Note 8) CS1 area H'0020 0000–H'0023 FFFF (Note 9) CS2 area H'0040 0000–H'0043 FFFF (Note 10) CS3 area H'0060 0000–H'0063 FFFF (Note 11) Note 1: A ghost of the CS1 area appears in the area ranging in address from H'0030 0000 to H'003F FFFF. Note 2: A ghost of the CS0 area appears in the area ranging in address from H'0018 0000 to H'001F FFFF. Note 3: A ghost of the CS1 area appears in the area ranging in address from H'0028 0000 to H'003F FFFF. Note 4: A ghost of the CS2 area appears in the area ranging in address from H'0048 0000 to H'005F FFFF. Note 5: A ghost of the CS0 area appears in areas ranging in address from H'0014 0000 to H'0017 FFFF and from H'001C 0000 to H'001F FFFF. Note 6: A ghost of the CS1 area appears in areas ranging in address from H'0024 0000 to H'0027 FFFF and from H'002C 0000 to H'003F FFFF. Note 7: A ghost of the CS3 area appears in areas ranging in address from H'0064 0000 to H'0067 FFFF and from H'006C 0000 to H'007F FFFF. Note 8: A ghost of the CS0 area appears in the area ranging in address from H'0014 0000 to H'001F FFFF. Note 9: A ghost of the CS1 area appears in the area ranging in address from H'0024 0000 to H'003F FFFF. Note 10: A ghost of the CS2 area appears in the area ranging in address from H'0044 0000 to H'005F FFFF. Note 11: A ghost of the CS3 area appears in the area ranging in address from H'0064 0000 to H'007F FFFF. WAIT CONTROLLER

18-5 Rev.1.0 Table 18.1.3 Number of Wait Cycles That Can Be Set by the Wait Controller during Processor Mode External extended area Address Number of wait cycles inserted CS0 area H'0000 0000–H'000F FFFF One to four wait cycles inserted by setting in (Note 1) ____ software + any wait cycles inserted by WAIT pin input (Software settings have priority, however.) CS1 area H'0020 0000–H'002F FFFF (Note 2) WAIT CONTROLLER Note 1: A (1 Mbyte) ghost of the CS0 area appears in the area ranging in address from H'0010 0000 to H'001F FFFF. Note 2: A (1 Mbyte) ghost of the CS1 area appears in the area ranging in address from H'0030 0000 to H'003F FFFF. Note 3: There is no CS2 and CS3 area in the processor mode.

18-6 Rev.1.0

18.2 Wait Controller Related Registers

A wait controller related register map is shown below. Figure 18.2.1 Wait Controller Related Register Map WAIT CONTROLLER H'0080 0180 Address D0 D7 +0 address +1 addressD8 D15 Wait Cycles Control Register (WTCCR) Blank areas are reserved for future use.

18-7 Rev.1.0

18.2.1 Wait States Control Register

I Wait States Control Register (WTCCR) <Address: H'0080 0180> D 0 123456 D 7 CS2WTC CS0WTC CS3WTC CS1WTC <When reset: H'00> D Bit Name Function R W 0,1 CS2WTC 00: 4 wait cycles (when reset) (Control the number of 01: 3 wait cycles CS2 wait states) 10: 2 wait cycles 11: 1 wait cycle 2,3 CS0WTC 00: 4 wait cycles (when reset) (Control the number of 01: 3 wait cycles CS0 wait states) 10: 2 wait cycles 11: 1 wait cycle 4,5 CS3WTC 00: 4 wait cycles (when reset) (Control the number of 01: 3 wait cycles CS3 wait states) 10: 2 wait cycles 11: 1 wait cycle 6,7 CS1WTC 00: 4 wait cycles (when reset) (Control the number of 01: 3 wait cycles CS1 wait states) 10: 2 wait cycles 11: 1 wait cycle WAIT CONTROLLER

18-8 Rev.1.0

18.3 Typical Operation of the Wait Controller

The following shows a typical operation of the wait controller. The wait controller can control bus access in the range of 2 to 5 cycles. If more access cycles than that are needed, use the WAIT function in combination with the wait controller. (1) When Bus Mode Control Register = 0 ___ External read/write operations are performed using the address bus, data bus, and signals CS0, CS1, CS2, CS3, RD, BHW, BLW, WAIT, and BCLK. Figure 18.3.1 Internal Bus Access during Bus Free State Note : THi-Z denotes a high-impedance state. WAIT CONTROLLER "H" BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD "H" Hi-z "H"

18-9 Rev.1.0 Figure 18.3.2 Read/Write Timing (for Access with 1 Internal Wait Cycle) Note : Circles above indicate points at which signals are sampled. WAIT CONTROLLER Read (2 cycles) "H" "H" "H" "H" One wait cycle BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD Read Write (2 cycles) One wait cycle BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD Write

18-10 Rev.1.0 Figure 18.3.3 Read/Write Timing (for Access with 2 Internal Wait Cycles) Note : Circles above indicate points at which signals are sampled. WAIT CONTROLLER "H" (Don't Care) "H" "H" (Don't Care) "H" 2 internal wait cycles Read (3 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD Read Write (3 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD Write 2 internal wait cycles

18-11 Rev.1.0 WAIT CONTROLLER Figure 18.3.4 Read/Write Timing (for Access with 3 Internal Wait Cycles) Note : Circles above indicate points at which signals are sampled. "H" (Don't Care) "H" "H" (Don't Care) "H" 3 internal wait cycles Read (4 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD Read Write (4 cycles) BCLK A12 - A30 CS0, CS1, CS0, CS1 BHW, BLW DB0 - DB15 WAIT RD Write 3 internal wait cycles

18-12 Rev.1.0 WAIT CONTROLLER Figure 18.3.5 Read/Write Timing (for Access with 4 Internal Wait Cycles) Note : Circles above indicate points at which signals are sampled. "H" (Don't Care) "H" "H" (Don't Care) "H" 4 internal wait cycles Read (5 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD Read Write (5 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD Write 4 internal wait cycles

18-13 Rev.1.0 WAIT CONTROLLER Figure 18.3.6 Read/Write Timing (for Access with 4 Internal and 1 External Wait Cycles) Note : Circles above indicate points at which signals are sampled. "H" (Don't Care) "H" "H" (Don't Care) "H" 4 internal wait cycles Read (6 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD Read Write (6 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD Write 4 internal wait cycles "L" "L" 1 external wait cycle 1 external wait cycle

18-14 Rev.1.0 WAIT CONTROLLER Figure 18.3.7 Read/Write Timing (for Access with 2 Internal and n External Wait Cycles) Note : Circles above indicate points at which signals are sampled. "H" (Don't Care) "H" "H" (Don't Care) "H" 2 internal wait cycles Read (3+n cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD Read Write (3+n cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD Write 2 internal wait cycles "L" "L" n external wait cycles n external wait cycles "L" "L" "L" "L" ~~~~ ~~~~ ~~~~

18-15 Rev.1.0 WAIT CONTROLLER Figure 18.3.8 Internal Bus Access during Bus Free State Note 1 : Hi-Z denotes a high-impedance state. Note 2 : BCLK is not output. (2) When Bus Mode Control Register = 1 ___ External read/write operations are performed using the address bus, data bus, and signals CS0, CS1, CS2, CS3, RD, BHE, BLE, WAIT, and WR. "H" "H" Hi-z "H" "H" Bus-free state internal bus access BCLK A12 - A30 CS0, CS1, CS2, CS3 BHW, BLW DB0 - DB15 WAIT RD WR

18-16 Rev.1.0 Figure 18.3.9 Read/Write Timing (for Access with 1 Internal Wait Cycle) Note 1 : Circles above indicate points at which signals are sampled. Note 2 : BCLK is not output. WAIT CONTROLLER "H" "H" "H" "H" Read (2 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHE, BLE DB0 - DB15 WAIT RD Read Write (2 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHE, BLE DB0 - DB15 WAIT RD Write WR WR 1 internal wait cycle 1 internal wait cycle

18-17 Rev.1.0 Figure 18.3.10 Read/Write Timing (for Access with 2 Internal Wait Cycles) Note 1 : Circles above indicate points at which signals are sampled. Note 2 : BCLK is not output. WAIT CONTROLLER "H" "H" "H" "H" (Don't Care) 2 internal wait cycles Read (3 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHE, BLE DB0 - DB15 WAIT RD Read Write (3 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHE, BLE DB0 - DB15 WAIT RD Write 2 internal wait cycles WR WR (Don't Care)

18-18 Rev.1.0 Figure 18.3.11 Read/Write Timing (for Access with 3 Internal Wait Cycles) Note 1 : Circles above indicate points at which signals are sampled. Note 2 : BCLK is not output. WAIT CONTROLLER "H" "H" "H" "H" (Don't Care) 3 internal wait cycles Read (4 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHE, BLE DB0 - DB15 WAIT RD Read Write (4 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHE, BLE DB0 - DB15 WAIT RD Write 3 internal wait cycles WR WR (Don't Care)

18-19 Rev.1.0 Figure 18.3.12 Read/Write Timing (for Access with 4 Internal Wait Cycles) Note 1 : Circles above indicate points at which signals are sampled. Note 2 : BCLK is not output. WAIT CONTROLLER "H" "H" "H" "H" (Don't Care) 4 internal wait cycles Read (5 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHE, BLE DB0 - DB15 WAIT RD Read Write (5 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHE, BLE DB0 - DB15 WAIT RD Write 4 internal wait cycles WR WR (Don't Care)

18-20 Rev.1.0 Figure 18.3.13 Read/Write Timing (for Access with 4 Internal and 1 External Wait Cycles) Note 1 : Circles above indicate points at which signals are sampled. Note 2 : BCLK is not output. WAIT CONTROLLER "H" "H" "H" "H" (Don't Care) 4 internal wait cycles Read (6 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHE, BLE DB0 - DB15 WAIT RD Read Write (6 cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHE, BLE DB0 - DB15 WAIT RD Write 4 internal wait cycles WR WR (Don't Care) "L" "L" 1 external wait cycle 1 external wait cycle

18-21 Rev.1.0 Figure 18.3.14 Read/Write Timing (for Access with 2 Internal and n External Wait Cycles) Note 1 : Circles above indicate points at which signals are sampled. Note 2 : BCLK is not output. WAIT CONTROLLER "H" "H" "H" "H" (Don't Care) 2 internal wait cycles Read (3+n cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHE, BLE DB0 - DB15 WAIT RD Read Write (3+n cycles) BCLK A12 - A30 CS0, CS1, CS2, CS3 BHE, BLE DB0 - DB15 WAIT RD Write 2 internal wait cycles WR WR (Don't Care) "L" "L" n external wait cycles n external wait cycles "L" "L" "L" "L" ~~~~

18-22 Rev.1.0 WAIT CONTROLLER

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19.1 Outline

19.2 Example of RAM Backup

19.3 Example of RAM Backup for

19.4 Exiting RAM Backup Mode

(Wakeup) CHAPTER 19CHAPTER 19 RAM BACKUP MODE

19-2 Rev.1.0 In RAM backup mode, the contents of the internal RAM are retained while the power is turned off. RAM backup mode is used for the following two purposes:

• Back up the internal RAM data when the power is down
• Turn off the power to the CPU whenever necessary to save on the system's power consumption The 32R/E CPU is placed in RAM backup mode by applying a voltage of 2.0-3.3 V to the VDD pin (provided for RAM backup) and 0 V to all other pins. During RAM backup mode, the contents of the internal RAM are retained, while the CPU and internal peripheral I/O remain idle. Also, because all pins except VDD are held low during RAM backup mode, power consumption in the system can effectively reduced.

19.2 Example of RAM Backup when Power is Down

A typical circuit for RAM backup at power outage is shown in Figure 19.2.1. The following explains how the RAM can be backed up by using this circuit as an example. RAM BACKUP MODE Figure 19.2.1 Typical Circuit for RAM Backup at Power Outage Note 1 : Power outage is detected by the DC IN (regulator input) voltage. Note 2 : These pins are used to detect a RAM backup signal. Note 3 : This pin outputs a high when the power is on and outputs a low when the power is down. VREFn SBI ADnINi M32R/E C Backup battery VCC VDD VBB VREF Reference voltage for power outage detection Power outage detection signal Backup power supply for power outage Power supply monitor IC VDD DC IN Input OutputRegulator (5V system) VCCI AVCCnOSC-VCC OUT VCCE (Note 1) OutputRegulator (3.3V system) (Note 3) (Note 2)

19-3 Rev.1.0 RAM BACKUP MODE

19.2.1 Normal Operating State

Figure 19.2.2 shows the normal operating state of the M32R/E. During normal operation, input on the SBI pin or ADnINi (i = 0-15) pin used for RAM backup signal detection remains high. Figure 19.2.2 Normal Operating State Note 1 : Power outage is detected by the DC IN (regulator input) voltage. Note 2 : These pins are used to detect a RAM backup signal. Note 3 : This pin outputs a high when the power is on and outputs a low when the power is down. Note 4 : Backup power supply = 2.0 to 3.3 V VREFn SBI ADnINi M32R/E C Backup battery VCC VDD VBB VREF Reference voltage for power outage detection Power outage detection signal Backup power supply for power outage Power supply monitor IC VDD DC IN Input OutputRegulator (5V system) VCCI AVCCnOSC-VCC OUT VCCE (Note 1) OutputRegulator (3.3V system) (Note 3) (Note 2) 5V3.3V 5V3.3V 5V3.3V(Note 4) "H"

19-4 Rev.1.0 Figure 19.2.3 RAM Backup State at Power Outage Note 1:Power outage is detected by the DC IN (regulator input) voltage. Note 2:These pins are used to detect a RAM backup signal. Note 3:This pin outputs a high when the power is on and outputs a low when the power is down. Note 4: ___ Determined by the input voltage level on SBI pin or ADnINi pin. Note 5:Adjust this capacitance to provid the necessary processing time in ➁ . RAM BACKUP MODE

19.2.2 RAM Backup State

Shown in Figure 19.2.3 is the power outage RAM backup state of the M32R/E. When the power supply goes down, the power supply monitor IC starts feeding current from the backup battery to the M32R/E. Also, the power supply monitor IC's power outage detection pin outputs a low, causing ___ the SBI pin or ADnINi pin input to go low, which generates a RAM backup signal (➀ in Figure 17.2.3). Whether the power is down or not must be determined with respect to the DC IN (regulator input) voltage in order to allow for a software processing time at power outage. To enable RAM backup mode, make the following settings. (1) Create check data to verify after returning from RAM backup to normal mode whether the RAM data has been retained normally (➁ in Figure 19.2.3). When the power supply to VCC goes down after settings in (1), the voltage applied to the VDD pin becomes 2.0-3.3 V and voltages applied to all other pins drop to 0 V, and the M32R/E thereby enters RAM backup mode (➂ in Figure 19.2.3). VREFn SBI ADnINi M32R/E C Backup battery VCC VDD VBB VREF Reference voltage for power outage detection Power outage detection signal Backup power supply for power outage Power supply monitor IC VDD DC IN Input OutputRegulator (5V system) VCCI AVCCnOSC-VCC OUT VCCE (Note 1) OutputRegulator (3.3V system) (Note 3) (Note 2) 3.3V 0V (Note 4) "L" (Note 5) 2.0V - 3.3V Example of RAM backup processing Power goes down (Note 4) Create check data for backup RAM ➂ RAM backup mode 0V0V0V0V

19-5 Rev.1.0 RAM BACKUP MODE

19.3 Example of RAM Backup for Saving Power Consumption

Figure 19.3.1 shows a typical circuit for RAM backup to save on power consumption. The following explains how the RAM is backed up for the purpose of low-power operation by using this circuit as an example. Figure 19.3.1 Typical Circuit for RAM Backup to Save on Power Consumption Note 1 : This signal outputs a low for RAM backup. Note 2 : This pin outputs a high when the power is on, and is set for input mode when in RAM backup mode. Note 3 : These pins are used to detect a RAM backup signal. RAM backup signal (Note 1) External circuit Port X IB RAM backup power supplyDC IN Input OutputRegulator (3.3V system) OutputRegulator (5V system) OutputRegulator (3.3V system) VREFn SBI ADnINi M32R/E VDD VCCI AVCCnOSC-VCC VCCE (Note 3) (Note 2)

19-6 Rev.1.0 RAM BACKUP MODE Figure 19.3.2 Normal Operating State

19.3.1 Normal Operating State

Figure 19.3.2 shows the normal operating state of the M32R/E. During normal operation, the RAM ___ backup signal output by the external signal is high. Also, input on the SBI pin or ADnINi (i = 0-15) pin used for RAM backup signal detection remains high. Port X, which is the transistor's base connecting pin, should output a high. This causes the transistor's base voltage, IB, to go high, so that current is fed from the power supply to the VCC pin via the transistor. Note 1 : This signal outputs a low for RAM backup. Note 2 : This pin outputs a high when the power is on, and is set for input mode when in RAM backup mode. Note 3 : These pins are used to detect a RAM backup signal. RAM backup signal (Note 1) External circuit Port X IB RAM backup power supplyDC IN Input OutputRegulator (3.3V system) OutputRegulator (5V system) OutputRegulator (3.3V system) VREFn SBI ADnINi M32R/E VDD VCCI AVCCnOSC-VCC VCCE (Note 3) (Note 2) 5V 3.3V5V3.3V 5V3.3V "H" "H" "H"

19-7 Rev.1.0 RAM BACKUP MODE Figure 19.3.3 RAM Backup State for Low-Power Operation

19.3.2 RAM Backup State

___ sequence. When the external circuit outputs a low, input on the SBI pin or ADnINi pin goes low. A low on these input pins generates a RAM backup signal (A and ➀ in Figure 19.3.3). To enable RAM backup mode, make the following settings. (1) Create check data to verify after returning from RAM backup to normal mode whether the RAM data has been retained normally (➁ in Figure 19.3.3). (2) To materialize low-power operation, set all programmable input/output pins except port X for input mode (or for output mode, with pins outputting a low) (➂ in Figure 19.3.3). (3) Set port X for input mode (B and √ in Figure 19.3.3). This causes the transistor's base voltage, IB, to go low, so that no current flows from the power supply to the VCC pin via the transistor (C in Figure 19.3.3). Consequently, the power to the VCC pin is shut off (D in Figure 19.3.3). Due to settings in (1) to (3), the voltage applied to the VDD pin becomes 3.3 V ± 10% and voltages applied to all other pins drop to 0 V, thus placing the M32R/E in RAM backup mode (√ in Figure 19.2.3). Note 1:This signal outputs a low for RAM backup. Note 2:This pin outputs a high when the power is on, and is set for input mode when in RAM backup mode. Note 3:These pins are used to detect a RAM backup signal. Note 4: ___ Determined by the input voltage level on SBI pin or ADnINi pin. Note 5:Base voltage IB = 0 causes the current fed to the VCC pin to stop. Explained in A to D above. RAM backup signal (Note 1) External circuit Port X IB Power supply for RAMDC IN Input OutputRegulator (3.3V system) OutputRegulator (5V system) OutputRegulator (3.3V system) VREFn SBI ADnINi M32R/E VDD VCCI AVCCnOSC-VCC VCCE (Note 3) (Note 2) 3.3V "L" "L" "L" DC "L" "L" B A 0V0V0V0V0V Example of RAM backup processing Generate RAM backup signal (Note 4) Create check data for backup RAM ➃ RAM backup mode Set transistor's base connecting pin (port X) for input mode (Note 5)

19-8 Rev.1.0 RAM BACKUP MODE Figure 19.3.4 Example of RAM Backup Sequence for Low-Power Operation

19.3.3 Precautions to Be Observed at Power-on

When changing port X from input mode to output mode after power-on, pay attention to the following. If port X is set for output mode while no data is set in the Port X Data Register, the port's initial output level is indeterminate. Therefore, be sure to set the output high level in the Port X Data Register before you set port X for output mode. Unless this method is followed, port output may go low at the same time port output is set after the clock oscillation has stabilized, causing the device to enter RAM backup mode. RESET SBI ADnINi VCCI, OSC-VCC VDD Oscillation stabilization time External input signal goes low RAM backup period Power on Port X Port input mode f (XIN) Port output setting (High level) VCCE, VREFn, AVCCn 3.3V 5.0V Port output setting (High level) External input signal goes high Oscillation stabilization time

19-9 Rev.1.0 RAM BACKUP MODE

19.4 Exiting RAM Backup Mode (Wakeup)

Processing to exit RAM backup mode and return to normal operation is referred to as "wakeup processing." Figure 19.4.1 shows an example of wakeup processing. Wakeup processing is initiated by reset input. The following shows how to execute wakeup processing. (1) Reset the device (➀ in Figure 19.4.1). For details about reset, refer to Chapter 7, "Reset." (2) Set port X for output mode and output a high from the port (➁ in Figure 19.4.1).(Note) (3) Check the RAM contents against the check data created before entering RAM backup mode (➂ in Figure 19.4.1). (4) If the RAM contents and check data did not match when checked in (3), initialize the RAM ({ in Figure 19.4.1). If the RAM contents and check data matched, use the retained data in the program. (5) After initializing each internal circuit (➄ in Figure 19.4.1), return the main routine ( in Figure 19.4.1). Note: For wakeup from power outage RAM backup mode, settings for port X are unnecessary. Figure 19.4.1 Wakeup Processing Note : For wakeup from power outage RAM backup mode, settings for port X are unnecessary. OK Error Check RAM contents against backup RAM check data Initialize RAM Example of wakeup processing Reset Set transistor's base connecting pin (port X) for high-level output mode (Note) Initial each internal circuit To main routine

19-10 Rev.1.0 RAM BACKUP MODE

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20.1 Oscillator Circuit

20.2 Clock Generator Circuit

20-2 Rev.1.0 OSCILLATION CIRCUIT Figure 20.1.1 Example of a System Clock Generating Circuit The M32R/E contains an oscillator circuit that supplies operating clocks for the CPU core, internal peripheral I/O, and internal memory. The frequency fed to the clock input pin (XIN) is multiplied by 4 by the internal PLL circuit to produce the CPU clock, which is the operating clock for the CPU core and internal memory. The frequency of this clock is divided by 2 in the subsequent circuit to produce the internal peripheral clock, which is the operating clock for the internal peripheral I/O.

20.1.1 Example of an Oscillator Circuit

A clock generating circuit can be configured by connecting a ceramic (or crystal) resonator between the XIN and XOUT pins external to the chip. Figure 20.1.1 below shows an example of a system clock generating circuit using a resonator connected external to the chip and an RC network connected to the PLL circuit control pin (VCNT). For constants Rf, CIN, COUT, and Rd, consult your resonator manufacturer to determine the appropriate values. When you use an externally sourced clock signal without using the internal oscillator circuit, connect the external clock signal to the XIN pin and leave the XOUT pin open. M32R/E OSCVCC XIN XOUTOSCVSS Rf Rd C IN C OUT VCNT BCLK / P70 C Oscillator circuit To internal peripheral clock PLL circuit 220pF(Note) 0.1µF (Note) 1KΩ Oscillator module OSCVCC : 3.3 V power supply To CPU clock Note: allowable error ±10% (Note)

20-3 Rev.1.0 OSCILLATION CIRCUIT

20.1.2 System Clock Output Function

A clock whose frequency is twice the input frequency can be output from the BCLK pin. The BCLK pin is shared with port P70. When you use this pin to output the system clock, set the P7 Operation Mode Register (P7MOD)'s D8 bit to 1. Configuration of the P7 Operation Mode Register is shown below. I P7 Operation Mode Register (P7MOD) <Address: H'0080 0747> D 8 9 1 01 11 21 31 4 D 1 5 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD <When reset : H'00> D Bit Name Function R W

8 P70MOD 0 : P70

(Port P70 operation mode) 1 : BCLK

9 P71MOD 0 : P71

(Port P71 operation mode) ____ 1 : WAIT

10 P72MOD 0 : P72

(Port P72 operation mode) ____ 1 : HREQ

11 P73MOD 0 : P73

(Port P73 operation mode) ____ 1 : HACK

12 P74MOD 0 : P74

(Port P74 operation mode) 1 : RTDTXD

13 P75MOD 0 : P75

(Port P75 operation mode) 1 : RTDRXD

14 P76MOD 0 : P76

(Port P76 operation mode) 1 : RTDACK

15 P77MOD 0 : P77

(Port P77 operation mode) 1 : RTDCLK

20-4 Rev.1.0 OSCILLATION CIRCUIT Figure 20.1.2 Oscillation Stabilization Time at Power-on

20.1.3 Oscillation Stabilization Time at Power-on

The oscillator circuit comprised of a ceramic (or crystal) resonator has a finite time after power-on at which its oscillation is instable. Therefore, create a certain amount of oscillation stabilization time that suits the oscillator circuit used. Figure 20.1.2 shows an oscillation stabilization time at power-on. RESET XIN Oscillation stabilization time OSC-VCC

20-5 Rev.1.0 Figure 20.2.1 Configuration of the Clock Generator Circuit OSCILLATION CIRCUIT The clock generator supplies independent clocks to the CPU and internal peripheral circuits. XIN (8MHz - 10MHz) BCLK (16MHz - 20MHz) CPU clock (32MHz - 40MHz) 1/2 internal peripheral clock (8MHz - 10MHz)

20-6 Rev.1.0 OSCILLATION CIRCUIT

• This is a blank page.*

21.1 Outline of the JTAG

21.2 Configuration of the JTAG

21.3 JTAG Registers

21.4 Basic Operation of the JTAG

21.5 Boundary Scan Description

21.6 Precautions on Board Design

21.7 Processing Pins when Not

21-2 Rev.1.0 The 32172/32173 contains a JTAG (Joint Test Action Group) interface based on IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1a-1993). This JTAG interface can be used as an input/output path for boundary-scan test (boundary-scan path). For details about IEEE 1149.1 JTAG test access ports, refer to the IEEE Std. 1149.1a-1993 documentation. The functions of JTAG interface related pins mounted on the 32172/32173 are shown below. Table 21.1.1 JTAG Pin Functions Type Symbol Pin Name I/O Function TAP JTCK Test clock Input Clock input to the test circuit. JTDI Test data input Input Synchronous serial data input pin used to enter test instruction code and test data. This input is sampled on rising edges of JTCK. JTDO Test data output output Synchronous serial data output pin used to output test instruction code and test data. This signal changes state on falling edges of JTCK, and is output only in Shift-IR or Shift- DR state. JTMS Test mode select Input Test mode select input to control the test circuit's state transitions. This input is sampled on rising edges of JTCK. JTRST Test reset Input Active-low test reset input to initialize the test circuit asynchronously. To ensure that the test circuit is reset without fail, JTMS signal input must be held high while this signal changes state from low to high. Note: TAP = Test Access Port, a JTAG interface stipulated in IEEE 1149.1. JTAG (Note)

21-3 Rev.1.0 JTAG

21.2 Configuration of the JTAG Circuit

Figure 21.2.1 Configuration of the JTAG Circuit The 32172/32173's JTAG circuit consists of the following blocks:

• Instruction register to hold instruction codes which are fetched through the boundary-scan path
• A set of data registers which are accessed through the boundary-scan path
• Test access port (abbreviated TAP) controller to control the JTAG unit's state transitions
• Control logic to select input, output, etc. A configuration of the JTAG circuit is shown below. JTCK JTMS JTRST TAP controller Instruction register (6 bits) (JTAGIR) Decoder JTDO ID code register (JTAGIDR) Bypass register (JTAGBPR) Boundary-scan register (JTAGBSR)JTDI Data register set M32R/E Output selection OutputselectionBuffer

21-4 Rev.1.0 JTAG

21.3.1 Instruction Register (JTAGIR)

The Instruction Register (JTAGIR) is a 6-bit register to hold instruction code. This register is set in IR path sequence. The instructions set in this register determine the data register to be selected in the subsequent DR path sequence. When test is reset (to initialize the test circuit), the initial value of this register is b'000010 (IDCODE instruction). After a test reset, the IDCODE Register is selected as the data register until an instruction code is set by an external device. In "Capture-IR" state, this register always has b'110001 (fixed value) loaded into it. Therefore, when in "Shift-IR" state, no matter what value was set in this register, b'110001 is always output from the JTDO pin (sequentially beginning with LSB). However, this value normally is not handled as instruction code. Shown below is outside the scope of guaranteed operations. Note that if this operation is performed, the device may inadvertently handle b'110001 as instruction code, which makes it unable to operate normally. [Capture-IR] → [Exit1-IR] → [Update-IR] The 32172/32173's JTAG interface supports the following instructions:

• Three instructions stipulated as essential in IEEE 1149.1 (EXTEST, SAMPLE/PRELOAD, BYPASS)
• Device ID register access instruction (IDCODE) Table 21.3.1 JTAG Instruction List Instruction Code Abbreviation Operation b'000000 EXTEST Tests circuit/board-level connections outside the chip. b'000001 SAMPLE/PRELOAD Samples operating circuit status and outputs the sampled status from JTDO pin, while at the same time entering the data used for boundary-scan test from the JTDI pin and presets it in Boundary Scan Register. b'000010 IDCODE Selects ID Code Register and outputs device and manufacturer identification data from JTDO pin. b'111111 BYPASS Selects Bypass Register and inspects or sets data. Note 1: Do not set any other instruction code. Note 2: For details about "IR path sequence," "DR path sequence," "Test reset," "Capture-IR" state, "Shift-IR" state, "Exit1-IR" state, and "Update-IR" state, refer to Section 21.4.

21-5 Rev.1.0 JTAG

21.3.2 Data Registers

(1) Boundary Scan Register (JTAGBSR) The Boundary Scan Register is a 471-bit register used to perform boundary-scan test. Bits in this register are assigned to each pin on the 32172/32173. Connected between the JTDI and JTDO pins, this register is selected when issuing EXTEST or SAMPLE/PRELOAD instruction. In "Capture-DR" state, this register captures the status of input pins or internal logic output values. In "Shift-DR" state, while outputting the sampled value, it is used to set pin functions (input/output pin and tristate output pin direction) and output values by entering data for boundary-scan test. (2) Bypass Register (JTAGBPR) The Bypass Register is a 1-bit register used to bypass boundary-scan passes when the 32172/ 32173 is not the target of boundary-scan test. Connected between the JTDI and JTDO pins, this register is selected when issuing BYPASS instruction. This register when in "Capture-DR" state has b'0 (fixed value) loaded into it. (3) ID Code Register (JTAGIDR) The ID Code Register is a 32-bit register used to identify the device and manufacturer. It holds the following information:

• Version information (4 bits) : b'0000
• Part number (16 bits) : b'0011 0010 0010 0000
• Manufacturer ID (11 bits) : b'000 0001 1100 This register is connected between the JTDI and JTDO pins, and is selected when issuing IDCODE instruction. When in "Capture-DR" state, this register has the said IDCODE data loaded into it, which is output from the JTDO pin in "Shift_DR" state. This register is a read-only register, so that the data written from the JTDI pin during DR pass sequence is ignored. Therefore, make sure JTDI input = low during "Shift-DR" state. 03 4 1 9 2 0 3 0 3 1 Version Part number Manufacturer ID 1 4 bits 16 bits 11 bits Note: For details about "Capture-DR" and "Shift-DR" states, refer to Section 21.4.

21-6 Rev.1.0 JTAG

21.4.1 Outline of JTAG Operation

The instruction and data registers basically are accessed in the following three operations, which are performed based on state transitions of the TAP controller. The TAP controller changes state according to JTMS input, and generates control signals required for operation in each state.

• Capture operation The result of boundary-scan test or the fixed data defined for each register is sampled. As register operation, the input data is loaded into the shift register stage.
• Shift operation The register is accessed from outside through the boundary-scan path. The sampled value is output to an external device at the same time data is set from outside. As register operation, bits are shifted right between each shift register stage.
• Update operation The data set from outside during shift is driven. As register operation, the value set in the shift register stage is transferred to the parallel output stage. The JTAG interface undergoes transitions of internal state depending on JTMS input as it performs the following two operations. In either case, the operation basically is performed in order of Capture → Shift → Update.
• IR path sequence Instruction code is set in the instruction register to select the data register to be operated on in the subsequent DR path sequence.
• DR path sequence The selected data register is operated on to inspect or set data.

21-7 Rev.1.0 JTAG The state transitions of the TAP controller and the basic configuration of the 32171's JTAG related registers are shown below. Figure 21.4.2 Basic Configuration of JTAG Related Registers Figure 21.4.1 TAP Controller State Transition Note : Shown here is the basic configuration, and the configuration of DR and IR does not all have to be like this. Data input G D T Q D T R Q "Shift-DR" or "Shift-IR" "Clock-DR" or "Clock-IR" "Update-DR" or "Update-IR" Test reset From preceding cell To next cell Data output Parallel output stage Shift register stageInput multiplexer Note : Values (0 and 1) in this diagram denote the state of JTMS input signal. Select-DR-Scan Test-Logic-Reset Run-Test/Idle Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR 1 0 Select-IR-Scan Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR 1 0 11 1

21-8 Rev.1.0 JTAG

21.4.2 IR Path Sequence

Instruction code is set in the Instruction Register (JTAGIR) to select the data register to be accessed in the subsequent DR path sequence. The IR path sequence is performed following the procedure described below. (1) Enter JTMS = high for a period of two JTCK cycles from "Run-Test/Idle" state to go to "Select-IR-Scan" state. (2) Set JTMS = low to go to "Capture-IR" state. At this time, b'110001 (fixed value) is set in the instruction register's shift register stage. (3) Subsequently, enter JTMS = low to go to "Shift-IR" state. In "Shift-IR" state, the value of the shift register stage is shifted right one bit every cycle, and the data b'110001 (fixed value) that was set in (2) is serially output from the JTDO pin. At the same time, the instruction code serially entered from the JTDI pin is set in the shift register stage bit by bit. Because instruction code is set in the instruction register which is comprised of 6 bits, the "Shift-IR" state continues for a period of 6 JTCK cycles. To stop the shift operation in the middle, go to "Pause-IR" state via temporarily "Exit1-IR" state (by setting JTMS input from high to low). Also, to return from "Pause-IR" state, go to "Shift-IR" state via temporarily "Exit1-IR" state (by setting JTMS input from high to low). (4) By setting JTMS = high, go from "Shift-IR" state to "Exit1-IR" state. This completes the shift operation. (5) Subsequently, enter JTMS = high to go to "Update-IR" state. In "Update-IR" state, the instruction code that was set in the instruction register's shift register stage is transferred to the instruction register's parallel output stage and, thus, JTAG instruction decoding begins. (6) Subsequently, enter JTMS = high to go to "Select-DR-Scan" state or JTMS = low to go to "Run-Test/Idle" state.

21-9 Rev.1.0 JTAG Figure 21.4.3 IR Path Sequence JTCK Select-DR-ScanSelect-IR-Scan Capture-IR Shift-IR Exit1-IRUpdate-IR Run-Test/IdleRun-Test/Idle Don't CareDon't Care Instruction code (6 bits) 1 0 0 0 1 1 LSB value JTMS TAP state JTDI JTDO High impedance Shift output from the instruction register is fixed to b'110001. Finished storing instruction code in the instruction register's shift register stage. Instruction code is set in the parallel output stage at fall of JTCK in "Update-IR" state. JTDI input is sampled at rise of JTCK in "Shift-IR" state. JTDO is output at fall of JTCK in "Shift-IR" state. MSB value High impedance

21-10 Rev.1.0 JTAG

21.4.3 DR Path Sequence

The data register that was selected during the IR path sequence prior to the DR path sequence is operated on to inspect or set data in it. The DR path sequence is performed following the procedure described below. (1) Enter JTMS = high for a period of one JTCK cycle from "Run-Test/Idle" state to go to "Select- DR-Scan" state. Which data register will be selected at this time depends on the instruction that was set during the IR path sequence performed prior to the DR path sequence. (2) Set JTMS = low to go to "Capture-DR" state. At this time, the result of boundary-scan test or the fixed data defined for each register is set in the data register's shift register stage. (3) Subsequently, enter JTMS = low to go to "Shift-DR" state. In "Shift-DR" state, the DR value is shifted right one bit every cycle, and the data that was set in (2) is serially output from the JTDO in. At the same time, the setup data serially entered from the JTDI pin is set in the data register's shift register stage bit by bit. By continuing the "Shift-DR" state as long as the number of bits of the selected data register (by entering JTMS = low), all bits of data can be set in and read out from the shift register stage. To stop the shift operation in the middle, go to "Pause-DR" state via temporarily "Exit1-DR" state (by setting JTMS input from high to low). Also, to return from "Pause-DR" state, go to "Shift-DR" state via temporarily "Exit1-DR" state (by setting JTMS input from high to low). (4) Set JTMS = high to go from "Shift-DR" state to "Exit2-DR" state. This completes the shift operation. (5) Subsequently, enter JTMS = high to go to "Update-DR" state. In "Update-DR" state, the data that was set in the data register's shift register stage is transferred to the parallel output stage and, thus, the setup data becomes ready for use. (6) Subsequently, enter JTMS = high to go to "Select-DR-Scan" state or JTMS = low to go to "Run-Test/Idle" state.

21-11 Rev.1.0 JTAG Figure 21.4.4 DR Path Sequence Note: The shift operation of the data register for the shift register stage is right-shifted, therefore, the output from JTDO is from the LSB side. Input to JTDI starts from the value to be set in LSB side. JTCK Select-DR-Scan Capture-DR Shift-DR Exit1-DRUpdate-DRRun-Test/IdleRun-Test/Idle Don't CareDon't Care JTMS JTDI JTDO Finished storing setup data in the shift register stage of the selected data register. Setup data is set in the parallel output stage at fall of JTCK in "Update-DR" state. JTDI input is sampled at rise of JTCK in "Shift-DR" state. TAP state LSB value High impedance MSB value High impedance JTDO is output at fall of JTCK in "Shift-DR" state.

21-12 Rev.1.0 JTAG

21.4.4 Examining and Setting Data Registers

To inspect or set the data register, follow the procedure described below. (1) To access the test access port (JTAG) for the first time, enter test reset (to initialize the test circuit). Test reset can be entered by one of the following two methods:

• Pull JTRST pin input low
• Drive JTMS pin input high and enter JTCK for 5 cycles or more (2) Set JTMS = low to go to "Run-Test/Idle" state. To continue the idle state, hold JTMS input low. (3) Set JTMS = high to exit "Run-Test/Idle" state and perform IR path sequence. In IR path sequence, specify the data register you want to inspect or set. (4) Subsequently, perform DR path sequence. For the data register specified in IR path sequence, enter setup data from the JTDI pin and read out reference data from the JTDO pin. (5) If after DR path sequence is completed you want to proceed and perform IR path sequence or DR path sequence, enter JTMS = high to return to "Select-DR-Scan" state. If after a series of IR and DR path sequence processing is completed you want to wait for the next processing, enter JTMS = low to go to "Run-Test/Idle" state and retain the state.

21-13 Rev.1.0 JTAG Figure 21.4.5 Continuous JTAG Access Note 1 : The setup value for each register must be entered from the JTDI pin beginning with the LSB. Note 2 : The value of each register is output from the JTDO pin beginning with the LSB. The JTDO pin outputs valid data in only "Shift-IR" state of IR path sequence and "Shift-DR" state of DR path sequence. In all other states, the JTDO pin is tristated (high impedance). Note 3 : Data can only be read out from the data register which is selected by the instruction that was set in the immediately preceding IR path sequence. Output in the selected data register's shift register stage is the value that was sampled during "Capture-DR" state. Specify the data register you want to inspect or set. Test-Logic- Reset state Run-Test /Idle state IR path sequence TAP states Instruction code #0 Setup data JTDI (Note 1) Fixed value b'110001 (Note 3)JTDO (Note 2) Setup data is entered serially from JTDI. Reference data is serially output from JTDO. (1) Basic access Same data register can be operated on to inspect or set data continuously. (2) Continuous access to the same data register Specify the data register you want to inspect or set. DR path sequence Run-Test /Idle state IR path sequence DR path sequence Instruction code #1 Setup data Fixed value b'110001 (Note 3) Test-Logic- Reset state Run-Test /Idle state IR path sequence TAP states Instruction code #0 Setup data JTDI (Note 1) Fixed value b'110001 (Note 3)JTDO (Note 2) DR path sequence Run-Test /Idle state IR path sequence DR path sequence Setup data (Note 3) Setup data (Note 3)

21-14 Rev.1.0 JTAG

21.5 Boundary Scan Description Language

The Boundary Scan Description Language (abbreviated BSDL) is stipulated in supplements to "Standard Test Access Port and Boundary-Scan Architecture" of IEEE 1149.1-1990 and IEEE 1149.1a-1993. BSDL is a subset of IEEE 1076-1993 Standard VHSIC Hardware Description Language (VHDL). BSDL helps to precisely describe the functions of standard-compliant components to be tested. For package connection test, this language is used by Automated Test Pattern Generation tools, and for synthesized test logic and verification, it is used by Electronic Design Automation tools. BSDL provides powerful extended functions usable in internal test generation and necessary to write hardware debug and diagnostics software. The primary section of BSDL contains statements of logical port description, physical pin map, instruction set, and boundary register description.

• Logical port description The logical port description assigns meaningful symbol names to each pin on the chip. This determines the logic type of input, output, input/output, buffer, or link of each pin that defines the logical direction of signal flow.
• Physical pin map The physical pin map correlates the chip's logical ports to the physical pins on each package. Use of separate names for each map makes it possible to define multiple physical pin maps in one BSDL description.
• Instruction set statement The instruction set statement writes bit patterns to be shifted in into the chip's instruction register. This bit pattern is necessary to place the chip into each test mode defined in standards. It is also possible to write instructions exclusive to the chip.
• Boundary register description The boundary register description is a list of boundary register cells or shift stages. Each cell is assigned a separate number. The cell with number 0 is located closest to the test data output (JTDO) pin, and the cell with the largest number is located closest to the test data input (JTDI) pin. Cells also contain related other information which includes cell type, logical port corresponding to cell, logical function of cell, safety value, control cell number, disable value, and result value. The BSDL for the 32172/32173 shown in the pages to follow have been prepared for use in test engineering for the purpose of PCB design and those stipulated in IEEE 1149.1 standards.

21-15 Rev.1.0 Figure 21.5.1 BSDL Description for the 32173(1/11) -- Boundary Scan Description Language (BSDL) for -- M32173F2VFP: M32R/E M32173 Group, Flash 256KB, 144P6Q -- Modification History -- Date Author Version -- Created '00/10/05 MITSUBISHI Ver. 0.0 -- Modified '--/--/-- entity M32173F2VFP is generic (PHYSICAL_PIN_MAP : string := "P6Q144"); port ( P221 :in bit; P225 :inout bit; OSCVSS_3 :linkage bit; XIN :in bit; XOUT :buffer bit; OSCVCC_6 :linkage bit; VCNT_7 :linkage bit; P30 :inout bit; P31 :inout bit; P32 :inout bit; P33 :inout bit; P34 :inout bit; P35 :inout bit; P36 :inout bit; P37 :inout bit; P20 :inout bit; P21 :inout bit; P22 :inout bit; P23 :inout bit; VCCE_20 :linkage bit; VSS_21 :linkage bit; P24 :inout bit; P25 :inout bit; P26 :inout bit; P27 :inout bit; P00 :inout bit; P01 :inout bit; P02 :inout bit; P03 :inout bit; P04 :inout bit; P05 :inout bit; P06 :inout bit; P07 :inout bit; P10 :inout bit; P11 :inout bit; P12 :inout bit; P13 :inout bit; P14 :inout bit; P15 :inout bit; P16 :inout bit; P17 :inout bit; VREF_42 :linkage bit; AVCC_43 :linkage bit; AD0IN0 :linkage bit; AD0IN1 :linkage bit; JTAG

21-16 Rev.1.0 JTAG Figure 21.5.2 BSDL Description for the 32173(2/11) AD0IN2 :linkage bit; AD0IN3 :linkage bit; AD0IN4 :linkage bit; AD0IN5 :linkage bit; AD0IN6 :linkage bit; AD0IN7 :linkage bit; AD1IN0 :linkage bit; AD1IN1 :linkage bit; AD1IN2 :linkage bit; AD1IN3 :linkage bit; DA0 :linkage bit; DA1 :linkage bit; P172 :in bit; P173 :in bit; AVSS_60 :linkage bit; VCCI_61 :linkage bit; VSS_62 :linkage bit; P174 :inout bit; P175 :inout bit; VCCE_65 :linkage bit; P82 :inout bit; P83 :inout bit; P84 :inout bit; P85 :inout bit; P86 :inout bit; P87 :inout bit; VSS_72 :linkage bit; FVCC_73 :linkage bit; P61 :inout bit; P62 :inout bit; P63 :inout bit; P64 :in bit; P70 :inout bit; P71 :inout bit; P72 :inout bit; P73 :inout bit; P74 :inout bit; P75 :inout bit; P76 :inout bit; P77 :inout bit; P93 :in bit; P94 :inout bit; P95 :inout bit; P96 :inout bit; P97 :in bit; RESET :in bit; MOD0 :in bit; MOD1 :in bit; FP :in bit; VCCE_95 :linkage bit; VSS_96 :linkage bit; P110 :inout bit; P111 :inout bit; P112 :inout bit; P113 :inout bit; P114 :inout bit; P115 :inout bit; P116 :inout bit; P117 :inout bit; P100 :inout bit;

21-17 Rev.1.0 JTAG Figure 21.5.3 BSDL Description for the 32173(3/11) P101 :inout bit; P102 :inout bit; VDD_108 :linkage bit; TMS :in bit; TCK :in bit; TRST :in bit; TDO :out bit; TDI :in bit; P103 :inout bit; P104 :inout bit; P105 :inout bit; P106 :inout bit; P107 :inout bit; P124 :in bit; P125 :in bit; P126 :in bit; P127 :in bit; VCCI_123 :linkage bit; P130 :in bit; P131 :in bit; P132 :in bit; P133 :in bit; P134 :in bit; P135 :in bit; P136 :in bit; P137 :in bit; VCCE_132 :linkage bit; P150 :inout bit; P153 :inout bit; P41 :inout bit; P42 :inout bit; VCCI_137 :linkage bit; VSS_138 :linkage bit; P43 :inout bit; P44 :inout bit; P45 :inout bit; P46 :inout bit; P47 :inout bit; P220 :inout bit use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of M32173F2VFP : entity is "STD_1149_1_1993"; attribute PIN_MAP of M32173F2VFP : entity is PHYSICAL_PIN_MAP; constant P6Q144 : PIN_MAP_STRING := "P221 :1," & "P225 :2," & "OSCVSS_3 :3," & "XIN :4," & "XOUT :5," & "OSCVCC_6 :6," & "VCNT_7 :7," & "P30 :8," & "P31 :9," & "P32 :10," & "P33 :11," & "P34 :12," &

21-18 Rev.1.0 JTAG Figure 21.5.4 BSDL Description for the 32173(4/11) "P35 :13," & "P36 :14," & "P37 :15," & "P20 :16," & "P21 :17," & "P22 :18," & "P23 :19," & "VCCE_20 :20," & "VSS_21 :21," & "P24 :22," & "P25 :23," & "P26 :24," & "P27 :25," & "P00 :26," & "P01 :27," & "P02 :28," & "P03 :29," & "P04 :30," & "P05 :31," & "P06 :32," & "P07 :33," & "P10 :34," & "P11 :35," & "P12 :36," & "P13 :37," & "P14 :38," & "P15 :39," & "P16 :40," & "P17 :41," & "VREF_42 :42," & "AVCC_43 :43," & "AD0IN0 :44," & "AD0IN1 :45," & "AD0IN2 :46," & "AD0IN3 :47," & "AD0IN4 :48," & "AD0IN5 :49," & "AD0IN6 :50," & "AD0IN7 :51," & "AD1IN0 :52," & "AD1IN1 :53," & "AD1IN2 :54," & "AD1IN3 :55," & "DA0 :56," & "DA1 :57," & "P172 :58," & "P173 :59," & "AVSS_60 :60," & "VCCI_61 :61," & "VSS_62 :62," & "P174 :63," & "P175 :64," & "VCCE_65 :65," & "P82 :66," & "P83 :67," & "P84 :68," & "P85 :69," & "P86 :70," & "P87 :71," & "VSS_72 :72," &

21-19 Rev.1.0 JTAG Figure 21.5.5 BSDL Description for the 32173(5/11) "FVCC_73 :73," & "P61 :74," & "P62 :75," & "P63 :76," & "P64 :77," & "P70 :78," & "P71 :79," & "P72 :80," & "P73 :81," & "P74 :82," & "P75 :83," & "P76 :84," & "P77 :85," & "P93 :86," & "P94 :87," & "P95 :88," & "P96 :89," & "P97 :90," & "RESET :91," & "MOD0 :92," & "MOD1 :93," & "FP :94," & "VCCE_95 :95," & "VSS_96 :96," & "P110 :97," & "P111 :98," & "P112 :99," & "P113 :100," & "P114 :101," & "P115 :102," & "P116 :103," & "P117 :104," & "P100 :105," & "P101 :106," & "P102 :107," & "VDD_108 :108," & "TMS :109," & "TCK :110," & "TRST :111," & "TDO :112," & "TDI :113," & "P103 :114," & "P104 :115," & "P105 :116," & "P106 :117," & "P107 :118," & "P124 :119," & "P125 :120," & "P126 :121," & "P127 :122," & "VCCI_123 :123," & "P130 :124," & "P131 :125," & "P132 :126," & "P133 :127," & "P134 :128," & "P135 :129," & "P136 :130," & "P137 :131," & "VCCE_132 :132," &

21-20 Rev.1.0 JTAG "P150 :133," & "P153 :134," & "P41 :135," & "P42 :136," & "VCCI_137 :137," & "VSS_138 :138," & "P43 :139," & "P44 :140," & "P45 :141," & "P46 :142," & "P47 :143," & "P220 :144" ; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (5.0e6, BOTH); attribute TAP_SCAN_RESET of TRST : signal is true; attribute INSTRUCTION_LENGTH of M32173F2VFP : entity is 6; attribute INSTRUCTION_OPCODE of M32173F2VFP : entity is "BYPASS (111111)," & "SAMPLE (000001)," & "EXTEST (000000)," & "IDCODE (000010)," & "USERCODE (000011)," & "MDM_SYSTEM (001000)," & "MDM_CONTROL (001001)," & "MDM_SETUP (001010)," & "MTM_CONTROL (001111)," & "MON_CODE (010000)," & "MON_DATA (010001)," & "MON_PARAM (010010)," & "MON_ACCESS (010011)," & "DMA_RADDR (011000)," & "DMA_RDATA (011001)," & "DMA_RTYPE (011010)," & "DMA_ACCESS (011011)," & "RTDENB (100000)" ; attribute INSTRUCTION_CAPTURE of M32173F2VFP : entity is "110001"; attribute INSTRUCTION_PRIVATE of M32173F2VFP : entity is "MDM_SYSTEM," & "MDM_CONTROL," & "MDM_SETUP," & "MTM_CONTROL," & "MON_CODE," & "MON_DATA," & "MON_PARAM," & "MON_ACCESS," & "DMA_RADDR," & "DMA_RDATA," & "DMA_RTYPE," & "DMA_ACCESS," & "RTDENB" ; Figure 21.5.6 BSDL Description for the 32173(6/11)

21-21 Rev.1.0 JTAG attribute IDCODE_REGISTER of M32173F2VFP : entity is "0000" & -- version "0011001000100001" & -- part number "00000011100" & -- manufacturer's identity "1"; -- required by 1149.1 --- attribute USERCODE_REGISTER of M32173F2VFP : entity is --- "0000 0000 0000 0000" & -- reserved --- "0000" & -- reserved --- "0001"; -- SDI version attribute REGISTER_ACCESS of M32173F2VFP : entity is "Bypass (BYPASS)," & "Boundary (SAMPLE, EXTEST)," & "Device_ID (IDCODE)," & "USERCODE_REG[32] (USERCODE)," & "MDM_SYSTEM_REG[17] (MDM_SYSTEM)," & "MDM_CONTROL_REG[20] (MDM_CONTROL)," & "MDM_SETUP_REG[2] (MDM_SETUP)," & "MTM_CONTROL_REG[4] (MTM_CONTROL)," & "MON_CODE_REG[32] (MON_CODE)," & "MON_DATA_REG[32] (MON_DATA)," & "MON_PARAM_REG[32] (MON_PARAM)," & "MON_ACCESS_REG[4] (MON_ACCESS)," & "DMA_RADDR_REG[32] (DMA_RADDR)," & "DMA_RDATA_REG[32] (DMA_RDATA)," & "DMA_RTYPE_REG[3] (DMA_RTYPE)," & "DMA_ACCESS_REG[3] (DMA_ACCESS)," & "RTDENB_REG[1] (RTDENB)"; attribute BOUNDARY_LENGTH of M32173F2VFP : entity is 265; attribute BOUNDARY_REGISTER of M32173F2VFP : entity is -- num cell port function safe [ccell disval rslt] "264 (BC_4, P103, observe_only, X)," & "263 (BC_1, P103, output3, X, 262, 0, Z)," & "262 (BC_1, *, control, 0)," & "261 (BC_4, P104, observe_only, X)," & "260 (BC_1, P104, output3, X, 259, 0, Z)," & "259 (BC_1, *, control, 0)," & "258 (BC_4, P105, observe_only, X)," & "257 (BC_1, P105, output3, X, 256, 0, Z)," & "256 (BC_1, *, control, 0)," & "255 (BC_4, P106, observe_only, X)," & "254 (BC_1, P106, output3, X, 253, 0, Z)," & "253 (BC_1, *, control, 0)," & "252 (BC_4, P107, observe_only, X)," & "251 (BC_1, P107, output3, X, 250, 0, Z)," & "250 (BC_1, *, control, 0)," & "249 (BC_4, P124, observe_only, X)," & "248 (BC_4, P125, observe_only, X)," & "247 (BC_4, P126, observe_only, X)," & "246 (BC_4, P127, observe_only, X)," & "245 (BC_4, P130, observe_only, X)," & "244 (BC_4, P131, observe_only, X)," & "243 (BC_4, P132, observe_only, X)," & Figure 21.5.7 BSDL Description for the 32173(7/11)

21-22 Rev.1.0 JTAG "242 (BC_4, P133, observe_only, X)," & "241 (BC_4, P134, observe_only, X)," & "240 (BC_4, P135, observe_only, X)," & "239 (BC_4, P136, observe_only, X)," & "238 (BC_4, P137, observe_only, X)," & "237 (BC_4, P150, observe_only, X)," & "236 (BC_1, P150, output3, X, 235, 0, Z)," & "235 (BC_1, *, control, 0)," & "234 (BC_4, P153, observe_only, X)," & "233 (BC_1, P153, output3, X, 232, 0, Z)," & "232 (BC_1, *, control, 0)," & "231 (BC_4, P41, observe_only, X)," & "230 (BC_1, P41, output3, X, 229, 0, Z)," & "229 (BC_1, *, control, 0)," & "228 (BC_4, P42, observe_only, X)," & "227 (BC_1, P42, output3, X, 226, 0, Z)," & "226 (BC_1, *, control, 0)," & "225 (BC_4, P43, observe_only, X)," & "224 (BC_1, P43, output3, X, 223, 0, Z)," & "223 (BC_1, *, control, 0)," & "222 (BC_4, P44, observe_only, X)," & "221 (BC_1, P44, output3, X, 220, 0, Z)," & "220 (BC_1, *, control, 0)," & "219 (BC_4, P45, observe_only, X)," & "218 (BC_1, P45, output3, X, 217, 0, Z)," & "217 (BC_1, *, control, 0)," & "216 (BC_4, P46, observe_only, X)," & "215 (BC_1, P46, output3, X, 214, 0, Z)," & "214 (BC_1, *, control, 0)," & "213 (BC_4, P47, observe_only, X)," & "212 (BC_1, P47, output3, X, 211, 0, Z)," & "211 (BC_1, *, control, 0)," & "210 (BC_4, P220, observe_only, X)," & "209 (BC_1, P220, output3, X, 208, 0, Z)," & "208 (BC_1, *, control, 0)," & "207 (BC_4, P221, observe_only, X)," & "206 (BC_4, P225, observe_only, X)," & "205 (BC_1, P225, output3, X, 204, 0, Z)," & "204 (BC_1, *, control, 0)," & "203 (BC_4, P30, observe_only, X)," & "202 (BC_1, P30, output3, X, 201, 0, Z)," & "201 (BC_1, *, control, 0)," & "200 (BC_4, P31, observe_only, X)," & "199 (BC_1, P31, output3, X, 198, 0, Z)," & "198 (BC_1, *, control, 0)," & "197 (BC_4, P32, observe_only, X)," & "196 (BC_1, P32, output3, X, 195, 0, Z)," & "195 (BC_1, *, control, 0)," & "194 (BC_4, P33, observe_only, X)," & "193 (BC_1, P33, output3, X, 192, 0, Z)," & "192 (BC_1, *, control, 0)," & "191 (BC_4, P34, observe_only, X)," & "190 (BC_1, P34, output3, X, 189, 0, Z)," & "189 (BC_1, *, control, 0)," & "188 (BC_4, P35, observe_only, X)," & "187 (BC_1, P35, output3, X, 186, 0, Z)," & "186 (BC_1, *, control, 0)," & "185 (BC_4, P36, observe_only, X)," & "184 (BC_1, P36, output3, X, 183, 0, Z)," & "183 (BC_1, *, control, 0)," & Figure 21.5.8 BSDL Description for the 32173(8/11)

21-23 Rev.1.0 JTAG "182 (BC_4, P37, observe_only, X)," & "181 (BC_1, P37, output3, X, 180, 0, Z)," & "180 (BC_1, *, control, 0)," & "179 (BC_4, P20, observe_only, X)," & "178 (BC_1, P20, output3, X, 177, 0, Z)," & "177 (BC_1, *, control, 0)," & "176 (BC_4, P21, observe_only, X)," & "175 (BC_1, P21, output3, X, 174, 0, Z)," & "174 (BC_1, *, control, 0)," & "173 (BC_4, P22, observe_only, X)," & "172 (BC_1, P22, output3, X, 171, 0, Z)," & "171 (BC_1, *, control, 0)," & "170 (BC_4, P23, observe_only, X)," & "169 (BC_1, P23, output3, X, 168, 0, Z)," & "168 (BC_1, *, control, 0)," & "167 (BC_4, P24, observe_only, X)," & "166 (BC_1, P24, output3, X, 165, 0, Z)," & "165 (BC_1, *, control, 0)," & "164 (BC_4, P25, observe_only, X)," & "163 (BC_1, P25, output3, X, 162, 0, Z)," & "162 (BC_1, *, control, 0)," & "161 (BC_4, P26, observe_only, X)," & "160 (BC_1, P26, output3, X, 159, 0, Z)," & "159 (BC_1, *, control, 0)," & "158 (BC_4, P27, observe_only, X)," & "157 (BC_1, P27, output3, X, 156, 0, Z)," & "156 (BC_1, *, control, 0)," & "155 (BC_4, P00, observe_only, X)," & "154 (BC_1, P00, output3, X, 153, 0, Z)," & "153 (BC_1, *, control, 0)," & "152 (BC_4, P01, observe_only, X)," & "151 (BC_1, P01, output3, X, 150, 0, Z)," & "150 (BC_1, *, control, 0)," & "149 (BC_4, P02, observe_only, X)," & "148 (BC_1, P02, output3, X, 147, 0, Z)," & "147 (BC_1, *, control, 0)," & "146 (BC_4, P03, observe_only, X)," & "145 (BC_1, P03, output3, X, 144, 0, Z)," & "144 (BC_1, *, control, 0)," & "143 (BC_4, P04, observe_only, X)," & "142 (BC_1, P04, output3, X, 141, 0, Z)," & "141 (BC_1, *, control, 0)," & "140 (BC_4, P05, observe_only, X)," & "139 (BC_1, P05, output3, X, 138, 0, Z)," & "138 (BC_1, *, control, 0)," & "137 (BC_4, P06, observe_only, X)," & "136 (BC_1, P06, output3, X, 135, 0, Z)," & "135 (BC_1, *, control, 0)," & "134 (BC_4, P07, observe_only, X)," & "133 (BC_1, P07, output3, X, 132, 0, Z)," & "132 (BC_1, *, control, 0)," & "131 (BC_4, P10, observe_only, X)," & "130 (BC_1, P10, output3, X, 129, 0, Z)," & "129 (BC_1, *, control, 0)," & "128 (BC_4, P11, observe_only, X)," & "127 (BC_1, P11, output3, X, 126, 0, Z)," & "126 (BC_1, *, control, 0)," & "125 (BC_4, P12, observe_only, X)," & "124 (BC_1, P12, output3, X, 123, 0, Z)," & "123 (BC_1, *, control, 0)," & Figure 21.5.9 BSDL Description for the 32173(9/11)

21-24 Rev.1.0 JTAG "122 (BC_4, P13, observe_only, X)," & "121 (BC_1, P13, output3, X, 120, 0, Z)," & "120 (BC_1, *, control, 0)," & "119 (BC_4, P14, observe_only, X)," & "118 (BC_1, P14, output3, X, 117, 0, Z)," & "117 (BC_1, *, control, 0)," & "116 (BC_4, P15, observe_only, X)," & "115 (BC_1, P15, output3, X, 114, 0, Z)," & "114 (BC_1, *, control, 0)," & "113 (BC_4, P16, observe_only, X)," & "112 (BC_1, P16, output3, X, 111, 0, Z)," & "111 (BC_1, *, control, 0)," & "110 (BC_4, P17, observe_only, X)," & "109 (BC_1, P17, output3, X, 108, 0, Z)," & "108 (BC_1, *, control, 0)," & "107 (BC_4, P172, observe_only, X)," & "106 (BC_4, P173, observe_only, X)," & "105 (BC_4, P174, observe_only, X)," & "104 (BC_1, P174, output3, X, 103, 0, Z)," & "103 (BC_1, *, control, 0)," & "102 (BC_4, P175, observe_only, X)," & "101 (BC_1, P175, output3, X, 100, 0, Z)," & "100 (BC_1, *, control, 0)," & "99 (BC_4, P82, observe_only, X)," & "98 (BC_1, P82, output3, X, 97, 0, Z)," & "97 (BC_1, *, control, 0)," & "96 (BC_4, P83, observe_only, X)," & "95 (BC_1, P83, output3, X, 94, 0, Z)," & "94 (BC_1, *, control, 0)," & "93 (BC_4, P84, observe_only, X)," & "92 (BC_1, P84, output3, X, 91, 0, Z)," & "91 (BC_1, *, control, 0)," & "90 (BC_4, P85, observe_only, X)," & "89 (BC_1, P85, output3, X, 88, 0, Z)," & "88 (BC_1, *, control, 0)," & "87 (BC_4, P86, observe_only, X)," & "86 (BC_1, P86, output3, X, 85, 0, Z)," & "85 (BC_1, *, control, 0)," & "84 (BC_4, P87, observe_only, X)," & "83 (BC_1, P87, output3, X, 82, 0, Z)," & "82 (BC_1, *, control, 0)," & "81 (BC_4, P61, observe_only, X)," & "80 (BC_1, P61, output3, X, 79, 0, Z)," & "79 (BC_1, *, control, 0)," & "78 (BC_4, P62, observe_only, X)," & "77 (BC_1, P62, output3, X, 76, 0, Z)," & "76 (BC_1, *, control, 0)," & "75 (BC_4, P63, observe_only, X)," & "74 (BC_1, P63, output3, X, 73, 0, Z)," & "73 (BC_1, *, control, 0)," & "72 (BC_4, P64, observe_only, X)," & "71 (BC_4, P70, observe_only, X)," & "70 (BC_1, P70, output3, X, 69, 0, Z)," & "69 (BC_1, *, control, 0)," & "68 (BC_4, P71, observe_only, X)," & "67 (BC_1, P71, output3, X, 66, 0, Z)," & "66 (BC_1, *, control, 0)," & "65 (BC_4, P72, observe_only, X)," & "64 (BC_1, P72, output3, X, 63, 0, Z)," & "63 (BC_1, *, control, 0)," & Figure 21.5.10 BSDL Description for the 32173(10/11)

21-25 Rev.1.0 JTAG "62 (BC_4, P73, observe_only, X)," & "61 (BC_1, P73, output3, X, 60, 0, Z)," & "60 (BC_1, *, control, 0)," & "59 (BC_4, P74, observe_only, X)," & "58 (BC_1, P74, output3, X, 57, 0, Z)," & "57 (BC_1, *, control, 0)," & "56 (BC_4, P75, observe_only, X)," & "55 (BC_1, P75, output3, X, 54, 0, Z)," & "54 (BC_1, *, control, 0)," & "53 (BC_4, P76, observe_only, X)," & "52 (BC_1, P76, output3, X, 51, 0, Z)," & "51 (BC_1, *, control, 0)," & "50 (BC_4, P77, observe_only, X)," & "49 (BC_1, P77, output3, X, 48, 0, Z)," & "48 (BC_1, *, control, 0)," & "47 (BC_4, P93, observe_only, X)," & "46 (BC_4, P94, observe_only, X)," & "45 (BC_1, P94, output3, X, 44, 0, Z)," & "44 (BC_1, *, control, 0)," & "43 (BC_4, P95, observe_only, X)," & "42 (BC_1, P95, output3, X, 41, 0, Z)," & "41 (BC_1, *, control, 0)," & "40 (BC_4, P96, observe_only, X)," & "39 (BC_1, P96, output3, X, 38, 0, Z)," & "38 (BC_1, *, control, 0)," & "37 (BC_4, P97, observe_only, X)," & "36 (BC_4, RESET, observe_only, X)," & "35 (BC_4, MOD0, observe_only, X)," & "34 (BC_4, MOD1, observe_only, X)," & "33 (BC_4, FP, observe_only, X)," & "32 (BC_4, P110, observe_only, X)," & "31 (BC_1, P110, output3, X, 30, 0, Z)," & "30 (BC_1, *, control, 0)," & "29 (BC_4, P111, observe_only, X)," & "28 (BC_1, P111, output3, X, 27, 0, Z)," & "27 (BC_1, *, control, 0)," & "26 (BC_4, P112, observe_only, X)," & "25 (BC_1, P112, output3, X, 24, 0, Z)," & "24 (BC_1, *, control, 0)," & "23 (BC_4, P113, observe_only, X)," & "22 (BC_1, P113, output3, X, 21, 0, Z)," & "21 (BC_1, *, control, 0)," & "20 (BC_4, P114, observe_only, X)," & "19 (BC_1, P114, output3, X, 18, 0, Z)," & "18 (BC_1, *, control, 0)," & "17 (BC_4, P115, observe_only, X)," & "16 (BC_1, P115, output3, X, 15, 0, Z)," & "15 (BC_1, *, control, 0)," & "14 (BC_4, P116, observe_only, X)," & "13 (BC_1, P116, output3, X, 12, 0, Z)," & "12 (BC_1, *, control, 0)," & "11 (BC_4, P117, observe_only, X)," & "10 (BC_1, P117, output3, X, 9, 0, Z)," & "9 (BC_1, *, control, 0)," & "8 (BC_4, P100, observe_only, X)," & "7 (BC_1, P100, output3, X, 6, 0, Z)," & "6 (BC_1, *, control, 0)," & "5 (BC_4, P101, observe_only, X)," & "4 (BC_1, P101, output3, X, 3, 0, Z)," & "3 (BC_1, *, control, 0)," & "2 (BC_4, P102, observe_only, X)," & "1 (BC_1, P102, output3, X, 0, 0, Z)," & "0 (BC_1, *, control, 0)"; end M32173F2VFP; Figure 21.5.11 BSDL Description for the 32173(11/11)

21-26 Rev.1.0 JTAG Figure 21.5.12 BSDL Description for the 32172(1/11) -- Boundary Scan Description Language (BSDL) for -- M32172F2VFP: M32R/E M32172 Group, Flash 256KB, 144P6Q -- Modification History -- Date Author Version -- Created '00/10/05 MITSUBISHI Ver. 0.0 -- Modified '--/--/-- entity M32172F2VFP is generic (PHYSICAL_PIN_MAP : string := "P6Q144"); port ( P221 :in bit; P225 :inout bit; OSCVSS_3 :linkage bit; XIN :in bit; XOUT :buffer bit; OSCVCC_6 :linkage bit; VCNT_7 :linkage bit; P30 :inout bit; P31 :inout bit; P32 :inout bit; P33 :inout bit; P34 :inout bit; P35 :inout bit; P36 :inout bit; P37 :inout bit; P20 :inout bit; P21 :inout bit; P22 :inout bit; P23 :inout bit; VCCE_20 :linkage bit; VSS_21 :linkage bit; P24 :inout bit; P25 :inout bit; P26 :inout bit; P27 :inout bit; P00 :inout bit; P01 :inout bit; P02 :inout bit; P03 :inout bit; P04 :inout bit; P05 :inout bit; P06 :inout bit; P07 :inout bit; P10 :inout bit; P11 :inout bit; P12 :inout bit; P13 :inout bit; P14 :inout bit; P15 :inout bit; P16 :inout bit; P17 :inout bit; VREF_42 :linkage bit; AVCC_43 :linkage bit; AD0IN0 :linkage bit; AD0IN1 :linkage bit;

21-27 Rev.1.0 JTAG Figure 21.5.13 BSDL Description for the 32172(2/11) AD0IN2 :linkage bit; AD0IN3 :linkage bit; AD0IN4 :linkage bit; AD0IN5 :linkage bit; AD0IN6 :linkage bit; AD0IN7 :linkage bit; AD1IN0 :linkage bit; AD1IN1 :linkage bit; AD1IN2 :linkage bit; AD1IN3 :linkage bit; DA0 :linkage bit; DA1 :linkage bit; P172 :in bit; P173 :in bit; AVSS_60 :linkage bit; VCCI_61 :linkage bit; VSS_62 :linkage bit; P174 :inout bit; P175 :inout bit; VCCE_65 :linkage bit; P82 :inout bit; P83 :inout bit; P84 :inout bit; P85 :inout bit; P86 :inout bit; P87 :inout bit; VSS_72 :linkage bit; FVCC_73 :linkage bit; P61 :inout bit; P62 :inout bit; P63 :inout bit; P64 :in bit; P70 :inout bit; P71 :inout bit; P72 :inout bit; P73 :inout bit; P74 :inout bit; P75 :inout bit; P76 :inout bit; P77 :inout bit; P93 :in bit; P94 :inout bit; P95 :inout bit; P96 :inout bit; P97 :in bit; RESET :in bit; MOD0 :in bit; MOD1 :in bit; FP :in bit; VCCE_95 :linkage bit; VSS_96 :linkage bit; P110 :inout bit; P111 :inout bit; P112 :inout bit; P113 :inout bit; P114 :inout bit; P115 :inout bit; P116 :inout bit; P117 :inout bit; P100 :inout bit;

21-28 Rev.1.0 JTAG P101 :inout bit; P102 :inout bit; VDD_108 :linkage bit; TMS :in bit; TCK :in bit; TRST :in bit; TDO :out bit; TDI :in bit; P103 :inout bit; P104 :inout bit; P105 :inout bit; P106 :inout bit; P107 :inout bit; P124 :in bit; P125 :in bit; P126 :in bit; P127 :in bit; VCCI_123 :linkage bit; P130 :in bit; P131 :in bit; P132 :in bit; P133 :in bit; P134 :in bit; P135 :in bit; P136 :in bit; P137 :in bit; VCCE_132 :linkage bit; P150 :inout bit; P153 :inout bit; P41 :inout bit; P42 :inout bit; VCCI_137 :linkage bit; VSS_138 :linkage bit; P43 :inout bit; P44 :inout bit; P45 :inout bit; P46 :inout bit; P47 :inout bit; P220 :inout bit use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of M32172F2VFP : entity is "STD_1149_1_1993"; attribute PIN_MAP of M32172F2VFP : entity is PHYSICAL_PIN_MAP; constant P6Q144 : PIN_MAP_STRING := "P221 :1," & "P225 :2," & "OSCVSS_3 :3," & "XIN :4," & "XOUT :5," & "OSCVCC_6 :6," & "VCNT_7 :7," & "P30 :8," & "P31 :9," & "P32 :10," & "P33 :11," & "P34 :12," & Figure 21.5.14 BSDL Description for the 32172(3/11)

21-29 Rev.1.0 JTAG "P35 :13," & "P36 :14," & "P37 :15," & "P20 :16," & "P21 :17," & "P22 :18," & "P23 :19," & "VCCE_20 :20," & "VSS_21 :21," & "P24 :22," & "P25 :23," & "P26 :24," & "P27 :25," & "P00 :26," & "P01 :27," & "P02 :28," & "P03 :29," & "P04 :30," & "P05 :31," & "P06 :32," & "P07 :33," & "P10 :34," & "P11 :35," & "P12 :36," & "P13 :37," & "P14 :38," & "P15 :39," & "P16 :40," & "P17 :41," & "VREF_42 :42," & "AVCC_43 :43," & "AD0IN0 :44," & "AD0IN1 :45," & "AD0IN2 :46," & "AD0IN3 :47," & "AD0IN4 :48," & "AD0IN5 :49," & "AD0IN6 :50," & "AD0IN7 :51," & "AD1IN0 :52," & "AD1IN1 :53," & "AD1IN2 :54," & "AD1IN3 :55," & "DA0 :56," & "DA1 :57," & "P172 :58," & "P173 :59," & "AVSS_60 :60," & "VCCI_61 :61," & "VSS_62 :62," & "P174 :63," & "P175 :64," & "VCCE_65 :65," & "P82 :66," & "P83 :67," & "P84 :68," & "P85 :69," & "P86 :70," & "P87 :71," & "VSS_72 :72," & Figure 21.5.15 BSDL Description for the 32172(4/11)

21-30 Rev.1.0 JTAG Figure 21.5.16 BSDL Description for the 32172(5/11) "FVCC_73 :73," & "P61 :74," & "P62 :75," & "P63 :76," & "P64 :77," & "P70 :78," & "P71 :79," & "P72 :80," & "P73 :81," & "P74 :82," & "P75 :83," & "P76 :84," & "P77 :85," & "P93 :86," & "P94 :87," & "P95 :88," & "P96 :89," & "P97 :90," & "RESET :91," & "MOD0 :92," & "MOD1 :93," & "FP :94," & "VCCE_95 :95," & "VSS_96 :96," & "P110 :97," & "P111 :98," & "P112 :99," & "P113 :100," & "P114 :101," & "P115 :102," & "P116 :103," & "P117 :104," & "P100 :105," & "P101 :106," & "P102 :107," & "VDD_108 :108," & "TMS :109," & "TCK :110," & "TRST :111," & "TDO :112," & "TDI :113," & "P103 :114," & "P104 :115," & "P105 :116," & "P106 :117," & "P107 :118," & "P124 :119," & "P125 :120," & "P126 :121," & "P127 :122," & "VCCI_123 :123," & "P130 :124," & "P131 :125," & "P132 :126," & "P133 :127," & "P134 :128," & "P135 :129," & "P136 :130," & "P137 :131," & "VCCE_132 :132," &

21-31 Rev.1.0 JTAG Figure 21.5.17 BSDL Description for the 32172(6/11) "P150 :133," & "P153 :134," & "P41 :135," & "P42 :136," & "VCCI_137 :137," & "VSS_138 :138," & "P43 :139," & "P44 :140," & "P45 :141," & "P46 :142," & "P47 :143," & "P220 :144" ; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (5.0e6, BOTH); attribute TAP_SCAN_RESET of TRST : signal is true; attribute INSTRUCTION_LENGTH of M32172F2VFP : entity is 6; attribute INSTRUCTION_OPCODE of M32172F2VFP : entity is "BYPASS (111111)," & "SAMPLE (000001)," & "EXTEST (000000)," & "IDCODE (000010)," & "USERCODE (000011)," & "MDM_SYSTEM (001000)," & "MDM_CONTROL (001001)," & "MDM_SETUP (001010)," & "MTM_CONTROL (001111)," & "MON_CODE (010000)," & "MON_DATA (010001)," & "MON_PARAM (010010)," & "MON_ACCESS (010011)," & "DMA_RADDR (011000)," & "DMA_RDATA (011001)," & "DMA_RTYPE (011010)," & "DMA_ACCESS (011011)," & "RTDENB (100000)" ; attribute INSTRUCTION_CAPTURE of M32172F2VFP : entity is "110001"; attribute INSTRUCTION_PRIVATE of M32172F2VFP : entity is "MDM_SYSTEM," & "MDM_CONTROL," & "MDM_SETUP," & "MTM_CONTROL," & "MON_CODE," & "MON_DATA," & "MON_PARAM," & "MON_ACCESS," & "DMA_RADDR," & "DMA_RDATA," & "DMA_RTYPE," & "DMA_ACCESS," & "RTDENB" ;

21-32 Rev.1.0 JTAG attribute IDCODE_REGISTER of M32172F2VFP : entity is "0000" & -- version "0011001000100001" & -- part number "00000011100" & -- manufacturer's identity "1"; -- required by 1149.1 --- attribute USERCODE_REGISTER of M32172F2VFP : entity is --- "0000 0000 0000 0000" & -- reserved --- "0000" & -- reserved --- "0001"; -- SDI version attribute REGISTER_ACCESS of M32172F2VFP : entity is "Bypass (BYPASS)," & "Boundary (SAMPLE, EXTEST)," & "Device_ID (IDCODE)," & "USERCODE_REG[32] (USERCODE)," & "MDM_SYSTEM_REG[17] (MDM_SYSTEM)," & "MDM_CONTROL_REG[20] (MDM_CONTROL)," & "MDM_SETUP_REG[2] (MDM_SETUP)," & "MTM_CONTROL_REG[4] (MTM_CONTROL)," & "MON_CODE_REG[32] (MON_CODE)," & "MON_DATA_REG[32] (MON_DATA)," & "MON_PARAM_REG[32] (MON_PARAM)," & "MON_ACCESS_REG[4] (MON_ACCESS)," & "DMA_RADDR_REG[32] (DMA_RADDR)," & "DMA_RDATA_REG[32] (DMA_RDATA)," & "DMA_RTYPE_REG[3] (DMA_RTYPE)," & "DMA_ACCESS_REG[3] (DMA_ACCESS)," & "RTDENB_REG[1] (RTDENB)"; attribute BOUNDARY_LENGTH of M32172F2VFP : entity is 265; attribute BOUNDARY_REGISTER of M32172F2VFP : entity is -- num cell port function safe [ccell disval rslt] "264 (BC_4, P103, observe_only, X)," & "263 (BC_1, P103, output3, X, 262, 0, Z)," & "262 (BC_1, *, control, 0)," & "261 (BC_4, P104, observe_only, X)," & "260 (BC_1, P104, output3, X, 259, 0, Z)," & "259 (BC_1, *, control, 0)," & "258 (BC_4, P105, observe_only, X)," & "257 (BC_1, P105, output3, X, 256, 0, Z)," & "256 (BC_1, *, control, 0)," & "255 (BC_4, P106, observe_only, X)," & "254 (BC_1, P106, output3, X, 253, 0, Z)," & "253 (BC_1, *, control, 0)," & "252 (BC_4, P107, observe_only, X)," & "251 (BC_1, P107, output3, X, 250, 0, Z)," & "250 (BC_1, *, control, 0)," & "249 (BC_4, P124, observe_only, X)," & "248 (BC_4, P125, observe_only, X)," & "247 (BC_4, P126, observe_only, X)," & "246 (BC_4, P127, observe_only, X)," & "245 (BC_4, P130, observe_only, X)," & "244 (BC_4, P131, observe_only, X)," & "243 (BC_4, P132, observe_only, X)," & Figure 21.5.18 BSDL Description for the 32172(7/11)

21-33 Rev.1.0 JTAG "242 (BC_4, P133, observe_only, X)," & "241 (BC_4, P134, observe_only, X)," & "240 (BC_4, P135, observe_only, X)," & "239 (BC_4, P136, observe_only, X)," & "238 (BC_4, P137, observe_only, X)," & "237 (BC_4, P150, observe_only, X)," & "236 (BC_1, P150, output3, X, 235, 0, Z)," & "235 (BC_1, *, control, 0)," & "234 (BC_4, P153, observe_only, X)," & "233 (BC_1, P153, output3, X, 232, 0, Z)," & "232 (BC_1, *, control, 0)," & "231 (BC_4, P41, observe_only, X)," & "230 (BC_1, P41, output3, X, 229, 0, Z)," & "229 (BC_1, *, control, 0)," & "228 (BC_4, P42, observe_only, X)," & "227 (BC_1, P42, output3, X, 226, 0, Z)," & "226 (BC_1, *, control, 0)," & "225 (BC_4, P43, observe_only, X)," & "224 (BC_1, P43, output3, X, 223, 0, Z)," & "223 (BC_1, *, control, 0)," & "222 (BC_4, P44, observe_only, X)," & "221 (BC_1, P44, output3, X, 220, 0, Z)," & "220 (BC_1, *, control, 0)," & "219 (BC_4, P45, observe_only, X)," & "218 (BC_1, P45, output3, X, 217, 0, Z)," & "217 (BC_1, *, control, 0)," & "216 (BC_4, P46, observe_only, X)," & "215 (BC_1, P46, output3, X, 214, 0, Z)," & "214 (BC_1, *, control, 0)," & "213 (BC_4, P47, observe_only, X)," & "212 (BC_1, P47, output3, X, 211, 0, Z)," & "211 (BC_1, *, control, 0)," & "210 (BC_4, P220, observe_only, X)," & "209 (BC_1, P220, output3, X, 208, 0, Z)," & "208 (BC_1, *, control, 0)," & "207 (BC_4, P221, observe_only, X)," & "206 (BC_4, P225, observe_only, X)," & "205 (BC_1, P225, output3, X, 204, 0, Z)," & "204 (BC_1, *, control, 0)," & "203 (BC_4, P30, observe_only, X)," & "202 (BC_1, P30, output3, X, 201, 0, Z)," & "201 (BC_1, *, control, 0)," & "200 (BC_4, P31, observe_only, X)," & "199 (BC_1, P31, output3, X, 198, 0, Z)," & "198 (BC_1, *, control, 0)," & "197 (BC_4, P32, observe_only, X)," & "196 (BC_1, P32, output3, X, 195, 0, Z)," & "195 (BC_1, *, control, 0)," & "194 (BC_4, P33, observe_only, X)," & "193 (BC_1, P33, output3, X, 192, 0, Z)," & "192 (BC_1, *, control, 0)," & "191 (BC_4, P34, observe_only, X)," & "190 (BC_1, P34, output3, X, 189, 0, Z)," & "189 (BC_1, *, control, 0)," & "188 (BC_4, P35, observe_only, X)," & "187 (BC_1, P35, output3, X, 186, 0, Z)," & "186 (BC_1, *, control, 0)," & "185 (BC_4, P36, observe_only, X)," & "184 (BC_1, P36, output3, X, 183, 0, Z)," & "183 (BC_1, *, control, 0)," & Figure 21.5.19 BSDL Description for the 32172(8/11)

21-34 Rev.1.0 JTAG "182 (BC_4, P37, observe_only, X)," & "181 (BC_1, P37, output3, X, 180, 0, Z)," & "180 (BC_1, *, control, 0)," & "179 (BC_4, P20, observe_only, X)," & "178 (BC_1, P20, output3, X, 177, 0, Z)," & "177 (BC_1, *, control, 0)," & "176 (BC_4, P21, observe_only, X)," & "175 (BC_1, P21, output3, X, 174, 0, Z)," & "174 (BC_1, *, control, 0)," & "173 (BC_4, P22, observe_only, X)," & "172 (BC_1, P22, output3, X, 171, 0, Z)," & "171 (BC_1, *, control, 0)," & "170 (BC_4, P23, observe_only, X)," & "169 (BC_1, P23, output3, X, 168, 0, Z)," & "168 (BC_1, *, control, 0)," & "167 (BC_4, P24, observe_only, X)," & "166 (BC_1, P24, output3, X, 165, 0, Z)," & "165 (BC_1, *, control, 0)," & "164 (BC_4, P25, observe_only, X)," & "163 (BC_1, P25, output3, X, 162, 0, Z)," & "162 (BC_1, *, control, 0)," & "161 (BC_4, P26, observe_only, X)," & "160 (BC_1, P26, output3, X, 159, 0, Z)," & "159 (BC_1, *, control, 0)," & "158 (BC_4, P27, observe_only, X)," & "157 (BC_1, P27, output3, X, 156, 0, Z)," & "156 (BC_1, *, control, 0)," & "155 (BC_4, P00, observe_only, X)," & "154 (BC_1, P00, output3, X, 153, 0, Z)," & "153 (BC_1, *, control, 0)," & "152 (BC_4, P01, observe_only, X)," & "151 (BC_1, P01, output3, X, 150, 0, Z)," & "150 (BC_1, *, control, 0)," & "149 (BC_4, P02, observe_only, X)," & "148 (BC_1, P02, output3, X, 147, 0, Z)," & "147 (BC_1, *, control, 0)," & "146 (BC_4, P03, observe_only, X)," & "145 (BC_1, P03, output3, X, 144, 0, Z)," & "144 (BC_1, *, control, 0)," & "143 (BC_4, P04, observe_only, X)," & "142 (BC_1, P04, output3, X, 141, 0, Z)," & "141 (BC_1, *, control, 0)," & "140 (BC_4, P05, observe_only, X)," & "139 (BC_1, P05, output3, X, 138, 0, Z)," & "138 (BC_1, *, control, 0)," & "137 (BC_4, P06, observe_only, X)," & "136 (BC_1, P06, output3, X, 135, 0, Z)," & "135 (BC_1, *, control, 0)," & "134 (BC_4, P07, observe_only, X)," & "133 (BC_1, P07, output3, X, 132, 0, Z)," & "132 (BC_1, *, control, 0)," & "131 (BC_4, P10, observe_only, X)," & "130 (BC_1, P10, output3, X, 129, 0, Z)," & "129 (BC_1, *, control, 0)," & "128 (BC_4, P11, observe_only, X)," & "127 (BC_1, P11, output3, X, 126, 0, Z)," & "126 (BC_1, *, control, 0)," & "125 (BC_4, P12, observe_only, X)," & "124 (BC_1, P12, output3, X, 123, 0, Z)," & "123 (BC_1, *, control, 0)," & Figure 21.5.20 BSDL Description for the 32172(9/11)

21-35 Rev.1.0 JTAG "122 (BC_4, P13, observe_only, X)," & "121 (BC_1, P13, output3, X, 120, 0, Z)," & "120 (BC_1, *, control, 0)," & "119 (BC_4, P14, observe_only, X)," & "118 (BC_1, P14, output3, X, 117, 0, Z)," & "117 (BC_1, *, control, 0)," & "116 (BC_4, P15, observe_only, X)," & "115 (BC_1, P15, output3, X, 114, 0, Z)," & "114 (BC_1, *, control, 0)," & "113 (BC_4, P16, observe_only, X)," & "112 (BC_1, P16, output3, X, 111, 0, Z)," & "111 (BC_1, *, control, 0)," & "110 (BC_4, P17, observe_only, X)," & "109 (BC_1, P17, output3, X, 108, 0, Z)," & "108 (BC_1, *, control, 0)," & "107 (BC_4, P172, observe_only, X)," & "106 (BC_4, P173, observe_only, X)," & "105 (BC_4, P174, observe_only, X)," & "104 (BC_1, P174, output3, X, 103, 0, Z)," & "103 (BC_1, *, control, 0)," & "102 (BC_4, P175, observe_only, X)," & "101 (BC_1, P175, output3, X, 100, 0, Z)," & "100 (BC_1, *, control, 0)," & "99 (BC_4, P82, observe_only, X)," & "98 (BC_1, P82, output3, X, 97, 0, Z)," & "97 (BC_1, *, control, 0)," & "96 (BC_4, P83, observe_only, X)," & "95 (BC_1, P83, output3, X, 94, 0, Z)," & "94 (BC_1, *, control, 0)," & "93 (BC_4, P84, observe_only, X)," & "92 (BC_1, P84, output3, X, 91, 0, Z)," & "91 (BC_1, *, control, 0)," & "90 (BC_4, P85, observe_only, X)," & "89 (BC_1, P85, output3, X, 88, 0, Z)," & "88 (BC_1, *, control, 0)," & "87 (BC_4, P86, observe_only, X)," & "86 (BC_1, P86, output3, X, 85, 0, Z)," & "85 (BC_1, *, control, 0)," & "84 (BC_4, P87, observe_only, X)," & "83 (BC_1, P87, output3, X, 82, 0, Z)," & "82 (BC_1, *, control, 0)," & "81 (BC_4, P61, observe_only, X)," & "80 (BC_1, P61, output3, X, 79, 0, Z)," & "79 (BC_1, *, control, 0)," & "78 (BC_4, P62, observe_only, X)," & "77 (BC_1, P62, output3, X, 76, 0, Z)," & "76 (BC_1, *, control, 0)," & "75 (BC_4, P63, observe_only, X)," & "74 (BC_1, P63, output3, X, 73, 0, Z)," & "73 (BC_1, *, control, 0)," & "72 (BC_4, P64, observe_only, X)," & "71 (BC_4, P70, observe_only, X)," & "70 (BC_1, P70, output3, X, 69, 0, Z)," & "69 (BC_1, *, control, 0)," & "68 (BC_4, P71, observe_only, X)," & "67 (BC_1, P71, output3, X, 66, 0, Z)," & "66 (BC_1, *, control, 0)," & "65 (BC_4, P72, observe_only, X)," & "64 (BC_1, P72, output3, X, 63, 0, Z)," & "63 (BC_1, *, control, 0)," & Figure 21.5.21 BSDL Description for the 32172(10/11)

21-36 Rev.1.0 JTAG "62 (BC_4, P73, observe_only, X)," & "61 (BC_1, P73, output3, X, 60, 0, Z)," & "60 (BC_1, *, control, 0)," & "59 (BC_4, P74, observe_only, X)," & "58 (BC_1, P74, output3, X, 57, 0, Z)," & "57 (BC_1, *, control, 0)," & "56 (BC_4, P75, observe_only, X)," & "55 (BC_1, P75, output3, X, 54, 0, Z)," & "54 (BC_1, *, control, 0)," & "53 (BC_4, P76, observe_only, X)," & "52 (BC_1, P76, output3, X, 51, 0, Z)," & "51 (BC_1, *, control, 0)," & "50 (BC_4, P77, observe_only, X)," & "49 (BC_1, P77, output3, X, 48, 0, Z)," & "48 (BC_1, *, control, 0)," & "47 (BC_4, P93, observe_only, X)," & "46 (BC_4, P94, observe_only, X)," & "45 (BC_1, P94, output3, X, 44, 0, Z)," & "44 (BC_1, *, control, 0)," & "43 (BC_4, P95, observe_only, X)," & "42 (BC_1, P95, output3, X, 41, 0, Z)," & "41 (BC_1, *, control, 0)," & "40 (BC_4, P96, observe_only, X)," & "39 (BC_1, P96, output3, X, 38, 0, Z)," & "38 (BC_1, *, control, 0)," & "37 (BC_4, P97, observe_only, X)," & "36 (BC_4, RESET, observe_only, X)," & "35 (BC_4, MOD0, observe_only, X)," & "34 (BC_4, MOD1, observe_only, X)," & "33 (BC_4, FP, observe_only, X)," & "32 (BC_4, P110, observe_only, X)," & "31 (BC_1, P110, output3, X, 30, 0, Z)," & "30 (BC_1, *, control, 0)," & "29 (BC_4, P111, observe_only, X)," & "28 (BC_1, P111, output3, X, 27, 0, Z)," & "27 (BC_1, *, control, 0)," & "26 (BC_4, P112, observe_only, X)," & "25 (BC_1, P112, output3, X, 24, 0, Z)," & "24 (BC_1, *, control, 0)," & "23 (BC_4, P113, observe_only, X)," & "22 (BC_1, P113, output3, X, 21, 0, Z)," & "21 (BC_1, *, control, 0)," & "20 (BC_4, P114, observe_only, X)," & "19 (BC_1, P114, output3, X, 18, 0, Z)," & "18 (BC_1, *, control, 0)," & "17 (BC_4, P115, observe_only, X)," & "16 (BC_1, P115, output3, X, 15, 0, Z)," & "15 (BC_1, *, control, 0)," & "14 (BC_4, P116, observe_only, X)," & "13 (BC_1, P116, output3, X, 12, 0, Z)," & "12 (BC_1, *, control, 0)," & "11 (BC_4, P117, observe_only, X)," & "10 (BC_1, P117, output3, X, 9, 0, Z)," & "9 (BC_1, *, control, 0)," & "8 (BC_4, P100, observe_only, X)," & "7 (BC_1, P100, output3, X, 6, 0, Z)," & "6 (BC_1, *, control, 0)," & "5 (BC_4, P101, observe_only, X)," & "4 (BC_1, P101, output3, X, 3, 0, Z)," & "3 (BC_1, *, control, 0)," & "2 (BC_4, P102, observe_only, X)," & "1 (BC_1, P102, output3, X, 0, 0, Z)," & "0 (BC_1, *, control, 0)"; end M32172F2VFP; Figure 21.5.22 BSDL Description for the 32172(11/11)

21-37 Rev.1.0

21.6 Precautions on Board Design when Connecting the JTAG

The JTAG pins must have their wiring lengths matched during board design. This is necessary to accomplish fast, highly reliable communication with the JTAG tool. Figure 21.6.1 Precautions on Connecting the User Board and JTAG JTAG Make sure the wiring lengths are the same and avoid bending wirings as much as possible. Also, do not use through holes within wirings. JTDO 33Ω 33Ω VCCE(5V) 33Ω 33Ω 33Ω 2KΩ 10KΩ 10KΩ 10KΩ 10KΩ 0.1µF SDI connector (JTAG connector) Power TDI TMS TCK TRST TDO GND

21-38 Rev.1.0 M32R/E JTDI JTMS JTCK JTRST User board When connecting the JTAG tool Make sure the wiring lengths are the same and avoid bending wirings as much as possible. Also, do not use through holes within wirings. JTDO 33Ω 33Ω VCCE(5V) 33Ω 33Ω 33Ω 33Ω 2KΩ 10KΩ 10KΩ 10KΩ 10KΩ DBI 10KΩ 33Ω TRCLK 33Ω TRSYNC 33Ω TRDATA[0:7] 33Ω EVENT[0:1] 0.1µF SDI connector (JTAG connector) Power TDI TMS TCK TRST TDO DBI TRCLK TRSYNC GND When connecting the emulator TRDATA[0:7] EVENT[0:1] Figure 21.6.2 Precautions on Connecting the User Board and JTAG (for the 255FBGA) JTAG

21-39 Rev.1.0

21.7 Processing Pins when Not Using the JTAG

When not using the JTAG, make sure the pins on the microcomputer are processed properly, as shown below. Figure 21.7.1 Processing Pins when Not Using the JTAG (for the 144LGFP) JTAG VCCE(5V) 0 to 100K‰ 0 to 100K‰ 0 to 10K‰ 0 to 10K‰ 0 to 10K‰

21-40 Rev.1.0 Figure 21.7.2 Processing Pins when Not Using the JTAG (for the 175FBGA) JTAG VCCE(5V) 0 to 100K‰ 0 to 100K‰ DBI TRCLK TRSYNC TRDATA[0:7] EVENT[0:1] 0 to 100K‰ 0 to 100K‰ 0 to 100K‰ 0 to 100K‰ ( OPEN ) ( OPEN ) ( OPEN ) ( OPEN )

22.1 Configuration of the Power

22.2 Power-On Sequence

22.3 Power-Shutdown Sequence

22-2 Rev.1.0 POWER-UP/POWER-SHUTDOWN SEQUENCE

22.1 Configuration of the Power Supply Circuit

To materialize high-speed operation at low power, the M32R/E is designed in such a way that its external interface circuits operate at 5 V power supply and all other circuits operate at 3.3 V. This requires that control timing of both 5 V and 3.3 V power supplies be considered when designing your circuit. Table 22.1.1 List of Power Supply Functions Type of Power Supply Pin Name Function

5.0 V system VCCE Supplies power to external I/O ports

AVCC0 Power supply for A-D converter VREF0 Reference voltage for A-D converter

3.3 V system VCCI Supplies power to internal logic

FVCC Power supply for internal flash memory VDD Power supply for internal RAM backup OSC-VCC Power supply for oscillator and PLL circuits OSC-VCC FVCC VDD VCCI AVCC VCCE M32R/E

5 V power supply

3.3 V power supply

Oscillator and PLL circuits Figure 22.1.1 Configuration of the Power Supply Circuit

22-3 Rev.1.0

22.2.1 Power-On Sequence When Not Using RAM Backup

The diagram below shows a power-on sequence (5.0 V, 3.3 V power supply) of the M32R/E when not using RAM backup. POWER-UP/POWER-SHUTDOWN SEQUENCE ➀ : Turn on the 3.3 V power supply after turning on the 5 V power supply. ➁ : After turning on all power supplies and holding the RESET pin low for an oscillation stabilization time, release the RESET pin input back high (to deactivate reset). Note: Power-on limitations

• VDD OSC-VCC VCCI FVCC
• VCCE VCCI, FVCC, OSC-VCC VCCE AVCC0 VREF0 RESET VDD VCCI FVCC OSC-VCC 3.3V 3.3V 3.3V 3.3V Figure 22.2.1 Power-On Sequence When Not Using RAM Backup

22-4 Rev.1.0

22.2.2 Power-On Sequence When Using RAM Backup

The diagram below shows a power-on sequence (5.0 V, 3.3 V power supply) of the M32R/E when using RAM backup. POWER-UP/POWER-SHUTDOWN SEQUENCE ➀ : Turn on the 3.3 V power supply after turning on the 5 V power supply. ➁ : After turning on all power supplies and holding the RESET pin low for an oscillation stabilization time, release the RESET pin input back high (to deactivate reset). Note: Power-on limitations

• VDD OSC-VCC VCCI FVCC
• VCCE VCCI, FVCC, OSC-VCC VCCE AVCC0 VREF0 RESET VDD VCCI FVCC OSC-VCC 3.3V 3.3V 3.3V 3.3V 2.0V Figure 22.2.2 Power-On Sequence When Using RAM Backup

22-5 Rev.1.0

22.3.1 Power-Shutdown Sequence When Not Using RAM Backup

The diagram below shows a power-shutdown sequence (5.0 V, 3.3 V power supply) of the M32R/ E when not using RAM backup. POWER-UP/POWER-SHUTDOWN SEQUENCE Figure 22.3.1 Power-Shutdown Sequence When Not Using RAM Backup ➀ : Pull the RESET pin input low. ➁ : Turn off the 5 V and the 3 V power supply after the RESET pin goes low. Note: Power-shutdown requirements

• VDD VCCI FVCC
• OSC-VCC VCCI VCCE AVCC0 VREF0 RESET VDD VCCI FVCC OSC-VCC 3.3V 3.3V 3.3V 3.3V

22-6 Rev.1.0

22.3.2 Power-Shutdown Sequence When Using RAM Backup

The diagram below shows a power-shutdown sequence (5.0 V, 3.3 V power supply) of the M32R/ E when using RAM backup. POWER-UP/POWER-SHUTDOWN SEQUENCE 3.3V 3.3V 3.3V 3.3V 2.0V ➀ : Pull the HREQ pin input low to halt the CPU at end of bus cycle. Or disable RAM access in software. The M32R/E allows P72 to be used as HREQ irrespective of its operation mode. ➁ : With the CPU halted, pull the RESET pin input low. Or while RAM access is disabled, pull the RESET pin input low. ➂ : Turn off the 5 V and the 3.3 V power supply after the RESET pin goes low. { : Reduce the VDD voltage from 3.3 V to 2.0 V as necessary. Note: Power-shutdown requirements

• VDD VCCI FVCC
• OSC-VCC VCCI Figure 22.3.2 Power-Shutdown Sequence When Using RAM Backup

22-7 Rev.1.0 POWER-UP/POWER-SHUTDOWN SEQUENCE 3.3V power supply I/O control circuit A-D converter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 3.3V OSC-VCC FVCC VDD VCCI AVCC0 VCCE M32R/E I/O control circuit A-D converter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 3.3V 5V power supply 3.3V power supply Figure 22.3.3 Microcomputer Ready to Run State (VCCE = 5 V, VCCI system = 3.3 V, VDD = 3.3 V) Figure 22.3.4 CPU Reset State

22-8 Rev.1.0 POWER-UP/POWER-SHUTDOWN SEQUENCE Oscillator and PLL circuits 5V power supply 3.3V power supply OSC-VCC FVCC VDD VCCI AVCC0 VCCE M32R/E 3.3V-2.0V I/O control circuit A-D converter circuit CPU Peripheral circuits Flash RAM Oscillator and PLL circuits 5V power supply 3.3V power supply Figure 22.3.5 CPU Halt State Figure 22.3.6 SRAM Data Backup State

23.1 Absolute Maximum Ratings

23.2 Recommended Operating

23.3 DC Characteristics

23.4 A-D Conversion Characteristics

23.5 D-A Conversion Characteristics

23.6 AC Characteristics

23-2 Rev.1.0 Absolute Maximum Ratings (-40 to 125°C)

ELECTRICAL CHARACTERISTICS

Symbol Parameter Condition Rated Value Unit VCCI V VDD RAM Power Supply Voltage V AVCC Analog Power Supply Voltage VOSC-VCC PLL Power Supply Voltage V VREF Analog Reference Voltage V FVCC Flash Power Supply Voltage V VI Xin, VCNT VO Pd Power Dissipation mW TOPR Operating Ambient Temperature (Note) oC Tstg Storage Temperature oC V Internal Logic Power Supply Voltage VDD VCCI FVCC=OSC-VCC VDD VCCI FVCC=OSC-VCC -0.3 — 4.2 -0.3 — 4.2 VDD VCCI FVCC=OSC-VCC VDD VCCI FVCC=OSC-VCC -0.3 — 4.2 -0.3 — 4.2 VCCE External I/O Buffer VoltageVCCE AVCC VREF Xout -0.3 — 6.5 -0.3 — 6.5 -0.3 — 6.5 -40 — 125 -65 — 150 -0.3 — OSC-VCC+0.3 -0.3 — VCCE+0.3 -0.3 — OSC-VCC+0.3 500 -0.3 — VCCE+0.3 V V Other Other VCCE AVCC VREF VCCE AVCC VREF Ta=-40 — 85oC Ta=-40 — 125oC mW600 Note: This does not guarantee that the device will operate continuously at 125°C. If yourapplication system is intended to operate at 125°C, please consult Mitsubishi.

23-3 Rev.1.0

23.2 Recommended Operating Conditions

Recommended Operating Conditions (Referenced to VCCE = 5 V±0.5 V, VCCI = 3.3 V±0.3 V, Ta = -40 to 85°C unless otherwise specified) Symbol Parameter Rated Value Unit VCCE External I/O Buffer Voltage (Note 1) V VDD RAM Power Supply Voltage (Note 2) AVCC Analog Power Supply Voltage (Note 1) VREF Analog Reference Voltage (Note 1) VIH High Level Input Voltage MIN TYP MAX VIL Low Level Input Voltage IOH(peak) IOH(avg) IOL(peak) IOL(avg) mA mA mA mA MHzf(XIN) FVCC Flash Power Supply Voltage (Note 2) PLL Power Supply Voltage (Note 2)OSC-VCC VCCI Internal Logic Power Supply Voltage (Note 2) 4.5 5.0 5.5 3.0 3.3 3.6 Ports P0, P1 (in only external extended/processor modes), WAIT 0.8VCCE 0.43VCCE VCCE 0.2VCCE0 0 0.16VCCE High Level Mean Output Current P0-P11, P14-P22 (Note 4) Low Level Peak Output Current P0-P11, P14-P22 (Note 3) Low Level Mean Output Current P0-P11, P14-P22 (Note 4) External Clock Input Frequency 5 -10 V V V V V V V V V V Ports P0-P22, RESET, MOD0, MOD1, FP Ports P0, P1 (in only external extended/processor modes), WAIT Ports P0-P22, RESET, MOD0, MOD1, FP 3.0 3.0 4.5 3.0 High Level Peak Output Current P0-P11, P14-P22 (Note 3) CL Output Load Capacitance

80 PFJTCK,JTDI,JTMS,

JTDO,JTRST Other than above 50 PF 3.3 3.3 5.0 3.3 3.6 3.6 5.5 3.6 5.0 5.5 VCCE Note 1: Tested under conditions VCCE AVCC VREF Note 2: Tested under conditions VDD VCCI FVCC OSC-VCC Note 3: Make sure the total output current of ports (peak) meet the conditions below. | Ports P0+P1+P2 | 80 mA | Ports P3+P4+P15+P22 | 80 mA | Ports P6+P7+P8+P9+P17 | 80 mA | Ports P10+P11 | 80 mA Note 4: The mean output current refers to the average current on ports within a 100-ms period.

23-4 Rev.1.0 Recommended Operating Conditions (Referenced to VCCE = 5 V±0.5 V, VCCI = 3.3 V±0.3 V, Ta = -40 to 125°C unless otherwise specified) Symbol Parameter Rated Value Unit VCCE External I/O Buffer Voltage (Note 1) V VDD RAM Power Supply Voltage (Note 2) AVCC Analog Power Supply Voltage (Note 1) VREF Analog Reference Voltage (Note 1) VIH High Level Input Voltage MIN TYP MAX VIL Low Level Input Voltage IOH(peak) IOH(avg) IOL(peak) IOL(avg) mA mA mA mA MHzf(XIN) FVCC Flash Power Supply Voltage (Note 2) PLL Power Supply Voltage (Note 2)OSC-VCC VCCI Internal Logic Power Supply Voltage (Note 2) 4.5 5.0 5.5 3.0 3.3 3.6 Ports P0, P1 (in only external extended/processor modes), WAIT 0.8VCCE VCCE 0.43VCCE VCCE 0.2VCCE0 0 0.16VCCE High Level Peak Output Current P0-P11, P14-P22 (Note 3) High Level Mean Output Current P0-P11, P14-P22 (Note 4) Low Level Peak Output Current P0-P11, P14-P22 (Note 3) Low Level Mean Output Current P0-P11, P14-P22 (Note 4) External Clock Input Frequency 5 V V V V V V V V V V Ports P0-P22, RESET, MOD0, MOD1, FP Ports P0, P1 (in only external extended/processor modes), WAIT Ports P0-P22, RESET, MOD0, MOD1, FP -10 CL Output Load Capacitance JTDO,JTRST Other than above 50 PF 3.0 3.0 4.5 3.0 3.3 3.3 3.3 5.0 5.0 3.6 3.6 3.6 5.5 5.5 Note 1: Tested under conditions VCCE AVCC VREF Note 2: Tested under conditions VDD VCCI FVCC OSC-VCC Note 3: Make sure the total output current of ports (peak) meet the conditions below. | Ports P0+P1+P2 | 80 mA | Ports P3+P4+P15+P22 | 80 mA | Ports P6+P7+P8+P9+P17 | 80 mA | Ports P10+P11 | 80 mA Note 4: The mean output current refers to the average current on ports within a 100-ms period.

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