30N6S2

FGH30N6S2_01 FAIRCHILD | Alldatasheet

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 100kHz Operation at 390V , 14A  200kHZ Operation at 390V , 9A  600V Switching SOA Capability oC  Low Conduction Loss Device Maximum Ratings TC = 25°C unless otherwise noted Symbol Parameter Ratings Units BV CES Collector to Emitter Breakdown Voltage 600 V IC25 Collector Current Continuous, TC = 25°C 45 A IC110 Collector Current Continuous, TC = 110°C 20 A ICM Collector Current Pulsed (Note 1) 108 A VGES Gate to Emitter Voltage Continuous ±20 V VGEM Gate to Emitter Voltage Pulsed ±30 V SSOA Switching Safe Operating Area at TJ = 150°C, Figure 2 60A at 600V EAS Pulsed Avalanche Energy, ICE = 20A, L = 1.3mH, VDD = 50V 150 mJ PD Power Dissipation Total TC = 25°C 167 W Power Dissipation Derating TC > 25°C 1.33 W/°C TJ Operating Junction Temperature Range -55 to 150 °C TSTG Storage Junction Temperature Range -55 to 150 °C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. Pulse width limited by maximum junction temperature. Package JEDEC STYLE TO-247 Symbol G CE C E G JEDEC STYLE TO-220AB GCE JEDEC STYLE TO-263AB G C E

©2001 Fairchild Semiconductor Corporation FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Package Marking and Ordering Information Electrical Characteristics TJ = 25°C unless otherwise noted Off State Characteristics On State Characteristics Dynamic Characteristics Switching Characteristics Thermal Characteristics Device Marking Device Package Tape Width Quantity 30N6S2 FGH30N6S2 TO-247 - - 30N6S2 FGP30N6S2 TO-220AB - - 30N6S2 FGB30N6S2 TO-263AB 24mm 800 Symbol Parameter Test Conditions Min Typ Max Units BV CES Collector to Emitter Breakdown Voltage IC = 250µA, VGE = 0 600 - - V BV ECS Emitter to Collector Breakdown Voltage IC = 10mA, VGE = 0 10 25 - V ICES Collector to Emitter Leakage Current VCE = 600V T J = 25°C - - 100 µA TJ = 125°C - - 2 mA IGES Gate to Emitter Leakage Current V GE = ± 20V - - ±250 nA VCE(SAT) Collector to Emitter Saturation Voltage IC = 12A, VGE = 15V TJ = 25°C - 2.0 2.5 V TJ = 125°C - 1.7 2.0 V Q G(ON) Gate Charge I C = 12A, VCE = 300V VGE = 15V - 23 29 nC VGE = 20V - 26 33 nC VGE(TH) Gate to Emitter Threshold Voltage IC = 250µA, VCE = 600V 3.5 4.3 5.0 V VGEP Gate to Emitter Plateau Voltage I C = 12A, VCE = 300V - 6.5 8.0 V SSOA Switching SOA T J = 150°C, RG = 10Ω, VGE = 15V, L = 100µH, VCE = 600V 60 - - A td(ON)I Current Turn-On Delay Time IGBT and Diode at T J = 25°C, ICE = 12A, VCE = 390V, VGE = 15V, R G = 10Ω L = 200µH Test Circuit - Figure 20 -6- n s trI Current Rise Time - 10 - ns td(OFF)I Current Turn-Off Delay Time - 40 - ns tfI Current Fall Time - 53 - ns EON1 Turn-On Energy (Note 2) - 55 - µJ EON2 Turn-On Energy (Note 2) - 110 - µJ EOFF Turn-Off Energy (Note 3) - 100 150 µJ td(ON)I Current Turn-On Delay Time IGBT and Diode at T J = 125°C ICE = 12A, VCE = 390V, VGE = 15V, R G = 10Ω L = 200µH Test Circuit - Figure 20 -1 1-n s trI Current Rise Time - 17 - ns td(OFF)I Current Turn-Off Delay Time - 73 100 ns tfI Current Fall Time - 90 100 ns EON1 Turn-On Energy (Note 2) - 55 - µJ EON2 Turn-On Energy (Note 2) - 160 200 µJ EOFF Turn-Off Energy (Note 3) - 250 350 µJ R θJC Thermal Resistance Junction-Case - - 0.75 °C/W NOTE: 2. Values for two Turn-On loss conditions are shown for the convenience of the circuit designer. EON1 is the turn-on loss of the IGBT only. EON2 is the turn-on loss when a typical diode is used in the test circuit and the diode is at the same TJas the IGBT. The diode type is specified in figure 20. 3. Turn-Off Energy Loss (EOFF ) is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the point where the collector current equals zero (ICE = 0A). All devices were tested per JEDEC Standard No. 24-1 Method for Measurement of Power Device Turn-Off Switching Loss. This test method produc- es the true total Turn-Off Energy Loss.

Figure 13. Transfer Characteristic Figure 14. Gate Charge Figure 15. Total Switching Loss vs Case Figure 16. Total Switching Loss vs Gate Figure 17. Capacitance vs Collector to Emitter Figure 18. Collector to Emitter On-State Voltage vs

1.0 ICE = 24A

©2001 Fairchild Semiconductor Corporation FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Handling Precautions for IGBTs Insulated Gate Bipolar Transistors are susceptible to gate-insulation damage by the electrostatic discharge of energy through the devices. When handling these devices, care should be exercised to assure that the static charge built in the handler’s body capacitance is not discharged through the device. With proper handling and application procedures, however, IGBTs are currently being extensively used in production by numerous equipment manufacturers in military, industrial and consumer applications, with virtually no damage problems due to electrostatic discharge. IGBTs can be handled safely if the following basic precautions are taken: 1. Prior to assembly into a circuit, all leads should be kept shorted together either by the use of metal shorting springs or by the insertion into conduc- tive material such as “ECCOSORBD ™ LD26” or equivalent. 2. When devices are removed by hand from their carriers, the hand being used should be grounded by any suitable means - for example, with a metallic wristband. 3. Tips of soldering irons should be grounded. 4. Devices should never be inserted into or removed from circuits with power on. 5. Gate Voltage Rating - Never exceed the gate- voltage rating of V GEM . Exceeding the rated VGE can result in permanent damage to the oxide layer in the gate region. 6. Gate Termination - The gates of these devices are essentially capacitors. Circuits that leave the gate open-circuited or floating should be avoided. These conditions can result in turn-on of the device due to voltage buildup on the input capacitor due to leakage currents or pickup. 7. Gate Protection - These devices do not have an internal monolithic Zener diode from gate to emitter. If gate protection is required an external Zener is recommended. Operating Frequency Information Operating frequency information for a typical device (Figure 3) is presented as a guide for estimating device performance for a specific application. Other typical frequency vs collector current (I CE ) plots are possible using the information shown for a typical unit in Figures 5, 6, 7, 8, 9 and 11. The operating frequency plot (Figure 3) of a typical device shows f MAX1 or fMAX2 ; whichever is smaller at each point. The information is based on measurements of a typical device and is bounded by the maximum rated junction temperature. f MAX1 is defined by fMAX1 = 0.05/(td(OFF)I+ td(ON)I). Deadtime (the denominator) has been arbitrarily held to 10% of the on-state time for a 50% duty factor. Other definitions are possible. t d(OFF)I and td(ON)I are defined in Figure 21. Device turn-off delay can establish an additional frequency limiting condition for an application other than T JM . td(OFF)I is important when controlling output ripple under a lightly loaded condition. f MAX2 is defined by fMAX2 = (PD - PC )/(EOFF + EON2 ). The allowable dissipation (PD ) is defined by PD =( TJM -TC )/RθJC. The sum of device switching and conduction losses must not exceed PD . A 50% duty factor was used (Figure 3) and the conduction losses (P C ) are approximated by PC =( VCE xICE )/2. EON2 and EOFF are defined in the switching waveforms shown in Figure 21. EON2 is the integral of the instantaneous power loss (ICE x VCE ) during turn-on and EOFF is the integral of the instantaneous power loss (ICE xV CE ) during turn-off. All tail losses are included in the calculation for EOFF ; i.e., the collector current equals zero (ICE = 0) ECCOSORBD  is a Trademark of Emerson and Cumming, Inc.

©2001 Fairchild Semiconductor Corporation FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A FGH30N6S2 / FGP30N6S2 / FGS30N6S2 TO-247

3 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE

A b c D E L Ø R Ø S Q Ø P BACK VIEW TERM. 4 e SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A 0.180 0.190 4.58 4.82 - b 0.046 0.051 1.17 1.29 2, 3 b1 0.060 0.070 1.53 1.77 1, 2 b2 0.095 0.105 2.42 2.66 1, 2 c 0.020 0.026 0.51 0.66 1, 2, 3 D 0.800 0.820 20.32 20.82 - E 0.605 0.625 15.37 15.87 - e 0.219 TYP 5.56 TYP 4 e1 0.438 BSC 11.12 BSC 4 J1 0.090 0.105 2.29 2.66 5 L 0.620 0.640 15.75 16.25 - L1 0.145 0.155 3.69 3.93 1 Ø P 0.138 0.144 3.51 3.65 - Q 0.210 0.220 5.34 5.58 - Ø R 0.195 0.205 4.96 5.20 - Ø S 0.260 0.270 6.61 6.85 - NOTES: 1. Lead dimension and finish uncontrolled in L1. 2. Lead dimension (without solder). 3. Add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimen- sion D. 5. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimen- sion D. 6. Controlling dimension: Inch. 7. Revision 1 dated 1-93.

©2001 Fairchild Semiconductor Corporation FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A FGH30N6S2 / FGP30N6S2 / FGS30N6S2 TO-263AB SURFACE MOUNT JEDEC TO-263AB PLASTIC PACKAGE TO-263AB 24mm TAPE REEL MINIMUM PAD SIZE RECOMMENDED FOR SURFACE-MOUNTED APPLICATIONS E A 1 A H 1 D L b e c TERM. 4 TERM. 4 0.450 0.350 0.150 (3.81) 0.080 TYP (2.03) 0.700 (11.43) (8.89) (17.78) 0.062 TYP (1.58) SYMBOL INCHES MILLIMETERS NOTE SMIN MAX MIN MAX A 0.170 0.180 4.32 4.57 - A1 0.048 0.052 1.22 1.32 4, 5 b 0.030 0.034 0.77 0.86 4, 5 b1 0.045 0.055 1.15 1.39 4, 5 b2 0.310 - 7.88 - 2 c 0.018 0.022 0.46 0.55 4, 5 D 0.405 0.425 10.29 10.79 - E 0.395 0.405 10.04 10.28 - e 0.100 TYP 2.54 TYP 7 e1 0.200 BSC 5.08 BSC 7 H 1 0.045 0.055 1.15 1.39 - J1 0.095 0.105 2.42 2.66 - L 0.175 0.195 4.45 4.95 - L1 0.090 0.110 2.29 2.79 4, 6 L2 0.050 0.070 1.27 1.77 3 L3 0.315 - 8.01 - 2 NOTES: 1. These dimensions are within allowable dimensions of Rev. C of JEDEC TO-263AB outline dated 2-92. 2. L3 and b2 dimensions established a minimum mounting surface for terminal 4. 3. Solder finish uncontrolled in this area. 4. Dimension (without solder). 5. Add typically 0.002 inches (0.05mm) for solder plating. 6. L 1 is the terminal length for soldering. 7. Position of lead to be measured 0.120 inches (3.05mm) from bottom of dimension D. 8. Controlling dimension: Inch. 9. Revision 10 dated 5-99. 2.0mm 4.0mm 1.75mm 1.5mm DIA. HOLE CL USER DIRECTION OF FEED 16mm 24mm 330mm 100mm 13mm 30.4mm 24.4mm COVER TAPE GENERAL INFORMATION 1. 800 PIECES PER REEL. 2. ORDER IN MULTIPLES OF FULL REELS ONLY . 3. MEETS EIA-481 REVISION "A" SPECIFICATIONS. ACCESS HOLE 40mm MIN.

©2001 Fairchild Semiconductor Corporation FGH30N6S2 / FGP30N6S2 / FGS30N6S2 Rev. A FGH30N6S2 / FGP30N6S2 / FGS30N6S2 TO-220AB

3 LEAD JEDEC TO-220AB PLASTIC PACKAGE

EØ P Q D H 1 L 60o b 123 e A c 45o D 1 A 1 TERM. 4 SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A 0.170 0.180 4.32 4.57 - A1 0.048 0.052 1.22 1.32 - b 0.030 0.034 0.77 0.86 3, 4 b1 0.045 0.055 1.15 1.39 2, 3 c 0.014 0.019 0.36 0.48 2, 3, 4 D 0.590 0.610 14.99 15.49 - D 1 -0 . 1 6 0 -4 . 0 6- E 0.395 0.410 10.04 10.41 - E1 -0 . 0 3 0 -0 . 7 6- e 0.100 TYP 2.54 TYP 5 e1 0.200 BSC 5.08 BSC 5 H 1 0.235 0.255 5.97 6.47 - J1 0.100 0.110 2.54 2.79 6 L 0.530 0.550 13.47 13.97 - L1 0.130 0.150 3.31 3.81 2 Ø P 0.149 0.153 3.79 3.88 - Q 0.102 0.112 2.60 2.84 - NOTES: 1. These dimensions are within allowable dimensions of Rev. J of JEDEC TO- 220AB outline dated 3-24-87. 2. Lead dimension and finish uncontrolled in L1. 3. Lead dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder coating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimen- sion D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimen- sion D. 7. Controlling dimension: Inch. 8. Revision 2 dated 7-97.

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