308RILF

ICS308_10 IDT | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 9

Technical content

Features

• Packaged in 20-pin SSOP (QSOP) – Pb-free, RoHS compliant • Operating voltage of 3.3 V • Highly accurate frequency generation •M/N Multiplier PLL: M = 1..2048, N = 1..1024 • Serially programmable: user determines the output frequency via a 3-wire interface • Eliminates need for custom quartz oscillators • Input crystal frequency of 5 - 27 MHz •Optional programmable on-chip crystal capacitors • Output clock frequencies up to 200 MHz • Reference clock output • Power down tri-state mode • Very low jitter Block Diagram Crystal Oscillator GND 2 3VDD PDTS PLL2 PLL3 Divide Logic and Output Enable Control SCLK DATA CLK1 CLK9 CLK8 CLK7 CLK6 CLK5 CLK4 CLK3 CLK2 PLL4 PLL1 Crystal or clock input External capacitors are required with a crystal input. X1/ICLK STROBE

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 2 ICS308 REV L 051310 Pin Assignment Pin Descriptions DATA STROBE X1/ICLK SCLK CLK9 PDTS VDD GND VDD VDD GND CLK1 CLK5 CLK2 CLK6 CLK3 CLK7 CLK4 CLK8 20 pin (150 mil) SSOP (QSOP) Pin Number Pin Name Pin Type Pin Description 1 DATA Input Serial data input. 2 X2 XO Crystal Output. Connect this pin to a crystal. Float for clock input. 3 X1/ICLK XI Connect this pin to a crystal or external clock input. 4 CLK9 Output Output clock 9. Default of Re ference frequency output when unprogrammed. 5 VDD Power Connect to +3.3 V. 6 GND Power Connect to Ground. 7 CLK1 Output Output clock 1. Default of Re ference frequency output when unprogrammed. 8 CLK2 Output Output clock 2. Default of Re ference frequency output when unprogrammed. 9 CLK3 Output Output clock 3. Default of Re ference frequency output when unprogrammed. 10 CLK4 Output Output clock 4. Default of Re ference frequency output when unprogrammed. 11 CLK8 Output Output clock 8. Default of Re ference frequency output when unprogrammed. 12 CLK7 Output Output clock 7. Default of Re ference frequency output when unprogrammed. 13 CLK6 Output Output clock 6. Default of Re ference frequency output when unprogrammed. 14 CLK5 Output Output clock 5. Default of Re ference frequency output when unprogrammed. 15 GND Power Connect to Ground. 16 VDD Power Connect to +3.3 V. 17 VDD Power Connect to +3.3 V.

18 PDTS

Input Powers down entire chip, tri-states all outputs when low. Internal pull-up. 19 SCLK Input Serial Shift register clock. See timing diagram. 20 STROBE Input Strobe to load data. See timing diagram. Use external 250 kOhm pull-up.

The STROBE pin must have an external 250 kOhm pull-up resistor to achieve the Initial State. The input crystal range for the ICS308 is 5 MHz to 27 MHz. the VersaClockTM software are written in DATA pin in this order: MSB (left most bit) first. data to the internal hatch and the CLK output will lock within 10 ms. low while DATA is being clocked into the ICS308 in order to avoid unintended changes on the output clocks. brought high, after the Strobe pin in brought high, the programmed output frequencies will be available. Figure 2. Timing Diagram for Programming the ICS308

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 4 ICS308 REV L 051310 External Components Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. STROBE Pull-up Resistor In order for the device to start up in the default state, a 250 kOhm pull-up resistor is required. Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS308 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF . Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2 = 20]. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to each clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. ICS308 Configuration Capabilities The architecture of the ICS308 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 2048 and N = 1 to 1024. The ICS308 also provides separate output divide values, from 2 through 20, to allow the two output clock banks to support widely differing frequency values from the same PLL. Each output frequency can be represented as: Output Freq. = (Ref. Freq)*(M/N)/Output Divide

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 5 ICS308 REV L 051310 VersaClock Software IDT applies years of PLL optimization experience into a user friendly software that accepts the user’s target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple output frequencies. VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS308. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Parameter Item Min. Typ. Max. Units Supply Voltage, VDD Referenced to GND 7 V Inputs Referenced to GND -0.5 VDD+ 0.5 V Clock Outputs Referenced to GND -0.5 VDD+ 0.5 V Storage Temperature -65 150 ° C Soldering Temperature Max 10 seconds 260 ° C Parameter Min. Typ. Max. Units Ambient Operating Temperature (ICS308R) 0 +70 ° C Ambient Operating Temperature (ICS308RI) -40 +85 ° C Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V Power Supply Ramp Time 4 ms

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 6 ICS308 REV L 051310 VDD=3.3 V ±10%, Ambient temperature -40 to +85° C, unless stated otherwise Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.00 3.60 V Operating Supply Current Input High Voltage IDD Configuration Dependent mA Ex. 25 MHz crystal, VDD=3.3 V, No load, 25 mA PDTS = 0 20 µA Input High Voltage V IH X1/ICLK only (VDD/2)+1 V Input Low Voltage V IL X1/ICLK only (VDD/2)-1 V Input High Voltage V IH VDD-0.5 V Input Low Voltage V IL PDTS, SRCLOCK, DATA, STROBE 0.8 V Output High Voltage V OH IOH = -8 mA 2.4 V Output Low Voltage V OL IOL = 8 mA 0.4 V Output High Voltage, CMOS level VOH IOH = -4 mA VDD-0.4 V Short Circuit Current CLK outputs + 70 mA Input Capacitance C IN PDTS pin 4 pF Internal Pull-down Resistor RPD CLK outputs 525 k Ω Internal Pull-up Resistor R PU PDTS pin 250 k Ω

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 7 ICS308 REV L 051310 VDD = 3.3 V±10%, Ambient Temperature -40 to +85° C, unless stated otherwise Note 1: Measured with 15 pF load. Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55% Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency F IN Fundamental crystal 5 27 MHz Input Clock 2 50 MHz Output Frequency VDD=3.3 V 0.25 200 MHz Output Clock Rise Time t OR 20% to 80%, Note 1 0.8 ns Output Clock Fall Time t OF 80% to 20%, Note 1 0.8 ns Output Clock Duty Cycle Note 2 40 49-51 60 % Power-up Time STROBE goes high until stable CLK out 31 0 m s PDTS goes high until stable CLK out .2 2 ms Maximum Output Jitter, short term t j Reference Clock ±300 ps Maximum Output Jitter, short term t j All other clocks, CL=15 pF , configuration dependent ±200 ps Pin-to-Pin Skew Low Skew Outputs -250 250 ps Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 135 ° C/W θJA 1 m/s air flow 93 ° C/W θJA 3 m/s air flow 78 ° C/W Thermal Resistance Junction to Case θJC 60 ° C/W

SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 8 ICS308 REV L 051310 Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

“LF” suffix to the part nu mber denotes Pb-Free configuration, RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature 308RLF 308RLF Tubes 20-pin SSOP 0 to +70 ° C 308RLFT Tape and Reel 20-pin SSOP 0 to +70 ° C 308RILF 308RILF Tubes 20-pin SSOP -40 to +85 ° C 308RILFT Tape and Reel 20-pin SSOP -40 to +85 ° C INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b aaa C c L *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 b 0.20 0.30 0.008 0.012 c 0.18 0.25 0.007 0.010 D 8.55 8.75 0.337 0.344 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e .635 Basic .025 Basic L 0.40 1.27 0.016 0.050 α 0° 8° 0° 8°

© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice . IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Techno logy, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com ICS308 SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER SER PROG CLOCK SYNTHESIZER