ICS307-03 IDT | Alldatasheet
Document overview
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Technical content
Features
- Crystal or clock reference input
- 3.3 V CMOS outputs
- Three outputs can be individually configured or shut off
- Small 16-pin TSSOP package – Pb-free, RoHS compliant
- Reprogrammable during operation
- 3-wire SPI serial interface
- Glitch-free output frequency switching
- User selectable charge pump current and damping resistor
- Power-down control via hardware pin or software control bit
- Programming word can be generated by IDT VersaClock II Software
- Directly programmable via VersaClock II Software and a Windows PC parallel port
- Industrial temperature range available Block Diagram REF Divide 1-2055 VCO DIVIDE 12-2055 Resistor (Table 4) Charge Pump (Table 3) (Table 2) (Table 5) CLK1 [Bit 110] [Bit 123] [Bit 124] [Bit 129] [Bit 111] CLK2 CLK3 (Table 7) Divider 2 - 8232 (Table 1) [Bit 122] Divider 2 - 34 Divider 2 - 34 (Table 6) 11pF 300 pF CP Programming Register (132 bits) DIN CS SCLK
SERIALLY PROGRAMMABLE CLOCK SOUR CE SER PROG CL OCK SYNTHESIZER IDT® SERIALLY PROGRAMMABLE CLOCK SOURCE 2 ICS307-03 REV L 032911 Pin Assignment Pin Descriptions VDD VDD PD VDD GND CLK3 GND CLK2 GND DIN SCLK GND CS CLK1 16-pin TSSOP ICS307-03 Pin Number Pin Name Pin Type Pin Description 1 X1 XI Connect to input reference clock or crystal. 2 VDD Power Power connection for crystal oscillator. 3 VDD Power Power connection for PLL. 4 VDD Power Power connection for inputs and outputs. 5 GND Power Ground connection for crystal oscillator. 6 GND Power Ground connection for PLL. 7 GND Power Ground connection for inputs and outputs. 8 CLK1 Output Clock 1 output. 9 SCLK Input Programming interface - Serial clock input. Internal pull-up. 10 CS Input Programming interface - LOAD input. Internal pull-down. 11 DIN Input Programming interface - Serial data input. Internal pull-up. 12 CLK2 Output Clock 2 output. 13 GND Power Ground connection. 14 CLK3 Output Clock 3 output. 15 PD Input Crystal, PLL, and outputs are powered-down when low. Internal pull-up. 16 X2 - Connect to crystal. Leave open if reference clock input is used.
Table 1. Input Divider Table 2. VCO Divider
3 X X X X X X X 1 1 1 0 1 0 subtract 2 from the
4 X X X X X X X 1 1 0 1 1 0
5 X X X X X X X 1 1 0 0 1 0
6 X X X X X X X 1 0 1 1 1 0
7 X X X X X X X 1 0 1 0 1 0
8 X X X X X X X 1 0 0 1 1 0
9 X X X X X X X 1 0 0 0 1 0
10 X X X X X X X 0 1 1 1 1 0
11 X X X X X X X 0 1 1 0 1 0
12 X X X X X X X 0 1 0 1 1 0
13 X X X X X X X 0 1 0 0 1 0
14 X X X X X X X 0 0 1 1 1 0
15 X X X X X X X 0 0 1 0 1 0
16 X X X X X X X 0 0 0 1 1 0
17 X X X X X X X 0 0 0 0 1 0
Table 3. Charge Pump Current (ICP) Table 4. Loop Filter Resistor (RS)
Table 5. Output Divider for Output 1
2 XXXXXXX X XX X 0 0 0 0
3 XXXXXXX X XX X 0 0 0 1
4 XXXXXXX X XX X 1 0 0 0
5 XXXXXXX X XX X X 0 1 0
6 XXXXXXX X XX X 1 0 0 1
7 XXXXXXX X XX 0 0 0 1 1
8 X X X X X X X 1 1 1 0 1 1 0 0 apply Rule from Divide Values 14-37
9 XXXXXXX X XX 0 1 0 1 1
10 X X X X X X X 1 1 0 1 1 1 0 0 apply Rule from Divide Values 14-37
11 XXXXXXX X XX 1 0 0 1 1
12 X X X X X X X 1 1 0 0 1 1 0 0 apply Rule from Divide Values 14-37
13 XXXXXXX X XX 1 1 0 1 1
14 X X X X X X X 1 0 1 1 1 1 0 0 subtract 6 from the desired divide
15 X X X X X X X 1 0 1 1 0 1 0 0
36 X X X X X X X 0 0 0 0 1 1 0 0
37 X X X X X X X 0 0 0 0 0 1 0 0
Table 6. Output Divider for Output 2 Table 7. Output Divider for Output 3
Table 8. Miscellaneous Control Bits The ICS307-03 requires a minimum number of external components for proper operation. 0.01µF capacitors must be placed as close to the ICS307-03’s power pins as possible to minimize lead inductance. line without the need for any series resistors. For a single ended clock input, connect it to X1 and leave X2 unconnected with no capacitors on either pin. provide an initial system clock at power-up.
110 OE1—set to 1 to enable CLK1
111 OE2—set to 1 to enable CLK2
122 Crystal Input = 1, Clock Input = 0
123 Selects source for CLK2 (see block diagram)
124 Selects source for CLK3 (see block diagram)
125 Reserved—set to 0
126 Reserved—set to 0
129 OE3—set to 1 to enable CLK3
130 Reserved—set to 0
131 Reserved—set to 0
SERIALLY PROGRAMMABLE CLOCK SOUR CE SER PROG CL OCK SYNTHESIZER IDT® SERIALLY PROGRAMMABLE CLOCK SOURCE 8 ICS307-03 REV L 032911 Determining and Controlling the Output Frequency with VersaClockTM II The ICS307-03 is directly supported by the IDT provided software called VersaClock II. Complete programming words for this device can be calculated on any Windows PC by running the VersaClock II software and simple inputting desired input and output frequencies. Once the software generates an appropriate programming word, it may then be either copied to the Windows clipboard or even directly programmed into the ICS307-03 via the host computers parallel port. For more information on VersaClock II, please visit www.idt.com. Manually Determining the Output Frequency The user has full control over the desired output frequency as long as it is operated within the limits shown in the AC Electrical Characteristics. The output of the ICS307-03 can be determined by the following equation: Where: VCO Divider (V) = 12 to 2055 Reference Divider Word (R) = 1 to 2055 Output Divider = values in tables 5, 6, 7 Also, the following operating ranges should be observed. To determine the best combination of VCO, reference, and output dividers, please use the VersaClock II software mentioned above. CLK1Frequency InputFrequency V VCOmin InputFrequency V R---- VCOmaxfreq<⋅< 20kHz Input Frequency
SERIALLY PROGRAMMABLE CLOCK SOUR CE SER PROG CL OCK SYNTHESIZER IDT® SERIALLY PROGRAMMABLE CLOCK SOURCE 9 ICS307-03 REV L 032911 Setting the PLL Loop Response The PLL loop response is determined both by fixed device characteristics and by other characterizes set by the user. This includes the values of RS and CS as shown in the PLL Components figure on this page. The PLL loop bandwidth is approximated by: Where: RS = Value of resistor RS in loop filter in Ohms ICP = Charge pump current in amps KO = VCO Gain in Hz/V FV Divider = 12 to 2055 The above equation calculates the “normalized” loop bandwidth (denoted as “NBW”) which is approximately equal to the - 3dB bandwidth. NBW does not take into account the effects of damping factor or the second pole imposed by CP. It does, however, provide a useful approximation of filter performance. To prevent jitter due to modulation of the PLL by the phase detector frequency, the following general rule should be observed: The PLL loop damping factor is determined by: Where: CS = Value of capacitor CS in loop filter in Farads = 300e-12 in Farads Default Register Values At power-up, the registers are set to: ref divide = 5 VCO divide = 50 output divide = 10 (CLK1) output divide = 2 (CLK2) output divide = 2 (CLK3) bit 123, 124 = 1 ICP = 3.75 µA R = 16k Default programming word is: 0x31FFDFFEE3BFFFFFFFFFFFFFFFF055FF2 NBW(PLL) RS ICP× KO× NBW(VCO PLL) f(Phase Detector) DF(VCLK) RS
SERIALLY PROGRAMMABLE CLOCK SOUR CE SER PROG CL OCK SYNTHESIZER IDT® SERIALLY PROGRAMMABLE CLOCK SOURCE 10 ICS307-03 REV L 032911 Programming Interface The dynamic register within the ICS307-03 controls the entire device and may be reprogrammed any time after power is properly applied. If V or R values are changed, the frequency will transition smoothly to the new value without glitches or short cycles. However, changing any divider or mux in the output signal path may generate a glitch. The register is 132 bits in length and accepts the MSB first. The SCLK signal latches the current data b it value in the rising edge. It latches the most recently shifted 132 bit values into the control register of device whenever CS is high. Care must be taken to ensure that CS is always low until the system is ready to load in a new register value and that SCLK is never toggled high when CS is high. The register can be programmed any time after power is applied, even while in power-down (pin 15 or bit 112 held low) with the waveform and timing shown below:. Figure 2: ICS307-03 Programming Timing Diagram Table 8: AC Parameters for Programming the ICS307-03 Programming with VersaClock Software The VersaClock II Software not only generates the programming word for the user, it can also be used to program the device via the host computer’s parallel port. Demonstration boards are available from IDT that allows the VersaClock II S/W to directly connect the ICS307-03 to a Windows based PC’s DB-25 parallel port connector and programmed simply by pressing the “Program Part” button. Parameter Condition Min. Max. Units tSETUP Setup time 2.5 ns tHOLD Hold time after SCLK 2.5 ns tW Data wait time 2.5 ns tS Strobe pulse width 10 ns SCLK Frequency 200 MHz 128129130131 10 thold tsetup SCLK CS tstw DIN
SERIALLY PROGRAMMABLE CLOCK SOUR CE SER PROG CL OCK SYNTHESIZER IDT® SERIALLY PROGRAMMABLE CLOCK SOURCE 11 ICS307-03 REV L 032911 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS307-03. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operating Conditions VDD=3.3 V ±0.3 V, Ambient temperature 0 to +70° C, unless stated otherwise Item Rating Supply Voltage, VDD 5 V All Inputs and Outputs -0.5 V to VDD+0.5 V Storage Temperature -65 to +150° C Soldering Temperature 260° C Parameter Min. Typ. Max. Units Ambient Operating Temperature 0 +70 ° C Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.0 3.6 V Input High Voltage V IH 2V Input Low Voltage V IL 0.8 V Output High Voltage V OH IOH = -4 mA 2.4 V Output Low Voltage V OL IOL = 4 mA 0.4 V Output High Voltage, CMOS level VOH IOH = -6.5 mA VDD-0.4 V Tri-state Output Leakage 1 µA Operating Supply Current IDD 27 MHz crystal No load, 100 MHz out, all outputs enabled 24 mA Short Circuit Current CLK outputs ±60 mA Input Capacitance C IN 4p F On-Chip Pull-up Resistor R PU 240 k Ω On-Chip Pull-down Resistor RPD 100 k Ω
SERIALLY PROGRAMMABLE CLOCK SOUR CE SER PROG CL OCK SYNTHESIZER IDT® SERIALLY PROGRAMMABLE CLOCK SOURCE 12 ICS307-03 REV L 032911 VDD = 3.3 V ±0.3 V, Ambient Temperature 0 to +70° C, unless stated otherwise Note 1: Measured with 15 pF load. Note 2: Jitter performance will change depending on configuration settings. Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency F IN Fundamental crystal 3 27 MHz Clock 0.1 300 MHz Clock Output Frequency F OUT 5 pF load 0.0002 270 MHz 15 pF load 0.0002 200 MHz Output Clock Rise/Fall Time t R, tF 20 to 80% (5 pF load) 1.5 ns Output Clock Duty Cycle Out put Divides <> 3 45 49-51 55 % Output Divide = 3 40 60 % Frequency Transition time STROBE high to CLK out 31 0 m s One Sigma Clock Period Jitter Note 2 50 ps Maximum Absolute Jitter t ja Deviation from mean, Note 2 ±120 ps VCO Frequency VCO F 100 730 MHz Divider 1 Input Output divider 1 = 2 (5 pF load)
540 MHz
Output divider 1 = 2 (15 pF load)
400 MHz
Output divider 1 = 3 (5 pF load)
720 MHz
Output divider 1 = 3 (15 pF load)
600 MHz
Output divider 1 = 38 ~ 1029
570 MHz
730 MHz
Divider 2 and 3 Inputs Output divider 2, 3 = 2 (5 pF load) Output divider 2, 3 = 2 (15 pF load) Output divider 2, 3=12 440 MHz Output divider 2, 3 = 16, 24, 28 and 32
500 MHz
Divider 2 & 3 values
SERIALLY PROGRAMMABLE CLOCK SOUR CE SER PROG CL OCK SYNTHESIZER IDT® SERIALLY PROGRAMMABLE CLOCK SOURCE 13 ICS307-03 REV L 032911 Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Ordering Information
"LF" suffix to the part number denotes Pb-Free configuration, RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping packaging Package Temperature 307G-03LF 307G03LF Tubes 16-pin TSSOP 0 to +70 ° C 307G-03LFT 307G03LF Tape and Reel 16-pin TSSOP 0 to +70 ° C 307GI-03LF 307GI03L Tubes 16-pin TSSOP -40 to +85 ° C 307GI-03LFT 307GI03L Tape and Reel 16-pin TSSOP -40 to +85 ° C INDEX AREA 1 2 D E1 E SEATING PLANE A AA e - C - b aaa C c L *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A- - 1.20 -- 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 C 0.09 0.20 0.0035 0.008 D 4.90 5.1 0.193 0.201 E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 0.169 0.177 e 0.65 Basic 0.0256 Basic L 0.45 0.75 0.018 0.030 α 0° 8° 0° 8°
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