3010 DATADELAY | Alldatasheet

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VOLTAGE-VARIABLE DELAY LINE TR < 1ns (SERIES 3010)

FEATURES

Fast rise time for high frequency applications Delay continuously adjustable from 2.4ns to 3.4ns Very narrow device (SIP package) Stackable for PC board economy Epoxy encapsulated Meets or exceeds MIL-D-23859C FUNCTIONAL DESCRIPTION The 3010-series devices are continuously variable, single-input, single- output, passive delay lines. The signal input (IN) is reproduced at the output (OUT), shifted by a time (TD) which is adjusted via an applied control voltage (VC). This control voltage is positive for the 3010-P and negative for the 3010-N. The characteristic impedance of the line is nominally 50 ohms. The rise time (TR) of the lines is no more than 1ns, resulting in a 3dB bandwidth of at least 300MHz. The delay resolution is limited only by that of the control voltage. data delay devices, inc. G G IN OUT VC 3010 3010-P: Positive control voltage 3010-N: Negative control voltage PIN DESCRIPTIONS IN Signal Input OUT Signal Output VC Control Voltage G Ground SERIES SPECIFICATIONS Varactor voltage range (3010-P): 1.3V (max TD) to 11.3V (min TD) Varactor voltage range (3010-N): -1.3V (max TD) to -11.3V (min TD) Range of delay variation: 1.0ns minimum Minimum delay: 2.4ns ± 0.25ns Impedance: 45Ω - 68Ω Output rise time: 1.0ns max Bandwidth: 300MHz min 1.3 11.3 6.3 0.0 0.5 1.0 1.5 Delay Impedance Varactor Voltage (V) Delay Variation (ns) Impedance (Ω) Typical Delay/Impedance Variation Overshoot/preshoot: ± 20% max Operating temperature: -10°C to +80°C Temperature coefficient: 1000 PPM/°C max .020 DIA Package Dimensions .100 MIN .150 MAX Series 3010 .200 .200 .100 .800

1.08 MAX

G G VC .380 MAX 2004 Data Delay Devices Doc #04001 DATA DELAY DEVICES, INC. 8/10/2005 3 Mt. Prospect Ave. Clifton, NJ 07013

G OUT G VC 3010-P 1.3V - 11.3V* Rin Signal source impedance Rin: Input termination resistor Ro: Output termination resistor Set Ro to the median impedance value within the delay adjustment range (50Ω - 60Ω) Set Rin = Rout - r r Ro *Reverse polarity for 3010-N. Analog Interface IN G OUT G VC 3010-P 2.6Ro 0V - 10V Vcc Vee Vee=-5.2V Vcc=0V 1.6Ro Vcc Vcc or Vee Vcc Vcc IN G OUT G VC 3010-P Ro 0V - 10V Vee Vcc Vcc, Vee or –2V -2V Vee IN G OUT G VC 3010-N 2.6Ro 2.6V – 12.6V Vcc Vee 1.6Ro Vee=-5.2V Vcc=0V Vcc Vcc or Vee Vcc Vcc IN G OUT G VC 3010-N Ro 2.6V – 12.6V Vee Vcc Vcc, Vee or –2V -2V Vee ECL with –2V Termination ECL without –2V Termination Note: The varicap voltage is referenced to the DC level of the input signal. In the case of ECL applications, a voltage of 0V to 10V (2.6V to 12.6V for the 3010-N) should be applied at pin 6, because the signal line has –1.3V DC level. This assumes the ECL signal has approximately 50% duty cycle. Doc #04001 DATA DELAY DEVICES, INC. 8/10/2005 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

PASSIVE DELAY LINE TEST SPECIFICATIONS TEST CONDITIONS INPUT: OUTPUT: Ambient Temperature: 25oC ± 3oC Rload: 50Ω Input Pulse: High = 1.8V typical Cload: <10pf Low = 0.8V typical Threshold: 50% (Rising & Falling) Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured at 10% and 90% levels) Pulse Width: PWIN = 500ns Period: PERIN = 1000ns NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. Timing Diagram For Testing DRISE DFALL PERIN PWIN TRISE TFALL 10% 10% 50% 50% 90% 90% 50% 50% VIH VIL VOH VOL INPUT SIGNAL OUTPUT SIGNAL TRISE TFALL 10% 10% 90% 90% IN OUT OUT (50Ω) TRIG IN (50Ω) TRIG Test Setup DEVICE UNDER TEST (DUT) OSCILLOSCOPE PULSE GENERATOR VC Doc #04001 DATA DELAY DEVICES, INC. 8/10/2005 3 Mt. Prospect Ave. Clifton, NJ 07013