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300 INTEL | Alldatasheet

Document overview

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• PDF pages: 95

Technical content

Datasheet sections

• 1 Introduction
• 1.1 Terminology
• 1.1.1 Processor Packaging Terminology
• 1.2 References
• 2 Electrical Specifications
• 2.1 Power and Ground Lands
• 2.2 Decoupling Guidelines
• 2.2.1 VCC Decoupling
• 2.2.2 VTT Decoupling
• 2.2.3 FSB Decoupling
• 2.3 Voltage Identification
• 2.4 Reserved, Unused, and TESTHI Signals
• 2.5 Voltage and Current Specification
• 2.5.1 Absolute Maximum and Minimum Ratings
• 2.5.2 DC Voltage and Current Specification
• 2.5.3 VCC Overshoot
• 2.5.4 Die Voltage Validation
• 2.6 Signaling Specifications
• 2.6.1 FSB Signal Groups
• 2.6.2 GTL+ Asynchronous Signals
• 2.6.3 Processor DC Specifications
• 2.6.3.1 GTL+ Front Side Bus Specifications
• 2.7 Clock Specifications
• 2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
• 2.7.2 FSB Frequency Select Signals (BSEL[2:0])
• 2.7.3 Phase Lock Loop (PLL) and Filter
• 2.7.4 BCLK[1:0] Specifications
• 3 Package Mechanical Specifications
• 3.1 Package Mechanical Drawing
• 3.2 Processor Component Keep-Out Zones
• 3.3 Package Loading Specifications
• 3.4 Package Handling Guidelines
• 3.5 Package Insertion Specifications
• 3.6 Processor Mass Specification
• 3.7 Processor Materials
• 3.8 Processor Markings
• 3.9 Processor Land Coordinates
• 4 Land Listing and Signal Descriptions
• 4.1 Processor Land Assignments
• 4.2 Alphabetical Signals Reference
• 5 Thermal Specifications and Design Considerations
• 5.1 Processor Thermal Specifications
• 5.1.1 Thermal Specifications
• 5.1.2 Thermal Metrology
• 5.2 Processor Thermal Features
• 5.2.1 Thermal Monitor
• 5.2.2 On-Demand Mode
• 5.2.3 PROCHOT# Signal
• 5.2.4 THERMTRIP# Signal

Document Number: 311826-005 Intel® Celeron® D Processor 300Δ Sequence Datasheet – On 65 nm Process in the 775-Land Package March 2007

2 Datasheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Celeron® D processor 300 sequence on 65 nm process may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Over time processor numbers will increment based on changes in clock speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See http://www.intel.com/products/processor_number for details. Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. Intel, Pentium, Celeron, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2006–2007 Intel Corporation.

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6.2.4 Enhanced HALT Snoop or HALT Snoop State,

7.1.3 Boxed Processor Retention Mechanism and Heatsink

1V CC Static and Transient Tolerance for 775_VR_CONFIG_05A and 775_VR_CONFIG_06 17 Space Requirements for the Boxed Processor (Side View: applies to all four side views) .... 90

22 Boxed Processor Fan Heatsink Airspace Keep-out Requirements

23 Boxed Processor Fan Heatsink Airspace Keep-out Requirements

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5 VCC Static and Transient Tolerance for 775_VR_CONFIG_05A and 775_VR_CONFIG_06

32 Thermal “Diode” n

Revision History

Rev No. Description Date -001 • Initial release May 2006 -002 • Added 775_VR_CONFIG_06 Specifications

• Added Celeron D processor 360 specifications September 2006 -003
• Added Celeron D processor 347 specifications
• Updated Table 16, “GLT+ Bus Voltage Definitions”.
• Updated VTT_SEL signal descrition in Table 25. October 2006 -004 • Added Celeron D processor 365 specifications January 2007 -005 • Added 775_VR_CONFIG_06 Specificati ons for Celeron D processor 347, 352, 356. March 2007

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Intel® Celeron® D Processor 300 Sequence Features The Intel® Celeron® D processor family expands Intel’s processor family into the value-priced PC market segment. Celeron D processors provide the value that offers the customer the capability to affordably get onto the Internet, and use educational programs, home-office software, and productivity applications. All of the Celeron D processors include an integrated L2 cache, and are built on Intel’s advanced CMOS process technology. The Celeron D processor is backed by over 30 years of Intel experience in manufacturing high-quality, reliable microprocessors. Intel® 64 architecture enables Celeron D processors to execute operating systems and applications written to take advantage of the Intel 64 architecture. The Celeron D processor also includes the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable. § §

• Available at 3.66 GHz, 3.46 GHz, 3.33 GHz, 3.2 GHz, and 3.06 GHz
• Supports Intel ® 64 architecture
• Supports Execute Disable Bit capability
• Binary compatible with applications running on previous members of the Intel microprocessor line
• Intel NetBurst ® microarchitecture
• FSB frequency at 533 MHz
• Hyper-Pipelined Technology
• Advance Dynamic Execution
• Very deep out-of-order execution
• Enhanced branch prediction
• Optimized for 32-bit applications running on advanced 32-bit operating systems
• 144 Streaming SIMD Extensions 2 (SSE2) instructions
• 13 Streaming SIMD Extensions 3 (SSE3) instructions
• Two 16-KB Level 1 data caches
• 256-KB Advanced Transfer Cache (on-die, full-speed Level 2 (L2) cache) with 8-way associativity and Error Correcting Code (ECC)
• 8-way cache associativity provides improved cache hit rate on load/store operations
• Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance
• Power Management capabilities
• System Management mode
• M u l t i p l e l o w - p o w e r s t a t e s
• 775-land Package

1 Introduction

The Intel® Celeron® D processors 365, 360, 356, 352, and 347 are single-core desktop processors on the 65 nm process. The processor uses Flip-Chip Land Grid Array (FC- LGA6) package technology, and plugs into the LGA775 socket. Note: In this document the Intel® Celeron® D processor 300 sequence on the 65 nm process is referred to as the “Celeron D processor” or simply “the processor.” Note: In this document, unless otherwise specified, the Intel® Celeron® D processor 300 sequence refers to Intel Celeron D processors 365, 360, 356, 352, and 347. The Celeron D processor supports Intel® 64 architecture as an enhancement to Intel’s IA-32 architecture. This enhancement enables the processor to execute operating systems and applications written to take advantage of Intel 64 architecture. Further details on the 64-bit extension architecture and programming model can be found in the Intel ® Extended Memory 64 Technology Software Developer Guide at http:// developer.intel.com/technology/64bitextensions/. The Celeron D processor is based on the Intel 32-bit microarchitecture and maintains the tradition of compatibility with IA-32 software. It has the Front Side Bus (FSB) data transfer speed at 533 MB/s and Level 2 cache size of 512 KB. The Celeron D processor also includes the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable. If code attempts to run in non-executable memory, the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can, thus, help improve the overall security of the system. See the Intel ® Architecture Software Developer's Manual for more detailed information. Intel will enable support components for the Celeron D processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling. The processor includes an address bus power down capability that removes power from the address and data signals when the FSB is not in use. This feature is always enabled on the processor.

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level). “Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.

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1.1.1 Processor Packaging Terminology

Commonly used terms are explained here for clarification:

• Intel® Celeron® D Processor 300 sequence on 65 nm process in the 775- land Package— Processor in the FC-LGA6 package with a 512 KB L2 cache.
• Processor — For this document, the term processor is the generic form of the Celeron D processor.
• Keep-out zone — The area on or near the processor that system design can not use.
• I n t e l® 945G/945GZ/945P/945PL Express chipset family — Chipset that supports DDR and DDR2 memory technology for the Celeron D processor on 65 nm process.
• Processor core — Processor core die with integrated L2 cache.
• LGA775 socket — The Celeron D processor on 65 nm process mates with the system board through a surface mount, 775-land, LGA socket.
• Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.
• Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket.
• FSB (Front Side Bus) — The electrical interface that connects the processor to the chipset; also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.
• Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.
• Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied.

1.2 References

Table 1. References NOTE: Refer to this document for 86 W processors. NOTE: Refer To this document for 65 W processors.

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2 Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.

2.1 Power and Ground Lands

The Celeron D processor has 226 VCC (power), 24 VTT and 273 VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied with the voltage determined by the Voltage IDentification (VID) lands. Twenty-four (24) signals are denoted as VTT that provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands that meets the VTT specifications outlined in Table 4.

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 4. Failure to do so can result in timing violations or reduced lifetime of the component.

2.2.1 V CC Decoupling

VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket for further information.

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2.2.2 V TT Decoupling

frequency ceramic capacitors.

2.2.3 FSB Decoupling

frequency capacitance required for the FSB is included on the processor package. also be provided by the motherboard for proper [A]GTL+ bus operation.

2.3 Voltage Identification

voltage for each processor frequency is provided in Table 4. frequency and VID values of the processor. Transportable LGA775 Socket for further details. specified VID are not permitted. Table 4 includes VID step sizes and DC shift ranges. as measured across the VCC_SENSE and VSS_SENSE lands. Table 5. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket for further details.

Table 2. Voltage Identification Definition

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2.4 Reserved, Unused, and TESTHI Signals

All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands. In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon. However, see Table 7 for details on GTL+ signals that do not include on-die termination. Unused active high inputs, should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected, however this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (R TT). For details see Table 16. TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die termination. Inputs and utilized outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. All TESTHI[13:0] lands should be individually connected to V TT via a pull-up resistor that matches the nominal trace impedance. The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:

• T E S T H I [ 1 : 0 ]
• T E S T H I [ 7 : 2 ]
• TESTHI8 – cannot be grouped with other TESTHI signals
• TESTHI9 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be groupe d with other TESTHI signals
• TESTHI11 – cannot be groupe d with other TESTHI signals
• TESTHI12 – cannot be groupe d with other TESTHI signals
• TESTHI13 – cannot be groupe d with other TESTHI signals However, use of boundary scan test will not be functional if these lands are connected together. For optimum noise margin, all pull-up resistor values used for TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used.

2.5 Voltage and Current Specification

2.5.1 Absolute Maximum and Minimum Ratings

limits, functionality and long-term reliability can be expected. Table 3. Absolute Maximu m and Minimum Ratings

1. For functional operation, all processor electr ical, signal quality, mechanical and thermal

specifications must be satisfied.

1. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the
2. Storage temperature is applicable to storage conditions only. In this scenario, the processor must

processor case temperature specifications.

1. This rating applies to the processor and does not include any tray or packaging.
2. Failure to adhere to this specification can affect the long term reliability of the processor.

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2.5.2 DC Voltage and Current Specification

Table 4. Voltage and Current Specifications

3.33 GHz

3.2 GHz

3.06 GHz

3.66 GHz

3.46 GHz

NOTES: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. Adherence to the voltage specifications for the processo r are required to ensure reliable processor operation. 3. Each processor is programmed with a maximum valid voltage identification value (VID) that is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. 4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3 and Table 2 for more information. 5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe. 6. Refer to Table 5 and Figure 1 for the minimum, typical, and maximum V CC allowed for a given current. The processor should not be subjected to any V CC and I CC combination wherein V CC exceeds V CC_MAX for a given current. 7. ICC_MAX is specified at VCC_MAX 8. The current specified is also for AutoHALT State. 9. ICC Stop-Grant is specified at VCC_MAX. 10.The maximum instantaneous current the processor will draw while the thermal control circuit is active (as indicated by the assertion of PROCHOT#) is the same as the maximum ICC for the processor. 11.VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured at the land. 12.Baseboard bandwidth is limited to 20 MHz. 13.This is maximum total current drawn from V TT plane by only the processor. Th is specification does not include the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket to determine the total ITT drawn by the system. 14.This is a steady-state ITT current specification that is applicable when both VTT and VCC are high. 15.This is a power-up peak current specification that is applicable when VTT is high and VCC is low.

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Table 5. V CC Static and Transient Tolerance for 775_VR_CONFIG_05A and

1. The loadline specification includes both static and transient limits except for

overshoot allowed as shown in Section 2.5.3.

1. This table is intended to aid in reading discrete points on Figure 1.
2. The loadlines specify voltage limits at the die measured at the VCC_SENSE and

loadline guidelines and VR implementation details.

1. Adherence to this loadline specification for the Celeron D processor is required to

ensure reliable processor operation.

1. The loadline specification includes both static and transient limits except for overshoot

allowed as shown in Section 2.5.3.

1. This loadline specification shows the deviation from the VID set point.
2. The loadlines specify voltage limits at the die measured at the VCC_SENSE and

and VR implementation details.

2.5.3 V CC Overshoot

exceeds the VID voltage when transitioning from a high to low current load condition. Figure 1. V CC Static and Transient Tolerance for 775_VR_CONFIG_05A and Table 6. Vcc Overshoot Specifications

1. Adherence to these specifications for the Celero n D processor is required to ensure reliable

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1. V OS is measured overshoot voltage.
2. T OS is measured time duration above VID.

2.5.4 Die Voltage Validation

2.6 Signaling Specifications

critical than with previous processor families. bus on the motherboard for most GTL+ signals. Figure 2. V CC Overshoot Example Waveform

2.6.1 FSB Signal Groups

well as the GTL+ I/O group when driving. (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 7. FSB Signal Groups (Sheet 1 of 2)

24 Datasheet

1. Refer to Section 4.2 for signal descriptions.
2. The value of these signals during the acti ve-to-inactive edge of RESET# defines the

processor configuration options. See Section 6.1 for details.

1. In processor systems where no debug port is implemented on the system board, these

implemented on the system board, these signals are no connects. Table 7. FSB Signal Groups (Sheet 2 of 2) Table 8. Signal Characteristics

1. These signals have a 500–5000 Ω pull-up to VTT rather than on-die termination.
2. Signals that do not have RTT, nor are actively driven to their high-voltage level.

Table 9. Signal Reference Voltages

1. These signals also have hysteresis added to the reference voltage. See Table 12 for more

2.6.2 GTL+ Asynchronous Signals

2.6.3 Processor DC Specifications

Table 10. GTL+ Signal Group DC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. The VTT referred to in these specifications is the instantaneous VTT.
4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. VIH and V OH may experience excursions above V TT. However, input signal drivers must comply with the

signal quality specifications.

1. Leakage to VSS with land held at VTT.
2. Leakage to VTT with land held at 300 mV.

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Table 11. GTL+ Asynchronous Si gnal Group DC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals V IH = GTLREF +
4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. VIH and VOH may experience excursions above V TT. However, input signal drivers must comply with the

signal quality specifications.

1. The VTT referred to in these specifications refers to instantaneous VTT.
2. All outputs are open drain.
3. The maximum output current is based on maximum cu rrent handling capability of the buffer and is not

specified into the test load.

1. Leakage to VSS with land held at VTT.

10.Leakage to VTT with land held at 300 mV. Table 12. PWRGOOD and TAP Sign al Group DC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open drain.
3. VHYS represents the amount of hysteresis, nominally centered about 0.5 * VTT, for all TAP inputs.
4. The VTT referred to in these specifications refers to instantaneous VTT.

1. 0.24 V is defined at 20% of nominal V TT of 1.2 V.
2. The TAP signal group must meet the signal quality specifications.
3. The maximum output current is based on maximum current handling capability of the buffer and is

not specified into the test load.

1. Leakage to VSS with land held at VTT.
2. Leakage to VTT with land held at 300 mV.

Table 13. VTTPWRGD DC Specifications Table 14. BSEL[2:0] and VI D[5:0] DC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. Leakage to VSS with land held at 1.2 V.

Table 15. BOOTSELECT DC Specifications

1. These parameters are not tested and are based on design simulations.

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2.6.3.1 GTL+ Front Side Bus Specifications

precision voltage divider circuits. Table 16. GTL+ Bus Voltage Definitions

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each GTLREF
3. For Intel 865 Express chipset LGA775 boards only, the GTLREF_PU should be 49.9 Ω 1%, and the GTLREF_PD should
4. These pull-ups are to VTT.
5. RTT is the on-die termination resistance measured at VTT/2 of the GTL+ output driver. The IMPSEL land

is used to select a 50 Ω or 60 Ω buffer and RTT value.

1. COMP resistance must be provided on the system board with 1% resistors. COMP[1:0] resistors are

to VSS. COMP[5:4] resistors are to VTT.

2.7 Clock Specifications

2.7.1 Front Side Bus Clock (BCL K[1:0]) and Processor Clocking

Table 17. Core Frequency to FS B Multiplier Configuration

533 MHz FSB)

1. Individual processors operate only at or below the rated frequency.
2. Listed frequencies are not necessarily committed production frequencies.

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2.7.2 FSB Frequency Sele ct Signals (BSEL[2:0])

133 MHz BCLK[1:0] frequency). For more information about these signals, refer to Section 4.2.

2.7.3 Phase Lock Lo op (PLL) and Filter

• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 3.

Table 18. BSEL[2:0] Frequency Table for BCLK[1:0]

1. No specification for frequencie s beyond fcore (core frequency).

peak, if existent, should be less than 0.05 MHz.

1. f core represents the maximum core frequency supported by the platform.

Figure 3. Phase Lock Loop (PLL) Filter Requirements

1 MHz 66 MHz fcorefpeak1 HzDC

32 Datasheet

2.7.4 BCLK[1:0] Specifications

Table 19. Front Side Bus Diffe rential BCLK Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0

equals the falling edge of BCLK1.

1. The crossing point must meet the absolute and relative crossing point specifications
2. VHavg is the statistical average of the VH measured by the oscilloscope.
3. VHavg can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on Tektronix*
4. Overshoot is defined as the absolute value of the maximum voltage.
5. Undershoot is defined as the absolute value of the minimum voltage.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising

Edge Ringback and the maximum Falling Edge Ringback.

1. Threshold Region is defined as a region entered around the crossing point voltage in which the

differential receiver switches. It includes input threshold hysteresis.

3 Package Mechanical

LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.

• Integrated Heat Spreader (IHS)
• Thermal Interface Material (TIM)
• Processor core (die)
• Package substrate
• Capacitors NOTE: 1. Socket and motherboard are included for refe rence and are not part of processor package.

3.1 Package Mechanical Drawing

• Package reference with tolerances (total height, length, width, etc.)
• IHS parallelism and tilt
• Land dimensions
• Top-side and back-side component keep-out dimensions
• Reference datums
• All drawing dimensions are in mm [in].
• Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines.

Figure 4. Processor Package Assembly Sketch

34 Datasheet

Figure 5. Processor Package Drawing (Sheet 1 of 3)

Figure 6. Processor Package Drawing (Sheet 2 of 3)

36 Datasheet

Figure 7. Processor Package Drawing (Sheet 3 of 3)

3.2 Processor Component Keep-Out Zones

manufacturing efficiencies but will remain within the component keep-in.

3.3 Package Loading Specifications

Table 20 provides dynamic and static load specifications for the processor package. maintained by any thermal and mechanical solutions.

3.4 Package Handling Guidelines

handling loads may be experienced during heatsink removal. Table 20. Processor Lo ading Specifications

1. These specifications apply to uniform compressive loading in a direction normal to the
2. This is the maximum force that can be applied by a heatsink retention clip. The clip must also

provide the minimum specified load on the processor package.

1. These specifications are based on limited testing for design characterization. Loading limits are

for the package only and do not include the limits of the processor socket.

1. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load

Table 21. Package Handling Guidelines

1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
2. These guidelines are based on limite d testing for design characterization.
3. A tensile load is defined as a pulling load appl ied to the IHS in a direction normal to the IHS
4. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the

38 Datasheet

3.5 Package Insertion Specifications

3.6 Processor Mass Specification

includes all the components that are included in the package.

3.7 Processor Materials

Table 22 lists some of the package components and associated materials.

3.8 Processor Markings

identification of the Celeron D processor. Table 22. Processor Materials Figure 8. Processor Top-Side Marking Example

356 SLxxx [COO]

3.9 Processor Land Coordinates

referred to throughout the document to identify processor lands. Figure 9. Processor La nd Coordinates and Quadrants (Top View)

Package Mechanical Specifications

40 Datasheet

Land Listing and Signal Descriptions

4 Land Listing and Signal

This chapter provides the processor land assignment and signal descriptions.

4.1 Processor Land Assignments

This section contains the land listings for the processor. The land-out footprint is shown in Figure 10 and Figure 11. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view). Table 23 is a listing of all processor lands ordered alphabetically by land (signal) name. Table 24 is also a listing of all processor lands; the ordering is by land number.

Land Listing and Signal Descriptions

42 Datasheet

Figure 10.land-out Diagram (Top View – Left Side) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AM VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AL VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AK VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AJ VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AH VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AG VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AF VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AE VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VCC VCC VSS VSS VCC AD VCC VCC VCC VCC VCC VCC VCC VCC AC VCC VCC VCC VCC VCC VCC VCC VCC AB VSS VSS VSS VSS VSS VSS VSS VSS AA VSS VSS VSS VSS VSS VSS VSS VSS Y VCC VCC VCC VCC VCC VCC VCC VCC W VCC VCC VCC VCC VCC VCC VCC VCC V VSS VSS VSS VSS VSS VSS VSS VSS U VCC VCC VCC VCC VCC VCC VCC VCC T VCC VCC VCC VCC VCC VCC VCC VCC R VSS VSS VSS VSS VSS VSS VSS VSS P VSS VSS VSS VSS VSS VSS VSS VSS N VCC VCC VCC VCC VCC VCC VCC VCC M VCC VCC VCC VCC VCC VCC VCC VCC L VSS VSS VSS VSS VSS VSS VSS VSS K VCC VCC VCC VCC VCC VCC VCC VCC J VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DP3# DP0# VCC H BSEL1 FC15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DP2# DP1# G BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31# F RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD VSS D43# D41# VSS D38# D37# VSS D30# E VSS VSS VSS VSS VSS FC17 RSVD D45# D42# VSS D40# D39# VSS D34# D33# D VTT VTT VTT VTT VTT VTT VSS RSVD D46# VSS D48# DBI2# VSS D49# RSVD VSS C VTT VTT VTT VTT VTT VTT VSS VCCIO PLL VSS D58# DBI3# VSS D54# DSTBP3# VSS D51# B VTT VTT VTT VTT VTT VTT VSS VSSA D63# D59# VSS D60# D57# VSS D55# D53# A VTT VTT VTT VTT VTT VTT VSS VCCA D62# VSS RSVD D61# VSS D56# DSTBN3# VSS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15

Land Listing and Signal Descriptions Figure 11.land-out Diagram (Top View – Right Side) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VCC VSS VCC VCC VSS VCC VCC FC16 VSS_MB_ REGULATION VCC_MB_ REGULATION VSS_ SENSE VCC_ SENSE VSS VSS AN VCC VSS VCC VCC VSS VCC VCC FC12 VTTPWRGD FC11 VSS VID2 VID0 VSS AM VCC VSS VCC VCC VSS VCC VCC VSS VID3 VID1 VID5 VSS PROCHOT# THERMDA AL VCC VSS VCC VCC VSS VCC VCC VSS FC8 VSS VID4 ITP_CLK0 VSS THERMDC AK VCC VSS VCC VCC VSS VCC VCC VSS A35# A34# VSS ITP_CLK1 BPM0# BPM1# AJ VCC VSS VCC VCC VSS VCC VCC VSS VSS A33# A32# VSS RSVD VSS AH VCC VSS VCC VCC VSS VCC VCC VSS A29# A31# A30# BPM5# BPM3# TRST# AG VCC VSS VCC VCC VSS VCC VCC VSS VSS A27# A28# VSS BPM4# TDO AF VCC VSS VCC VCC VSS VCC SKTOCC# VSS RSVD VSS RSVD RSVD VSS TCK AE VCC VSS A22# ADSTB1# VSS BINIT# BPM2# TDI AD VCC VSS VSS A25# RSVD VSS DBR# TMS AC VCC VSS A17# A24# A26# MCERR# IERR# VSS AB VCC VSS VSS A23# A21# VSS LL_ID1 VTT_OUT_ RIGHT AA VCC VSS A19# VSS A20# RSVD VSS BOOT SELECT Y VCC VSS A18# A16# VSS TESTHI1 TESTHI12 MSID0 W VCC VSS VSS A14# A15# VSS LL_ID0 MSID1 V VCC VSS A10# A12# A13# AP1# AP0# VSS U VCC VSS VSS A9# A11# VSS COMP5 COMP1 T VCC VSS ADSTB0# VSS A8# FERR#/ PBE# VSS FC2 R VCC VSS A4# RSVD VSS INIT# SMI# TESTHI11 P VCC VSS VSS RSVD RSVD VSS IGNNE# PWRGOOD N VCC VSS REQ2# A5# A7# STPCLK# THERMTRI P# VSS M VCC VSS VSS A3# A6# VSS TESTHI13 LINT1 L VCC VSS REQ3# VSS REQ0# A20M# VSS LINT0 K VCC VCC VCC VCC VCC VCC VCC VSS REQ4# REQ1# VSS RSVD COMP4 VTT_OUT_ LEFT J VSS VSS VSS VSS VSS VSS VSS VSS VSS TESTHI10 RSP# VSS GTLREF1 GTLREF0 H D29# D27# DSTBN1# DBI1# RSVD D16# BPRI# DEFER# RSVD FC7 TESTHI9 TESTHI8 FC1 VSS G D28# VSS D24# D23# VSS D18# D17# VSS IMPSEL RS1# VSS BR0# FC5 F VSS D26# DSTBP1# VSS D21# D19# VSS RSVD RSVD RSVD HITM# TRDY# VSS E RSVD D25# VSS D15# D22# VSS D12# D20# VSS VSS HIT# VSS ADS# RSVD D D52# VSS D14# D11# VSS RSVD DSTBN0# VSS D3# D1# VSS LOCK# BNR# DRDY# C VSS RSVD D13# VSS D10# DSTBP0# VSS D6# D5# VSS D0# RS0# DBSY# VSS B D50# COMP0 VSS D9# D8# VSS DBI0# D7# VSS D4# D2# RS2# VSS A 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Land Listing and Signal Descriptions

44 Datasheet

Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction A3# L5 Source Synch Input/Output A4# P6 Source Synch Input/Output A5# M5 Source Synch Input/Output A6# L4 Source Synch Input/Output A7# M4 Source Synch Input/Output A8# R4 Source Synch Input/Output A9# T5 Source Synch Input/Output A10# U6 Source Synch Input/Output A11# T4 Source Synch Input/Output A12# U5 Source Synch Input/Output A13# U4 Source Synch Input/Output A14# V5 Source Synch Input/Output A15# V4 Source Synch Input/Output A16# W5 Source Synch Input/Output A17# AB6 Source Synch Input/Output A18# W6 Source Synch Input/Output A19# Y6 Source Synch Input/Output A20# Y4 Source Synch Input/Output A20M# K3 Asynch GTL+ Input A21# AA4 Source Synch Input/Output A22# AD6 Source Synch Input/Output A23# AA5 Source Synch Input/Output A24# AB5 Source Synch Input/Output A25# AC5 Source Synch Input/Output A26# AB4 Source Synch Input/Output A27# AF5 Source Synch Input/Output A28# AF4 Source Synch Input/Output A29# AG6 Source Synch Input/Output A30# AG4 Source Synch Input/Output A31# AG5 Source Synch Input/Output A32# AH4 Source Synch Input/Output A33# AH5 Source Synch Input/Output A34# AJ5 Source Synch Input/Output A35# AJ6 Source Synch Input/Output ADS# D2 Common Clock Input/Output ADSTB0# R6 Source Synch Input/Output ADSTB1# AD5 Source Synch Input/Output AP0# U2 Common Clock Input/Output AP1# U3 Common Clock Input/Output BCLK0 F28 Clock Input BCLK1 G28 Clock Input BINIT# AD3 Common Clock Input/Output BNR# C2 Common Clock Input/Output BOOTSELECT Y1 Power/Other Input BPM0# AJ2 Common Clock Input/Output BPM1# AJ1 Common Clock Input/Output BPM2# AD2 Common Clock Input/Output BPM3# AG2 Common Clock Input/Output BPM4# AF2 Common Clock Input/Output BPM5# AG3 Common Clock Input/Output BPRI# G8 Common Clock Input BR0# F3 Common Clock Input/Output BSEL0 G29 Power/Other Output BSEL1 H30 Power/Other Output BSEL2 G30 Power/Other Output COMP0 A13 Power/Other Input COMP1 T1 Power/Other Input COMP4 J2 Power/Other Input COMP5 T2 Power/Other Input D0# B4 Source Synch Input/Output D1# C5 Source Synch Input/Output D2# A4 Source Synch Input/Output D3# C6 Source Synch Input/Output D4# A5 Source Synch Input/Output D5# B6 Source Synch Input/Output D6# B7 Source Synch Input/Output D7# A7 Source Synch Input/Output D8# A10 Source Synch Input/Output D9# A11 Source Synch Input/Output D10# B10 Source Synch Input/Output D11# C11 Source Synch Input/Output D12# D8 Source Synch Input/Output D13# B12 Source Synch Input/Output D14# C12 Source Synch Input/Output D15# D11 Source Synch Input/Output D16# G9 Source Synch Input/Output D17# F8 Source Synch Input/Output D18# F9 Source Synch Input/Output Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction

Land Listing and Signal Descriptions Datasheet 45 D19# E9 Source Synch Input/Output D20# D7 Source Synch Input/Output D21# E10 Source Synch Input/Output D22# D10 Source Synch Input/Output D23# F11 Source Synch Input/Output D24# F12 Source Synch Input/Output D25# D13 Source Synch Input/Output D26# E13 Source Synch Input/Output D27# G13 Source Synch Input/Output D28# F14 Source Synch Input/Output D29# G14 Source Synch Input/Output D30# F15 Source Synch Input/Output D31# G15 Source Synch Input/Output D32# G16 Source Synch Input/Output D33# E15 Source Synch Input/Output D34# E16 Source Synch Input/Output D35# G18 Source Synch Input/Output D36# G17 Source Synch Input/Output D37# F17 Source Synch Input/Output D38# F18 Source Synch Input/Output D39# E18 Source Synch Input/Output D40# E19 Source Synch Input/Output D41# F20 Source Synch Input/Output D42# E21 Source Synch Input/Output D43# F21 Source Synch Input/Output D44# G21 Source Synch Input/Output D45# E22 Source Synch Input/Output D46# D22 Source Synch Input/Output D47# G22 Source Synch Input/Output D48# D20 Source Synch Input/Output D49# D17 Source Synch Input/Output D50# A14 Source Synch Input/Output D51# C15 Source Synch Input/Output D52# C14 Source Synch Input/Output D53# B15 Source Synch Input/Output D54# C18 Source Synch Input/Output D55# B16 Source Synch Input/Output D56# A17 Source Synch Input/Output D57# B18 Source Synch Input/Output Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction D58# C21 Source Synch Input/Output D59# B21 Source Synch Input/Output D60# B19 Source Synch Input/Output D61# A19 Source Synch Input/Output D62# A22 Source Synch Input/Output D63# B22 Source Synch Input/Output DBI0# A8 Source Synch Input/Output DBI1# G11 Source Synch Input/Output DBI2# D19 Source Synch Input/Output DBI3# C20 Source Synch Input/Output DBR# AC2 Power/Other Output DBSY# B2 Common Clock Input/Output DEFER# G7 Common Clock Input DP0# J16 Common Clock Input/Output DP1# H15 Common Clock Input/Output DP2# H16 Common Clock Input/Output DP3# J17 Common Clock Input/Output DRDY# C1 Common Clock Input/Output DSTBN0# C8 Source Synch Input/Output DSTBN1# G12 Source Synch Input/Output DSTBN2# G20 Source Synch Input/Output DSTBN3# A16 Source Synch Input/Output DSTBP0# B9 Source Synch Input/Output DSTBP1# E12 Source Synch Input/Output DSTBP2# G19 Source Synch Input/Output DSTBP3# C17 Source Synch Input/Output FC1 G2 Power/Other Input FC2 R1 Power/Other Input FC5 F2 Common Clock Input FC7 G5 Source Synch Output FC8 AK6 FC11 AM5 Power/Other Output FC12 AM7 Power/Other Output FC15 H29 Power/Other Output FC16 AN7 Power/Other Output FC17 E24 Power/Other Output FERR#/PBE# R3 Asynch GTL+ Output GTLREF0 H1 Power/Other Input GTLREF1 H2 Power/Other Input Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction

Land Listing and Signal Descriptions

46 Datasheet

HIT# D4 Common Clock Input/Output HITM# E4 Common Clock Input/Output IERR# AB2 Asynch GTL+ Output IGNNE# N2 Asynch GTL+ Input IMPSEL F6 Power/Other Input INIT# P3 Asynch GTL+ Input ITP_CLK0 AK3 TAP Input ITP_CLK1 AJ3 TAP Input LINT0 K1 Asynch GTL+ Input LINT1 L1 Asynch GTL+ Input LL_ID0 V2 Power/Other Output LL_ID1 AA2 Power/Other Output LOCK# C3 Common Clock Input/Output MCERR# AB3 Common Clock Input/Output MSID0 W1 Power/Other Output MSID1 V1 Power/Other Output PROCHOT# AL2 Asynch GTL+ Input/Output PWRGOOD N1 Power/Other Input REQ0# K4 Source Synch Input/Output REQ1# J5 Source Synch Input/Output REQ2# M6 Source Synch Input/Output REQ3# K6 Source Synch Input/Output REQ4# J6 Source Synch Input/Output RESERVED B13 RESERVED A20 RESERVED AC4 RESERVED AE3 RESERVED AE4 RESERVED AE6 RESERVED AH2 RESERVED C9 RESERVED D1 RESERVED D14 RESERVED D16 RESERVED D23 RESERVED E23 RESERVED E5 RESERVED E6 RESERVED E7 Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction RESERVED F23 RESERVED F29 RESERVED G10 RESERVED G6 RESERVED J3 RESERVED N4 RESERVED N5 RESERVED P5 RESERVED Y3 RESET# G23 Common Clock Input RS0# B3 Common Clock Input RS1# F5 Common Clock Input RS2# A3 Common Clock Input RSP# H4 Common Clock Input SKTOCC# AE8 Power/Other Output SMI# P2 Asynch GTL+ Input STPCLK# M3 Asynch GTL+ Input TCK AE1 TAP Input TDI AD1 TAP Input TDO AF1 TAP Output TESTHI0 F26 Power/Other Input TESTHI1 W3 Power/Other Input TESTHI2 F25 Power/Other Input TESTHI3 G25 Power/Other Input TESTHI4 G27 Power/Other Input TESTHI5 G26 Power/Other Input TESTHI6 G24 Power/Other Input TESTHI7 F24 Power/Other Input TESTHI8 G3 Power/Other Input TESTHI9 G4 Power/Other Input TESTHI10 H5 Power/Other Input TESTHI11 P1 Power/Other Input TESTHI12 W2 Power/Other Input TESTHI13 L2 Asynch GTL+ Input THERMDA AL1 Power/Other THERMDC AK1 Power/Other THERMTRIP# M2 Asynch GTL+ Output TMS AC1 TAP Input TRDY# E3 Common Clock Input Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction

Land Listing and Signal Descriptions Datasheet 47 TRST# AG1 TAP Input VCC AA8 Power/Other VCC AB8 Power/Other VCC AC23 Power/Other VCC AC24 Power/Other VCC AC25 Power/Other VCC AC26 Power/Other VCC AC27 Power/Other VCC AC28 Power/Other VCC AC29 Power/Other VCC AC30 Power/Other VCC AC8 Power/Other VCC AD23 Power/Other VCC AD24 Power/Other VCC AD25 Power/Other VCC AD26 Power/Other VCC AD27 Power/Other VCC AD28 Power/Other VCC AD29 Power/Other VCC AD30 Power/Other VCC AD8 Power/Other VCC AE11 Power/Other VCC AE12 Power/Other VCC AE14 Power/Other VCC AE15 Power/Other VCC AE18 Power/Other VCC AE19 Power/Other VCC AE21 Power/Other VCC AE22 Power/Other VCC AE23 Power/Other VCC AE9 Power/Other VCC AF11 Power/Other VCC AF12 Power/Other VCC AF14 Power/Other VCC AF15 Power/Other VCC AF18 Power/Other VCC AF19 Power/Other VCC AF21 Power/Other VCC AF22 Power/Other Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC AF8 Power/Other VCC AF9 Power/Other VCC AG11 Power/Other VCC AG12 Power/Other VCC AG14 Power/Other VCC AG15 Power/Other VCC AG18 Power/Other VCC AG19 Power/Other VCC AG21 Power/Other VCC AG22 Power/Other VCC AG25 Power/Other VCC AG26 Power/Other VCC AG27 Power/Other VCC AG28 Power/Other VCC AG29 Power/Other VCC AG30 Power/Other VCC AG8 Power/Other VCC AG9 Power/Other VCC AH11 Power/Other VCC AH12 Power/Other VCC AH14 Power/Other VCC AH15 Power/Other VCC AH18 Power/Other VCC AH19 Power/Other VCC AH21 Power/Other VCC AH22 Power/Other VCC AH25 Power/Other VCC AH26 Power/Other VCC AH27 Power/Other VCC AH28 Power/Other VCC AH29 Power/Other VCC AH30 Power/Other VCC AH8 Power/Other VCC AH9 Power/Other VCC AJ11 Power/Other VCC AJ12 Power/Other VCC AJ14 Power/Other VCC AJ15 Power/Other VCC AJ18 Power/Other Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction

Land Listing and Signal Descriptions

48 Datasheet

Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC AM21 Power/Other VCC AM22 Power/Other VCC AM25 Power/Other VCC AM26 Power/Other VCC AM29 Power/Other VCC AM30 Power/Other VCC AM8 Power/Other VCC AM9 Power/Other VCC AN11 Power/Other VCC AN12 Power/Other VCC AN14 Power/Other VCC AN15 Power/Other VCC AN18 Power/Other VCC AN19 Power/Other VCC AN21 Power/Other VCC AN22 Power/Other VCC AN25 Power/Other VCC AN26 Power/Other VCC AN29 Power/Other VCC AN30 Power/Other VCC AN8 Power/Other VCC AN9 Power/Other VCC J10 Power/Other VCC J11 Power/Other VCC J12 Power/Other VCC J13 Power/Other VCC J14 Power/Other VCC J15 Power/Other VCC J18 Power/Other VCC J19 Power/Other VCC J20 Power/Other VCC J21 Power/Other VCC J22 Power/Other VCC J23 Power/Other VCC J24 Power/Other VCC J25 Power/Other VCC J26 Power/Other VCC J27 Power/Other VCC J28 Power/Other Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction

Land Listing and Signal Descriptions Datasheet 49 VCC J29 Power/Other VCC J30 Power/Other VCC J8 Power/Other VCC J9 Power/Other VCC K23 Power/Other VCC K24 Power/Other VCC K25 Power/Other VCC K26 Power/Other VCC K27 Power/Other VCC K28 Power/Other VCC K29 Power/Other VCC K30 Power/Other VCC K8 Power/Other VCC L8 Power/Other VCC M23 Power/Other VCC M24 Power/Other VCC M25 Power/Other VCC M26 Power/Other VCC M27 Power/Other VCC M28 Power/Other VCC M29 Power/Other VCC M30 Power/Other VCC M8 Power/Other VCC N23 Power/Other VCC N24 Power/Other VCC N25 Power/Other VCC N26 Power/Other VCC N27 Power/Other VCC N28 Power/Other VCC N29 Power/Other VCC N30 Power/Other VCC N8 Power/Other VCC P8 Power/Other VCC R8 Power/Other VCC T23 Power/Other VCC T24 Power/Other VCC T25 Power/Other VCC T26 Power/Other VCC T27 Power/Other Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC T28 Power/Other VCC T29 Power/Other VCC T30 Power/Other VCC T8 Power/Other VCC U23 Power/Other VCC U24 Power/Other VCC U25 Power/Other VCC U26 Power/Other VCC U27 Power/Other VCC U28 Power/Other VCC U29 Power/Other VCC U30 Power/Other VCC U8 Power/Other VCC V8 Power/Other VCC W23 Power/Other VCC W24 Power/Other VCC W25 Power/Other VCC W26 Power/Other VCC W27 Power/Other VCC W28 Power/Other VCC W29 Power/Other VCC W30 Power/Other VCC W8 Power/Other VCC Y23 Power/Other VCC Y24 Power/Other VCC Y25 Power/Other VCC Y26 Power/Other VCC Y27 Power/Other VCC Y28 Power/Other VCC Y29 Power/Other VCC Y30 Power/Other VCC Y8 Power/Other VCC_MB_ REGULATION AN5 Power/Other Output VCC_SENSE AN3 Power/Other Output VCCA A23 Power/Other VCCIOPLL C23 Power/Other VID0 AM2 Power/Other Output VID1 AL5 Power/Other Output VID2 AM3 Power/Other Output Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction

Land Listing and Signal Descriptions

50 Datasheet

VID3 AL6 Power/Other Output VID4 AK4 Power/Other Output VID5 AL4 Power/Other Output VSS B1 Power/Other VSS B11 Power/Other VSS B14 Power/Other VSS B17 Power/Other VSS B20 Power/Other VSS B24 Power/Other VSS B5 Power/Other VSS B8 Power/Other VSS A12 Power/Other VSS A15 Power/Other VSS A18 Power/Other VSS A2 Power/Other VSS A21 Power/Other VSS A24 Power/Other VSS A6 Power/Other VSS A9 Power/Other VSS AA23 Power/Other VSS AA24 Power/Other VSS AA25 Power/Other VSS AA26 Power/Other VSS AA27 Power/Other VSS AA28 Power/Other VSS AA29 Power/Other VSS AA3 Power/Other VSS AA30 Power/Other VSS AA6 Power/Other VSS AA7 Power/Other VSS AB1 Power/Other VSS AB23 Power/Other VSS AB24 Power/Other VSS AB25 Power/Other VSS AB26 Power/Other VSS AB27 Power/Other VSS AB28 Power/Other VSS AB29 Power/Other VSS AB30 Power/Other Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS AB7 Power/Other VSS AC3 Power/Other VSS AC6 Power/Other VSS AC7 Power/Other VSS AD4 Power/Other VSS AD7 Power/Other VSS AE10 Power/Other VSS AE13 Power/Other VSS AE16 Power/Other VSS AE17 Power/Other VSS AE2 Power/Other VSS AE20 Power/Other VSS AE24 Power/Other VSS AE25 Power/Other VSS AE26 Power/Other VSS AE27 Power/Other VSS AE28 Power/Other VSS AE29 Power/Other VSS AE30 Power/Other VSS AE5 Power/Other VSS AE7 Power/Other VSS AF10 Power/Other VSS AF13 Power/Other VSS AF16 Power/Other VSS AF17 Power/Other VSS AF20 Power/Other VSS AF23 Power/Other VSS AF24 Power/Other VSS AF25 Power/Other VSS AF26 Power/Other VSS AF27 Power/Other VSS AF28 Power/Other VSS AF29 Power/Other VSS AF3 Power/Other VSS AF30 Power/Other VSS AF6 Power/Other VSS AF7 Power/Other VSS AG10 Power/Other VSS AG13 Power/Other Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction

Land Listing and Signal Descriptions Datasheet 51 VSS AG16 Power/Other VSS AG17 Power/Other VSS AG20 Power/Other VSS AG23 Power/Other VSS AG24 Power/Other VSS AG7 Power/Other VSS AH1 Power/Other VSS AH10 Power/Other VSS AH13 Power/Other VSS AH16 Power/Other VSS AH17 Power/Other VSS AH20 Power/Other VSS AH23 Power/Other VSS AH24 Power/Other VSS AH3 Power/Other VSS AH6 Power/Other VSS AH7 Power/Other VSS AJ10 Power/Other VSS AJ13 Power/Other VSS AJ16 Power/Other VSS AJ17 Power/Other VSS AJ20 Power/Other VSS AJ23 Power/Other VSS AJ24 Power/Other VSS AJ27 Power/Other VSS AJ28 Power/Other VSS AJ29 Power/Other VSS AJ30 Power/Other VSS AJ4 Power/Other VSS AJ7 Power/Other VSS AK10 Power/Other VSS AK13 Power/Other VSS AK16 Power/Other VSS AK17 Power/Other VSS AK2 Power/Other VSS AK20 Power/Other VSS AK23 Power/Other VSS AK24 Power/Other VSS AK27 Power/Other Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS AK28 Power/Other VSS AK29 Power/Other VSS AK30 Power/Other VSS AK5 Power/Other VSS AK7 Power/Other VSS AL10 Power/Other VSS AL13 Power/Other VSS AL16 Power/Other VSS AL17 Power/Other VSS AL20 Power/Other VSS AL23 Power/Other VSS AL24 Power/Other VSS AL27 Power/Other VSS AL28 Power/Other VSS AL3 Power/Other VSS AL7 Power/Other VSS AM1 Power/Other VSS AM10 Power/Other VSS AM13 Power/Other VSS AM16 Power/Other VSS AM17 Power/Other VSS AM20 Power/Other VSS AM23 Power/Other VSS AM24 Power/Other VSS AM27 Power/Other VSS AM28 Power/Other VSS AM4 Power/Other VSS AN1 Power/Other VSS AN10 Power/Other VSS AN13 Power/Other VSS AN16 Power/Other VSS AN17 Power/Other VSS AN2 Power/Other VSS AN20 Power/Other VSS AN23 Power/Other VSS AN24 Power/Other VSS AN27 Power/Other VSS AN28 Power/Other VSS C10 Power/Other Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction

Land Listing and Signal Descriptions

52 Datasheet

Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS H14 Power/Other VSS H17 Power/Other VSS H18 Power/Other VSS H19 Power/Other VSS H20 Power/Other VSS H21 Power/Other VSS H22 Power/Other VSS H23 Power/Other VSS H24 Power/Other VSS H25 Power/Other VSS H26 Power/Other VSS H27 Power/Other VSS H28 Power/Other VSS H3 Power/Other VSS H6 Power/Other VSS H7 Power/Other VSS H8 Power/Other VSS H9 Power/Other VSS J4 Power/Other VSS J7 Power/Other VSS K2 Power/Other VSS K5 Power/Other VSS K7 Power/Other VSS L23 Power/Other VSS L24 Power/Other VSS L25 Power/Other VSS L26 Power/Other VSS L27 Power/Other VSS L28 Power/Other VSS L29 Power/Other VSS L3 Power/Other VSS L30 Power/Other VSS L6 Power/Other VSS L7 Power/Other VSS M1 Power/Other VSS M7 Power/Other VSS N3 Power/Other VSS N6 Power/Other VSS N7 Power/Other Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction

Land Listing and Signal Descriptions Datasheet 53 VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other VSS P26 Power/Other VSS P27 Power/Other VSS P28 Power/Other VSS P29 Power/Other VSS P30 Power/Other VSS P4 Power/Other VSS P7 Power/Other VSS R2 Power/Other VSS R23 Power/Other VSS R24 Power/Other VSS R25 Power/Other VSS R26 Power/Other VSS R27 Power/Other VSS R28 Power/Other VSS R29 Power/Other VSS R30 Power/Other VSS R5 Power/Other VSS R7 Power/Other VSS T3 Power/Other VSS T6 Power/Other VSS T7 Power/Other VSS U1 Power/Other VSS U7 Power/Other VSS V23 Power/Other VSS V24 Power/Other VSS V25 Power/Other VSS V26 Power/Other VSS V27 Power/Other VSS V28 Power/Other VSS V29 Power/Other VSS V3 Power/Other VSS V30 Power/Other VSS V6 Power/Other VSS V7 Power/Other VSS W4 Power/Other VSS W7 Power/Other Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS Y2 Power/Other VSS Y5 Power/Other VSS Y7 Power/Other VSS_MB_ REGULATION AN6 Power/Other Output VSS_SENSE AN4 Power/Other Output VSSA B23 Power/Other VTT B25 Power/Other VTT B26 Power/Other VTT B27 Power/Other VTT B28 Power/Other VTT B29 Power/Other VTT B30 Power/Other VTT A25 Power/Other VTT A26 Power/Other VTT A27 Power/Other VTT A28 Power/Other VTT A29 Power/Other VTT A30 Power/Other VTT C25 Power/Other VTT C26 Power/Other VTT C27 Power/Other VTT C28 Power/Other VTT C29 Power/Other VTT C30 Power/Other VTT D25 Power/Other VTT D26 Power/Other VTT D27 Power/Other VTT D28 Power/Other VTT D29 Power/Other VTT D30 Power/Other VTT_OUT_LEFT J1 Power/Other Output VTT_OUT_ RIGHT AA1 Power/Other Output VTT_SEL F27 Power/Other Output VTTPWRGD AM6 Power/Other Input Table 23.Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction

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Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction A2 VSS Power/Other A3 RS2# Common Clock Input A4 D2# Source Synch Input/Output A5 D4# Source Synch Input/Output A6 VSS Power/Other A7 D7# Source Synch Input/Output A8 DBI0# Source Synch Input/Output A9 VSS Power/Other A10 D8# Source Synch Input/Output A11 D9# Source Synch Input/Output A12 VSS Power/Other A13 COMP0 Power/Other Input A14 D50# Source Synch Input/Output A15 VSS Power/Other A16 DSTBN3# Source Synch Input/Output A17 D56# Source Synch Input/Output A18 VSS Power/Other A19 D61# Source Synch Input/Output A20 RESERVED A21 VSS Power/Other A22 D62# Source Synch Input/Output A23 VCCA Power/Other A24 VSS Power/Other A25 VTT Power/Other A26 VTT Power/Other A27 VTT Power/Other A28 VTT Power/Other A29 VTT Power/Other A30 VTT Power/Other B1 VSS Power/Other B2 DBSY# Common Clock Input/Output B3 RS0# Common Clock Input B4 D0# Source Synch Input/Output B5 VSS Power/Other B6 D5# Source Synch Input/Output B7 D6# Source Synch Input/Output B8 VSS Power/Other B9 DSTBP0# Source Synch Input/Output B10 D10# Source Synch Input/Output B11 VSS Power/Other B12 D13# Source Synch Input/Output B13 RESERVED B14 VSS Power/Other B15 D53# Source Synch Input/Output B16 D55# Source Synch Input/Output B17 VSS Power/Other B18 D57# Source Synch Input/Output B19 D60# Source Synch Input/Output B20 VSS Power/Other B21 D59# Source Synch Input/Output B22 D63# Source Synch Input/Output B23 VSSA Power/Other B24 VSS Power/Other B25 VTT Power/Other B26 VTT Power/Other B27 VTT Power/Other B28 VTT Power/Other B29 VTT Power/Other B30 VTT Power/Other C1 DRDY# Common Clock Input/Output C2 BNR# Common Clock Input/Output C3 LOCK# Common Clock Input/Output C4 VSS Power/Other C5 D1# Source Synch Input/Output C6 D3# Source Synch Input/Output C7 VSS Power/Other C8 DSTBN0# Source Synch Input/Output C9 RESERVED C10 VSS Power/Other C11 D11# Source Synch Input/Output C12 D14# Source Synch Input/Output C13 VSS Power/Other C14 D52# Source Synch Input/Output C15 D51# Source Synch Input/Output C16 VSS Power/Other C17 DSTBP3# Source Synch Input/Output C18 D54# Source Synch Input/Output C19 VSS Power/Other C20 DBI3# Source Synch Input/Output C21 D58# Source Synch Input/Output Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction

Land Listing and Signal Descriptions Datasheet 55 C22 VSS Power/Other C23 VCCIOPLL Power/Other C24 VSS Power/Other C25 VTT Power/Other C26 VTT Power/Other C27 VTT Power/Other C28 VTT Power/Other C29 VTT Power/Other C30 VTT Power/Other D1 RESERVED D2 ADS# Common Clock Input/Output D3 VSS Power/Other D4 HIT# Common Clock Input/Output D5 VSS Power/Other D6 VSS Power/Other D7 D20# Source Synch Input/Output D8 D12# Source Synch Input/Output D9 VSS Power/Other D10 D22# Source Synch Input/Output D11 D15# Source Synch Input/Output D12 VSS Power/Other D13 D25# Source Synch Input/Output D14 RESERVED D15 VSS Power/Other D16 RESERVED D17 D49# Source Synch Input/Output D18 VSS Power/Other D19 DBI2# Source Synch Input/Output D20 D48# Source Synch Input/Output D21 VSS Power/Other D22 D46# Source Synch Input/Output D23 RESERVED D24 VSS Power/Other D25 VTT Power/Other D26 VTT Power/Other D27 VTT Power/Other D28 VTT Power/Other D29 VTT Power/Other D30 VTT Power/Other E2 VSS Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction E3 TRDY# Common Clock Input E4 HITM# Common Clock Input/Output E5 RESERVED E6 RESERVED E7 RESERVED E8 VSS Power/Other E9 D19# Source Synch Input/Output E10 D21# Source Synch Input/Output E11 VSS Power/Other E12 DSTBP1# Source Synch Input/Output E13 D26# Source Synch Input/Output E14 VSS Power/Other E15 D33# Source Synch Input/Output E16 D34# Source Synch Input/Output E17 VSS Power/Other E18 D39# Source Synch Input/Output E19 D40# Source Synch Input/Output E20 VSS Power/Other E21 D42# Source Synch Input/Output E22 D45# Source Synch Input/Output E23 RESERVED E24 FC17 Power/Other Output E25 VSS Power/Other E26 VSS Power/Other E27 VSS Power/Other E28 VSS Power/Other E29 VSS Power/Other F2 FC5 Common Clock Input F3 BR0# Common Clock Input/Output F4 VSS Power/Other F5 RS1# Common Clock Input F6 IMPSEL Power/Other Input F7 VSS Power/Other F8 D17# Source Synch Input/Output F9 D18# Source Synch Input/Output F10 VSS Power/Other F11 D23# Source Synch Input/Output F12 D24# Source Synch Input/Output F13 VSS Power/Other F14 D28# Source Synch Input/Output Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction

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F15 D30# Source Synch Input/Output F16 VSS Power/Other F17 D37# Source Synch Input/Output F18 D38# Source Synch Input/Output F19 VSS Power/Other F20 D41# Source Synch Input/Output F21 D43# Source Synch Input/Output F22 VSS Power/Other F23 RESERVED F24 TESTHI7 Power/Other Input F25 TESTHI2 Power/Other Input F26 TESTHI0 Power/Other Input F27 VTT_SEL Power/Other Output F28 BCLK0 Clock Input F29 RESERVED G1 VSS Power/Other G2 FC1 Power/Other Input G3 TESTHI8 Power/Other Input G4 TESTHI9 Power/Other Input G5 FC7 Source Synch Output G6 RESERVED G7 DEFER# Common Clock Input G8 BPRI# Common Clock Input G9 D16# Source Synch Input/Output G10 RESERVED G11 DBI1# Source Synch Input/Output G12 DSTBN1# Source Synch Input/Output G13 D27# Source Synch Input/Output G14 D29# Source Synch Input/Output G15 D31# Source Synch Input/Output G16 D32# Source Synch Input/Output G17 D36# Source Synch Input/Output G18 D35# Source Synch Input/Output G19 DSTBP2# Source Synch Input/Output G20 DSTBN2# Source Synch Input/Output G21 D44# Source Synch Input/Output G22 D47# Source Synch Input/Output G23 RESET# Common Clock Input G24 TESTHI6 Power/Other Input G25 TESTHI3 Power/Other Input Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction G26 TESTHI5 Power/Other Input G27 TESTHI4 Power/Other Input G28 BCLK1 Clock Input G29 BSEL0 Power/Other Output G30 BSEL2 Power/Other Output H1 GTLREF0 Power/Other Input H2 GTLREF1 Power/Other Input H3 VSS Power/Other H4 RSP# Common Clock Input H5 TESTHI10 Power/Other Input H6 VSS Power/Other H7 VSS Power/Other H8 VSS Power/Other H9 VSS Power/Other H10 VSS Power/Other H11 VSS Power/Other H12 VSS Power/Other H13 VSS Power/Other H14 VSS Power/Other H15 DP1# Common Clock Input/Output H16 DP2# Common Clock Input/Output H17 VSS Power/Other H18 VSS Power/Other H19 VSS Power/Other H20 VSS Power/Other H21 VSS Power/Other H22 VSS Power/Other H23 VSS Power/Other H24 VSS Power/Other H25 VSS Power/Other H26 VSS Power/Other H27 VSS Power/Other H28 VSS Power/Other H29 FC15 Power/Other Output H30 BSEL1 Power/Other Output J1 VTT_OUT_LEFT Power/Other Output J2 COMP4 Power/Other Input J3 RESERVED J4 VSS Power/Other J5 REQ1# Source Synch Input/Output Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction

Land Listing and Signal Descriptions Datasheet 57 J6 REQ4# Source Synch Input/Output J7 VSS Power/Other J8 VCC Power/Other J9 VCC Power/Other J10 VCC Power/Other J11 VCC Power/Other J12 VCC Power/Other J13 VCC Power/Other J14 VCC Power/Other J15 VCC Power/Other J16 DP0# Common Clock Input/Output J17 DP3# Common Clock Input/Output J18 VCC Power/Other J19 VCC Power/Other J20 VCC Power/Other J21 VCC Power/Other J22 VCC Power/Other J23 VCC Power/Other J24 VCC Power/Other J25 VCC Power/Other J26 VCC Power/Other J27 VCC Power/Other J28 VCC Power/Other J29 VCC Power/Other J30 VCC Power/Other K1 LINT0 Asynch GTL+ Input K2 VSS Power/Other K3 A20M# Asynch GTL+ Input K4 REQ0# Source Synch Input/Output K5 VSS Power/Other K6 REQ3# Source Synch Input/Output K7 VSS Power/Other K8 VCC Power/Other K23 VCC Power/Other K24 VCC Power/Other K25 VCC Power/Other K26 VCC Power/Other K27 VCC Power/Other K28 VCC Power/Other K29 VCC Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction K30 VCC Power/Other L1 LINT1 Asynch GTL+ Input L2 TESTHI13 Asynch GTL+ Input L3 VSS Power/Other L4 A6# Source Synch Input/Output L5 A3# Source Synch Input/Output L6 VSS Power/Other L7 VSS Power/Other L8 VCC Power/Other L23 VSS Power/Other L24 VSS Power/Other L25 VSS Power/Other L26 VSS Power/Other L27 VSS Power/Other L28 VSS Power/Other L29 VSS Power/Other L30 VSS Power/Other M1 VSS Power/Other M2 THERMTRIP# Asynch GTL+ Output M3 STPCLK# Asynch GTL+ Input M4 A7# Source Synch Input/Output M5 A5# Source Synch Input/Output M6 REQ2# Source Synch Input/Output M7 VSS Power/Other M8 VCC Power/Other M23 VCC Power/Other M24 VCC Power/Other M25 VCC Power/Other M26 VCC Power/Other M27 VCC Power/Other M28 VCC Power/Other M29 VCC Power/Other M30 VCC Power/Other N1 PWRGOOD Power/Other Input N2 IGNNE# Asynch GTL+ Input N3 VSS Power/Other N4 RESERVED N5 RESERVED N6 VSS Power/Other N7 VSS Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction

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P1 TESTHI11 Power/Other Input P2 SMI# Asynch GTL+ Input P3 INIT# Asynch GTL+ Input P4 VSS Power/Other P5 RESERVED P6 A4# Source Synch Input/Output P7 VSS Power/Other P8 VCC Power/Other P23 VSS Power/Other P24 VSS Power/Other P25 VSS Power/Other P26 VSS Power/Other P27 VSS Power/Other P28 VSS Power/Other P29 VSS Power/Other P30 VSS Power/Other R1 FC2 Power/Other Input R2 VSS Power/Other R3 FERR#/PBE# Asynch GTL+ Output R4 A8# Source Synch Input/Output R5 VSS Power/Other R6 ADSTB0# Source Synch Input/Output R7 VSS Power/Other R8 VCC Power/Other R23 VSS Power/Other R24 VSS Power/Other R25 VSS Power/Other R26 VSS Power/Other R27 VSS Power/Other R28 VSS Power/Other R29 VSS Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction R30 VSS Power/Other T1 COMP1 Power/Other Input T2 COMP5 Power/Other Input T3 VSS Power/Other T4 A11# Source Synch Input/Output T5 A9# Source Synch Input/Output T6 VSS Power/Other T7 VSS Power/Other T8 VCC Power/Other T23 VCC Power/Other T24 VCC Power/Other T25 VCC Power/Other T26 VCC Power/Other T27 VCC Power/Other T28 VCC Power/Other T29 VCC Power/Other T30 VCC Power/Other U1 VSS Power/Other U2 AP0# Common Clock Input/Output U3 AP1# Common Clock Input/Output U4 A13# Source Synch Input/Output U5 A12# Source Synch Input/Output U6 A10# Source Synch Input/Output U7 VSS Power/Other U8 VCC Power/Other U23 VCC Power/Other U24 VCC Power/Other U25 VCC Power/Other U26 VCC Power/Other U27 VCC Power/Other U28 VCC Power/Other U29 VCC Power/Other U30 VCC Power/Other V1 MSID1 Power/Other Output V2 LL_ID0 Power/Other Output V3 VSS Power/Other V4 A15# Source Synch Input/Output V5 A14# Source Synch Input/Output V6 VSS Power/Other V7 VSS Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction

Land Listing and Signal Descriptions Datasheet 59 V8 VCC Power/Other V23 VSS Power/Other V24 VSS Power/Other V25 VSS Power/Other V26 VSS Power/Other V27 VSS Power/Other V28 VSS Power/Other V29 VSS Power/Other V30 VSS Power/Other W1 MSID0 Power/Other Output W2 TESTHI12 Power/Other Input W3 TESTHI1 Power/Other Input W4 VSS Power/Other W5 A16# Source Synch Input/Output W6 A18# Source Synch Input/Output W7 VSS Power/Other W8 VCC Power/Other W23 VCC Power/Other W24 VCC Power/Other W25 VCC Power/Other W26 VCC Power/Other W27 VCC Power/Other W28 VCC Power/Other W29 VCC Power/Other W30 VCC Power/Other Y1 BOOTSELECT Power/Other Input Y2 VSS Power/Other Y3 RESERVED Y4 A20# Source Synch Input/Output Y5 VSS Power/Other Y6 A19# Source Synch Input/Output Y7 VSS Power/Other Y8 VCC Power/Other Y23 VCC Power/Other Y24 VCC Power/Other Y25 VCC Power/Other Y26 VCC Power/Other Y27 VCC Power/Other Y28 VCC Power/Other Y29 VCC Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction Y30 VCC Power/Other AA1 VTT_OUT_RIG HT Power/Other Output AA2 LL_ID1 Power/Other Output AA3 VSS Power/Other AA4 A21# Source Synch Input/Output AA5 A23# Source Synch Input/Output AA6 VSS Power/Other AA7 VSS Power/Other AA8 VCC Power/Other AA23 VSS Power/Other AA24 VSS Power/Other AA25 VSS Power/Other AA26 VSS Power/Other AA27 VSS Power/Other AA28 VSS Power/Other AA29 VSS Power/Other AA30 VSS Power/Other AB1 VSS Power/Other AB2 IERR# Asynch GTL+ Output AB3 MCERR# Common Clock Input/Output AB4 A26# Source Synch Input/Output AB5 A24# Source Synch Input/Output AB6 A17# Source Synch Input/Output AB7 VSS Power/Other AB8 VCC Power/Other AB23 VSS Power/Other AB24 VSS Power/Other AB25 VSS Power/Other AB26 VSS Power/Other AB27 VSS Power/Other AB28 VSS Power/Other AB29 VSS Power/Other AB30 VSS Power/Other AC1 TMS TAP Input AC2 DBR# Power/Other Output AC3 VSS Power/Other AC4 RESERVED AC5 A25# Source Synch Input/Output AC6 VSS Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction

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AD2 BPM2# Common Clock Input/Output AD3 BINIT# Common Clock Input/Output AD4 VSS Power/Other AD5 ADSTB1# Source Synch Input/Output AD6 A22# Source Synch Input/Output AD7 VSS Power/Other AD8 VCC Power/Other AD23 VCC Power/Other AD24 VCC Power/Other AD25 VCC Power/Other AD26 VCC Power/Other AD27 VCC Power/Other AD28 VCC Power/Other AD29 VCC Power/Other AD30 VCC Power/Other AE1 TCK TAP Input AE2 VSS Power/Other AE3 RESERVED AE4 RESERVED AE5 VSS Power/Other AE6 RESERVED AE7 VSS Power/Other AE8 SKTOCC# Power/Other Output AE9 VCC Power/Other AE10 VSS Power/Other AE11 VCC Power/Other AE12 VCC Power/Other AE13 VSS Power/Other AE14 VCC Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AE15 VCC Power/Other AE16 VSS Power/Other AE17 VSS Power/Other AE18 VCC Power/Other AE19 VCC Power/Other AE20 VSS Power/Other AE21 VCC Power/Other AE22 VCC Power/Other AE23 VCC Power/Other AE24 VSS Power/Other AE25 VSS Power/Other AE26 VSS Power/Other AE27 VSS Power/Other AE28 VSS Power/Other AE29 VSS Power/Other AE30 VSS Power/Other AF1 TDO TAP Output AF2 BPM4# Common Clock Input/Output AF3 VSS Power/Other AF4 A28# Source Synch Input/Output AF5 A27# Source Synch Input/Output AF6 VSS Power/Other AF7 VSS Power/Other AF8 VCC Power/Other AF9 VCC Power/Other AF10 VSS Power/Other AF11 VCC Power/Other AF12 VCC Power/Other AF13 VSS Power/Other AF14 VCC Power/Other AF15 VCC Power/Other AF16 VSS Power/Other AF17 VSS Power/Other AF18 VCC Power/Other AF19 VCC Power/Other AF20 VSS Power/Other AF21 VCC Power/Other AF22 VCC Power/Other AF23 VSS Power/Other AF24 VSS Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction

Land Listing and Signal Descriptions Datasheet 61 AF25 VSS Power/Other AF26 VSS Power/Other AF27 VSS Power/Other AF28 VSS Power/Other AF29 VSS Power/Other AF30 VSS Power/Other AG1 TRST# TAP Input AG2 BPM3# Common Clock Input/Output AG3 BPM5# Common Clock Input/Output AG4 A30# Source Synch Input/Output AG5 A31# Source Synch Input/Output AG6 A29# Source Synch Input/Output AG7 VSS Power/Other AG8 VCC Power/Other AG9 VCC Power/Other AG10 VSS Power/Other AG11 VCC Power/Other AG12 VCC Power/Other AG13 VSS Power/Other AG14 VCC Power/Other AG15 VCC Power/Other AG16 VSS Power/Other AG17 VSS Power/Other AG18 VCC Power/Other AG19 VCC Power/Other AG20 VSS Power/Other AG21 VCC Power/Other AG22 VCC Power/Other AG23 VSS Power/Other AG24 VSS Power/Other AG25 VCC Power/Other AG26 VCC Power/Other AG27 VCC Power/Other AG28 VCC Power/Other AG29 VCC Power/Other AG30 VCC Power/Other AH1 VSS Power/Other AH2 RESERVED AH3 VSS Power/Other AH4 A32# Source Synch Input/Output Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AH5 A33# Source Synch Input/Output AH6 VSS Power/Other AH7 VSS Power/Other AH8 VCC Power/Other AH9 VCC Power/Other AH10 VSS Power/Other AH11 VCC Power/Other AH12 VCC Power/Other AH13 VSS Power/Other AH14 VCC Power/Other AH15 VCC Power/Other AH16 VSS Power/Other AH17 VSS Power/Other AH18 VCC Power/Other AH19 VCC Power/Other AH20 VSS Power/Other AH21 VCC Power/Other AH22 VCC Power/Other AH23 VSS Power/Other AH24 VSS Power/Other AH25 VCC Power/Other AH26 VCC Power/Other AH27 VCC Power/Other AH28 VCC Power/Other AH29 VCC Power/Other AH30 VCC Power/Other AJ1 BPM1# Common Clock Input/Output AJ2 BPM0# Common Clock Input/Output AJ3 ITP_CLK1 TAP Input AJ4 VSS Power/Other AJ5 A34# Source Synch Input/Output AJ6 A35# Source Synch Input/Output AJ7 VSS Power/Other AJ8 VCC Power/Other AJ9 VCC Power/Other AJ10 VSS Power/Other AJ11 VCC Power/Other AJ12 VCC Power/Other AJ13 VSS Power/Other AJ14 VCC Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction

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AK3 ITP_CLK0 TAP Input AK4 VID4 Power/Other Output AK5 VSS Power/Other AK6 FC8 AK7 VSS Power/Other AK8 VCC Power/Other AK9 VCC Power/Other AK10 VSS Power/Other AK11 VCC Power/Other AK12 VCC Power/Other AK13 VSS Power/Other AK14 VCC Power/Other AK15 VCC Power/Other AK16 VSS Power/Other AK17 VSS Power/Other AK18 VCC Power/Other AK19 VCC Power/Other AK20 VSS Power/Other AK21 VCC Power/Other AK22 VCC Power/Other AK23 VSS Power/Other AK24 VSS Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AK25 VCC Power/Other AK26 VCC Power/Other AK27 VSS Power/Other AK28 VSS Power/Other AK29 VSS Power/Other AK30 VSS Power/Other AL1 THERMDA Power/Other AL2 PROCHOT# Asynch GTL+ Input/Output AL3 VSS Power/Other AL4 VID5 Power/Other Output AL5 VID1 Power/Other Output AL6 VID3 Power/Other Output AL7 VSS Power/Other AL8 VCC Power/Other AL9 VCC Power/Other AL10 VSS Power/Other AL11 VCC Power/Other AL12 VCC Power/Other AL13 VSS Power/Other AL14 VCC Power/Other AL15 VCC Power/Other AL16 VSS Power/Other AL17 VSS Power/Other AL18 VCC Power/Other AL19 VCC Power/Other AL20 VSS Power/Other AL21 VCC Power/Other AL22 VCC Power/Other AL23 VSS Power/Other AL24 VSS Power/Other AL25 VCC Power/Other AL26 VCC Power/Other AL27 VSS Power/Other AL28 VSS Power/Other AL29 VCC Power/Other AL30 VCC Power/Other AM1 VSS Power/Other AM2 VID0 Power/Other Output AM3 VID2 Power/Other Output AM4 VSS Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction

Land Listing and Signal Descriptions Datasheet 63 AM5 FC11 Power/Other Output AM6 VTTPWRGD Power/Other Input AM7 FC12 Power/Other Output AM8 VCC Power/Other AM9 VCC Power/Other AM10 VSS Power/Other AM11 VCC Power/Other AM12 VCC Power/Other AM13 VSS Power/Other AM14 VCC Power/Other AM15 VCC Power/Other AM16 VSS Power/Other AM17 VSS Power/Other AM18 VCC Power/Other AM19 VCC Power/Other AM20 VSS Power/Other AM21 VCC Power/Other AM22 VCC Power/Other AM23 VSS Power/Other AM24 VSS Power/Other AM25 VCC Power/Other AM26 VCC Power/Other AM27 VSS Power/Other AM28 VSS Power/Other AM29 VCC Power/Other AM30 VCC Power/Other AN1 VSS Power/Other AN2 VSS Power/Other AN3 VCC_SENSE Power/Other Output AN4 VSS_SENSE Power/Other Output AN5 VCC_MB_ REGULATION Power/Other Output AN6 VSS_MB_ REGULATION Power/Other Output AN7 FC16 Power/Other Output AN8 VCC Power/Other AN9 VCC Power/Other AN10 VSS Power/Other AN11 VCC Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction AN12 VCC Power/Other AN13 VSS Power/Other AN14 VCC Power/Other AN15 VCC Power/Other AN16 VSS Power/Other AN17 VSS Power/Other AN18 VCC Power/Other AN19 VCC Power/Other AN20 VSS Power/Other AN21 VCC Power/Other AN22 VCC Power/Other AN23 VSS Power/Other AN24 VSS Power/Other AN25 VCC Power/Other AN26 VCC Power/Other AN27 VSS Power/Other AN28 VSS Power/Other AN29 VCC Power/Other AN30 VCC Power/Other Table 24.Numerical Land Assignment Land # Land Name Signal Buffer Type Direction

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4.2 Alphabetical Signals Reference

Table 25. Signal Description (Sheet 1 of 9) configuration. See Section 6.1 for more details. Output Write bus transaction. ID match operations associated with the new transaction. with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]#. allows parity to be high when all the covered signals are high.

drive their outputs and latch their inputs. rising edge of BCLK0 crossing VCROSS. condition that prevents reliable future operation. FSB and attempt completion of their bus queue and IOQ entries. the error handling architecture of the system. current bus owner cannot issue any new transactions. appropriate pins/lands of all processor FSB agents. for termination requirements. completed, then releases the bus by de-asserting BPRI#. signal is sampled to determine the agent ID = 0.

66 Datasheet

including termination recommendations refer to Chapter 2. system board using precision resistors. DRDY# to indicate a valid data transfer. data signals correspond to a pair of one DSTBP# and one DSTBN#. group is inverted and therefore sampled active high. signals for that particular sub-phase for that 16-bit group.

connect in the system. DBR# is not a processor signal. clock data transfer, DRDY# may be de-asserted to insert idle clocks. DSTBN[3:0]# are the data strobes used to latch in D[63:0]#. DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.

68 Datasheet

indicates that the processor should be returned to the Normal state. and the CPUID Instruction application note. signal is a logical 0 or logical 1. be continued by reasserting HIT# and HITM# together. for termination requirements. effect when the NE bit in control register 0 (CR0) is set. Output Write bus transaction.

appropriate pins/lands of all processor FSB agents. RESET#, then the processor executes its Built-in Self-Test (BIST). systems where no debug port is implemented on the system board. D processor. Both signals are asynchronous. for the processor. LL_ID[1:0] = 00 for the Celeron D processor. end of the last transaction. the processor FSB, it will wait until it observes LOCK# de-asserted. driven by all processor FSB agents. MCERR# assertion conditions are configurable at a system level.

• Enabled or disabled.
• Asserted, if configured, for in ternal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus transaction after it observes an error.
• Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, refer to the IA-32 Software Developer’s Manual, Volume 3: System Programming Guide.

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775_VR_CONFIG_05A processor will ignore this input. MSID1 must be electrically low for the processor to boot. system de-asserts PROCHOT#. See Section 5.2.3 for more details. before a subsequent rising edge of PWRGOOD. should be driven high throughout boundary scan operation. signal description for a details on parity checking of these signals. asserted for more than 10 ms while PWRGOOD is asserted. configuration options are described in the Section 6.1. terminated on the system board.

being driven by any agent ensuring correct parity. if the processor is present. processor begins program execution from the SMM handler. processor will tri-state its outputs. signals to all processor core units except the FSB and APIC units. STPCLK# is an asynchronous input. (also known as the Test Access Port). provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. Section 2.4 for more details. THERMDA Other Thermal Diode Anode. See Section 5.2.6. THERMDC Other Thermal Diode Cathode. See Section 5.2.6.

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must connect the appropriate pins/lands of all FSB agents. must be driven low during power on Reset. these lands is determined by the VID[5:0] lands. VCCA Input VCCA provides isolated power for the internal processor core PLLs. VCCIOPLL Input VCCIOPLL provides isolated power for internal processor FSB PLLs. the silicon with little noise. 10.1 Design Guide for Desktop Socket 775. by the signals, or disable itself. VSSA Input VSSA is the isolated ground for internal PLLs.

10.1 Design Guide for Desktop Socket 775. VTT Miscellaneous voltage supply. are stable and within specification.

Land Listing and Signal Descriptions

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Thermal Specifications and Design Considerations

5 Thermal Specifications and

5.1 Processor Thermal Specifications

The Celeron D processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting. For more information on designing a component level thermal solution, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on the boxed processor.

5.1.1 Thermal Specifications

To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T specifications when operating at or below the Thermal Design Power (TDP) value listed per frequency in Table 26. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). The Celeron D processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control. Selection of the appropriate fan speed will be based on the temperature reported by the processor’s Thermal Diode. If the diode temperature is greater than or equal to TCONTROL then the processor case temperature must remain at or below the temperature as specified by the thermal profile. If the diode temperature is less than TCONTROL then the case temperature is permitted to exceed the thermal profile, but the diode temperature must remain at or below TCONTROL. Systems that implement fan speed control must be designed to take these conditions in to account. Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications. To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) and the Processor Power Characterization Methodology for the details of this methodology.

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Feature must be enabled for the processor to remain within specification. Table 26. Processor Thermal Specificatio ns for 775_VR_CONFIG_05A Processors

1. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the

maximum power that the processor can dissipate.

1. This table shows the maximum TDP for a given frequenc y range. Individual processors may have a lower TDP.

figure and associated table for the allowed combinations of power and TC. Table 27. Processor Thermal Specificatio ns for 775_VR_CONFIG_06 Processors

1. Thermal Design Power (TDP) should be us ed for processor thermal solution design tar gets. The TDP is not the maximum power

that the processor can dissipate.

1. This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP. Therefore, the max-

allowed combinations of power and TC.

Table 28. Thermal Profile for 775_VR_CONFIG_05A Processors Figure 12. Thermal Profile for 775_VR_CONFIG_05A Processors

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Table 29. Thermal Profile for 775_VR_CONFIG_06 Processors Figure 13. Thermal Profile fo r 775_VR_CONFIG_06 Processors

5.1.2 Thermal Metrology

Guidelines (see Section 1.2).

5.2 Processor Thermal Features

5.2.1 Thermal Monitor

Figure 14. Case Temperature (T

Thermal Specifications and Design Considerations

80 Datasheet

periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.

5.2.2 On-Demand Mode

The Celeron D processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “On-Demand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to reduce system level power consumption. Systems using the Celeron D processor must not rely on software usage of this mechanism to limit the processor temperature. If bit 4 of the ACPI P_CNT Control Register (located in the processor IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI P_CNT Control Register. In On-Demand mode, the duty cycle can be programmed from 12.5% used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode.

5.2.3 PROCHOT# Signal

for specific register and programming details. for thermal protection of system components. bi-directional PROCHOT# feature.

5.2.4 THERMTRIP# Signal

Table 25. THERMTRIP# activation is independent of processor activity and does not

5.2.5 T CONTROL and Fan Speed Reduction

control. Contact your field representative for further details.

5.2.6 Thermal Diode

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1. Intel does not support or re commend operation of the thermal diode under reverse bias.
2. Characterized across a temperature range of 50 - 80 °C.
3. Not 100% tested. Specified by design characterization.
4. The ideality factor, n, represents the deviat ion from ideal diode behavior as exemplified by

and T = absolute temperature (Kelvin).

1. The series resistance, R T, is provided to allow for a more accurate measurement of the
2. Intel does not support or re commend operation of the thermal diode under reverse bias.
3. Characterized across a temperature range of 50 – 80 °C.
4. Not 100% tested. Specified by design characterization.
5. The ideality factor, nQ, represents the deviat ion from ideal transistor model behavior as

(same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin).

1. The series resistance, R T, provided in the Diode Model Table (Table 30) can be used for

more accurate readings as needed. Table 30. Thermal “Diode” Pa rameters using Diode Model Table 31. Thermal “Diode” Parame ters using Transistor Model

containing Thermal Diode Offset data has been added to the Celeron D processor. correct temperatures read by diode based temperature sensing devices. Table 32. Thermal “Diode” n trim and Diode_Correction_Offset Table 33. Thermal Diode Interface

Thermal Specifications and Design Considerations

84 Datasheet

Features

6 Features

6.1 Power-On Configuration Options

Several configuration options can be configured by hardware. The Celeron D processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 34. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.

6.2 Clock Control and Low Power States

The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 15 for a visual representation of the processor low power states. Table 34. Power-On Configuration Option Signals

1. Asserting this signal during RESET# will select the corresponding option.
2. Address signals not identified in this table as configuration options should not be asserted during

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6.2.1 Normal State

This is the normal operating state for the processor.

6.2.2 HALT and Enhanced HALT Powerdown States

The Celeron D processor supports the HALT or Enhanced HALT powerdown state. The Enhanced HALT Powerdown state is configured and enabled via the BIOS. The Enhanced HALT state must be enabled via the BIOS for the processor to remain within its specifications. The Enhanced HALT state is a lower power state as compared to the Stop Grant State. If Enhanced HALT is not enabled, the default Powerdown state entered will be HALT. Refer to the following sections for details about the HALT and Enhanced HALT states. Figure 15. Processor Low Power State Machine

6.2.2.1 HALT Powerdown State

HALT is a low power state entered when all the logical processors have executed the HALT or MWAIT instructions. When one of the logical processors executes the HALT instruction, that logical processor is halted, however, the other processor continues normal operation. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops.

6.2.2.2 Enhanced HALT Powerdown State

Enhanced HALT is a low power state entered when all logical processors have executed the HALT or MWAIT instructions and Enhanced HALT has been enabled via the BIOS. When one of the logical processors executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The processor will automatically transition to a lower frequency and voltage operating point before entering the Enhanced HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID. While in Enhanced HALT state, the processor will process bus snoops. The processor exits the Enhanced HALT state when a break event occurs. When the processor exits the Enhanced HALT state, it will first transition the VID to the original value and then change the bus ratio back to the original value.

6.2.3 Stop Grant State

When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop Grant state. The event will be latched and can be serviced by software upon exit from the Stop Grant state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the de- assertion of the STPCLK# signal. A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 6.2.4).

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While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process a FSB snoop. The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state. If Enhanced HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State, Grant Snoop State and Enhanced HALT Snoop State.

6.2.4.1 HALT Snoop State, Stop Grant Snoop State

The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT Power Down state. During a snoop transaction, the processor enters the HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB). After the snoop is serviced, the processor will return to the Stop Grant state or HALT Power Down state, as appropriate.

6.2.4.2 Enhanced HALT Snoop State

The Enhanced HALT Snoop State is the default Snoop State when the Enhanced HALT state is enabled via the BIOS. The processor will remain in the lower bus ratio and VID operating point of the Enhanced HALT state. While in the Enhanced HALT Snoop State, snoops are handled the same way as in the HALT Snoop State. After the snoop is serviced the processor will return to the Enhanced HALT state. § §

7 Boxed Processor Specifications

particularly important for OEMs that manufacture baseboards for system integrators.

• Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designers’ responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for further guidance. Contact your local Intel Sales Representative for this document. NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.

7.1 Mechanical Specifications

7.1.1 Boxed Processor Coo ling Solution Dimensions

This section documents the mechanical specifications of the boxed Celeron D processor. a mechanical representation of the boxed Celeron D processor. Figure 16. Mechanical Represen tation of the Boxed Processor

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assembled fan heatsink are shown in Figure 17 (Side View), and Figure 18 (Top View). (marked with alphabetic designations) to clarify relative dimensioning.

1. The boxed Celeron D processor in the 775-la nd package cooling solution with clip is

not reflect the final product.

1. Diagram does not show the attached hardware fo r the clip design and is provided only as a

Figure 17. Space Requir ements for the Boxed Processor (Side View: applies to all four Figure 18. Space Requir ements for the Boxed Processor (Top View)

7.1.2 Boxed Processor Fan Heatsink Weight

Section 1.2) for details on the processor weight and heatsink requirements. will ship with the heatsink attach clip assembly.

7.2 Electrical Requirements

7.2.1 Fan Heatsi nk Power Supply

contains specifications for the input and output signals at the fan heatsink connector. the connector labeled as CONTROL. Figure 19. Space Requirements for the Boxed Processor (Overall View)

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does not support variable voltage control or 3-pin PWM control. Figure 20. Boxed Processor Fan Heatsi nk Power Cable Connector Description Table 35. Fan Heatsink Power and Signal Specifications

1. Baseboard should pull this pi n up to 5 V with a resistor.
2. Open Drain Type, Pulse Width Modulated.
3. Fan will have a pull-up resistor to 4.75 V, max 5.25 V.

polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width.

7.3 Thermal Specifications

7.3.1 Boxed Processor Cooling Requirements

for the fan heatsink. The air temperature entering the fan should be kept below 38 °C. responsibility of the system integrator. not capable of keeping regulator components below maximum rated temperatures. Figure 21. Baseboard Power Header Plac ement Relative to Processor Socket

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Figure 22. Boxed Processor Fan Heatsi nk Airspace Keep-out Requirements Figure 23. Boxed Processor Fan Heatsi nk Airspace Keep-out Requirements

Debug Tools Specifications

8 Debug Tools Specifications

8.1 Logic Analyzer Interface (LAI)

Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Celeron D processor systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of Celeron D processor systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a Celeron D processor system that can make use of an LAI: mechanical and electrical.

8.1.1 Mechanical Considerations

The LAI is installed between the processor socket and the Celeron D processor. The LAI lands plug into the processor socket, while the Celeron D processor lands plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the Celeron D processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the Celeron D processor heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI.

8.1.2 Electrical Considerations

The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides. § §