M29W040 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 31
Technical content
Figure 1. Logic Diagram
4 Mbit (512Kb x8, Uniform Block)
20 YEARS DATA RETENTION
Table 1. Signal Names This is information on a product still in productionbut not recommended for new designs.
E DQ5 DQ1 DQ2 DQ3 DQ4 DQ6 A17 W A16 A12 A18 VCC A15 AI02076 M29W040 (Normal) 16 17 VSS Figure 2B. TSOP Pin Connections AI02075 A17 A13 A10 DQ5 DQ0 DQ1 DQ2 DQ3 DQ4 W
1 A16
32 A18
G E VSS Figure 2A. LCC Pin Connections DQ0 A4A3 A13 A10 DQ7 A14 A11G E DQ5 DQ1 DQ2 DQ3 DQ4 DQ6 A17 W A16 A12 A18 VCC A15 AI02077 M29W040 (Reverse) 16 17 VSS Figure 2C. TSOP Reverse Pin Connections DESCRIPTION The M29W040 is a non-volatile memory that may be erased electrically at the block level, and pro- grammed Byte-by-Byte. The interface is directly compatible with most mi- croprocessors. PLCC32, TSOP32(8 x 20mm)and TSOP32 (8 x 14mm) packages are available. Both normal and reverse pin outs are available for the TSOP32 (8 x 20mm) package. Organisation The FlashMemoryorganisationis 512Kx8 bitswith Address lines A0-A18 and Data Inputs/Outputs DQ0-DQ7. Memory control is provided by Chip Enable, Output Enable and Write Enable Inputs. Erase and Program are performed through the internal Program/Erase Controller (P/E.C.). Data Outputs bits DQ7 and DQ6 provide polling or toggle signals during Automatic Program or Erase to indicate the Ready/Busy state of the internal Program/Erase Controller. Memory Blocks Erasure of the memory is in blocks. There are 8 uniform blocks of 64 Kbytes each in the memory address space. Each block can be programmed and erased over 100,000 cycles. Each uniform M29W040
- Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
Table 2. Absolute Maximum Ratings(1) blocks of the memory, and then resumed. mand Interface which is common to all P/E.C. command instruction to the Command Interface. tion or the addressed data for Read operations.
Table 3. Operations Table 4. Electronic Signature Table 5. Block Protection Status the block addressed by A16, A17, A18. ID during Block Unprotect operations. Block Protect and Block Unprotect operations. Command Registerand Addressand Data latches. Data Inputs are latched on the rising edge of W. operations(Read, Program and Erase).
Read Memory Array until a new write cycle is initiated. write cycle is initiated. See Note 4. cycle is initiated. See Note 5. uniform block(s) not being erased then Resume Erase. Notes:1. Command not interpreted in this table will default to read array mode.
- The first cycle of the RST,RBP or RSIG instruction is followed by read operations to read memory array,Status Register or
Electronic Signature codes. Any number of read cycles can occur after one command cycle.
- Signature Address bits A0, A1, A6 at V
- Protection Address: A0, A6 at VIL,A 1a tVIH and A16, A17, A18 within the uniform block to be checked, will output the
- Address bits A15-A18 are don’t care for coded address inputs.
- Optional, additional blocks addresses must be entered within a 80µs delay after last write entry, timeout status can be verified
through DQ3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
- Read Data Polling or Toggle bit until Erase completes.
- A wait time of 5µs is necessary after a Reset command, if the memory is in a Block Erase or Power Down status, before
- Writing an RST command to the P/E.C. is mandatory prior to any new operation when the memory is in Power Down mode.
Table 6. Instructions(1)
Figure 3. The memory array is divided in 8 uniform other block, and then resumed. Block Protection provides additional data security. RST and RSIG, and Status Bits). on the falling edge of W or E whicheveroccurs last. edge of W or E whichever occurs first. CC6 (typically less than 1.0µA). are ignored. The codes are output on DQ0-DQ7.
Figure 3. Memory Map and Block Address Table Table 7. CommandsBlock Protection.Each uniform block can be separately protected against Program or Erase. ID and the block address is applied on A16-A18. ILwhile W is at VIH and A9 at VID. Protection Status is shown in Table 5.
is again preceeded by the two coded cycles.
7 Data
6 Toggle Bit
3 Erase
2 Reserved
1 Reserved
0 Reserved
Note: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. Table 8. Status Register DQ6, or Error on DQ5 and Erase Timer DQ3 bits. plement of the bit being programmed on DQ7.
Symbol Alt Parameter Test Condition M29W040 Unit-100 -120 VCC = 3.3V±0.3V C L = 30pF VCC = 3.3V±0.3V Min Max Min Max tAVAV tRC Address Valid to Next Address Valid E = VIL,G=V IL 100 120 ns tAVQV tACC Address Valid to Output Valid E = V IL,G=V IL 100 120 ns tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL 00 n s tELQV (2) tCE Chip Enable Low to Output Valid G = V IL 100 120 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E=V IL 00 n s tGLQV (2) tOE Output Enable Low to Output Valid E = V IL 40 50 ns tEHQX tOH Chip Enable High to Output Transition G=V IL 00 n s tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = V IL 20 30 ns tGHQX tOH Output Enable High to Output Transition E=V IL 00 n s tGHQZ (1) tDF Output Enable High to Output Hi-Z E = V IL 20 30 ns tAXQX tOH Address Transition to Output Transition E=V IL,G=V IL 00 n s Notes:1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV -tGLQV after the falling edge of E without increasing tELQV . Table 12A. Read AC Characteristics A = 0 to 70°C, –20 to 85°C or –40 to 85°C) Toggle bit (DQ6).When Programming operations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will toggle following toggling of either G or E when G is low. The operation is completed when two successive reads yield the same output data. The next read will output the bit last programmed or a ’1’ after erasing. The togglebit is validonly effective during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. If the byte to be programmed belongs to a protected block the command will be ignored. If the blocks selected for erasure are protected, DQ6 will toggle for about 100µs and then return back to Read. See Figure 11 for Toggle Bit flowchart and Figure 12 for Toggle Bit waveforms. Error bit (DQ5).This bit is set to ’1’ by the P/E.C when there is a failure of byte programming, block erase, or chip erase that results in invalid data being programmedin the memory block. In case of error in block erase or byte program, the block in which the error occured or to which the pro- grammed byte belongs, must be discarded. Other blocksmay still be used.Error bit resetsafter Reset (RST) instruction. In case of success, the error bit will set to ’0’ during Program or Erase and to valid data after write operation is completed. Erase Timer bit (DQ3).This bit is set to ’0’ by the P/E.C. when the last Block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the erase timeout period is finished, after 80 to 120µs, DQ3 returns back to ’1’. Coded Cycles.The two coded cycles unlock the Command Interface. They are followed by a com- mand input or a comand confirmation. The coded cycles consist of writing the data AAh at address 5555hduring thefirstcycleand data55hat address 2AAAh during the second cycle. Addresses are latched on the falling edge of W or E while data is latched on the rising edge of W or E. The coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles. M29W040
Symbol Alt Parameter Test Condition M29W040 Unit-150 -200 VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V Min Max Min Max tAVAV tRC Address Valid to Next Address Valid E=V IL,G=V IL 150 200 ns tAVQV tACC Address Valid to Output Valid E = VIL,G=V IL 150 200 ns tELQX (1) tLZ Chip Enable Low to Output Transition G=V IL 00 n s tELQV (2) tCE Chip Enable Low to Output Valid G = VIL 150 200 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E=V IL 00 n s tGLQV (2) tOE Output Enable Low to Output Valid E=V IL 55 70 ns tEHQX tOH Chip Enable High to Output Transition G=V IL 00 n s tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL 40 50 ns tGHQX tOH Output Enable High to Output Transition E=V IL 00 n s tGHQZ (1) tDF Output Enable High to Output Hi-Z E=V IL 40 50 ns tAXQX tOH Address Transition to Output Transition E=V IL,G=V IL 00 n s Notes:1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV -tGLQV after the falling edge of E without increasing tELQV . Table 12B. Read AC Characteristics A = 0 to 70°C, –20 to 85°C or –40 to 85°C) Read Array/Reset (RST) instruction.The Reset instruction consists of one write operation giving the command F0h. It can be optionally preceded by the two coded cycles. A wait state of 5µs before read operationsis necessaryif theReset command is applied during an Erase or Power Down opera- tion. Read Electronic Signature (RSIG) instruction. This instructionuses the two codedcyclesfollowed by one write cycle giving the command 90h to address 5555h for command setup. A subsequent read will output the manufacturer code, the device code or the Block Protection status depending on the levels of A0, A1, A6, A16, A17 and A18. The manufacturer code, 20h, is output when the ad- dresses lines A0, A1 and A6 are Low, the device code, E2h is output when A0 is High with A1 and A6 Low. Read Block Protection (RBP) instruction.The use of ReadElectronicSignature(RSIG) command also allows access to the Block Protection status verify. After giving the RSIG command, A0 and A6 are set to V IL with A1 at VIH, while A16, A17 and A18 define the block of the block to be verified. A read in these conditions will output a 01h if block is protected and a 00h if block is not protected. This Read Block Protection is the only valid way to check the protection status of a block. Neverthe- less, it mustnot be used during the blockprotection phase as a method to verify the Block Protection. Please refer to Block Protection paragraph. Power Down (PD) instruction.The Power Down instruction uses one write cycle to put the memory into a power down mode where current consump- tion is typically reduced to less than 1.0µA. Once in this state, a Reset (RST) command must be written to the P/E.C. prior to any operation. M29W040
Figure 6. Read Mode AC Waveforms
VCC = 3.3V±0.3V C L = 30pF VCC = 3.3V±0.3V Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 100 120 ns tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns tWLWH tWP Write Enable Low to Write Enable High 45 50 ns tDVWH tDS Input Valid to Write Enable High 45 50 ns tWHDX tDH Write Enable High to Input Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low 25 30 ns tAVWL tAS Address Valid to Write Enable Low 0 0 ns tWLAX tAH Write Enable Low to Address Transition 45 50 ns tGHWL Output Enable High to Write Enable Low 0 0 ns tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs tWHQV1 (1) Write Enable High to Output Valid (Program) 12 12 µs tWHQV2 (1) Write Enable High to Output Valid (Block Erase) 1.5 30 1.5 30 sec tWHGL tOEH Write Enable High to Output Enable Low 0 0 ns Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV =tWHQ7V +t Q7VQV . Table 13A. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) Chip Erase(CE) instruction.This instructionuses six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two coded cycles. The Chip Erase Confirm com- mand 10h is writtenat address5555h on sixthcycle after another two coded cycles. If the second com- mand given is not an erase confirm or if the coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessaryto program the array with 00h first as the P/E.C. will automatically do this before erasing to FFh. Read operations after the sixth rising edge of W or E output the status register bits. During the execu- tion of the erase by the P/E.C. the memory will not accept any instruction. Read of DataPolling bit DQ7 returns’0’, then ’1’ on completion. The Toggle Bit DQ6 toggles during erase operation and stops when erase is com- pleted. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure because the erasure has not been verified even after the maximum number of erase cycles have been executed. M29W040
VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V Min Max Min Max tAV AV tWC Address Valid to Next Address Valid 150 200 ns tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns tWLWH tWP Write Enable Low to Write Enable High 65 80 ns tDVWH tDS Input Valid to Write Enable High 65 80 ns tWHDX tDH Write Enable High to Input Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low 35 35 ns tAVWL tAS Address Valid to Write Enable Low 0 0 ns tWLAX tAH Write Enable Low to Address Transition 65 65 ns tGHWL Output Enable High to Write Enable Low 0 0 ns tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs tWHQV1 (1) Write Enable High to Output Valid (Program) 12 12 µs tWHQV2 (1) Write Enable High to Output Valid (Block Erase) 1.5 30 1.5 30 sec tWHGL tOEH Write Enable High to Output Enable Low 0 0 ns Note: 1. Time is measured to Data Polling or ToggleBit, tWHQV =tWHQ7V +t Q7VQV . Table 13B. Write AC Characteristics,Write Enable Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) Block Erase (BE) instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 5555h on thirdcycle after the two coded cycles.The Block Erase Confirm command 30h is written on sixth cycle after another two coded cycles. During the input of the second command an address within the block to be erasedis given and latched into the memory. Additional Block Erase confirm com- mands and block addresses can be written sub- sequently to erase other blocks in parallel, without further coded cycles. The erase will start after the Erase timeout period (see Erase Timer Bit DQ3 description). Thus, additional Block Erase com- mands mustbe given within this delay.The input of a newBlockErasecommandwill restartthetimeout period. The status of the internal timer can be monitoredthrough the levelof DQ3, if DQ3 is ’0’ the Block Erase Command has been given and the timeout is running, if DQ3 is ’1’, the timeout has expired and the P/E.C is erasing the block(s). During Erase timeout, any command different from 30h will abort the instruction and reset the device to read array mode. It is not necessary to program the block with 00h as the P/E.C. will do this auto- matically before erasing to FFh. Read operations after the sixth rising edge of W or E output the status register bits. Duringthe executionof the erase by the P/E.C.,the memoryaccepts onlythe ES(Erase Suspend)and RST (Reset) instructions. Data Polling bit DQ7 returns ’0’ while the erasure is in progress and ’1’ when it has completed.The ToggleBit DQ6 toggles during the erase operation. It stops when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure because erasure has not completed even after the maximum number of erase cycles have been executed. In this case, it will be necessary to input a Reset (RST) to the command interface in order to reset the P/E.C. M29W040
Figure 7. Write AC Waveforms, W Controlled Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W. a checkof the statusof the programmingoperation. to suspending the erase, terminate the timeout. The ToggleBit DQ6 stops togglingwhen the P/E.C. data, Read from block not being erased is valid.
VCC = 3.3V±0.3V C L = 30pF VCC = 3.3V±0.3V Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 100 120 ns tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High 45 50 ns tDVEH tDS Input Valid to Chip Enable High 45 50 ns tEHDX tDH Chip Enable High to Input Transition 0 0 ns tEHWH tWH Chip Enable High to Write Enable High 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low 25 30 ns tAVEL tAS Address Valid to Chip Enable Low 0 0 ns tELAX tAH Chip Enable Low to Address Transition 45 50 ns tGHEL Output Enable High Chip Enable Low 0 0 ns tVCHWL tVCS VCC High to Write Enable Low 50 50 µs tEHQV1 (1) Chip Enable High to Output Valid (Program) 12 12 µs tEHQV2 (1) Chip Enable High to Output Valid (Block Erase) 1.5 30 1.5 30 sec tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns Note: 1. Time is measured to Data Polling or ToggleBit, tWHQV =tWHQ7V +t Q7VQV . Table 14A. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) Power Up The memoryCommandInterfaceis reseton power up to Read Array. Either E or W must be tied to VIH during Power-up to allow maximum security and the possibility to write a command on the first rising adge of E or W. Anywrite cycle initiation is blocked when V CC is below VLKO . Supply Rails Normal precautions must be taken for supply volt- age decoupling, each device in a system should havethe VCC rail decoupledwith a 1.0µF capacitor close to the VCC and V SS pins. The PCB trace widths should be sufficient to carry the VCC pro- gram and erase currents required. M29W040
VCC = 2.7V to 3.6V VCC = 2.7V to 3.6V Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 150 200 ns tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High 65 80 ns tDVEH tDS Input Valid to Chip Enable High 65 80 ns tEHDX tDH Chip Enable High to Input Transition 0 0 ns tEHWH tWH Chip Enable High to Write Enable High 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low 35 35 ns tAVEL tAS Address Valid to Chip Enable Low 0 0 ns tELAX tAH Chip Enable Low to Address Transition 65 65 ns tGHEL Output Enable High Chip Enable Low 0 0 ns tVCHWL tVCS VCC High to Write Enable Low 50 50 µs tEHQV1 (1) Chip Enable High to Output Valid (Program) 12 12 µs tEHQV2 (1) Chip Enable High to Output Valid (Block Erase) 1.5 30 1.5 30 sec tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV =tWHQ7V +t Q7VQV . Table 14B. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W040
Figure 8. Write AC Waveforms, E Controlled Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.
VCC = 3.3V±0.3V C L = 30pF VCC = 3.3V±0.3V Min Max Min Max tWHQ7V1 (2) Write Enable High to DQ7 Valid (Program, W Controlled) 12 12 µs tWHQ7V2 (2) Write Enable High to DQ7 Valid (Block Erase, W Controlled) 1.5 30 1.5 30 sec tEHQ7V1 (2) Chip Enable High to DQ7 Valid (Program, E Controlled) 12 12 µs tEHQ7V2 (2) Chip Enable High to DQ7 Valid (Block Erase, E Controlled) 1.5 30 1.5 30 sec tQ7VQV Q7 Valid to Output Valid (Data Polling) 45 50 ns tWHQV1 Write Enable High to Output Valid (Program) 12 12 µs tWHQV2 Write Enable High to Output Valid (Block Erase) 1.5 30 1.5 30 sec tEHQV1 Chip Enable High to Output Valid (Program) 12 12 µs tEHQV2 Chip Enable High to Output Valid (Block Erase) 1.5 30 1.5 30 sec Notes:1. All other timings are defined in Read AC Characteristics table. 2. tWHQ7V is the Program or Erase time. Table 15A. Data Polling and Toggle Bit AC Characteristics(1) (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W040
VCC = 2.7V to 3.6V V CC = 2.7V to 3.6V Min Max Min Max tWHQ7V1 (2) Write Enable High to DQ7 Valid (Program, W Controlled) 12 12 µs tWHQ7V2 (2) Write Enable High to DQ7 Valid (Block Erase, W Controlled) 1.5 30 1.5 30 sec tEHQ7V1 (2) Chip Enable High to DQ7 Valid (Program, E Controlled) 12 12 µs tEHQ7V2 (2) Chip Enable High to DQ7 Valid (Block Erase, E Controlled) 1.5 30 1.5 30 sec tQ7VQV Q7 Valid to Output Valid (Data Polling) 55 70 ns tWHQV1 Write Enable High to Output Valid (Program) 12 12 µs tWHQV2 Write Enable High to Output Valid (Block Erase) 1.5 30 1.5 30 sec tEHQV1 Chip Enable High to Output Valid (Program) 12 12 µs tEHQV2 Chip Enable High to Output Valid (Block Erase) 1.5 30 1.5 30 sec Notes:1. All other timings are defined in Read AC Characteristics table. 2. tWHQ7V is the Program or Erase time. Table 15B. Data Polling and Toggle Bit AC Characteristics(1) (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W040
Figure 9. Data Polling DQ7 AC Waveforms Notes:1. All other timings are as a normal Read cycle.
- DQ7 and DQ0-DQ6 can transmit to valid at any point during the data output valid period.
- tWHQ7V is the Program or Erase time.
- During erasing operation Byte address must be within Block being erased.
Figure 12. Data Toggle DQ6 AC Waveforms Note: All other timings are as a normal Read cycle.
Figure 13. Block Protection Flowchart
Figure 14. Block Unprotecting Flowchart reads, A6 must be kept at VIL.
ORDERING INFORMATION SCHEME Note: 1. This speed is obtained with a supply voltage range of VCC = 3.3V ± 0.3V and a load capacitance at 30pF . M29W040 is replaced by the new version M29W040B Device are shipped from the factory with the memory content erased (to FFh). For a list of availableoptions(Speed, Package,etc...) or for furtherinformationon any aspect of thisdevice, please contact the STMicroelectronics Sales Office nearest to you. Operating Voltage W 2.7V to 3.6V Speed -100(1) 100ns -120 120ns -150 150ns -200 200ns Package K PLCC32 N TSOP32 8 x 20mm NZ TSOP32 8 x 14mm Temp. Range 1 0 to 70 °C 5 –20 to 85 °C 6 –40 to 85 °C Option R Reverse Pinout TR Tape & Reel Packing Example: M29W040 -120 N 1 TR M29W040
D Ne E1 E Nd CP B D2/E2 e A R 0.51 (.020) 1.14 (.045) F Symb mm inches Typ Min Max Typ Min Max A 2.54 3.56 0.100 0.140 A1 1.52 2.41 0.060 0.095 A2 – 0.38 – 0.015 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 F 0.00 0.25 0.000 0.010 N3 2 3 2 Nd 7 7 Ne 9 9 CP 0.10 0.004 Drawing is not to scale. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular M29W040
E CP B e A N/2 D DIE C LA1 α Symb mm inches Typ Min Max Typ Min Max A 1.20 0.047 A1 0.05 0.15 0.002 0.007 A2 0.95 1.05 0.037 0.041 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 7.90 8.10 0.311 0.319 L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N3 2 3 2 CP 0.10 0.004 Drawing is not to scale. TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm M29W040
E CP B e A N/2 D DIE C LA1 α Symb mm inches Typ Min Max Typ Min Max A 1.20 0.047 A1 0.05 0.17 0.002 0.006 A2 0.95 1.05 0.037 0.041 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 7.90 8.10 0.311 0.319 L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N3 2 3 2 CP 0.10 0.004 Drawing is not to scale. TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm M29W040
E CP B e A N/2 D DIE C LA1 α Drawing is not to scale. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14mm Symb mm inches Typ Min Max Typ Min Max A 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 B 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 13.80 14.20 0.543 0.559 D1 12.30 12.50 0.484 0.492 E 7.90 8.10 0.311 0.319 L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N3 2 3 2 CP 0.10 0.004 M29W040
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland- France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com M29W040