MX29SL800CT MCNIX | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 64

Technical content

P/N:PM1224 MX29SL800C T/B 8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE 1.8V ONLY FLASH MEMORY

  • Ready/Busy# pin (RY/BY#) - Provides a hardware method of detecting program or erase operation completion  Hardware reset pin (RESET#) - Hardware method to reset the device to reading array data  Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Temporary sector unprotected allows code changes in previously locked sectors  CFI (Common Flash Interface) compliant - Flash device parameters stored on the device and provide the host system to access  100,000 minimum erase/program cycles  Latch-up protected to 100mA from -1V to VCC+1V  Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector  Package type: - 48-pin TSOP - 48-ball CSP - All Pb-free devices are RoHS Compliant  Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash  10 years data retention

FEATURES

 Extended single - supply voltage range 1.65V to 2.2V  1,048,576 x 8/524,288 x 16 switchable  Single power supply operation - 1.8V only operation for read, erase and program operation  Fast access time: 90ns  Low power consumption - 12mA maximum active current (10MHz) - 1uA typical standby current  Command register architecture - Byte/word Programming (12us/18us typical) - Sector Erase (Sector structure 16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)  Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically program and verify data at specified address  Erase suspend/Erase Resume - Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase  Status Reply - Data# polling & Toggle bit for detection of program and erase operation completion GENERAL DESCRIPTION The MX29SL800C T/B is a 8-mega bit Flash memory organized as 1M bytes of 8 bits or 512K words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29SL800C T/B is packaged in 48-pin TSOP and 48-ball CSP . It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29SL800C T/B offers access time as fast as 90ns, allowing operation of high-speed micropro- cessors without wait states. To eliminate bus conten- tion, the MX29SL800C T/B has separate chip enable (CE#) and output enable (OE#) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29SL800C T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maxi- mum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy- cling. The MX29SL800C T/B uses a 1.65V~2.2V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro- tection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V. REV. 1.0, APR. 20, 2006

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 PIN CONFIGURATIONS

48 TSOP (Standard Type) (12mm x 20mm)

A0~A18 Address Input Q0~Q14 Data Input/Output Q15/A-1 Q15 (data input/output, word mode)/ A-1(LSB address input, byte mode) CE# Chip Enable Input WE# Write Enable Input BYTE# Word/Byte Selection input RESET# Hardware Reset Pin OE# Output Enable Input RY/BY# Ready/Busy Output VCC Power Supply Pin (1.65V~2.2V) GND Ground Pin A15 A14 A13 A12 A11 A10 NC NC WE# RESET# NC NC RY/BY# A18 A17 A16 BYTE# GND Q15/A-1 Q14 Q13 Q12 VCC Q11 Q10 OE# GND CE# MX29SL800C T/B 48-Ball CSP( Ball Pitch = 0.5 mm), Top View, Balls Facing Down A B CDEF H GJ CE# GND KL OE# A18 Q10 NC NC Q2 Q3 VCC Q12 NC NC Q13 A10 A2 A4 A6 A17 NC NC WE# NC A9 Q14 A13 A11 A12 Q11 Q15 A14 A15 A16 GND

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 48-Ball CSP( Ball Pitch = 0.8 mm), Top View, Balls Facing Down AB C D E F G H WE# RY/BY# RE- SET# NC A17 A10 NC A18 A11 NC NC Q14 Q12 Q10 CE# Q13 VCC Q11 OE# GND A13 A12 A14 A15 A16 BYTE# Q15/ A-1 GND

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 BLOCK STRUCTURE TABLE 1: MX29SL800CT SECTOR ARCHITECTURE Note: Byte mode:address range A18:A-1, word mode:address range A18:A0. Sector Sector Size Address range Sector Address Byte Mode Word Mode Byte Mode (x8) Word Mode (x16) A18 A17 A16 A15 A14 A13 A12 SA0 64Kbytes 32Kwords 00000h-0FFFFh 00000h-07FFFh 0000XX X SA1 64Kbytes 32Kwords 10000h-1FFFFh 08000h-0FFFFh 0001XX X SA2 64Kbytes 32Kwords 20000h-2FFFFh 10000h-17FFFh 0010XX X SA3 64Kbytes 32Kwords 30000h-3FFFFh 18000h-1FFFFh 0011XX X SA4 64Kbytes 32Kwords 40000h-4FFFFh 20000h-27FFFh 0100XX X SA5 64Kbytes 32Kwords 50000h-5FFFFh 28000h-2FFFFh 0101XX X SA6 64Kbytes 32Kwords 60000h-6FFFFh 30000h-37FFFh 0110XX X SA7 64Kbytes 32Kwords 70000h-7FFFFh 38000h-3FFFFh 0111XX X SA8 64Kbytes 32Kwords 80000h-8FFFFh 40000h-47FFFh 1000XX X SA9 64Kbytes 32Kwords 90000h-9FFFFh 48000h-4FFFFh 1001XX X SA10 64Kbytes 32Kwords A0000h-AFFFFh 50000h-57FFFh 1010XX X SA11 64Kbytes 32Kwords B0000h-BFFFFh 58000h-5FFFFh 1011XX X SA12 64Kbytes 32Kwords C0000h-CFFFFh 60000h-67FFFh 1100XX X SA13 64Kbytes 32Kwords D0000h-DFFFFh 68000h-6FFFFh 1101XX X SA14 64Kbytes 32Kwords E0000h-EFFFFh 70000h-77FFFh 1110XX X SA15 32Kbytes 16Kwords F0000h-F7FFFh 78000h-7BFFFh 11110X X SA16 8Kbytes 4Kwords F8000h-F9FFFh 7C000h-7CFFFh 111110 0 SA17 8Kbytes 4Kwords FA000h-FBFFFh 7D000h-7DFFFh 111110 1 SA18 16Kbytes 8Kwords FC000h-FFFFFh 7E000h-7FFFFh 111111 X

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 Sector Sector Size Address range Sector Address Byte Mode Word Mode Byte Mode (x8) Word Mode (x16) A18 A17 A16 A15 A14 A13 A12 SA0 16Kbytes 8Kwords 00000h-03FFFh 00000h-01FFFh 000000 X SA1 8Kbytes 4Kwords 04000h-05FFFh 02000h-02FFFh 000001 0 SA2 8Kbytes 4Kwords 06000h-07FFFh 03000h-03FFFh 000001 1 SA3 32Kbytes 16Kwords 08000h-0FFFFh 04000h-07FFFh 00001X X SA4 64Kbytes 32Kwords 10000h-1FFFFh 08000h-0FFFFh 0001XX X SA5 64Kbytes 32Kwords 20000h-2FFFFh 10000h-17FFFh 0010XX X SA6 64Kbytes 32Kwords 30000h-3FFFFh 18000h-1FFFFh 0011XX X SA7 64Kbytes 32Kwords 40000h-4FFFFh 20000h-27FFFh 0100XX X SA8 64Kbytes 32Kwords 50000h-5FFFFh 28000h-2FFFFh 0101XX X SA9 64Kbytes 32Kwords 60000h-6FFFFh 30000h-37FFFh 0110XX X SA10 64Kbytes 32Kwords 70000h-7FFFFh 38000h-3FFFFh 0111XX X SA11 64Kbytes 32Kwords 80000h-8FFFFh 40000h-47FFFh 1000XX X SA12 64Kbytes 32Kwords 90000h-9FFFFh 48000h-4FFFFh 1001XX X SA13 64Kbytes 32Kwords A0000h-AFFFFh 50000h-57FFFh 1010XX X SA14 64Kbytes 32Kwords B0000h-BFFFFh 58000h-5FFFFh 1011XX X SA15 64Kbytes 32Kwords C0000h-CFFFFh 60000h-67FFFh 1100XX X SA16 64Kbytes 32Kwords D0000h-DFFFFh 68000h-6FFFFh 1101XX X SA17 64Kbytes 32Kwords E0000h-EFFFFh 70000h-77FFFh 1110XX X SA18 64Kbytes 32Kwords F0000h-FFFFFh 78000h-7FFFFh 1111XX X TABLE 2: MX29SL800CB SECTOR ARCHITECTURE Note: Byte mode:address range A18:A-1, word mode:address range A18:A0.

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 BLOCK DIAGRAM CONTROL INPUT LOGIC PROGRAM/ERASE HIGH VOLTAGE WRITE STATE MACHINE (WSM) STATE REGISTER FLASH ARRAY X-DECODER ADDRESS LATCH AND BUFFER Y -PASS GATE Y -DECODER ARRAY SOURCE HV COMMAND DATA DECODER COMMAND DATA LATCH I/O BUFFER PGM DATA HV PROGRAM DATA LATCH SENSE AMPLIFIER Q0-Q15/A-1 A0-A18 CE# OE# WE# RESET#

gram verification, and counts the number of sequences. information on these status bits. according to MXIC's Automatic Chip Erase algorithm. controlled internally within the device. multiple sectors, or the entire device. status of the erasing operation. the rising edge of WE# or CE#, whichever happens first. ter to respond to its full command set. vice to be programmed with its programming algorithm. Table 3. In addition, to access the automatic select codes

TABLE 3. MX29SL800C T/B AUTO SELECT MODE OPERATION

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX29SL800C T/B is capable of operating in the CFI mode. This mode all the host system to determine the manu- facturer of the device such as operating parameters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in Table 6. The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Read ID mode; however, it is ig- nored otherwise. The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode. The command is valid only when the device is in the CFI mode. TABLE 4-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Address Address Data (Byte Mode) (Word Mode) Query-unique ASCII string "QRY" 20 10 0051 22 11 0052 24 12 0059 Primary vendor command set and control interface ID code 26 13 0002 28 14 0000 Address for primary algorithm extended query table 2A 15 0040 2C 16 0000 Alternate vendor command set and control interface ID code (none) 2E 17 0000 30 18 0000 Address for secondary algorithm extended query table (none) 32 19 0000 34 1A 0000 TABLE 4-2. CFI Mode: System Interface Data Values (All values in these tables are in hexadecimal) Description Address Address Data (Byte Mode) (Word Mode) VCC supply, minimum (1.65V) 36 1B 0016 VCC supply, maximum (2.2V) 38 1C 0022 VPP supply, minimum (none) 3A 1D 0000 VPP supply, maximum (none) 3C 1E 0000 Typical timeout for single word/byte write (2N us) 3E 1F 0004 Typical timeout for Minimum size buffer write (2N us) 40 20 0000 Typical timeout for individual block erase (2N ms) 42 21 000A Typical timeout for full chip erase (2N ms) 44 22 0000 Maximum timeout for single word/byte write times (2N X Typ) 46 23 0005 Maximum timeout for buffer write times (2N X Typ) 48 24 0000 Maximum timeout for individual block erase times (2N X Typ) 4A 25 0004 Maximum timeout for full chip erase times (not supported) 4C 26 0000

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 TABLE 4-3. CFI Mode: Device Geometry Data Values (All values in these tables are in hexadecimal) Description Address Address Data (Byte Mode) (Word Mode) Device size (2N bytes) 4E 27 0014 Flash device interface code (refer to the CFI publication 100) 50 28 0002 52 29 0000 Maximum number of bytes in multi-byte write (not supported) 54 2A 0000 56 2B 0000 Number of erase block regions 58 2C 0004 Erase block region 1 information (refer to the CFI publication 100) 5A 2D 0000 5C 2E 0000 5E 2F 0040 60 30 0000 Erase block region 2 information 62 31 0001 64 32 0000 66 33 0020 68 34 0000 Erase block region 3 information 6A 35 0000 6C 36 0000 6E 37 0080 70 38 0000 Erase block region 4 information 72 39 000E 74 3A 0000 76 3B 0000 78 3C 0001 TABLE 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values (All values in these tables are in hexadecimal) Description Address Address Data (Byte Mode) (Word Mode) Query-unique ASCII string "PRI" 80 40 0050 82 41 0052 84 42 0049 Major version number, ASCII 86 43 0031 Minor version number, ASCII 88 44 0030 Address sensitive unlock (0=required, 1= not required) 8A 45 0000 Erase suspend (2= to read and write) 8C 46 0002 Sector protect (N= # of sectors/group) 8E 47 0001 Temporary sector unprotected (1=supported) 90 48 0001 Sector protect/unprotected scheme 92 49 0004 Simultaneous R/W operation (0=not supported) 94 4A 0000 Burst mode type (0=not supported) 96 4B 0000 Page mode type (0=not supported) 98 4C 0000

TABLE 5. MX29SL800C T/B COMMAND DEFINITIONS

  1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care.

DDI = Data of Device identifier : C2H for manufacture code, 22EAH/EAH(Top), and 226BH/6BH(Bottom) for device code. RA=Address of memory location to be read. RD=Data to be read at location RA.

  1. PA = Address of memory location to be programmed.

PD = Data to be programmed at location P A.

  1. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or

555H to Address A10~A-1 in byte mode. Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A18 in either state.

  1. For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,

it means the sector is still not being protected.

  1. Any number of CFI data read cycle are permitted.
  2. Set sector address (SA) with (A6, A1, A0)=(0,1,0).
  3. This command is valid while RESET#=VID.

TABLE 6. MX29SL800C T/B BUS OPERATION

  1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 5.
  2. VID is the Silicon-ID-Read high voltage, 10V to 11V.
  3. Refer to Table 5 for valid Data-In during a write operation.
  4. Code=00H/XX00H means unprotected.

Code=01H/XX01H means protected.

  1. A18~A12=Sector address for sector protect.
  2. The sector protect and chip unprotected functions may also be implemented via programming equipment.

Sector Erase operation is in progress. dress and data sequences into the command register.

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory , the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors , or the entire device. Table indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence section for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODE When using both pins of CE# and RESET#, the device enter CMOS Standby with both pins held at Vcc ± 0.3V. If CE# and RESET# are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (Icc2) is required even CE# = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data. OUTPUT DISABLE With the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. RESET# OPERATION The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP , the device immediately terminates any operation in progress, tri- states all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3V, the standby current will be greater. The RESET# pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is completed within a

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 22 for the timing diagram. READ/RESET COMMAND The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data. The de- vice remains enabled for reads until the command regis- ter contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid com- mand must then be written to place the device in the desired state. SILICON-ID READ COMMAND Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manu- facturer and device codes must be accessible while the device resides in the target system. PROM program- mers typically access signature codes by raising A9 to a high voltage (VID). However, multiplexing high voltage onto address lines is not generally desired system de- sign practice. The MX29SL800C T/B contains a Silicon-ID-Read op- eration to supple traditional PROM programming meth- odology. The operation is initiated by writing the read silicon ID command sequence into the command regis- ter. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of EAH/22EAH for MX29SL800CT, 6BH/ 226BH for MX29SL800CB. SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H or sector erase command 30H. The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Auto- matic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pat- tern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or tim- ing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). If the Erase operation was unsuccessful, the data on Q5 is "1" (see Table 8), indicating the erase operation ex- ceed internal timing limit. The automatic erase begins on the rising edge of the last WE# or CE# pulse, whichever happens first in the com- mand sequence and terminates when the data on Q7 is "1" at which time the device returns to the Read mode, or the data on Q6 stops toggling for two consecutive read cycles at which time the device returns to the Read mode.

Resume Commands ” for more information on this mode. reset commands until the operation is complete. ing array data (also applies during Erase Suspend). TABLE 7. SILICON ID CODE

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the de- vice to be entirely pre-programmed prior to executing the Automatic Sector Erase Set-up command and Au- tomatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will auto- matically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when either the data on Q7 is "1" at which time the de- vice returns to the Read mode, or the data on Q6 stops toggling for two consecutive read cycles at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "un- lock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE# or CE#, whichever happens later, while the command (data) is latched on the rising edge of WE# or CE#, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE# or CE#, whichever happens later. Each succes- sive sector load cycle started by the falling edge of WE# or CE#, whichever happens later must begin within 50us from the rising edge of the preceding WE# or CE#, which- ever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase (30H) or Erase Suspend (B0H) during the time-out period resets the device to read mode. ERASE SUSPEND This command only has meaning while the state ma- chine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend Com- mand is issued during the sector erase operation, the device requires a maximum 20us to suspend the sector erase operation. However, when the Erase Suspend com- mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to re- spond to Erase Resume, program data to , or read data from any sector not selected for erasure. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended sectors. ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing. However, a delay time must be required after the erase resume command (500us for MX29SL800C T/B), if the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times. The erase times will be expended if the erase behavior always be suspended. (Please refer to MXIC Flash Application Note for details.) WORD/BYTE PROGRAM COMMAND SEQUENCE The device programs one word/byte of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 1 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/ BY#. Table 10 and the following subsections describe the functions of these bits. Q7, RY/BY#, and Q6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Q7: Data# Polling The DATA# polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or com- pleted, or whether the device is in Erase Suspend. DATA# polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Automatic Program algorithm, the device out- puts on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to programming dur- ing Erase Suspend. When the Automatic Program algo- rithm is complete, the device outputs the datum pro- grammed to Q7. The system must provide the program address to read valid status information on Q7. If a pro- gram address falls within a protected sector, DATA# poll- ing on Q7 is active for approximately 2 us, then the de- vice returns to reading array data. During the Automatic Erase algorithm, DATA# polling pro- duces a "0" on Q7. When the Automatic Erase algo- determine the status of the program operation by using Q7, Q6, or RY/BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set Q5 to "1" , or cause the DATA# polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". rithm is complete, or if the device enters the Erase Sus- pend mode, DATA# polling produces a "1" on Q7. This is analogous to the complement/true datum out-put de- scribed for the Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement," or "0". The system must provide an address within any of the sec- tors selected for erasure to read valid status information on Q7. After an erase command sequence is written, if all sec- tors selected for erasing are protected, DATA# polling on Q7 is active for approximately 100 us, then the device returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchronously with Q0-Q6 while Output En- able (OE#) is asserted low. RY/BY# : Ready/Busy The RY/BY# is a dedicated, open-drain output pin that indicates whether an Automatic Erase/Program algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# or CE#, whichever happens first, in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the de- vice is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 8 shows the outputs for RY/BY# during write op- eration. Q6:Toggle BIT I Toggle Bit I on Q6 indicates whether an Automatic Pro- gram or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# or CE#, whichever

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 During an Automatic Program or Erase algorithm opera- tion, successive read cycles to any address cause Q6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sec- tors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase sus- pended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-sus- pended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program com- mand sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algo- rithm is complete. Table 8 shows the outputs for Toggle Bit I on Q6. Q2:Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# or CE#, whichever happens first, in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by com- parison, indicates whether the device is actively eras- ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 8 to compare outputs for Q2 and Q6. Reading Toggle Bits Q6/ Q2 Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase op- eration. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. Alterna- tively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Exceeded Timing Limits Q5 will indicate if the program or erase time has ex- ceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data# Polling and Toggle Bit are the only operating functions of the device under this condition. happens first, in the command sequence (prior to the program or erase operation), and during the sector time- out.

tion. The device must be reset to use other sectors. bination of sectors are bad. TABLE 8. WRITE OPERATION STATUS

  1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
  2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more information.

  1. Successive reads from the erasing or erase-suspend sector causes Q2 to toggle.
  2. Reading from non-erase suspended sector address will indicate logic "1" at the Q2 bit.

device was incorrectly used.

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 POW ER SUPPLY DECOUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be- tween its VCC and GND. POWER-UP SEQUENCE The MX29SL800C T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. TEMPORARY SECTOR UNPROTECTED This feature allows temporary unprotected of previously protected sector to change data in-system. The Tempo- rary Sector Unprotected mode is activated by setting the RESET# pin to VID (10V-11V). During this mode, formerly protected sectors can be programmed or erased as un-protected sector. Once VID is remove from the RESET# pin, all the previously protected sectors are protected again. SECTOR PROTECTION The MX29SL800C T/B features hardware sector protec- tion. This feature will disable both program and erase operations for these sectors protected. To activate this mode, the programming equipment must force VID on address pin A9 and OE#. Programming of the protection circuitry begins on the falling edge of the WE# pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform. To verify programming of the protection circuitry, the pro- gramming equipment must force VID on address pin A9 ( with CE# and OE# at VIL and WE# at VIH). When A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1" code at device output Q0 for a protected sector. Other- wise the device will produce 00H for the unprotected sector. In this mode, the addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes. (Read Silicon ID) It is also possible to determine if the sector is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. DATA# polling and Toggle Bit are valid after the initial sector erase com- mand sequence. If DATA# polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by DATA# polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the com- mand has been accepted, the system software should check the status of Q3 prior to and following each sub- sequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. DATA PROTECTION The MX29SL800C T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically re- sets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down tran- sition or system noise. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns(typical) on CE# or WE# will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one.

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 a logical "1" at Q0 for the protected sector. CHIP UNPROTECTED The MX29SL800C T/B also features the chip unprotected mode, so that all sectors are unprotected after chip un- protected is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotected mode. To activate this mode, the programming equipment must force VID on control pin OE# and address pin A9. The CE# pins must be set at VIL. Pins A6 must be set to VIH. Refer to chip unprotected algorithm and waveform for the chip unprotected algorithm. The unprotection mechanism begins on the falling edge of the WE# pulse and is terminated on the rising edge. It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs (Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotected algorithm is completed.

  1. Minimum DC voltage on input or I/O pins is -0.3 V.

Figure 6. Maximum DC voltage on input or I/O pins is

  1. Minimum DC input voltage on pins A9, OE#, and

12.5 V for periods up to 20 ns.

  1. No more than one output may be shorted to ground at

Ratings" may cause permanent damage to the device. functionality of the device is guaranteed.

  1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

  1. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.

TABLE 9. DC CHARACTERISTICS TA = -40oC to 85oC, VCC = 1.65V~2.2V

0.1 V IOL = 100uA, VCC= VCC min

  1. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.  Input rise and fall times is equal to or less than 5ns. TABLE 10. READ OPERATIONS

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 SWITCHING TEST CIRCUITS SWITCHING TEST WAVEFORMS DEVICE UNDER TEST DIODES=IN3064 OR EQUIVALENT CL 6.2K ohm 2.7K ohm VCC CL= 30pF Including jig capacitance TEST POINTS VCC AC TESTING: Inputs are driven at VCC for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. OUTPUTINPUT

FIGURE 1. READ TIMING WAVEFORMS

  1. See the "Erase and Programming Performance" section for more information.

TABLE 11. Erase/Program Operations

  1. See the "Erase and Programming Performance" section for more information.

TABLE 12. Alternate CE# Controlled Erase/Program Operations

FIGURE 2. COMMAND WRITE TIMING WAVEFORM

FIGURE 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM

FIGURE 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

FIGURE 5. CE# CONTROLLED PROGRAM TIMING WAVEFORM 1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device. 2.Figure indicates the last two bus cycles of the command sequence.

FIGURE 6. AUTOMATIC CHIP ERASE TIMING WAVEFORM SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

FIGURE 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

FIGURE 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

FIGURE 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

FIGURE 10. ERASE SUSPEND/ERASE RESUME FLOWCHART

  1. If the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is

exceeded 1024 times, then the delay time must be put into consideration.

  1. Delay timing: 1.5ms for MX29SL800C T/B.

FIGURE 11. IN-SYSTEM SECTOR PROTECT/UNPROTECTED TIMING WAVEFORM (RESET# Control) Note: When sector protect, A6=0, A1=1, A0=0. When chip unprotect, A6=1, A1=1, A0=0.

FIGURE 12. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control)

FIGURE 13. SECTOR PROTECTION ALGORITHM (A9, OE# Control)

FIGURE 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID

FIGURE 15. IN-SYSTEM CHIP UNPROTECTION ALGORITHM WITH RESET#=VID

FIGURE 16. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control) Notes: tVLHT (Voltage transition time)=4us min. tOESP (OE# setup time to WE# active)=4us min.

FIGURE 17. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)

  • It is recommended before unprotect whole chip, all sectors should be protected in advance.

FIGURE 18. DATA# POLLING ALGORITHM

FIGURE 19. TOGGLE BIT ALGORITHM Note:1.Read toggle bit twice to determine whether or not it is toggling.

  1. Recheck toggle bit because it may stop toggling as Q5 change to "1".

FIGURE 20. DATA# Polling Timings (During Automatic Algorithms)

  1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.
  2. CE# must be toggled when DATA# polling.

FIGURE 21. Toggle Bit Timings (During Automatic Algorithms)

  1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle,
  2. CE# must be toggled when toggle bit toggling.

FIGURE 22. RESET# TIMING WAVEFORM TABLE 13. AC CHARACTERISTICS

FIGURE 23. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte TABLE 14. WORD/BYTE CONFIGURATION (BYTE#)

FIGURE 28. TEMPORARY SECTOR UNPROTECTED ALGORITHM

  1. All previously protected sectors are protected again.

Note : 1. All protected sectors are temporary unprotected.

FIGURE 29. ID CODE READ TIMING WAVEFORM

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. Figure A. AC Timing at Device Power-Up Notes : 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. Symbol Parameter Notes Min. Max. Unit tVR VCC Rise Time 1 20 500000 us/V tR Input Signal Rise Time 1,2 20 us/V tF Input Signal Fall Time 1,2 20 us/V VCC ADDRESS CE# WE# OE# DATA tVR tACCtR or tF tCEtF VCC(min) GND VIH VIL VIH VIL VIH VIL VIH VIL VOH High Z VOL WP#/ACC VIH VIL Valid Ouput Valid Address tR or tF tR tOEtF tR

TABLE 16. ERASE AND PROGRAMMING PERFORMANCE (1) Note: 1. Not 100% Tested, Excludes external system level over head.

  1. Typical values measured at 25°C, 1.8V .
  2. Maximum values measured at 90°C, 1.65V , 100K cycles.

Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin at a time. TABLE 17. LATCH-UP CHARACTERISTICS

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006

ORDERING INFORMATION

PART NO. ACCESS OPERATING STANDBY P ACKAGE Remark TIME (ns) Current MAX. (mA) Current MAX. (uA) MX29SL800CTTC-90 90 12 5 48-Pin TSOP (Normal T ype) MX29SL800CBTC-90 90 12 5 48-Pin TSOP (Normal T ype) MX29SL800CTXBC-90 90 12 5 48-ball CSP (Ball Size:0.3mm) MX29SL800CBXBC-90 90 12 5 48-ball CSP (Ball Size:0.3mm) MX29SL800CTXEC-90 90 12 5 48-ball CSP (Ball Size:0.4mm) MX29SL800CBXEC-90 90 12 5 48-ball CSP (Ball Size:0.4mm) MX29SL800CTXHC-90 90 12 5 48-ball CSP (Ball Pitch:0.5mm, Ball Size:0.3mm) MX29SL800CBXHC-90 90 12 5 48-ball CSP (Ball Pitch:0.5mm, Ball Size:0.3mm) MX29SL800CTTI-90 90 12 5 48-Pin TSOP (Normal T ype) MX29SL800CBTI-90 90 12 5 48-Pin TSOP (Normal T ype) MX29SL800CTXBI-90 90 12 5 48-ball CSP (Ball Size:0.3mm) MX29SL800CBXBI-90 90 12 5 48-ball CSP (Ball Size:0.3mm) MX29SL800CTXEI-90 90 12 5 48-ball CSP (Ball Size:0.4mm) MX29SL800CBXEI-90 90 12 5 48-ball CSP (Ball Size:0.4mm) MX29SL800CTXHI-90 90 12 5 48-ball CSP (Ball Pitch:0.5mm, Ball Size:0.3mm) MX29SL800CBXHI-90 90 12 5 48-ball CSP (Ball Pitch:0.5mm, Ball Size:0.3mm)

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006 PART NAME DESCRIPTION MX 29 SL 90C T T C G OPTION: G: Lead-free package blank: normal SPEED: 90: 90ns TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: T: TSOP XB: CSP (0.8mm ball pitch, 0.3mm ball size) XE: CSP (0.8mm ball pitch, 0.4mm ball size) XH: CSP (0.5mm ball pitch, 0.3mm ball size) BOOT BLOCK TYPE: T: Top Boot B: Bottom Boot REVISION: C DENSITY & MODE: 800: 8M, x8/x16 Boot Block TYPE: SL: 1.8V DEVICE: 29: Flash 800

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006

PACKAGE INFORMATION

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006

P/N:PM1224 MX29SL800C T/B REV. 1.0, APR. 20, 2006

REVISION HISTORY

Revision No.Description Page Date 1.0 1. Removed "Preliminary" title P1 APR/20/2006

MACRONIX INTERNATIONAL CO., LTD. Headquarters: Europe Office : TEL:+32-2-456-8020 FAX:+32-2-456-8021 Hong Kong Office : Japan Office : Kawasaki Office : Osaka Office : Singapore Office : TEL:+65-6346-5505 FAX:+65-6348-8096 Taipei Office : TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.