MBM29LV160TE FUJITSU | Alldatasheet

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DS05-20883-2EFUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 16M (2M · 8/1M · 16) BIT MBM29LV160TE/BE -70/90/12 n GENERAL DESCRIPTION The MBM29LV160TE/BE is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29LV160TE/BE is offered in a 48-pin TSOP (I), 48-pin CSOP and 48-ball FBGA packages. The device is designed to be programmed in-system with the standard system 3.0 V V CC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard MBM29LV160TE/BE offers access times of 70 ns, 90 ns and 120 ns, allowing operation of high- speed microprocessors without wait states. T o eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29LV160TE/BE is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29LV160TE/BE is programmed by executing the program command sequence. This will invoke the Embedded Program TM* Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. T ypically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase TM* Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins. Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.) within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. (Continued) n PRODUCT LINE UP Part No. MBM29LV160TE/160BE Ordering Part No. VCC = 3.3 V 70 — — VCC = 3.0 V —9 01 2 Max. Address Access Time (ns) 70 90 120 Max. CE Access Time (ns) 70 90 120 Max. OE Access Time (ns) 30 35 50 +0.3 V –0.3 V +0.6 V –0.3 V

(Continued) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV160TE/BE is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low V CC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the T oggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. The MBM29LV160TE/BE also has a hardware RESET pin. When this pin is driven low, execution of any Em- bedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s micropro- cessor to read the boot-up firmware from the Flash memory. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29LV160TE/BE memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. * : n PACKAGES 48-pin plastic TSOP (I) (FPT -48P-M19) 48-pin plastic CSOP (LCC-48P-M03) 48-pin plastic TSOP (I) (FPT -48P-M20) 48-pin plastic FBGA (BGA-48P-M11) Marking Side Marking Side Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

  • 0 . 2 3 mm Process Technology
  • Single 3.0 V read, program and erase Minimizes system level power requirements
  • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs
  • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (I) (Package suffix: TN-Normal Bend T ype, TR-Reversed Bend T ype) 48-pin CSOP (Package suffix: PCV) 48-ball FBGA (Package suffix: PBT)
  • Minimum 100,000 program/erase cycles
  • High performance 70 ns maximum access time
  • Sector erase architecture One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase
  • Boot Code Sector Architecture T = T op sector B = Bottom sector
  • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector
  • Embedded Program TM Algorithms Automatically programs and verifies data at specified address
  • D a t a Polling and Toggle Bit feature for detection of program or erase cycle completion
  • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion
  • Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode
  • L o w VCC write inhibit £ 2.5 V
  • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device
  • Sector protection Hardware method disables any combination of sectors from program or erase operations
  • Sector Protection Set function by Extended sector Protection command
  • Fast Programming Function by Extended command
  • Temporary sector unprotection T emporary sector unprotection via the RESET pin
  • In accordance with CFI (Common F lash Memory Interface)

(Continued) A A14 A13 A12 A11 A10 A19 N.C. WE RESET N.C. N.C. RY/BY A A17 A16 BYTE V SS DQ 15/A-1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 VCC DQ 11 DQ 3 DQ 10 DQ 2 DQ 9 DQ 1 DQ 8 DQ 0 OE V SS CE A Standard Pinout TSOP(I) (Marking Side) (FPT-48P-M19) Reverse Pinout (Marking Side) (FPT-48P-M20) A17 A18 RY/BY N.C. N.C. RESET WE N.C. A A10 A11 A12 A13 A14 A15 CE V SS OE DQ DQ 8 DQ 1 DQ 9 DQ 2 DQ 10 DQ 3 DQ 11 VCC DQ 4 DQ 12 DQ 5 DQ 13 DQ 6 DQ 14 DQ 7 DQ 15/A-1 VSS BYTE A

(Continued) (TOP VIEW) (Marking side) CSOP (LCC-48P-M03) A A17 A18 RY /BY N.C. N.C. RESET WE N.C. A A10 A11 A12 A13 A14 A15 CE V SS OE DQ DQ 8 DQ 1 DQ 9 DQ 2 DQ 10 DQ 3 DQ 11 VCC DQ 4 DQ 12 DQ 5 DQ 13 DQ 6 DQ 14 DQ 7 DQ 15/A-1 VSS BYTE A16 Marking side (TOP VIEW) FBGA (BGA-48P-M11) A1 A 3 A2 A 7 A3 RY/BY A4 WE A5 A 9 A6 A 13 B1 A 4 B2 A 17 B3 N.C. B4 RESET B5 A 8 B6 A 12 C1 A 2 C2 A 6 C3 A 18 C4 N.C. C5 A 10 C6 A 14 D1 A 1 D2 A 5 D3 N.C. D4 A 19 D5 A 11 D6 A 15 E1 A 0 E2 DQ 0 E3 DQ 2 E4 DQ 5 E5 DQ 7 E6 A 16 F1 CE F2 DQ 8 F3 DQ 10 F4 DQ 12 F5 DQ 14 F6 BYTE G1 OE G2 DQ 9 G3 DQ 11 G4 V CC G5 DQ 13 G6 DQ 15/A-1 H1 V SS H2 DQ 1 H3 DQ 3 H4 DQ 4 H5 DQ 6 H6 V SS

Table 1 MBM29LV160TE/BE Pin Configuration Pin Function A-1, A0 to A19 Address Inputs DQ 0 to DQ15 Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy Output RESET Hardware Reset Pin/ T emporary Sector Unprotection BYTE Selects 8-bit or 16-bit mode N.C. Pin Not Connected Internally VSS Device Ground VCC Device Power Supply A0 to A19 RY/BY OE CE DQ 0 to DQ15 16 or 8 RESET BYTE WE A-1

Legend: L = VIL, H = VIH, X = VIL or VIH. = Pulse input. See DC Characteristics for voltage levels. Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See T able 7. 2. Refer to the section on Sector Protection. 3. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 5. It is also used for the extended sector protection. Table 2 MBM29LV160TE/BE User Bus Operation (BYTE = VIH) Operation CE OE WE A 0 A 1 A 6 A 9 DQ 0 to DQ15 RESET Auto-Select Manufacture Code (1) L L H L L L V ID Code H Auto-Select Device Code (1) L L H H L L V ID Code H Read (3) L L H A 0 A1 A6 A9 D OUT H S t a n d b y HXXXXXX H I G H - Z H O u t p u t D i s a b l e LHHXXXX H I G H - Z H Write (Program/Erase) L H L A

0 A1 A6 A9 D IN H

Enable Sector Protection (2), (4) L V ID LHL V ID XH Verify Sector Protection (2), (4) L L H L H L V ID Code H T emporary Sector Unprotection (5) X X X X X X X X V ID R e s e t ( H a r d w a r e ) / S t a n d b y XXXXXXX H I G H - Z L Table 3 MBM29LV160TE/BE User Bus Operation (BYTE = VIL) Operation CE OE WE DQ 15 / A -1 A 0 A 1 A 6 A 9 DQ 0 to DQ7 RESET Auto-Select Manufacture Code (1) L L H L L L L V ID Code H Auto-Select Device Code (1) L L H L H L L V ID Code H Read (3) L L H A -1 A0 A1 A6 A9 D OUT H S t a n d b y HXX X XXXX H I G H - Z H Output Disable L H H X X X X X HIGH-Z H Write (Program/Erase) L H L A -1 A0 A1 A6 A9 D IN H Enable Sector Protection (2), (4) L VID LL H L V ID XH Verify Sector Protection (2), (4) L L H L L H L V ID Code H T emporary Sector Unprotection (5) X X X X X X X X X V ID Reset (Hardware)/Standby X X X X X X X X HIGH-Z L

n FLEXIBLE SECTOR-ERASE ARCHITECTURE

  • One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode.
  • One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode.
  • Individual-sector, multiple-sector, or bulk-erase capability.
  • Individual or multiple-sector protection is user definable. MBM29LV160TE Top Boot Sector Architecture Sector Sector Size ( · 8) Address Range ( · 16) Address Range SA0 64 Kbytes or 32 Kwords 00000H to 0FFFFH 00000H to 07FFFH SA1 64 Kbytes or 32 Kwords 10000H to 1FFFFH 08000H to 0FFFFH SA2 64 Kbytes or 32 Kwords 20000H to 2FFFFH 10000H to 17FFFH SA3 64 Kbytes or 32 Kwords 30000H to 3FFFFH 18000H to 1FFFFH SA4 64 Kbytes or 32 Kwords 40000H to 4FFFFH 20000H to 27FFFH SA5 64 Kbytes or 32 Kwords 50000H to 5FFFFH 28000H to 2FFFFH SA6 64 Kbytes or 32 Kwords 60000H to 6FFFFH 30000H to 37FFFH SA7 64 Kbytes or 32 Kwords 70000H to 7FFFFH 38000H to 3FFFFH SA8 64 Kbytes or 32 Kwords 80000H to 8FFFFH 40000H to 47FFFH SA9 64 Kbytes or 32 Kwords 90000H to 9FFFFH 48000H to 4FFFFH SA10 64 Kbytes or 32 Kwords A0000H to AFFFFH 50000H to 57FFFH SA11 64 Kbytes or 32 Kwords B0000H to BFFFFH 58000H to 5FFFFH SA12 64 Kbytes or 32 Kwords C0000H to CFFFFH 60000H to 67FFFH SA13 64 Kbytes or 32 Kwords D0000H to DFFFFH 68000H to 6FFFFH SA14 64 Kbytes or 32 Kwords E0000H to EFFFFH 70000H to 77FFFH SA15 64 Kbytes or 32 Kwords F0000H to FFFFFH 78000H to 7FFFFH SA16 64 Kbytes or 32 Kwords 100000H to 10FFFFH 80000H to 87FFFH SA17 64 Kbytes or 32 Kwords 110000H to 11FFFFH 88000H to 8FFFFH SA18 64 Kbytes or 32 Kwords 120000H to 12FFFFH 90000H to 97FFFH SA19 64 Kbytes or 32 Kwords 130000H to 13FFFFH 98000H to 9FFFFH SA20 64 Kbytes or 32 Kwords 140000H to 14FFFFH A0000H to A7FFFH SA21 64 Kbytes or 32 Kwords 150000H to 15FFFFH A8000H to AFFFFH SA22 64 Kbytes or 32 Kwords 160000H to 16FFFFH B0000H to B7FFFH SA23 64 Kbytes or 32 Kwords 170000H to 17FFFFH B8000H to BFFFFH SA24 64 Kbytes or 32 Kwords 180000H to 18FFFFH C0000H to C7FFFH SA25 64 Kbytes or 32 Kwords 190000H to 19FFFFH C8000H to CFFFFH SA26 64 Kbytes or 32 Kwords 1A0000H to 1AFFFFH D0000H to D7FFFH SA27 64 Kbytes or 32 Kwords 1B0000H to 1BFFFFH D8000H to DFFFFH SA28 64 Kbytes or 32 Kwords 1C0000H to 1CFFFFH E0000H to E7FFFH SA29 64 Kbytes or 32 Kwords 1D0000H to 1DFFFFH E8000H to EFFFFH SA30 64 Kbytes or 32 Kwords 1E0000H to 1EFFFFH F0000H to F7FFFH SA31 32 Kbytes or 16 Kwords 1F0000H to 1F7FFFH F8000H to FBFFFH SA32 8 Kbytes or 4 Kwords 1F8000H to 1F9FFFH FC000H to FCFFFH SA33 8 Kbytes or 4 Kwords 1FA000H to 1FBFFFH FD000H to FDFFFH SA34 16 Kbytes or 8 Kwords 1FC000H to 1FFFFFH FE000H to FFFFFH

MBM29LV160BE Bottom Boot Sector Architecture Sector Sector Size ( · 8) Address Range ( · 16) Address Range SA0 16 Kbytes or 8 Kwords 00000H to 03FFFH 00000H to 01FFFH SA1 8 Kbytes or 4 Kwords 04000H to 05FFFH 02000H to 02FFFH SA2 8 Kbytes or 4 Kwords 06000H to 07FFFH 03000H to 03FFFH SA3 32 Kbytes or 16 Kwords 08000H to 0FFFFH 04000H to 07FFFH SA4 64 Kbytes or 32 Kwords 10000H to 1FFFFH 08000H to 0FFFFH SA5 64 Kbytes or 32 Kwords 20000H to 2FFFFH 10000H to 17FFFH SA6 64 Kbytes or 32 Kwords 30000H to 3FFFFH 18000H to 1FFFFH SA7 64 Kbytes or 32 Kwords 40000H to 4FFFFH 20000H to 27FFFH SA8 64 Kbytes or 32 Kwords 50000H to 5FFFFH 28000H to 2FFFFH SA9 64 Kbytes or 32 Kwords 60000H to 6FFFFH 30000H to 37FFFH SA10 64 Kbytes or 32 Kwords 70000H to 7FFFFH 38000H to 3FFFFH SA11 64 Kbytes or 32 Kwords 80000H to 8FFFFH 40000H to 47FFFH SA12 64 Kbytes or 32 Kwords 90000H to 9FFFFH 48000H to 4FFFFH SA13 64 Kbytes or 32 Kwords A0000H to AFFFFH 50000H to 57FFFH SA14 64 Kbytes or 32 Kwords B0000H to BFFFFH 58000H to 5FFFFH SA15 64 Kbytes or 32 Kwords C0000H to CFFFFH 60000H to 67FFFH SA16 64 Kbytes or 32 Kwords D0000H to DFFFFH 68000H to 6FFFFH SA17 64 Kbytes or 32 Kwords E0000H to EFFFFH 70000H to 77FFFH SA18 64 Kbytes or 32 Kwords F0000H to FFFFFH 78000H to 7FFFFH SA19 64 Kbytes or 32 Kwords 100000H to 10FFFFH 80000H to 87FFFH SA20 64 Kbytes or 32 Kwords 110000H to 11FFFFH 88000H to 8FFFFH SA21 64 Kbytes or 32 Kwords 120000H to 12FFFFH 90000H to 97FFFH SA22 64 Kbytes or 32 Kwords 130000H to 13FFFFH 98000H to 9FFFFH SA23 64 Kbytes or 32 Kwords 140000H to 14FFFFH A0000H to A7FFFH SA24 64 Kbytes or 32 Kwords 150000H to 15FFFFH A8000H to AFFFFH SA25 64 Kbytes or 32 Kwords 160000H to 16FFFFH B0000H to B7FFFH SA26 64 Kbytes or 32 Kwords 170000H to 17FFFFH B8000H to BFFFFH SA27 64 Kbytes or 32 Kwords 180000H to 18FFFFH C0000H to C7FFFH SA28 64 Kbytes or 32 Kwords 190000H to 19FFFFH C8000H to CFFFFH SA29 64 Kbytes or 32 Kwords 1A0000H to 1AFFFFH D0000H to D7FFFH SA30 64 Kbytes or 32 Kwords 1B0000H to 1BFFFFH D8000H to DFFFFH SA31 64 Kbytes or 32 Kwords 1C0000H to 1CFFFFH E0000H to E7FFFH SA32 64 Kbytes or 32 Kwords 1D0000H to 1DFFFFH E8000H to EFFFFH SA33 64 Kbytes or 32 Kwords 1E0000H to 1EFFFFH F0000H to F7FFFH SA34 64 Kbytes or 32 Kwords 1F0000H to 1FFFFFH F8000H to FFFFFH

  • R e a d M o d e The MBM29LV160TE/BE has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC ) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE ) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC - tOE time.) When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”.
  • Standby Mode There are two ways to implement the standby mode on the MBM29LV160TE/BE devices. One is by using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ±0.3 V . Under this condition the current consumed is less than 5 mA max. During Embedded Algorithm operation, VCC Active current (ICC2 ) is required even CE = “H”. The device can be read with standard access time (tCE ) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with the RESET input held at VSS ±0.3 V (CE = “H” or “L”). Under this condition the current consumed is less than 5 mA max. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode, the outputs are in the high-impedance state, independent of the OE input.
  • Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29LV160TE/BE data. This mode can be used effectively with an application requesting low power con- sumption such as handy terminals. T o activate this mode, MBM29LV160TE/BE automatically switches itself to low power mode when addresses remain stable for 150 ns. It is not necessary to control CE , WE, and OE in this mode. During such mode, the current consumed is typically 1 mA (CMOS Level). Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system.
  • Output Disable If the OE input is at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high-impedance state.
  • Autoselect The Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. The intent is to allow programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The Autoselect command may also be used to check the status of write-protected sectors. (See T ables 4.1 and 4.2.) This mode is functional over the entire temperature range of the device. T o activate this mode, the programming equipment must force V ID (11.5 V to 12.5 V) on address pin A9. T wo identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON’T CARES except A0, A1, and A6 (A-1). (See T able 2 or T able 3.)

The manufacturer and device codes may also be read via the command register, for instances when the MBM29LV160TE/BE is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in T able 7, Command Definitions. Byte 0 (A 0 = VIL) represents the manufacture’s code and byte 1 (A0 = VIH) represents the device identifier code. For the MBM29LV160TE/BE these two bytes are given in the T able 4.2. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Autoselect, A1 must be VIL. (See T ables 2 or 3.) For device indentification in word mode (BYTE = VIH), DQ9 and DQ13 are equal to ‘1’ and DQ8, DQ10 to DQ12, DQ14, and DQ15 are equal to ‘0’. If BYTE = VIL (for byte mode), the device code is C4H (for top boot block) or 49H (for bottom boot block). If BYTE = VIH (for word mode), the device code is 22C4H (for top boot block) or 2249H (for bottom boot block). In order to determine which sectors are write protected, A1 must be at VIH while running through the sector addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ0 (DQ0 =1). *1: A-1 is for Byte mode. *2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses. (B): Byte mode (W): Word mode Table 4.1 MBM29LV160TE/BE Sector Protection Verify Autoselect Code Type A 12 to A19 A 6 A 1 A 0 A -1*1 Code (HEX) Manufacture’s Code X V IL VIL VIL VIL 04H Device Code MBM29LV160TE Byte XV IL VIL VIH VIL C4H Word X 22C4H MBM29LV160BE Byte XV IL VIL VIH VIL 49H Word X 2249H Sector Protection Sector Addresses VIL VIH VIL VIL 01H*2 Table 4.2 Expanded Autoselect Code Table Type Code DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8 DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 Manufacture’s Code 04H A -1/ 0 0000000 00000100 Device Code MBM29LV160TE (B) C4H A -1 H I - Z H I - Z H I - Z H I - Z H I - Z H I - Z H I - Z 11000100 (W) 2 2 C 4 H 00100010 11000100 MBM29LV160BE (B) 49H A -1 H I - Z H I - Z H I - Z H I - Z H I - Z H I - Z H I - Z 01001001 (W) 2249H 0 0100010 01001001 Sector Protection 01H A -1/ 0 0000000 00000001

Table 5 Sector Address Tables (MBM29LV160TE) Sector Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 (· 8) Address Range (· 16) Address Range S A 0 00000XXX0 0000H to 0FFFFH 00000H to 07FFFH S A 1 00001XXX1 0000H to 1FFFFH 08000H to 0FFFFH S A 2 00010XXX2 0000H to 2FFFFH 10000H to 17FFFH S A 3 00011XXX3 0000H to 3FFFFH 18000H to 1FFFFH S A 4 00100XXX4 0000H to 4FFFFH 20000H to 27FFFH S A 5 00101XXX5 0000H to 5FFFFH 28000H to 2FFFFH S A 6 00110XXX6 0000H to 6FFFFH 30000H to 37FFFH S A 7 00111XXX7 0000H to 7FFFFH 38000H to 3FFFFH S A 8 01000XXX8 0000H to 8FFFFH 40000H to 47FFFH S A 9 01001XXX9 0000H to 9FFFFH 48000H to 4FFFFH S A 1 0 01010XXXA 0000H to AFFFFH 50000H to 57FFFH S A 1 1 01011XXXB 0000H to BFFFFH 58000H to 5FFFFH S A 1 2 01100XXX C 0000H to CFFFFH 60000H to 67FFFH S A 1 3 01101XXX D 0000H to DFFFFH 68000H to 6FFFFH S A 1 4 01110XXXE 0000H to EFFFFH 70000H to 77FFFH S A 1 5 01111XXXF 0000H to FFFFFH 78000H to 7FFFFH S A 1 6 10000XXX 1 0 0000H to 10FFFFH 80000H to 87FFFH S A 1 7 10001XXX 1 1 0000H to 11FFFFH 88000H to 8FFFFH S A 1 8 10010XXX 1 2 0000H to 12FFFFH 90000H to 97FFFH S A 1 9 10011XXX 1 3 0000H to 13FFFFH 98000H to 9FFFFH S A 2 0 10100XXX 1 4 0000H to 14FFFFH A0000H to A7FFFH S A 2 1 10101XXX 1 5 0000H to 15FFFFH A8000H to AFFFFH S A 2 2 10110XXX 1 6 0000H to 16FFFFH B0000H to B7FFFH S A 2 3 10111XXX 1 7 0000H to 17FFFFH B8000H to BFFFFH S A 2 4 11000XXX 1 8 0000H to 18FFFFH C0000H to C7FFFH S A 2 5 11001XXX 1 9 0000H to 19FFFFH C8000H to CFFFFH S A 2 6 11010XXX 1 A 0000H to 1AFFFFH D0000H to D7FFFH S A 2 7 11011XXX 1 B 0000H to 1BFFFFH D8000H to DFFFFH S A 2 8 11100XXX 1 C 0000H to 1CFFFFH E0000H to E7FFFH S A 2 9 11101XXX 1 D 0000H to 1DFFFFH E8000H to EFFFFH S A 3 0 11110XXX 1 E 0000H to 1EFFFFH F0000H to F7FFFH S A 3 1 111110XX 1 F 0 0 0 0 H t o 1 F 7 F F F H F 8000H to FBFFFH S A 3 2 11111100 1 F 8 0 0 0 H t o 1 F 9 F F F H F C 0 0 0 H t o F C F F F H S A 3 3 11111101 1 F A 0 0 0 H t o 1 F B F F F H F D 0 0 0 H t o F D F F F H S A 3 4 1111111X 1 F C 000H to 1FFFFFH FE000H to FEFFFH

Table 6 Sector Address Tables (MBM29LV160BE) Sector Address A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 (· 8) Address Range (· 16) Address Range S A 0 0000000X 00000H to 03FFFH 00000H to 01FFFH S A 1 00000010 04000H to 05FFFH 02000H to 02FFFH S A 2 00000011 06000H to 07FFFH 03000H to 03FFFH S A 3 0000010X0 8000H to 0FFFFH 04000H to 07FFFH S A 4 00001XXX1 0000H to 1FFFFH 08000H to 0FFFFH S A 5 00010XXX2 0000H to 2FFFFH 10000H to 17FFFH S A 6 00011XXX3 0000H to 3FFFFH 18000H to 1FFFFH S A 7 00100XXX4 0000H to 4FFFFH 20000H to 27FFFH S A 8 00101XXX5 0000H to 5FFFFH 28000H to 2FFFFH S A 9 00110XXX6 0000H to 6FFFFH 30000H to 37FFFH S A 1 0 00111XXX7 0000H to 7FFFFH 38000H to 3FFFFH S A 1 1 01000XXX8 0000H to 8FFFFH 40000H to 47FFFH S A 1 2 01001XXX9 0000H to 9FFFFH 48000H to 4FFFFH S A 1 3 01010XXXA 0000H to AFFFFH 50000H to 57FFFH S A 1 4 01011XXXB 0000H to BFFFFH 58000H to 5FFFFH S A 1 5 01100XXX C 0000H to CFFFFH 60000H to 67FFFH S A 1 6 01101XXX D 0000H to DFFFFH 68000H to 6FFFFH S A 1 7 01110XXXE 0000H to EFFFFH 70000H to 77FFFH S A 1 8 01111XXXF 0000H to FFFFFH 78000H to 7FFFFH S A 1 9 10000XXX 1 0 0000H to 1FFFFFH 80000H to 87FFFH S A 2 0 10001XXX 1 1 0000H to 11FFFFH 88000H to 8FFFFH S A 2 1 10010XXX 1 2 0000H to 12FFFFH 90000H to 97FFFH S A 2 2 10011XXX 1 3 0000H to 13FFFFH 98000H to 9FFFFH S A 2 3 10100XXX 1 4 0000H to 14FFFFH A0000H to A7FFFH S A 2 4 10101XXX 1 5 0000H to 15FFFFH A8000H to 8FFFFH S A 2 5 10110XXX 1 6 0000H to 16FFFFH B0000H to B7FFFH S A 2 6 10111XXX 1 7 0000H to 17FFFFH B8000H to BFFFFH S A 2 7 11000XXX 1 8 0000H to 18FFFFH C0000H to C7FFFH S A 2 8 11001XXX 1 9 0000H to 19FFFFH C8000H to CFFFFH S A 2 9 11010XXX 1 A 0000H to 1AFFFFH D0000H to D7FFFH S A 3 0 11011XXX 1 B 0000H to 1BFFFFH D8000H to DFFFFH S A 3 1 11100XXX 1 C 0000H to 1CFFFFH E0000H to E7FFFH S A 3 2 11101XXX 1 D 0000H to 1DFFFFH E8000H to EFFFFH S A 3 3 11110XXX 1 E 0000H to 1EFFFFH F0000H to F7FFFH S A 3 4 11111XXX 1 F 0000H to 1FFFFFH F8000H to FFFFFH

  • W r i t e Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The com- mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
  • Sector Protection The MBM29LV160TE/BE features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 34). The sector protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sectors unprotected. T o activate this mode, the programming equipment must force V ID on address pin A9 and control pin OE, CE = VIL, A0 = A6 = VIL, A1 = VIH. The sector addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. T ables 5 and 6 define the sector address for each of the thirty five (35) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See Figures 17 and 24 for sector protection waveforms and algorithm. T o verify programming of the protection circuitry, the programming equipment must force V ID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. Otherwise the device will read 00H for an unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to VIL in byte mode. It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02H, where the higher order addresses pins (A 19, A18, A17, A16, A15, A14, A13, and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See T ables 4.1 and 4.2 for Autoselect codes.
  • Temporary Sector Unprotection This feature allows temporary unprotection of previously protected sectors of the MBM29LV160TE/BE devices in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (VID). During this mode, formerly protected sectors can be programmed or erased by selecting the sector ad- dresses. Once the VID is taken away from the RESET pin, all the previously protected sectors will be protected again. (See Figures 18 and 25.)

Table 7 MBM29LV160TE/BE Standard Command Definitions Command Sequence Bus Write Cycles Req’d First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Read/Reset Word Byte Read/Reset Word 555H AAH 2AAH 55H 555H F0H RA RD — — — — Byte AAAH 555H AAAH Autoselect Word 555H AAH 2AAH 55H 555H Byte AAAH 555H AAAH Program Word 555H AAH 2AAH 55H 555H A0H PA PD — — — — Byte AAAH 555H AAAH Chip Erase Word 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Byte AAAH 555H AAAH AAAH 555H AAAH Sector Erase Word 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Byte AAAH 555H AAAH AAAH 555H Set to Fast Mode Word 555H AAH 2AAH 55H 555H Byte AAAH 555H AAAH Fast Program *1 Word XXXH Byte XXXH Reset from Fast Mode Word XXXH 90H XXXH *4 Byte XXXH XXXH Extended Sector Protection Word

4 XXXH 60H SPA 60H SPA 40H SPA SD — — — —

Query *3 Word 55H Byte AAH

Notes: 1. Address bits A11 to A19 = X = “H” or “L” for all address commands except or Program Address (P A) and Sector Address (SA). 2. Bus operations are defined in T ables 2 and 3. 3. RA =Address of the memory location to be read. P A =Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA =Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. 4. RD =Data read from location RA during read operation. PD =Data to be programmed at location P A. Data is latched on the rising edge of WE. 5. SP A=Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD =Sector protection verify data. Output 01H at protected sector addressed and output 00H at unprotected sector addresses. 6. The system should generate the following address patterns: Word Mode: 555H or 2AAH to addresses A0 to A10 Byte Mode: AAAH or 555H to addresses A-1 to A10 7. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. *1: This command is valid while Fast Mode. *2: This command is valid while RESET = VID. *3: The valid addresses are A6 to A0. The other addresses are “Don’t care”. *4: The data “00H” is also acceptable.

Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in an improper sequence will reset the device to the read mode. T able 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ 0 to DQ7 and DQ8 to DQ15 bits are ignored.

  • Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read mode, the read/reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read Charac- teristics and Waveforms for specific timing parameters. (See Figure 5.1.)
  • Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufactures and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A 9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming method- ology. The operation is initiated by writing the Autoselect command sequence into the command register. Fol- lowing the last command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read cycle from address XX01H for ·16 (XX02H for ·8) retrieves the device code (MBM29LV160TE = C4H and MBM29LV160BE = 49H for ·8 mode; MBM29LV160TE = 22C4H and MBM29LV160BE = 2249H for ·16 mode). (See T ables 4.1 and 4.2.) All manufactures and device codes will exhibit odd parity with DQ 7 defined as the parity bit. The sector state (protection or unprotection) will be indicated by address XX02H for ·16 (XX04H for ·8). Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin mode verification on the protected sector. (See T ables 2 and 3.) T o terminate the operation, it is necessary to write the Read/Reset command sequence into the register and, also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command sequence.
  • Byte/Word Programming The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.) The automatic programming operation is completed when the data on DQ 7 is equivalent to data written to this bit at which time the device return to the read mode and addresses are no longer latched. (See T able 8, Hardware Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occures during the programming operation, it is impossible to guarantee whether the data being written is correct or not.

written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when writing the Erase Suspend or Erase Resume commands. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of “t SPD ” to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ 2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for Program. This Program mode is known as the erase-suspend-program mode. Again, pro- gramming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ 2 to toggle. The end of the erase- suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or the T oggle Bit (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. T o resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

  • Extended Command (1) Fast Mode MBM29LV160TE/BE has Fast Mode function. This mode dispenses with the initial two unlock cycles required in the standard program command sequence writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. T o exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to the Figure 26 Extended algorithm.) The V CC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0H) and data write cycles (P A/PD). (Refer to the Figure 26 Extended algorithm.) (3) Extended Sector Protection In addition to normal sector protection, the MBM29LV160TE/BE has Extended Sector Protection as extended function. This function enable to protect sector by forcing V ID on RESET pin and write a commnad sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60H) into the command register. Then, the sector addresses pins (A 19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector to be protected (recommend to set VIL for the other addresses pins), and write extended sector protect command (60H). A sector is typically protected in 250 ms. T o verify programming of the protection circuitry, the sector addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40H). Following the command write, a logical “1” at device output DQ 0 will produce for protected sector in the read operation. If the output data is logical “0”, please repeat to write extended sector protect command (60H) again. T o terminate the operation, it is necessary to set RESET pin to VIH. (4) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backward- compatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98H) into the command register. Following the command write, a read cycle from specific address retrives device information. Please note that output data of upper byte (DQ 8 to DQ15) is “0” in word mode (16 bit) read. Refer to the CFI code table. T o terminate operation, it is necessary to write the read/reset command sequence into the register.
  • Write Operation Status Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle. 2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. 3. DQ 0 and DQ1 are reserve pins for future use. 4. DQ 4 is Fujitsu internal use only.
  • D Q7 Data Polling The MBM29LV160TE/BE device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the devices will produce the complement of the data last written to DQ 7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 22. For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the MBM29LV160TE/BE data pins (DQ 7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm operation and DQ 7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. See Figure 9 for the Data Polling timing specifications and diagram. Table 8 Hardware Sequence Flags Status DQ 7 DQ 6 DQ 5 DQ 3 DQ 2 In Progress Embedded Program Algorithm DQ 7 Toggle 0 0 1 Embedded/Erase Algorithm 0 Toggle 0 1 Toggle Erase Suspend Mode Erase Suspend Read (Erase Suspended Sector) 1 1 0 0 Toggle Erase Suspend Read (Non-Erase Suspended Sector) Data Data Data Data Data Erase Suspend Program (Non-Erase Suspended Sector) DQ 7 Toggle (Note 1) 00 1 (Note 2) Exceeded Time Limits Embedded Program Algorithm DQ 7 Toggle 1 0 1 Embedded/Erase Algorithm 0 Toggle 1 1 N/A Erase Suspend Program (Non-Erase Suspended Sector) DQ 7 Toggle 1 0 N/A
  • D Q6 T oggle Bit I The MBM29LV160TE/BE also feature the “T oggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data can be read on the next successive attempts. During programming, the T oggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase and sector erase, the T oggle Bit I is valid after the rising edge of the sixth WE pulse in the six- write pulse sequence. The T oggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 ms and then stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the T oggle Bit I for about 200 ms and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause the DQ6 to toggle. See Figure 10 and Figure 23 for the T oggle Bit I timing specifications and diagram.
  • D Q5 Exceeded Timing Limits DQ 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions. The OE and WE pins will control the output disable functions as described in T ables 2 and 3. The DQ 5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ 7 and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset the device with command sequence.
  • D Q3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and T oggle Bit I are valid after the initial sector erase command sequence. If Data Polling or the T oggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or T oggle Bit I. If DQ3 is low (“0”), the device will accept additional sector erase commands. T o insure the command has been accepted, the system software should check the status of DQ 3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the command may not have been accepted. See T able 8: Hardware Sequence Flags.
  • D Q2 T oggle Bit II This T oggle Bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ 2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ 2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at DQ2. DQ 6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. For example, DQ 2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ 2 toggles while DQ6 does not.) See also T able 9 and Figure 11. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. Notes: 1. Performing successive read operations from any address will cause DQ6 to toggle. 2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
  • R Y / B Y Ready/Busy Pin The MBM29LV160TE/BE provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase com- mands with the exception of the Erase Suspend command. If the MBM29LV160TE/BE is placed in an Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pull-up resister to VCC . During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. See Figures 12 and 13 for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC . Table 9 Toggle Bit Status Mode DQ 7 DQ 6 DQ 2 Program DQ 7 Toggle 1 Erase 0 Toggle Toggle Erase Suspend Read (Erase Suspended Sector) (Note 1)

11 T o g g l e

7 Toggle (Note 1) 1 (Note 2)

  • RESET Hardware Reset Pin The MBM29LV160TE/BE device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least “tRP ” in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode “t READY ” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device requires an additional “tRH ” before it allows read access. When the RESET pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. Refer to Figure 13 for the timing diagram. Refer to T emporary Sector Unprotection for additional functionality. If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will need to be erased again before they can be programmed.
  • Byte/Word Configuration The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV160TE/BE device. When this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ0 to DQ15. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ15/A-1 pin becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored. Refer to Figures 14, 15 and 16 for the timing diagram.
  • Data Protection The MBM29LV160TE/BE is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequence. The device also incorporates several features to prevent inadvertent write cycles resulting form V CC power-up and power-down transitions or system noise.
  • L o w VCC Write Inhibit T o avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO (min.). If VCC < VLKO , the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the V CC level is greater than VLKO . It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO (min.). If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be erased again prior to programming.
  • Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.
  • Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. T o initiate a write, CE and WE must be a logical zero while OE is a logical one.
  • Power-up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up.

Table 10 Common Flash Memory Interface Code Description A 0 to A6 DQ 0 to DQ15 Query-unique ASCII string “QRY” 10h 11h 12h 0051h 0052h 0059h Primary OEM Command Set 2h: AMD/FJ standard type 13h 14h 0002h 0000h Address for Primary Extended T able 15h 16h 0040h 0000h Alternate OEM Command Set (00h = not applicable) 17h 18h 0000h 0000h Address for Alternate OEM Extended T able 19h 1Ah 0000h 0000h V CC Min. (write/erase) D7-4: volt, D3-0: 100 mvolt 1Bh 0027h VCC Max. (write/erase) D7-4: volt, D3-0: 100 mvolt 1Ch 0036h VPP Min. voltage 1Dh 0000h VPP Max. voltage 1Eh 0000h T ypical timeout per single byte/w ord write 2 N ms 1Fh 0004h T ypical timeout for Min. size buffer write 2 N ms 20h 0000h T ypical timeout per individual block erase 2 N ms 21h 000Ah T ypical timeout for full chip erase 2 N ms 22h 0000h Max. timeout for byte/word write 2 N times typical 23h 0005h Max. timeout for buffer write N times typical 24h 0000h Max. timeout per individual block erase 2 N times typical 25h 0004h Max. timeout for full chip erase 2 N times typical 26h 0000h Device Size = 2N byte 27h 0015h Flash Device Interface

description

Max. number of byte in multi-byte write = 2 N 2Ah 2Bh 0000h 0000h Number of Erase Block Regions within device 2Ch 0004h Description A 0 to A6 DQ 0 to DQ15 Erase Block Region 1 Information 2Dh 2Eh 2Fh 30h 0000h 0000h 0040h 0000h Erase Block Region 2 Information 31h 32h 33h 34h 0001h 0000h 0020h 0000h Erase Block Region 3 Information 35h 36h 37h 38h 0000h 0000h 0080h 0000h Erase Block Region 4 Information 39h 3Ah 3Bh 3Ch 001Eh 0000h 0000h 0001h Query-unique ASCII string “PRI” 40h 41h 42h 0050h 0052h 0049h Major version number, ASCII 43h 0031h Minor version number, ASCII 44h 0031h Address Sensitive Unlock 0 = Required 1 = Not Required 45h 0000h Erase Suspend 0 = Not Supported 1 = T o Read Only 2 = T o Read & Write 46h 0002h Sector Protect 0 = Not Supported X = Number of sectors in per group 47h 0001h Sector T emporary Unprotect 00 = Not Supported 01 = Supported 48h 0001h Sector Protection Algorithm 49h 04h Number of Sector for Bank 2 00h = Not Supported 4Ah 00h Burst Mode T ype 00h = Not Supported 4Bh 00h Page Mode T ype 00h = Not Supported 4Ch 00h

n ABSOLUTE MAXIMUM RATINGS Notes: 1. Minimum DC voltage on input or l/O pins are –0.5 V . During voltage transitions, inputs may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and l/O pins are VCC +0.5 V . During voltage transitions,outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns. 2. Minimum DC input voltage on A9, OE, and RESET pins are –0.5 V . During voltage transitions, A9, OE, and RESET pins may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE, and RESET pins are +13.0 V which may positive overshoot to 14.0 V for periods of up to 20 ns. Voltage difference between input voltage and supply voltage (VIN – VCC ) do not exceed 9 V . WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. n RECOMMENDED OPERATING CONDITIONS Operating ranges define those limits between which the functionality of the device is quaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Rating Unit Min. Max. Storage T emperature Tstg –55 +125 °C Ambient T emperature with Power Applied T A –40 +85 °C Voltage with Respect to Ground All pins except A 9, OE, RESET (Note 1) VIN, VOUT –0.5 V CC +0.5 V Power Supply Voltage (Note 1) V CC –0.5 +5.5 V A9, OE, and RESET (Note 2) VIN –0.5 +13.0 V Parameter Symbol Value Unit Min. Typ. Max. Ambient T emperature (-70) TA –20 ¾ +70 °C Power Supply Voltage (-70) VCC +3.0 ¾ +3.6 V

n ELECTRICAL CHARACTERISTICS 1. DC Characteristics Notes: 1. The lCC current listed includes both the DC operating current and the frequency dependent component. 2. lCC active while Embedded Erase or Embedded Program is in progress. 3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. (VID – VCC ) do not exceed 9 V . Parameter Symbol Parameter Description Test Conditions Min. Max. Unit ILI Input Leakage Current V IN = VSS to VCC , VCC = VCC Max. –1.0 +1.0 µA ILO Output Leakage Current V OUT = VSS to VCC , VCC = VCC Max. –1.0 +1.0 µA ILIT A9, OE, RESET Inputs Leakage Current VCC = VCC Max., A9, OE, RESET = 12.5 V —3 5 µ A ICC1 VCC Active Current (Note 1) CE = VIL, OE = VIH f = 10 MHz Byte mA Word 35 CE = VIL, OE = VIH f = 5 MHz Byte mA Word 17 ICC2 VCC Active Current (Note 2) CE = VIL, OE = VIH —3 5 m A ICC3 VCC Current (Standby) VCC = VCC Max., CE = VCC –0.3 V , RESET = VCC –0.3 V —5 µ A ICC4 VCC Current (Standby, RESET) VCC = VCC Max., RESET = VSS –0.3 V —5 µ A ICC5 VCC Current (Automatic Sleep Mode) (Note 3) VCC = VCC Max., CE = VSS –0.3 V , RESET = VCC –0.3 V , VIN = VCC –0.3 V or VSS –0.3 V —5 µ A VIL Input Low Level — –0.5 0.6 V VIH Input High Level — 2.0 V CC + 0.3 V VID Voltage for Autoselect,Sector Protection, and T emporary Sector Unprotection 9, OE, RESET) (Note 4) —1 1 . 5 1 2 . 5 V VOL Output Low Voltage Level I OL = 4.0 mA, VCC = VCC Min. — 0.45 V VOH1 Output High Voltage Level IOH = –2.0 mA, VCC = VCC Min. 2.4 — V VOH2 IOH = –100 µA V CC – 0.4 — V VLKO Low VCC Lock-Out Voltage — 2.3 2.5 V

  1. AC Characteristics
  • Read Only Operations Characteristics Note : T est Conditions: Output Load:1 TTL gate and 30 pF (MBM29LV160TD/BD-70)

1 TTL gate and 100 pF (MBM29LV160TD/BD-90/12)

Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output:1.5 V Parameter Symbols Description Test Setup 70 (Note) (Note) (Note) Unit JEDEC Standard t AVAV tRC Read Cycle Time — Min. 70 90 120 ns tAVQV tACC Address to Output Delay CE = VIL OE = VIL Max. 70 90 120 ns tELQV tCE Chip Enable to Output Delay OE = VIL Max. 70 90 120 ns tGLQV tOE Output Enable to Output Delay — Max. 30 35 50 ns tEHQZ tDF Chip Enable to Output HIGH-Z — Max. 25 30 30 ns tGHQZ tDF Output Enable to Output HIGH-Z — Max. 25 30 30 ns tAXQX tOH Output Hold Time From Address, CE or OE, Whichever Occurs First —M i n . 0 0 0 n s —t READY RESET Pin Low to Read Mode — Max. 20 20 20 ms — tELFL tELFH CE or BYTE Switching Low or High — Max. 5 5 5 ns 2.7 kW 3.3 V IN3064 or Equivalent 6.2 kW C L Device Under Test Diodes = IN3064 or Equivalent Figure 4 Test Conditions

  • Write (Erase/Program) Operations (Continued) Parameter Symbols Description 70 90 12 Unit JEDEC Standard tAVAV tWC Write Cycle Time Min. 70 90 120 ns tAVWL tAS Address Setup Time Min. 0 0 0 ns tWLAX tAH Address Hold Time Min. 45 45 50 ns tDVWH tDS Data Setup Time Min. 35 45 50 ns tWHDX tDH Data Hold Time Min. 0 0 0 ns —t OES Output Enable Setup Time Min. 0 0 0 ns —t OEH Output Enable Hold Time Read Min. 0 0 0 ns T oggle and Data Polling Min. 10 10 10 ns tGHWL tGHWL Read Recover Time Before Write Min. 0 0 0 ns tGHEL tGHEL Read Recover Time Before Write (OE High to CE Low) Min. 0 0 0 ns tELWL tCS CE Setup Time Min. 0 0 0 ns tWLEL tWS WE Setup Time Min. 0 0 0 ns tWHEH tCH CE Hold Time Min. 0 0 0 ns tEHWH tWH WE Hold Time Min. 0 0 0 ns tWLWH tWP Write Pulse Width Min. 35 45 50 ns tELEH tCP CE Pulse Width Min. 35 45 50 ns tWHWL tWPH Write Pulse Width High Min. 25 25 30 ns tEHEL tCPH CE Pulse Width High Min. 25 25 30 ns tWHWH1 tWHWH1 Programming Operation Byte Typ. 888 µs Word 16 16 16 tWHWH2 tWHWH2 Sector Erase Operation (Note 1) Typ. 1 1 1 s —t VCS VCC Setup Time Min. 50 50 50 µs —t VIDR Rise Time to VID (Note 2) Min. 500 500 500 ns —t VLHT Voltage T ransition Time (Note 2) Min. 4 4 4 µs —t WPP Write Pulse Width (Note 2) Min. 100 100 100 µs —t OESP OE Setup Time to WE Active (Note 2) Min. 4 4 4 µs —t CSP CE Setup Time to WE Active (Note 2) Min. 4 4 4 µs —t RB Recover Time From RY/BY Min. 0 0 0 ns

(Continued) Notes: 1. This does not include the preprogramming time. 2. This timing is for Sector Protection operation. Parameter Symbols D e s c r i p t i o n 7 09 01 2 U n i t JEDEC Standard —t RP RESET Pulse Width Min. 500 500 500 ns —t RH RESET High Level Period Before Read Min. 200 200 200 ns —t BUSY Program/Erase Valid to RY/BY D e l a y M a x . 9 09 09 0 n s —t EOE Delay Time from Embedded Output Enable Max. 70 90 120 ns —t FLQZ BYTE Switching Low to Output HIGH-Z Max. 30 35 50 ns —t FHQV BYTE Switching High to Output Active Min. 30 35 50 ns —t TOW Erase Time-out Time Min. 50 50 50 µs —t SPD Erase Suspend T ransition Time Max. 20 20 20 µs

n ERASE AND PROGRAMMING PERFORMANCE n PIN CAPACITANCE Note: T est conditions TA = 25°C, f = 1.0 MHz Parameter Limits Unit Comments Min. Typ. Max. Sector Erase Time — 1 10 s Excludes programming time prior to erasure Byte Programming Time — 8 300 µs Excludes system-level overheadWord Programming Time — 16 360 Chip Programming Time — 16.8 50 s Excludes system-level overhead Erase/Program Cycle 100,000 — — cycle — Parameter Symbol Test Setup Typ. Max. Unit Input Capacitance C IN VIN = 0 6 7.5 pF Output Capacitance C OUT VOUT = 0 8 10 pF Control Pin Capacitance C IN2 VIN = 0 7.5 9 pF

  • Key to Switching Waveforms WAVEFORM INPUTS Must Be Steady May Change from H to L May Change from L to H “H” or “L”; Any Change Permitted Does Not Apply OUTPUTS Will Be Steady Will Be Change from H to L Will Be Change from L to H Changing, State Unknown Center Line Is High- Impedance “Off” State Output Valid WE OE CE tACC tDF tOHtCE tOE Outputs tRC Addresses Addresses Stable tOEH HIGH-Z HIGH-Z Figure 5.1 Read Operation Timing Diagram

Figure 5.2 Hardware Reset/Read Operation Timing Diagram RESET tACC tOH Outputs t RC Addresses Addresses Stable High-Z Output Valid tRH

Notes: 1. P A is address of the memory location to be programmed. 2. PD is data to be programmed at word address. 3. DQ 7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the ·16 mode. (The addresses differ from ·8 mode.) Figure 6 Alternate WE Controlled Program Operation Timing Diagram

Figure 7 Alternate CE Controlled Program Operation Timing Diagram Notes: 1. P A is address of the memory location to be programmed. 2. PD is data to be programmed at word address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the ·16 mode. (The addresses differ from ·8 mode.)

555H 2AAH 555H 555H 2AAH SA* tGHWL tWP tCS tCH tDS tVCS tWPH tAH AAH 10H55H 80H AAH 55H 30H for Sector Erase Figure 8 Chip/Sector Erase Operation Timing Diagram * : 1. SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte) for Chip Erase. 2. These waveforms are for the ·16 mode. (The addresses differ from ·8 mode.)

DQ 7 = Valid Data DQ 0 to DQ6 Valid Data DQ 7 DQ 7 DQ 0 to DQ6 RY/BY Data DQ 0 to DQ6 = Output Flag Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram * : DQ7 = Valid Data (The device has completed the Embedded operation).

Figure 17 Sector Protection Timing Diagram SAX : Sector Address for initial sector SAY : Sector Address for next sector Note: A-1 is VIL on byte mode. tVLHT SAX A19, A18, A17 A16, A15, A14 A13, A12 SAY 3 V tVLHT OE 3 V t VLHTtVLHT tOESP tWPP tCSP WE CE tOE 01HData VCC tVCS VID VID

tVLHT Program or Erase Command Sequence 3 V tVLHT tVCS tVIDR VID tVLHT Unprotection period Figure 18 Temporary Sector Unprotection Timing Diagram

Figure 19 Extended Sector Protection Timing Diagram SP AX : Sector Address to be protected SP AY : Next Sector Address to be protected TIME-OUT : Time-Out window = 250 ms (min) SPAY RESET OE WE CE Data VCC Add SPAXSPAX 60H01H40H60H60H TIME-OUT tVCS tVLHT tVIDR tOE tWP tWC tWC

(See Below) No No Yes Yes Increment Address Last Address Verify Byte Program Command Sequence* (Address/Command) : 555H/AAH 2AAH/55H 555H/A0H Program Address/Program Data Data Polling Davice Programming Completed Start Figure 20 Embedded ProgramTM Algorithm * : The sequence is applied for ·16 mode. The addresses differ from ·8 mode. EMBEDDED ALGORITHM

Chip Erase Command Sequence* (Address/Command) : 555H/AAH 2AAH/55H 555H/AAH 555H/80H 555H/10H 2AAH/55H Individual Sector/Multlple Sector* Erase Command Sequence (Address/Command) : 555H/AAH 2AAH/55H 555H/AAH 555H/80H Sector Address /30H 2AAH/55H Sector Address /30H Sector Address /30H Additional sector erase commands are optional. Write Erase Command Sequence (See Below) No Yes Data = FFH Data Polling or Toggle Bit from Device Start Erasure Completed Figure 21 Embedded EraseTM Algorithm * : The sequence is applied for ·16 mode. The addresses differ from ·8 mode. EMBEDDED ALGORITHM

DQ 7 = Data ? No No DQ 7 = Data ? DQ 5 = 1 ? Yes Yes Yes No Read Byte (DQ 0 to DQ7) Addr. = VA Read Byte (DQ 0 to DQ7) Addr. = VA Start Fail Pass Figure 22 Data Polling Algorithm * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. VA =Address for programming =Any of the sector addresses within the sector being erased during sector erase or multiple erases operation. =Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation.

DQ 6 = Toggle ? * Yes No DQ 6 = Toggle DQ 5 = 1 ? Yes No No Yes Read (DQ 0 to DQ7) Addr. = “H” or “L” Read Byte (DQ 0 to DQ7) Addr. = “H” or “L” Start Fail Pass Figure 23 Toggle Bit Algorithm * : DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ 5 changing to “1”.

Setup Sector Addr, (A19, A18, A17, A16, A15, A14, A13, A12) Activate WE Pulse WE = VIH, CE = OE = VIL (A9 should remain VID) Data = 01H ? Protect Another Sector Sector Protection Completed Device Failed PLSCNT = 25 ? Yes Yes No No PLSCNT = 1 Time out 100 µs Read from Sector (A1 = VIH, A0 = VIL Addr. = SA, A6 = VIL) * Remove V ID from A9 Write Reset Command Pemove V ID from A9 Write Reset Command Increment PLSCNT No Yes OE = VID, A9 = VID A6 = CE = VIL, RESET = VIH A0 = VIL, A1 = VIH Figure 24 Sector Protection Algorithm * : A-1 is VIL on byte mode.

RESET = VID (Note 1) RESET = VIH Temporary Sector Unprotection Completed (Note 2) Start Figure 25 Temporary Sector Unprotection Algorithm Notes: 1. All protected sectors are unprotected. 2. All previously protected sectors are protected once again.

Increment Address Last Address XXXXH/90H XXXXH/F0H 555H/AAH 2AAH/55H 555H/20H XXXXH/A0H Program Address/Program Data Data Polling Device Programming Completed Reset Fast Mode Set Fast Mode* in Fast Program Start Verify Byte ? Figure 26 Embedded Programming Algorithm for Fast Mode * : The sequence is applied for ·16 mode. * : The addresses differ from ·8 mode. FAST MODE ALGORITHM

RESET = VID PLSCNT = 1 Sector Protection Completed Device Failed Yes Yes No No Wait to 4 µs Time Out 250 µs Remove V ID from RESET Write Reset Command Increment PLSCNT No Yes Yes Device Is Operating in Temporary Sector Unprotect Mode To Setup Sector Protect Write XXXH/60H To Sector Protect Write 60H to Sector Address (A0 = V1L, A1 = VIH, A6 = VIL) Setup Next Sector Address No To Verify Sector Protect Write 40H to Sector Address (A0 = V1L, A1 = VIH, A6 = VIL) Read from Sector Protect (A0 = V1L, A1 = VIH, A6 = VIL) Remove V ID from RESET Write Reset Command Extended Sector Protect Entry ? Data = 01H ? Protect Other Sector PLSCNT = 25 ? Figure 27 Extended Sector Protection Algorithm

Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29LV160 T E 70 TN DEVICE NUMBER/DESCRIPTION MBM29LV160

16 Mega-bit (2M · 8-Bit or 1M · 16-Bit) CMOS Flash Memory

3.0 V-only Read, Write, and Erase

TN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout TR = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout PCV = 48-Pin C- leaded Small Outline Package (CSOP) PBT = 48-Pin Fine Pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION BOOT CODE SECTOR ARCHITECTURE T = T op sector B = Bottom sector Valid Combinations MBM29LV160TE/BE TN TR PCV PBT Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.

(Continued) C 1996 FUJITSU LIMITED F48029S-2C-2 Details of "A" part 0.15(.006) MAX 0.35(.014) MAX INDEX "A" 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) 19.00±0.20 (.748±.008) 0.10(.004) 0.50±0.10 (.020±.004) 0.15±0.05 (.006±.002) 11.50REF (.460) 0.50(.0197) TYP 0.20±0.10 (.008±.004) 0.05(0.02)MIN .043–.002 +.004 –0.05 +0.10 1.10 M0.10(.004) (STAND OFF) 24 25 LEAD No. * 12.00±0.20 (.472±.008) (Mounting height Dimensions in mm (inches) 48-pin plastic TSOP (I) (FPT-48P-M19) *: Resin protruction. (Each side: 0.15(.006) Max)

(Continued) C 1996 FUJITSU LIMITED F48030S-2C-2 Details of "A" part 0.15(.006) MAX 0.35(.014) MAX INDEX "A" 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) 19.00±0.20 (.748±.008) 0.10(.004) 0.50±0.10 (.020±.004) 0.15±0.10 (.006±.002) 11.50(.460)REF 0.50(.0197) TYP 0.20±0.10 (.008±.004) 0.05(0.02)MIN .043–.002 +.004 –0.05 +0.10 1.10 M0.10(.004) (STAND OFF) 24 25 LEAD No. (Mounting height) Dimensions in mm (inches) 48-pin plastic TSOP (I) (FPT-48P-M20) *: Resin protrusion. (Each side: 0.15(.006) Max)

(Continued) C 1998 FUJITSU LIMITED C48056S-1C-1 TYP 9.20(.362)REF 1 24 2548 INDEX INDEX 9.50±0.10 (.374±.004) 10.00±0.20 (.394±.008) "A" 0.22±0.035 (.009±.001) .002–.0 +.002 +0.05 0.05 (Mounting height) (Stand off) 0.65(.026) 1.15(.045) Details of "A" part 0°~10° LEAD No. Dimensions in mm (inches) 48-pin plastic CSOP (LCC-48P-M03)

(Continued) C 1998 FUJITSU LIMITED B480011S-1C-1 (Stand off) (Mounting height) 6.00±0.20 (.236±.008) 0.10(.004) 0.80(.031)TYP 5.60(.221) 4.00(.157) 48-Ø0.45±0.10 (48-.018±.004) MØ0.08(.003) INDEX HGFEDCBA C0.25(.010) .041–.004 +.006 –0.10 +0.15 1.05 Dimensions in mm (inches) Note: The actual shape of corners may differ from the dimension. 48-pin plastic FBGA (BGA-48P-M11)

For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT , 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan T el: +81-44-754-3763 Fax: +81-44-754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, USA T el: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) T el: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany T el: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan, New T ech Park, Singapore 556741 T el: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ F0001 ª FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.