MX29LV160B MCNIX | Alldatasheet
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P/N:PM1041 REV. 1.2, JUL. 01, 2004 MX29LV160BT/BB 16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY erase operation completion.
- Ready/Busy pin (RY/BY) - Provides a hardware method of detecting program or erase operation completion. Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Temporary sector unprotect allows code changes in previously locked sectors. CFI (Common Flash Interface) compliant - Flash device parameters stored on the device and provide the host system to access 100,000 minimum erase/program cycles Latch-up protected to 100mA from -1V to VCC+1V Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector Low VCC write inhibit is equal to or less than 1.4V Package type: - 44-pin SOP - 48-pin TSOP - 48-ball CSP Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash 10 years data retention
FEATURES
Extended single - supply voltage range 2.7V to 3.6V 2,097,152 x 8/1,048,576 x 16 switchable Single power supply operation - 3.0V only operation for read, erase and program operation Fully compatible with MX29LV160A device Fast access time: 70/90ns Low power consumption - 30mA maximum active current - 0.2uA typical standby current Command register architecture - Byte/word Programming (9us/11us typical) - Sector Erase (Sector structure 16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and 64K-Byte x31) Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically program and verify data at specified address Erase Suspend/Erase Resume - Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase. Status Reply - Data polling & Toggle bit for detection of program and GENERAL DESCRIPTION The MX29LV160BT/BB is a 16-mega bit Flash memory organized as 2M bytes of 8 bits or 1M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV160BT/BB is packaged in 44-pin SOP , 48-pin TSOP and 48-ball CSP . It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29LV160BT/BB offers access time as fast as 70ns, allowing operation of high-speed micropro- cessors without wait states. To eliminate bus conten- tion, the MX29LV160BT/BB has separate chip enable (CE) and output enable (OE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV160BT/BB uses a command register to man- age this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy- cling. The MX29LV160BT/BB uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V. R
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R PIN CONFIGURATIONS PIN DESCRIPTION SYMBOL PIN NAME A0~A19 Address Input Q0~Q14 Data Input/Output Q15/A-1 Q15(Word mode)/LSB addr(Byte mode) CE Chip Enable Input WE Write Enable Input BYTE Word/Byte Selection input RESET Hardware Reset Pin/Sector Protect Unlock OE Output Enable Input RY/BY Ready/Busy Output VCC Power Supply Pin (2.7V~3.6V) GND Ground Pin
48 TSOP (Standard Type) (12mm x 20mm)
44 SOP(500 mil)
6 A13 A12 A14 A15 A16 BYTE Q15/A-1 GND
5 A9 A8 A10 A11 Q7 Q14 Q13 Q6
4 WE RESET NC A19 Q5 Q12 VCC Q4
3 RY/BY NC A18 NC Q2 Q10 Q11 Q3
2 A7 A17 A6 A5 Q0 Q8 Q9 Q1
1 A 3A 4A 2A 1A 0C EO E G N D
48-Ball CSP 6mm x 8mm (Ball Pitch=0.8mm) Top View, Balls Facing Down RESET A18 A17 CE GND OE Q10 Q11 WE A19 A10 A11 A12 A13 A14 A15 A16 BYTE GND Q15/A-1 Q14 Q13 Q12 VCC MX29LV160BT/BB A15 A14 A13 A12 A11 A10 A19 NC WE RESET NC NC RY/BY A18 A17 A16 BYTE GND Q15/A-1 Q14 Q13 Q12 VCC Q11 Q10 OE GND CE MX29LV160BT/BB
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R BLOCK STRUCTURE Sector Sector Size Address range Sector Address Byte Mode Word Mode Byte Mode(x8) Word Mode(x16) A19 A18 A17 A16 A15 A14 A13 A12 SA0 64Kbytes 32Kwords 000000-00FFFF 00000-07FFF 00000XX X SA1 64Kbytes 32Kwords 010000-01FFFF 08000-0FFFF 00001XX X SA2 64Kbytes 32Kwords 020000-02FFFF 10000-17FFF 00010XX X SA3 64Kbytes 32Kwords 030000-03FFFF 18000-1FFFF 00011XX X SA4 64Kbytes 32Kwords 040000-04FFFF 20000-27FFF 00100XX X SA5 64Kbytes 32Kwords 050000-05FFFF 28000-2FFFF 00101XX X SA6 64Kbytes 32Kwords 060000-06FFFF 30000-37FFF 00110XX X SA7 64Kbytes 32Kwords 070000-07FFFF 38000-3FFFF 00111XX X SA8 64Kbytes 32Kwords 080000-08FFFF 40000-47FFF 01000XX X SA9 64Kbytes 32Kwords 090000-09FFFF 48000-4FFFF 01001XX X SA10 64Kbytes 32Kwords 0A0000-0AFFFF 50000-57FFF 01010XX X SA11 64Kbytes 32Kwords 0B0000-0BFFFF 58000-5FFFF 01011XX X SA12 64Kbytes 32Kwords 0C0000-0CFFFF 60000-67FFF 01100XX X SA13 64Kbytes 32Kwords 0D0000-0DFFFF 68000-6FFFF 01101XX X SA14 64Kbytes 32Kwords 0E0000-0EFFFF 70000-77FFF 01110XX X SA15 64Kbytes 32Kwords 0F0000-0FFFFF 78000-7FFFF 01111XX X SA16 64Kbytes 32Kwords 100000-10FFFF 80000-87FFF 10000XX X SA17 64Kbytes 32Kwords 110000-11FFFF 88000-8FFFF 10001XX X SA18 64Kbytes 32Kwords 120000-12FFFF 90000-97FFF 10010XX X SA19 64Kbytes 32Kwords 130000-13FFFF 98000-9FFFF 10011XX X SA20 64Kbytes 32Kwords 140000-14FFFF A0000-A7FFF 10100XX X SA21 64Kbytes 32Kwords 150000-15FFFF A8000-AFFFF 10101XX X SA22 64Kbytes 32Kwords 160000-16FFFF B0000-B7FFF 10110XX X SA23 64Kbytes 32Kwords 170000-17FFFF B8000-BFFFF 10111XX X SA24 64Kbytes 32Kwords 180000-18FFFF C0000-C7FFF 11000XX X SA25 64Kbytes 32Kwords 190000-19FFFF C8000-CFFFF 11001XX X SA26 64Kbytes 32Kwords 1A0000-1AFFFF D0000-D7FFF 11010XX X SA27 64Kbytes 32Kwords 1B0000-1BFFFF D8000-DFFFF 11011XX X SA28 64Kbytes 32Kwords 1C0000-1CFFFF E0000-E7FFF 11100XX X SA29 64Kbytes 32Kwords 1D0000-1DFFFF E8000-EFFFF 11101XX X SA30 64Kbytes 32Kwords 1E0000-1EFFFF F0000-F7FFF 11110XX X SA31 32Kbytes 16Kwords 1F0000-1F7FFF F8000-FBFFF 111110X X SA32 8Kbytes 4Kwords 1F8000-1F9FFF FC000-FCFFF 1111110 0 SA33 8Kbytes 4Kwords 1FA000-1FBFFF FD000-FDFFF 1111110 1 SA34 16Kbytes 8Kwords 1FC000-1FFFFF FE000-FFFFF 1111111 X Table 1: MX29LV160BT SECTOR ARCHITECTURE Note: Byte mode: address range A19:A-1, word mode:address range A19:A0.
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R Sector Sector Size Address range Sector Address Byte Mode Word Mode Byte Mode (x8) Word Mode (x16) A19 A18 A17 A16 A15 A14 A13 A12 SA0 16Kbytes 8Kwords 000000-003FFF 00000-01FFF 0000000 X SA1 8Kbytes 4Kwords 004000-005FFF 02000-02FFF 0000001 0 SA2 8Kbytes 4Kwords 006000-007FFF 03000-03FFF 0000001 1 SA3 32Kbytes 16Kwords 008000-00FFFF 04000-07FFF 000001X X SA4 64Kbytes 32Kwords 010000-01FFFF 08000-0FFFF 00001XX X SA5 64Kbytes 32Kwords 020000-02FFFF 10000-17FFF 00010XX X SA6 64Kbytes 32Kwords 030000-03FFFF 18000-1FFFF 00011XX X SA7 64Kbytes 32Kwords 040000-04FFFF 20000-27FFF 00100XX X SA8 64Kbytes 32Kwords 050000-05FFFF 28000-2FFFF 00101XX X SA9 64Kbytes 32Kwords 060000-06FFFF 30000-37FFF 00110XX X SA10 64Kbytes 32Kwords 070000-07FFFF 38000-3FFFF 00111XX X SA11 64Kbytes 32Kwords 080000-08FFFF 40000-47FFF 01000XX X SA12 64Kbytes 32Kwords 090000-09FFFF 48000-4FFFF 01001XX X SA13 64Kbytes 32Kwords 0A0000-0AFFFF 50000-57FFF 01010XX X SA14 64Kbytes 32Kwords 0B0000-0BFFFF 58000-5FFFF 01011XX X SA15 64Kbytes 32Kwords 0C0000-0CFFFF 60000-67FFF 01100XX X SA16 64Kbytes 32Kwords 0D0000-0DFFFF 68000-6FFFF 01101XX X SA17 64Kbytes 32Kwords 0E0000-0EFFFF 70000-77FFF 01110XX X SA18 64Kbytes 32Kwords 0F0000-0FFFFF 78000-7FFFF 01111XX X SA19 64Kbytes 32Kwords 100000-10FFFF 80000-87FFF 10000XX X SA20 64Kbytes 32Kwords 110000-11FFFF 88000-8FFFF 10001XX X SA21 64Kbytes 32Kwords 120000-12FFFF 90000-97FFF 10010XX X SA22 64Kbytes 32Kwords 130000-13FFFF 98000-9FFFF 10011XX X SA23 64Kbytes 32Kwords 140000-14FFFF A0000-A7FFF 10100XX X SA24 64Kbytes 32Kwords 150000-15FFFF A8000-AFFFF 10101XX X SA25 64Kbytes 32Kwords 160000-16FFFF B0000-B7FFF 10110XX X SA26 64Kbytes 32Kwords 170000-17FFFF B8000-BFFFF 10111XX X SA27 64Kbytes 32Kwords 180000-18FFFF C0000-C7FFF 11000XX X SA28 64Kbytes 32Kwords 190000-19FFFF C8000-CFFFF 11001XX X SA29 64Kbytes 32Kwords 1A0000-1AFFFF D0000-D7FFF 11010XX X SA30 64Kbytes 32Kwords 1B0000-1BFFFF D8000-DFFFF 11011XX X SA31 64Kbytes 32Kwords 1C0000-1CFFFF E0000-E7FFF 11100XX X SA32 64Kbytes 32Kwords 1D0000-1DFFFF E8000-EFFFF 11101XX X SA33 64Kbytes 32Kwords 1E0000-1EFFFF F0000-FFFFF 11110XX X SA34 64Kbytes 32Kwords 1F0000-1FFFFF F8000-FFFFF 11111XX X Table 2: MX29LV160BB SECTOR ARCHITECTURE Note: Byte mode:address range A19:A-1, word mode:address range A19:A0.
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R BLOCK DIAGRAM CONTROL INPUT LOGIC PROGRAM/ERASE HIGH VOLTAGE WRITE STATE MACHINE (WSM) STATE REGISTER FLASH ARRAY X-DECODER ADDRESS LATCH AND BUFFER Y -PASS GATE Y -DECODER ARRAY SOURCE HV COMMAND DATA DECODER COMMAND DATA LATCH I/O BUFFER PGM DATA HV PROGRAM DATA LATCH SENSE AMPLIFIER Q0-Q15/A-1 A0-A19 CE OE WE RESET
less than 18 sec (byte)/12 sec (word). gram verification, and counts the number of sequences. more information on these status bits. according to MXIC's Automatic Chip Erase algorithm. are controlled internally within the device. one sector, multiple sectors, or the entire device. status of the erasing operation. ter to respond to its full command set. vice to be programmed with its programming algorithm. Table 3. In addition, to access the automatic select codes
TABLE 3. MX29LV160BT/BB AUTO SELECT MODE BUS OPERATION (A9=VID)
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX29LV160BT/BB is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating param- eters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in Table 4. The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Automatic Select mode; however, it is ignored otherwise. The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or Automatic Se- lect mode. The command is valid only when the device is in the CFI mode. Table 4-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Address Address Data (Byte Mode) (Word Mode) Query-unique ASCII string "QRY" 20 10 0051 22 11 0052 24 12 0059 Primary vendor command set and control interface ID code 26 13 0002 28 14 0000 Address for primary algorithm extended query table 2A 15 0040 2C 16 0000 Alternate vendor command set and control interface ID code (none) 2E 17 0000 30 18 0000 Address for secondary algorithm extended query table (none) 32 19 0000 34 1A 0000 Table 4-2. CFI Mode: System Interface Data Values (All values in these tables are in hexadecimal) Description Address Address Data (Byte Mode) (Word Mode) VCC supply, minimum (2.7V) 36 1B 0027 VCC supply, maximum (3.6V) 38 1C 0036 VPP supply, minimum (none) 3A 1D 0000 VPP supply, maximum (none) 3C 1E 0000 Typical timeout for single word/byte write (2N us) 3E 1F 0004 Typical timeout for Minimum size buffer write (2N us) (not supported) 40 20 0000 Typical timeout for individual sector erase (2N ms) 42 21 000A Typical timeout for full chip erase (2N ms) 44 22 0000 Maximum timeout for single word/byte write times (2N X Typ) 46 23 0005 Maximum timeout for buffer write times (2N X Typ) 48 24 0000 Maximum timeout for individual sector erase times (2N X Typ) 4A 25 0004 Maximum timeout for full chip erase times (not supported) 4C 26 0000
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R Table 4-3. CFI Mode: Device Geometry Data Values (All values in these tables are in hexadecimal) Description Address Address Data (Byte Mode) (Word Mode) Device size (2N bytes) 4E 27 0015 Flash device interface code (x8/x16 async.) 50 28 0002 52 29 0000 Maximum number of bytes in multi-byte write (not supported) 54 2A 0000 56 2B 0000 Number of erase sector regions 58 2C 0004 Erase sector region 1 information (refer to the CFI publication 100) 5A 2D 0000 5C 2E 0000 5E 2F 0040 60 30 0000 Erase sector region 2 information 62 31 0001 64 32 0000 66 33 0020 68 34 0000 Erase sector region 3 information 6A 35 0000 6C 36 0000 6E 37 0080 70 38 0000 Erase sector region 4 information 72 39 001E 74 3A 0000 76 3B 0000 78 3C 0001 Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values (All values in these tables are in hexadecimal) Description Address Address Data (Byte Mode) (Word Mode) Query-unique ASCII string "PRI" 80 40 0050 82 41 0052 84 42 0049 Major version number, ASCII 86 43 0031 Minor version number, ASCII 88 44 0030 Address sensitive unlock (0=required, 1= not required) 8A 45 0000 Erase suspend (2= to read and write) 8C 46 0002 Sector protect (N= # of sectors/group) 8E 47 0001 Temporary sector unprotect (1=supported) 90 48 0001 Sector protect/chip unprotect scheme 92 49 0004 Simultaneous R/W operation (0=not supported) 94 4A 0000 Burst mode type (0=not supported) 96 4B 0000 Page mode type (0=not supported) 98 4C 0000
Sector Erase operation is in progress. dress and data sequences into the command register. TABLE 5. MX29LV160BT/BB COMMAND DEFINITIONS
- ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A19=do not care.
DDI = Data of Device identifier : C2H for manufacture code, C4H/49H (x8) and 22C4H/2249H (x16) for device code. RA=Address of memory location to be read. RD=Data to be read at location RA. 2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address of the sector to be erased. 555H to Address A10~A-1 in byte mode. Address (SA). Write Sequence may be initiated with A11~A19 in either state.
- For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,
it means the sector is still not being protected.
- Any number of CFI data read cycles are permitted.
TABLE 6. MX29LV160BT/BB BUS OPERATION
- Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.
- VID is the high voltage, 11.5V to 12.5V .
- Refer to Table 5 for valid Data-In during a write operation.
- Code=00H/XX00H means unprotected.
Code=01H/XX01H means protected.
- A19~A12=Sector address for sector protect.
- The sector protect and chip unprotect functions may also be implemented via programming equipment.
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con- tent occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory, the system must drive WE and CE to VIL, and OE to VIH. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 1 and Table 2 indicate the address space that each sector occupies. A "sector ad- dress" consists of the address bits required to uniquely select a sector. The Writing specific address and data commands or sequences into the command register ini- tiates device operations. Table 5 defines the valid regis- ter command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has de- tails on erasing a sector or the entire chip, or suspend- ing/resuming the erase operation. After the system writes the "read silicon-ID" and "sector protect verify" command sequence, the device enters the "read silicon-ID" and "sector protect verify" mode. The system can then read "read silicon-ID" and "sector protect verify" codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the "read silicon-ID" and "sector protect verify" Mode and "read silicon-ID" and "sector protect verify" Command Se- quence section for more information. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODE When using both pins of CE and RESET, the device enter CMOS Standby with both pins held at Vcc ± 0.3V. If CE and RESET are held at VIH, but not within the range of VCC ± 0.3V , the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (ICC2) is required even CE = "H" until the operation is completed. The de- vice can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data. OUTPUT DISABLE With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. RESET OPERATION The RESET pin provides a hardware method of reset- ting the device to reading array data. When the RESET pin is driven low for at least a period of tRP , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write com- mands for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be re- initiated once the device is ready to accept another com- mand sequence, to ensure data integrity. Current is reduced for the duration of the RESET pulse. When RESET is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS±0.3V, the standby current will be greater. The RESET pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET is asserted during a program or erase opera-
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R READ/RESET COMMAND The read or reset operation is initiated by writing the read/reset command sequence into the command reg- ister. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid com- mand must then be written to place the device in the desired state. SILICON-ID READ COMMAND Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manu- facturer and device codes must be accessible while the device resides in the target system. PROM program- mers typically access signature codes by raising A9 to a high voltage (VID). However, multiplexing high volt- age onto address lines is not generally desired system design practice. The MX29LV160BT/BB contains a Silicon-ID-Read op- eration to supple traditional PROM programming meth- odology. The operation is initiated by writing the read silicon ID command sequence into the command regis- ter. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of C4H/22C4H for MX29LV160BT, 49H/ 2249H for MX29LV160BB. The system must write the reset command to exit the "Silicon-ID Read Command" code. AUTOMATIC CHIP ERASE COMMANDS Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cy- cles are then followed by the chip erase command 10H. The device does not require the system to entirely pre- program prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is auto- matically verified to contain an all-zero pattern, a self- timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). If the Erase operation was unsuccessful, the data on Q5 is "1" (see Table 8), indicating the erase operation exceed internal timing limit. The automatic erase begins on the rising edge of the last WE or CE pulse, whichever happens first in the command sequence and terminates when either the data on Q7 is "1" at which time the device returns to the Read mode or the data on Q6 stops toggling for two consecutive read cycles at which time the device re- turns to the Read mode. tion, the RY/BY pin remains a "0" (busy) until the inter- nal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY to determine whether the reset op- eration is complete. If RESET is asserted when a pro- gram or erase operation is completed within a time of tREADY (not during Embedded Algorithms). The sys- tem can read data tRH after the RESET pin returns to VIH. Refer to the AC Characteristics tables for RESET parameters and to Figure 22 for the timing diagram.
Resume Commands ” for more information on this mode. mode. See the "Reset Command" section, next. reset commands until the operation is complete. (also applies to Automatic Select during Erase Suspend). array data (also applies during Erase Suspend). TABLE 7. SILICON ID CODE
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R SECTOR ERASE COMMANDS The device does not require the system to entirely pre- program prior to executing the Automatic Sector Erase Set-up command and Automatic Sector Erase com- mand. Upon executing the Automatic Sector Erase com- mand, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when either the data on Q7 is "1" at which time the de- vice returns to the Read mode or the data on Q6 stops toggling for two consecutive read cycles at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "un- lock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE or CE, whichever happens later, while the command (data) is latched on the rising edge of WE or CE, which- ever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE or CE, whichever happens later. Each successive sector load cycle started by the falling edge of WE or CE, whichever happens later must begin within 50us from the rising edge of the preceding WE or CE, which- ever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase (30H) or Erase Suspend (B0H) during the time-out period resets the device to read mode. ERASE SUSPEND This command only has meaning while the state ma- chine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend Com- mand is issued during the sector erase operation, the device requires a maximum 20us to suspend the sector erase operation. However, when the Erase Suspend com- mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to re- spond to Erase Resume, program data to , or read data from any sector not selected for erasure. The system can use Q7 or Q6 and Q2 together, to determine if a sector is actively erasing or is erase-suspend. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended sectors. ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing. However, for MX29LV160BT/BB, a 10ms time delay must be re- quired after the erase resume command, if the system implements a endless erase suspend/resume loop, or the number of erase suspend/resume is exceeded 1024 times. The erase times will be expended if the erase behavior always be suspended. (Please refer to MXIC Flash Application Note for details.) Please note that the above 10ms time delay is not necessary for MX29LV160BT/BB. WORD/BYTE PROGRAM COMMAND SEQUENCE The device programs one byte of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 5 shows the address
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Q7, Q6, or RY/BY . See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte/Word Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may cause the device to set Q5 to "1", or cause the Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/ BY . Table 8 and the following subsections describe the functions of these bits. Q7, RY/BY , and Q6 each offer a method for determining whether a program or erase op- eration is complete or in progress. These three bits are discussed first. Q7: Data Polling The Data Polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or com- pleted, or whether the device is in Erase Suspend. Data Polling is valid after the rising edge of the final WE pulse in the program or erase command sequence. During the Automatic Program algorithm, the device out- puts on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to programming dur- ing Erase Suspend. When the Automatic Program algo- rithm is complete, the device outputs the datum pro- grammed to Q7. The system must provide the program address to read valid status information on Q7. If a pro- gram address falls within a protected sector, Data Poll- ing on Q7 is active for approximately 1 us, then the de- vice returns to reading array data. During the Automatic Erase algorithm, Data Polling pro- duces a "0" on Q7. When the Automatic Erase algo- rithm is complete, or if the device enters the Erase Sus- pend mode, Data Polling produces a "1" on Q7. This is analogous to the complement/true datum output de- scribed for the Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement,” or "0".” The system must provide an address within any of the sec- tors selected for erasure to read valid status information on Q7. After an erase command sequence is written, if all sec- tors selected for erasing are protected, Data Polling on Q7 is active for approximately 100 us, then the device returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchronously with Q0-Q6 while Output En- able (OE) is asserted low. RY/BY : Ready/Busy The RY/BY is a dedicated, open-drain output pin that indicates whether an Automatic Erase/Program algorithm is in progress or complete. The RY/BY status is valid after the rising edge of the final WE or CE, whichever happens first, in the command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to Vcc. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the de- vice is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 8 shows the outputs for RY/BY during write opera- tion.
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R During an Automatic Program or Erase algorithm opera- tion, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to con- trol the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sec- tors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase sus- pended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-sus- pended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program com- mand sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algo- rithm is complete. Table 8 shows the outputs for Toggle Bit I on Q6. Q2:Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE or CE, whichever happens first, in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by com- parison, indicates whether the device is actively eras- ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 7 to compare outputs for Q2 and Q6. Reading Toggle Bits Q6/ Q2 Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase op- eration. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. Alterna- tively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Q5 : Exceeded Timing Limits Q5 will indicate if the program or erase time has ex- Q6:Toggle BIT I Toggle Bit I on Q6 indicates whether an Automatic Pro- gram or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, whichever happens first, in the command sequence (prior to the program or erase operation), and during the sector time- out.
tion. The device must be reset to use other sectors. Table 8. WRITE OPERATION STATUS
- Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
- Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5: Exceeded Timing Limits " for more information. bination of sectors are bad. device was incorrectly used.
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R POW ER SUPPLY DECOUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be- tween its VCC and GND. POWER-UP SEQUENCE The MX29LV160BT/BB powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. TEMPORARY SECTOR UNPROTECT This feature allows temporary unprotection of previously protected sector to change data in-system. The Tempo- rary Sector Unprotect mode is activated by setting the RESET pin to VID (11.5V-12.5V). During this mode, for- merly protected sectors can be programmed or erased as un-protected sector. Once VID is remove from the RESET pin. All the previously protected sectors are pro- tected again. Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase com- mand sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the com- mand has been accepted, the system software should check the status of Q3 prior to and following each sub- sequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. DATA PROTECTION The MX29LV160BT/BB is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically re- sets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down tran- sition or system noise. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns (typical) on OE, CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. SECTOR PROTECTION The MX29LV160BT/BB features hardware sector pro- tection. This feature will disable both program and erase operations for these sectors protected. To activate this mode, the programming equipment must force VID on address pin A9 and OE (suggest VID = 12V). Program- ming of the protection circuitry begins on the falling edge of the WE pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform. To verify programming of the protection circuitry, the pro- gramming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes. (Read Silicon ID) It is also possible to determine if the sector is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector.
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R CHIP UNPROTECT The MX29LV160BT/BB also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode. To activate this mode, the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH. Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE pulse and is terminated on the rising edge. It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed. The system must write the reset command to exit the "Silicon-ID Read Command" code.
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature oC to +125oC Voltage with Respect to Ground A9, OE, and Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may over- shoot VSS to -2.0 V for periods of up to 20 ns. Maxi- mum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may over- shoot to VCC +2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on pins A9, OE, and RESET is -0.5 V. During voltage transitions, A9, OE, and RESET may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. OPERATING RATINGS Commercial (C) Devices Industrial (I) Devices VCC Supply Voltages Operating ranges define those limits between which the functionality of the device is guaranteed.
1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns. VIL min. = -2.0V for pulse width is equal to or less than 20 ns. If VIH is over the specified maximum value, read operation cannot be guaranteed. 3.Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns. Table 9. DC CHARACTERISTICS TA = -40 oC TO 85oC, VCC = 2.7V~3.6V
- tDF is defined as the time at which the output achieves
the open circuit condition and data is no longer driven. Input pulse levels: 0V/3.0V. Input rise and fall times is equal to or less than 5ns. ing scope and jig) for 29LV160BT/BB-70. Reference levels for measuring timing: 1.5V. Table 10. READ OPERATIONS
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R SWITCHING TEST CIRCUITS SWITCHING TEST WAVEFORMS TEST POINTS 3.0V AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. OUTPUTINPUT DEVICE UNDER TEST DIODES=IN3064 OR EQUIVALENT CL 6.2K ohm 2.7K ohm +3.3V CL=100pF Including jig capacitance for MX29LV160BT/BB-90 CL=30pF Including jig capacitance for MX29LV160BT/BB-70
Figure 1. READ TIMING WAVEFORMS
- See the "Erase and Programming Performance" section for more information.
Table 11. Erase/Program Operations
- See the "Erase and Programming Performance" section for more information.
Table 12. Alternate CE Controlled Erase/Program Operations
Figure 2. COMMAND WRITE TIMING WAVEFORM
Figure 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM
Figure 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
Figure 5. CE CONTROLLED WRITE TIMING WAVEFORM 1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device. 2.Figure indicates the last two bus cycles of the command sequence.
Figure 6. AUTOMATIC CHIP ERASE TIMING WAVEFORM VA=Valid Address for reading status data(see "Write Operation Status").
Figure 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
Figure 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
Figure 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
Figure 10. ERASE SUSPEND/ERASE RESUME FLOWCHART
Figure 11. IN-SYSTEM SECTOR PROTECT/CHIP UNPROTECT TIMING WAVEFORM (RESET Control) Note: When sector protect, A6=0, A1=1, A0=0. When chip unprotect, A6=1, A1=1, A0=0.
Figure 12. SECTOR PROTECT TIMING WAVEFORM (A9, OE Control) Notes: tVLHT (Voltage transition time)=4us min. tOESP (OE setup time to WE active)=4us min.
Figure 13. SECTOR PROTECTION ALGORITHM (A9, OE Control)
Figure 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET=VID
Figure 15. IN-SYSTEM CHIP UNPROTECTION ALGORITHM WITH RESET=VID
Figure 16. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE Control)
Figure 17. CHIP UNPROTECTION ALGORITHM (A9, OE Control)
- It is recommended before unprotect whole chip, all sectors should be protected in advance.
Figure 18. DATA POLLING ALGORITHM NOTE : 1.VA=Valid address for programming or erasure.
Figure 19. TOGGLE BIT ALGORITHM Note:1.Read toggle bit twice to determine whether or not it is toggling.
- Recheck toggle bit because it may stop toggling as Q5 change to "1".
Figure 20. Data Polling Timings (During Automatic Algorithms) VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 21. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Figure 22. RESET TIMING WAVEFORM Table 13. AC CHARACTERISTICS
Figure 23. BYTE TIMING WAVEFORM FOR READ OPERATIONS (BYTE switching from byte
Figure 28. TEMPORARY SECTOR UNPROTECT ALGORITHM
- All previously protected sectors are protected again.
Note : 1. All protected sectors are temporary unprotected.
Figure 29. ID CODE READ TIMING WAVEFORM
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R MIN. MAX. Input Voltage with respect to GND on all pins except I/O pins -1.0V 12.5V Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V VCC Current -100mA +100mA Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time. LIMITS PARAMETER MIN. TYP.(2) MAX.(3) UNITS Sector Erase Time 0.7 15 sec Chip Erase Time 15 30 sec Byte Programming Time 9 300 us Word Programming Time 11 360 us Chip Programming Time Byte Mode 18 54 sec Word Mode 12 36 sec Erase/Program Cycles 100,000 Cycles LATCH-UP CHARACTERISTICS ERASE AND PROGRAMMING PERFORMANCE (1) Note: 1. Not 100% Tested, Excludes external system level over head. 2. Typical values measured at 25°C, 3V. 3. Maximum values measured at 85°C, 2.7V, 100,000 cycles.
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R PART NO. ACCESS OPERATING STANDBY P ACKAGE Remark TIME (ns) Current MAX. (mA) Current MAX. (uA) MX29LV160BTMC-70 70 30 5 44 Pin SOP MX29LV160BBMC-70 70 30 5 44 Pin SOP MX29LV160BTMC-90 90 30 5 44 Pin SOP MX29LV160BBMC-90 90 30 5 44 Pin SOP MX29LV160BTMI-70 70 30 5 44 Pin SOP MX29LV160BBMI-70 70 30 5 44 Pin SOP MX29LV160BTMI-90 90 30 5 44 Pin SOP MX29LV160BBMI-90 90 30 5 44 Pin SOP MX29LV160BTTC-70 70 30 5 48 Pin TSOP (Normal T ype) MX29LV160BBTC-70 70 30 5 48 Pin TSOP (Normal T ype) MX29LV160BTTC-90 90 30 5 48 Pin TSOP (Normal T ype) MX29LV160BBTC-90 90 30 5 48 Pin TSOP (Normal T ype) MX29LV160BTTI-70 70 30 5 48 Pin TSOP (Normal T ype) MX29LV160BBTI-70 70 30 5 48 Pin TSOP (Normal T ype) MX29LV160BTTI-90 90 30 5 48 Pin TSOP (Normal T ype) MX29LV160BBTI-90 90 30 5 48 Pin TSOP (Normal T ype) MX29LV160BTXBC-70 70 30 5 48 Ball CSP (ball size:0.3mm) MX29LV160BBXBC-70 70 30 5 48 Ball CSP (ball size:0.3mm) MX29LV160BTXBC-90 90 30 5 48 Ball CSP (ball size:0.3mm) MX29LV160BBXBC-90 90 30 5 48 Ball CSP (ball size:0.3mm) MX29LV160BTXBI-70 70 30 5 48 Ball CSP (ball size:0.3mm) MX29LV160BBXBI-70 70 30 5 48 Ball CSP (ball size:0.3mm) MX29LV160BTXBI-90 90 30 5 48 Ball CSP (ball size:0.3mm) MX29LV160BBXBI-90 90 30 5 48 Ball CSP (ball size:0.3mm)
ORDERING INFORMATION
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R PART NO. ACCESS OPERATING STANDBY P ACKAGE Remark TIME (ns) Current MAX. (mA) Current MAX. (uA) MX29LV160BTXEC-70 70 30 5 48 Ball CSP (ball size:0.4mm) MX29LV160BBXEC-70 70 30 5 48 Ball CSP (ball size:0.4mm) MX29LV160BTXEC-90 90 30 5 48 Ball CSP (ball size:0.4mm) MX29LV160BBXEC-90 90 30 5 48 Ball CSP (ball size:0.4mm) MX29LV160BTXEI-70 70 30 5 48 Ball CSP (ball size:0.4mm) MX29LV160BBXEI-70 70 30 5 48 Ball CSP (ball size:0.4mm) MX29LV160BTXEI-90 90 30 5 48 Ball CSP (ball size:0.4mm) MX29LV160BBXEI-90 90 30 5 48 Ball CSP (ball size:0.4mm) MX29LV160BTTC-70G 70 30 5 48 Pin TSOP PB free (Normal T ype) MX29LV160BBTC-70G 70 30 5 48 Pin TSOP PB free (Normal T ype) MX29LV160BTTC-90G 90 30 5 48 Pin TSOP PB free (Normal T ype) MX29LV160BBTC-90G 90 30 5 48 Pin TSOP PB free (Normal T ype) MX29LV160BTTI-70G 70 30 5 48 Pin TSOP PB free (Normal T ype) MX29LV160BBTI-70G 70 30 5 48 Pin TSOP PB free (Normal T ype) MX29LV160BTTI-90G 90 30 5 48 Pin TSOP PB free (Normal T ype) MX29LV160BBTI-90G 90 30 5 48 Pin TSOP PB free (Normal T ype) MX29LV160BTXBC-70G 70 30 5 48 Ball CSP PB free (ball size:0.3mm) MX29LV160BBXBC-70G 70 30 5 48 Ball CSP PB free (ball size:0.3mm) MX29LV160BTXBC-90G 90 30 5 48 Ball CSP PB free (ball size:0.3mm) MX29LV160BBXBC-90G 90 30 5 48 Ball CSP PB free (ball size:0.3mm)
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R PART NO. ACCESS OPERATING STANDBY P ACKAGE Remark TIME (ns) Current MAX. (mA) Current MAX. (uA) MX29LV160BTXBI-70G 70 30 5 48 Ball CSP PB free (ball size:0.3mm) MX29LV160BBXBI-70G 70 30 5 48 Ball CSP PB free (ball size:0.3mm) MX29LV160BTXBI-90G 90 30 5 48 Ball CSP PB free (ball size:0.3mm) MX29LV160BBXBI-90G 90 30 5 48 Ball CSP PB free (ball size:0.3mm) MX29LV160BTXEC-70G 70 30 5 48 Ball CSP PB free (ball size:0.4mm) MX29LV160BBXEC-70G 70 30 5 48 Ball CSP PB free (ball size:0.4mm) MX29LV160BTXEC-90G 90 30 5 48 Ball CSP PB free (ball size:0.4mm) MX29LV160BBXEC-90G 90 30 5 48 Ball CSP PB free (ball size:0.4mm) MX29LV160BTXEI-70G 70 30 5 48 Ball CSP PB free (ball size:0.4mm) MX29LV160BBXEI-70G 70 30 5 48 Ball CSP PB free (ball size:0.4mm) MX29LV160BTXEI-90G 90 30 5 48 Ball CSP PB free (ball size:0.4mm) MX29LV160BBXEI-90G 90 30 5 48 Ball CSP PB free (ball size:0.4mm)
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R
PACKAGE INFORMATION
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R 48-Ball CSP (for MX29LV160BTXBC/BTXBI/BBXBC/BBXBI)
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R 48-Ball CSP (for MX29LV160BTXEC/BTXEI/BBXEC/BBXEI)
P/N:PM1041 MX29LV160BT/BB REV. 1.2, JUL. 01, 2004 R
REVISION HISTORY
Revision No.Description Page Date 1.0 1. Added 90ns & pb-free information All MAR/16/2004 2. Removed 55R information All 3. Removed "Advanced Information" P1 1.1 1. To added data retention information P1 MAY/28/2004 1.2 1. To corrected CFI Query command address P10 JUL/01/2004 2. To added "PB free" remark P56,57
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