29LV017B-70

MX29LV017B MCNIX | Alldatasheet

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P/N:PM1086 REV. 1.1, DEC. 07, 2004 MX29LV017B 16M-BIT [2Mx8] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY

• Status Reply - Data# Polling & Toggle bit for detection of program and erase operation completion.  Ready/Busy# pin (RY/BY#) - Provides a hardware method of detecting program or erase operation completion.  Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Temporary sector unprotect allows code changes in previously locked sectors.  CFI (Common Flash Interface) compliant - Flash device parameters stored on the device and provide the host system to access  100,000 minimum erase/program cycles  Latch-up protected to 100mA from -1V to VCC+1V  Low VCC write inhibit is equal to or less than 1.4V  Package type: - 40-pin TSOP  Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash

FEATURES

 Extended single - supply voltage range 2.7V to 3.6V  2,097,152 x 8  Single power supply operation - 3.0V only operation for read, erase and program operation  Fast access time: 70/90ns

• Fully compatible with MX29LV017A decice  Low power consumption - 30mA maximum active current - 0.2uA typical standby current  Command register architecture - Byte Programming (9us typical) - Sector Erase (Sector structure 64K-Byte x32)  Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically program and verify data at specified address  Erase suspend/Erase Resume - Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase. GENERAL DESCRIPTION The MX29LV017B is a 16-mega bit Flash memory orga- nized as 2M bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. The MX29LV017B is packaged in 40-pin TSOP . It is designed to be repro- grammed and erased in system or in standard EPROM programmers. The standard MX29LV017B offers access time as fast as 70ns, allowing operation of high-speed microproces- sors without wait states. To eliminate bus contention, the MX29LV017B has separate chip enable (CE#) and output enable (OE#) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV017B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maxi- mum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy- cling. The MX29LV017B uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/ Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro- tection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V.

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 PIN CONFIGURATIONS PIN DESCRIPTION SYMBOL PIN NAME A0~A20 Address Input Q0~Q7 Data Input/Output CE# Chip Enable Input WE# Write Enable Input RESET# Hardware Reset Pin/Sector Protect Unlock OE# Output Enable Input RY/BY# Ready/Busy Output VCC Power Supply Pin (2.7V~3.6V) GND Ground Pin

40 TSOP (Standard Type) (10mm x 20mm)

WE# RESET# NC RY/BY# A18 A17 GND A20 A19 A10 VCC VCC NC OE# GND CE# MX29LV017B

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 BLOCK STRUCTURE Sector A20 A19 A18 A17 A16 Address Range (in hexadecimal) SA0 0 0 0 0 0 000000-00FFFF SA1 0 0 0 0 1 010000-01FFFF SA2 0 0 0 1 0 020000-02FFFF SA3 0 0 0 1 1 030000-03FFFF SA4 0 0 1 0 0 040000-04FFFF SA5 0 0 1 0 1 050000-05FFFF SA6 0 0 1 1 0 060000-06FFFF SA7 0 0 1 1 1 070000-07FFFF SA8 0 1 0 0 0 080000-08FFFF SA9 0 1 0 0 1 090000-09FFFF SA10 0 1 0 1 0 0A0000-0AFFFF SA11 0 1 0 1 1 0B0000-0BFFFF SA12 0 1 1 0 0 0C0000- 0CFFFF SA13 0 1 1 0 1 0D0000- 0DFFFF SA14 0 1 1 1 0 0E0000-0EFFFF SA15 0 1 1 1 1 0F0000-0FFFFF SA16 1 0 0 0 0 100000-10FFFF SA17 1 0 0 0 1 110000-11FFFF SA18 1 0 0 1 0 120000-12FFFF SA19 1 0 0 1 1 130000-13FFFF SA20 1 0 1 0 0 140000-14FFFF SA21 1 0 1 0 1 150000-15FFFF SA22 1 0 1 1 0 160000-16FFFF SA23 1 0 1 1 1 170000-17FFFF SA24 1 1 0 0 0 180000-18FFFF SA25 1 1 0 0 1 190000-19FFFF SA26 1 1 0 1 0 1A0000-1AFFFF SA27 1 1 0 1 1 1B0000-1BFFFF SA28 1 1 1 0 0 1C0000- 1CFFFF SA29 1 1 1 0 1 1D0000- 1DFFFF SA30 1 1 1 1 0 1E0000-1EFFFF SA31 1 1 1 1 1 1F0000-1FFFFF Table 1: MX29LV017B SECTOR ARCHITECTURE

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 BLOCK DIAGRAM CONTROL INPUT LOGIC PROGRAM/ERASE HIGH VOLTAGE WRITE STATE MACHINE (WSM) STATE REGISTER FLASH ARRAY X-DECODER ADDRESS LATCH AND BUFFER Y -PASS GATE Y -DECODER ARRAY SOURCE HV COMMAND DATA DECODER COMMAND DATA LATCH I/O BUFFER PGM DATA HV PROGRAM DATA LATCH SENSE AMPLIFIER Q0-Q7 A0-A20 CE# OE# WE# RESET#

gram verification, and counts the number of sequences. more information on these status bits. according to MXIC's Automatic Chip Erase algorithm. are controlled internally within the device. multiple sectors, or the entire device. status of the erasing operation. ter to respond to its full command set. vice to be programmed with its programming algorithm. Table 2. In addition, to access the automatic select codes

TABLE 2. MX29LV017B AUTOMATIC SELECT MODE BUS OPERATION (A9=VID) may read the corresponding identifier code on Q7~Q0.

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 QUERY COMMAND AND COMMON FLASH INTERFACE(CFI) MODE MX29LV017B is capable of operating in the CFI mode. This mode all the host system to determine the manu- facturer of the device such as operating parameters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in Table 3. The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Automatic Select mode; however, it is ignored otherwise. The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or Automatic Se- lect mode. The command is valid only when the device is in the CFI mode. Table 3-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Address Data Query-unique ASCII string "QRY" 10 51 11 52 12 59 Primary vendor command set and control interface ID code 13 02 14 00 Address for primary algorithm extended query table 15 40 16 00 Alternate vendor command set and control interface ID code (none) 17 00 18 00 Address for secondary algorithm extended query table (none) 19 00 1A 00 Table 3-2. CFI Mode: System Interface Data Values (All values in these tables are in hexadecimal) Description Address Data VCC supply, minimum (2.7V) 1B 27 VCC supply, maximum (3.6V) 1C 36 VPP supply, minimum (none) 1D 00 VPP supply, maximum (none) 1E 00 Typical timeout for single word/byte write (2N us) 1F 04 Typical timeout for Minimum size buffer write (2N us) (not supported) 20 00 Typical timeout for individual sector erase (2N ms) 21 0A Typical timeout for full chip erase (2N ms) 22 00 Maximum timeout for single word/byte write times (2N X Typ) 23 05 Maximum timeout for buffer write times (2N X Typ) 24 00 Maximum timeout for individual sector erase times (2N X Typ) 25 04 Maximum timeout for full chip erase times (not supported) 26 00

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 Table 3-3. CFI Mode: Device Geometry Data Values (All values in these tables are in hexadecimal) Description Address Data Device size (2N bytes) 27 15 Flash device interface code (asynchronous x 8) 28 00 29 00 Maximum number of bytes in multi-byte write (not supported) 2A 00 2B 00 Number of erase sector regions 2C 01 Erase sector region 1 information (refer to the CFI publication 100) 2D 1F 2E 00 2F 00 30 01 Erase sector region 2 information 31 00 32 00 33 00 34 00 Erase sector region 3 information 35 00 36 00 37 00 38 00 Erase sector region 4 information 39 00 3A 00 3B 00 3C 00 Table 3-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values (All values in these tables are in hexadecimal) Description Address Data Query-unique ASCII string "PRI" 40 50 41 52 42 49 Major version number, ASCII 43 31 Minor version number, ASCII 44 30 Address sensitive unlock (0=required, 1= not required) 45 01 Erase suspend (2= to read and write) 46 02 Sector protect (N= # of sectors/group) 47 01 Temporary sector unprotect (1=supported) 48 01 Sector protect/chip unprotect scheme 49 04 Simultaneous R/W operation (0=not supported) 4A 00 Burst mode type (0=not supported) 4B 00 Page mode type (0=not supported) 4C 00

Sector Erase operation is in progress. dress and data sequences into the command register. TABLE 4. MX29LV017B COMMAND DEFINITIONS

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A20=do

DDI = Data of Device identifier : C2H for manufacture code, C8H for device code. RA=Address of memory location to be read. RD=Data to be read at location RA.

1. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA. SA = Address of the sector to be erased.

1. For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data

is 00H, it means the sector is still not being protected.

1. Any number of CFI data read cycles are permitted.
2. The reset command is required to return to the read mode when the device is in the automatic select mode or if Q5

TABLE 5. MX29LV017B BUS OPERATION

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.
2. VID is the high voltage, 11.5V to 12.5V.
3. Refer to Table 4 for valid Data-In during a write operation.
4. Code=00H means unprotected.
5. A20~A16=Sector address for sector protect.
6. The sector protect and chip unprotect functions may also be implemented via programming equipment.

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory , the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors , or the entire device. Table indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the "read silicon-ID" and "sector protect verify" command sequence, the device enters the "read silicon-ID" and "sector protect verify" mode. The system can then read "read silicon-ID" and "sector protect verify" codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the "read silicon-ID" and "sector protect verify" Mode and "read silicon-ID" and "sector protect verify" Command Sequence section for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODE When using both pins of CE# and RESET#, the device enter CMOS Standby with both pins held at VCC ± 0.3V. If CE# and RESET# are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, VCC active current (ICC2) is re- quired even CE# = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data. OUTPUT DISABLE With the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. RESET# OPERATION The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be re-initiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at GND±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within GND±0.3V, the standby current will be greater. The RESET# pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 READ/RESET COMMAND The read or reset operation is initiated by writing the read/reset command sequence into the command reg- ister. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid com- mand must then be written to place the device in the desired state. SILICON-ID READ COMMAND Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manu- facturer and device codes must be accessible while the device resides in the target system. PROM program- mers typically access signature codes by raising A9 to a high voltage (VID). However, multiplexing high volt- age onto address lines is not generally desired system design practice. The MX29LV017B contains a Silicon-ID-Read operation to supple traditional PROM programming methodology. The operation is initiated by writing the read silicon ID command sequence into the command register. Fol- lowing the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of C8H for MX29LV017B. The system must write the reset command to exit the "Silicon-ID Read Command". AUTOMATIC CHIP ERASE COMMANDS Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cy- cles are then followed by the chip erase command 10H. The device does not require the system to entirely pre- program prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is auto- matically verified to contain an all-zero pattern, a self- timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 7), indicating the erase operation exceed internal timing limit. The automatic erase begins on the rising edge of the last WE# or CE# pulse, whichever happens first in the command sequence and terminates when either the data on Q7 is "1" at which time the device returns to the Read mode or the data on Q6 stops toggling for two consecutive read cycles at which time the device re- turns to the Read mode. time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 22 for the timing diagram.

Resume Commands ” for more information on this mode. mode. See the "Reset Command" section, next. reset commands until the operation is complete. (also applies to Automatic Select during Erase Suspend). array data (also applies during Erase Suspend). TABLE 6. SILICON ID CODE

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 SECTOR ERASE COMMANDS The device does not require the system to entirely pre- program prior to executing the Automatic Sector Erase Set-up command and Automatic Sector Erase com- mand. Upon executing the Automatic Sector Erase com- mand, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. The system is not required to provide any control or timing during these operations. When the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. The erase and verify operations are complete when either the data on Q7 is "1" at which time the de- vice returns to the Read mode or the data on Q6 stops toggling for two consecutive read cycles at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Sector Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). Sector erase is a six-bus cycle operation. There are two "un- lock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command 30H. The sector address is latched on the falling edge of WE# or CE#, whichever happens later, while the command (data) is latched on the rising edge of WE# or CE#, which- ever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge of WE# or CE#, whichever happens later. Each succes- sive sector load cycle started by the falling edge of WE# or CE#, whichever happens later must begin within 50us from the rising edge of the preceding WE# or CE#, which- ever happens first. Otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see section Q3, Sector Erase Timer.) Any command other than Sector Erase(30H) or Erase Suspend(B0H) during the time-out period resets the device to read mode. ERASE SUSPEND This command only has meaning while the state ma- chine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend Com- mand is issued during the sector erase operation, the device requires a maximum 20us to suspend the sector erase operation. However, when the Erase Suspend com- mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been executed, the command register will initiate erase suspend mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to re- spond to Erase Resume, program data to , or read data from any sector not selected for erasure. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended sectors. ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the device has resumed erasing. BYTE PROGRAM COMMAND SEQUENCE The device programs one byte of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 4 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Q7, Q6, or RY/BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Em-

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/ BY#. Table 7 and the following subsections describe the functions of these bits. Q7, RY/BY#, and Q6 each offer a method for determining whether a program or erase op- eration is complete or in progress. These three bits are discussed first. Q7: Data# Polling The Data# Polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or com- pleted, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Automatic Program algorithm, the device out- puts on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to programming dur- ing Erase Suspend. When the Automatic Program algo- rithm is complete, the device outputs the datum pro- grammed to Q7. The system must provide the program address to read valid status information on Q7. If a pro- gram address falls within a protected sector, Data# Poll- ing on Q7 is active for approximately 1 us, then the de- vice returns to reading array data. During the Automatic Erase algorithm, Data# Polling pro- duces a "0" on Q7. When the Automatic Erase algo- rithm is complete, or if the device enters the Erase Sus- pend mode, Data# Polling produces a "1" on Q7. This is analogous to the complement/true datum out-put de- scribed for the Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be re-initiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set Q5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". this, the device outputs the "complement," or "0". The system must provide an address within any of the sec- tors selected for erasure to read valid status information on Q7. After an erase command sequence is written, if all sec- tors selected for erasing are protected, Data# Polling on Q7 is active for approximately 100 us, then the device returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchronously with Q0-Q6 while Output En- able (OE#) is asserted low. RY/BY#:Ready/Busy The RY/BY# is a dedicated, open-drain output pin that indicates whether an Automatic Erase/Program algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# or CE#, whichever happens first, in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the de- vice is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 7 shows the outputs for RY/BY# during write op- eration. Q6:Toggle BIT I Toggle Bit I on Q6 indicates whether an Automatic Pro- gram or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# or CE#, whichever happens first, in the command sequence (prior to the program or erase operation), and during the sector time- out.

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 During an Automatic Program or Erase algorithm opera- tion, successive read cycles to any address cause Q6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sec- tors selected for erasing are protected, Q6 toggles for approximately 100us and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase sus- pended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-sus- pended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program com- mand sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algo- rithm is complete. Table 7 shows the outputs for Toggle Bit I on Q6. Q2:Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# or CE#, whichever happens first, in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by com- parison, indicates whether the device is actively eras- ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 7 to compare outputs for Q2 and Q6. Reading Toggle Bits Q6/ Q2 Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase op- eration. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. Alterna- tively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Exceeded Timing Limits Q5 will indicate if the program or erase time has ex- ceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data# Polling and Toggle Bit are the only operating functions of the device under this condition. If this time-out condition occurs during sector erase op-

tion. The device must be reset to use other sectors. bination of sectors are bad. Table 7. WRITE OPERATION STATUS

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more information. device was incorrectly used.

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 POWER SUPPLY DECOUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be- tween its VCC and GND. POWER-UP SEQUENCE The MX29LV017B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command se- quences. TEMPORARY SECTOR UNPROTECT This feature allows temporary unprotection of previously protected sector to change data in-system. The Tempo- rary Sector Unprotect mode is activated by setting the RESET# pin to VID(11.5V-12.5V). During this mode, for- merly protected sectors can be programmed or erased as un-protected sector. Once VID is remove from the RESET# pin, all the previously protected sectors are pro- tected again. Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase com- mand sequence. If Data# Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data# Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the com- mand has been accepted, the system software should check the status of Q3 prior to and following each sub- sequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. DATA PROTECTION The MX29LV017B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi- tion. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of spe- cific command sequences. The device also incorpo- rates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns(typical) on CE# or WE# will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. SECTOR PROTECTION The MX29LV017B features hardware sector protection. This feature will disable both program and erase opera- tions for these sectors protected. To activate this mode, the programming equipment must force VID on address pin A9 and OE# (suggest VID = 12V). Programming of the protection circuitry begins on the falling edge of the WE# pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform. To verify programming of the protection circuitry, the pro- gramming equipment must force VID on address pin A9 ( with CE# and OE# at VIL and WE# at VIH). When A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1" code at device output Q0 for a protected sector. Other- wise the device will produce 00H for the unprotected sec- tor. In this mode, the addresses, except for A6, A1, A0, are don't care. Address locations with A6=A1=VIL are reserved to read manufacturer and device codes.(Read Silicon ID) It is also possible to determine if the sector is protected in the system by writing a Automatic Select command. Performing a read operation with A1=VIH, it will produce

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 CHIP UNPROTECT The MX29LV017B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode. To activate this mode, the programming equipment must force VID on control pin OE# and address pin A9. The CE# pins must be set at VIL. Pins A6 must be set to VIH. Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE# pulse and is terminated on the rising edge. It is also possible to determine if the chip is unprotected in the system by writing the Automatic Select command. Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed. a logical "1" at Q0 for the protected sector. The system must write the reset command to exit the Automatic Select mode.

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature oC to +125oC Voltage with Respect to Ground A9, OE#, and Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may over- shoot GND to -2.0 V for periods of up to 20 ns. Maxi- mum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may over- shoot to VCC +2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on pins A9, OE#, and RE- SET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot GND to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. OPERATING RATINGS Commercial (C) Devices Industrial (I) Devices VCC Supply Voltages Operating ranges define those limits between which the functionality of the device is guaranteed.

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

1. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

1. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.

Table 8. DC CHARACTERISTICS TA = -40 oC TO 85oC, VCC = 2.7V~3.6V

1. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.  Input pulse levels: 0V/3.0V.  Input rise and fall times is equal to or less than 5ns.  Reference levels for measuring timing: 1.5V. Table 9. READ OPERATIONS

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 SWITCHING TEST CIRCUITS SWITCHING TEST WAVEFORMS TEST POINTS 3.0V AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. OUTPUTINPUT DEVICE UNDER TEST DIODES=IN3064 OR EQUIVALENT CL 6.2K ohm 2.7K ohm +3.3V CL=100pF Including jig capacitance (MX29LV017B-90) CL=30pF Including jig capacitance (MX29LV017B-70)

Figure 1. READ TIMING WAVEFORMS

1. See the "Erase and Programming Performance" section for more information.

Table 10. Erase/Program Operations

1. See the "Erase and Programming Performance" section for more information.

Table 11. Alternate CE# Controlled Erase/Program Operations

Figure 2. COMMAND WRITE TIMING WAVEFORM

Figure 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM

Figure 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

Figure 5. CE# CONTROLLED WRITE TIMING WAVEFORM

1. PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.
2. Figure indicates the last two bus cycles of the command sequence.

Figure 6. AUTOMATIC CHIP ERASE TIMING WAVEFORM VA=Valid Address for reading status data(see "Write Operation Status").

Figure 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

Figure 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

Figure 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

Figure 10. ERASE SUSPEND/ERASE RESUME FLOWCHART

Figure 11. IN-SYSTEM SECTOR PROTECT/CHIP UNPROTECT TIMING WAVEFORM (RESET# Con- Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0.

Figure 12. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control) Notes : tVLHT (Voltage transition time)=4us min. tWPP1 (Write pulse width for sector protect)=100ns min. tOESP (OE# setup time to WE# active)=4us min.

Figure 13. SECTOR PROTECTION ALGORITHM (A9, OE# Control)

Figure 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID

Figure 15. IN-SYSTEM CHIP UNPROTECTION ALGORITHM WITH RESET#=VID

Figure 16. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control) Notes : tVLHT (Voltage transition time)=4us min. tWPP2 (Write pulse width for chip unprotect)=100ns min. tOESP (OE# setup time to WE# active)=4us min.

Figure 17. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)

• It is recommended before unprotect whole chip, all sectors should be protected in advance.

Figure 18. DATA# POLLING ALGORITHM

1. Q7 should be re-checked even Q5="1" because Q7 may change

Figure 19. TOGGLE BIT ALGORITHM Notes : 1. Read toggle bit twice to determine whether or not it is toggling.

1. Recheck toggle bit because it may stop toggling as Q5 change to "1".

Figure 20. Data# Polling Timings (During Automatic Algorithms) VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 21. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

Figure 22. RESET# TIMING WAVEFORM Table 12. AC CHARACTERISTICS

Figure 25. TEMPORARY SECTOR UNPROTECT ALGORITHM Notes : 1. All protected sectors are temporary unprotected.

1. All previously protected sectors are protected again.

Figure 26. ID CODE READ TIMING WAVEFORM

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 MIN. MAX. Input Voltage with respect to GND on all pins except I/O pins -1.0V 12.5V Input Voltage with respect to GND on all I/O pins -1.0V VCC + 1.0V VCC Current -100mA +100mA Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. LIMITS PARAMETER MIN. TYP.(2) MAX.(3) UNITS Sector Erase Time 0.7 15 sec Chip Erase Time 22.5 sec Byte Programming Time 9 300 us Chip Programming Time 18 54 sec Erase/Program Cycles 100,000 Cycles LATCH-UP CHARACTERISTICS ERASE AND PROGRAMMING PERFORMANCE (1) Notes : 1. Not 100% Tested, Excludes external system level over head. 2. Typical values measured at 25°C, 3V. 3. Maximum values measured at 85°C, 2.7V, 100,000 cycles.

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004 PART NO. ACCESS OPERATING STANDBY PACKAGE Remark TIME(ns) Current MAX.(mA) Current MAX.(uA) MX29LV017BTC-70 70 30 15 40 Pin TSOP (Normal Type) MX29LV017BTC-90 90 30 15 40 Pin TSOP (Normal Type) MX29LV017BTI-70 70 30 15 40 Pin TSOP (Normal Type) MX29LV017BTI-90 90 30 15 40 Pin TSOP (Normal Type) MX29LV017BTC-70G 70 30 15 40 Pin TSOP Pb-free (Normal Type) MX29LV017BTC-90G 90 30 15 40 Pin TSOP Pb-free (Normal Type) MX29LV017BTI-70G 70 30 15 40 Pin TSOP Pb-free (Normal Type) MX29LV017BTI-90G 90 30 15 40 Pin TSOP Pb-free (Normal Type)

ORDERING INFORMATION

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004

PACKAGE INFORMATION

P/N:PM1086 MX29LV017B REV. 1.1, DEC. 07, 2004

REVISION HISTORY

Revision No.Description Page Date 1.1 1. Added Pb-free package information P52 DEC/07/2004 2. Removed 48-CSP information P1,2,52

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