29F800

M29F800AT STMICROELECTRONICS | Alldatasheet

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

8 Mbit (1Mb x8 or 512Kb x16, Boot Block)

Figure 1. Logic Diagram

ranged, see Tables 3A and 3B, Block Addresses. nals control the bus operation of the memory. cessors, often without additional logic. all the bits erased (set to ’1’). Command Interface of the internal state machine. these bits should be ignored. Data Input/Output or Address Input (DQ15A-1). when stated explicitly otherwise. Table 2. Absolute Maximum Ratings

1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

M29F800AT, M29F800AB Table 3A. M29F800AT Block Addresses Size (Kbytes) Address Range (x8) Address Range (x16)

16 FC000h-FFFFFh 7E000h-7FFFFh

8 FA000h-FBFFFh 7D000h-7DFFFh

8 F8000h-F9FFFh 7C000h-7CFFFh

32 F0000h-F7FFFh 78000h-7BFFFh

64 E0000h-EFFFFh 70000h-77FFFh

64 D0000h-DFFFFh 68000h-6FFFFh

64 C0000h-CFFFFh 60000h-67FFFh

64 B0000h-BFFFFh 58000h-5FFFFh

64 A0000h-AFFFFh 50000h-57FFFh

64 90000h-9FFFFh 48000h-4FFFFh 64 80000h-8FFFFh 40000h-47FFFh 64 70000h-7FFFFh 38000h-3FFFFh 64 60000h-6FFFFh 30000h-37FFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 40000h-4FFFFh 20000h-27FFFh 64 30000h-3FFFFh 18000h-1FFFFh 64 20000h-2FFFFh 10000h-17FFFh 64 10000h-1FFFFh 08000h-0FFFFh 64 00000h-0FFFFh 00000h-07FFFh Table 3B. M29F800AB Block Addresses Size (Kbytes) Address Range (x8) Address Range (x16)

64 F0000h-FFFFFh 78000h-7FFFFh

64 90000h-9FFFFh 48000h-4FFFFh 64 80000h-8FFFFh 40000h-47FFFh 64 70000h-7FFFFh 38000h-3FFFFh 64 60000h-6FFFFh 30000h-37FFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 40000h-4FFFFh 20000h-27FFFh 64 30000h-3FFFFh 18000h-1FFFFh 64 20000h-2FFFFh 10000h-17FFFh 64 10000h-1FFFFh 08000h-0FFFFh 32 08000h-0FFFFh 04000h-07FFFh 8 06000h-07FFFh 03000h-03FFFh 8 04000h-05FFFh 02000h-02FFFh 16 00000h-03FFFh 00000h-01FFFh Chip Enable (E).The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G).The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W).The Write Enable, W, controls the Bus Write operation of the memory’s Com- mand Interface. Reset/Block Temporary Unprotect (RP).The Re- set/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to tem- porarily unprotect all blocks that have been pro- tected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V IL, for at least tPLPX . After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL , whichever occurs last. See the Ready/Busy Output section, Table 14 and Figure 10, Reset/ Temporary Unprotect AC Characteristics for more details. Holding RP at V ID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH . Ready/Busy Output (RB).The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedan ce during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be- comes high-impedance. See Table 14 and Figure 10, Reset/Temporary Unprotect AC Characteris- tics. During Program or Erase operations Ready/Busy is Low, V OL . Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE).The Byte/ Word Organization Select pin is used to switch be- tween the 8-bit and 16-bit Bus modes of the mem- ory. When Byte/Word Organization Select is Low, VIL, the memory is in 8-bit mode, when it is High, VIH, the memory is in 16-bit mode.

M29F800AT, M29F800AB Table 4A. Bus Operations, BYTE = VIL Note: X = VILor VIH. Table 4B. Bus Operations, BYTE = VIH Note: X = VILor VIH. Operation E G W Address Inputs DQ15A–1, A0-A18 Data Inputs/Outpu ts DQ14-DQ8 DQ7-DQ0 Bus Read V IL VIL V IH Cell Address Hi-Z Data Output Bus Write VIL VIH VIL Command Address Hi-Z Data Input Output Disable X VIH V IH X Hi-Z Hi-Z Standby V IH X X X Hi-Z Hi-Z Read Manufacturer Code VIL VIL V IH A0 = VIL,A 1=V IL,A 9=V ID, Others VILor VIH Hi-Z 20h Read Device Code VIL VIL V IH A0 = VIH,A 1=V IL,A 9=V ID, Others VILor VIH Hi-Z ECh (M29F800AT) 58h (M29F800AB) Operation E G W Address Inputs A0-A18 Data Inputs/Outpu ts DQ15A–1, DQ14-DQ0 Bus Read VIL VIL V IH Cell Address Data Output Bus Write VIL VIH VIL Command Address Data Input Output Disable X VIH V IH X Hi-Z Standby V IH X X X Hi-Z Read Manufacturer Code VIL VIL V IH A0 = VIL,A 1=V IL,A 9=V ID, Others VILor VIH 0020h Read Device Code VIL VIL V IH A0 = VIH,A 1=V IL,A 9=V ID, Others VILor VIH 00ECh (M29F800AT) 0058h (M29F800AB) VCC Supply Voltage.The V CC Supply Voltage supplies the power for all operations (Read, Pro- gram, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO . This prevents Bus Write operations from ac- cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1µF capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I CC4 . VSS Ground. The VSS Ground is the reference for all voltage measurements. BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby and Automatic Standby. See Tables 4A and 4B, Bus Operations, for a summa- ry. Typically glitches of less than 5ns on Chip En- able or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Com- mand Interface. A valid Bus Read operation in- volves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 7, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid. Bus Write.Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Ad-

M29F800AT, M29F800AB dress Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Com- mand Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output En- able must remain High, V IH, during the whole Bus Write operation. See Figures 8 and 9, Write AC Waveforms, and Tables 12 and 13, Write AC Characteristics, for details of the timing require- ments. Output Disable.The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V IH. Standby. When Chip Enable is High, VIH, the Data Inputs/Outputs pins are placed in the high- impedance state and the Supply Current is re- duced to the Standby level. When Chip Enable is at VIH the Supply Current is reduced to the TTL Standby Supply Current, ICC2 . To further reduce the Supply Current to the CMOS Standby Supply Current, ICC3 , Chip Enable should be held within VCC ± 0.2V. For Standby current levels see Table 10, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC4 , for Program or Erase operations un- til the operation completes. Automatic Standby.If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is re- duced to the CMOS Standby Supply Current, I CC3 . The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. They require V ID to be applied to some pins. Electronic Signature.The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 4A and 4B, Bus Operations. Block Protectionand Blocks Unprotection.Each block can be separately protected against acci- dental Program or Erase. Protected blocks can be unprotected to allow data to be changed. Block Protection and Block Unprotection operations must only be performed on programming equip- ment. For further information refer to Application Note AN1122, Applying Protection and Unprotection to M29 Series Flash. COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. Failure to observe a valid sequence of Bus Write operations will result in the memory return- ing to Read mode. In this case, after at least 50ns, an address transition or Chip Enable going Low is required before reading correct data. The long command sequences are imposed to maximize data security. The address used for the commands changes de- pending on whether the memory is in 16-bit or 8- bit mode. See either Table 5A, or 5B, depending on the configuration that is being used, for a sum- mary of the commands. Read/Reset Command. The Read/Reset com- mand returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take up to 10 µs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory. Auto Select Command. The Auto Select com- mand is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are re- quired to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another com- mand is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V ILand A1 = VIL. The other address bits may be set to either VILor VIH. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VILor VIH. The Device Code for the M29F800AT is 00ECh and for the M29F800AB is 0058h. The Block Protection Status of each block can be read using a Bus Read operation with A0 = V IL, A1 = VIH, and A12-A18 specifying the address of the block. The other address bits may be set to ei- ther VILor VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0- DQ7, otherwise 00h is output. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command re-

M29F800AT, M29F800AB Table 5A. Commands, 16-bit mode, BYTE = VIH Table 5B. Commands, 8-bit mode, BYTE = VIL Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VILor DQ15 when BYTE is VIH. Read/Reset.After a Read/Reset command, read the memory as normal until another command is issued. Auto Select.After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Program, Chip Erase, Block Erase.After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations until the Timeout Bit is set. Erase Suspend.After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/ Erase Controller completes and the memory returns to Read Mode. Command Length Bus Write Operations 1st 2nd 3rd 4th 5th 6th Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read/Reset 1X F 0 3 555 AA 2AA 55 X F0 Auto Select 3 555 AA 2AA 55 555 90 Program 4 555 AA 2AA 55 555 A0 PA PD Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 Command Length Bus Write Operations 1st 2nd 3rd 4th 5th 6th Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read/Reset 1X F 0

3 AAA AA 555 55 X F0

Auto Select 3 AAA AA 555 55 AAA 90 Program 4 AAA AA 555 55 AAA A0 PA PD Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 quires four Bus Write operations, the final write op- eration latches the address and data in the internal state machine and starts the Program/Erase Con- troller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ig- nore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read op- erations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’ and attempting to do so will cause an error. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

given when protected blocks are ignored. the Status Register on the Data Inputs/Outputs. set the error condition and return to Read Mode. timer restarts when an additional block is selected. Controller has started the Block Erase operation. the Status Register on the Data Inputs/Outputs. set the error condition and return to Read mode. data in the selected blocks is lost. Table 6. Program, Erase Times and Program, Erase Endurance Cycles

blocks for erasure after the Erase Resume. memory to Erase Suspend mode. can be suspended and resumed more than once. Table 7, Status Register Bits. tion or if it has responded to an Erase Suspend. eration the memory returns to Read Mode. Controller has suspended the Erase operation. address within the block being erased. Table 7. Status Register Bits Note: Unspecified data bits should be ignored.

Table 10. DC Characteristics Note: 1. Sampled only, not 100% tested. completes the memory returns to Read mode. the memory cell data as if in Read mode.

Figure 7. Read Mode AC Waveforms Table 11. Read AC Characteristics Note: 1. Sampled only, not 100% tested.

Figure 8. Write AC Waveforms, Write Enable Controlled Table 12. Write AC Characteristics, Write Enable Controlled Note: 1. Sampled only, not 100% tested.

Table 13. Write AC Characteristics, Chip Enable Controlled Note: 1. Sampled only, not 100% tested. Figure 9. Write AC Waveforms, Chip Enable Controlled

Table 14. Reset/Block Temporary Unprotect AC Characteristics Note: 1. Sampled only, not 100% tested. Figure 10. Reset/Block Temporary Unprotect AC Waveforms

Table 15. Ordering Information Scheme parts, otherwise devices are shipped from the factory with the memory content erased (to FFFFh). vice, please contact the ST Sales Office nearest to you.

Table 16. Revision History

Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data Figure 11. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

Table 18. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

M29F800AT, M29F800AB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics  2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://w ww.st.com