29F800

MX29F800T MCNIX | Alldatasheet

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P/N:PM0578 REV. 1.7, JUL. 24, 2001 MX29F800T/B 8M-BIT [1Mx8/512Kx16] CMOS FLASH MEMORY PRELIMINARY erase operation completion.

• Ready/Busy pin (RY/BY) - Provides a hardware method of detecting program or erase operation completion.
• Sector protection - Sector protect/chip unprotect for 5V/12V system. - Hardware method to disable any combination of sectors from program or erase operations - Tempory sector unprotect allows code changes in previously locked sectors.
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Code Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.2V
• Package type: - 44-pin SOP - 48-pin TSOP
• Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash

FEATURES

• 1,048,576 x 8/524,288 x 16 switchable
• Single power supply operation - 5.0V only operation for read, erase and program operation
• Fast access time: 70/90/120ns
• Low power consumption - 50mA maximum active current - 0.2uA typical standby current
• Command register architecture - Byte/word Programming (7us/12us typical) - Sector Erase (Sector structure 16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)
• Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically program and verify data at specified address
• Erase suspend/Erase Resume - Suspends sector erase operation to read data from, or program data to, another sector that is not being erased, then resumes the erase.
• Status Reply - Data polling & Toggle bit for detection of program and GENERAL DESCRIPTION The MX29F800T/B is a 8-mega bit Flash memory or- ganized as 1M bytes of 8 bits or 512K words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29F800T/B is packaged in 44-pin SOP , 48-pin TSOP . It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29F800T/B offers access time as fast as 70ns, allowing operation of high-speed microproces- sors without wait states. To eliminate bus contention, the MX29F800T/B has separate chip enable (CE) and output enable (OE) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F800T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maxi- mum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy- cling. The MX29F800T/B uses a 5.0V±10% VCC sup- ply to perform the High Reliability Erase and auto Pro- gram/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 PIN CONFIGURATIONS

44 SOP(500 mil)

A0~A18 Address Input Q0~Q14 Data Input/Output Q15/A-1 Q15(Word mode)/LSB addr(Byte mode) CE Chip Enable Input WE Write Enable Input BYTE Word/Byte Selction input RESET Hardware Reset Pin/Sector Protect Unlock OE Output Enable Input RY/BY Ready/Busy Output VCC Power Supply Pin (+5V) GND Ground Pin

48 TSOP (Standard Type) (12mm x 20mm)

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 Sector Size Address Range (in hexadecimal) (Kbytes/ (x16) (x8) Sector A18 A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range SA0 0 0 0 0 X X X 64/32 00000h-07FFFh 00000h-0FFFFh SA1 0 0 0 1 X X X 64/32 08000h-0FFFFh 10000h-1FFFFh SA2 0 0 1 0 X X X 64/32 10000h-17FFFh 20000h-2FFFFh SA3 0 0 1 1 X X X 64/32 18000h-1FFFFh 30000h-3FFFFh SA4 0 1 0 0 X X X 64/32 20000h-27FFFh 40000h-4FFFFh SA5 0 1 0 1 X X X 64/32 28000h-2FFFFh 50000h-5FFFFh SA6 0 1 1 0 X X X 64/32 30000h-37FFFh 60000h-6FFFFh SA7 0 1 1 1 X X X 64/32 38000h-3FFFFh 70000h-7FFFFh SA8 1 0 0 0 X X X 64/32 40000h-47FFFh 80000h-8FFFFh SA9 1 0 0 1 X X X 64/32 48000h-4FFFFh 90000h-9FFFFh SA10 1 0 1 0 X X X 64/32 50000h-57FFFh A0000h-AFFFFh SA11 1 0 1 1 X X X 64/32 58000h-5FFFFh B0000h-BFFFFh SA12 1 1 0 0 X X X 64/32 60000h-67FFFh C0000h-CFFFFh SA13 1 1 0 1 X X X 64/32 68000h-6FFFFh D0000h-DFFFFh SA14 1 1 1 0 X X X 64/32 70000h-77FFFh E0000h-EFFFFh SA15 1 1 110XX 32/16 78000h-7BFFFh F0000h-F7FFFh SA16 1 1 11100 8 / 4 7C000h-7CFFFh F8000h-F9FFFh SA17 1 1 11101 8 / 4 7D000h-7DFFFh FA000h-FBFFFh SA18 1 1 1111X 16/8 7E000h-7FFFFh FC000h-FFFFFh Note: Address range is A18:A-1 in byte mode and A18:A0 in word mode. BLOCK STRUCTURE MX29F800T TOP BOOT SECTOR ADDRESS TABLE MX29F800B BOTTOM BOOT SECTOR ADDRESS TABLE Sector Size Address Range (in hexadecimal) (Kbytes/ (x16) (x8) Sector A18 A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range S A 0 000000X 16/8 00000h-01FFFh 00000h-03FFFh S A 1 0000010 8 / 4 02000h-02FFFh 04000h-05FFFh S A 2 0000011 8 / 4 03000h-03FFFh 06000h-07FFFh S A 3 00001XX 32/16 04000h-07FFFh 08000h-0FFFFh SA4 0 0 0 1 X X X 64/32 08000h-0FFFFh 10000h-1FFFFh SA5 0 0 1 0 X X X 64/32 10000h-17FFFh 20000h-2FFFFh SA6 0 0 1 1 X X X 64/32 18000h-1FFFFh 30000h-3FFFFh SA7 0 1 0 0 X X X 64/32 20000h-27FFFh 40000h-4FFFFh SA8 0 1 0 1 X X X 64/32 28000h-2FFFFh 50000h-5FFFFh SA9 0 1 1 0 X X X 64/32 30000h-37FFFh 60000h-6FFFFh SA10 0 1 1 1 X X X 64/32 38000h-3FFFFh 70000h-7FFFFh SA11 1 0 0 0 X X X 64/32 40000h-47FFFh 80000h-8FFFFh SA12 1 0 0 1 X X X 64/32 48000h-4FFFFh 90000h-9FFFFh SA13 1 0 1 0 X X X 64/32 50000h-57FFFh A0000h-AFFFFh SA14 1 0 1 1 X X X 64/32 58000h-5FFFFh B0000h-BFFFFh SA15 1 1 0 0 X X X 64/32 60000h-67FFFh C0000h-CFFFFh SA16 1 1 0 1 X X X 64/32 68000h-6FFFFh D0000h-DFFFFh SA17 1 1 1 0 X X X 64/32 70000h-77FFFh E0000h-EFFFFh SA18 1 1 1 1 X X X 64/32 78000h-7FFFFh F0000h-FFFFFh

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 BLOCK DIAGRAM CONTROL INPUT LOGIC PROGRAM/ERASE HIGH VOLTAGE WRITE STATE MACHINE (WSM) STATE REGISTERMX29F800T/B FLASH ARRAY X-DECODER ADDRESS LATCH AND BUFFER Y -PASS GATE Y -DECODER ARRAY SOURCE HV COMMAND DATA DECODER COMMAND DATA LATCH I/O BUFFER PGM DATA HV PROGRAM DATA LATCH SENSE AMPLIFIER Q0-Q15/A-1 A0-A18 CE OE WE

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 AUTOMATIC PROGRAMMING The MX29F800T/B is byte programmable using the Au- tomatic Programming algorithm. The Automatic Pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29F800T/B is less than 8 seconds. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 8 second. The Automatic Erase algorithm automatically programs the entire array prior to electri- cal erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC SECTOR ERASE The MX29F800T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes al- low sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are con- trolled internally within the device. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the pro- gram verification, and counts the number of sequences. A status bit similar to DATA polling and a status bit tog- gling between consecutive read cycles, provide feed- back to the user as to the status of the programming operation. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to write commands to the command register using stan- dard microprocessor write timings. The device will au- tomatically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecu- tive read cycles provides feedback to the user as to the status of the programming operation. Register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. During write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE or CE, whichever hap- pens first. MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reli- ability, and cost effectiveness. The MX29F800T/B elec- trically erases all bits simultaneously using Fowler- Nordheim tunneling. The bytes are programmed by us- ing the EPROM programming mechanism of hot elec- tron injection. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command regis- ter to respond to its full command set.

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Command Bus Cycle Cycle Cycle Cycle Cycle Cycle Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset 1 XXXH F0H Read 1 RA RD Read Silicon ID Word 4 555H AAH 2AAH 55H 555H 90H ADI DDI Byte 4 AAAH AAH 555H 55H AAAH 90H ADI DDI Sector Protect Word 4 555H AAH 2AAH 55H 555H 90H (SA) XX00H Verify x02H XX01H Byte 4 AAAH AAH 555H 55H AAAH 90H (SA) 00H x04H 01H Porgram Word 4 555H AAH 2AAH 55H 555H A0H PA PD Byte 4 AAAH AAH 555H 55H AAAH A0H PA PD Chip Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H Sector Erase Word 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Byte 6 AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SA 30H Sector Erase Suspend 1 XXXH B0H Sector Erase Resume 1 XXXH 30H TABLE1. SOFTWARE COMMAND DEFINITIONS Note: 1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code. A2-A18=do not care. (Refer to table 3) DDI = Data of Device identifier : C2H for manufacture code, D6H/58H (x8) and 22D6H/2258H (x16) for device code. X = X can be VIL or VIH RA=Address of memory location to be read. RD=Data to be read at location RA. 2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address to the sector to be erased. 3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or 555H to Address A10~A-1 in byte mode. Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated with A11~A18 in either state. 4. For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00H, it means the sector is still not being protected.

TABLE 2. MX29F800T/B BUS OPERATION

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. Code=00H/0000H means unprotected.

Code=01H/0001H means protected.

1. A18~A12=Sector address for sector protect.

dress and data sequences into the command register.

ister. Microprocessor read cycles retrieve array data. mand register contents are altered. TABLE 3. EXPANDED SILICON ID CODE cles are then followed by the chip erase command 10H. verify the entire memory for an all-zero data pattern. any control or timing during these operations. array(no erase verification command is required). exceed internal timing limit.

are then followed by the sector erase command 30H. the time-out period resets the device to read mode. provide any control or timing during these operations. Table 4. Write Operation Status

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more information.

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 ERASE SUSPEND This command only has meaning while the state ma- chine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend com- mand is written during a sector erase operation, the de- vice requires a maximum of 100us to suspend the erase operations. However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been ex- ecuted, the command register will initiate erase suspend mode. The state machine will return to read mode auto- matically after suspend is ready. At this time, state ma- chine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend program operation is complete, the system can once again read array data within non-suspended sectors. ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions.Another Erase Suspend command can be written after the chip has resumed erasing. SET-UP AUTOMATIC PROGRAM COMMANDS To initiate Automatic Program mode, A three-cycle com- mand sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Pro- gram command A0H. Once the Automatic Program command is initiated, the next WE pulse causes a transition to an active program- ming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE or CE, whichever happens first. The rising edge of WE or CE, whichever happens first, also begins the programming operation. The system is not required to provide further controls or timings. The de- vice will automatically provide an adequate internally gen- erated program pulse and verify margin. If the program opetation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode(no program verify command is required). DATA POLLING-Q7 The MX29F800T/B also features Data Polling as a method to indicate to the host system that the Auto- matic Program or Erase algorithms are either in progress or completed. While the Automatic Programming algorithm is in op- eration, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an at- tempt to read the device will produce the true data last written to Q7. The Data Polling feature is valid after the rising edge of the fourth WE or CE, whichever happens first pulse of the four write pulse sequences for auto- matic program. While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data Polling feature is valid after the ris- ing edge of the sixth WE or CE, whichever happens first pulse of six write pulse sequences for automatic chip/ sector erase. The Data Polling feature is active during Automatic Pro- gram/Erase algorithm or sector erase time-out.(see sec- tion Q3 Sector Erase Timer) RY/BY:Ready/Busy The RY/BY is a dedicated, open-drain output pin that indicates whether an Automatic Erase/Program algo- rithm is in progress or complete. The RY/BY status is valid after the rising edge of the final WE or CE, which- ever happens first pulse in the command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resis- tor to Vcc. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)If the output is high (Ready), the

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 Q2:Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively eraseing (that is, the Automatic Erase alorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE or CE, whichever happens first, in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by com- parison, indicates whether the device is actively eras- ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 4 to compare outputs for Q2 and Q6. Reading Toggle Bits Q6/ Q2 Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has com- pleted the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfuly completed the program or erase op- eration. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially deter- mines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Al- ternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Q6:Toggle BIT I Toggle Bit I on Q6 indicates whether an Automatic Pro- gram or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, which- ever happens first, in the command sequence(prior to the program or erase operation), and during the sector time-out. During an Automatic Program or Erase algorithm op- eration, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sec- tors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase sus- pended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-sus- pended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program com- mand sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete. Table 4 shows the outputs for Toggle Bit I on Q6. device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 4 shows the outputs for RY/BY .

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 Exceeded Timing Limits Q5 will indicate if the program or erase time has ex- ceeded the specified limits(internal pulse count). Un- der these conditions Q5 will produce a "1". This time- out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition. If this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still func- tional and may be used for the program or erase opera- tion. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other ac- tive sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com- bination of sectors are bad. If this time-out condition occurs during the byte program- ming operation, it specifies that the entire sector con- taining that byte is bad and this sector maynot be re- used, (other sectors are still functional and can be re- used). The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Au- tomatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops tog- gling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. DATA PROTECTION The MX29F800T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automati- cally resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The de- vice also incorporates several features to prevent inad- vertent write cycles resulting from VCC power-up and power-down transition or system noise. TEMPORARY SECTOR UNPROTECT This feature allows temporary unprotection of previously protected sector to change data in-system. The Tempo- rary Sector Unprotect mode is activated by setting the RESET pin to VID(11.5V-12.5V). During this mode, for- merly protected sectors can be programmed or erased as un-protected sector. Once VID is remove from the RESET pin,all the previously protected sectors are pro- tected again. Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase com- mand sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept addi- tional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been ac- cepted. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns(typical) on CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. POWER SUPPLY DECOUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be- tween its VCC and GND.

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 SECTOR PROTECTION The MX29F800T/B features hardware sector protection. This feature will disable both program and erase opera- tions for these sectors protected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL.(see Table 2) Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform. To verify programming of the protection circuitry, the pro- gramming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses,except for A1, are don't care. Address loca- tions with A1 = VIL are reserved to read manufacturer and device codes.(Read Silicon ID) It is also possible to determine if the sector is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will pro- duce a logical "1" at Q0 for the protected sector. CHIP UNPROTECT The MX29F800T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode. To activate this mode, the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE pulse and is terminated on the rising edge. It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed. POWER-UP SEQUENCE The MX29F800T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature -40oC to 85oC Storage Temperature -65 oC to 125oC Applied Input Voltage -0.5V to 7.0V Applied Output Voltage -0.5V to 7.0V VCC to Ground Potential -0.5V to 7.0V A9 & OE -0.5V to 13.5V NOTICE: Stresses greater than those listed under ABSOLUTE MAXI- MUM RATINGS may cause permanent damage to the de- vice. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to ab- solute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are sub- ject to change.

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 CAPACITANCE TA = 25oC, f = 1.0 MHz SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS CIN1 Input Capacitance 8 pF VIN = 0V CIN2 Control Pin Capacitance 12 pF VIN = 0V COUT Output Capacitance 12 pF VOUT = 0V DC CHARACTERISTICS TA = -40oC TO 85oC, VCC = 5V±±±±±10% (TA = 0oC TO 70oC for MX29F800T/B-70) SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS ILI Input Leakage Current 1 uA VIN = GND to VCC ILO Output Leakage Current ± 1 uA VOUT = GND to VCC ISB1 Standby VCC current 1 mA CE = VIH ISB2 0.2 5 uA CE = VCC + 0.3V ICC1 Operating VCC current 30 mA IOUT = 0mA, f=1MHz ICC2 50 mA IOUT= 0mA, f=10MHz VIL Input Low Voltage -0.3(NOTE 1) 0.8 V VIH Input High Voltage 2.0 VCC + 0.3 V VOL Output Low Voltage 0.45 V IOL = 2.1mA VOH1 Output High Voltage(TTL) 2.4 V IOH = -2mA VOH2 Output High Voltage(CMOS) VCC-0.4 V IOH = -100uA, VCC=VCC MIN NOTES: 1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns. VIL min. = -2.0V for pulse width is equal to or less than 20 ns. 2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns If VIH is over the specified maximum value, read operation cannot be guaranteed. AC CHARACTERISTICS TA = -40oC TO 85oC, VCC = 5V±±±±±10% (TA = 0oC TO 70oC for MX29F800T/B-70) 29F800T/B-70 29F800T/B-90 29F800T/B-12 tACC Address to Output Delay 70 90 120 ns CE=OE=VIL tCE CE to Output Delay 70 90 120 ns OE=VIL tOE OE to Output Delay 40 40 50 ns CE=VIL tDF OE High to Output Float (Note1) 0 30 0 30 0 30 ns CE=VIL tOH Address to Output hold ns CE=OE=VIL NOTE: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. TEST CONDITIONS:

• Input pulse levels: 0.45V/2.4V
• Input rise and fall times is equal to or less than 10ns
• Output load: 1 TTL gate + 100pF (Including scope and jig)
• Reference levels for measuring timing: 0.8V, 2.0V READ OPERATION

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 READ TIMING WAVEFORMS Addresses CE OE tACC WE VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL HIGH Z HIGH Z DATA Valid tOE tDF tCE Outputs tOH ADD Valid COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION NOTES: 1. VIL min. = -0.6V for pulse width is equal to or less than 20ns. 2. If VIH is over the specified maximum value, programming operation cannot be guranteed. 3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2. 4. All current are in RMS unless otherwise noted. DC CHARACTERISTICS TA = -40oC TO 85oC, VCC = 5V±±±±±10% (TA = 0oC TO 70oC for MX29F800T/B-70) SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS ICC1 (Read) Operating VCC Current 30 mA IOUT=0mA, f=1MHz ICC2 50 mA IOUT=0mA, F=10MHz ICC3 (Program) 50 mA In Programming ICC4 (Erase) 50 mA In Erase ICCES VCC Erase Suspend Current 2 mA CE=VIH, Erase Suspended

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 AC CHARACTERISTICS TA = -40oC TO 85oC, VCC = 5V±±±±±10% (TA = 0oC TO 70oC for MX29F800T/B-70) 29F800T/B-70 29F800T/B-90 29F800T/B-12 tOES OE setup time 50 50 50 ns tCWC Command programming cycle 70 90 120 ns tCEP WE programming pulse width 55 55 55 ns tCEPH1 WE programming pluse width High 20 20 20 ns tCEPH2 WE programming pluse width High 20 20 20 ns tAS Address setup time 0 0 0 ns tAH Address hold time 45 45 50 ns tDS Data setup time 35 45 50 ns tDH Data hold time 0 0 0 ns tCESC CE setup time before command write 0 0 0 ns tAETC Total erase time in auto chip erase13(TYP.) 35 13(TYP.) 35 13(TYP.) 35 s tAETB Total erase time in auto sector erase 3(TYP.) 12 3(TYP.) 12 3(TYP.) 12 s tAVT Total programming time in auto verify 7/12(TYP.) 210/360 7/12(TYP.) 210/360 7/12(TYP.) 210/360 us (byte/word program time) tBAL Sector address load time 100 100 100 us tCH CE Hold Time 0 0 0 ns tCS CE setup to WE going low 0 0 0 ns tVLHT Voltge Transition Time 4 4 4 us tOESP OE Setup Time to WE Active 4 4 4 us tWPP1 Write pulse width for sector protect 10 10 10 us tWPP2 Write pulse width for sector unprotect 12 12 12 ms

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 SWITCHING TEST CIRCUITS SWITCHING TEST WAVEFORMS 2.0V 2.0V 0.8V0.8V TEST POINTS 2.4V 0.45V AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are <20ns. OUTPUTINPUT COMMAND WRITE TIMING WAVEFORM Addresses CE OE WE DIN tDS tAH Data tDH tCS tCH tCWC tCEPH1tCEPtOES tAS VCC VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ADD Valid DEVICE UNDER TEST DIODES=IN3064 OR EQUIVALENT CL 1.2K ohm 1.6K ohm +5V CL=100pF Including jig capacitance

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 AUTOMATIC PROGRAMMING TIMING AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE) WAVEFORM One byte data is programmed. Verify in fast algorithm and additional programming by external control are not required because these operations are executed auto- matically by internal control circuit. Programming completion can be verified by DATA polling and toggle bit checking after automatic verification starts. Device outputs DATA during programming and DATA after pro- gramming on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) tCWCtAS tCEP tDS tDH tDF Vcc 5V CE OE Q0,Q1, Q4(Note 1) WE A11~A18 tCEPH1 tAH ADD Valid tCESC Command In ADD ValidA0~A10 Command InCommand In Data In DATA Command In Command InCommand In Data In DATADATA tAVT tOE DATA polling 2AAH555H 555H (Q0~Q7) Command #55H Command #A0H Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit Command #AAH

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE) START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Program Data/Address Write Data A0H Address 555H YES Verify Word Ok ? YES Auto Program Completed Data Poll from systemIncrement Address Last Address ? No No

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 All data in chip are erased. External erase verification is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase starts. Device outputs 0 during era- sure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE) AUTOMATIC CHIP ERASE TIMING WAVEFORM tCWCtAS tCEP tDS tDH Vcc 5V CE OE Q0,Q1, Q4(Note 1) WE A11~A18 tCEPH1 tAH Command In A0~A10 Command InCommand In Command In Command InCommand In tAETC DATA polling 2AAH555H 555H Command #AAH Command #55H Command #80H (Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit 555H 2AAH 555H Command In Command In Command #AAH Command In Command In Command #55H Command In Command In Command #10H

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE) START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data AAH Address 555H Write Data 80H Address 555H YES Write Data 10H Address 555H Write Data 55H Address 2AAH DATA = FFh ? YES Auto Erase Completed Data Poll from system No

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 AUTOMATIC SECTOR ERASE TIMING WAVEFORM (WORD MODE) Sector data indicated by A12 to A18 are erased. Exter- nal erase verify is not required because data are erased automatically by internal control circuit. Erasure comple- tion can be verified by DATA polling and toggle bit check- ing after automatic erase starts. Device outputs 0 dur- ing erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) AUTOMATIC SECTOR ERASE TIMING WAVEFORM tAH Sector Address0 555H 2AAH 2AAH 555H 555H Sector Address1 Sector Addressn Vcc 5V CE OE Q0,Q1, Q4(Note 1) WE A12~A18 A0~A10 Command In Command In Command In Command In Command In Command In Command In Command In Command In Command In Command In Command In Command In Command In Command #30HCommand #30HCommand #30HCommand #55HCommand #AAHCommand #80HCommand #55HCommand #AAH (Q0~Q7) Command In Command In tDHtDS tCEP tCWC tAETB tBAL DATA polling tCEPH1 tAS Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART (WORD MODE) START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data AAH Address 555H Write Data 80H Address 555H Write Data 30H Sector Address Write Data 55H Address 2AAH Auto Sector Erase Completed Data Poll from System YES NO Data=FFh? Last Sector to Erase ? NO YES

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 ERASE SUSPEND/ERASE RESUME FLOWCHART START Write Data B0H Toggle Bit checking Q6 not toggled YES NO Write Data 30H Continue Erase Reading or Programming End Read Array or Program Another Erase Suspend ? NO YES YES NO

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 TIMING WAVEFORM FOR SECTOR PROTECTION tOE Data OE WE 12V 12V CE tOESP tWPP 1 tVLHT tVLHT tVLHT Verify 01H F0H A18-A12 Sector Address

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 TIMING WAVEFORM FOR CHIP UNPROTECTION tOE Data OE WE 12V 12V CE tOESP tWPP 2 tVLHT tVLHT tVLHT Verify 00H Sector AddressA18-A12 F0H

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 SECTOR PROTECTION ALGORITHM START Set Up Sector Addr PLSCNT=1 Sector Protection Complete Data=01H? Ye s Ye s OE=VID,A9=VID,CE=VIL A6=VIL Activate WE Pulse Time Out 10us Set WE=VIH, CE=OE=VIL A9 should remain VID Read from Sector Addr=SA, A1=1 Protect Another Sector? Remove VID from A9 Write Reset Command Device Failed PLSCNT=32? Ye s No No No

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 CHIP UNPROTECTION ALGORITHM START Protect All Sectors PLSCNT=1 Chip Unprotect Complete Data=00H? Ye s Set OE=A9=VID CE=VIL,A6=1 Activate WE Pulse Time Out 12ms Set OE=CE=VIL A9=VID,A1=1 Set Up First Sector Addr All sectors have been verified? Remove VID from A9 Write Reset Command Device Failed PLSCNT=1000? No Increment PLSCNT No Read Data from Device Ye s Ye s No Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance.

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 RESET TIMING WAVFORM AC CHARACTERISTICS Parameter Std Description Test Setup All Speed OptionsUnit tREADY1 RESET PIN Low (During Automatic Algorithms) MAX 20 us to Read or Write (See Note) tREADY2 RESET PIN Low (NOT Dur ing Automatic MAX 500 ns Algorithms) to Read or Write (See Note) tRP1 RESET Pulse Width (During Automatic Algorithms) MIN 10 us tRP2 RESET Pulse Width (NOT During Automatic Algorithms) MIN 500 ns tRH RESET High Time Before Read(See Note) MIN 0 ns tRB1 R Y/BY Recovery Time(to CE, OE go low) MIN 0 ns tRB2 R Y/BY Recovery Time(to WE go low) MIN 50 ns Note:Not 100% tested tRH tRB1 tRB2 tReady1 tRP2 tRP1 tReady2 RY/BY CE, OE RESET Reset Timing NOT during Automatic Algorithms Reset Timing during Automatic Algorithms RY/BY CE, OE RESET WE

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 RESET CE WE RY/BY tVIDR tVIDRProgram or Erase Command Sequence 12V 0 or 5V 0 or 5V tRSP TEMPORARY SECTOR UNPROTECT Parameter Std. Description Test Setup AllSpeed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tRSP RESET Setup Time for Temporary Sector Unprotect Min 4 us Note: Not 100% tested TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 TEMPORARY SECTOR UNPROTECT ALGORITHM Start RESET = VID (Note 1) Perform Erase or Program Operation RESET = VIH Temporary Sector Unprotect Completed(Note 2) Operation Completed 2. All previously protected sectors are protected again. Note : 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 NOTES: VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle. tDF tCE tOE tOH Address CE OE Q0-Q6 Status Data Status Data Status Data Complement True Valid Data VAVA High Z High ZValid DataTr ue DATA POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 Data Polling Algorithm START Read Q7~Q0 Add. = VA (1) Ye s Ye s Ye s No No No Q7 = Data ? Q7 = Data ? Q5 = 1 ? Read Q7~Q0 Add. = VA PASSFAIL (2) Notes: 1.VA=valid address for programming. 2.Q7 should be rechecked even Q5="1"because Q7 may change simultaneously with Q5.

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 NOTES: VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. tDF tCE tOE tOH Address CE OE Q6/Q2 Valid Status (first raed) Valid Status (second read) (stops toggling) Valid Data VA VAVAVA Valid Data TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALOGRITHMS)

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 START Read Q7~Q0 Read Q7~Q0 YES NOToggle Bit Q6 =Toggle? Q5=1? YES NO (Note 1) Read Q7~Q0 Twice (Note 1,2) Toggle Bit Q6= Toggle? Program/Erase Operation Not Complete, Write Reset Command YES Program/Erase Operation Complete Toggle Bit Algorithm Note: 1.Read toggle bit twice to determine whether or not it is toggling. 2.Recheck toggle bit because it may stop toggling as Q5 changes to "1".

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 ID CODE READ TIMING WAVEFORM tACC tCE tACC tOE tOH tOH tDF DATA OUT C2H/00C2H D6H/58H (Byte) 22D6H/2258H (Word) VID VIH VIL ADD ADD A1-A8 A10-A18 CE OE WE ADD DATA OUTDATA Q0-Q15 VCC VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 MIN. MAX. Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V Current -100mA +100mA Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. LIMITS PARAMETER MIN. TYP.(2) MAX.(3) UNITS Sector Erase Time 3 12 sec Chip Erase Time 13 35 sec Byte Programming Time 7 210 us Word Programming Time 12 360 us Chip Programming Time 8 24 sec Erase/Program Cycles 100,000 Cycles LATCHUP CHARACTERISTICS ERASE AND PROGRAMMING PERFORMANCE(1) Note: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25°C, 5V. 3.Maximum values measured at 25°C, 4.5V.

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001

ORDERING INFORMATION

PLASTIC PACKAGE (Top Boot Sector as an sample. For Bottom Boot Sector ones,MX29F800Txx will change to MX29F800Bxx) PART NO. ACCESS TIME OPERATING CURRENT STANDBY CURRENT PACKAGE (ns) MAX.(mA) MAX.(uA) MX29F800TMC-70 70 50 5 44 Pin SOP MX29F800TMC-90 90 50 5 44 Pin SOP MX29F800TMC-12 120 50 5 44 Pin SOP MX29F800TTC-70 70 50 5 48 Pin TSOP (Normal T ype) MX29F800TTC-90 90 50 5 48 Pin TSOP (Normal T ype) MX29F800TTC-12 120 50 5 48 Pin TSOP (Normal T ype) MX29F800TMI-90 90 50 5 44 Pin SOP MX29F800TMI-12 120 50 5 44 Pin SOP MX29F800TTI-90 90 50 5 48 Pin TSOP (Normal T ype) MX29F800TTI-12 120 50 5 48 Pin TSOP (Normal T ype)

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001

PACKAGE INFORMATION

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001 44-PIN PLASTIC SOP

P/N:PM0578 MX29F800T/B REV. 1.7, JUL. 24, 2001

REVISION HISTORY

Revision No.Description Page Date

1.1 Modified chip erase time to 13/35 sec P16,37 MAY/09/2000

Corrected content error P11 1.2 Add erase suspend ready max. 100us in ERASE SUSPEND's P10 MAY/29/2000 section at page10

1.3 Corrected content error at TOP BOOT SECTOR ADDRESS TABLE P3 JUN/08/2000

1.4 To add the fast access time to 70ns P1,14,16,38 DEC/04/2000

1.5 Modify Erase/Program Cycles:10,000 Cycles-->100,000 Cycles P1,37 FEB/12/2001

1.6 To modify "Package Information" P39~40 JUN/15/2001

1.7 To add I-grade (TA = -40 °C TO 85°C) P13~16,38 JUL/24/2001

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