ST72681_07 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 32
Technical content
Datasheet sections
- 1 Introduction
- 2 Pin description
- 3 Application schematics
- 4 NAND interface
- 4.1 NAND support table
- 4.2 NAND error correction
- 4.2.1 Hardware error correction
- 4.2.2 Firmware error management
- 4.3 Management of bad NAND blocks
- 4.3.1 Bad block identification
- 4.3.2 Bad block replacement
- 4.3.3 Late fail block
- 4.4 Wear levelling
- 4.4.1 LUT usage
- 4.5 NAND interface configuration
- 5 Mass storage implementation
- 5.1 USB characteristics
- 5.2 BOT / SCSI implementation
- 5.2.1 BOT specification
- 5.2.2 SCSI specification
- 5.2.3 Bootability specification
- 5.3 Multi-LUN device characteristics
- 5.3.1 Public drive
- 5.3.2 Private drive
- 5.3.3 Additional drive
- 5.3.4 CD-ROM considerations
- 5.4 Mass storage interface configuration
- 6 Human interface implementation
- 6.1 LED behavior
- 6.2 Read only switch
- 7 Electrical characteristi cs
Features
■ USB 2.0 interface compatible with mass storage device class – Integrated USB 2.0 PHYSupports USB high speed and full speed – Suspend and Resume operations ■ Mass storage controller interface (MSCI) – Supports all types of NAND Flash devices including ST, Hynix, Samsung, Toshiba, Micron, Renesas – Reed-Solomon encoder/decoder on-the-fly correction (4 bytes of a 512-byte block) – Flash identification support – Up to 12 MB/s for read and 8 MB/s for write operations in single channel – Up to 4 NAND devices supported in a single channel ■ Embedded ST7 8-bit MCU ■ Supply management – 3.3 V operation – Integrated 3.3-1.8 V voltage regulator ■ USB 2.0 low-power device compliant – Less than 100 mA during write operation with two NAND Flash devices – Less than 500 µA in suspend mode ■ AutoRun CDROM partition support ■ Bootability support (HDD mode) ■ Clock management – Integrated PLL for generating core and USB 2.0 clock sources using an external
12 MHz crystal oscillator
■ Data protection – Write protect switch control – Public/private partitions support ■ Production tool device configurability: – USB vendor ID/product ID (VID/PID), serial number and USB strings with foreign language support –S C S I s t r i n g s – One or two LED outputs – Adjustable NAND Flash bus frequency to reach highest performance ■ Code update in the NAND Flash memory ■ TQFP48 7x7 ECOPACK® package ■ Development support – Complete reference design including schematics, BOM and gerber files ■ Supports Windows (Vista, XP, 2000, ME), Linux and MacOS. Drivers available for Windows 98 SE TQFP48 7x7 Table 1. Device summary USB interface USB 2.0 high speed Number of NAND devices supported (1) up to 1 up to 4 R/W speed 11MB/s and 7MB/s 12MB/s and 8MB/s Operating voltage 3.0 to 3.6 V Operating temperature 0 to +70 °C 1. Number of NAND devices supported in a single channel.
1 Introduction
interface including PHY and function supports USB 2.0 mass storage device class. high transfer rate solution for interfacing a wide of range NAND Flash memory device types. frequency for the USB 2.0 PHY . and patch code are stored in internal RAM. I/O ports provide functions for EEPROM connection, LEDs and write protect switch control. Figure 1. Device block diagram
12 MHz
2 Pin description
- Type – I = input – O = output – S = supply
- Input level: A = Dedicated analog input
- In/Output level T = CMOS 0.3VDD/0.7VDD with input trigger –T T= TTL 0.8V / 2V with Schmitt trigger
- Output level – D8 = 8mA drive – D4 = 4mA drive – D2 = 2mA drive
Figure 2. 48-pin TQFP package pinout
- Must remain NOT connected in the application.
Table 2. Power supply
Description
48 VSS_1 S Ground
47 VDD33_1 S I/Os and regulator supply voltage
33 VSS_2 S Ground
32 VDD33_2 S I/Os and regulator supply voltage
25 VSS_3 S Ground
24 VDD33_3 S I/Os and regulator supply voltage
14 VSS_4 S Ground
15 VDD33_4 S I/Os and regulator supply voltage
13 VDDOUSB S USB2 PHY , OSC and PLL power supply output (1.8 V) Table 3. USB 2.0 interface 12 VDDBL S Supply voltage for buffers and deserialization flip flops (1.8 V) 11 VSSBL S Ground for buffers and deserialization flip flops (1.8 V)
10 USBDM I/O USB2 DATA -
9 USBDP I/O USB2 DATA +
8 VDD3 S Supply voltage for the FS compliance (3.3 V) 7 VDDC S Supply voltage for DLL & XOR tree (1.8 V) 6 VSSC S Ground for DLL & XOR tree (1.8 V) 5 RREF I/O Ref. resistor for integrated impedance process adaptation (11.3 kOhms 1% pull down) Table 4. USB 2.0 and core clock system 4 VSSA S Ground for osc & PLL (1.8 V)
3 OSCOUT O 12 MHz oscillator output
2 OSCIN I 12 MHz oscillator input
1 VDDA S Supply voltage for osc & PLL (1.8 V)
Table 5. General Purpose I/O Ports / Mass Storage I/Os
45 NAND D[0] I/O T T D4 NAND Data [0]
44 NAND D[1] I/O T T D4 NAND Data [1]
43 NAND D[2] I/O T T D4 NAND Data [2]
42 NAND D[3] I/O T T D4 NAND Data [3]
41 NAND D[4] I/O T T D4 NAND Data [4]
40 NAND D[5] I/O T T D4 NAND Data [5]
39 NAND D[6] I/O T T D4 NAND Data [6]
38 NAND D[7] I/O T T D4 NAND Data [7]
26 NAND ALE I/O T T D8 NAND Address Latch Enable
22 NAND CLE O T T D8 NAND Command Latch Enable
21 NAND WE O T T D8 NAND WRite Enable
20 NAND RE O T T D8 NAND read enable
19 NAND CE1 O T T D4 NAND Chip Enable 1
18 NAND CE2 O T T D4 NAND Chip Enable 2
17 NAND CE3 O T T D4 NAND Chip Enable 3
16 NAND CE4 O T T D4 NAND Chip Enable 4
37 NAND RnB I T T D2 NAND Ready/Busy
36 NAND WP O T T D2 NAND Write Protect
35 READ ONL Y I T T D2 Read -only switch (“0”: Read/Write; “1”: Read only)
34 EEPROM SCL O T T D2 EEPROM serial clock
28 LED2 O T T D8 Green LED (USB access)
27 LED1 O T T D8 Red LED (NAND memory access)
3 Application schematics
and NAND_CE4 should remain unconnected.
- One NAND device with four Chip Enable signals; NAND_CE1, NAND_CE2, NAND_CE3 and NAND_CE4 are used.
- One NAND device with two Chip Enable signals; NAND_CE1 and NAND_CE2 are used.
- One NAND device with one Chip Enable signal; only NAND_CE1 is used.
- Two NAND devices with two Chip Enable signals; NAND_CE1 and NAND_CE2 are used to select the first NAND device and NAND_CE3 and NAND_CE4 to select the second NAND device.
- Two NAND devices with one Chip Enable signal; NAND_CE1 and NAND_CE2 are used to select is used to select the first NAND device and the 2nd NAND device, respectively.
- 4 NAND devices with 1Chip Enable signal; NAND_CE1 selects the first NAND device, NAND_CE2 the 2nd NAND device, NAND_CE3 to select the third, and NAND_CE4 to select the fourth NAND device.
Figure 3. Application schematic
4 NAND interface
4.1 NAND support table
for all the additions and updates across the listed ranges of manufacturers’ devices. Table 6. Known NAND compatibility guide for R20 and R21 devices
4.2 NAND error correction
No NAND Flash memory arrays are guaranteed by manufacturers to be error-free. Error occurrence depends on the Flash cell type (MLC or SLC). The ST72681 embeds hardware and firmware mechanisms to correct the errors.
4.2.1 Hardware error correction
The ST72681 embeds a Reed-Solomon algorithm-based hardware cell. This cell directly manages 512-byte data packets on the NAND I/O system. Based on a data packet contents, the cell generates an 80-bit Error Correction Code (ECC) consisting of 8 words each containing 10 bits. During write operations to NAND memory, the 512-bytes of data and the ECC are stored together in the same page. The ECC is stored in the corresponding Redundant Area (RA), using 10 bytes. During read operations, the 512-bytes of data and the 8 ECC words are read back and are passed through the Reed-Solomon cell for decoding. The cell allows the correction of 4 symbols in this 520-symbol packet (512 symbols from data + 8 symbols from ECC). The hardware cell gives 3 possible results: ■ No error detected: the data packet can be used as it is. ■ Correctable error detected: the corrected data are available in a specific 512-byte buffer in the Reed-Solomon cell and are ready to use. ■ Uncorrectable error detected: data corruption is not repairable.
4.2.2 Firmware error management
The firmware defines the error correction possibilities with the corrected data packet. When data is not repairable, the block is considered as bad and replaced by another one. See below for further information.
4.3 Management of bad NAND blocks
NAND device manufacturers deliver their products with factory-marked bad blocks. This marking depends on the manufacturer and the NAND type (page size, memory technology, etc.). The ST72681 supports all bad block markings currently available on the market.
4.3.1 Bad block identification
During firmware initialization, the MCU scans the entire NAND configuration to identify bad blocks. A bad block is defined as follows: ■ 5 different Block Status bytes are considered: 4 Status bytes from page 0 and 1 from an other page (page 127 for MLC NAND; page 1 for SLC NAND). ■ The considered block is declared bad if 1 of these 5 bytes contains 4 bits or more at 0.
4.3.2 Bad block replacement
The firmware works with groups of 1024 blocks, called zones. A complete NAND configuration can contain several zones. Each zone is described in a Look Up Table (LUT) containing 1024 entries. A LUT is composed of 3 parts: used blocks, free blocks and bad blocks.
- The “bad blocks” part contains as many entries as the number of bad blocks identified in that zone.
- The “used blocks” part can have a size of 1000, 900 or 500 entries. This size is configurable and also depends on the number of identified bad blocks.
- The “free blocks” part contains the remaining entries. The used blocks part is used to do a correspondence between NAND blocks and logical address ranges. This system allows all bad blocks to be masked from the Host. As a result, bad blocks are never seen. Only a range of logical addresses are visible which correspond to the sum of the used blocks part of all zones.
4.3.3 Late fail block
During normal application life, defects can appear in the NAND memory. Under certain conditions, these defects are not correctable and the corresponding block is declared as “bad”. In this case, new bad blocks are identified in the bad blocks part of the LUT and replaced by new blocks from the “free blocks” part.
4.4 Wear levelling
During normal application life, the NAND is written and erased (by block) many times. The NAND device is guaranteed for a limited number of writes (about 100 000 cycles). As a consequence, the controller must keep write/erase operations to a minimum for any individual block. A method to limit these cycles is to use a “Wear Levelling” scheme between all NAND blocks.
4.4.1 LUT usage
The LUT is used for transfers between a logical address range and a block. It contains free blocks which are used in the “wear levelling” scheme. During write command treatment, the firmware calculates the zones, blocks and pages for data write access. In a block write operation, the firmware applies the following scheme to avoid block wearing:
- The least recently-used block is chosen from the free block part of the LUT.
- Valid data from the old block is copied to the new block.
- New data from the write command is written to the new block.
- The old block is erased.
- The LUT is updated after identifying the new block in the used block part and the old block in the free block part.
Using this scheme, a logical address range doesn’t correspond to a constant block. A write command repeated several times to the same logical address writes physically into different blocks. This method shares the wearing evenly across all blocks of the concerned zone.
4.5 NAND interface configuration
The NAND RE and WE signals frequencies can be independently configured to 30 MHz, 20 MHz, 15 MHz, 12 MHz and 10 MHz. The logical size reduction factor can be configured to 90% or 50% in the event of having too many bad blocks. this option resizes the used blocks part of the LUT to 900 or 500.
ST72681 Mass storage implementation
5 Mass storage implementation
5.1 USB characteristics
The ST72681 is compliant with USB 2.0 specification. It is able to operate in both high speed and full speed modes using a bidirectional control endpoint 0 and a bidirectional bulk endpoint 2. It automatically recognizes the speed to use on the bus by a process of negotiation with USB Host.
5.2 BOT / SCSI implementation
5.2.1 BOT specification
The USB Mass Storage Class Bulk Only Transport (BOT) specification version 1.0 is implemented. It allows the device to be recognized by the host as a mass-storage USB device.
5.2.2 SCSI specification
Moreover, inside BOT transfers, SCSI commands are encapsulated for mass storage operations. The related specifications are SBC-2 revision 10 (SCSI Block Commands 2) and SPC-4 revision 7a (SCSI Primary Commands 4).
5.2.3 Bootability specification
The USB Mass Storage Specification for Bootability revision 1.0 is implemented. It allows the PC host to boot the operating system from the USB mass storage application. In this case, the Host uses BOT LUN 0 (logical unit number). A specific tool must be used to format the logical drive in order to make it bootable by programming the correct information.
5.3 Multi-LUN device characteristics
The application can be configured with a dedicated PC software tool as a multi-LUN device. In this case, up to 3 different drives are available: public drive, additional drive and private drive. Public and additional drives can be configured as removable drive, hard disk drive or CD- ROM drive.
Mass storage implementation ST72681
5.3.1 Public drive
The public drive is the default configuration in a mono-LUN mode. In this default case, it is declared as a removable drive. The public drive is mandatory and can not be removed from the configuration. By customization (using PC software), it can be declared as a removable drive, a CD-ROM drive or a hard disk drive. This drive is the LUN 0 in BOT commands.
5.3.2 Private drive
The Private drive is optional. Its type is “removable drive” and is not configurable. This drive is protected by password and cannot be directly accessed through the PC operating system. A PC software tool is necessary to send a command with the password to unlock the device. The device is then open and accessible by the PC operating system until reset or reception of a new command to lock the drive. This drive is the LUN 1 in BOT commands.
5.3.3 Additional drive
The additional drive is optional. Its type can be “removable drive”, “hard disk drive” or “CD- ROM drive”. This drive is LUN 1 in BOT commands if the private drive option is not active, and is LUN 2 if the private drive option is active.
5.3.4 CD-ROM considerations
When a drive is declared as CD-ROM, the ST72681/R21 manages this drive with a logical block size of 2 Kbytes. To be correctly recognized by the host, it is preferable to build a CDFS partition on this CD-ROM. See the ‘ST7268x Production Tool User Manual’ for more information. Note that the ST72681/R20 doesn’t consider the CD-ROM partition as a specific case. The logical block size is 512 bytes and any file system can be used. In both cases, the CD-ROM partition allows the use of the autorun operating system feature. During device connection, the CD-ROM partition is recognized and the host tries to run the application corresponding to the ‘autorun.inf’ file present into this CD-ROM partition.
5.4 Mass storage interface configuration
In addition to the parameters already described as configurable in the previous chapters, additional customizable information includes:
- USB parameters: VID, PID, all string information
- SCSI parameters: strings for inquiry commands
ST72681 Human interface implementation
6 Human interface implementation
6.1 LED behavior
The application is designed to manage 2 LEDs. This behavior is configurable through PC dedicated software: ‘ST7268x Production Tool’. By default, LED 1 responds to NAND access activity and LED 2 responds to USB activity. Use of LED 1 is optional. When this option is not active, LED 2 reacts to both USB and NAND activity.
6.2 Read only switch
The READ ONL Y pin of the ST72681 is an input pin to be connected to VDD or GND depending on the behavior of the device.
- When this pin is connected to GND, no limitations are applied on the PC command received.
- When this pin is connected to VDD or unconnected, the firmware filters all accesses to the NAND which modify the NAND state (write, erase, etc.) and returns an error to the PC.
7 Electrical characteristics
7.1 Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
7.1.1 Minimum and maximum values
selected temperature range). mean value plus or minus three times the standard deviation (mean ±3Σ).
7.1.2 Typical values
given only as design guidelines and are not tested.
7.1.3 Typical curves
7.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 4. Figure 4. Pin loading conditions
7.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 5. Figure 5. Pin input voltage
7.2 Absolute maximum ratings
7.2.1 Voltage characteristics
7.2.2 Current characteristics
7.2.3 Thermal characteristics
Table 7. Voltage characteristics
- Directly connecting the RESET and I/O pins to VDD33 or VSS could damage the device if an unintentional
not be directly tied to VDD33 or VSS.
- When the current limitati on is not possible, the VIN absolute maximum rating must be respected, otherwise
Table 8. Current characteristics
- All power supply (V DD33) and ground (VSS) lines must always be connected to the external supply.
- Refer to Table 5: General Purpose I/O Ports / Mass Storage I/Os for the output drive capability of each of
Table 9. Thermal characteristics
7.3 Operating conditions
7.3.1 General operating conditions
Figure 6. Guaranteed functionality range
7.4 Supply current characteristics
7.4.1 RUN and SUSPEND modes
7.4.2 Supply and clock managers
Table 10. General operating conditions Table 11. RUN and SUSPEND modes Table 12. Supply and clock managers
- Typical data are based on T A = 25°C and fCPU = 12 MHz.
- Not tested in production, guar anteed by characterization.
- Data based on characterization results done with the external components specified in Section 7.5.2:
Crystal oscillator, not tested in production.
7.5 Clock and timing characteristics
Subject to general operating conditions for VDD33, fOSC, and TA.
7.5.1 General timings
7.5.2 Crystal oscillator
to the crystal manufacturer for more details (frequency, package, accuracy...). Figure 7. Typical application with a crystal oscillator
- Depending on the crystal oscillator power dissipation, a serial resistor RsOscout may be added. Refer to the
crystal oscillator manufacturer for more details. Table 13. General timing characteristics
- Data based on typical application software.
- Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles
required to finish executing the current instruction. Table 14. Crystal oscillator characteristics
- The crystal oscillator duty cycle has to be adjusted through the two CL capacitors. Refer to the crystal
manufacturer for more details. Table 15. Typical C L and RS values by crystal oscillator
7.6 EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
7.6.1 Functional EMS (elect ro magnetic susceptibility)
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. with the IEC 1000-4-4 standard. table below based on the EMS levels and classes defined in application note AN1709. performance is highly dependent on the user application and the software in particular. prequalification tests in relation with the EMC level requested for his application.
- Corrupted program counter
- Unexpected reset
- Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 16. EMC characterization and optimization values
7.6.2 Electromagnetic interference (EMI)
norm SAE J 1752/3 which specifies the board and the loading of each pin.
7.6.3 Absolute maximum rati ngs (electrical sensitivity)
product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. conforms to the JESD22-A114A/A115A standard. refer to the application note AN1181. Table 17. Electromagnetic interference
- Refer to Application Note AN1709 for data on other package types.
0.1 MHz to 30 MHz 20
130 MHz to 1 GHz 25
Table 18. Absolute Maximum Ratings
- Data based on characterization results, not tested in production.
7.7 I/O port pin characteristics
7.7.1 General characteristics
Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified. Figure 8. Typical V IL and VIH standard I/Os Table 19. Electrical sensitivity values
- Class description: A Class is an STMi croelectronics internal specification. All its limits are higher than the
Class strictly covers all the JEDEC criteria (international standard). Table 20. General I/O port pin characteristics
- Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested
- The R PU pull-up equivalent resistor is based on a resistive transistor. This data is based on
characterization results, tested in production at VDD33 max.
Figure 9. Typical R PU vs. VDD33 with VIN=VSS Figure 10. Two typical Appli cations with unused I/O Pin
7.7.2 Output driving current
Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified. Table 21. Output driving current
- The I IO current sunk must always respect the absolute maximum rating specified in Section 7.2.2: Current
characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
- The I IO current sourced must always respect the absolute maximum rating specified in Section 7.2.2:
drain I/O pins do not have VOH.
Figure 16. Typical V DD33-VOH vs. VDD33 (I/O D8)
7.8 Control pin characteristics
7.8.1 Asynchronous RESET pin
TA = 0 to +55 °C unless otherwise specified. Figure 17. Typical R ON on RESET pin Table 22. RESET pin characteristics
- The level on the RESET pin must be free to go below the VIL max. level specified in Section 7.8.1:
Asynchronous RESET pin. Otherwise the reset will not be taken into account internally.
- To guarantee the reset of the Device, a minimum pulse has to be applied to the RESET pin. All short
- The reset network protects t he device against parasitic resets.
- The external reset duration must respect this timing to guarantee a correct start-up of the internal regulator
at power-up. Not tested in production, guaranteed by design.
7.9 Other communication interface characteristics
7.9.1 MSCI parallel interface
Figure 18. Timing diagrams for input mode (with max load on CTRL signal = 50 pF) Figure 19. Timing diagrams for output mode (with max CTRL signal = 50 pF, DATA) Table 23. MSCI Parallel Interface: DC Characteristics
- Data based on design simulation and not tested in production.
7.9.2 Universal serial bus interface (USB)
Table 24. DC characteristics
- The values provided do not take into account the current through both the 1.5kΩ pull-up resistor (on the
device-side) and the 15kΩ pull-down resistor (on the host-side).
- Not tested in production, guar anteed by characterization.
Table 25. Timing characteristics
- Not tested in production, guar anteed by characterization.
Table 26. USB High Speed Transmit Waveform requirements
Figure 20. USB signal eye diagram
8 Package mechanical data
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 21. 48-pin low profile quad flat package outline Table 27. 48-pin low profile quad flat package dimensions
- Values in inches are converted from mm and rounded to 3 decimal digits.
9 Device ordering information
Table 28. Feature comparison table is inserted into a computer. Table 29. Ordering information
Table 30. Document revision history R20 and R21 devices on page 9. Section 6: Human interface implementation on page 15. operating conditions on page 18.