TMS29F256 TI | Alldatasheet
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TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES REV A — SMJS256C — MARCH 1989 — REVISED JANUARY 1991 * Single 5-V Power Supply (Top View) (Top View) = U * HVCMOS Technology wis J sh vec ata: © call Voc At2{}2 ar{] A14 At2i]2 arf) W * All Inputs/Outputs TTL Compatible avis coll ats a7ds ool 13 * Max Access/Min Cycle Time Abi] 4 25[] AS. AGi] 4 25 j AB Asils zal] Ao Asils — 2afJ Ao Voc + 5% Voc + 10% Asi]e 2a) Att Aal}e — 2af] Att '29F256/6/9-170 170 ns Ay7 2S es ee 29F256/8/9-200 '29F256/8/9-20 200s peye ap aro aye i 4 '29F256/8/9-250 '29F256/8/9-25 250 ns 149 20 o 20) '29F256/8/9-300 '29F256/8/9-30 300 ns. Royo 19) 007 Aofro 19] 007 . Daol}1: —18f) Das Dao} —18[] Dae * Self-Timed Erasure of the Entire Memory pari}i2 17} bas par{}i2 — 17[] pas Before any Reprogramming (15 ms MAX) pazi}is 16) 0a4 pagi}1s —16f] Das . Vgsi] 14 t5f) 0a3 Vgs]14 —15{] a3, * Single Byte and Page (64 Bytes) Program: ~ Latched Address and Data ~ Self-Timed Programming Operation 1115206259... .N Pack ..N Package (15 ms MAX) ‘TMS29F259... J Package — Data Polling Verification (op view) * 100, 1000, and 10000 Cycles Endurance U0 Versions Nef} 1" s2f! Veo Nof}2 aif) W * Software Inadvertent Write Protection NCi]3 — 30f} NC At2(] 4 29f] A14 Software Erase Mode Entry avis 2af] A13 © TMS29F256 Pinout Compatible With Abi] 6 27[) AB EPROM JEDEC Standard Asi]7 26] A9 Aa] as[}Ant * TMS29F258 Pinout Compatible With aal}e af G EEPROM JEDEC Standard A2[] 10 2af) Ato * Choice of Operating Temperature Ranges Ai] 22pe Aof}i2 21f}Da7 description Dao{] 13 20f} Das par{]i4 — s9f] Das The TMS29F 256, TMS29F258, and TMS29F259 are oaa{] 1s ssf) Da4 262 14-bit, programmable read-only memories that Vssi] 16 17f) bas can be electrically bulk-erased and reprogrammed. These devices are fabricated using HVCMOS flotox technology for high reliability and very low power dissipation. They perform the erase/program operations automatically with a single 5-V supply, and they can program a single byte or any number of AO-A14 ‘Address Inputs "y E Chip Enable bytes between 1 and 64. é Output Enable The TMS29F256, TMS29F258, and TMS29F259 Va Witenes Flash EEPROMsare offered ina dual-in-line ceramic DG0.007 Data inData Out package (J suffix) designed for insertion in Voc 5.V Power Supply mounting-hole rows on 15,2-mm (600-mil) centers. Yss Ground The TMS29F256, TMS29F258, and TMS29F259 in ProodcoNOAdecmcorsnrmsienceret Copyight © 1981, Texas instruments Incorporated " INSTRUMENTS POSTOFFICE BOX 1449. * HOUSTON, TEXAS 77001 ret
TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES REV A— SMJS256C _ MARCH 1989 — REVISED JANUARY 1991 the ceramic package are each offered with three guaranteed temperature ranges of 0°C to 70°C, ~ 40°C to 85°C, and ~ 40°C to 125°C (TMS29F256-__JL, TMS29F258-__JL, and TMS29F259-__JL for 0°C to 70°C; TMS29F256-__JE, TMS29F258-__JE, and TMS29F259-__JE for ~ 40°C to 85°C; and TMS29F256-__JQ, TMS29F258-_ _JQ, and TMS29F259-__JQ for ~- 40°C to 125°C). TMS29F256 TMS29F258 TMS29F259 FM PACKAGE FM PACKAGE FM PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) o gse2 X8%5o8 2 a Fy Zee 292z Rez? 9isz 2222 922 S32 1 2 3t 0 a 327 5130 Agl]s ° 20[] AB Ael]s ° 2o(] as a7ts ° 2e(} arg as[}6 2e[] ao ASL 6 2e[] Ao Agi) 20] 13 * Aatl7 27a Ast]? a7tjait As]7 27] as Asis 26]]NC Aat)s 26(]NC Aafe 26[] Ao Alls 2G A2tj9 2s] EX) at) ast} ait Ail10 2a[JA1o At}}10 24[A10 A2p}10 qe Aof]11 ae Aoi] 11 2a(]E Aif}1 23} a10 Nef} 12 22{| Daz Nep}12 22{]DQ7 Ao 12 22efE Dao|j13 2ioas —oaof}13 21JD06 paof}13 21(}0a7 1475 16 17 18 19 20 2418 16 1 8 18 20 SN RQODED SN ROOST SS QATS B28 92888 gg S2888 88 #8888 The TMS29F256, TMS29F258, and TMS29F259 are also offered with 168 hour burn-in temperature ranges (TMS29F256-_ _JL4, JE4, and JQ4; TMS29F258-__JL4, JE4, and JQ4; TMS29F259-__JL4, JE4, and JO4, respectively). (See table on page 7-29.) The TMS29F256, TMS29F258, and TMS29F259 are also offered in a dual-in-line plastic package (N suffix) designed for insertion in mounting-hole rows on 15,2-mm (600-mil) centers. The TMS29F256, TMS29F 258, and TMS29F 259 are offered in a 32-lead plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing (FM suffix). These packages are guaranteed from 0°C to 70°C (NL or FML suffix). The TMS29F256, TMS29F258, and TMS29F259 are organized as 32K x 8 bits. They feature internal circuitry {o minimize the external hardware interface that provides latched address and data, self-timed programming, and data polling verification. In the erased state all bits are at a logic high. To reprogram, all memory bits are erased first, then those bits that should be logic lows are programmed accordingly. During programming, the data polling function is enabled, causing the memory to respond with the last data read except that the most significant bit is inverted to inform the host microprocessor that the memory is busy until the programming is completed, . ‘The TMS29F256, TMS29F258, and TMS29F259 are available in 100 cycle endurance versions and will be available in 1000 and 10 000 cycle endurance versions. TEXAS ¥ INSTRUMENTS 7-28 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77001
TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES EV A. SMS256C_— MARGH 1969 — REVISED JANUARY 1531 puvenon fT sar [Fae [SSR ee [ae a AO 000.007 [wea [eevice 1X = Don't care for V < Voc. $125V< VY <15V. § TMS29F256 J and N package pins. operation read/output disable When the outputs of two or more TMS29F256s, TMS29F258s, and TMS29F259s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. To read the output of the TMS29F256, TMS29F258, or TMS29F259 a low-level signal is applied to the Eand G pins. All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. power down Active Igc current can be reduced from 20 mA to 2 mA typically, by applying a high TTL signal to the E pin. In this mode all the outputs are in the high-impedance state. single-byte program The single-byte program initiates with W low and G high applied to a selected device. The addresses on the address pins will be latched on the falling edge of E or W, whichever comes first. Figure 1 illustrates the single-byte programming flow. After the latching operations are completed, the device starts automatically programming the data in the addressed location within the memory array. This internal programming operation is completed in 15 ms maximum. ‘SUFFIX FOR OPERATING ‘SUFFIX FOR PEP4 TEMPERATURE RANGES 168 HR. BURN-IN WITHOUT PEP4 BURN-IN vs TEMPERATURE RANGES [wew7e | -arctoasc [-arctwiae | Oct IN | -aPCtoESTC | - aC aT | [_tuseerasemx | auncrm [ve | va [tae ses Toe i TEXAS % INSTRUMENTS POST OFFICE BOX 1449. © HOUSTON, TEXAS 7701 729
‘operation starts if a subsequent rising edge of W is not detected within 100 us.
- Sumiarto ne page popes see
Figure 1. Single-byte Programming Flowchart
TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES EV A-~ SMIS256C__ MARGH 1969 — REVISED JANUARY 1991 automatic page program The page mode of the ‘29F256, '29F258, and '29F259 allow the user to program 2 to 64 bytes at a time. These bytes are initially loaded in the internal device register and then automatically stored in the addressed memory locations within the memory array. The internal programming operation is completed in 15 ms maximum, regardless of the number of bytes (64 maximum) loaded. During the page loading, the page address (A6 to A14) must be the same as the initial page address. Figure 2 illustrates the automatic page programming flow. The page mode operation initiates in the same way as the single byte mode. After the first byte has been loaded, the '29F256, '29F258, and '29F259 can be loaded with 1 to 63 additional bytes. Each byte load cycle starts with the falling edge of W, or E, whichever comesiast. A successive byte must be loaded within 100 us from the rising edge of the previous byte load cycle. If a subsequent rising edge of W is not detected within 100 us, the internal programming operation starts automatically and subsequent attempts to load additional bytes are ignored until the operation is completed. Note that both the single byte and the automatic page programs can be entered after a proper “dummy” sequence of bytes has been loaded (see inadvertent write protection). i Texas 4 INSTRUMENTS
voltage of: (internal Vsenge volt) + (pragram margin voltage). Figure 2. Page Programming Flowchart — Entire Memory Algorithm
TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES REV A — SMJS256C_ MARCH 1960 REVISED JANUARY 1Go1 rN SI ARCH 1989 REVISED JANUARY 1991 data polling During a programming operation, the data polling software function is enabled to notify the host microcomputer that the memory is busy with programming and ignores any command until the programming operation is completed. If an attempt to read any byte occurs during the programming cycle, the device answers with the last loaded byte, but with the inverted logical value of DQ7. (See page 7-44 for data polling timing diagram.) flash erase mode The flash erase operation can be activated via software by loading a dummy sequence of data/address strings. The timing characteristics of this sequence are the same as those used for the page mode. The device detects this particular sequence and automatically starts the self-timed erase. If the sequence load cycle is longer than 100 us, the device ignores it. This sequence should not be used in the actual software program to prevent inadvertent flash erase operations. The specified dummy sequence to initiate the flash erase mode is: STEP MODE A14-A0 DQ7-Da0
1 Access Write 5555 AA
2 Access Write 2AAA 55
3 Access Write 5555 80
4 Access Write 5555, AA
5 Access Write 2AAA 55,
6 Access Write 5555, 10
The self-timed flash erase mode starts automatically. ——— TEXAS %» INSTRUMENTS
8 Weds
Of 1 418 up to 100 us per byte.
- Upon the three-step sequence completion, the device is latched into the program verity mode. All the bytes are read with a sense
voltage of: (internal Veenge volt) + (program margin voltage).
- Upon the three-step sequence completion, the device exits the program verify mode and retums to the page write setup.
Figure 3. Page Programming Flowchart — Standard Algorithm
NOTES: 6. The bulk-erase operation starts automatically once the six-step sequence is completed. of (nfornal Vepnge voltage) — (erase margin voltage.
- Upon the three-step sequence completion, the device is de-latched and returns to Flash operating setup.
Figure 4. Flash Erase Flowchart
TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES REV A — SMJS256C _ MARCH 1989 — REVISED JANUARY 1991 ee signature mode The signature mode provides access to two bytes contained in a spare row. One byte designates the manufacturer, the other byte designates the device code. The signature mode can be entered through either a hardware or a software operation. The hardware entry mode is specified in the mode table in the description section. Setting the device in the read mode and applying Vy on pin A9 produces the manufacturer byte code at the I/O pins if AO = Vi, or the device identifier byte code if AO = Vj. The information provided by these two bytes helps the programmer select the proper programming algorithm. The signature mode software entry sequence is specified as follows: STEP MODE A14-A0 DQ7-DQ0
1 Access Write 5555, AA
3 Access Write 5555 90
The software exit sequence for any mode is specified as follows: STEP MODE A14-A0 DQ7-Da0
3 Access Write 5555, FO
The program verify mode allows the programmer to verify the adequacy of the programming. STEP MODE A14-A0 DQ7-DQ0
3 Access Write 5555, BO
Upon completion of the three-step sequence, the device is latched into the program verify mode. All the bytes are read with a sense voltage of: (internal Vsense Voltage) + (program margin voltage) The three access write (steps 1-3) are used only to enable the program verify mode: no data will actually be written to the device. The software exit sequence must be applied to exit this program verify mode. erase verify mode The erase verify mode allows the programmer to verify the extent of erasure. The device provides the following software sequence to access the erase verify mode: STEP MODE A14-A0 DQ7-DQo
3 Access Write 5555 DO
Upon completion of the three-step sequence, the device is latched into erase verify mode. Allthe bytes are read with a sense voltage of: (internal Vsense voltage) ~ (erase margin voltage) The software exit sequence must be applied to exit this program verify mode. S aaEey TEXAS % INSTRUMENTS
7.36 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77001
TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES REV A SMJS256C _— MARCH 1989 — REVISED JANUARY 1931 eee el Inadvertent write protection The device is protected against write commands during power-up and power down. The protection is released only if Voc is higher than 3 V. Moreover, the device provides a hardware and a software protection against inadvertent write commands that may occur even with a stable V¢c. The hardware protection consists of noise immunity to a pulse on W shorter than 20 ns, which is unable to start a program cycle, and of a logic inhibit that prevents starting the program cycle unless the conditions of W low, E low, and G high are satisfied simultaneously. The software protection is such that no program operation is enabled unless preceded by a sequence of three dummy write operations. Should the specified sequence not be loaded before any program operation or the sequence load cycle is longer than 100 us, the device ignores the program commands. The inadvertent write protection software sequence is specified as follows: STEP MODE A14-A0 ba7-Da0
3 Access Write 5555 AO
4 Page Program page address + —_1st data up to the 64th
—-20__) at 6 1 Sj G2 WwW 1,2 EN (READ) Usl 103 (WRITE) iW oa pat pF paz— pT pas _ paa—18 pT pas— ; pas —12 ; a7 12 es 1 This symbol is in accordance with ANSI/EEE Std 91-1964 and 1EC Publication 617-12. ‘The pin numbers shown are for the TMS29F256 J and N packages. LN Texas %y INSTRUMENTS POSTOFFICE BOX 1449. * HOUSTON, TEXAS 77001 737
TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES BEV A SMJSZ66C —_ MARGH 1009 REVISED JANUARY 1091 SS EE functional block diagram AO At | | A | | ‘ rey d AO | AY - A2 | AZ 1 aa — Dae) poe as 262,144 Bit pie paz as R pee) [Row Flash vo a3 ar [J eccocer EEPROM Lee] Butters pes a ——d Array Le oas Ao sd LY an [ pee bar a [7 ear aa | aa [FT ata i Control Logic & Timing Ww Programming High Voltage Generator absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t Supply voltage range, Veg (See Note 9)... eee cece eee ee eee ee teereeees —0.6Vt07V Gand Ad oo... cece eect ee ee eect eteeeetsetseessereees O.6V1t015V Operating free-air temperature range ('29F256-__ JL, JL4, NL, and FML; ‘29F258-__ JL, JL4, NL, and FML; ’29F259-__ JL, JL4, NL, and FML) .. teens . 0°C to 70°C Operating free-air temperature range ('29F256-__ JE and JE4; '29F258-__ JE and JE4; '29F259-__ JE and JE4) oo eee eee eee. — 40°C to 85°C. Operating free-air temperature range ('29F256-__ JQ and JQ4; '29F258-__ JQ and JQ4; '29F259-__ JQ and JQ4) .0 wee eee — 40°C to 125°C. Storage temperature range 6... eee eee cece eee ee eee eee tee tateeeeseseees 65°C to 125°C 1 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functionaloperation ofthe device at these or anyother conditions beyond those incicatod inthe ‘Recommended Operating Candtions: section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 9: All voltage values are with respect to the most negative supply voltage Vgg (substrate). ——— TEXAS 2 INSTRUMENTS 7-38 POST OFFICE BOX 1443 ® HOUSTON, TEXAS 77001
TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES REV A. SMJS256C _ MARCH 1989 _ REVISED JANUARY 1931 aa eee recommended operating conditions 29F256-170 '29F256-250 | ‘29F256-20 '29F256-30 "'29F258-170 '20F258-250 | '29F258-20 29F 258-30 29F259-170 '29F259-250 | '29F259-20 29F259-30 '29F256-200 '29F256-300 | '29F256-25 '29F258-200 '29F258-300 | '29F258-25 29F259-200 '29F259-300 | '29F259-25 Vin High-level input voltage Cus Voo_02 Voott_ | Voc-02 Voo+t -leve! input v "29F256-__JLIL4.NUFML TA Reever mee "29F258-__JLJL4.NLFML ° 70 0 70 “c "29F259-__JLJL4,.NLFML “29F256-__JEJES Ta Rperating Wee-air ‘29F258._JE JES -40 85 -40 85 “c ip '29F259-__JEJE4 "29F256-__JOJ04 Operating free-air : 2 TA ‘29F258-__JO,J04 *c temperature ‘29F259-__JO.J04 electrical characteristics over full range of operating conditions [You Higrievtoupavotage | tows ~a00wa_—Sip a [Vou Lewievelouputvotags | gustma iS [aiexcep'a | w-owssv iP Input current (leakage) ercert 9 120195 uA Veo=55V,E= Vi [335 | lect Voc supply current (standby) put co = mA CHOSinpitiew | Voo=55¥.E=Voo ven teycie = minimum cycle time, Icc2 Voc average supply current (active read) Spats open 18 | ma
1 Typical values are at Ta = 25° C and nominal voltages
POST OFFICE BOX 1443. * HOUSTON, TEXAS 77001 7-39
F Typical values are at Ta = 25°C and nominal voltage. + Capacitance measurements are made on sample basis only.
2.08 V -
Figure 5. Output Load Circuit between V¢c and Vgg as close as possible to the device pins.
TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES REV A — SMJS256C — MARCH 1989 — REVISED JANUARY 1991 switching characteristics over full ranges of recommended operating conditionst "29F 256-170 | '29F 256-200 | ‘29F256-250 | ‘29F 256-300 "29F258-170 | '29F258-200 | ‘29F258-250 | ‘29F258-300 '29F259-170 | '29F259-200 | '29F259-250 '29F 259-300 “er lei wn ‘29F250-20 | '29F259-25 | 29F259-30 [wn wax | win wax | win Max | win Max | [em Acessmoroneares CSOs] oe | [ster Access ime tomchip erabie SSS raz fas] 0 |_| [entgyOupstenabetinotomG Ts] [gay TReedoyseime OC Cd | [je) Delay tine, chip enabetowieoapa [100 | isso] aol es 70] s_| [rste1 Deby ne. cubu enabctowio ound | «0 | v5 s0| 29 60 | 2 70] rom [nie Hot tino, cw enabiotorzoupa | 040 se | 20 oo | a5 70 ns [ig)—Holdtine oaptersbetoHzoup@ | 10a 15 s0| 20 oo] as 70[ ms [yoy Hote, datavaidto access | 2a a0 | 90 so | so eo | 070] os These parameters are guaranteed in regular read mode only. timing requirements over recommended ranges of supply voltage and operating free-air temperature en ex Tn] [nme Byeleasonietme | hawt) Addesssewpime i [icstuy We seuptme SS [iso)Detaseupime SSC fsuig) Oubut erase seupime [way Adtessrowime SSC | [ing wiereime lig) Output enatieraidime —SSSCSSSSCSCSCS~dS lino) atateane [imo Wie puso cute SSS Hwy. Wie ighecovey ine id a [wctiy Wie rign covey imeinpasemede SSCS Od [wey chp enasenghrocoveytine id Oe [uo Daevaid ine | [ine Chip enebie puss duaion i | a TEXAS % INSTRUMENTS POST OFFICE BOX 1443 * HOUSTON, TEXAS 77001 Tat
TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES BEVA-~ SMSS2E6CWARGH 1668- REVISED JANUARY 1001 read cycle __) E \\. Lt / : tenia) >, 1 tne) | i { i a I i il : il 1 _———---- I+ -)- - i setae) , fh ‘way | RRR bana SIRE W controlled write cycle to.) EXXXKR ERI on XX EX EO “oy Oita © ori _| 1 RRA Hie teu \\ \\ a SREY OME : s wy a ay #4 tau(a) + beta) | ao) an CE canines KT pacar RES A_Pas nv RRR CORR —tsyo) gg tho) Eee TEXAS % INSTRUMENTS 7-42 POST OFFICE BOX 1443 © HOUSTON, TEXAS 77001
TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORIES TIS’ A> 0 MAR bd —RENABED JATUNEY 25 E controlled write cycle —— teqw) al , EXXXKELNKREOO wan XE SOX tsu(a) + - ‘no) 1—— te) —* \\ E <— we) — SE — > teu) ie — thay : é Rey |_|) RRR i RXKERRKKREI S SOhoy | RRR Senoy . ! | $+ teu \\ am + 10M > LREXXKRE » TREES — ty | ; EELS, EEXXRERY REE onna7 FERRO retnvans RRR ease eens ‘2u0) $"q) —o page write cycle ‘— — G E ANY AXX™) xm AX) AX AEX — \\_ AQ AB AD AR AB ARE tw) * ban B > VFR DVPPYPION. eo reegup Byteo Byte1 Byten Bytens1 1 ‘ean ' ee TEXAS % INSTRUMENTS
TMS29F256, TMS29F258, TMS29F259 262 144-BIT FLASH ELECTRICALY EMASABLE PROGRAMMABLE READ-ONLY MEMORIES data polling 4#——*- tenia) ins) ++ tance) roy etc | | leon 1 14 ;_ He) ae, cy, LY | l - Ao-ata GED GEE UNI H \\ \\ Dao-pas _Byten\\ Byte n+1 ) Lest Byte QW Data Out Valld NY Data Out 1 1 | TEXAS %