29F200

M29F200BT STMICROELECTRONICS | Alldatasheet

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2 Mbit (256Kb x8 or 128Kb x16, Boot Block)

Figure 1. Logic Diagram

ranged, see Tables 3A and 3B, Block Addresses. nals control the bus operation of the memory. cessors, often without additional logic. plied with all the bits erased (set to ’1’). Command Interface of the internal state machine. these bits should be ignored. Data Input/Output or Address Input (DQ15A-1). when stated explicitly otherwise. IH, all other pins are ignored. trols the Bus Read operation of the memory. Table 2. Absolute Maximum Ratings(1)

1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

M29F200BT, M29F200BB Table 3A. M29F200BT Block Addresses Size (Kbytes) Address Range (x8) Address Range (x16) 16 3C000h-3FFFFh 1E000h-1FFFFh 8 3A000h-3BFFFh 1D000h-1DFFFh 8 38000h-39FFFh 1C000h-1CFFFh 32 30000h-37FFFh 18000h-1BFFFh 64 20000h-2FFFFh 10000h-17FFFh 64 10000h-1FFFFh 08000h-0FFFFh 64 00000h-0FFFFh 00000h-07FFFh Reset/Block Temporary Unprotect (RP).The Re- set/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to tem- porarily unprotect all Blocks that have been pro- tected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX . After Reset/Block temporary unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL , whichever occurs last. See the Ready/Busy Out- put section, Table 14 and Figure 10, Reset/Tem- porary Unprotect AC Characteristics for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH . Ready/Busy Output (RB).The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be- comes high-impedance. See Table 14 and Figure 10, Reset/Temporary Unprotect AC Characteris- tics. During Program or Erase operations Ready/Busy is Low, V OL . Ready/Busy will remain Low during Table 3B. M29F200BB Block Addresses Size (Kbytes) Address Range (x8) Address Range (x16) 64 30000h-3FFFFh 18000h-1FFFFh 64 20000h-2FFFFh 10000h-17FFFh 64 10000h-1FFFFh 08000h-0FFFFh 32 08000h-0FFFFh 04000h-07FFFh 8 06000h-07FFFh 03000h-03FFFh 8 04000h-05FFFh 02000h-02FFFh 16 00000h-03FFFh 00000h-01FFFh Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE).The Byte/ Word Organization Select pin is used to switch be- tween the 8-bit and 16-bit Bus modes of the mem- ory. When Byte/Word Organization Select is Low, V IL, the memory is in 8-bit mode, when it is High, VIH, the memory is in 16-bit mode. VCC Supply Voltage.The V CC Supply Voltage supplies the power for all operations (Read, Pro- gram, Erase etc.). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO . This prevents Bus Write operations from ac- cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1µF capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I CC4 . Vss Ground. The VSS Ground is the reference for all voltage measurements.

M29F200BT, M29F200BB Table 4A. Bus Operations, BYTE = VIL Note: X = VILor VIH. Table 4B. Bus Operations, BYTE = VIH Note: X = VILor VIH. Operation E G W Address Inputs DQ15A–1, A0-A16 Data Inputs/Outpu ts DQ14-DQ8 DQ7-DQ0 Bus Read V IL VIL V IH Cell Address Hi-Z Data Output Bus Write VIL VIH VIL Command Address Hi-Z Data Input Output Disable X VIH V IH X Hi-Z Hi-Z Standby V IH X X X Hi-Z Hi-Z Read Manufacturer Code VIL VIL V IH A0 = VIL,A 1=V IL,A 9=V ID, Others VILor VIH Hi-Z 20h Read Device Code VIL VIL V IH A0 = VIH,A 1=V IL,A 9=V ID, Others VILor VIH Hi-Z D3h (M29F200BT) D4h (M29F200BB) Operation E G W Address Inputs A0-A16 Data Inputs/Outpu ts DQ15A–1, DQ14-DQ0 Bus Read VIL VIL V IH Cell Address Data Output Bus Write VIL VIH VIL Command Address Data Input Output Disable X VIH V IH X Hi-Z Standby V IH X X X Hi-Z Read Manufacturer Code VIL VIL V IH A0 = VIL,A 1=V IL,A 9=V ID, Others VILor VIH 0020h Read Device Code VIL VIL V IH A0 = VIH,A 1=V IL,A 9=V ID, Others VILor VIH 00D3h (M29F200BT) 00D4h (M29F200BB) BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby and Automatic Standby. See Tables 4A and 4B, Bus Operations, for a summa- ry. Typically glitches of less than 5ns on Chip En- able or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Com- mand Interface. A valid Bus Read operation in- volves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 7, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid. Bus Write.Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Ad- dress Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Com- mand Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output En- able must remain High, V IH, during the whole Bus Write operation. See Figures 8 and 9, Write AC Waveforms, and Tables 12 and 13, Write AC Characteristics, for details of the timing require- ments. Output Disable.The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

M29F200BT, M29F200BB Standby. When Chip Enable is High, VIH, the Data Inputs/Outputs pins are placed in the high- impedance state and the Supply Current is re- duced to the Standby level. When Chip Enable is at V IH the Supply Current is reduced to the TTL Standby Supply Current, ICC2 . To further reduce the Supply Current to the CMOS Standby Supply Current, ICC3 , Chip Enable should be held within VCC ± 0.2V. For Standby current levels see Table 10, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC4 , for Program or Erase operations un- til the operation completes. Automatic Standby.If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is re- duced to the CMOS Standby Supply Current, ICC3 . The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. They require V ID to be applied to some pins. Electronic Signature.The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 4A and 4B, Bus Operations. Block Protectionand Blocks Unprotection.Each block can be separately protected against acci- dental Program or Erase. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on pro- gramming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotec- tion to M29 Series Flash. COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. Failure to observe a valid sequence of Bus Write operations will result in the memory return- ing to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes de- pending on whether the memory is in 16-bit or 8- bit mode. See either Table 5A, or 5B, depending on the configuration that is being used, for a sum- mary of the commands. Read/Reset Command. The Read/Reset com- mand returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10 µs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory. Auto Select Command. The Auto Select com- mand is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are re- quired to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another com- mand is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V ILand A1 = VIL. The other address bits may be set to either VILor VIH. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VILor VIH. The Device Code for the M29F200BT is 00D3h and for the M29F200BB is 00D4h.

M29F200BT, M29F200BB Table 5A. Commands, 16-bit mode, BYTE = VIH Table 5B. Commands, 8-bit mode, BYTE = VIL Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A16, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VILor DQ15 when BYTE is VIH. Read/Reset.After a Read/Reset command, read the memory as normal until another command is issued. Auto Select.After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Program, Unlock Bypass Program, Chip Erase, Block Erase.After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations until the Timeout Bit is set. Unlock Bypass.After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset.After the Unlock Bypass Reset command read the memory as normal until another command is issued. Erase Suspend.After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/ Erase Controller completes and the memory returns to Read Mode. Command Length Bus Write Operations 1st 2nd 3rd 4th 5th 6th Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read/Reset 1X F 0 3 555 AA 2AA 55 X F0 Auto Select 3 555 AA 2AA 55 555 90 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program 2X A 0P AP D Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 Command Length Bus Write Operations 1st 2nd 3rd 4th 5th 6th Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read/Reset 1X F 0

3 AAA AA 555 55 X F0

Auto Select 3 AAA AA 555 55 AAA 90 Program 4 AAA AA 555 55 AAA A0 PA PD Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass Program 2X A 0P AP D Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30

DQ0-DQ7, otherwise 00h is output. no error condition is given. the Status Register on the Data Inputs/Outputs. set the error condition and return to Read mode. to issue the Unlock Bypass command. Table 6. Program, Erase Times and Program, Erase Endurance Cycles

M29F200BT, M29F200BB Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Chip Erase Command. The Chip Erase com- mand can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation ap- pears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any com- mand to abort the operation. Typical chip erase times are given in Table 6. All Bus Read opera- tions during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in un- protected blocks of the memory to ’1’. All previous data is lost. Block Erase Command. The Block Erase com- mand can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation . Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data un- changed. No error condition is given when protect- ed blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend and Read/Reset commands. Typical block erase times are given in Table 6. All Bus Read opera- tions during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Erase Suspend Command. The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command being is- sued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start im- mediately when the Erase Resume Command is issued. It will not be possible to select any further blocks for erasure after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. Reading from blocks that are being erased will output the Status Register. It is also possible to enter the Auto Select mode: the memory will behave as in the Auto Select mode on all blocks until a Read/Reset command returns the memory to Erase Suspend mode. Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once.

Table 10. DC Characteristics Note: 1. Sampled only, not 100% tested.

Figure 7. Read Mode AC Waveforms Table 11. Read AC Characteristics Note: 1. Sampled only, not 100% tested.

Figure 8. Write AC Waveforms, Write Enable Controlled Table 12. Write AC Characteristics, Write Enable Controlled Note: 1. Sampled only, not 100% tested.

Table 13. Write AC Characteristics, Chip Enable Controlled Note: 1. Sampled only, not 100% tested. Figure 9. Write AC Waveforms, Chip Enable Controlled

Table 14. Reset/Block Temporary Unprotect AC Characteristics Note: 1. Sampled only, not 100% tested. Figure 10. Reset/Block Temporary Unprotect AC Waveforms

Table 15. Ordering Information Scheme parts, otherwise devices are shipped from the factory with the memory content erased (to FFFFh). vice, please contact the ST Sales Office nearest to you.

Table 16. Revision History

Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data Figure 11. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline Table 18. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data

M29F200BT, M29F200BB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics  1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://w ww.st.com