M29F102BB STMICROELECTRONICS | Alldatasheet
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1 Mbit (64Kb x16, Boot Block) Single Supply Flash Memory
Figure 1. Package
in the same way as a ROM or EPROM. Block where the application may be stored. nals control the bus operation of the memory. cessors, often without additional logic. Lead-free soldering processes. Figure 2. Logic Diagram Table 1. Signal Names Table 2. Bottom Boot Block Addresses, M29F102BB
Figure 3. PLCC Connections Figure 4. TSOP Connections
See Figure 2., Logic Diagram, and Table 1., Signal Names, for a brief overview of the sig- nals connected to this device. Address Inputs (A0-A15).The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ15).The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations DQ0-DQ7 represent the com- mands sent to the Command Interface of the inter- nal state machine; the Command Interface does not use DQ8-DQ15 to decode the commands. Chip Enable (E ).The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G).The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W).The Write Enable, W, controls the Bus Write operation of the memory’s Com- mand Interface. Reset/Block Temporary Unprotect (RP).The Re- set/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to tem- porarily unprotect all blocks that have been pro- tected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX . After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tPLYH , whichever occurs last. See Table 13., Write AC Characteristics, Chip Enable Con- trolled (TA = 0 to 70 °C) and Figure 12., Reset/ Block Temporary Unprotect AC Waveforms. Holding RP at VID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH . Reset/Block Temporary Unprotect can be left un- connected. A weak internal pull-up resistor en- sures that the memory always operates correctly. V CC Supply Voltage.The V CC Supply Voltage supplies the power for all operations (Read, Pro- gram, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO . This prevents Bus Write operations from ac- cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I CC3 . Vss Ground. The VSS Ground is the reference for all voltage measurements.
Enable or Write Enable, whichever occurs last. til the operation completes. Read operation is in progress. ment and are not usually used in applications. ID to be applied to some pins. code, that can be read to identify the memory. listed in Table 3., Bus Operations. unprotected to allow data to be changed. Table 3. Bus Operations
All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. Failure to observe a valid sequence of Bus Write operations will result in the memory return- ing to Read mode. The long command sequences are imposed to maximize data security. The commands are summarized in Table 4., Commands. Refer to Table 4. in conjunction with the text descriptions below. Read/Reset Command. The Read/Reset com- mand returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take up to 10 µs to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory. Auto Select Command. The Auto Select com- mand is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are re- quired to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another com- mand is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29F102BB is 0097h. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A15 specifying the address of the block. The other address bits may be set to ei- ther VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command re- quires four Bus Write operations, the final write op- eration latches the address and data in the internal state machine and starts the Program/Erase Con- troller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ig- nore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 5.. Bus Read op- erations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Com- mands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memo- ry. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these com- mands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been is- sued the memory will only accept the Unlock By- pass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. Unlock Bypass Program Command. The Un- lock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Pro- gram/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Pro- gram operation using the Program command. A protected block cannot be programmed; the oper- ation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock By- pass Mode. See the Program command for details on the behavior. Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command.
Chip Erase Command. The Chip Erase com- mand can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation ap- pears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any com- mand to abort the operation. Typical chip erase times are given in Table 5.. All Bus Read opera- tions during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in un- protected blocks of the memory to ’1’. All previous data is lost. Block Erase Command. The Block Erase com- mand can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data un- changed. No error condition is given when protect- ed blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend and Read/Reset commands. Typical block erase times are given in Table 5.. All Bus Read opera- tions during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Erase Suspend Command. The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command being is- sued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start im- mediately when the Erase Resume Command is issued. It will not be possible to select any further blocks for erasure after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. Reading from blocks that are being erased will output the Status Register. It is also possible to enter the Auto Select mode: the memory will behave as in the Auto Select mode on all blocks until a Read/Reset command returns the memory to Erase Suspend mode. Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once.
Table 4. Commands Note: 1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
- All values in the table are in hexadecimal.
- The Command Interface only uses address bits A0-A10 and DQ0-DQ7 to verify the commands, the upper address bits and the
upper data bits are Don’t Care.
- After a Read/Reset command, read the memory as normal until another command is issued.
- After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
- Program, Unlock Bypass Program, Chip Erase, Block Erase.
- After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read
Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations until the Timeout Bit is set.
- After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
- After the Unlock Bypass Reset command read the memory as normal until another command is issued.
- After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-
- After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/Erase Con-
troller completes and the memory returns to Read Mode. Table 5. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70°C)
Table 6. Status Register Bits Note: 1. Unspecified data bits should be ignored. Figure 5. Data Polling Flowchart Figure 6. Data Toggle Flowchart
Table 7. Absolute Maximum Ratings (1)
- Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
- Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
Table 8. Operating and AC Measurement Conditions Figure 7. AC Testing Input Output Waveform Figure 8. AC Testing Load Circuit Table 9. Capacitance (TA = 25 °C, f = 1 MHz) Note: Sampled only, not 100% tested.
Table 10. DC Characteristics (TA = 0 to 70°C) Note: 1. Excluding the RP input.
- Sampled only, not 100% tested.
Table 11. Read AC Characteristics (TA = 0 to 70°C) Note: 1. This timing refers to a Load Capacitance (CL) of 30pF. If CL is higher, add 1.5ns for each extra 10pF.
- Sampled only, not 100% tested.
Figure 9. Read Mode AC Waveforms
Table 12. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70 °C) Figure 10. Write AC Waveforms, Write Enable Controlled
Table 13. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70 °C) Figure 11. Write AC Waveforms, Chip Enable Controlled
Table 14. Reset/Block Temporary Unprotect AC Characteristics (TA = 0 to 70°C) Note: 1. Sampled only, not 100% tested. Figure 12. Reset/Block Temporary Unprotect AC Waveforms
Figure 13. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline Note: Drawing is not to scale. Table 15. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data
Figure 14. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm, Package Outline Note: Drawing is not to scale. Table 16. PTSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm, Package Mechanical Data
Table 17. Ordering Information Scheme parts, otherwise devices are shipped from the factory with the memory content bits erased to ‘1’. vice, please contact the ST Sales Office nearest to you.
REVISION HISTORY
Table 18. Revision History
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America