29F080-12

MX29F080 MCNIX | Alldatasheet

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Technical content

P/N:PM0579 REV. 1.6, NOV, 21, 2002 MX29F080 8M-BIT [1024K x 8] CMOS EQUAL SECTOR FLASH MEMORY PRELIMINARY

FEATURES

• 1,048,576 x 8 byte mode only
• Single power supply operation - 5.0V only operation for read, erase and program operation
• Fast access time: 70/90/120ns
• Low power consumption - 30mA maximum active current - 0.2uA typical standby current
• Command register architecture - Byte Programming (7us typical) - Sector Erase of 16 equal sector with 64K-Byte each
• Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically program and verify data at specified address
• Erase suspend/Erase Resume - Suspends sector erase operation to read data from, or program data to, another sector that is not being erased, then resumes the erase. TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maxi- mum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The MX29F080 uses a 5.0V±10% VCC supply to perform the High Reliability Erase and auto Program/ Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V. GENERAL DESCRIPTION The MX29F080 is a 8-mega bit Flash memory organized as 1024K bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-vola- tile random access memory. The MX29F080 is pack- aged in 40-pin TSOP or 44-pin SOP . It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29F080 offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the MX29F080 has separate chip enable (CE) and output enable (OE ) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F080 uses a command register to manage this functionality. The command register allows for 100%
• Status Reply - Data polling & Toggle bit for detection of program and erase operation completion.
• Ready/Busy (RY/BY) - Provides a hardware method of detecting program and erase operation completion.
• Sector Group protect/chip unprotect for 5V/12V sys- tem.
• Sector Group protection - Hardware protect method for each group which con- sists of two adjacent sectors - Temporary sector group unprotect allows code changes in previously locked sectors
• 10,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Low VCC write inhibit is equal to or less than 3.2V
• Package type: - 40-pin TSOP or 44-pin SOP
• Compatibility with JEDEC standard - Pinout and software compatible with single-power supply Flash

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 PIN CONFIGURATIONS

40 TSOP (Standard Type) (10mm x 20mm)

A0~A19 Address Input Q0~Q7 8 Data Inputs/Outputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input RESET Hardware Reset Pin, Active Low RY/BY Read/Busy Output VCC +5.0V single power supply VSS Device Ground NC Pin Not Connected Internally PIN DESCRIPTION44 SOP LOGIC SYMBOL A19 A18 A17 A16 A15 A14 A13 A12 CE VCC NC RESET A11 A10 NC NC WE OE RY/BY VCC VSS VSS MX29F080 NC RESET A11 A10 NC NC VSS VSS VCC CE A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC WE OE RY/BY VCC MX29F080 Q0-Q7 RY/BY A0-A19 CE OE WE RESET

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 Legend:SA=Sector Address ; SGA =Sector Group Address Note:All sectors are 64 Kbytes in size. SECTOR STRUCTURE MX29F080 SECTOR ADDRESS TABLE Sector Group Sector A19 A18 A17 A16 Address Range SGA0 SA0 0000 000000h-00FFFFh SGA0 SA1 0001 010000h-01FFFFh SGA1 SA2 0010 020000h-02FFFFh SGA1 SA3 0011 030000h-03FFFFh SGA2 SA4 0100 040000h-04FFFFh SGA2 SA5 0101 050000h-05FFFFh SGA3 SA6 0110 060000h-06FFFFh SGA3 SA7 0111 070000h-07FFFFh SGA4 SA8 1000 080000h-08FFFFh SGA4 SA9 1001 090000h-09FFFFh SGA5 SA10 1010 0 A 0000h-0AFFFFh SGA5 SA11 1011 0 B 0000h-0BFFFFh SGA6 SA12 1100 0C0000h-0CFFFFh SGA6 SA13 1101 0D0000h-0DFFFFh SGA7 SA14 1110 0 E 0000h-0EFFFFh SGA7 SA15 1111 0F0000h-0FFFFFh

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 BLOCK DIAGRAM CONTROL INPUT LOGIC PROGRAM/ERASE HIGH VOLTAGE WRITE STATE MACHINE (WSM) STATE REGISTER MX29F080 FLASH ARRAY X-DECODER ADDRESS LATCH AND BUFFER Y -PASS GATE Y -DECODER ARRAY SOURCE HV COMMAND DATA DECODER COMMAND DATA LATCH I/O BUFFER PGM DATA HV PROGRAM DATA LATCH SENSE AMPLIFIER Q0-Q7 A0-A19 CE OE WE

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 AUTOMATIC PROGRAMMING The MX29F080 is byte programmable using the Auto- matic Programming algorithm. The Automatic Program- ming algorithm makes the external system do not need to have time out sequence nor to verify the data pro- grammed. The typical chip programming time at room temperature of the MX29F080 is less than 8 seconds. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 8 seconds. The Automatic Erase algorithm automatically programs the entire array prior to electri- cal erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC SECTOR ERASE The MX29F080 is sector(s) erasable using MXIC's Auto Sector Erase algorithm. Sector erase modes allow sectors of the array to be erased in one erase cycle. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm require the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the pro- gram verification, and counts the number of sequences. A status bit similar to DATA polling and a status bit tog- gling between consecutive read cycles, provide feed- back to the user as to the status of the programming operation. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to write commands to the command register using stand- ard microprocessor write timings. The device will auto- matically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecu- tive read cycles provides feedback to the user as to the status of the programming operation. Register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. During write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE or CE, whichever hap- pens first . MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, re- liability, and cost effectiveness. The MX29F080 electri- cally erases all bits simultaneously using Fowler-Nord- heim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command regis- ter to respond to its full command set.

TABLE 1. SOFTWARE COMMAND DEFINITIONS

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code. A2-A19=do

DDI = Data of Device identifier : C2H for manufacture code, D5H for device code. RA=Address of memory location to be read. RD=Data to be read at location RA.

1. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA. SA = Address of the sector to be erased. Address A16-A19 select a unique sector. SGA=Address of the sector group. Address A17~A19 select a unique sector group.

1. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 .

Address (SA). Write Sequence may be initiated with A11~A19 in either state.

1. For Sector Group Protect Verify Operation : If read out data is 01H, it means the sector has been protected. If read

out data is 00H, it means the sector is still not being protected. dress and data sequences into the command register.

TABLE 2. MX29F080 BUS OPERATION

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 13V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. Code=00H means unprotected.
5. A19~A17=Sector group address for sector group protect.

Refer to sector group protect/chip unprotect algorithm and waveform.

ister. Microprocessor read cycles retrieve array data. register contents are altered. A1=VIL,A0=VIL retrieves the manufacturer code of C2H. are then followed by the chip erase command 10H. or timing during these operations. (no erase verification command is required). the device returns to the Read mode. TABLE 3. EXPANDED SILICON ID CODE

command and Automatic Sector Erase command. control or timing during these operations. control or timing during these operations. required). Sector erase is a six-bus cycle operation. TABLE 4. WRITE OPERATION STATUS

1. Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.
2. Performing successive read operations from any address will cause Q6 to toggle.
3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the

However, successive reads from the erase-suspended sector will cause Q2 to toggle.

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 ERASE SUSPEND This command only has meaning while the state ma- chine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend com- mand is written during a sector erase operation, the de- vice requires a maximum of 100us to suspend the erase operations. However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been ex- ecuted, the command register will initiate erase suspend mode. The state machine will return to read mode auto- matically after suspend is ready. At this time, state ma- chine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended sector. ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing. SET-UP AUTOMATIC PROGRAM COMMANDS To initiate Automatic Program mode, A three-cycle com- mand sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Pro- gram command A0H. Once the Automatic Program command is initiated, the next WE pulse causes a transition to an active program- ming operation. Addresses are latched on the falling edge, and data are internally latched on the rising edge of the WE or CE, whichever happens first pulse. The rising edge of WE or CE, whichever happens first also begins the programming operation. The system is not required to provide further controls or timings. The de- vice will automatically provide an adequate internally gen- erated program pulse and verify margin. If the program operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating the program operation exceed internal timing limit. The automatic programming operation is completed when the data read on Q6 stops toggling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode (no program verify command is required). DATA POLLING-Q7 The MX29F080 also features Data Polling as a method to indicate to the host system that the Automatic Pro- gram or Erase algorithms are either in progress or com- pleted. While the Automatic Programming algorithm is in opera- tion, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program Algorithm an at- tempt to read the device will produce the true data last written to Q7. The Data Polling feature is valid after the rising edge of the fourth WE or CE, whichever happens first, of the four write pulse sequences for automatic program. While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1". The Data Polling feature is valid after the rising edge of the sixth WE or CE, whichever happens first, of six write pulse sequences for automatic chip/sector erase. The Data Polling feature is active during Automatic Pro- gram/Erase algorithm or sector erase time-out. (see sec- tion Q3 Sector Erase Timer)

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 pens first pulse in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by com- parison, indicates whether the device is actively eras- ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 4 to compare outputs for Q2 and Q6. Reading Toggle Bits Q6/ Q2 Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase opera- tion. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the al- gorithm when it returns to determine the status of the operation. Q6:Toggle BIT I Toggle Bit I on Q6 indicates whether an Automatic Pro- gram or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, whichever happens first pulse in the command sequence(prior to the program or erase operation), and during the sector time-out. During an Automatic Program or Erase algorithm opera- tion, successive read cycles to any address cause Q6 to toggle. The system may use either OE or CE to con- trol the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sec- tors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase sus- pended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-sus- pended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2us after the program com- mand sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algo- rithm is complete. Table 4 shows the outputs for Toggle Bit I on Q6. Q2:Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit I is valid af- ter the rising edge of the final WE or CE, whichever hap-

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 Exceeded Timing Limits Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not suc- cessfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condi- tion. If this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still func- tional and may be used for the program or erase opera- tion. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com- bination of sectors are bad. If this time-out condition occurs during the byte program- ming operation, it specifies that the entire sector con- taining that byte is bad and this sector maynot be re- used, (other sectors are still functional and can be re- used). The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Au- tomatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. DATA PROTECTION The MX29F080 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi- tion. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of spe- cific command sequences. The device also incorporates several features to prevent inadvertent write cycles re- sulting from VCC power-up and power-down transition or system noise. Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase com- mand sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low ("0"), the device will accept addi- tional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns( typical) on CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. TEMPORARY SECTOR GROUP UNPROTECT This feature allows temporary unprotection of previously protected sector group to change data in-system. The Temporary Sector group Unprotect mode is activated by setting the RESET pin to VID(11.5V-12.5V). During this mode, formerly protected sectors can be programmed or erased as un-protected sector. Once VID is remove from the RESET pin, all the previously protected sector groups are protected again.

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 SECTOR GROUP PROTECTION The MX29F080 features hardware sector group protec- tion. This feature will disable both program and erase operations for these group sector protected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL. (see Table 2) Program- ming of the protection circuitry begins on the falling edge of the WE or CE, whichever happens later pulse and is terminated on the rising edge. Please refer to group sector protect algorithm and waveform. To verify programming of the protection circuitry, the pro- gramming equipment must force VID on address pin A9 ( with CE and OE at VIL and WE at VIH). When A1=1, it will produce a logical "1" code at device output Q0 for a protected sector. Otherwise the device will produce 00H for the unprotected sector. In this mode, the addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes. (Read Silicon ID) It is also possible to determine if the group is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector. CHIP UNPROTECT The MX29F080 also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode. To activate this mode, the programming equipment must force VID on control pin OE and address pin A9. The CE pins must be set at VIL. Pins A6 must be set to VIH. (see Table 2) Refer to chip unprotect algorithm and wave- form for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE or CE, whichever happens later pulse and is terminated on the rising edge. POWER-UP SEQUENCE The MX29F080 powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command se- quences. POWER SUPPLY DECOUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be- tween its VCC and GND. It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs (Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed.

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 29F080-70* 29F080-90 29F080-12 tACC Address to Output Delay 70 90 120 ns CE=OE=VIL tCE CE to Output Delay 70 90 120 ns OE=VIL tOE OE to Output Delay 40 40 50 ns CE=VIL tDF OE High to Output Float (Note1) 0 20 0 30 0 30 ns CE=VIL tOH Address to Output hold 0 0 0 ns CE=OE=VIL NOTE: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. * For -70, the input levels : 0.0/3.0V, the output load : 1TTL gate+30pF (including scope and jig) TEST CONDITIONS:

• Input pulse levels: 0.45V/2.4V*
• Input rise and fall times is equal to or less than 0ns
• Output load: 1 TTL gate + 100pF* (Including scope and jig)
• Reference levels for measuring timing: 0.8V, 2.0V NOTES: 1. VIL min. = -1.0V for pulse width < 50 ns. VIL min. = -2.0V for pulse width < 20 ns. 2. VIH max. = VCC + 1.5V for pulse width < 20 ns. If VIH is over the specified maximum value, read operation cannot be guaranteed. READ OPERATION DC CHARACTERISTICS (TA = 0°C TO 70°C, VCC = 5V±±±±±10%) SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS ILI Input Leakage Current ± 1 uA VIN = GND to VCC ILO Output Leakage Current ± 1 uA VOUT = GND to VCC ISB1 Standby VCC current 1 mA CE = VIH ISB2 0.2 5 uA CE = VCC + 0.3V ICC1 Operating VCC current 30 mA IOUT = 0mA, f=1MHz ICC2 50 mA IOUT = 0mA, f=10MHz VIL Input Low Voltage -0.3 (NOTE 1) 0.8 V VIH Input High Voltage 2.0 VCC + 0.3 V VOL Output Low Voltage 0.45 V IOL = 2.1mA VOH1 Output High Voltage(TTL) 2.4 V IOH = -2mA VOH2 Output High Voltage(CMOS) VCC-0.4 V IOH = -100uA, VCC=VCC MIN CAPACITANCE (TA = 25 oC, f = 1.0 MHz) SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS CIN1 Input Capacitance 8 pF VIN = 0V CIN2 Control Pin Capacitance 12 pF VIN = 0V COUT Output Capacitance 12 pF VOUT = 0V AC CHARACTERISTICS (TA = 0oC to 70oC, VCC = 5V±±±±±10%)

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature 0oC to 70oC Storage Temperature -65 oC to 125oC Applied Input Voltage -0.5V to 7.0V Applied Output Voltage -0.5V to 7.0V VCC to Ground Potential -0.5V to 7.0V A9 & OE -0.5V to 13.5V NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change. READ TIMING WAVEFORMS NOTES: 1. VIL min. = -0.6V for pulse width is equal to or less than 20ns. 2. If VIH is over the specified maximum value, programming operation cannot be guranteed. 3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2. 4. All current are in RMS unless otherwise noted. DC CHARACTERISTICS (TA = 0oC to 70oC, VCC = 5V±±±±±10%) SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS ICC1 (Read) Operating VCC Current 30 mA IOUT=0mA, f=1MHz ICC2 50 mA IOUT=0mA, F=10MHz ICC3 (Program) 50 mA In Programming ICC4 (Erase) 50 mA In Erase ICCES VCC Erase Suspend Current 2 mA CE=VIH, Erase Suspended COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION Addresses CE OE tACC WE VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL HIGH Z HIGH Z DATA Valid tOE tDF tCE Outputs tOH ADD Valid

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 AC CHARACTERISTICS TA = 0 oC to 70oC, VCC = 5V ±±±±± 10% 29F080-70 29F080-90 29F080-12 tOES OE setup time 50 50 50 ns tCWC Command programming cycle 70 90 120 ns tCEP WE programming pulse width 35 45 50 ns tCEPH1 WE programming pulse width High 20 20 20 ns tCEPH2 WE programming pulse width High 20 20 20 ns tAS Address setup time 0 0 0 ns tAH Address hold time 45 45 50 ns tDS Data setup time 30 45 50 ns tDH Data hold time 0 0 0 ns tCESC CE setup time before command write 0 0 0 ns tDF Output disable time (Note 1) 20 30 30 ns tAETC Total erase time in auto chip erase8(TYP.) 64 8(TYP.) 64 8(TYP.) 64 s tAVT Total programming time in auto verify 7(TYP.) 210 7(TYP.) 210 7(TYP.) 210 us tBAL Sector address load time 80 80 80 us tCH CE Hold Time 0 0 0 ns tCS CE setup to WE going low 0 0 0 ns tVLHT Voltge Transition Time 4 4 4 us tOESP OE Setup Time to WE Active 4 4 4 us tWPP1 Write pulse width for sector protect 10 10 10 us tWPP2 Write pulse width for sector unprotect 12 12 12 ms NOTES: 1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 SWITCHING TEST CIRCUITS SWITCHING TEST WAVEFORMS COMMAND WRITE TIMING WAVEFORM 2.0V 2.0V 0.8V0.8V TEST POINTS 2.4V 0.45V AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are <20ns. OUTPUTINPUT DEVICE UNDER TEST DIODES=IN3064 OR EQUIVALENT CL 1.2K ohm 1.6K ohm +5V CL=30pF Including jig capacitance for -70 grade, CL=100pF for others Addresses CE OE WE DIN tDS tAH Data tDH tCS tCH tCWC tCEPH1tCEPtOES tAS VCC VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ADD Valid

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 One byte data is programmed. Verify in fast algorithm and additional programming by external control are not required because these operations are executed auto- matically by internal control circuit. Programming completion can be verified by DATA polling and toggle bit checking after automatic verification starts. Device outputs DATA during programming and DATA after pro- gramming on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) AUTOMATIC PROGRAMMING TIMING WAVEFORM tCWCtAS tCEP tDS tDH tDF Vcc 5V CE OE Q0,Q1, Q4(Note 1) WE A11~A19 tCEPH1 tAH ADD Valid tCESC Command In ADD ValidA0~A10 Command InCommand In Data In DATA Command In Command InCommand In Data In DATADATA tAVT tOE DATA polling 2AAH555H 555H (Q0~Q7) Command #55H Command #A0H Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit Command #AAH

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Program Data/Address Write Data A0H Address 555H YES NOToggle Bit Checking Q6 not Toggled Verify Byte Ok YES Q5 = 1 Reset Auto Program Completed Auto Program Exceed Timing Limit NOInvalid Command YES NO

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 All data in chip are erased. External erase verification is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) AUTOMATIC CHIP ERASE TIMING WAVEFORM AUTOMATIC CHIP ERASE TIMING WAVEFORM tCWCtAS tCEP tDS tDH Vcc 5V CE OE Q0,Q1, Q4(Note 1) WE A11~A19 tCEPH1 tAH Command In A0~A10 Command InCommand In Command In Command InCommand In tAETC DATA polling 2AAH555H 555H Command #AAH Command #55H Command #80H (Q0~Q7) Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit 555H 2AAH 555H Command In Command In Command #AAH Command In Command In Command #55H Command In Command In Command #10H

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data AAH Address 555H Write Data 80H Address 555H YES NOToggle Bit Checking Q6 not Toggled Write Data 10H Address 555H Write Data 55H Address 2AAH Reset Auto Chip Erase Exceed Timing Limit DATA Polling Q7 = 1 YES Q5 = 1Auto Chip Erase Completed NO . NOInvalid Command YES

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 Block data indicated by A16 to A19 are erased. External erase verify is not required because data are erased automatically by internal control circuit. Erasure comple- tion can be verified by DATA polling and toggle bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) AUTOMATIC SECTOR ERASE TIMING WAVEFORM AUTOMATIC SECTOR ERASE TIMING WAVEFORM tAH Sector Address0 555H 2AAH 2AAH 555H 555H Sector Address1 Sector Addressn Vcc 5V CE OE Q0,Q1, Q4(Note 1) WE A16-A19 A0~A10 Command In Command In Command In Command In Command In Command In Command In Command In Command In Command In Command In Command In Command In Command In Command #30HCommand #30HCommand #30HCommand #55HCommand #AAHCommand #80HCommand #55HCommand #AAH (Q0~Q7) Command In Command In tDHtDS tCEP tCWC tAETB tBAL DATA polling tCEPH1 tAS Notes: (1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data AAH Address 555H Write Data 80H Address 555H YES NOToggle Bit Checking Q6 not Toggled Write Data 30H Sector Address Write Data 55H Address 2AAH Reset Auto Sector Erase Exceed Timing Limit DATA Polling Q7 = 1 Q5 = 1 Auto Sector Erase Completed Load Other Sector Addrss If Necessary (Load Other Sector Address) YES NOLast Sector to Erase Time-out Bit Checking Q3=1 ? Toggle Bit Checking Q6 Toggled ? Invalid Command NO YES YES NO

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 ERASE SUSPEND/ERASE RESUME FLOWCHART START Write Data B0H Toggle Bit checking Q6 not toggled YES NO Write Data 30H Continue Erase Reading or Programming End Read Array or Program Another Erase Suspend ? NO YES YES NO

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 TIMING WAVEFORM FOR SECTOR GROUP PROTECTION tOE Data OE WE 12V 12V CE tOESP tWPP 1 tVLHT tVLHT tVLHT Verify 01H F0H A19-A17 Sector Address

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 TIMING WAVEFORM FOR CHIP UNPROTECTION tOE Data OE WE 12V 12V CE tOESP tWPP 2 tVLHT tVLHT tVLHT Verify 00H Sector AddressA19-A17 F0H

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 SECTOR GROUP PROTECTION ALGORITHM START Set Up Sector Group Addr (A19, A18, A17) PLSCNT=1 Sector Group Protection Complete Data=01H? Ye s OE=VID,A9=VID,CE=VIL A6=VIL Activate WE Pulse Time Out 10us Set WE=VIH, CE=OE=VIL A9 should remain VID Read from Sector Group Addr=SGA, A1=1 Protect Another Sector Group? Remove VID from A9 Write Reset Command Device Failed PLSCNT=32? Ye s No No

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 CHIP UNPROTECTION ALGORITHM START Protect All Sectors PLSCNT=1 Chip Unprotect Complete Data=00H? Ye s Set OE=A9=VID CE=VIL,A6=1 Activate WE Pulse Time Out 12ms Set OE=CE=VIL A9=VID,A1=1 Set Up First Sector Addr All sectors have been verified? Remove VID from A9 Write Reset Command Device Failed PLSCNT=1000? No Increment PLSCNT No Read Data from Device Ye s Ye s No Increment Sector Addr * It is recommended before unprotect the whole chip, all sectors should be protected in advance.

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 RESET TIMING WAVEFORM AC CHARACTERISTICS Parameter Std Description Test Setup All Speed OptionsUnit tREADY1 RESET PIN Low (During Automatic Algorithms) MAX 20 us to Read or Write (See Note) tREADY2 RESET PIN Low (NOT Dur ing Automatic MAX 500 ns Algorithms) to Read or Write (See Note) tRP1 RESET Pulse Width (During Automatic Algorithms) MIN 10 us tRP2 RESET Pulse Width (NOT During Automatic Algorithms) MIN 500 ns tRH RESET High Time Before Read (See Note) MIN 0 ns tRB1 R Y/BY Recovery Time (to CE, OE go low) MIN 0 ns tRB2 R Y/BY Recovery Time (to WE go low) MIN 50 ns Note:Not 100% tested tRH tRB1 tRB2 tReady1 tRP2 tRP1 tReady2 RY/BY CE, OE RESET Reset Timing NOT during Automatic Algorithms Reset Timing during Automatic Algorithms RY/BY CE, OE RESET WE

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 RESET CE WE RY/BY tVIDR tVIDRProgram or Erase Command Sequence 12V 0 or 5V 0 or 5V tRSP TEMPORARY SECTOR UNPROTECT Parameter Std. Description Test Setup All Speed OptionsUnit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tRSP RESET Setup Time for Temporary Sector Unprotect Min 4 us Note: Not 100% tested TEMPORARY SECTOR GROUP UNPROTECT TIMING WAVEFORM

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 TEMPORARY SECTOR GROUP UNPROTECT ALGORITHM Start RESET = VID (Note 1) Perform Erase or Program Operation RESET = VIH Temporary Sector Group Unprotect Completed(Note 2) Operation Completed 2. All previously protected sectors are protected again. Note : 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 ID CODE READ TIMING WAVEFORM tACC tCE tACC tOE tOH tOH tDF DATA OUT C2H D5H ADD ADD A2-A8 A10-A19 CE OE WE ADD DATA OUTDATA Q0-Q7 VCC VIH VIL VID VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080 MIN. MAX. Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V Current -100mA +100mA Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. LIMITS PARAMETER MIN. TYP.(2) MAX. UNITS Sector Erase Time 1.3 10.4 sec Chip Erase Time 8 64 sec Byte Programming Time 7 210 us Chip Programming Time 8 24 sec Erase/Program Cycles 10,000 Cycles LATCH-UP CHARACTERISTICS ERASE AND PROGRAMMING PERFORMANCE (1) Note: 1. Not 100% Tested, Excludes external system level over head. 2. Typical values measured at 25°C,5V.

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080

ORDERING INFORMATION

PART NO. ACCESS TIME OPERATING CURRENT STANDBY CURRENT PACKAGE (ns) MAX.(mA) MAX. (uA) MX29F080TC-70 70 50 5 40 Pin TSOP (Normal Type) MX29F080TC-90 90 50 5 40 Pin TSOP (Normal Type) MX29F080TC-12 120 50 5 40 Pin TSOP (Normal Type) MX29F080MC-70 70 50 5 44 Pin SOP MX29F080MC-90 90 50 5 44 Pin SOP MX29F080MC-12 120 50 5 44 Pin SOP

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080

PACKAGE INFORMATION

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080

P/N:PM0579 REV. 1.6, NOV. 21, 2002 MX29F080

REVISION HISTORY

Revision Description Page Date 1.1 Add erase suspend ready max. 100us in ERASE SUSPEND's P10 MA Y/29/2000 section at page10

1.2 Modify Package Information 40-pin TSOP P35 A UG/10/2000

1.3 To modify "Package Information" P35~36 JUN/18/2001

Modify "Chip Unprotection Algorithm" P28

1.4 To modify Package Information--40-TSOP(10x20mm) P35 JAN/16/2002

1.5 To corrected typing error All JUN/10/2002

1.6 To modify Package Information P35~36 NOV/21/2002

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