29F040

M29F040 STMICROELECTRONICS | Alldatasheet

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Technical content

Figure 1. Logic Diagram

4 Mbit (512Kb x8, Uniform Block) Single Supply Flash Memory

20 YEARS DATA RETENTION

Table 1. Signal Names This is information on a product still in production but not recommended for new designs.

E DQ5 DQ1 DQ2 DQ3 DQ4 DQ6 A17 W A16 A12 A18 VCC A15 AI01379 M29F040 (Normal) 16 17 VSS Figure 2B. TSOP Pin Connections AI01378 A17 A13 A10 DQ5 DQ0 DQ1 DQ2 DQ3 DQ4 W

1 A16

32 A18

G E VSS Figure 2A. LCC Pin Connections DQ0 A4A3 A13 A10 DQ7 A14 A11G E DQ5 DQ1 DQ2 DQ3 DQ4 DQ6 A17 W A16 A12 A18 VCC A15 AI01174B M29F040 (Reverse) 16 17 VSS Figure 2C. TSOP Reverse Pin Connections DESCRIPTION The M29F040 is a non-volatile memory that may be erased electrically at the block level, and pro- grammed Byte-by-Byte. The interface is directly compatible with most mi- croprocessors. PLCC32 and TSOP32 (8 x 20mm) packages are available. Both normal and reverse pin outs are available for the TSOP32 package. Organisation The Flash Memory organisation is 512K x8 bits with Address lines A0-A18 and Data Inputs/Outputs DQ0-DQ7. Memory control is provided by Chip Enable, Output Enable and Write Enable Inputs. Erase and Program are performed through the internal Program/Erase Controller (P/E.C.). Data Outputs bits DQ7 and DQ6 provide polling or toggle signals during Automatic Program or Erase to indicate the Ready/Busy state of the internal Program/Erase Controller. Memory Blocks Erasure of the memory is in blocks. There are 8 uniform blocks of 64 Kbytes each in the memory address space. Each block can be programmed and erased over 100,000 cycles. Each uniform block may separately be protected and unpro- M29F040

1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

Table 2. Absolute Maximum Ratings (1) blocks of the memory, and then resumed. mand Interface which is common to all P/E.C. command instruction to the Command Interface. tion or the addressed data for Read operations.

Table 3. Operations Table 4. Electronic Signature Table 5. Block Protection Status forced to VID during Block Unprotect operations. Block Protect and Block Unprotect operations. Command Register and Address and Data latches. Data Inputs are latched on the rising edge of W. operations (Read, Program and Erase).

Read Memory Array until a new write cycle is initiated. write cycle is initiated. See Note 5. cycle is initiated. See Note 6. uniform block(s) not being erased then Resume Erase. Notes:1. Command not interpreted in this table will default to read array mode.

1. The first cycle of the RST, RBP or RSIG instruction is followed by read operations to read memory array, Status Register or

Electronic Signature codes. Any number of read cycles can occur after one command cycle.

1. Signature Address bits A0, A1, A6 at V
2. Protection Address: A0, A6 at VIL, A1 at VIH and A16, A17, A18 within the uniform block to be checked, will output the Block Protection
3. Address bits A15-A18 are don’t care for coded address inputs.
4. Optional, additional blocks addresses must be entered within a 80µs delay after last write entry, timeout status can be verified

through DQ3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.

1. Read Data Polling or Toggle bit until Erase completes.
2. A wait time of 5µs is necessary after a Reset command, if the memory is in a Block Erase status, before starting

Table 6. Instructions (1,2)

Figure 3. The memory array is divided in 8 uniform other block, and then resumed. Block Protection provides additional data security. RST and RSIG, and Status Bits). on the falling edge of W or E whichever occurs last. W or E whichever occurs first. are ignored. The codes are output on DQ0-DQ7. separately protected against Program or Erase. VID and the block address is applied on A16-A18. G, E and A6 to VIL while W is at VIH and A9 at VID. of the 8 uniform blocks have been unprotected. Block Protection Status is shown in Table 5.

Figure 3. Memory Map and Block Address Table Table 7. CommandsInstructions and Commands of commands will reset the device to Read Array. DQ6, or Error on DQ5 and Erase Timer DQ3 bits.

7 Data

6 Toggle Bit

3 Erase

2 Reserved

1 Reserved

0 Reserved

Note: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. Table 8. Status Register plement of the bit being programmed on DQ7. Figure 12 for Toggle Bit waveforms. data after write operation is completed.

Table 11. DC Characteristics protected and a 00h if block is not protected. phase as a method to verify the block protection. Please refer to Block Protection paragraph. Polling bit DQ7 returns ’0’, then ’1’ on completion. number of erase cycles have been executed.

Symbol Alt Parameter Test Condition M29F040 Unit -70 -90 VCC = 5V ± 5% V CC = 5V ± 10% Standard Interface Standard Interface Min Max Min Max tAVAV tRC Address Valid to Next Address ValidE = VIL, G = VIL 70 90 ns tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL 70 90 ns tELQX (1) tLZ Chip Enable Low to Output TransitionG = VIL 00 n s tELQV (2) tCE Chip Enable Low to Output Valid G = VIL 70 90 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL 00 n s tGLQV (2) tOE Output Enable Low to Output Valid E = VIL 30 35 ns tEHQX tOH Chip Enable High to Output Transition G = VIL 00 n s tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL 20 20 ns tGHQX tOH Output Enable High to Output Transition E = VIL 00 n s tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL 20 20 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 20 20 ns Notes:1. Sampled only, not 100% tested. 2.G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV . 3. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%. Table 12A. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(3) Block Erase (BE) instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two coded cycles. The Block Erase Confirm command 30h is written on sixth cycle after another two coded cycles. During the input of the second command an address within the block to be erased is given and latched into the memory. Additional Block Erase confirm com- mands and block addresses can be written sub- sequently to erase other blocks in parallel, without further coded cycles. The erase will start after an Erase timeout period of about 100µs. Thus, addi- tional Block Erase commands must be given within this delay. The input of a new Block Erase com- mand will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is ’0’ the Block Erase Com- mand has been given and the timeout is running, if DQ3 is ’1’, the timeout has expired and the P/E.C is erasing the block(s). Before and during Erase timeout, any command different from 30h will abort the instruction and reset the device to read array mode. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before erasing to FFh. Read operations after the sixth rising edge of W or E output the status register bits. During the execution of the erase by the P/E.C., the memory accepts only the ES (Erase Suspend) and RST (Reset) instructions. Data Polling bit DQ7 returns ’0’ while the erasure is in progress and ’1’ when it has completed. The Toggle Bit DQ6 toggles during the erase operation. It stops when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure because erasure has not completed even after the maximum number of erase cycles have been executed. In this case, it will be necessary to input a Reset (RST) to the command interface in order to reset the P/E.C. M29F040

Symbol Alt Parameter Test Condition M29F040 Unit -120 -150 VCC = 5V ± 10% V CC = 5V ± 10% Standard Interface Standard Interface Min Max Min Max tAVAV tRC Address Valid to Next Address ValidE = VIL, G = VIL 120 150 ns tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL 120 150 ns tELQX (1) tLZ Chip Enable Low to Output TransitionG = VIL 00 n s tELQV (2) tCE Chip Enable Low to Output Valid G = VIL 120 150 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL 00 n s tGLQV (2) tOE Output Enable Low to Output Valid E = VIL 50 55 ns tEHQX tOH Chip Enable High to Output Transition G = VIL 00 n s tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL 30 35 ns tGHQX tOH Output Enable High to Output Transition E = VIL 00 n s tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL 30 35 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 20 20 ns Notes:1. Sampled only, not 100% tested. 2.G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV . Table 12B. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C) Program (PG) instruction. The memory can be programmed Byte-by-Byte. This instruction uses four write cycles. The Program command A0h is written on the third cycle after two coded cycles. A fourth write operation latches the Address on the falling edge of W or E and the Data to be written on its rising edge and starts the P/E.C. During the execution of the program by the P/E.C., the mem- ory will not accept any instruction. Read operations output the status bits after the programming has started. The status bits DQ5, DQ6 and DQ7 allow a check of the status of the programming operation. Memory programming is made only by writing ’0’ in place of ’1’ in a Byte. Erase Suspend (ES) instruction. The Block Erase operation may be suspended by this instruc- tion which consists of writing the command 0B0h without any specific address code. No coded cycles are required. It allows reading of data from another block while erase is in progress. Erase suspend is accepted only during the Block Erase instruction execution and defaults to read array mode. Writing this command during Erase timeout will, in addition to suspending the erase, terminate the timeout. The Toggle Bit DQ6 stops toggling when the P/E.C. is suspended. Toggle Bit status must be monitored at an address out of the block being erased. Toggle Bit will stop toggling between 0.1µs and 15µs after the Erase Suspend (ES) command has been writ- ten. The M29F040 will then automatically set to Read Memory Array mode. When erase is suspended, Read from blocks being erased will output invalid data, Read from block not being erased is valid. During the suspension the memory will respond only to Erase Resume (ER) and Reset (RST) in- structions. RST command will definitively abort erasure and result in the invalid data in the blocks being erased. M29F040

Figure 6. Read Mode AC Waveforms

-70 -90 VCC = 5V ± 10% V CC = 5V ± 10% Standard Interface Standard Interface Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 70 90 ns tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns tWLWH tWP Write Enable Low to Write Enable High 35 45 ns tDVWH tDS Input Valid to Write Enable High 30 45 ns tWHDX tDH Write Enable High to Input Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low 20 20 ns tAVWL tAS Address Valid to Write Enable Low 0 0 ns tWLAX tAH Write Enable Low to Address Transition 45 45 ns tGHWL Output Enable High to Write Enable Low 0 0 ns tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs tWHQV1 (1) Write Enable High to Output Valid (Program) 10 10 µs tWHQV2 (1) Write Enable High to Output Valid (Block Erase) 1.0 30 1.0 30 sec tWHGL t OEH Write Enable High to Output Enable Low 0 0 ns Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV 2. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%. Table 13A. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(2) Erase Resume (ER) instruction. If an Erase Sus- pend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any coded cycles. Power Up The memory Command Interface is reset on power up to Read Array. Either E or W must be tied to VIH during Power-up to allow maximum security and the possibility to write a command on the first rising adge of E or W. Any write cycle initiation is blocked when VCC is below VLKO . Supply Rails Normal precautions must be taken for supply volt- age decoupling, each device in a system should have the V CC rail decoupled with a 1.0µF capacitor close to the VCC and VSS pins. The PCB trace widths should be sufficient to carry the VCC pro- gram and erase currents required. M29F040

-120 -150 VCC = 5V ± 10% V CC = 5V ± 10% Standard Interface Standard Interface Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 120 150 ns tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns tWLWH tWP Write Enable Low to Write Enable High 50 50 ns tDVWH tDS Input Valid to Write Enable High 50 50 ns tWHDX tDH Write Enable High to Input Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low 20 20 ns tAVWL tAS Address Valid to Write Enable Low 0 0 ns tWLAX tAH Write Enable Low to Address Transition 50 50 ns tGHWL Output Enable High to Write Enable Low 0 0 ns tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs tWHQV1 (1) Write Enable High to Output Valid (Program) 10 10 µs tWHQV2 (1) Write Enable High to Output Valid (Block Erase) 1.0 30 1.0 30 sec tWHGL t OEH Write Enable High to Output Enable Low 0 0 ns Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV Table 13B. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C) M29F040

Figure 7. Write AC Waveforms, W Controlled Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

-70 -90 VCC = 5V ± 10% V CC = 5V ± 10% Standard Interface Standard Interface Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 70 90 ns tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High 35 45 ns tDVEH tDS Input Valid to Chip Enable High 30 45 ns tEHDX tDH Chip Enable High to Input Transition 0 0 ns tEHWH tWH Chip Enable High to Write Enable High 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low 20 20 ns tAVEL tAS Address Valid to Chip Enable Low 0 0 ns tELAX tAH Chip Enable Low to Address Transition 45 45 ns tGHEL Output Enable High Chip Enable Low 0 0 ns tVCHWL tVCS VCC High to Write Enable Low 50 50 µs tEHQV1 (1) Chip Enable High to Output Valid (Program) 10 10 µs tEHQV2 (1) Chip Enable High to Output Valid (Block Erase) 1 . 03 01 . 03 0 s e c tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV . 2. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%. Table 14A. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(2) M29F040

-120 -150 VCC = 5V ± 10% V CC = 5V ± 10% Standard Interface Standard Interface Min Max Min Max tAVAV tWC Address Valid to Next Address Valid 120 150 ns tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High 50 50 ns tDVEH tDS Input Valid to Chip Enable High 50 50 ns tEHDX tDH Chip Enable High to Input Transition 0 0 ns tEHWH tWH Chip Enable High to Write Enable High 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low 20 20 ns tAVEL tAS Address Valid to Chip Enable Low 0 0 ns tELAX tAH Chip Enable Low to Address Transition 50 50 ns tGHEL Output Enable High Chip Enable Low 0 0 ns tVCHWL tVCS VCC High to Write Enable Low 50 50 µs tEHQV1 (1) Chip Enable High to Output Valid (Program) 10 10 µs tEHQV2 (1) Chip Enable High to Output Valid (Block Erase) 1.0 30 1.0 30 sec tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + tQ7VQV . Table 14B. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C) M29F040

Figure 8. Write AC Waveforms, E Controlled Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.

-70 -90 VCC = 5V ± 10% V CC = 5V ± 10% Standard Interface Standard Interface Min Max Min Max tWHQ7V1 (2) Write Enable High to DQ7 Valid (Program, W Controlled) 10 10 µs tWHQ7V2 (2) Write Enable High to DQ7 Valid (Block Erase, W Controlled) 1.0 30 1.0 30 sec tEHQ7V1 (2) Chip Enable High to DQ7 Valid (Program, E Controlled) 10 10 µs tEHQ7V2 (2) Chip Enable High to DQ7 Valid (Block Erase, E Controlled) 1.0 30 1.0 30 sec tQ7VQV Q7 Valid to Output Valid (Data Polling) 30 35 ns tWHQV1 Write Enable High to Output Valid (Program) 10 10 µs tWHQV2 Write Enable High to Output Valid (Block Erase) 1.0 30 1.0 30 sec tEHQV1 Chip Enable High to Output Valid (Program) 10 10 µs tEHQV2 Chip Enable High to Output Valid (Block Erase) 1.0 30 1.0 30 sec Notes:1. All other timings are defined in Read AC Characteristics table. 2. tWHQ7V is the Program or Erase time. 3. The temperature range –40 to 125°C is guaranteed at 70ns with High Speed Interface test condition and VCC = 5V ± 5%. Table 15A. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C)(3) M29F040

VCC = 5V ± 10% V CC = 5V ± 10% Standard Interface Standard Interface Min Max Min Max tWHQ7V1 (2) Write Enable High to DQ7 Valid (Program, W Controlled) 10 10 µs tWHQ7V2 (2) Write Enable High to DQ7 Valid (Block Erase, W Controlled) 1.0 30 1.0 30 sec tEHQ7V1 (2) Chip Enable High to DQ7 Valid (Program, E Controlled) 10 10 µs tEHQ7V2 (2) Chip Enable High to DQ7 Valid (Block Erase, E Controlled) 1.0 30 1.0 30 sec tQ7VQV Q7 Valid to Output Valid (Data Polling) 50 55 ns tWHQV1 Write Enable High to Output Valid (Program) 10 10 µs tWHQV2 Write Enable High to Output Valid (Block Erase) 1.0 30 1.0 30 sec tEHQV1 Chip Enable High to Output Valid (Program) 10 10 µs tEHQV2 Chip Enable High to Output Valid (Block Erase) 1.0 30 1.0 30 sec Notes:1. All other timings are defined in Read AC Characteristics table. 2. tWHQ7V is the Program or Erase time. Table 15B. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70°C, –20 to 85°C, –40 to 85°C or –40 to 125°C) M29F040

Figure 9. Data Polling DQ7 AC Waveforms Notes:1. All other timings are as a normal Read cycle.

1. DQ7 and DQ0-DQ6 can transmit to valid at any point during the data output valid period.
2. tWHQ7V is the Program or Erase time.
3. During erasing operation Byte address must be within Block being erased.

Figure 12. Data Toggle DQ6 AC Waveforms Note: All other timings are as a normal Read cycle.

Figure 13. Block Protection Flowchart

Figure 14. Block Unprotecting Flowchart reads, A6 must be kept at VIL.

ORDERING INFORMATION SCHEME M29F040 is replaced by the new version M29F040B Device are shipped from the factory with the memory content erased (to FFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Operating Voltage F5 V Speed -70 70ns -90 90ns -120 120ns -150 150ns Power Supplies blank V CC ± 10% XV CC ± 5% Package K PLCC32 N TSOP32 8 x 20mm Option R Reverse Pinout TR Tape & Reel Packing Temp. Range 1 0 to 70 °C 3 –40 to 125 °C 5 –20 to 85 °C 6 –40 to 85 °C Example: M29F040 -70 X N 1 TR M29F040

D Ne E1 E 1 N Nd CP B D2/E2 e A R 0.51 (.020) 1.14 (.045) F Symb mm inches Typ Min Max Typ Min Max A 2.54 3.56 0.100 0.140 A1 1.52 2.41 0.060 0.095 A2 – 0.38 – 0.015 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 F 0.00 0.25 0.000 0.010 N3 2 3 2 Nd 7 7 Ne 9 9 CP 0.10 0.004 Drawing is not to scale. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular M29F040

E 1 N CP B e A N/2 D DIE C LA1 α Symb mm inches Typ Min Max Typ Min Max A 1.20 0.047 A1 0.05 0.15 0.002 0.007 A2 0.95 1.05 0.037 0.041 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 7.90 8.10 0.311 0.319 L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N3 2 3 2 CP 0.10 0.004 Drawing is not to scale. TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm M29F040

E 1 N CP B e A N/2 D DIE C LA1 α Symb mm inches Typ Min Max Typ Min Max A 1.20 0.047 A1 0.05 0.17 0.002 0.006 A2 0.95 1.05 0.037 0.041 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 7.90 8.10 0.311 0.319 L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N3 2 3 2 CP 0.10 0.004 Drawing is not to scale. TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm M29F040

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com M29F040