M29F010B STMICROELECTRONICS | Alldatasheet
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Technical content
1 Mbit (128Kb x8, Uniform Block) Single Supply Flash Memory
Figure 1. Logic Diagram
Figure 2. PLCC Connections
1 A16
Figure 3. TSOP Connections Table 2. Uniform Block Addresses, M29F010B Table 1. Signal Names
the same way as a ROM or EPROM. nals control the bus operation of the memory. cessors, often without additional logic. Table 3. Absolute Maximum Ratings
- Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
specifications are available at: www.st.com. Command Interface of the internal state machine. High, VIH, all other pins are ignored. trols the Bus Read operation of the memory.
VLKO . This prevents Bus Write operations from ac- cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1µF capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I CC4 . Vss Ground. The VSS Ground is the reference for all voltage measurements. BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby and Automatic Standby. See Table 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not af- fect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Com- mand Interface. A valid Bus Read operation in- volves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 8, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid. Bus Write.Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Ad- dress Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Com- mand Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output En- able must remain High, V IH, during the whole Bus Write operation. See Figures 9 and 10, Write AC Waveforms, and Tables 12 and 13, Write AC Characteristics, for details of the timing require- ments. Output Disable.The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Standby. When Chip Enable is High, VIH, the Data Inputs/Outputs pins are placed in the high- impedance state and the Supply Current is re- duced to the Standby level. When Chip Enable is at V IH the Supply Current is reduced to the TTL Standby Supply Current ICC2 . To further reduce the Supply Current to the CMOS Standby Supply Current, ICC3 , Chip Enable should be held within VCC ± 0.2V. For Standby current levels see Table 10, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC4 , for Program or Erase operations un- til the operation completes. Automatic Standby.If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is re- duced to the CMOS Standby Supply Current, I CC3 . The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. They require V ID to be applied to some pins. Electronic Signature.The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 4, Bus Operations. Block Protection and Blocks Unprotection.Each block can be separately protected against acci- dental Program or Erase. Protected blocks can be unprotected to allow data to be changed. Block Protection and Blocks Unprotection operations must only be performed on programming equip- ment. For further information refer to Application Note AN1122, Applying Protection and Unprotec- tion to M29 Series Flash.
Table 4. Bus Operations are imposed to maximize data security. leave invalid data in the memory. Device Code and the Block Protection Status. Code for STMicroelectronics is 20h. Device Code for the M29F010B is 20h. no error condition is given. the Status Register on the Data Inputs/Outputs. set the error condition and return to Read mode.
mands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memo- ry. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these com- mands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been is- sued the memory will only accept the Unlock By- pass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. Unlock Bypass Program Command. The Un- lock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Pro- gram/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Pro- gram operation using the Program command. A protected block cannot be programmed; the oper- ation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock By- pass Mode. See the Program command for details on the behavior. Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Chip Erase Command. The Chip Erase com- mand can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation ap- pears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any com- mand to abort the operation. Typical chip erase times are given in Table 6. All Bus Read opera- tions during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in un- protected blocks of the memory to ’1’. All previous data is lost. Block Erase Command. The Block Erase com- mand can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data un- changed. No error condition is given when protect- ed blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend and Read/Reset commands. Typical block erase times are given in Table 6. All Bus Read opera- tions during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Erase Suspend Command. The Erase Suspend Command may be used to temporarily suspend a
Table 5. Commands Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care. Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Operations until the Timeout Bit is set. Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued. on non-erasing blocks as normal. Erase Controller completes and the memory returns to Read Mode. blocks for erasure after the Erase Resume. memory to Erase Suspend mode. can be suspended and resumed more than once.
completes the memory returns to Read mode. the memory cell data as if in Read mode. Table 7. Status Register Bits Note: Unspecified data bits should be ignored.
Table 10. DC Characteristics Note: 1. Sampled only, not 100% tested.
Figure 8. Read Mode AC Waveforms Table 11. Read AC Characteristics Note: 1. Sampled only, not 100% tested.
Figure 9. Write AC Waveforms, Write Enable Controlled Table 12. Write AC Characteristics, Write Enable Controlled
Table 13. Write AC Characteristics, Chip Enable Controlled Figure 10. Write AC Waveforms, Chip Enable Controlled
Table 14. Ordering Information Scheme parts, otherwise devices are shipped from the factory with the memory content bits erased to ’1’. vice, please contact the ST Sales Office nearest to you.
Table 16. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data Figure 11. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline Note: Drawing is not to scale.
Table 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data Figure 12. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline Note: Drawing is not to scale.
Table 15. Revision History Table 14. Ordering Information Scheme: standard package added and ECOPACK version added for both standard package, and Tape & Reel packing.
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