291PG

ICS291 IDT | Alldatasheet

Document overview

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• PDF pages: 10

Technical content

Features

• Packaged as 20-pin TSSOP
• Eight addressable registers
• Replaces multiple crystals and oscillators
• Output frequencies up to 200 MHz at 3.3 V
• Configurable Spread Spectrum Modulation
• Input crystal frequency of 5 to 27 MHz
• Clock input frequency of 3 to 166 MHz
• Up to six reference outputs
• Separate 1.8 to 3.3 V VDDO output level controls for each bank of 3 outputs
• Up to two sets of three low-skew outputs
• Operating voltages of 3.3 V
• Controllable output drive levels
• Advanced, low-power CMOS process
• Available in Pb (lead) free packaging Block Diagram Crystal Oscillator GND 3 3VDD PDTS PLL2 PLL3 Divide Logic and Output Enable Control S2:S0 CLK1 CLK6 CLK5 CLK4 CLK3 CLK2 OTP ROM with PLL Values Crystal or Clock Input External capacitors are required with a crystal input. X1/ICLK PLL1 with Spread Spectrum VDDO1 VDDO2

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 2 ICS291 REV D 061306 Pin Assignment Pin Descriptions VDD GND CLK2 CLK5CLK1 CLK3 CLK6 VDDO2 3S1 GND S2

18 PDTS

20 pin (173 mil) TSSOP X1/ICLK Pin Number Pin Name Pin Type Pin Description 1 GND Power Connect to ground. 2 S0 Input Select pin 0. Internal pull-up resistor. 3 S1 Input Select pin 1. Internal pull-up resistor. 4V D D P o w e r Connect to +3.3 V. 5 VDDO1 Power Power supply for outputs CLK1-CLK3. 6 CLK1 Output Output clock 1. Weak internal pull-down when tri-state. 7 CLK2 Output Output clock 2. Weak internal pull-down when tri-state. 8 CLK3 Output Output clock 3. Weak internal pull-down when tri-state. 9 GND Power Connect to ground. 10 X1/ICLK XI Crystal input. Connect this pin to a crystal or external input clock. 11 X2 XO Crystal Output. Connect this pin to a crystal. Float for clock input. 12 VDD Power Connect to +3.3 V. 13 VDDO2 Power Power supply for outputs CLK4-CLK6. 14 CLK4 Output Output clock 4. Weak internal pull-down when tri-state. 15 CLK5 Output Output clock 5. Weak internal pull-down when tri-state. 16 CLK6 Output Output clock 6. Weak internal pull-down when tri-state. 17 GND Power Connect to ground. Input Power-down tri-state. Powers down entire chip and tri-states clock outputs when low. Internal pull-up resistor. 19 VDD Power Connect to +3.3 V. 20 S2 Input Select pin 2. Internal pull-up resistor.

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 3 ICS291 REV D 061306 External Components The ICS291 requires a minimum number of external components for proper operation. Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS291 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias on the decoupling circuit. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (C L -6 pF)*2. In this equation, CL= crystal load capacitance in pF . Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. ICS291 Configuration Capabilities The architecture of the ICS291 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 1024 and N = 1 to 32,895. The ICS291 also provides separate output divide values, from 2 through 63, to allow the two output clock banks to support widely differing frequency values from the same PLL. Each output frequency can be represented as: Output Drive Control The ICS291 has two output drive settings. For VDDO=VDD, low drive should be selected when outputs are less than 100 MHz. High drive should be selected when outputs are greater than 100 MHz. For VDDO<2.8 V, high drive should be selected for all output frequencies. (Consult the AC Electrical Characteristics for output rise and fall times for each drive option.) ICS VersaClock Software ICS applies years of PLL optimization experience into a user friendly software that accepts the user’s target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple output frequencies. VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds. Spread Spectrum Modulation The ICS291 utilizes frequency modulation (FM) to distribute energy over a range of frequencies. By modulating the output clock frequencies, the device effectively lowers energy across a broader range of frequencies; thus, lowering a system’s electromagnetic interference (EMI). The modulation rate is the time from transitioning from a minimum frequency to a maximum frequency and then back to the minimum. OutputFreq REFFreq M N-----⋅=

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 4 ICS291 REV D 061306 Spread Spectrum Modulation can be applied as either “center spread” or “down spread”. During center spread modulation, the deviation from the target frequency is equal in the positive and negative directions. The effective average frequency is equal to the target frequency. In applications where the clock is driving a component with a maximum frequency rating, down spread should be applied. In this case, the maximum frequency, including modulation, is the target frequency. The effective average frequency is less than the target frequency. The ICS291 operates in both center spread and down spread modes. For center spread, the frequency can be modulated between ±0.125% to ±2.0%. For down spread, the frequency can be modulated between -0.25% to -4.0%. Both output frequency banks will utilize identical spread spectrum percentage deviations and modulation rates, if a common VCO frequency can be identified. Spread Spectrum Modulation Rate The spread spectrum modulation frequency applied to the output clock frequency may occur at a variety of rates. For applications requiring the driving of “down-circuit” PLLs, Zero Delay Buffers, or those adhering to PCI standards, the spread spectrum modulation rate should be set to 30-33 kHz. For other applications, a 120 kHz modulation option is available. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS291. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Parameter Condition Min. Typ. Max. Units Supply Voltage, VDD Referenced to GND 7 V Inputs Referenced to GND -0.5 VDD+0.5 V Clock Outputs Referenced to GND -0.5 VDD+0.5 V Storage Temperature -65 150 ° C Soldering Temperature Max 10 seconds 260 ° C Junction Temperature 125 ° C Parameter Min. Typ. Max. Units Ambient Operating Temperature (ICS291GP) 0 +70 ° C Ambient Operating Temperature (ICS291GIP) -40 +85 ° C Power Supply Voltage (measured in respect to GND) +3.135 +3.3 +3.465 V Power Supply Ramp Time 4 ms

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 5 ICS291 REV D 061306 Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C Note 1: Example with 25 MHz crystal input with six outputs of 33.3 MHz, no load, and VDD = 3.3 V. Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.135 3.465 V VDDO Voltage VDDO1 and VDDO2 1.80 VDD V Operating Supply Current IDD Config. Dependent - See VersaClockTM Estimates mA Six 33.3333 MHz outs, VDD=VDDO=3.3 V; PDTS = 1, no load, Note 1 25 mA PDTS = 0, no load 500 µA Input High Voltage V IH S2:S0 VDD/2+1 V Input Low Voltage V IL S2:S0 0.4 V Input High Voltage, PDTS VIH VDD-0.5 V Input Low Voltage, PDTS VIL 0.4 V Input High Voltage V IH ICLK VDD/2+1 V Input Low Voltage V IL ICLK VDD/2-1 V Output High Voltage (CMOS High) VOH IOH = -4 mA VDD-0.4 V Output High Voltage V OH IOH = -8 mA (Low Drive); IOH = -12 mA (High Drive) 2.4 VDDO-0.4 V Output Low Voltage V OL IOL = 8 mA (Low Drive); IOL = 12 mA (High Drive) 0.4 V Short Circuit Current I OS Low Drive ±40 mAHigh Drive ±70 Nom. Output Impedance Z O 20 Ω Internal Pull-up Resistor R PUS S2:S0, PDTS 190 k Ω Internal Pull-down Resistor RPD CLK outputs 120 k Ω Input Capacitance C IN Inputs 4 pF

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 6 ICS291 REV D 061306 Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C Note 1: Measured with 15 pF load. Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%. Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency F IN Fundamental crystal 5 27 MHz Clock input 3 166 MHz Output Frequency VDDO=VDD 0.314 200 MHz 1.8 V<VDDO<2.8 V 0.314 150 MHz Output Rise/Fall Time t OF 80% to 20%, high drive, Note 1 1.0 ns Output Rise/Fall Time t OF 80% to 20%, low drive, Note 1 2.0 ns Output Rise/Fall Time t OF 80% to 20%, high drive, 1.8 V<VDDO<2.8 Note 2 2.0 ns Duty Cycle Note 2 40 49-51 60 % Output Frequency Synthesis Error Configuration Dependent TBD ppm Power-up time PLL lock-time from power-up 41 0 m s PDTS goes high until stable CLK output, Spread Spectrum Off 0.6 2 ms PDTS goes high until stable CLK output, Spread Spectrum On 47 m s One Sigma Clock Period Jitter Configuration Dependent 50 ps Maximum Absolute Jitter t ja Deviation from Mean. Configuration Dependent +200 ps Pin-to-Pin Skew Low Skew Outputs -250 250 ps Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 93 ° C/W θJA 1 m/s air flow 78 ° C/W θJA 3 m/s air flow 65 ° C/W Thermal Resistance Junction to Case θJC 20 ° C/W

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 7 ICS291 REV D 061306 Marking Diagrams Marking Diagrams (Pb free) Notes: 2. YYWW is the last two digits of the year and week that the part was assembled. 3. “I” denotes industrial temperature range (if applicable). 4. “L ” denotes Pb (lead) free package. 5. Bottom marking: country of origin. 1 10 1120 YYWW$$ 291PG 1 10 1120 YYWW$$ 291PGI 1 10 1120 YYWW 291PGL 1 10 1120 YYWW 291PGIL

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 8 ICS291 REV D 061306 Package Outline and Package Dimensions (20-pin TSSOP, 173 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b .10 (.004) C c L Millimeters Inches Symbol Min Max Min Max A — 1.20 — .047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 C 0.09 0.20 0.0035 0.008 D 6.40 6.60 0.252 0.260 E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 0.169 0.177 e 0.65 Basic 0.0256 Basic L 0 . 4 50 . 7 5. 0 1 8. 0 3 0 α 0° 8° 0° 8°

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 9 ICS291 REV D 061306

Ordering Information

Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. The 291G-XX, 291G-XXLF, 291GI-XX, and 291GI-XXLF are factory programmed versions of the 291PG, 291PGLF, 291PGI, and 291PGILF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing representative. While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. VersaClockTM is a trademark of Integrated Circuit Systems, Inc. All rights reserved. Part / Order Number Marking Shipping Packaging Package Temperature 291PG See page 7 Tubes 20-pin TSSOP 0 to +70 ° C 291PGI Tubes 20-pin TSSOP -40 to +85 ° C 291PGLF Tubes 20-pin TSSOP 0 to +70 ° C 291PGILF Tubes 20-pin TSSOP -40 to +85 ° C 291G-XX 291G-XX Tubes 20-pin TSSOP 0 to +70 ° C 291GI-XX 291GIXX Tubes 20-pin TSSOP -40 to +85 ° C 291G-XXLF 291GXXL Tubes 20-pin TSSOP 0 to +70 ° C 291GI-XXLF 291GIXXL Tubes 20-pin TSSOP -40 to +85 ° C 291G-XXT 291G-XX Tape and Reel 20-pin TSSOP 0 to +70 ° C 291GI-XXT 291GIXX Tape and Reel 20-pin TSSOP -40 to +85 ° C 291G-XXLFT 291GXXL Tape and Reel 20-pin TSSOP 0 to +70 ° C 291GI-XXLFT 291GIXXL Tape and Reel 20-pin TSSOP -40 to +85 ° C

© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-4522 www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com ICS291 TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER