HM-65162 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • TTL Compatible Inputs and Outputs
  • JEDEC Approved Pinout (2716, 6116 Type)
  • No Clocks or Strobes Required
  • Equal Cycle and Access Time
  • Single 5V Supply
  • Gated Inputs
  • No Pull-Up or Pull-Down Resistors Required

Description

The HM-65162 is a CMOS 2048 x 8 Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle time and ease of use. The pinout is the JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which allows easy memory board layouts flexible to accommodate a variety of industry standard PROMs, RAMs, ROMs and EPROMs. The HM-65162 is ideally suited for use in microprocessor based systems with its 8-bit word length organization. The conve- nient output enable also simplifies the bus interface by allow- ing the data outputs to be controlled independent of the chip enable. Gated inputs lower operating current and also elimi- nate the need for pull-up or pull-down resistors. Pinouts

Ordering Information

PACKAGE TEMP. RANGE 70ns/20 µA (NOTE 1) 90ns/40µA (NOTE 1) 90ns/300µA (NOTE 1) PKG. NO. CERDIP -40 oC to +85oC HM1-65162B-9 HM1-65162-9 HM1-65162C-9 F24.6 JAN# -55 oC to +125oC 29110BJA 29104BJA - F24.6 SMD# -55 oC to +125oC 8403606JA 8403602JA 8403603JA F24.6 CLCC -40 oC to +85oC HM4-65162B-9 HM4-65162-9 HM4-65162C-9 J32.A SMD# -55 oC to 125oC 8403606ZA 8403602ZA 8403603ZA J32.A NOTE: 1. Access time/data retention supply current. HM-65162 (CERDIP) TOP VIEW HM-65162 (CLCC) TOP VIEW VCC W G A10 DQ7 DQ5 DQ4 DQ3 E DQ6 DQ0 DQ1 DQ2 GND 3 2 14 32 31 30 16 17 18 19 2014 15 NC DQ0 DQ1 DQ2 GND NC DQ3 DQ4 DQ5 VCC NC NC NC NC NC NC G A10 E DQ7 DQ6 W PIN DESCRIPTION NC No Connect A0 - A10 Address Input E Chip Enable/Power Down VSS/GND Ground DQ0 - DQ7 Data In/Data Out VCC Power (+5V) W Write Enable G Output Enable FN3000.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved

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A A A0 A8 A9 A10 G A A COLUMN DECODER AND DATA INPUT / OUTPUT (X8) COLUMN ADDRESS BUFFER HM-65162

Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range HM-65162S-9, HM-65162B-9, Thermal Resistance θJA (oC/W) θJC (oC/W) oC to +150oC Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specific ation is not implied. SYMBOL PARAMETER LIMITS UNITS TEST CONDITIONSMIN MAX ICCSB1 Standby Supply Current - 50 µA HM-65162B-9, IO = 0mA, E = VCC - 0.3V, VCC = 5.5V -1 0 0 µA HM-65162S-9, HM65162-9, IO = 0mA, E = VCC - 0.3V, VCC = 5.5V -9 0 0 µA HM-65162C-9, IO = 0mA, E = VCC - 0.3V, VCC = 5.5V ICCSB Standby Supply Current - 8 mA E = 2.2V, IO = 0mA, VCC = 5.5V ICCEN Enabled Supply Current - 70 mA E = 0.8V, IO = 0mA, VCC = 5.5V ICCOP Operating Supply Current (Note 1) - 70 mA E = 0.8V, IO = 0mA, f = 1MHz, VCC = 5.5V ICCDR Data Retention Supply Current - 20 µA HM-65162B-9, IO = 0mA, VCC = 2.0V, E = VCC - 0.3V -4 0 µA HM-65162S-9, HM-65162-9, IO = 0mA, VCC = 2.0V, E = VCC - 0.3V -3 0 0 µA HM-65162C-9, IO = 0mA, VCC = 2.0V, E = VCC - 0.3V VCCDR Data Retention Supply Voltage 2.0 - V II Input Leakage Current -1.0 +1.0 µAV I = V CC or GND, VCC = 5.5V IIOZ Input/Output Leakage Current -1.0 +1.0 µA VIO = V CC or GND, VCC = 5.5V VIL Input Low Voltage -0.3 0.8 V V CC = 4.5V VIH Input High Voltage 2.2 V CC +0.3 V V CC = 5.5V VOL Output Low Voltage - 0.4 V IO = 4.0mA, V CC = 4.5V VOH1 Output High Voltage 2.4 - V IO = -1.0mA, V CC = 4.5V VOH2 Output High Voltage (Note 2) V CC -0.4 - V IO = -100 µA, VCC = 4.5V Capacitance TA = +25oC SYMBOL PARAMETER MAX UNITS TEST CONDITIONS CI Input Capacitance (Note 2) 10 pF f = 1MHz, All measurements are referenced to device GNDCIO Input/Output Capacitance (Note 2) 12 pF NOTES: 1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes. HM-65162

HM-65162S-9 HM-65162B-9 HM-65162-9 HM-65162C-9 MIN MAX MIN MAX MIN MAX MIN MAX READ CYCLE (1) TAVAX Read Cycle Time 55 - 70 - 90 - 90 - ns (Notes 1, 3) (2) TAVQV Address Access Time - 55 - 70 - 90 - 90 ns (Notes 1, 3, 4) (3) TELQV Chip Enable Access Time - 55 - 70 - 90 - 90 ns (Notes 1, 3) (4) TELQX Chip Enable Output Enable Time 5-5-5-5-n s (Notes 2, 3) (5) TGLQV Output Enable Access Time - 35 - 50 - 65 - 65 ns (Notes 1, 3) (6) TGLQX Output Enable Output Enable Time 5-5-5-5-n s (Notes 2, 3) (7) TEHQZ Chip Enable Output Disable Time - 35 - 35 - 50 - 50 ns (Notes 2, 3) (8) TGHQZ Output Enable Output Disable Time - 30 - 35 - 40 - 40 ns (Notes 2, 3) (9) TAVQX Output Hold From Address Change 5-5-5-5-n s (Notes 1, 3) WRITE CYCLE (10) TAVAX Write Cycle Time 55 - 70 - 90 - 90 - ns (Notes 1, 3) (11) TELWH Chip Selection to End of Write 45 - 45 - 55 - 55 - ns (Notes 1, 3) (12) TAVWL Address Setup Time 5 - 10 - 10 - 10 - ns (Notes 1, 3) (13) TWLWH Write Enable Pulse Width 40 - 40 - 55 - 55 - ns (Notes 1, 3) (14) TWHAX Write Enable Read Setup Time 10 - 10 - 10 - 10 - ns (Notes 1, 3) (15) TGHQZ Output Enable Output Disable Time - 30 - 35 - 40 - 40 ns (Notes 2, 3) (16) TWLQZ Write Enable Output Disable Time - 30 - 40 - 50 - 50 ns (Notes 2, 3) (17) TDVWH Data Setup Time 25 - 30 - 30 - 30 - ns (Notes 1, 3) (18) TWHDX Data Hold Time 10 - 10 - 15 - 15 - ns (Notes 1, 3) (19) TWHQX Write Enable Output Enable Time 0-0-0-0-n s (Notes 1, 3) (20) TWLEH Write Enable Pulse Setup Time 45 - 40 - 55 - 55 - ns (Notes 1, 3) (21) TDVEH Chip Enable Data Setup Time 25 - 30 - 30 - 30 - ns (Notes 1, 3) (22) TAVWH Address Valid to End of Write 45 - 50 - 65 - 65 - ns (Notes 1, 3) NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent and CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. V CC = 4.5 and 5.5V. 4. TAVQV = TELQV + TAVEL. HM-65162

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FIGURE 5. TYPICAL ICCDR vs T A