MX28F4100 MCNIX | Alldatasheet
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Technical content
WIA. MxX28F4100 4M-BIT (512K x 8) CMOS FLASH MEMORY
FEATURES
+ 524,288x8/262,144x16 switchable * Auto Erase (chip & block) and Auto Program + Fast access time: 120/150/200ns = DATA polling + Low power consumption — Toggle bit - 50mA maximum active current * 10,000 minimum erase/program cycles = 100pAmaximum standby current * Latch-up protected to 100mA from -1 to VCC+1V * Programming and erasing voltage 12V + 5% * Advanced CMOS Flash memory technology * Command register architecture + Package type: — Byte/Word Programming (50us typical) - 44-pin SOP ~ Chip Erase (1 sec typical) — 48-pin TSOP (Type 1) — Auto chip erase 30 sec typical (including preprogramming time) — Block Erase (16384 bytes by 32 blocks or 8,912 words by 32 blocks) GENERAL DESCRIPTION ‘The MX28F4100 is a 4-mega bit Flash memory organ- ized as 512K bytes of 8 bits or 256K words of 16 bits The highest degree of latch-up protection is achieved switchable. MXIC's Flash memories offer the most with MXIC's proprietary non-epi process. Latch-up cost-effective and reliable read/write non-volatile ran- protection is proved for stresses up to 100 milliamps dom access memory. The MX28F4100 is packaged on address and data pin from -1V to VCC + 1V. in 44-pin SOP and 48-pin TSOP(\\). It is designed to rz be reprogrammed and erased in-system or in-stand- GS ard EPROM programmers. 2 The standard MX28F4100 offers access times as fast as 120ns, allowing operation of high-speed micropro- cessors without wait states. To eliminate bus conten- tion, the MX28F4100 has separate chip enable (CE) and output enable (OE ) controls. MXIC's Flash memories augment EPROM functional- ity with in-circuit electrical erasure and programming. The MX28F4100 uses a command register to manage this functionality. The command register allows for 100% TTL level contro! inputs and fixed power supply levels during erase and programming, while maintain- ing maximum EPROM compatibility. MXIC Flash technology reliably stores memory con- tents even after 10,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combina- tion of advanced tunnel oxide processing and low internal electric fields for erase and programming op- erations produces reliable cycling. The MX28F4100 uses a 12.0V + 5% VPP supply to perform the High Reliability Erase and auto Program/Erase algorithms. oN PMs as REV. 10.MAR 24, 1994 36-1
WEA. MACROMOL Bic MX28F4100 Oe PIN CONFIGURATIONS
44 SOP TSOP (TYPE 1)
ver CTO 4p NC aye ct 48 [=> GND neces fh we ome =] 2 CO) 2 E a a qs aip es ats 3 46 = a1gat argl4 41/5 Ao AMS 4 45 a7 wis 40 | ATO AIS 8 44 > a4 adie ib at nels 43 = a6. ma? 38 | are ANY 7 42 5 13 adie a [p aa aio =| 8 aE os eqeg Spe “BSS, Siel aici F as|p as wai a7 5 vee wen Bw fb ae NG cy 12 MX28F4100 33 voc ce 33 p evTE vPP cj 13 6 NC eno G] 13 82 |P GND NC Cy 14 35 | ant ced F baw: Ao tts 34 © a3. oo ]1s a Por a7 =| 16 23 5 Gio oi = 2p om ns] 7 32 [> ag aii 2a |b 06 a5 Sj 18 31 2 G9 a@G 27 Pars Mel 0 so ot aj ap ag =] 20 2 | oe aro Fy) 20 aie oe AY oy 2 27 OE oe Fy 2 24 Oe ao | 29 26 F= eno an pp wee ce S| 4 25 = Gno (NORMAL TYPE) ono TEs ave Sno =| «7 2p aie ou shar Os | 43 saa ose 2 7a ‘as 41 [ato wes 1058 vac 7 11 we vee S| 38 MX28F4100 12, 5Ne Gal 3 laa a0] 33 16 f> a7 =— 17 boas Saat 1PoAs =r 19a Se a 20f 5 a3 Go 2 aa a2 OES 27 22, at GNO Sj 26 236-40 GND 25 240 CE (REVERSE TYPE) PIN DESCRIPTION: SYMBOL PIN NAME AI-A17____Address Input _ 0-015 Data Input/Output cE Chip Enable Input WE Write Enable Input BYTE Byte Input OE ‘Output Enable Input VPP Program Supply Voltage vec Power Supply Pin (+5V) GND Ground Pin ee