28C64AT-15ISO

28C64A MICROCHIP | Alldatasheet

Document overview

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Technical content

Ó 1996 Microchip Technology Inc. DS11109H-page 1

FEATURES

• Fast Read Access Time—150 ns
• CMOS Technology for Low Power Dissipation - 30 mA Active - 100 m A Standby
• Fast Byte Write Time—200 m s or 1 ms
• Data Retention >200 years
• High Endurance - Minimum 100,000 Erase/Write Cycles
• Automatic Write Operation - Internal Control Timer - Auto-Clear Before Write Operation - On-Chip Address and Data Latches
• Data Polling
• Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection CC Detector - Pulse Filter - Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
• Organized 8Kx8 JEDEC Standard Pinout - 28-pin Dual-In-Line Package - 32-pin PLCC Package - 28-pin Thin Small Outline Package (TSOP) 8x20mm - 28-pin Very Small Outline Package (VSOP) 8x13.4mm
• Available for Extended Temperature Ranges: - Commercial: 0˚C to +70˚C

DESCRIPTION

The Microchip Technology Inc. 28C64A is a CMOS 64K non- volatile electrically Erasable PROM. The 28C64A is accessed like a static RAM for the read or write cycles without the need of external components. During a “byte write”, the address and data are latched internally, freeing the micropro- cessor address and data bus for other operations. Following the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. To determine when the write cycle is complete, the user has a choice of monitoring the Ready/ Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in wired- or systems. Alternatively, Data polling allows the user to read the location last written to when the write operation is com- plete. CMOS design and processing enables this part to be used in systems where reduced power consumption and reli- ability are required. A complete family of packages is offered to provide the utmost flexibility in applications PACKAGE TYPES BLOCK DIAGRAM A10 CE V SS I/O2 OE A11 RDY/BSY A12 NC WE V CC I/O7 I/O6 I/O5 I/O4 I/O3 I/O1 I/O0 OE A11 NC WE Vcc RDY/BSY A12 A10 CE I/07 I/06 I/05 I/04 I/03 Vss I/02 I/01 I/00

• Pin 1 indicator on PLCC on top of package
• 1 RDY/BSY A12 I/O0 I/O1 I/O2 V Vcc WE NC A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 SS NC I/O0 A11 NC OE A10 CE I/O7 I/O6 A12 RDY/BSY NU Vcc WE NC I/O1 I/O2 Vss NU I/O3 I/O4 I/O5 DIP/SOIC PLCC TSOPVSOP I/O0 I/O7 Input/Output Buffers Chip Enable/ Output Enable Control Logic CE OE Data Protection Circuitry A12 Y Gating 16K bit Cell Matrix X Decoder Y Decoder Data Poll Auto Erase/Write Timing VCC VSS WE L a t c h e s Program Voltage Generation Rdy/ Busy 28C64A 64K (8K x 8) CMOS EEPROM This document was created with FrameMaker404

Ó 1996 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 MAXIMUM RA TINGS*

V CC and input voltages w.r.t. V SS Voltage on OE w.r.t. V SS Voltage on A9 w.r.t. V SS Output Voltage w.r.t. V SS CC +0.6V *Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating con- ditions for extended periods may affect device reliability. TABLE 1-1: PIN FUNCTION TABLE Name Function A0 - A12 Address Inputs CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs RDY/Busy Ready/Busy V CC +5V Power Supply V SS Ground NC No Connect; No Internal Connection NU Not Used; No External Connection is Allowed TABLE 1-2: READ/WRITE OPERATION DC CHARACTERISTIC V CC = +5V 10% Commercial (C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Parameter Status Symbol Min Max Units Conditions Input Voltages Logic ‘1’ Logic ‘0’ V IH V IL 2.0 -0.1 Vcc+1 0.8 V V Input Leakage — I LI -10 10 m AV IN = -0.1V to Vcc +1 Input Capacitance — C IN —1 0p F V IN = 0V; Tamb = 25˚C; f = 1 MHz (Note 2) Output Voltages Logic ‘1’ Logic ‘0’ V OH V OL 2.4 0.45 V V I OH = -400 m A I OL = 2.1 mA Output Leakage — I LO -10 10 m AV OUT = -0.1V to Vcc +0.1V Output Capacitance — C OUT —1 2p F V IN = 0V; Tamb = 25˚C; f = 1 MHz (Note 2) Power Supply Current, Active TTL input I CC — 30 mA f = 5 MHz (Note 1) V CC = 5.5V Power Supply Current, Standby TTL input TTL input CMOS input I CC S TTL I CC S TTL I CC S CMOS 100 mA mA m A CE = V IH (0˚C to +70˚C) CE = V IH (-40˚C to +85˚C) CE = V CC -0.3 to Vcc +1 Note 1: AC power supply current above 5MHz: 2mA/MHz. 2: Not 100% tested.

Ó 1996 Microchip Technology Inc. DS11109H-page 3 28C64A TABLE 1-3: READ OPERATION AC CHARACTERISTICS FIGURE 1-1: READ WAVEFORMS AC Testing Waveform: V IH = 2.4V; V IL = 0.45V; V OH = 2.0V; V OL = 0.8V Output Load: 1 TTL Load + 100 pF Input Rise and Fall Times: 20 ns Ambient Temperature: Commercial (C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Parameter Symbol 28C64A -15 28C64A -20 28C64A -25 Units Conditions Min Max Min Max Min Max Address to Output Delay t ACC — 150 — 200 — 250 ns OE = CE = V IL CE to Output Delay t CE — 150 — 200 — 250 ns OE = V IL OE to Output Delay t OE —7 0—8 0— 1 0 0 n s C E = V IL CE or OE High to Output Float t OFF 05 005 50 7 0 n s (Note 1) Output Hold from Address, CE or OE, whichever occurs first. t OH 0—0—0 — n s (Note 1) Endurance — 1M — 1M — 1M — cycles 25 C, Vcc = 5.0V, Block Mode (Note 2) Note 1: Not 100% tested. 2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli- cation, please consult the Total Endurance Model which can be obtained on our BBS or website. Address CE VIH VIL VIH VIL VIH VIL OE Data WE VOH VOL VIH VIL Address Valid High Z Valid Output tACC (1) tOFF is specified for OE or CE, whichever occurs first (2) OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE (3) This parameter is sampled and is not 100% tested High Z tOH tOFF(1,3) Notes: tOE(2) tCE(2)

Ó 1996 Microchip Technology Inc. TABLE 1-4: BYTE WRITE AC CHARACTERISTICS FIGURE 1-2: PROGRAMMING WAVEFORMS AC Testing Waveform: V IH = 2.4V; V IL = 0.45V; V OH = 2.0V; V OL = 0.8V Output Load: 1 TTL Load + 100 pF Input Rise/Fall Times: 20 ns Ambient Temperature: Commercial (C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Parameter Symbol Min Max Units Remarks Address Set-Up Time t AS 10 — ns Address Hold Time t AH 50 — ns Data Set-Up Time t DS 50 — ns Data Hold Time t DH 10 — ns Write Pulse Width t WPL 100 — ns Note 1 Write Pulse High Time t WPH 50 — ns OE Hold Time t OEH 10 — ns OE Set-Up Time t OES 10 — ns Data Valid Time t DV — 1000 ns Note 2 Time to Device Busy t DB 25 0 n s Write Cycle Time (28C64A ) t WC — 1 ms 0.5 ms typical Write Cycle Time (28C64A F) t WC — 200 m s 100 m s typical Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the pos- itive edge WE, whichever occurs first. 2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until t DH after the positive edge of WE or CE, whichever occurs first. tAS tAH tWPL tDS tDH tOES tOEH tWC Address CE, WE Data In OE VIH VIL VIH VIL VIH VIL VIH VIL Rdy/Busy VOH VOL tDB tDV Busy Ready

DS11109H-page 6 Ó 1996 Microchip Technology Inc.

2.0 DEVICE OPERATION

The Microchip Technology Inc. 28C64A has four basic modes of operation—read, standby, write inhibit, and byte write—as outlined in the following table.

2.1 Read Mode

The 28C64A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip enable (CE ) is the power control and should be used for device selection. Output Enable (OE ) is the output control and is used to gate data to the output pins independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the output tOE after the fall- ing edge of OE, assuming that CE has been low and addresses have been stable for at least tACC -tOE .

2.2 Standb y Mode

The 28C64A is placed in the standby mode by applying a high signal to the CE input. When in the standby mode, the outputs are in a high impedance state, inde- pendent of the OE input.

2.3 Data Pr otection

In order to ensure data integrity, especially during criti- cal power-up and power-down transitions, the following enhanced data protection circuits are incorporated: First, an internal V CC detect (3.3 volts typical) will inhibit the initiation of non-volatile programming operation when V CC is less than the VCC detect circuit trip. Second, there is a WE filtering circuit that prevents WE pulses of less than 10 ns duration from initiating a write cycle. Third, holding WE or CE high or OE low, inhibits a write cycle during power-on and power-off (VCC ). Operation Mode CE OE WE I/O Rdy/Busy (1) Read L L H D OUT H Standby H X X High Z H Write Inhibit H X X High Z H Write Inhibit X L X High Z H Write Inhibit X X H High Z H Byte Write L H L D IN L Byte Clear Automatic Before Each “Write” Note 1: Open drain output. 2: X = Any TTL level.

2.4 Write Mode

The 28C64A has a write cycle similar to that of a Static RAM. The write cycle is completely self-timed and ini- tiated by a low going pulse on the WE pin. On the fall- ing edge of WE, the address information is latched. On rising edge, the data and the control pins (CE and OE) are latched. The Ready/Busy pin goes to a logic low level indicating that the 28C64A is in a write cycle which signals the microprocessor host that the system bus is free for other activity. When Ready/Busy goes back to a high, the 28C64A has completed writing and is ready to accept another cycle.

2.5 Data Polling

The 28C64A features Data polling to signal the comple- tion of a byte write cycle. During a write cycle, an attempted read of the last byte written results in the data complement of I/O7 (I/O0 to I/O6 are indetermin- able). After completion of the write cycle, true data is available. Data polling allows a simple read/compare operation to determine the status of the chip eliminat- ing the need for external hardware.

2.6 Electr onic Signature for Device

Identification An extra row of 32 bytes of EEPROM memory is avail- able to the user for device identification. By raising A9 to 12V –0.5V and using address locations 1FEO to 1FFF, the additional bytes can be written to or read from in the same manner as the regular memory array.

2.7 Chip Clear

All data may be cleared to 1's in a chip clear cycle by raising OE to 12 volts and bringing the WE and CE low. This procedure clears all data, except for the extra row.

Ó 1996 Microchip Technology Inc. DS11109H-page 7 28C64A Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. Package: L = Plastic Leaded Chip Carrier (PLCC) P = Plastic DIP (600 mil) SO = Plastic Small Outline IC (600 mil) TS = Thin Small Outline Package (TSOP) 8x20mm VS = Very Small Outline Package (VSOP) 8x13.4mm Temperature Blank = 0°C to +70°C Range: I = -40°C to +85°C Access Time: 15 150 ns 20 200 ns 25 250 ns Shipping: Blank Tube T Tape and Reel “L” and “SO” Option: Blank = twc = 1ms F = twc = 200 ms Device: 28C64A 8K x 8 CMOS EEPROM 28C64A FT–1 5I/ P

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