ISL28278_07 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Low power 120µA typical supply current (ISL28278)
  • 2 2 5μV max offset voltage
  • 30pA max input bias current
  • 300kHz typical gain-bandwidth product
  • 105dB typical PSRR
  • 100dB typical CMRR
  • Single supply operation down to 2.4V
  • Input is capable of swinging above V+ and below V- (ground sensing)
  • Rail-to-rail input and output (RRIO)
  • Enable Pin (ISL28278 only)
  • Pb-free plus anneal available (RoHS compliant)

Applications

  • Battery- or solar-powered systems
  • 4mA to 25mA current loops
  • Handheld consumer products
  • Medical devices
  • Thermocouple amplifiers
  • Photodiode pre-amps
  • pH probe amplifiers

Ordering Information

OUT_A IN-_A NC OUT_B IN-_B IN+_A IN+_B EN EN_B NC NC NC 8 9 OUT_A IN-_A IN+_A OUT_D IN-_D IN+_D IN+_B IN+_C IN-_B OUT_B IN-_C OUT_C NC NC PART NUMBER (Note) PART MARKING PACKAGE (Pb-Free) PKG. DWG. # ISL28278FAZ* 28278FAZ 16 Ld QSOP MDP0040 ISL28478FAZ* 28478FAZ 16 Ld QSOP MDP0040 *“-T7” suffix is for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet July 11, 2007 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN6145.2 July 11, 2007 Operating Junction Absolute Maximum Ratings (TA = +25°C) Thermal Information - 0.5V to V+ + 0.5V ESD Tolerance Thermal Resistance θJA (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. U nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C, temperature data established by characterization PARAMETER DESCRIPTION CONDITIONS MIN (Note 1) TYP MAX (Note 1) UNIT DC SPECIFICATIONS V OS Input Offset Voltage -225 -450 ±0.20 225 450 µV Input Offset Voltage vs Temperature 1.0 µV/°C IOS Input Offset Current -40°C to +85°C -30 -80 ±53 0 pA IB Input Bias Current -40°C to +85°C -30 -80 ±10 30 pA CMIR Common-Mode Voltage Range Guaranteed by CMRR 05 V CMRR Common-Mode Rejection Ratio V CM = 0V to 5V 80 100 dB PSRR Power Supply Rejection Ratio V+ = 2.4V to 5V 85 105 dB AVOL Large Signal Voltage Gain V O = 0.5V to 4.5V, RL = 100kΩ 200 190

300 V/mV

VO = 0.5V to 4.5V, RL = 1kΩ 60 V/mV VOUT Maximum Output Voltage Swing Output low, R L = 100kΩ 36 mV Output low, RL = 1kΩ 130 175 225 mV Output high, RL = 100kΩ 4.990 4.97 4.996 V Output high, RL = 1kΩ 4.800 4.750 4.880 V IS,ON Quiescent Supply Current, Enabled ISL28278, All channels enabled. 120 156 175 µA ISL28478, All channels enabled. 240 315 350 µA IS,OFF Quiescent Supply Current, Disabled All channels disabled. ISL28278 µA ΔVOS ISL28278, ISL28478

3 FN6145.2 July 11, 2007 IO+ Short Circuit Sourcing Capability R L = 10Ω 29 31 mA IO- Short Circuit Sinking Capability R L = 10Ω 24 26 mA VSUPPLY Supply Operating Range V - to V+ 2.4 5.0 V VENH EN Pin High Level ISL28278 2 V VENL EN Pin Low Level ISL28278 0.8 V IENH EN Pin Input High Current VEN = V+ ISL28278 0.8 1 1.5 µA IENL EN Pin Input Low Current VEN = V- ISL28278 0 0.1 µA AC SPECIFICATIONS GBW Gain Bandwidth Product A V = 100, RF = 100kΩ, RG = 1kΩ, RL = 10kΩ to VCM 300 kHz en Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz 4.5 µV P-P Input Noise Voltage Density f O = 1kHz 45 nV /√Hz in Input Noise Current Density f O = 1kHz 0.04 pA/ √Hz CMRR @ 60Hz Input Common Mode Rejection Ratio V CM = 1VP-P, RL = 10kΩ to VCM -70 dB PSRR+ @ 120Hz Power Supply Rejection Ratio, +V V+,V- = ±1.2V and ±2.5V, VSOURCE = 1VP-P, RL = 10kΩ to VCM -80 dB PSRR- @ 120Hz Power Supply Rejection Ratio, -V V+,V- = ±1.2V and ±2.5V VSOURCE = 1VP-P, RL = 10kΩ to VCM -60 dB TRANSIENT RESPONSE SR Slew Rate ±0.12 ±0.09 ±0.14 ±0.16 ±0.21 V/µs tEN Enable to Output Turn-on Delay Time, 10% EN to 10% Vout VEN = 5V to 0V, AV = -1, RG = RF = RL = 1k to VCM, ISL28278 2µ s Enable to Output Turn-off Delay Time, 10% EN to 10% Vout VEN = 0V to 5V, AV = -1, RG = RF = RL = 1k to VCM, ISL28278 0.1 µs NOTE: 1. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested. Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C, temperature data established by characterization (Continued) PARAMETER DESCRIPTION CONDITIONS MIN (Note 1) TYP MAX (Note 1) UNIT ISL28278, ISL28478

10 FN6145.2 July 11, 2007 Applications Information Introduction The ISL28278 and ISL28478 are dual and quad CMOS rail-to-rail input, output (RRIO) micropower operational amplifiers. These devices are designed to operate from a single supply (2.4V to 5.0V) or dual supplies (±1.2V to ±2.5V) while drawing only 120μA (ISL28278) of supply current. This combination of low power and precision performance makes these devices suitable for solar and battery power applications. Rail-to-Rail Input Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The ISL28278 achieves input rail-to-rail without sacrificing important precision specifications and degrading distortion performance. The devices’ input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current versus the common-mode voltage range gives us an undistorted behavior from typically 100mV below the negative rail and 10% higher than the V rail (0.5V higher than V+ when V+ equals 5V). Input Protection All input terminals have internal ESD protection diodes to the positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. There is an additional pair of back-to-back diodes across the input terminals. For applications where the input differential voltage is expected to exceed 0.5V, external series resistors must be used to ensure the input currents never exceed 5mA. Pin Descriptions ISL28278 (16 LD QSOP) ISL28478 (16 LD QSOP) PIN NAME EQUIVALENT CIRCUIT DESCRIPTION 3 1 OUT_A Circuit 3 Amplifier A output 4 2 IN-_A Circuit 1 Amplifier A inverting input 5 3 IN+_A Circuit 1 Amplifier A non-inverting input 15 4 V+ Circuit 4 Positive power supply 12 5 IN+_B Circuit 1 Amplifier B non-inverting input 13 6 IN-_B Circuit 1 Amplifier B inverting input 14 7 OUT_B Circuit 3 Amplifier B output 1, 2, 8, 9, 10, 16 8, 9 NC No internal connection

10 OUT_C Circuit 3 Amplifier C output

11 IN-_C Circuit 1 Amplifier C inverting input

12 IN+_C Circuit 1 Amplifier B non-inverting input

7 13 V- Circuit 4 Negative power supply

14 IN+_D Circuit 1 Amplifier D non-inverting input

15 IN-_D Circuit 1 Amplifier D inverting input

16 OUT_D Circuit 3 Amplifier D output

_A Circuit 2 Amplifier A enable pin internal pul l-down; Logic “1” selects the disabled state; Logic “0” selects the enabled state.

11 EN _B Circuit 2 Amplifier B enable pin with inter nal pull-down; Logic “1” selects the disabled

state; Logic “0” selects the enabled state. IN- LOGIC PIN OUT CIRCUIT 3CIRCUIT 1 CIRCUIT 2 IN+ CAPACITIVELY COUPLED ESD CLAMPCIRCUIT 4 ISL28278, ISL28478

12 FN6145.2 July 11, 2007 where:

  • P DMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX)
  • P D MAX for each amplifier is calculated in Equation 2: where:
  • T MAX = Maximum ambient temperature
  • θJA = Thermal resistance of the package
  • P D MAX = Maximum power dissipation of 1 amplifier
  • V S = Supply voltage (Magnitude of V+ and V-)
  • I MAX = Maximum supply current of 1 amplifier
  • V OUTMAX = Maximum output voltage swing of the application
  • R L = Load resistance PDMAX 2*V S ISMAX VS( - VOUTMAX ) VOUTMAX RL (EQ. 2) ISL28278, ISL28478

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6145.2 July 11, 2007 ISL28278, ISL28478 Quarter Size Outline Plastic Packages Family (QSOP)

0.010 C A B

1 (N/2) (N/2)+1N PIN #1 I.D. MARK b 0.004 C c A SEE DETAIL "X" 4°±4° GAUGE PLANE 0.010 LA1 D B H C e A

0.007 C A B

QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY SYMBOL INCHES TOLERANCE NOTESQSOP16 QSOP24 QSOP28 A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference - Rev. F 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994.