28236-BRF-001-A

28236-BRF-001-A MA-COM | Alldatasheet

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ATM OC-3 Service SAR Plus with xBR Traffic Management Mindspeed’s CN8236 Service Segmentation and Reassembly (ServiceSAR) controller integrates ATM terminal functions,PCI bus master and slave controllers, and a UTOPIA1 or 2 interface with service-specific func- tions in a single package for AAL0,AAL3/4,and AAL5 operations.The ServiceSAR controller generates and terminates ATM traffic (TM.4.1) and automatically schedules cells for transmission with patented xBR traffic management.The CN8236 is targeted at 155 Mbps throughput systems where the number ofVCCs is relatively large,or the performance ofthe overall system is critical.Examples ofsuch networking equipment include routers,Ethernet switches,ATM edge switches,or frame relay switches. Service-Specific Performance Accelerators The CN8236 incorporates numerous service-specific features designed to accelerate and enhance system performance.For example,the CN8236 implements echo suppression ofLAN traffic via LECID filtering, and supports frame relay DE to CLP interworking. Advanced xBR Traffic Management The xBR traffic manager in the CN8236 supports multiple ATM service categories.These include CBR,VBR (both single and dual leaky bucket),UBR,GFR (guaranteed frame rate),and ABR (explicit rate,relative rate and EFCI marking).The CN8236 manages each VCC independently. It dynamically schedules segmentation traffic to comply with up to 16+CBR user-configured scheduling priorities for the various traffic classes.Scheduling is controlled by a schedule table configured by the user and based on a user-specified time reference.ABR channels are managed in hardware according to user-programmable ABR templates.These templates tune the performance ofthe CN8236’s ABR algorithms to a specific system’s or network’s requirements. > AAL0,AAL3/4,AAL5,inter- working function for AAL1/2 scheduling (cell-on-demand scheduling) > ATM TM 4.1 service cate- gories: ABR,CBR,GFR,VBR- rt,VBR-nrt,GFR > Service-specific performance accelerators–LECD filtering and echo suppression, CLP0+1,Frame Relay DE interworking > Dynamic per-VCC scheduling > Flexible tunneling with mixed service categories (16 priorities) > Multi-peer architecture with up to 32 peers > Head-of-line blocking protec- tion for multi-PHYoperation > 64 K VCC,155 Mbps full duplex with 2-cell PDU > UTOPIALevel 2,8/16 bit @ 50 MHz > 33 MHz (up to 40 MHz),PCI 2.1 > 388 BGA,low-power dissipation > KEY FEATURES OC-3 ATM SAR Controller with UTOPIALevel 2 CN8236

Multi-Queue Segmentation Processing The CN8236’s segmentation coprocessor generates ATM cells for up to 64 K VCCs.The segmentation coprocessor formats cells on each channel according to segmentation VCC tables, utilizing up to 32 independent transmit queuesand reporting segmentation status on a parallel set of up to 32 segmentation status queues.The segmentation coprocessor fetches client data from the host,formats ATM cells while generating and appending protocol overhead,and forwards these to the UTOPIA port.The segmentation coprocessor operates as a slave to the xBR traffic manager which schedules VCCs for transmission. Multi-Queue Reassembly Processing The CN8236’s reassembly coprocessor stores the payload data from the cell stream received by the UTOPIAport into host data buffers.Using a dynamic lookup method which supports NNI or UNI addressing,the reassembly coprocessor processes up to 64K VCCs simultaneously.The host supplies free buffers on up to 32 independent free buffer queues.The reassembly coprocessor performs all CPCS protocol checks and reports the results ofthese checks and other status data on one of32 independent reassembly status queues. High-Performance Host Architecture with Buffer Isolation The CN8236 host interface architecture maximizes perform- ance and system flexibility.The device’s control and status queues enable host/SAR communication via write operations alone.This “write-only architecture”lowers latency and PCI bus occupancy.Flexibility is achieved by supporting a scalable peer-to-peer architecture.Multiple host clients can be addressed by the segmentation and reassembly (SAR) as separate physical or logical PCI peers.Segmentation and reassembly data buffers on the host system are identified by buffer descriptors in SAR-shared (or host) memory,which contain pointers to buffers.The use ofbuffer descriptors in this way allows for isolation ofdata buffers from the mecha- nisms that handle buffer allocation and linking.This provides a layer ofindirection in buffer assignment and management that maximizes system architecture flexibility. OC-3 Service SAR Controller Multi-client PCI Bus Timer Counters Local Bus PCI Master/ Slave DMA Co- Proc'r Local Memory Interface Reassembly Coprocessor Segmentation Coprocessor CBR, VBR, ABR, UBR, GFRTraffic Manager Rx/Tx UTOPIA Master/ Slave Control/ StatusCN8236 CX28250 PHY Device Cell FIFO CN8236 functional block diagram

Mindspeed provides an evaluation environment for the CN8236 which provides a working reference design and facilities for generating and terminating all service categories ofATM traffic.This system accelerates ATM system development by providing a rapid prototyping environment. What is ATM? Asynchronous transfer mode (ATM) has emerged as the primary networking technology for next-generation,multiser- vice communication networks.ATM-enabled services benefit the Internet as well as emerging applications in science, telemedicine,and distance learning.Just as the Internet revo- lutionized worldwide communications,ATM brings new meaning to high-speed networking. ATM,which uses a fixed size packet,or cell,is a transport protocol capable ofproviding a homogeneous network for all traffic types,regardless ofwhether the application is to carry conventional telephony,entertainment video,or data traffic over LANs,MANs,or WANs. The ITU-Tand ANSI selected ATM for Broadband-ISDN. SONET/SDH,as specified by the ITU,is intended as the primary transport mechanism for ATM cells in WAN applica- tions.ATM also plays a key role in next-generation consumer applications for high-speed Internet access and wireless access.The ADSL Forum and the Universal ADSL Working Group chose ATM as the network layer protocol for G.lite and G.DMTADSL. ATM physical layer (ATM-PHY) IC devices adapt ATM cells to and from a broad range oftransmission rates ranging from 1.544 Mbps to 2.4 Gbps via a standard system interface called UTOPIA. CN8236

www.mindspeed.com/salesoffices General Information: (949) 579-3000 Headquarters –Newport Beach 4000 MacArthur Blvd.,East Tower Newport Beach,CA 92660-3007 8236-BRF-001-A M01-0590 © 2003 Mindspeed Technologies™. All rights reserved. Mindspeed and the Mindspeed logo are trademarks ofMindspeed Technologies.All other trademarks are the property oftheir respective owners.Although Mindspeed Technologies strives for accuracy in all its publications,this material may contain errors or omissions and is subject to change without notice. This material is provided as is and without any express or implied warranties, including merchantability, fitness for a particular purpose and non- infringement.Mindspeed Technologies shall not be liable for any special, indirect, inci- dental or consequential damages as a result ofits use. Service-Specific Performance Accelerators

• LECID filtering and echo suppression
• Dual leaky bucket based on CLP (frame relay)
• Frame relay DE interworking
• Internal SNMP MIB counters
• IP over ATM; supports both CLP0+1 and ABR shaping Flexible Architectures
• Multi-peer host
• Direct switch attachment via reverse UTOPIA
• ATM terminal –Host control –Local bus control
• Optional local processor New

Features

• 3.3 V,388 BGAlowers power and eases PCB assembly (0.75 W max)
• AAL3/4 CPCS generation and checking
• PCI 2.1,including support for serial EEPROM
• Enhancements to xBR Traffic Manager –Fewer ABR templates –Improved CBR tunneling
• Reduced memory size for VCC lookup tables
• Increased addressing flexibility
• Additional byte lane swappers for increased system flexibility
• UTOPIALevel 2,8/16 bit 50 MHz
• Programmable size routing tags for up to 64 byte cells
• Selectable single/separate UTOPIAclocks
• Interworking function for all AAL1/2 scheduling –Cell-on-demand scheduling
• Updated PM-OAM processing per i.610
• SECBC calculated per GR-1248
• Paging function in order to gluelessly control RS8228 cell delineator
• Robust EEPROM operation (SAR provides power)
• Compact PCI Hot Swap capabilities
• Master PCI write over read arbitration control
• Increase incoming DMAFIFO buffer from 2 KB to 8 KB
• Prepended VCC index on RSM BOM cells
• Optional reference clock drive scheduler
• Head ofline blocking protection for multi-PHYoperation xBR Traffic Management
• TM4.1 Service Classes –CBR –VBR (single,dual and CLP-based leaky buckets) –Real-time VBR –ABR (explicit rate,relative rate and EFCI marking) –UBR –GFC (controlled and uncontrolled flows) –Guaranteed Frame Rate (GFR) (guaranteed MCR on UBR VCCs)
• 16 levels ofpriorities (16 + CBR)
• Dynamic per-VCC scheduling
• Multiple programmable ABR templates (supplied by Mindspeed or user)
• Scheduler driven by selectable clock –Local system clock –External reference clock
• Internal RM OAM cell feedback path
• Virtual FIFO buffer rate matching (Source Rate Matching)
• Per-VCC MCR and ICR
• Tunneling –VP tunnels (VCI interleaving on PDU boundaries) –CBR tunnels (cells interleaved as UBR,VBR or ABR with an aggregate CBR limit)
• 155 Mbps full-duplex (2-cell PDUs) Multi-Queue Segmentation Processing
• 32 transmit queues with optional priority levels
• 64 K VCCs maximum
• AAL5 and AAL3/4 CPCS generation
• AAL0 Null CPCS (optional use ofPTI for PDU demarcation)
• ATM cell header generation
• Raw cell mode (52 octet)
• 200 Mbps half-duplex
• 155 Mbps full-duplex (with 2-cell PDUs)
• Variable length transmit FIFO buffer –CDV-host latency matching (1 to 9 cells)
• Symmetric Tx and Rx architecture –Buffer descriptors –Queues
• User defined field circulates back to the host (32 bits)
• Distributed host or SAR-shared memory segmentation
• Simultaneous segmentation and reassembly
• Per-PDU control ofCLP/PTI (UBR)
• Per-PDU control ofAAL5 UU field
• Message and streaming status modes
• Virtual Tx FIFO buffer (PCI host) Multi-Queue Reassembly Processing
• 32 reassembly queues
• 64K VCCs maximum*
• AAL5 and AAL3/4 CPCS checking
• AAL0 –PTI termination –Cell count termination
• Early Packet Discard,based on: –Receive buffer underflow –Receive status overflow –CLP with priority threshold –AAL5 max PDU length –Rx FIFO buffer full –Frame relay DE with priority threshold –LECID filtering and echo suppression –Per-VCC firewalls
• Dynamic channel lookup (NNI or UNI addressing) –Supports full address space –Deterministic –Flexible VCI count per VPI –Optimized for signaling address assignment
• Message and streaming status modes
• Raw cell mode (52 octet)
• 200 Mbps halfduplex
• 155 Mbps full duplex (with 2-cell PDUs)
• Distributed host or SAR-shared memory reassembly
• 8 Programmable reassembly hard- ware time outs (per-VCC assignable)
• Global max PDU length for AAL5
• Per-VCC buffer firewall (memory usage limit)
• Simultaneous reassembly and segmentation
• Idle cell filtering High-Performance Host Architecture with Buffer Isolation
• Write-only control and status
• Read multiple command for data transfer
• Up to 32 host clients control and status queues
• Physical or logical clients –Enables peer-to-peer architecture
• Descriptor-based buffer chaining
• Scatter/gather DMA
• Endian neutral (allows data word and control word byte swapping,for both big and little endian systems)
• Non-word (byte) aligned host buffer addresses
• Automatically detects presence ofTx data or Rx free buffers
• Virtual FIFO buffers (PCI bursts treated as a single address)
• Hardware indication ofBOM
• Allows isolation ofsystem resources
• Status queue interrupt delay Designer Toolkit
• Evaluation hardware
• Reference schematics
• Generous Implementation ofOAM- PM Protocols
• Detection ofall F4/F5 OAM flows
• Internal PM monitoring and generation for up to 128 VCCs
• Optional global OAM Rx/Tx queues
• In-line OAM insertion and generation Standards-Based I/O
• 33 MHz PCI 2.1 (to 40 MHz)
• Serial EEPROM to store PCI configuration information
• PHYinterfaces –UTOPIAmaster (Level 1) –UTOPIAslave (Level 1) –UTOPIAmaster (Level 2) –UTOPIAslave (Level 2)
• Flexible SAR-shared memory architecture
• Optional local control interface
• Boundary scan for board- level testing
• Source loopback,for diagnostics
• Glueless connection to Mindspeed’s ATM physical layer device,the CX28250 and CN8223 Standards Compliance
• UNI/NNI 3.1
• TM 4.0 / TM 4.1 compliant
• Bellcore GR-1248
• ATM Forum B-ICI V2.0

Ordering Information

Model number: CN8236EBGB Manufacturing part number: 28236-12P Product revision: B Package: 388-pin BGA Operating temperature: -40°C to 85ºC Product Features