APD-256G064A_V01 VISHAY | Alldatasheet

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www.vishay.com APD-256G064A Vishay Dale Document Number: 37073 Revision 09-Dec-03 For Technical Questions, Contact: Displays@vishay.com Plasma Panel Display Module 256 x 64 Graphics Display with Drive Electronics, + 5V CMOS Level Video Interface and Integrated DC Converter

FEATURES

  • + 5V CMOS level video interface (with 4.7k pull-up resistors)
  • On board DC converter
  • Slim Profile
  • Large, bright characters and graphics
  • Highly visible for long distance viewing ELECTRICAL SPECIFICATIONS Voltages Required: VDC: + 12 to + 24VDC Vcc: + 5VDC Power Required: Typical = 20 watts, Maximum = 65 watts OPTICAL SPECIFICATIONS Viewing Area: 15.85” W x 5.00” H Pixel Pitch: 0.062” Pixel Size: 0.038” diameter Color: Neon orange Text with typical 5x7 character matrix using 1 column between characters and 1 row between lines. Maximum Number of Characters per Line: 42 Maximum Number of Lines: 16 Luminance: 40 foot lamberts minimum ENVIRONMENTAL SPECIFICATIONS Operating Temperature: 0°C to + 70°C Storage Temperature: - 20°C to + 85°C Relative Operating Humidity: To 95% non-condensing Mechanical Shock: 30G Vibration: 3G Operating Altitude: 10,000 feet The APD-256G064A has been designed to offer high brightness and superior viewing aesthetics in a package that is very affordable. This display is ideal for low to medium level information content messages and would be ideal for applications such as arcade games, process control, POS terminals, medical equipment, message centers and ATM machines. The APD-256G064A DC Plasma display offers viewing qualities designers seek such as high contrast, viewing angle of 150 ° minimum, and long distance readability. It is bright (40 foot lamberts minimum) with characters and graphics figures presented in a pleasing neon orange color against a black background. Plasma is much more readable and eye-pleasing than liquid crystal or vacuum fluorescent displays and is filterable to red, amber, or neutral density. These plasma display panels are driven in a standard row - column refresh method much like a CRT display. The designer need only supply + 5V CMOS level signals for SERIAL DATA, DOT CLOCK, COLUMN LATCH, ROW DATA, ROW CLOCK and DISPLAY ENABLE. The SERIAL DATA is entered with the DOT CLOCK up to frequencies as high as 8mHz. After a row of 256 pixels is clocked in, the COLUMN LATCH signal is toggled and the data is latched. At the time the data is latched, the display is briefly disabled using the DISPLAY ENABLE signal, then the row pointer is advanced with the ROW CLOCK signal. Once each frame the ROW DATA must be asserted to synchronize the column serial data with the beginning row. The recommended scanning frequency is approximately 70Hz but may be as high as 200Hz. The high clock rate on the data clock allows for rapid refresh and maximum access time to the refresh ram. *Recommended operating voltages. All maximums are absolute maximum. STANDARD ELECTRICAL SPECIFICATIONS*

DESCRIPTION

power @ + 12V Logic 1 Input Logic 0 Input SYMBOL Vcc Icc VDC IDC Vih Vil MIN. + 4.5 + 10 Screen Clear 0.13 2/3Vcc TYP. + 5.0 + 50.0 + 24.0 50% Lit 2.7 MAX. + 5.5 + 200 + 28.0 100% Lit 5.5 1/3Vcc UNITS VDC mADC VDC ADC VDC VDC

Document Number: 37073 Revision 09-Dec-03 www.vishay.com APD-256G064A Vishay Dale For Technical Questions, Contact: Displays@vishay.com DIMENSIONS in inches [millimeters] 10.511

12.236 PIN 1

18.112 8.906 8.906 0.150 DIA (6) 16.95 15.848 0.420 0.426 4.9953.9445.6865.986 0.551 0.150 0.581

256 X 64 FULL FIELD

0.038 DIAMETER PIXEL

0.062 PIXEL PITCH

1.10 MAX

0.425 MAX

0.062 PCB

0.150 AMP #640445-5 or equivalent.(Mates with AMP 640428-5, MOLEX 09-05-3051 or equivalent.) PIN DESCRIPTION P3, POWER CONNECTOR PIN SIGNAL DESCRIPTION

1 GND GROUND

2 VDC DC Converter Supply

4 KEY Used to key connector

5 GND GROUND

P2, DATA CONNECTOR PIN DESCRIPTION PIN DESCRIPTION

1 DISPLAY ENABLE 2 GROUND

3 ROW DATA 4 GROUND

5 ROW CLOCK 6 GROUND

7 COLUMN LATCH 8 GROUND

9 DOT CLOCK 10 GROUND

11 SERIAL DATA 12 GROUND

13 No connect 14 GROUND

AMP #103309-2 or equivalent. (Mates with AMP 746195-2, MOLEX 39-27-1146 or equivalent.)

www.vishay.com APD-256G064A Vishay Dale Document Number: 37073 Revision 09-Dec-03 For Technical Questions, Contact: Displays@vishay.com DESCRIPTION OF INPUT SIGNALS DOT CLOCK - This signal enters the SERIAL DATA on each low to high transition. A total of 256 DOT CLOCK transitions must be present for each line of column/anode data. SERIAL DATA - This signal presents the pixel data in positive logic format. A logic one represents a lit pixel and a logic zero represents an extinguished pixel. Data is entered from right to left. The first pixel data entered will represent the leftmost pixel in the row. COLUMN LATCH - This signal latches the pixel data into the driver outputs. When the COLUMN LATCH signal goes to logic one the data entered previously will fall through to the driver outputs. When the signal returns to a logic zero, the data is latched and the shift register is now ready to accept the next row of data. Must be held low while entering new SERIAL DATA. DISPLAY ENABLE - This signal enables the output drivers. Using a duty cycle control, this signal may also be used for intensity control. The DISPLAY ENABLE must be at logic zero before the COLUMN LATCH signal transitions. To avoid display blurring, the ROW CLOCK signal should also transition while DISPLAY ENABLE is a logic zero. It is recommended that this signal remain low for 10 µS min. ROW DATA - This signal is the first line marker for the scan. This input should be held high to correspond to the first row of pixel data. ROW CLOCK - This signal clocks ROW DATA on the falling edge. The ROW CLOCK signal is repetitive and must be present for proper scanning of the display module. The APD-256G064A has a unique input protection circuit that assures the column drivers stay blanked on power up. The protection circuit unblanks the column drivers when the ROW CLOCK signal begins (i.e. the display begins scanning).

ORDERING INFORMATION

1st Bit of Row Will Appear in Leftmost Column 0 1 2 254 255 Row Data Row Clock Display Enable Row Clock Column Latch PARAMETER MINIMUM 100 TYPICAL MAXIMUM 200 UNITS nS uS uS Hz nS nS nS 16362210 63622100 1 t7t6 Positive Edge x 256

Document Number: 91000 www.vishay.com Revision: 18-Jul-08 1 Disclaimer Legal Disclaimer Notice Vishay All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all li ability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permit ted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners.