27LV002CB-70

MX29LV002CT MCNIX | Alldatasheet

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Technical content

P/N:PM1204 REV. 1.0, JUN. 30, 2005 2M-BIT [256K x 8] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY

• Ready/Busy# pin (RY/BY#) - Provides a hardware method of detecting program or erase operation completion.  Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Temporary sector unprotect allows code changes in previously locked sectors  CFI (Common Flash Interface) compliant - Flash device parameters stored on the device and provide the host system to access  100,000 minimum erase/program cycles  Latch-up protected to 100mA from -1V to VCC+1V  Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector  Hardware RESET# pin (only for 29LV002C) - Resets internal state machine to read mode  Package type: - 32-pin TSOP (type 1) - 32-pin PLCC  20 years data retention

FEATURES

 Extended single - supply voltage range 2.7V to 3.6V  262,411 x 8  Single power supply operation - 3.0V only operation for read, erase and program operation  Fast access time: 70/90ns  Low power consumption - 20mA maximum active current - 0.2uA typical standby current  Command register architecture - Byte Programming (9us typical) - Sector Erase (Sector structure 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x1, and 64K-Byte x3)  Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically program and verify data at specified address  Erase suspend/Erase Resume - Suspends sector erase operation to read data from, or program data to, any sector that is not being erased, then resumes the erase.  Status Reply - Data# Polling & Toggle bit for detection of program and erase operation completion. GENERAL DESCRIPTION The MX29LV002C T/B is a 2-mega bit Flash memory organized as 256K bytes of 8 bits. MXIC's Flash memo- ries offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV002C T/B is packaged in 32-pin TSOP and 32-pin PLCC. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The standard MX29LV002C T/B offers access time as fast as 70ns, allowing operation of high-speed micropro- cessors without wait states. To eliminate bus conten- tion, the MX29LV002C T/B has separate chip enable (CE#) and output enable (OE#) controls. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV002C T/B uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maxi- mum EPROM compatibility. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy- cling. The MX29LV002C T/B uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V. MX29LV002C/002NC T/B

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 PIN CONFIGURATIONS SECTOR STRUCTURE

32 PLCC32 TSOP (TYPE 1)

A0~A17 Address Input Q0~Q7 Data Input/Output CE# Chip Enable Input WE# Write Enable Input RESET# Hardware Reset Pin/Sector Protect Unlock OE# Output Enable Input VCC Power Supply Pin (+3V) GND Ground Pin MX29LV002CT Sector Architecture

16 K-BYTE

8 K-BYTE

32 K-BYTE

(BOOT SECTOR)

64 K-BYTE

A17~A0 MX29LV002CB Sector Architecture 00000H (BOOT SECTOR) A17~A0 14 17 20 32 30 A14 A13 A11 OE# A10 CE# VSS A12 A15 A16 RESET# VCC WE# A17 MX29LV002C/ 002NC T/B NC on MX29LV002NC A11 A13 A14 A17 WE# VCC RESET# A16 A15 A12 OE# A10 CE# GND MX29LV002C/002NC T/B NC on MX29LV002NC

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 BLOCK DIAGRAM CONTROL INPUT LOGIC PROGRAM/ERASE HIGH VOLTAGE WRITE STATE MACHINE (WSM) STATE REGISTERFLASH ARRAY X-DECODER ADDRESS LATCH AND BUFFER Y -PASS GATE Y -DECODER ARRAY SOURCE HV COMMAND DATA DECODER COMMAND DATA LATCH I/O BUFFER PGM DATA HV PROGRAM DATA LATCH SENSE AMPLIFIER Q0-Q7 A0~A17 WE# OE# WP# RESET#

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 AUTOMATIC PROGRAMMING The MX29LV002C T/B is byte programmable using the Automatic Programming algorithm. The Automatic Pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV002C T/B is less than 10 seconds. AUTOMATIC CHIP ERASE The entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. Typical erasure at room temperature is accomplished in less than 4 second. The Automatic Erase algorithm au- tomatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device. AUTOMATIC SECTOR ERASE The MX29LV002C T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verifi- cation of electrical erase are controlled internally within the device. An erase operation can erase one sector, multiple sectors, or the entire device. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the pro- gram verification, and counts the number of sequences. The device provides an unlock bypass mode with faster programming. Only two write cycles are needed to pro- gram a byte, instead of four. A status bit similar to Data# Polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the sta- tus of the programming operation. Refer to write opera- tion status, table7, for more information on these status bits. AUTOMATIC ERASE ALGORITHM MXIC's Automatic Erase algorithm requires the user to write commands to the command register using stan- dard microprocessor write timings. The device will auto- matically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecu- tive read cycles provides feedback to the user as to the status of the erasing operation. Register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. During write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE# or CE#, whichever happens first. MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reli- ability, and cost effectiveness. The MX29LV002C T/B electrically erases all bits simultaneously using Fowler- Nordheim tunneling. The bytes are programmed by us- ing the EPROM programming mechanism of hot elec- tron injection. During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command regis- ter to respond to its full command set. AUTOMATIC SELECT The automatic select mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on Q7~Q0. This mode is mainly adapted for programming equipment on the de- vice to be programmed with its programming algorithm. When programming by high voltage method, automatic select mode requires VID (11.5V to 12.5V) on address pin A9 and other address pin A6, A1 as referring to Table 3. In addition, to access the automatic select codes in- system, the host can issue the automatic select com-

TABLE 3. MX29LV002C T/B AUTOSELECT MODE OPERATION NOTE: SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High. RESET# pin for 32-TSOP only.

TABLE 4. MX29LV002C T/B COMMAND DEFINITIONS

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A17=do

DDI = Data of Device identifier : C2H for manufacture code, 59H/5AH (Top/Bottom) for device code. RA=Address of memory location to be read. RD=Data to be read at location RA.

1. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA. SA = Address of the sector to be erased.

1. The system should generate the following address patterns: 555H or 2AAH to Address A11~A0.

Address (SA). Write Sequence may be initiated with A12~A18 in either state.

1. For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data

is 00H, it means the sector is still not being protected.

TABLE 5. MX29LV002C T/B BUS OPERATION

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 4 for valid Data-In during a write operation.
4. Code=00H means unprotected.
5. A18~A13=Sector address for sector protect.
6. The sector protect and chip unprotect functions may also be implemented via programming equipment.
7. RESET# pin for 32-TSOP package type only.

Sector Erase operation is in progress. dress and data sequences into the command register.

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCES To program data to the device or erase sectors of memory , the system must drive WE# and CE# to VIL, and OE# to VIH. An erase operation can erase one sector, multiple sectors , or the entire device. Table indicates the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence section for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODE When using both pins of CE# and RESET#, the device enter CMOS Standby with both pins held at Vcc ± 0.3V . The RESET# pin is provided only for 40-pin TSOP pack- age type. If CE# and RESET# are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (Icc2) is required even CE# = "H" until the operation is completed. The device can be read with standard ac- cess time (tCE) from either of these standby modes, before it is ready to read data. OUTPUT DISABLE With the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. RESET# OPERATION (for 32-TSOP package type) The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3V, the standby current will be greater. The RESET# pin may be tied to system reset circuitry. A system reset would that also reset the Flash memory, enabling the system to read the boot-up firm-ware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 operation is complete. If RESET# is asserted when a program or erase operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 24 for the timing diagram. READ/RESET COMMAND The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data. The de- vice remains enabled for reads until the command regis- ter contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid com- mand must then be written to place the device in the desired state. SILICON-ID READ COMMAND Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manu- facturer and device codes must be accessible while the device resides in the target system. PROM program- mers typically access signature codes by raising A9 to a high voltage (VID). However, multiplexing high voltage onto address lines is not generally desired system de- sign practice. The MX29LV002C T/B contains a Silicon-ID-Read op- eration to supple traditional PROM programming meth- odology. The operation is initiated by writing the read silicon ID command sequence into the command regis- ter. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 59H for MX29LV002CT, 5AH for MX29LV002CB. SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H or sector erase command 30H. The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Auto- matic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pat- tern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verification command is required). If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 7), indicating the erase operation ex- ceed internal timing limit. The automatic erase begins on the rising edge of the last WE# or CE# pulse, whichever happens first in the com- mand sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecu- tive read cycles, at which time the device returns to the Read mode.

TABLE 6. EXPANDED SILICON ID CODE reset commands until the operation is complete. ray data (also applies during Erase Suspend).

the time-out period resets the device to read mode. provide any control or timing during these operations. Table 7. Write Operation Status

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more information.

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 ERASE SUSPEND This command only has meaning while the state ma- chine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend com- mand is written during a sector erase operation, the de- vice requires a maximum of 20us to suspend the erase operations. However, When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After this command has been ex- ecuted, the command register will initiate erase suspend mode. The state machine will return to read mode auto- matically after suspend is ready. At this time, state ma- chine only allows the command register to respond to the Read Memory Array, Erase Resume and program commands. The system can determine the status of the program operation using the Q7 or Q6 status bits, just as in the standard program operation. After an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended sectors. ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions. Another Erase Suspend command can be written after the chip has resumed erasing. However, a 10ms time delay must be required after the erase re- sume command, if the system implements an endless erase suspend/resume loop, or the number of erase sus- pend/resume is exceeded 1024 times. The erase times will be expended if the erase behavior always be sus- pended. (Please refer to MXIC Flash Application Note for details.) AUTOMATIC PROGRAM COMMANDS To initiate Automatic Program mode, A three-cycle com- mand sequence is required. There are two "unlock" write cycles. These are followed by writing the Automatic Pro- gram command A0H. Once the Automatic Program command is initiated, the next WE# pulse causes a transition to an active pro- gramming operation. Addresses are latched on the fall- ing edge, and data are internally latched on the rising edge of the WE# or CE#, whichever happens first. The rising edge of WE# or CE#, whichever happens first, also begins the programming operation. The system is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin. The device provides Q2, Q3, Q5, Q6, Q7, and RY/BY# to determine the status of a write operation. If the pro- gram operation was unsuccessful, the data on Q5 is "1"(see Table 7), indicating the program operation exceed internal timing limit. The automatic programming opera- tion is completed when the data read on Q6 stops tog- gling for two consecutive read cycles and the data on Q7 and Q6 are equivalent to data written to these two bits, at which time the device returns to the Read mode(no program verify command is required). BYTE PROGRAM COMMAND SEQUENCE The device programs one byte of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 1 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using Q7, Q6, or RY/BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set Q5 to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 still "0". Only erase operations can convert a "0" to a "1". WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/ BY#. Table 10 and the following subsections describe the functions of these bits. Q7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Please note that RY/BY# pin is pro- vided for 40-pin TSOP package type only. Q7: Data# Polling The Data# Polling bit, Q7, indicates to the host sys-tem whether an Automatic Algorithm is in progress or com- pleted, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Automatic Program algorithm, the device out- puts on Q7 the complement of the datum programmed to Q7. This Q7 status also applies to programming dur- ing Erase Suspend. When the Automatic Program algo- rithm is complete, the device outputs the datum pro- grammed to Q7. The system must provide the program address to read valid status information on Q7. If a pro- gram address falls within a protected sector, Data# Poll- ing on Q7 is active for approximately 1 us, then the de- vice returns to reading array data. During the Automatic Erase algorithm, Data# Polling pro- duces a "0" on Q7. When the Automatic Erase algo- rithm is complete, or if the device enters the Erase Sus- pend mode, Data# Polling produces a "1" on Q7. This is analogous to the complement/true datum out-put de- scribed for the Automatic Program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement," or "0". The system must provide an address within any of the sec- tors selected for erasure to read valid status information on Q7. After an erase command sequence is written, if all sec- tors selected for erasing are protected, Data# Polling on Q7 is active for approximately 100 us, then the device returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects Q7 has changed from the complement to true data, it can read valid data at Q7-Q0 on the following read cycles. This is because Q7 may change asynchronously with Q0-Q6 while Output En- able (OE#) is asserted low. RY/BY#:Ready/Busy# (for 32-pin TSOP package only) The RY/BY# is a dedicated, open-drain output pin that indicates whether an Automatic Erase/Program algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# or CE#, whichever happens first, in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to Vcc. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the de- vice is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 7 shows the outputs for RY/BY# during write op- eration. Q6:Toggle BIT I Toggle Bit I on Q6 indicates whether an Automatic Pro- gram or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# or CE#, whichever happens first, in the command sequence (prior to the program or erase operation), and during the sector time- out. During an Automatic Program or Erase algorithm opera- tion, successive read cycles to any address cause Q6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all sec- tors selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected sectors are protected, the Automatic Erase algorithm erases the

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 Q2:Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively erasing (that is, the Automatic Erase algorithm is in process), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# or CE#, whichever happens first, in the command sequence. Q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by com- parison, indicates whether the device is actively eras- ing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 7 to compare outputs for Q2 and Q6. Reading Toggle Bits Q6/ Q2 Whenever the system initially begins reading toggle bit status, it must read Q7-Q0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7-Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase op- eration. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. Alterna- tively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Exceeded Timing Limits Q5 will indicate if the program or erase time has ex- ceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data# Polling and Toggle Bit are the only operating functions of the device under this condition. If this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still func- tional and may be used for the program or erase opera- tion. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase unprotected sectors, and ignores the selected sectors that are protected. The system can use Q6 and Q2 together to determine whether a sector is actively erasing or is erase sus- pended. When the device is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which sectors are erasing or erase-sus- pended. Alternatively, the system can use Q7. If a program address falls within a protected sector, Q6 toggles for approximately 2 us after the program com- mand sequence is written, then returns to reading array data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algo- rithm is complete. Table 7 shows the outputs for Toggle Bit I on Q6.

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase com- mand sequence. If Data# Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data# Polling or Toggle Bit. If Q3 is low ("0"), the device will accept additional sector erase commands. To insure the com- mand has been accepted, the system software should check the status of Q3 prior to and following each sub- sequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. DATA PROTECTION The MX29LV002C T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically re- sets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down tran- sition or system noise. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns(typical) on CE# or WE# will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one. POW ER SUPPLY DECOUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be- tween its VCC and GND. POWER-UP SEQUENCE The MX29LV002C T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. TEMPORARY SECTOR UNPROTECT This feature allows temporary unprotection of previously protected sector to change data in-system. The Tempo- rary Sector Unprotect mode is activated by setting the RESET# pin to VID(11.5V-12.5V). During this mode, for- merly protected sectors can be programmed or erased as un-protected sector. Once VID is remove from the RESET# pin, all the previously protected sectors are pro- tected again. SECTOR PROTECTION The MX29LV002C T/B features hardware sector protec- tion. This feature will disable both program and erase operations for these sectors protected. To activate this mode, the programming equipment must force VID on address pin A9 and OE# (suggest VID = 12V). Program- operation, it specifies that the entire chip is bad or com- bination of sectors are bad. If this time-out condition occurs during the byte program- ming operation, it specifies that the entire sector con- taining that byte is bad and this sector maynot be re- used, (other sectors are still functional and can be re- used). The time-out condition will not appear if a user tries to program a non blank location without erasing. Please note that this is not a device failure condition since the device was incorrectly used.

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 ming of the protection circuitry begins on the falling edge of the WE# pulse and is terminated on the rising edge. Please refer to sector protect algorithm and waveform. To verify programming of the protection circuitry, the pro- gramming equipment must force VID on address pin A9 ( with CE# and OE# at VIL and WE# at VIH). When A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1" code at device output Q0 for a protected sector. Other- wise the device will produce 00H for the unprotected sec- tor. In this mode, the addresses, except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer and device codes. (Read Silicon ID) It is also possible to determine if the sector is protected in the system by writing a Read Silicon ID command. Performing a read operation with A1=VIH, it will produce a logical "1" at Q0 for the protected sector. CHIP UNPROTECT The MX29LV002C T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. It is recommended to protect all sectors before activating chip unprotect mode. To activate this mode, the programming equipment must force VID on control pin OE# and address pin A9. The CE# pins must be set at VIL. Pins A6 must be set to VIH.(see Table 2) Refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. The unprotection mechanism begins on the falling edge of the WE# pulse and is terminated on the rising edge. It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector. It is noted that all sectors are unprotected after the chip unprotect algorithm is completed.

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature oC to +125oC Voltage with Respect to Ground A9, OE#, and Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may over- shoot VSS to -2.0 V for periods of up to 20 ns. Maxi- mum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may over- shoot to VCC +2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on pins A9, OE#, and RE- SET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. The RESET# pin is provided for 40-pin TSOP package type. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RATINGS Commercial (C) Devices Industrial (I) Devices VCC Supply Voltages Operating ranges define those limits between which the functionality of the device is guaranteed.

Table 8. CAPACITANCE TA = 25oC, f = 1.0 MHz

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

1. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

1. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.

Table 9. DC CHARACTERISTICS TA = -40oC to 85oC, VCC = 2.7V to 3.6V

1. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.  Input pulse levels: 0V/3.0V.  Input rise and fall times is equal to or less than 5ns. scope and jig) for 29LV002CT/B-70.  Reference levels for measuring timing: 1.5V. Table 10. READ OPERATIONS

Figure 3. READ TIMING WAVEFORMS

Table 11. Erase/Program Operations

1. See the "Erase and Programming Performance" section for more information.
2. RY/BY# pin is provided for 32-TSOP .

1. See the "Erase and Programming Performance" section for more information.

Table 12. Alternate CE# Controlled Erase/Program Operations

Figure 4. COMMAND WRITE TIMING WAVEFORM

Figure 5. AUTOMATIC PROGRAMMING TIMING WAVEFORM

Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

Figure 7. CE# CONTROLLED PROGRAM TIMING WAVEFORM 1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device. 2.Figure indicates the last two bus cycles of the command sequence.

Figure 8. AUTOMATIC CHIP ERASE TIMING WAVEFORM SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

Figure 9. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

Figure 10. AUTOMATIC SECTOR ERASE TIMING WAVEFORM SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

Figure 12. ERASE SUSPEND/ERASE RESUME FLOWCHART exceeded 1024 times, then the 10ms time delay must be put into consideration.

Figure 13. IN-SYSTEM SECTOR PROTECT/UNPROTECT TIMING WAVEFORM (RESET# Control) Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0.

Figure 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID

Figure 15. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control)

Figure 16. SECTOR PROTECTION ALGORITHM (A9, OE# Control)

Figure 17. IN-SYSTEM SECTOR UNPROTECTION ALGORITHM WITH RESET#=VID

Figure 18. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control) Notes: tWPP1 (Write pulse width for sector protect)=100ns min, 10us(typ.). tWPP2 (Write pulse width for sector unprotect)=100ns min, 12ms(typ).

Figure 19. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)

• It is recommended before unprotect whole chip, all sectors should be protected in advance.

Figure 20. DATA# POLLING ALGORITHM

Figure 21. TOGGLE BIT ALGORITHM Note:1.Read toggle bit twice to determine whether or not it is toggling.

1. Recheck toggle bit because it may stop toggling as Q5 change to "1".

Figure 22. DATA# POLLING TIMINGS (DURING AUTOMATIC ALGORITHMS)

1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.
2. CE# must be toggled when DATA# polling.

Figure 23. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle,
2. CE# must be toggled when toggle bit toggling.

Figure 24. RESET# TIMING WAVEFORM (for 32-pin TSOP package type) Table 13. AC CHARACTERISTICS (for 32-pin TSOP package type)

Figure 27. TEMPORARY SECTOR UNPROTECT ALGORITHM Note : 1. All protected sectors are temporary unprotected.

1. All previously protected sectors are protected again.

Figure 28. ID CODE READ TIMING WAVEFORM

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. Figure A. AC Timing at Device Power-Up Notes : 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. Symbol Parameter Notes Min. Max. Unit tVR VCC Rise Time 1 20 500000 us/V tR Inptut Signal Rise Time 1,2 20 us/V tF Inptut Signal Fall Time 1,2 20 us/V VCC ADDRESS CE# WE# OE# DATA tVR tACCtR or tF tCEtF VCC(min) GND VIH VIL VIH VIL VIH VIL VIH VIL VOH High Z VOL WP#/ACC VIH VIL Valid Ouput Valid Address tR or tF tR tOEtF tR

Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time. Table 16. LATCH-UP CHARACTERISTICS Table 15. ERASE AND PROGRAMMING PERFORMANCE(1) Note: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25°C, 3V. 3.Maximum values measured at 25°C, 2.7V. Table 17. DATA RETENTION

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE ( for MX29LV002CT/ CB) MX29LV002CT/CB is capable of operating in the CFI mode. This mode all the host system to determine the manufacturer of the device such as operating param- eters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are TABLE 18-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Address Data Query-unique ASCII string "QRY" 20 0051 22 0052 24 0059 Primary vendor command set and control interface ID code 26 0002 28 0000 Address for primary algorithm extended query table 2A 0040 2C 0000 Alternate vendor command set and control interface ID code (none) 2E 0000 30 0000 Address for secondary algorithm extended query table (none) 32 0000 34 0000 TABLE 18-2. CFI Mode: System Interface Data Values (All values in these tables are in hexadecimal) Description Address Data VCC supply, minimum (2.7V) 36 0027 VCC supply, maximum (3.6V) 38 0036 VPP supply, minimum (none) 3A 0000 VPP supply, maximum (none) 3C 0000 Typical timeout for single word/byte write (2N us) 3E 0004 Typical timeout for Minimum size buffer write (2N us) 40 0000 Typical timeout for individual block erase (2N ms) 42 000A Typical timeout for full chip erase (2N ms) 44 0000 Maximum timeout for single word/byte write times (2N X Typ) 46 0005 Maximum timeout for buffer write times (2N X Typ) 48 0000 Maximum timeout for individual block erase times (2N X Typ) 4A 0004 Maximum timeout for full chip erase times (not supported) 4C 0000 described in Table 18. The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Read ID mode; however, it is ignored otherwise. The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or read ID mode. The command is valid only when the device is in the CFI mode.

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 TABLE 18-3. CFI Mode: Device Geometry Data Values (All values in these tables are in hexadecimal) Description Address Data Device size (2N bytes) 4E 0012 Flash device interface code (refer to the CFI publication 100) 50 0000 52 0000 Maximum number of bytes in multi-byte write (not supported) 54 0000 56 0000 Number of erase block regions 58 0004 Erase block region 1 information (refer to the CFI publication 100) 5A 0000 5C 0000 5E 0040 60 0000 Erase block region 2 information 62 0001 64 0000 66 0020 68 0000 Erase block region 3 information 6A 0000 6C 0000 6E 0080 70 0000 Erase block region 4 information 72 0002 74 0000 76 0000 78 0001 TABLE 18-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values (All values in these tables are in hexadecimal) Description Address Data Query-unique ASCII string "PRI" 80 0050 82 0052 84 0049 Major version number, ASCII 86 0031 Minor version number, ASCII 88 0030 Address sensitive unlock (0=required, 1= not required) 8A 0000 Erase suspend (2= to read and write) 8C 0002 Sector protect (N= # of sectors/group) 8E 0001 Temporary sector unprotected (1=supported) 90 0001 Sector protect/unprotected scheme 92 0004 Simultaneous R/W operation (0=not supported) 94 0000 Burst mode type (0=not supported) 96 0000 Page mode type (0=not supported) 98 0000

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005

ORDERING INFORMATION

PART NO. Access Time Operating Current Standby Current PACKAGE Remark (ns) MAX. (mA) MAX. (uA) MX29LV002CTTC-70 70 30 5 32 Pin TSOP MX29LV002CBTC-70 70 30 5 32 Pin TSOP MX29LV002CTTC-90 90 30 5 32 Pin TSOP MX29LV002CBTC-90 90 30 5 32 Pin TSOP MX29LV002CTTI-70 70 30 5 32 Pin TSOP MX29LV002CBTI-70 70 30 5 32 Pin TSOP MX29LV002CTTI-90 90 30 5 32 Pin TSOP MX29LV002CBTI-90 90 30 5 32 Pin TSOP MX29LV002CTQC-70 70 30 5 32 Pin PLCC MX29LV002CBQC-70 70 30 5 32 Pin PLCC MX29LV002CTQC-90 70 30 5 32 Pin PLCC MX29LV002CBQC-90 70 30 5 32 Pin PLCC MX29LV002CTQI-70 70 30 5 32 Pin PLCC MX29LV002CBQI-70 70 30 5 32 Pin PLCC MX29LV002CTQI-90 70 30 5 32 Pin PLCC MX29LV002CBQI-90 70 30 5 32 Pin PLCC MX29LV002CTTC-70G 70 30 5 32 Pin TSOP PB free MX29LV002CTTC-90G 90 30 5 32 Pin TSOP PB free MX29LV002CBTC-70G 70 30 5 32 Pin TSOP PB free MX29LV002CBTC-90G 90 30 5 32 Pin TSOP PB free MX29LV002CTTI-70G 70 30 5 32 Pin TSOP PB free MX29LV002CTTI-90G 90 30 5 32 Pin TSOP PB free MX29LV002CBTI-70G 70 30 5 32 Pin TSOP PB free MX29LV002CBTI-90G 90 30 5 32 Pin TSOP PB free MX29LV002CTQC-70G 70 30 5 32 Pin PLCC PB free MX29LV002CTQC-90G 90 30 5 32 Pin PLCC PB free MX29LV002CBQC-70G 70 30 5 32 Pin PLCC PB free MX29LV002CBQC-90G 90 30 5 32 Pin PLCC PB free MX29LV002CTQI-70G 70 30 5 32 Pin PLCC PB free MX29LV002CTQI-90G 90 30 5 32 Pin PLCC PB free MX29LV002CBQI-70G 70 30 5 32 Pin PLCC PB free MX29LV002CBQI-90G 90 30 5 32 Pin PLCC PB free

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 PART NO. Access Time Operating Current Standby Current PACKAGE Remark (ns) MAX. (mA) MAX. (uA) MX29LV002NCTTC-70 70 30 5 32 Pin TSOP MX29LV002NCBTC-70 70 30 5 32 Pin TSOP MX29LV002NCTTC-90 90 30 5 32 Pin TSOP MX29LV002NCBTC-90 90 30 5 32 Pin TSOP MX29LV002NCTTI-70 70 30 5 32 Pin TSOP MX29LV002NCBTI-70 70 30 5 32 Pin TSOP MX29LV002NCTTI-90 90 30 5 32 Pin TSOP MX29LV002NCBTI-90 90 30 5 32 Pin TSOP MX29LV002NCTQC-70 70 30 5 32 Pin PLCC MX29LV002NCBQC-70 70 30 5 32 Pin PLCC MX29LV002NCTQC-90 70 30 5 32 Pin PLCC MX29LV002NCBQC-90 70 30 5 32 Pin PLCC MX29LV002NCTQI-70 70 30 5 32 Pin PLCC MX29LV002NCBQI-70 70 30 5 32 Pin PLCC MX29LV002NCTQI-90 70 30 5 32 Pin PLCC MX29LV002NCBQI-90 70 30 5 32 Pin PLCC MX29LV002NCTTC-70G 70 30 5 32 Pin TSOP PB free MX29LV002NCTTC-90G 90 30 5 32 Pin TSOP PB free MX29LV002NCBTC-70G 70 30 5 32 Pin TSOP PB free MX29LV002NCBTC-90G 90 30 5 32 Pin TSOP PB free MX29LV002NCTTI-70G 70 30 5 32 Pin TSOP PB free MX29LV002NCTTI-90G 90 30 5 32 Pin TSOP PB free MX29LV002NCBTI-70G 70 30 5 32 Pin TSOP PB free MX29LV002NCBTI-90G 90 30 5 32 Pin TSOP PB free MX29LV002NCTQC-70G 70 30 5 32 Pin PLCC PB free MX29LV002NCTQC-90G 90 30 5 32 Pin PLCC PB free MX29LV002NCBQC-70G 70 30 5 32 Pin PLCC PB free MX29LV002NCBQC-90G 90 30 5 32 Pin PLCC PB free MX29LV002NCTQI-70G 70 30 5 32 Pin PLCC PB free MX29LV002NCTQI-90G 90 30 5 32 Pin PLCC PB free MX29LV002NCBQI-70G 70 30 5 32 Pin PLCC PB free MX29LV002NCBQI-90G 90 30 5 32 Pin PLCC PB free

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005 PART NAME DESCRIPTION MX 29 LV 70C T T C G OPTION: G: Lead-free package R: Restricted VCC (3.0V~3.6V) Q: Restricted VCC (3.0V~3.6V) with Lead-free package SPEED: 70: 70ns 90: 90ns TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: Q: PLCC T: TSOP BOOT BLOCK TYPE: T: Top Boot B: Bottom Boot REVISION: C DENSITY & MODE: 002: 2M, x8 Boot Block 002N: 2M, x8 Boot Block, RESET PIN DISABLE TYPE: L, LV: 3V DEVICE: 29:Flash 002/002N

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005

PACKAGE INFORMATION

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005

P/N:PM1204 MX29LV002C/002NC T/B REV. 1.0, JUN. 30, 2005

REVISION HISTORY

Revision No.Description Page Date 1.0 1. Removed "Preliminary" P1 JUN/30/2005 2. Added "Recommended Operating Conditions" P48

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