MX27L1000 MCNIX | Alldatasheet

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Technical content

A0~A16 Address Input Q0~Q7 Data Input/Output CE Chip Enable Input OE Output Enable Input PGM Programmable Enable Input VPP Program Supply Voltage NC No Internal Connection VCC Power Supply Pin GND Ground Pin may be used. The MX27L1000 supports a intelligent fast programming algorithm which can result in programming time of less than thirty seconds. This EPROM is packaged in industry standard 32 pin dual-in-line packages,32 lead SOP , 32 lead PLCC, and 32 lead TSOP packages.

FEATURES

  • 128K x 8 organization
  • Wide power supply range, 2.7V DC to 3.6VDC
  • +12.5V programming voltage
  • Fast access time:90/120/150/200/250 ns
  • Totally static operation
  • Completely TTL compatible PIN CONFIGURATIONS

32 PDIP/SOP

  • Operating current: 20mA @3.6V, 5MHz
  • Standby current: 10uA
  • Package type: - 32 pin plastic DIP - 32 pin SOP - 32 pin TSOP - 32 pin PLCC P/N: PM0238 REV. 3.8, AUG. 26, 2003 GENERAL DESCRIPTION The MX27L1000 is a 1M-bit, One Time Programmable Read Only Memory. It isorganized as 128K words by 8 bits per word, opeates from a single 2.7 to 3.6 volt supply, has a static standby mode, and features fast single address location programming. All programming signals are TTL levels, requirin a single pulse. For programming outside from the system, existing EPROM programmers

32 PLCC

32 TSOP

1M-BIT [128Kx8] LOW VOLTAGE OPERATION CMOS EPROM MX27L1000 VPP A16 A15 A12 GND VCC PGM NC A14 A13 A11 OE A10 CE 14 17 20 32 30 A14 A13 A11 OE A10 CE GND A12 A15 A16 VPP VCC PGM NC MX27L1000 A11 A13 A14 NC PGM VCC VPP A16 A15 A12 OE A10 CE GND MX27L1000 CONTROL LOGIC OUTPUT BUFFERS Q0~Q17 CE PGM OE A0~A16 ADDRESS INPUTS Y -DECODER X-DECODER Y -SELECT 1M BIT CELL MAXTRIX VCC GND VPP

P/N: PM0238 REV. 3.8 , AUG. 26, 2003 AUTO IDENTIFY MODE The auto identify mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and device type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the MX27L1000. To activate this mode, the programming equipment must force 12.0 ± 0.5 V on address line A9 of the device. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode. Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX27L1000, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (Q7) defined as the parity bit. READ MODE The MX27L1000 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tQE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC - tOE. STANDBY MODE The MX27L1000 has a CMOS standby mode which reduces the maximum VCC current to 10 uA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The MX27L1000 also has a TTL-standby mode which reduces the maximum VCC current to 0.25mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. FUNCTIONAL DESCRIPTION THE PROGRAMMING OF THE MX27L1000 When the MX27L1000 is delivered, or it is erased, the chip has all 1M bits in the "ONE" or HIGH state. "ZERO" are loaded into the MX27L1000 through the procedure of programming. For programming, the data to be programmed is applied with 8 bits in parallel to the data pins. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. When programming an MXIC EPROM, a 0.1uF capacitor is required across VPP and ground to suppress spurious voltage transients which may damage the device. FAST PROGRAMMING The device is set up in the fast programming mode when the programming voltage VPP = 12.75V is applied, with VCC = 6.25 V and PGM = VIL(or OE = VIH) (Algorithm is shown in Figure 1). The programming is achieved by applying a single TTL low level 100us pulse to the PGM input after addresses and data line are stable. If the data is not verified, an additional pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = VPP = 5V ± 10%. PROGRAM INHIBIT MODE Programming of multiple MX27L1000s in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX27L1000 may be common. A TTL low-level program pulse applied to an MX27L1000 CE input with VPP = 12.5 ± 0.5 V and PGM LOW will program that MX27L1000. A high-level CE input inhibits the other MX27L1000s from being programmed. PROGRAM VERIFY MODE Verification should be performed on the programmed bits to determine that they were correctly programmed. The verification should be performed with OE and CE at VIL, PGM at VIH, and VPP at its programming voltage.

P/N: PM0238 REV. 3.8 , AUG. 26, 2003 TWO-LINE OUTPUT CONTROL FUNCTION To accommodate multiple memory connections, a two- line control function is provided to allow for: 1. Low memory power dissipation, 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. NOTES: 1. VH = 12.0 V ± 0.5 V 2. X = Either VIH or VIL 3. A1 - A8 = A10 - A16 = VIL(For auto select) 4. See DC Programming Characteristics for VPP voltage during programming. SYSTEM CONSIDERATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 uF bulk electrolytic capacitor should be used between Vcc and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE PINS MODE CE OE PGM A0 A9 VPP OUTPUTS Read VIL VIL X X X VCC DOUT Output Disable VIL VIH X X X VCC High Z Standby (TTL) VIH X X X X VCC High Z Standby (CMOS) VCC ± 0.3V X X X X VCC High Z Program VIL VIH VIL X X VPP DIN Program Verify VIL VIL VIH X X VPP DOUT Program Inhibit VIH X X X X VPP High Z Manufacturer Code(3) VIL VIL X VIL VH VCC C2H Device Code(3) VIL VIL X VIH VH VCC 0EH

FIGURE 1. FAST PROGRAMMING FLOW CHART

P/N: PM0238 REV. 3.8 , AUG. 26, 2003 SWITCHING TEST CIRCUITS SWITCHING TEST WAVEFORMS DEVICE UNDER TEST DIODES = IN3064 OR EQUIVALENT CL = 100 pF including jig capacitance CL = 30 pF including jig capacitance for 90/120ns 6.2K ohm 1.8K ohm +5V CL 2.0V 0.8V TEST POINTS INPUT 2.0V 0.8V OUTPUT AC TESTING: AC driving levels are 2.4V/0.4V for both commercial grade and industrial grade. Input pulse rise and fall times are < 10ns. AC driving levels SWITCHING TEST WAVEFORMS (For Speed 90/120ns) 1.5V TEST POINTS INPUT 1.5V OUTPUT AC TESTING: AC driving levels are 3.0V/0V for both commercial grade and industrial grade. Input pulse rise and fall times are < 10ns. AC driving levels

P/N: PM0238 REV. 3.8 , AUG. 26, 2003 DC CHARACTERISTICS SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS VOH Output High Voltage VCC - 0.3 V IOH = -100uA VCC=3.0V VOL Output Low Voltage 0.3 V IOL = 2.1mA, VCC = 3.0V VIH Input High Voltage 2.0 Vcc + 0.5 V VIL Input Low Voltage -0.3 0.6 V 2.7V < VCC < 3.6V ILI Input Leakage Current -10 10 uA VIN = 0 to 3.6V ILO Output Leakage Current -10 10 uA VOUT = 0 to 3.6V ICC3 VCC Power-Down Current 10 uA CE = VCC ± 0.3V ICC2 VCC Standby Current 0.25 mA CE = VIH ICC1 VCC Active Current 20 mA CE = VIH, f=5MHz, lout = OmA, Vcc=3.6V IPP Supply Current Read 10 uA CE = OE = VIL, VPP = VCC NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change. DC/AC Operating Conditions for Read Operation ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature -40oC to 85oC Storage Temperature -65 oC to 125oC Applied Input Voltage -0.5V to 7.0V Applied Output Voltage -0.5V to VCC+0.5V VCC to Ground Potential -0.5V to 7.0V V9 & VPP -0.5V to 13.5V MX27L1000 Operating Temperature Commercial 0 °C to 70°C0 °C to 70°C0 °C to 70°C0 °C to 70°C0 °C to 70°C Industrial -40°C to 85°C -40 °C to 85°C -40°C to 85°C -40 °C to 85°C -40°C to 85°C CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only) SYMBOL PARAMETER TYP. MAX. UNIT CONDITIONS CIN Input Capacitance 8 12 pF VIN = 0V COUT Output Capacitance 8 12 pF VOUT = 0V CVPP VPP Capacitance 18 25 pF VPP = 0V

P/N: PM0238 REV. 3.8 , AUG. 26, 2003 AC CHARACTERISTICS 27L1000-90 27L1000-12 27L1000-15 27L1000-20 27L1000-25 tACC Address to Output Delay 90 120 150 200 250 ns CE = OE = VIL tCE Chip Enable to Output Delay 90 120 150 200 250 ns OE = VIL tOE Output Enable to Output Delay 40 50 70 100 120 ns CE = VIL tDF OE High to Output Float, 0 30 0 40 0 50 0 60 0 70 ns or CE High to Output Float tOH Output Hold from Address, 00000n s CE or OE which ever occurred first AC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5°C SYMBOL PARAMETER MIN. MAX. UNIT tAS Address Setup Time 2.0 us tOES OE Setup Time 2.0 us tDS Data Setup Time 2.0 us tAH Address Hold Time 0 us tDH Data Hold Time 2.0 us tDFP Out put Enable to Output Float Delay 0 130 ns tVPS VPP Setup Time 2.0 us tPW PGM Program Pulse Width 95 105 us tVCS VCC Setup Time 2.0 us tCES CE Setup Time 2.0 us tOE Data valid from OE 150 ns DC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5°C SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS VOH Output High Voltage 2.4 V IOH = -0.10mA VOL Output Low Voltage 0.4 V IOL = 2.1mA VIH Input High Voltage 2.0 VCC + 0.5 V VIL Input Low Voltage -0.3 0.8 V ILI Input Leakage Current -10 10 uA VIN = 0 to 3.6V VH A9 Auto Select Voltage 11.5 12.5 V ICC3 VCC Supply Current (Program & Verify) 50 mA IPP2 VPP Supply Current(Program) 30 mA CE = VIL, OE = VIH VCC1 Fast Programming Supply Voltage 6.00 6.50 V VPP1 Fast Programming Voltage 12.5 13.0 V

P/N: PM0238 REV. 3.8 , AUG. 26, 2003 FAST PROGRAMMING ALGORIHTM WAVEFORMS WAVEFORMS READ CYCLE ADDRESS INPUTS DATA OUT OE CE DATA ADDRESS VALID DATA tDF tACC tCE tOE tOH Addresses CE OE PGM DATA VPP VCC VIH VIL VPP1 VCC VCC1 VCC VIH VIL VIH VIL VIH VIL DATA OUT VALID Hi-z DATA IN STABLE tAS tVPS tVCS tCES tOE Max tPW tDS tDH tOES tDFP tAH PROGRAM VERIFYPROGRAM

P/N: PM0238 REV. 3.8 , AUG. 26, 2003 ORDER INFORMATION PART NO. ACCESS TIME(ns) OPERATING STANDBY OPERATING PACKAGE CURRENT MAX.(mA) CURRENT MAX.(uA) TEMPERATURE MX27L1000PC-25 250 30 10 0 °C to 70°C 32 Pin DIP MX27L1000QC-25 250 20 10 0 °C to 70°C 32 Pin PLCC MX27L1000MC-25 250 30 10 0 °C to 70°C 32 Pin SOP MX27L1000TC-25 250 30 10 0 °C to 70°C 32 Pin TSOP MX27L1000PC-20 200 30 10 0 °C to 70°C 32 Pin DIP MX27L1000QC-20 200 20 10 0 °C to 70°C 32 Pin PLCC MX27L1000MC-20 200 30 10 0 °C to 70°C 32 Pin SOP MX27L1000TC-20 200 30 10 0 °C to 70°C 32 Pin TSOP MX27L1000PC-15 150 30 10 0 °C to 70°C 32 Pin DIP MX27L1000QC-15 150 20 10 0 °C to 70°C 32 Pin PLCC MX27L1000MC-15 150 30 10 0 °C to 70°C 32 Pin SOP MX27L1000TC-15 150 30 10 0 °C to 70°C 32 Pin TSOP MX27L1000PC-12 120 30 10 0 °C to 70°C 32 Pin DIP MX27L1000QC-12 120 20 10 0 °C to 70°C 32 Pin PLCC MX27L1000MC-12 120 30 10 0 °C to 70°C 32 Pin SOP MX27L1000TC-12 120 30 10 0 °C to 70°C 32 Pin TSOP MX27L1000PC-90 90 30 10 0 °C to 70°C 32 Pin DIP MX27L1000QC-90 90 20 10 0 °C to 70°C 32 Pin PLCC MX27L1000MC-90 90 30 10 0 °C to 70°C 32 Pin SOP MX27L1000TC-90 90 30 10 0 °C to 70°C 32 Pin TSOP MX27L1000PI-25 250 30 10 -40 °C to 85°C 32 Pin DIP MX27L1000QI-25 250 20 10 -40 °C to 85°C 32 Pin PLCC MX27L1000MI-25 250 30 10 -40 °C to 85°C 32 Pin SOP MX27L1000TI-25 250 30 10 -40 °C to 85°C 32 Pin TSOP MX27L1000PI-20 200 30 10 -40 °C to 85°C 32 Pin DIP MX27L1000QI-20 200 20 10 -40 °C to 85°C 32 Pin PLCC MX27L1000MI-20 200 30 10 -40 °C to 85°C 32 Pin SOP MX27L1000TI-20 200 30 10 -40 °C to 85°C 32 Pin TSOP MX27L1000PI-15 150 30 10 -40 °C to 85°C 32 Pin DIP MX27L1000QI-15 150 20 10 -40 °C to 85°C 32 Pin PLCC MX27L1000MI-15 150 30 10 -40 °C to 85°C 32 Pin SOP MX27L1000TI-15 150 30 10 -40 °C to 85°C 32 Pin TSOP MX27L1000PI-12 120 30 10 -40 °C to 85°C 32 Pin DIP MX27L1000QI-12 120 20 10 -40 °C to 85°C 32 Pin PLCC MX27L1000MI-12 120 30 10 -40 °C to 85°C 32 Pin SOP MX27L1000TI-12 120 30 10 -40 °C to 85°C 32 Pin TSOP MX27L1000PI-90 90 30 10 -40 °C to 85°C 32 Pin DIP MX27L1000QI-90 90 20 10 -40 °C to 85°C 32 Pin PLCC MX27L1000MI-90 90 30 10 -40 °C to 85°C 32 Pin SOP MX27L1000TI-90 90 30 10 -40 °C to 85°C 32 Pin TSOP

P/N: PM0238 REV. 3.8 , AUG. 26, 2003

PACKAGE INFORMATION

P/N: PM0238 REV. 3.8 , AUG. 26, 2003

P/N: PM0238 REV. 3.8 , AUG. 26, 2003

P/N: PM0238 REV. 3.8 , AUG. 26, 2003

P/N: PM0238 REV. 3.8 , AUG. 26, 2003

REVISION HISTORY

Revision No.Description Page Date 2.4 Page 3:Mode Select Table : VPP pin-"VCC" instead of " X". 9/24/1996 Revise SWITCHING TEST WAVEFORM, VOL=0.6V to VOL=0.8V. 3.0 Eliminate Interactive Programming Mode. 6/18/1997

3.1 IPP 100uA --> 10uA 8/07/1997

3.2 Change TSOP Orientation 4/09/1998

3.3 Add speed 90/120ns P1 ,9,10 OCT/13/1999

Change VIH/VIL, VOH/VOL for 90/120ns P5 Change CL to 30pF for 90/120ns P5

3.4 Cancel 32pin ceramic DIP Package P1,2,9,11 FEB/25/2000

3.5 To modify Package Information P10~13 JUL/19/2001

3.6 Cancel "Ultraviolet Erasable" wording in General Description P1 AUG/20/2001

3.7 To modify Package Information P10~13 NOV/19/2002

3.8 To modify 32-PLCC package information P12 AUG/26/2003

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