27C256

27C256 SYC | Alldatasheet

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Features

Y Clocked sense amps for fast access time down to 250 ns Y Low CMOS power consumption Ð Active power: 55 mW max Ð Standby power: 0.55 mW max Y Performance compatible to NSC800 TM CMOS microprocessor Y Single 5V power supply Y Pin compatible with NMOS 256K EPROMs Y Fast and reliable programming (0.5 ms for most bytes) Y Static operationÐno clocks required Y TTL, CMOS compatible inputs/outputs Y TRI-STATEÉ output Y Optimum EPROM for total CMOS systems Y Windowed DIP and LCC package options Y Specifications guaranteed over full military temperature range ( b55§Ct o a125§C) Y This device is processed in compliance with SMD 86063, and the DIP version is dual marked Block Diagram TL/D/10332–1 Pin Names A0–A14 Addresses CE Chip Enable OE Output Enable O0 –O7 Outputs PGM Program NC No Connect TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. NSC800TM is a trademark of National Semiconductor Corporation.

27C512 27C128 27C64 27C32 27C16 27512 27128 2764 2732 2716 A15 V PP VPP A12 A12 A12 A7 A7 A7 A7 A7 A6 A6 A6 A6 A6 A5 A5 A5 A5 A5 A4 A4 A4 A4 A4 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 O0 O0 O0 O0 O0 O1 O1 O1 O1 O1 O2 O2 O2 O2 O2 GND GND GND GND GND 27C256Q Dual-In-Line Package TL/D/10332–2 27C16 27C32 27C64 27C128 27C512 2716 2732 2764 27128 27512 VCC VCC VCC PGM PGM A14 VCC VCC NC A13 A13 A8 A8 A8 A8 A8 A9 A9 A9 A9 A9 VPP A11 A11 A11 A11 OE OE/VPP OE OE OE/VPP A10 A10 A10 A10 A10 CE/PGM CE CE CE CE O7 O7 O7 O7 O7 O6 O6 O6 O6 O6 O5 O5 O5 O5 O5 O4 O4 O4 O4 O4 O3 O3 O3 O3 O3 Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the 27C256 pins. TL/D/10332–6 Bottom View Military Temperature Range ( b55§Ct o a125§C) VCC e 5V g10% Parameter/Order Number Access Time 27C256Q250/883 250 27C256Q300/883 300 27C256Q350/883 350 27C256E250/883 250 27C256E300/883 300 27C256E350/883 350

Absolute Maximum Ratings (Note 1) Temperature Under Bias b55§Ct o a125§C Storage Temperature b65§Ct o a150§C All Input Voltages with Respect to Ground (Note 10) a6.5V to b0.6V All Output Voltages with Respect to Ground (Note 10) V CC a1.0V to GND b 0.6V VPP Supply Voltage with Respect to Ground during Programming a14.0V to b0.6V Power Dissipation 1.0W Lead Temperature (Soldering, 10 Seconds) 300 §C VCC Supply Voltage with Respect to Ground a7.0V to b0.6V Operating Conditions (Note 7) Temperature Range (T case) b55§Ct o a125§C VCC Power Supply 5V g10% READ OPERATION Symbol Parameter Conditions Min Typ Max Units ILI Input Load Current V IN e VCC or GND 10 mA ILO Output Leakage Current V OUT e VCC or GND, CE e VIH 10 mA ICC1 VCC Current (Active) CE e VIL,f e 5 MHz 52 0 m A(Note 9) TTL Inputs Inputs e VIH or V IL, I/O e 0m A ICC2 VCC Current (Active) CE e GND, f e 5 MHz 31 0 m A(Note 9) CMOS Inputs Inputs e VCC or GND, I/O e 0m A ICCSB1 VCC Current (Standby) CE e VIH 0.1 1 mATTL Inputs ICCSB2 VCC Current (Standby) CE e VCC 0.5 100 mACMOS Inputs IPP VPP Load Current V PP e VCC 200 mA VIL Input Low Voltage b0.1 0.8 V VIH Input High Voltage 2.0 V CC a 1V VOL1 Output Low Voltage I OL e 2.1 mA 0.45 V VOH1 Output High Voltage I OH eb 400 mA 2.4 V VOL2 Output Low Voltage I OL e 0 mA 0.1 V VOH2 Output High Voltage I OH e 0 mA 4.4 V 27C256 Symbol Parameter Conditions 250 300 350 Units Min Max Min Max Min Max tACC Address to Output Delay CE e OE e VIL 250 300 350 ns tCE CE to Output Delay OE e VIL 250 300 350 ns tOE OE to Output Delay CE e VIL 100 120 120 ns tDF OE High to Output Float CE e VIL 0 60 0 105 0 105 ns tOH Output Hold from Addresses, CE e OE e VIL CE or OE , Whichever 0 0 0 ns Occurred First

Capacitance TA ea 25§C, f e 1 MHz (Note 2) Symbol Parameter Conditions Typ Max Units CIN Input Capacitance V IN e 0V 6 10 pF COUT Output Capacitance V OUT e 0V 9 14 pF AC Test Conditions Output Load 1 TTL Gate and CL e 100 pF (Note 8) Input Rise and Fall Times s 5n s Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level Inputs 0.8V and 2V Outputs 0.8V and 2V AC Waveforms (Notes 6, 7 and 9) TL/D/10332–3 Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to t ACC b tOE after the falling edge of CE without impacting t ACC. Note 4: The t DF and t CF compare level is determined as follows: High to TRI-STATE, the measured V OH1 (DC) b 0.10V; Low to TRI-STATE, the measured V OL1 (DC) a 0.10V. Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 mF ceramic capacitor be used on every device between V CC and GND. Note 7: The outputs must be restricted to V CC a 1.0V to avoid latch-up and device damage. Note 8: TTL Gate: I OL e 1.6 mA, I OH eb 400 mA. CL: 100 pF includes fixture capacitance. Note 9: VPP may be connected to V CC except during programming. Note 10: Inputs and outputs can undershoot to b2.0V for 20 ns Max.

Programming Characteristics (Notes 1, 2, 3 and 4) Symbol Parameter Conditions Min Typ Max Units tAS Address Setup Time 2 ms tOES OE Setup Time 2 ms tVPS VPP Setup Time 2 ms tVCS VCC Setup Time 2 ms tDS Data Setup Time 2 ms tAH Address Hold Time 0 ms tDH Data Hold Time 2 ms tDF Output Enable to CE e VIL 0 130 nsOutput Float Delay tPW Program Pulse Width 0.5 0.5 10 ns tOE Data Valid from OE CE e VIL 150 ns IPP VPP Supply Current during CE e VIL 30 mAProgramming Pulse PGM e VIL ICC VCC Supply Current 10 mA TA Temperature Ambient 20 25 30 §C VCC Power Supply Voltage 5.75 6.0 6.25 V VPP Programming Supply Voltage 12.2 13.0 13.3 V tFR Input Rise, Fall time 5 ns VIL Input Low Voltage 0.0 0.45 V VIH Input High Voltage 2.4 4.0 V tIN Input Timing Reference Voltage 0.8 1.5 2.0 V tOUT Output Timing Reference Voltage 0.8 1.5 2.0 V Note 1: National’s standard product warranty applies only to devices programmed to specifications described herein. Note 2: VCC must be applied simultaneously or before V PP and removed simultaneously or after V PP. The EPROM must not be inserted into or removed from a board with voltage applied to V PP or V CC. Note 3: The maximum absolute allowable voltage which may be applied to the V PP pin during programming is 14V. Care must be taken when switching the V PP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 mF capacitor is required across V PP,V CC to GND to suppress spurious voltage transients which may damage the device. Note 4: Programming and program verify are tested with the Interactive Program Algorithm, at typical power supply voltages and timings. The Min and Max Limit Parameters are Design parameters, not Tested or guaranteed. Programming Waveforms (Note 3) TL/D/10332–4

Interactive Programming Algorithm Flow Chart TL/D/10332–5 FIGURE 1

The six modes of operation of the 27C256 are listed in Ta- ble I. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are V CC and VPP. The V PP power supply must be at 13.0V during the three programming modes, and must be at 5V in the other three modes. The V CC power supply must be at 6V during the three programming modes, and at 5V in the other three modes. Read Mode The 27C256 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE ) is the power control and should be used for device selection. Output Enable (OE ) is the output con- trol and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (t ACC) is equal to the delay from CE to output (t CE). Data is available at the outputs t OE after the falling edge of OE , assuming that CE has been low and addresses have been stable for at least t ACC –tOE. The sense amps are clocked for fast access time. V CC should therefore be maintained at operating voltage during read and verify. If V CC temporarily drops below the spec. voltage (but not to ground) an address transition must be performed after the drop to ensure proper output data. Standby Mode The 27C256 has a standby mode which reduces the active power dissipation by 99%, from 55 mW to 0.55 mW. The 27C256 is placed in the standby mode by applying a CMOS high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Output OR-Tying Because 27C256s are usually used in larger memory arrays, National has provided a 2-line control function that accom- modates this use of multiple memory connections. The 2- line control function allows for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recom- mended that CE (pin 20) be decoded and used as the pri- mary device selecting function, while OE (pin 22) be made a common connection to all devices in the array and connect- ed to the READ line from the system control bus. This as- sures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. Programming CAUTION: Exceeding 14V on pin 1 (V PP will damage the 27C256. Initially, and after each erasure, all bits of the 27C256 are in the ‘‘1’’ state. Data is introduced by selectively program- ming ‘‘0s’’ into the desired bit locations. Although only ‘‘0s’’ will be programmed, both ‘‘1s’’ and ‘‘0s’’ can be presented in the data word. The only way to change a ‘‘0’’ to a ‘‘1’’ is by ultraviolet light erasure. The 27C256 is in the programming mode when the V PP power supply is at 13.0V and OE is at V IH. It is required that at least a 0.1 mF capacitor be placed across V PP,V CC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active low TTL program pulse is applied to the CE /PGM input. A program pulse must be applied at each address location to be pro- grammed. Any location may be programmed at any timeÐ either individually, sequentially, or at random. The 27C256 is designed to be programmed with interactive programming, where each address is programmed with a series of 0.5 ms pulses until it verifies (up to a maximum of 20 pulses or 10 ms). The 27C256 must not be programmed with a DC signal applied to the CE /PGM input. Programming multiple 27C256s in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the paralleled 27C256s may be connected together when they are pro- grammed with the same data. A low level TTL pulse applied to the CE /PGM input programs the paralleled 27C256s. TABLE I. Mode Selection Mode Pins CE /PGM OE VPP VCC Outputs Read V IL VIL 5V 5V D OUT Standby V IH Don’t Care 5V 5V Hi-Z Program V IL VIH 13.0V 6V D IN Program Verify V IH VIL 13.0V 6V D OUT Program Inhibit V IH VIH 13.0V 6V Hi-Z Output Disable Don’t Care V IH 5V 5V Hi-Z

Functional Description (Continued) Program Inhibit Programming multiple 27C256s in parallel with different data is also easily accomplished. Except for CE all like in- puts (including OE ) of the parallel 27C256s may be com- mon. A TTL low level program pulse applied to an 27C256’s. CE /PGM input with V PP at 13.0V will program that 27C256. A TTL high level CE input inhibits the other 27C256s from being programmed. Program Verify A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with V PP at 13.0V. V PP must be at VCC, except during programming and program verify. ERASURE CHARACTERISTICS The erasure characteristics of the 27C256 are such that erasure begins to occur when exposed to light with wave- lengths shorter than approximately 4000 Angstroms ( Ð). It should be noted that sunlight and certain types of fluores- cent lamps have wavelengths in the 3000 Ж4000Ð range. After programming, opaque labels should be placed over the 27C256’s window to prevent unintentional erasure. Cov- ering the window will also prevent temporary functional fail- ure due to the generation of photo currents. The recommended erasure procedure for the 27C256 is ex- posure to short wave ultraviolet light which has a wave- length of 2537 Angstroms ( Ð). The integrated dose (i.e., UV intensity c exposure time) for erasure should be a minimum of 15W-sec/cm 2. The 27C256 should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. Table II shows the minimum 27C256 erasure time for various light intensities. An erasure system should be calibrated periodically. The distance from lamp to unit should be maintained at one inch. The erasure time increases as the square of the distance. (If distance is doubled the erasure time increases by a factor of 4.) Lamps lose intensity as they age. When a lamp is changed, the distance has changed or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incompete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when in- complete erasure was the problem. SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, I CC, has three segments that are of interest to the system de- signerÐthe standby current level, the active current level, and the transient current peaks that are produced by volt- age transitions on input pins. The magnitude of these tran- sient current peaks is dependent on the output capacitance loading of the device. The associated V CC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 mF ceramic capacitor be used on every device between V CC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 mF bulk electrolytic capacitor should be used between V CC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The pur- pose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces. TABLE II. Minimum 27C256 Erasure Time Light Intensity Erasure Time (Micro/Watts/cm2) (Minutes) 15,000 20 10,000 25 5,000 50

Physical Dimensions inches (millimeters) 32L Leadless Chip Carrier (E) Order Number 27C256E350/883, 27C256E300/883, 27C256E250/883

27C256 262, 144-BIT (32,768 x 8) UV Erasable CMOS PROM Military Qualified Physical Dimensions inches (millimeters) (Continued) Lit. Ý 114730

28 Lead EPROM Dual-In-Line Cerdip Package (JQ) Small Window

Order Number 27C256Q350/883, 27C256Q300/883, 27C256Q250/883