27C256

27C256 NSC | Alldatasheet

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Ð 120 ns access time Y JEDEC standard pin configuration Ð 28-pin DIP package Ð 32-pin chip carrier Y Drop-in replacement for 27C256 or 27256 Y Manufacturer’s identification code Block Diagram TL/D/10833–1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. HPCTM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M65/Printed in U. S. A.

27C080 27C040 27C020 27C010 27C512 A19 XX/V PP XX/VPP XX/VPP A16 A16 A16 A16 A15 A15 A15 A15 A15 A12 A12 A12 A12 A12 A7 A7 A7 A7 A7 A6 A6 A6 A6 A6 A5 A5 A5 A5 A5 A4 A4 A4 A4 A4 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 O0 O0 O0 O0 O0 O1 O1 O1 O1 O1 O2 O2 O2 O2 O2 GND GND GND GND GND DIP NM27C256 TL/D/10833–2 27C512 27C010 27C020 27C040 27C080 VCC VCC VCC VCC XX/PGM XX/PGM A18 A18 VCC XX A17 A17 A17 A14 A14 A14 A14 A14 A13 A13 A13 A13 A13 A8 A8 A8 A8 A8 A9 A9 A9 A9 A9 A11 A11 A11 A11 A11 OE/VPP OE OE OE OE/VPP A10 A10 A10 A10 A10 CE/PGM CE CE CE/PGM CE/PGM O7 O7 O7 O7 O7 O6 O6 O6 O6 O6 O5 O5 O5 O5 O5 O4 O4 O4 O4 O4 O3 O3 O3 O3 O3 Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C256 pins. Commercial Temp. Range (0 §Ct o a70§C) VCC e 5V g10% Parameter/Order Number Access Time (ns) NM27C256 Q, N, V 120 120 NM27C256 Q, N, V 150 150 NM27C256 Q, N, V 200 200 Military Temp. Range ( b55§Ct o a125§C) VCC e 5V g10% Parameter/Order Number Access Time (ns) NM27C256 QM 150 150 NM27C256 QM 250 250 Extended Temp. Range ( b40§Ct o a85§C) VCC e 5V g10% Parameter/Order Number Access Time (ns) NM27C256 QE, NE, VE 120 120 NM27C256 QE, NE, VE 150 150 NM27C256 QE, NE, VE 200 200 Note: Surface mount PLCC package available for commercial and extended temperature ranges only. Q e Quartz-Windowed Ceramic DIP N e Plastic OTP DIP V e Surface-Mount PLCC # All packages conform to the JEDEC standard. # All versions are guaranteed to function for slower speeds. Pin Names Symbol Description A0–A14 Addresses CE Chip Enable OE Output Enable O0–O7 Outputs PGM Program XX Don’t Care (during Read) PLCC TL/D/10833–3 Top

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C All Input Voltages except A9 with Respect to Ground b0.6V to a7V VPP and A9 with Respect to Ground b0.7V to a14V VCC Supply Voltage with Respect to Ground b 0.6V to a7V ESD Protection l 2000V All Output Voltages with Respect to Ground V CC a 1.0V to GND b0.6V Operating Range Range Temperature V CC Comm’l 0 §Ct o a70§C a5V g10% Industrial b40§Ct o a85§C a5V g10% Military b55§Ct o a125§C a5V g10% Read Operation Symbol Parameter Test Conditions Min Max Units VIL Input Low Level b0.5 0.8 V VIH Input High Level 2.0 V CC a 1V VOL Output Low Voltage I OL e 2.1 mA 0.4 V VOH Output High Voltage I OH eb 2.5 mA 3.5 V ISB1 VCC Standby Current CE e VCC g0.3V 100 mA(Note 11) (CMOS) ISB2 VCC Standby Current (TTL) CE e VIH 1m A ICC1 VCC Active Current CE e OE e VIL,f e 5 MHz 35 mATTL Inputs Inputs e VIH or V IL, I/O e 0m A IPP VPP Supply Current V PP e VCC 10 mA VPP VPP Read Voltage V CC b 0.7 V CC V ILI Input Load Current V IN e 5.5V or GND b11 mA ILO Output Leakage Current V OUT e 5.5V or GND b10 10 mA Symbol Parameter 100 120 150 200 Units Min Max Min Max Min Max Min Max tACC Address to Output Delay 100 120 150 200 ns tCE CE to Output Delay 100 120 150 200 tOE OE to Output Delay 50 50 50 50 tDF Output Disable to 30 35 45 55(Note 2) Output Float tOH Output Hold from Addresses, (Note 2) CE or OE ,0 0 0 0 Whichever Occurred First

Capacitance TA ea 25§C, f e 1 MHz (Note 2) Symbol Parameter Conditions Typ Max Units CIN Input Capacitance V IN e 0V 6 12 pF COUT Output Capacitance V OUT e 0V 9 12 pF AC Test Conditions Output Load 1 TTL Gate and CL e 100 pF (Note 8) Input Rise and Fall Times s 5n s Input Pulse Levels 0.45 to 2.4V Timing Measurement Reference Level (Note 10) Inputs 0.8V and 2.0V Outputs 0.8V and 2.0V AC Waveforms (Notes 6, 7 and 9) TL/D/10833–4 Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to t ACC b tOE after the falling edge of CE without impacting t ACC. Note 4: The t DF and t CF compare level is determined as follows: High to TRI-STATE É, the measured V OH1 (DC) b 0.10V; Low to TRI-STATE, the measured V OL1 (DC) a 0.10V. Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 mF ceramic capacitor be used on every device between V CC and GND. Note 7: The outputs must be restricted to V CC a 1.0V to avoid latch-up and device damage. Note 8: TTL Gate: I OL e 1.6 mA, I OH eb 400 mA. CL e 100 pF includes fixture capacitance. Note 9: VPP may be connected to V CC except during programming. Note 10: Inputs and outputs can undershoot to b2.0V for 20 ns Max. Note 11: CMOS inputs: V IL e GND g0.3V, V IH e VCC g0.3V.

Programming Characteristics (Notes 1, 2, 3, 4 and 5) Symbol Parameter Conditions Min Typ Max Units tAS Address Setup Time 1 ms tOES OE Setup Time 1 ms tVPS VPP Setup Time 1 ms tVCS VCC Setup Time 1 ms tDS Data Setup Time 1 ms tAH Address Hold Time 0 ms tDH Data Hold Time 1 ms tDF Output Enable to Output CE e VIL 06 0 n sFloat Delay tPW Program Pulse Width 95 100 105 ms tOE Data Valid from OE CE e VIL 100 ns IPP VPP Supply Current CE e VIL 30 mAduring Programming Pulse ICC VCC Supply Current 50 mA TA Temperature Ambient 20 25 30 §C VCC Power Supply Voltage 6.0 6.25 6.5 V VPP Programming Supply Voltage 12.5 12.75 13.0 V tFR Input Rise, Fall Time 5 ns VIL Input Low Voltage 0.0 0.45 V VIH Input High Voltage 2.4 4.0 V tIN Input Timing Reference Voltage 0.8 2.0 V tOUT Output Timing Reference Voltage 0.8 2.0 V Programming Waveforms (Note 3) TL/D/10833–5 Note 1: National’s standard product warranty applies to devices programmed to specifications described herein. Note 2: VCC must be applied simultaneously or before V PP and removed simultaneously or after V PP. The EPROM must not be inserted into or removed from a board with voltage applied to V PP or V CC. Note 3: The maximum absolute allowable voltage which may be applied to the V PP pin during programming is 14V. Care must be taken when switching the V PP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 mF capacitor is required across V PP,V CC to GND to suppress spurious voltage transients which may damage the device. Note 4: Programming and program verify are tested with the Fast Program Algorithm, at typical power supply voltages and timings. Note 5: During power up the PGM pin must be brought high ( t VIH) either coincident with or before power is applied to V PP.

Fast Programming Algorithm Flow Chart TL/D/10833–6 FIGURE 1

The six modes of operation of the EPROM are listed in Ta- ble I. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are V CC and VPP. The V PP power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The V CC power supply must be at 6.25V dur- ing the three programming modes, and at 5V in the other three modes. Read Mode The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (t ACC) is equal to the delay from CE to output (t CE). Data is available at the outputs t OE after the falling edge of OE, assuming that CE/PGM has been low and addresses have been stable for at least t ACC – tOE. Standby Mode The EPROM has a standby mode which reduces the active power dissipation by over 99%, from 385 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE/PGM input. When in standby mode, the outputs are in a high impedance state, indepen- dent of the OE input. Output Disable The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all cir- cuitry is enabled, except the outputs are in a high imped- ance state (TRI-STATE). Output OR-Typing Because the EPROM is usually used in larger memory ar- rays, National has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recom- mended that CE/PGM be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. Programming CAUTION: Exceeding 14V on pin 1 (V PP) will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the ‘‘1’s’’ state. Data is introduced by selectively program- ming ‘‘0’s’’ into the desired bit locations. Although only ‘‘0’s’’ will be programmed, both ‘‘1’s’’ and ‘‘0’s’’ can be pre- sented in the data word. The only way to change a ‘‘0’’ to a ‘‘1’’ is by ultraviolet light erasure. The EPROM is in the programming mode when the V PP power supply is at 12.75V and OE is at V IH. It is required that at least a 0.1 mF capacitor be placed across V PP,V CC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active low, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be pro- grammed. The EPROM is programmed with the Fast Pro- gramming Algorithm shown in Figure 1 . Each Address is programmed with a series of 100 ms pulses until it verifies good, up to a maximum of 25 pulses. Most memory cells will program with a single 100 ms pulse. The EPROM must not be programmed with a DC signal ap- plied to the CE/PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirments. Like inputs of the parallel EP- ROM may be connected together when they are pro- grammed with the same data. A low level TTL pulse applied to the CE/PGM input programs the paralleled EPROM. Program Inhibit Programming multiple EPROMs in parallel with different data is also easily accomplished. Except for CE/PGM, all like inputs (including OE) of the parallel EPROMs may be common. A TTL low level program pulse applied to an EP- ROM’s CE/PGM input with V PP at 12.75V will program that EPROM. A TTL high level CE/PGM input inhibits the other EPROMs from being programmed.

Functional Description (Continued) Program Verify A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with V PP at 12.75V. V PP must be at VCC, except during programming and program verify. AFTER PROGRAMMING Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the genera- tion of photo currents. MANUFACTURER’S IDENTIFICATION CODE The EPROM has a manufacturer’s identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algo- rithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. The Manufacturer’s Identification code, shown in Table II, specifically identifies the manufacturer and device type. The code for NM27C256 is ‘‘8F04’’, where ‘‘8F’’ designates that it is made by National Semiconductor, and ‘‘04’’ designates a 256K part. The code is accessed by applying 12V g0.5V to address pin A9. Addresses A1–A8, A10–A16, and all control pins are held at V IL. Address pin A0 is held at V IL for the manu- facturer’s code, and held at V IH for the device code. The code is read on the eight data pins, O 0 –O7. Proper code access is only guaranteed at 25 §Ct o g5§C. ERASURE CHARACTERISTICS The erasure characteristics of the device are such that era- sure begins to occur when exposed to light with wave- lengths shorter than approximately 4000 Angstroms ( Ð). It should be noted that sunlight and certain types of fluores- cent lamps have wavelengths in the 3000 Ж4000Ð range. The recommended erasure procedure for the EPROM is ex- posure to short wave ultraviolet light which has a wave- length of 2537 Ð. The integrated dose (i.e., UV intensity c exposure time) for erasure should be a minimum of 15W-sec/cm2. The EPROM should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. Table III shows the minimum EPROM erasure time for various light intensities. An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increases as the square of the dis- tance from the lamp (if distance is doubled the erasure time increases by factor of 4). Lamps lose intensity as they age. When a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make cer- tain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, compo- nents, and even system designs have been erroneously suspected when incomplete erasure was the problem. SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, I CC, has three segments that are of interest to the system de- signer: the standby current level, the active current level, and the transient current peaks that are produced by volt- age transitions on input pins. The magnitude of these tran- sient current peaks is dependent of the output capacitance loading of the device. The associated V CC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 mF ceramic capacitor be used on every device between V CC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 mF bulk electrolytic capacitor should be used between V CC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The pur- pose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces.

The modes of operation of NM27C256 listed in Table I. A single 5V power supply is required in the read mode. All inputs are TTL levels except for V PP and A9 for device signature. TABLE I. Modes Selection Pins CE/PGM OE VPP VCC OutputsMode Read V IL VIL VCC 5.0V D OUT Output Disable X VIH VCC 5.0V High-Z(Note 1) Standby V IH XV CC 5.0V High-Z Programming V IL VIH 12.75V 6.25V D IN Program Verify V IH VIL 12.75V 6.25V D OUT Program Inhibit V IH VIH 12.75V 6.25V High-Z Note 1: X can be V IL or V IH. TABLE II. Manufacturer’s Identification Code Pins A0 A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex Manufacturer Code V IL 1 2 V 100011118 F Device Code V IH 1 2 V 000001000 4

Physical Dimensions inches (millimeters) UV Window Cavity Dual-In-Line CerDIP Package (Q) Order Number NM27C256QXXX 28-Lead Plastic One-Time-Programmable Dual-In-Line Package OrderNumber NM27C256NXXX

NM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM Physical Dimensions inches (millimeters) (Continued) 32-Lead Plastic Leaded Chip Carrier (PLCC) Order Number NM27C256VXXX LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd. 2900 Semiconductor Drive Livry-Gargan-Str. 10 Sumitomo Chemical 13th Floor, Straight Block, Rue Deputado Lacorda Franco Building 16 P.O. Box 58090 D-82256 F 4urstenfeldbruck Engineering Center Ocean Centre, 5 Canton Rd. 120-3A Business Park Drive Santa Clara, CA 95052-8090 Germany Bldg. 7F Tsimshatsui, Kowloon Sao Paulo-SP Monash Business Park Tel: 1(800) 272-9959 Tel: (81-41) 35-0 1-7-1, Nakase, Mihama-Ku Hong Kong Brazil 05418-000 Nottinghill, Melbourne TWX: (910) 339-9240 Telex: 527649 Chiba-City, Tel: (852) 2737-1600 Tel: (55-11) 212-5066 Victoria 3168 Australia Fax: (81-41) 35-1 Ciba Prefecture 261 Fax: (852) 2736-9960 Telex: 391-1131931 NSBR BR Tel: (3) 558-9999 Tel: (043) 299-2300 Fax: (55-11) 212-1181 Fax: (3) 558-9998 Fax: (043) 299-2500 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.