27C16

27C16 NSC | Alldatasheet

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Y Access time down to 450 ns Y Low CMOS power consumption Ð Active Power: 26.25 mW max Ð Standby Power: 0.53 mW max (98% savings) Y Performance compatible to NSC800 TM CMOS micro- processor Y Single 5V power supply Y Pin compatible to MM2716 and higher density EPROMs Y StaticÐno clocks required Y TTL compatible inputs/outputs Y TRI-STATEÉ output Y Windowed DIP Package Y Specifications guaranteed over full military temperature range ( b55§Ct o a125§C) Block Diagram TL/D/10329–1 Pin Names A0–A10 Addresses CE Chip Enable OE Output Enable O0 –O7 Outputs PGM Program NC No Connect TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. NS800TM are P 2CMOSTM trademarks of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/D/10329–2 Top View 27C32 27C64 27C128 27256 2732 2764 27128 27256 VCC VCC VCC PGM PGM A14 VCC NC A13 A13 A8 A8 A8 A8 A9 A9 A9 A9 A11 A11 A11 A11 OE /VPP OE OE OE A10 A10 A10 A10 CE CE CE CE O7 O7 O7 O7 O6 O6 O6 O6 O5 O5 O5 O5 O4 O4 O4 O4 O3 O3 O3 O3 Note: Socket compatible EPROM pin configurations are shown in the blocks adjacent to the 27C16 pins. Military Temp Range ( b55§Ct o a125§C) V CC e 5V g10% Parameter/Order Number Access Time (ns) 27C16Q450/883 450 27C16Q550/883 550

Absolute Maximum Ratings (Note 1) Temperature Under Bias b55§Ct o a125§C Storage Temperature b65§Ct o a125§C All Input Voltages with Respect to Ground a6.5V to b0.3V All Output Voltages with Respect to Ground (Note 11) V CC a0.3V to GND b0.3V VPP Supply Voltage with Respect to Ground during Programming a26.5V to b0.3V Power Dissipation 1.0W Lead Temperature (Soldering, 10 Seconds) 300 Operating Conditions (Note 9) Temperature Range (T case) b55§Ct o a125§C VCC Power Supply (Notes 2 and 3) 5V a10% VPP Power Supply (Note 3) V CC READ OPERATION Symbol Parameter Conditions Min Typ Max Units(Note 4) ILI Input Load Current V IN e VCC or V IL 10 mA ILO Output Leakage Current V OUT e VCC or V IL,C E e VIH 10 mA ICC1 VCC Current (Active) OE e CE e VIL,f e 1 MHz 23 0 m A(Note 3) TTL Inputs Inputs e VIH or V IL, I/O e 0m A ICC2 VCC Current (Active) OE e CE e VIL,f e 1 MHz 12 5 mA (Note 3) CMOS Inputs Inputs e VCC or GND, I/O e 0m A ICCSB1 VCC Current (Standby) CE e VIH 0.1 1 mATTL Inputs ICCSB2 VCC Current (Standby) CE e VCC 0.01 0.1 mACMOS Inputs VIL Input Low Voltage b0.1 0.8 V VIH Input High Voltage 2.2 V CC a 1V VOL1 Output Low Voltage I OL e 2.1 mA 0.45 V VOH1 Output High Voltage I OH eb 400 mA 2.4 V VOL2 Output Low Voltage I OL e 0 mA 0.1 V VOH2 Output High Voltage I OH e 0 mA 4.4 V 27C16 Symbol Parameter Conditions 450 550 Units Min Max Min Max tACC Address to Output Delay CE e OE e VIL 450 550 ns tCE CE to Output Delay OE e VIL 450 550 ns tOE OE to Output Delay CE e VIL 120 120 ns tDF OE High to Output Float CE e VIL 0 100 0 100 ns tOH Output Hold from Addresses, CE e OE e VIL (Note 5) CE or OE , Whichever 0 0 ns Occurred First

Capacitance TA ea 25§C, f e 1 MHz (Note 5) Symbol Parameter Conditions Typ Max Units CIN Input Capacitance V IN e 0V 4 10 pF COUT Output Capacitance V OUT e 0V 8 12 pF AC Test Conditions Output Load 1 TTL Gate and C L e 100 pF Input Rise and Fall Times s 20 ns Input Pulse Levels 0.8V to 2.2V Timing Measurement Reference Level Inputs 1V and 2V Outputs 0.8V and 2V AC Waveforms (Notes 2, 8, 9, 10) TL/D/10329–3 Note 1: Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: V CC must be applied simultaneously or before V PP and removed simultaneously or after V PP. Note 3: VPP may be connected to V CC except during programming. I CC1 s the sum of the I CC active and I PP read currents. Note 4: Typical values are for T A ea 25§C and nominal supply voltages. Note 5: This parameter is only sampled and is not 100% tested. Note 6: OE may be delayed up to t ACC b tOE after the falling edge of CE without impact on t ACC. Note 7: The t DF compare level is determined as follows: High to TRI-STATE, the measured V OH1 (DC) b 0.10V Low to TRI-STATE, the measured V OL1 (DC) a 0.10V Note 8: TRI-STATE may be attained using OE or CE . Note 9: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that a 0.1 mF ceramic capacitor be used on every device between V CC and GND. Note 10: The 27C16 requires one address transition after initial power-up to reset the outputs. Note 11: The outputs must be restricted to V CC a 0.3V to avoid latch-up and device damage.

PROGRAMMING CHARACTERISTICS (Note 1) DC Programming Characteristics (Notes2&3 ) (TA ea 25§C g5§C, V CC e 5V g10%, V PP e 25V g1V) Symbol Parameter Conditions Min Typ Max Units ILI Input Current (for Any Input) V IN e VCC or GND 10 mA IPP VPP Supply Current during CE /PGM e VIH 30 mA Programming Pulse ICC VCC Supply Current 10 mA VIL Input Low Level b0.1 0.8 V VIH Input High Level 2.0 V CC a1V AC Programming Characteristics (Notes2&3 ) (TA ea 25§C g5§C, V CC e 5V g10%, V PP e 25V g1V) Symbol Parameter Conditions Min Typ Max Units tAS Address Setup Time 2 ms tOES OE Setup Time 2 mS tDS Data Setup Time 2 ms tAH Address Hold Time 2 ms tOEH OE Hold Time 2 ms tDH Data Hold Time 2 ms tDF Output Enable to Output Float Delay CE /PGM e VIL 0 120 ns tOE Output Enable to Output Delay CE /PGM e VIL 100 ns tPW Program Pulse Width 45 50 55 ms tPRT Program Pulse Rise Time 5 ns tPFT Program Pulse Fall Time 5 ns AC Test Conditions VCC 5V g10% VPP 25V g1V Input Rise and Fall Times s20 ns Input Pulse Levels 0.8V to 2.2V Timing Measurement Reference Level Inputs 1V and 2V Outputs 0.8V and 2V

Programming Waveforms VPP e 25V g11V, V CC e 5V g5% (Note 3) TL/D/10329–4 Note: All times shown in parentheses are minimum and in ms unless otherwise specified. Note 1: National’s standard product warranty applies only to devices programmed to specifications described herein. Note 2: VCC must be applied simultaneously or before V PP and removed simultaneously or after V PP. The 27C16 must not be inserted into or removed from a board with V PP at 25V g1V to prevent damage to the device. Note 3: The maximum allowable voltage which may be applied to the V PP pin during programming is 26V. Care must be taken when switching the V PP supply to prevent overshoot exceeding this 26V maximum specification. A 0.1 mF capacitor is required across V PP,V CC to GND to suppress spurious voltage transients which may damage the device. Functional Description DEVICE OPERATION The six modes of operation of the 27C16 are listed in Table I. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are a 5V V CC and a VPP. The V PP power supply must be at 25V during the three programming modes, and must be at 5V in the other three modes. Read Mode The 27C16 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE ) is the power control and should be used for device selection. Output Enable (OE ) is the output control and should be used to gate data to the output pins, indepen- dent of device selection. Assuming that addresses are sta- ble, address access time (t ACC) is equal to the delay from CE to output (t CE). Data is available at the outputs t OE after the falling edge of OE , assuming that CE has been low and addresses have been stable for at least t ACC –tOE. The 27C16 requires one address transition after initial power-up to reset the outputs. Standby Mode The 27C16 has a standby mode which reduces the active power dissipation by 98%, from 26.25 mW to 0.53 mW. The 27C16 is placed in the standby mode by applying a TTL high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Output OR-Tying Because 27C16s are usually used in larger memory arrays, National has provided a 2-line control function that accom- modates this use of multiple memory connections. The 2-line control function allows for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recom- mended that CE (pin 18) be decoded and used as the pri- mary device selecting function, while OE (pin 20) be made a common connection to all devices in the array and connect- ed to the READ line from the system control bus. This as- sures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. Programming CAUTION: Exceeding 26.5V on pin 21 (V PP) will damage the 27C16. Initially, and after each erasure, all bits of the 27C16 are in the ‘‘1’’ state. Data is introduced by selectively program- ming ‘‘0s’’ into the desired bit locations. Although only ‘‘0s’’ will be programmed, both ‘‘1s’’ and ‘‘0s’’ can be presented in the data word. The only way to change a ‘‘0’’ to a ‘‘1’’ is by ultraviolet light erasure. The 27C16 is in the programming mode when the V PP pow- er supply is at 25V and OE is at V IH. It is required that a 0.1 mF capacitor be placed across V PP,V CC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, a 50 ms, active high, TTL program pulse is applied to the CE /PGM input. A pro- gram pulse must be applied at each address location to be programmed. You can program any location at any timeÐ either individually, sequentially, or at random. The program pulse has a maximum width of 55 ms. The 27C16 must not be programmed with a DC signal applied to the CE /PGM input.

Functional Description (Continued) Programming multiple 27C16s in parallel with the same data can be easily accomplished due to the simplicity of the pro- gramming requirements. Like inputs of the paralleled 27C16s may be connected together when they are pro- grammed with the same data. A high level TTL pulse ap- plied to the CE /PGM input programs the paralleled 27C16s. Program Inhibit Programming multiple 27C16s in parallel with different data is also easily accomplished. Except for CE /PGM, all like inputs (including OE ) of the parallel 27C16s may be com- mon. A TTL level program pulse applied to an 27C16’s CE / PGM input with V PP at 25V will program that 27C16. A low level CE /PGM input inhibits the other 27C16 from being programmed. Program Verify A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with V PP at 25V. V PP must be at VCC, except during programming and program verify. ERASURE CHARACTERISTICS The erasure characteristics of the 27C16 are such that era- sure begins to occur when exposed to light with wave- lengths shorter than approximately 4000 Angstroms ( Ð). It should be noted that sunlight and certain types of fluores- cent lamps have wavelengths in the 3000 Ж4000Ð range. Opaque labels should be placed over the 27C16 window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents. The recommended erasure procedure for the 27C16 is ex- posure to short wave ultraviolet light which has a wave- length of 2537 Angstroms ( Ð). The integrated dose (i.e., UV intensity c exposure time) for erasure should be a minimum of 15W-sec/cm 2. The erasure time with this dosage is ap- proximately 21 minutes using an ultraviolet lamp with a 12,000 mW/cm2 power rating. The 27C16 should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. Note: The 27C16-550 may take up to 60 minutes for complete erasure to occur. An erasure system should be calibrated periodically. The distance from lamp to unit should be maintained at one inch. The erasure time increases as the square of the distance. (If distance is doubled the erasure time increases by a factor of 4.) Lamps lose intensity as they age. When a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when in- complete erasure was the problem. SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, I CC, has three segments that are of interest to the system de- signerÐthe standby current level, the active current level, and the transient current peaks that are produced on the falling and rising edges of chip enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated transient voltage peaks can be suppressed by properly selected de- coupling capacitors. It is recommended that a 0.1 mF ce- ramic capacitor be used on every device between V CC and GND. This should be a high frequency capacitor of low in- herent inductance. In addition, a 4.7 mF bulk electrolytic ca- pacitor should be used between V CC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The pur- pose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces. TABLE I. Mode Selection Pins CE /PGM OE VP VCC Outputs Read V IL VIL VCC 5D OUT Standby V IH Don’t Care V CC 5 Hi-Z Program Pulsed V IL to V IH VIH 25 5 D IN Program Verify V IL VIL 25 5 D OUT Program Inhibit V IL VIH 25 5 Hi-Z Output Disable X V IH VCC 5 Hi-Z

27C16 16,384-Bit (2048 x 8) UV Erasable CMOS PROM Military Qualified Physical Dimensions inches (millimeters) Lit. Ý 114700

24 Lead Ceramic Dual-In-Line Package (J)

Order Number 27C16Q450/883 or 27C16Q550/883 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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