27C1028 | DigiCamel IC Datasheet

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MBM27C1028-15 FUJITSU | Alldatasheet

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mM CMOS 1,048,576 BIT MBM27C1028-15 FUJITSU BO Bs SN ea aN) MBM2701028-20 4 -25 SI ONLY MEMORY IATA CMOS 1,048,576 BIT UV ERASABLE READ ONLY sept on te MEMORY (EPROM) ‘The Fujitsu MBM27C1028 EPROM Is a high speed read-only static memory that is UV-erasable and reprogrammable. The devices contains 1,048,576 programma- ble or reprogrammable bits organized In a 131,072-byte/8 bit or 65,536-word/16-bit format. The M&M27C1026 has a mulitplexed address and data pin which permits the device to reduce the number of pin-count for portable system where compact circuit layout Ie required. The MBM27C1028 can thon be housed in a 26-pin DIP or a 32-pad LCC with a transparent lid: when the id Is properly exposed to an ultraviolet light source, a previously programmed bit pattern is erased in approximately 15-to-21 minutes. A new bit pattern can then be written into memory. ‘The MBM27C1028 EPROM Is fabricated using CMOS double polysilicon gate technology with stacked single transistor gate cols. The MBM27C1028 Is an ‘excellent choice for system development work and In other appications where program changes are frequently necessary. Once programmed, the device requires only a single +5V power supply; the current requirements are exceptionally low In both the active and standby modes of operation. CERAMIC PACKAGE © 65,536 word/16 bit organization with on chip decoding DIP-28C-CO1 16-bit or 8-bit organization capabilty using a control signal © On-chip latches for address Easy and simple memory expansion via OE pin © Thvee-state output for word-OR capabilty Lco-320-F01 See P @ TTL-compatibie inputs/outputs ee joe Page 11 # Fast access time: MBM27C 1028-15 = 150ns (max.) MBM27C 1028-20 = 200ns (rmax.) MBM27C 1028-25 = 250ns (max.) @ Single +5V(10%) power supply with low current drain: PIN ASSIGNMENT ‘Active operation = 30mA {max} Standby operation = 0.imA (max) @ Programming voltage: +12.5V(+0.3V) ‘© Programming capability with Quick Pro™ algorithm vee B veo, '* No interface to be required to MBL8086 and MBLBO1E8 eds 2h pe ‘© JEDEC approved pin assignments eqs ssp) AE © Standard package: nos 24 NC 28-pin Ceramic (Cerdip ) DIP Package : suffix = Z A00g 6 zap) 16 32-pad Frit seal LCC Package : suffix = TV peat: i 2B tor dood of abi ABSOLUTE MAXIMUM RATINGS (see NOTE; soe t0 oh eee sorogn ep Ab1a [ating ['symbot | vatue unit | noo 2 7B aos. Supply Voktage with Respect to GNO| Vec | 0.6 047.0 Soda spa VPP Voltage with Respect to GNO 0.6 to +14.0 All Inputs, I/Os Voltage with Vn Yoo | ~ + v LCC : See page 11 Respect to GNO- i Yu | -0.8 to Vocs0.3 pag NOTE: Permanent device damage may occur if the above Absolute adviced that cermel precautions be then to Maximum Ratings are exceeded. Functional operation should be RR Festricted to the conditions as detailed f the operational sections of | Cans’ ‘at0e wotaaes fo ths ign imecarce this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device relabilty Quick Pro TM is a trademark of FUJITSU LIMITED ‘Copyright © 1988 by FUJITSU LIMITED. 4-97

Fig. 1 — MBM27C1028 BLOCK DIAGRAM co CE Pam ROW ADDRESS decobeR OUTPUT ENABLE & ‘COLUMN a Xroza Chip ENABLE AODRESS t— cIRCUIT DECODER }—1 1.048.578 ett MATRIX ourput coLunne Row OIRECTION Aooness aooness CONTROL BUFFER BUFFER vo coLuMN Gare ve ate bo ors DATA INPUT BUFFER & PROGRAM CONTROL |__| ~~ Vee || a ane ae CAPACITANCE ¢r,- 25°c, ¢ = mz) Parameter Unit [min [tye [max | [ now easacrarcevu-ovi | ow | | | |r| A 4-98

MBM27C1028-15 _BIINIDHIEIR MBM27C1028-20 FUJITSU MBM27C1028-25 HHH NININN Pad No Ne 2.5.24 Output enable. When OE and CE are active low and the PGM strove Is active High; all proper output fines (Either “ADO to AD1S" or “ADO to AD?" are enabiod cE Chip enable. When active low, the device Is enabled for data read and programming operations. ‘Ado to ADis 6-13,15-22 ‘Address/Data. When OE Is High, all ADs work as address Input line. 7-11,13-15.18-25)| When Low, all ADs work as data output line. oe 23 ‘Address line {MSB) 27) ALE ‘Address latch enable. When CE is Low and ALE Is High, the address from input butter Is transtfer to address decoder by falling edge of ALE. are Bus high enable. When BHE Is Low in conjection with ADO, a word/16-bit data le available. When BHE is High, a byte/8-bit data is avairablo 27 Program Control/Output Enable. When active Low, programming data from the input buffer is written Into a species at memory provided the following conditions (31) are mot: _VPP=12,5V; VCC-6V, CE-ALE-Low; OE-High, [eae ——Fe name] dq _[aoy=adrd ase [ace | ame | ce | ot [Faw | vec | ve [on] srwwer [ware] wove [| x x [m [x |x [w [ow fon “T= PRET [> [or] mao [oor loom | x [wf fu fu | m | © [ow [ov] PRET To for] ‘OUTPUT DISABLE vit vit m sv | sv | ov |_ourrurosasce [wore] rene | x | [x [me Peery [room foe fm fe fee fm Pome | ofa ov] A A Note “1: X canbe either Vi or Vit *2: See below fesse oat money ds [aman [ rovwaa| Grable for tho wor and upper vyte-ottne | A02 | BHE | Ado to aoy | A08 to Adis ‘aig. rospotvery_But whan 90% Abo and byte Satay iower byte bus, ADoto AO | M< | ve [ Otoor | Wenz byte data to lower byte bus, ADo to AD7; ve al Do to 07 Hah. Sree 2K weras teen me [eT vn [bate bis ghz] organized 128K words by 8 bit 4-99

MBM27C 1028-15 _ III) MBM27C1028-20 FUJITSU MBM27C1028-25 __IVHNMIIGIOINIME AC CHARACTERISTICS (Recommended operating conditions unless otherwise noted) a [mewarccexe | woncnane | ones | [ns | re [ve [va oe etn mn oe ote [ese rinn | te TP Pet fet fe [| (CE=OE=Vu . PGM=Vin ) [REmowo me ceva fe te] { || | f=, | |e] [ener tee f@ | | [mt | fom] fo] [ssswmnoern tm tat | ts] | =| | |e [meee te tat | ft fT f= {| [el [Benwrm m tat | t=] | l=] | del [aes tow to | | fol { fo] | [nl [aewona vac Famven | tee te [mle] [mle] |m|n| [Faw omn ver Gv | tw | | tm fo] [nfo] fo le] [owen onnewononren [to [et Lelel [el>| [x [| NOTE: ** GEIPGM) may be delayed up to tacc-toe (team) after the falling edge of ALE *? tor is specified from CE. OE or PGM or ALE. whichever occurs first. TYPICAL READ WAVEFORM | “ae ae Be [a a 4-101

TELM (4BM27C1028-15 iinet MBMa7¢1038-95 eo eer ACTS if 4-102

MBM27C1028-15 ‘INH MBM27C1028-20 FUsITsu MBM27C1028-25 _ FIIININAIIA PROGRAMMING When the MBM27C1028 Is shipped the factory, all memory cells. to the FGM. Also, a 0.1j1F capacitor must be connected (1,048,576 bits) are set to High state (logic 1). During the between Vop and ground to prevent excessive voltage programming procedure, affected bit cells are set to the Low transients. Neglecting either of these precautions ray escee state (logic 0) device failure. The MBM27C1028 is programmed with a fast programming algorithm design by Fujitsu called Quick Pro™. When ERASING 412.5V(40.3V) is applied to Vpp, +6V(+0.25V) Is applied to Veo. TE = Vit, PGM and DE = Viv, the programming mode is in order to clear all memory cells of programmed contents, the initiated. Next, the proper address in conjection with BHE are. MBM27C1028 must be exposed to an ultraviolet light source. input by faling edge of ALE . and the data pattern is applied to To completely erase the memory (restore ali cells to a logic 1 the Input butter (Figuret}, When both address (and BHE) and state). a dosage of 15Wsec/cm? Is required. The required data are stable, a 0,5ms negative pulse is applied to the Xposure can be obtained by using a UV-lamp with a “PGM . Upon verification of written data read out by OE an Wavelength of 253.7nm with an Intensity of 12mWiem2 over puise (three times the intial pulse width times the number Remove all fiters from the iamp and clean the transparent lid of of pulses used to accomplish a write) should be appiled to the MBM27C102B with a non-abrasive cleaner. Hold the complate the programming of one byte. Refer to the | MBM27C1028 approximately one inch from the light source for PROGRAMMING FLOWCHART that follows for step-by-step _15-to-21 mimute. (Note. The MBM27C1028 and other similar proprarmming pros echree dovices can bo erased by ight sources with longer wavelength however, the erasing time is much groater. Nonetheless, Caution exposure to fluorescents or sunlght wil severely degrade and eventually erase the memory. When used ina. Ighted ‘The width of one programming pulse must not exceed 40ms; environment. it Is recommended that the transparent window thus, a continuous TTL low-level voltage should not be applied be covered with an opaque label.) 4-103

(GERI) MBM27C1028-25 PROGRAMMING / ERASING INFORMATION (Cont'd) PROGRAMMING WAVEFORM veo ya wes un OR tew toow tas tar tos ton tos ton on Vin/Vor = se oe CU {oman > * evo. — Caceres $f caren ‘uy, ni cs : v= tec errs 4-104

MBM27C1028-15 _ MINIM MBM27C1028-20 FUJITSU MBM27C1028-25 _IMIMEIINONAN DC CHARACTERISTICS purine pRoGRAMMING (Ta= 25°C+5°C, Vec=6V20.25V, Vpp =12.5V40.3V) ee Ea a [resins a [resis Pe] Peseeme ee [ es sew oven Beveerso tw P| [we seoveweniGevgy es | | [ie aor ewren SEY ore) | we | me | [i see ere) ves Pe | [issn we acting vee [_cuwueriontove Cioweaouar | vw Tee [OT Tv | AC CHARACTERISTICS purine procRaMMING {Ta= 25°C25°C, Voc=6V£0.25V, Vpp=12,5V40.3V} vost [min [tye [ae [ VecSetwe tine tes Te Ts | [ veo sew tine ts Te TT ns [ Gesewptme tees Te Ps [nasew nip ne tw | Aceress ho tie Tt Ps | Re prechaaetine | tee | TT ns [ AE towHogtime | te Te Ts PS [ daeroatme tw Te gs | [OE setup time oes eas | SE 10 output vate te 00s | | GEroouutron ST tee OT | Preoramming Puse wan tow | ers | oso | oses [me | [over Programming Puse Number Tn Tt Ts tenes 4-105

CMA =~ MBM27C1028-25 Fig. 3 — PROGRAMMING CHART Voc=6V + 0.25V VPP =12.5V Vino av cosy tew=0.5ms + 5% TopN=1.5xNms + 5% ADDR=FIRST LOCATION _4 | FARES one Oe Tene ous 4-106

DE_NC_vPP_Nc_vco FGM Bre POU OUy eps 7 aC) ne Pde ze CJ ne noo 7 27] aw wos Fs 2s] ne aor fod 2s (J ans noo [5 10 2] 07 aoe [1 23] 0% ne [J iz 22] As aor fF) 19 2) (J aor 1s we a7 we 1 20 LCC-32C-FO1 CI [I a O LU U ] AD2 ADITGNO NC ADE ADIZ ADS 32-PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER (Case No.: LCC-32C-F01) a6019.141T YP sp. No. 1 i // INDEX | _corswo.ssytve é \\) | roorganer C/U UU) ooo i & = | = = = q +010 ma] cy a 2951749) 550.08 rooe.2011ve | ne DIA REF “025 13.97°223) css 4 050: 008 ore 025:,008 E Fyazreois) “Sye"® | @seosoTve}_P je Jj Tp qGoiot | i J \\ cosoworrve XO OO ONg/ i 450 : L908 1 oestiairye RT | aossusarrye (9943925) | [oon.2artve 3007.61" (Torsivaurye [2 }:13013.30MAx TYP “Shape of PIN NO.1 INDEX. Subject to change without novice umension mn nches eee PULITSU LimiTeD c320175 2c dnd tonlimeters) 4-107

MRE! 48M2701028-15 FUJITSU —MBM27C1028-20 UGE M4BM27C1028-25 28-PIN CERAMIC DUAL IN-LINE PACKAGE (Case No.: DIP-28C-C01) Lig as? nee ee o't018 Beer S77 tor | (14.66°0-48) 3501889) DIA, 70.18 600(15.24)TYP. wy 610" D0 . (1549°238) | 4 | | niniieininiaiaiabeeeiaied }_ oro! 204 1450" 580(a6 9°27) oe Sap t0012 samax (0.2529) Bossoeimax ——} 134s o14 | jea0te36 (2,540.25) 11.3220.25) TYP ek org" 208 ©1988 FUsITSU LIMITED 026007S.3¢ 4-108

Product Information

27C1028 specifications and overview.

Summary

CMOS 1048576 BIT UV ERASABLE READ ONLY MEMORY

Description

CMOS 1048576 BIT UV ERASABLE READ ONLY MEMORY

Source title 27C1028 Datasheet(PDF) - fujitsu semiconductor

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