DS2762 MAXIM | Alldatasheet
Document overview
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Technical content
1 of 25 REV: 111703 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS2762 high-precision Li+ battery monitor is a data-acquisition, information-storage, and safety- protection device tailored for cost-sensitive battery pack applications. This low-power device integrates precise temperature, voltage, and current measurement, nonvolatile (NV) data storage, and Li+ protection into the small footprint of either a TSSOP package or flip-chip package. The DS2762 is a key component in applications including remaining capacity estimation, safety monitoring, and battery- specific data storage. PIN CONFIGURATIONS
FEATURES
/g167 Li+ Safety Circuit Overvoltage Protection Overcurrent/Short-Circuit Protection Undervoltage Protection /g167 Host Alerted When Accumulated Current or Temperature Exceeds User-Selectable Limits /g167 0V Battery Recovery Charge /g167 Available in Two Configurations: Internal 25m/g87 Sense Resistor External User-Selectable Sense Resistor /g167 Current Measurement 12-Bit Bidirectional Measurement Internal Sense Resistor Configuration: 0.625mA LSB and ±1.9A Dynamic Range External Sense Resistor Configuration: 15.625/g109V LSB and ±64mV Dynamic Range /g167 Current Accumulation: Internal Sense Resistor: 0.25mAhr LSB External Sense Resistor: 6.25/g109Vhr LSB /g167 Voltage Measurement with 4.88mV Resolution /g167 Temperature Measurement Using Integrated Sensor with 0.125°C Resolution /g167 System Power Management and Control Feature Support /g167 32 Bytes of Lockable EEPROM /g167 16 Bytes of General-Purpose SRAM /g167 Dallas 1-Wire ® Interface with Unique 64-Bit Device Address /g167 Low-Power Consumption: Active Current: 60/g109A typ, 90/g109A max Sleep Current: 1/g109A typ, 2/g109A max
APPLICATIONS
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS2762BE -20°C to +70°C 16 TSSOP Selector Guide appears at end of data sheet, for additional options. DS2762 High-Precision Li+ Battery Monitor With Alerts www.maxim-ic.com TOP VIEW CC VIN VDD PIO VSS VSS VSS PS IS1 TSSOP IS2 SNS SNS SNS DQ PLS D C 1-Wire is registered trademark of Dallas Semiconductor. FLIP CHIP (top view – bumps on bottom) PLS DC DQ CC IS2 VIN IS1 VDD PIO PS SNS VSS 1 2 3 4 A B C D E F SNS PROBE VSS PROBE
DS2762 High-Precision Li+ Battery Monitor With Alerts 2 of 25 ABSOLUTE MAXIMUM RATINGS Voltage Range on PLS and CC Pin, Relative to VSS -0.3V to +18V Voltage Range on PIO Pin, Relative to VSS -0.3V to +12V Voltage Range on Any Other Pin, Relative to VSS -0.3V to +6V Continuous Internal Sense Resistor Current /g1772.5A Pulsed Internal Sense Resistor Current /g17750A for <100µs/s, <1000 pulses Operating Temperature Range -40°C to +85°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JEDEC J-STD-020A Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device. RECOMMENDED DC OPERATING CONDITIONS (2.5V /g163 VDD /g163 5.5V, TA = -20°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V DD (Note 1) 2.5 5.5 V Data Pin DQ (Note 1) -0.3 +5.5 V DC ELECTRICAL CHARACTERISTICS (2.5V /g163 VDD /g163 5.5V, TA = -20°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Active Current I ACTIVE DQ = VDD, normal operation 60 90 /g109A Sleep Mode Current I SLEEP DQ = 0V, no activity, PS floating 12 /g109A Input Logic High: DQ, PIO V IH (Note 1) 1.5 V Input Logic High: PS VIH (Note 1) V DD - 0.2V V Input Logic Low: DQ, PIO V IL (Note 1) 0.4 V Input Logic Low: PS VIL (Note 1) 0.2 V Output Logic High: CC VOH IOH = -0.1mA (Note 1) V PLS - 0.4V V Output Logic High: DC VOH IOH = -0.1mA (Note 1) V DD - 0.4V V Output Logic Low: CC, DC VOL IOL = 0.1mA (Note 1) 0.4 V Output Logic Low: DQ, PIO V OL IOL = 4mA (Note 1) 0.4 V DQ Pulldown Current I PD 1 /g109A Input Resistance: VIN RIN 5 M/g87 Internal Current-Sense Resistor R SNS +25°C 20 25 30 m/g87 DQ Low to Sleep time t SLEEP 2.1 s
DS2762 High-Precision Li+ Battery Monitor With Alerts 3 of 25 ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUITRY (2.5V /g163 VDD /g163 5.5V, TA = 0°C to +50°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.325 4.350 4.375 Overvoltage Detect V OV (Notes 1, 2) 4.250 4.275 4.300 V Charge Enable V CE (Note 1) 4.10 4.15 4.20 V Undervoltage Detect V UV (Note 1) 2.5 2.6 2.7 V Overcurrent Detect I OC (Note 3) 1.8 1.9 2.0 A Overcurrent Detect V OC (Note 1, 4) 45 47.5 50 mV Short-Circuit Detect I SC (Note 3) 5.0 8.0 11 A Short-Circuit Detect V SC (Note 1) 150 200 250 mV Overvoltage Delay t OVD 0.8 1 1.2 s Undervoltage Delay t UVD 90 100 110 ms Overcurrent Delay t OCD 51 0 2 0 m s Short-Circuit Delay t SCD 160 200 240 /g109s Test Threshold V TP 0.5 1.0 1.5 V Test Current I TST 10 20 40 /g109A Recovery Charge Current I RC (Note 5) 0.5 1 2 mA
DS2762 High-Precision Li+ Battery Monitor With Alerts 4 of 25 ELECTRICAL CHARACTERISTICS: TEMPERATURE, VOLTAGE, CURRENT (2.5V /g163 VDD /g163 5.5V, TA = -20°C to +50°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Temperature Resolution T LSB 0.125 /g176C Temperature Full-Scale Magnitude T FS 127 /g176C Temperature Error T ERR (Note 6) /g1773 /g176C Voltage Resolution V LSB 4.88 mV Voltage Full-Scale Magnitude V FS 4.75 V Voltage Offset Error V OERR (Note 7) 1 LSB Voltage Gain Error V GERR 5% (Note 3) 0.625 mA Current Resolution I LSB (Note 4) 15.625 /g109V (Notes 3, 4) 1.9 2.56 A Current Full-Scale Magnitude I FS (Note 8) 64 mV Current Offset Error I OERR (Note 9) 1 LSB (Notes 3, 10) 3 Current Gain Error I GERR (Note 4) 1 (Note 3) 0.25 mAhr Accumulated Current Resolution q CA (Note 4) 6.25 µVhr Current Sampling Frequency f SAMP 1456 Hz tERR1 (Note 11) /g1771 /g1773 % Internal Timebase Accuracy tERR2 (Note 11) /g1776.5 % EEPROM RELIABILITY SPECIFICATION (2.5V /g163 VDD /g163 5.5V, TA = -20/g176C to +70/g176C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Copy to EEPROM Time t EEC 21 0 m s EEPROM Copy Endurance N EEC (Note 12) 25,000 cycles
DS2762 High-Precision Li+ Battery Monitor With Alerts 5 of 25 ELECTRICAL CHARACTERISTICS: 1-WIRE INTERFACE (2.5V /g163 VDD /g163 5.5V, TA = -20/g176C to +70/g176C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Time Slot t SLOT 60 120 /g109s Recovery Time t REC 1 /g109s Write 0 Low Time t LOW0 60 120 /g109s Write 1 Low Time t LOW1 11 5 /g109s Read Data Valid t RDV 15 /g109s Reset Time High t RSTH 480 /g109s Reset Time Low t RSTL 480 960 /g109s Presence Detect High t PDH 15 60 /g109s Presence Detect Low t PDL 60 240 /g109s SWAP Timing Pulse Width t SWL 0.2 120 /g109s SWAP Timing Pulse Falling Edge to DC Release tSWOFF (Note 13) 0 1 /g109s SWAP Timing Pulse Rising Edge to DC Engage tSWON (Note 13) 0 1 /g109s DQ Capacitance C DQ 60 pF Note 1: All voltages are referenced to VSS. Note 2: See the Selector Guide section to determine the corresponding part number for each VOV value. Note 3: Internal current-sense resistor configuration. Note 4: External current-sense resistor configuration. Note 5: Test conditions are PLS = 4.1V, VDD = 2.5V. Maximum current for conditions of PLS = 15V, VDD = 0V is 10mA. Note 6: Self-heating due to output pin loading and sense resistor power dissipation can alter the reading from ambient conditions. Note 7: Voltage offset measurement is with respect to VOV at +25°C. Note 8: The current register supports measurement magnitudes up to 2.56A using the internal sense resistor option and 64mV with the external resistor option. Compensation of the internal sense resistor value for process and temperature variation can reduce the maximum reportable magnitude to 1.9A. Note 9: Current offset error null to ±1LSB typically requires 3.5s in-system calibration by user. Note 10: Current gain error specification applies to gain error in converting the voltage difference at IS1 and IS2, and excludes any error remaining after the DS2762 compensates for the internal sense resistor’s temperature coefficient of 3700ppm//g176C to an accuracy of /g177500ppm//g176C. The DS2762 does not compensate for external sense resistor characteristics, and any error terms arising from the use of an external sense resistor should be taken into account when calculating total current measurement error. Note 11: Typical value for tERR1 is specified at 3.6V and +25/g176C, max value is specified for 0°C to +50°C. Max value for tERR2 is specified for -20°C to +70°C. Note 12: Four-year data retention at +70/g176C. Note 13: Typical load capacitance on DC and CC is 1000pF.
DS2762 High-Precision Li+ Battery Monitor With Alerts 6 of 25 PIN DESCRIPTION PIN TSSOP FLIP CHIP SYMBOL FUNCTION 1C 1 CC Charge Protection Control Output. Controls an external P-channel high-side charge protection FET. 2B 1 P L S Battery Pack Positive Terminal Input. The DS2762 monitors the pack plus terminal through PLS to detect overcurrent and overload conditions, as well as the presence of a charge source. Additionally, a charge path to recover a deeply depleted cell is provided from PLS to V DD. In sleep mode (with SWEN = 0), any capacitance or voltage source connected to PLS is discharged internally to VSS through 200µA (nominal) to assure reliable detection of a valid charge source. For details of other internal connections to PLS and associated conditions see the Li+ Protection Circuitry section. 3B 2 DC Discharge Protection Control Output. Controls an external P-channel high-side discharge protection FET. 4, 5, 6 A3 SNS Sense Resistor Connection. Connect to the negative terminal of the battery pack. In the internal sense resistor configuration, the sense resistor is connected between VSS and SNS. 7B 4 D Q Data Input/Out. 1-Wire data line. Open-drain output driver. Connect this pin to the DATA terminal of the battery pack. Pin has an internal 1/g109A pulldown for sensing disconnection. 8C 4 I S 2 Current-Sense Input. This pin is internally connected to SNS through a 4.7k/g87 resistor. 9D 4 I S 1 Current-Sense Input. This pin is internally connected to VSS through a 4.7k/g87 resistor. Connect a 0.1/g109F capacitor between IS1 and IS2 to complete a lowpass input filter. 10 E4 PS Power Switch Sense Input. The device wakes up from sleep mode when it senses the closure of a switch to VSS on this pin. Pin has an internal 1/g109A pullup to VDD. 11, 12, 13 F3 VSS Device Ground. Connect directly to the negative terminal of the Li+ cell. For the external sense resistor configuration, connect the sense resistor between VSS and SNS.
14 E2 PIO
Programmable I/O Pin. Can be configured to be used to control and monitor user- defined external circuitry or as an interrupt output to alert the host when preset current accumulator or temperature limits are exceeded. Open drain to VSS.
15 E1 V DD
Power-Supply Input. Connect to the positive terminal of the Li+ cell through a decoupling network.
16 D1 V IN
Voltage Sense Input. The voltage of the Li+ cell is monitored through this input pin. This pin has a weak pullup to VDD. —C 2 SNS Probe Do not connect. —D 2 VSS Probe Do not connect.
Figure 1. Block Diagram capacity estimation, safety monitoring, and battery-specific data storage. net address that allows it to be individually addressed by the host system, supporting multibattery operation. monitoring. Temperature is measured using an on-chip sensor, eliminating the need for a separate thermistor. may also be used to alert the host when preset accumulated current or temperature limits are exceeded. security for unchanging battery data. SRAM provides inexpensive storage for temporary data.
Figure 2. Application Example
IN drops below undervoltage threshold VUV for tUVD (cell depletion). /g167 The pack is disabled through the issuance of a SWAP command (SWEN bit = 1). PS pin is pulled low (power switch). /g167 The voltage on PLS becomes greater than the voltage on V IN (charger connection) with the SWEN bit set to 0. /g167 The pack is enabled through the issuance of a SWAP command (SWEN bit = 1). The DS2762 defaults to active mode when power is first applied. Table 1. Li+ Protection Conditions and DS2762 Responses VIS = VIS1 - VIS2. Logic high = VPLS for CC and VDD for DC. All voltages are with respect to VSS. ISNS references current delivered from pin SNS. direction and ISNS < -IOC for discharge direction. Note 3: With test current ITST flowing from PLS to VSS (pulldown on PLS). Note 4: With test current ITST flowing from VDD to PLS (pullup on PLS). IN < VCE if a discharge current of -80mA (VIS ≤ -2mV) or less is detected.
FET and pull out of sleep mode. offending charge current source. VDD to PLS to pull PLS up to detect the removal of the offending low-impedance load. protection register. The discharge current path is not re-established until the voltage on PLS rises above V DD - VTP. Figure 3. Li+ Protection Circuitry Example Waveforms Summary. All of the protection conditions described above are ORed together to affect the CC and DC outputs. FILTERED IS1 AND IS2 PINS. THE ACTUAL SHORT-CIRCUIT DETECT CONDITION IS VSNS > VSC.
To use the PIO pin as described in this section, the IE bit (bit 2) of the Status Register must be set to 0. is low for more than 2s, regardless of the state of the PMOD bit. The host may then poll the DS2762 to determine which threshold has been met or exceeded. Figure 9. Interrupt Threshold Register Formats
DS2762 High-Precision Li+ Battery Monitor With Alerts 14 of 25 Temperature Interrupt High Threshold Address 84 S2 6 25 24 23 22 21 20 MSb LSb Units: 1.0°C Temperature Alarm Low Threshold Address 85 S2 6 25 24 23 22 21 20 MSb LSb Units: 1.0°C POWER SWITCH INPUT The DS2762 provides a power control function that uses the discharge protection FET to gate battery power to the system. The PS pin, internally pulled to V DD through a 1 /g109A current source, is continuously monitored for a low- impedance connection to V SS. If the DS2762 is in sleep mode, the detection of a low on the PS pin causes the device to transition into active mode, turning on the discharge FET. If the DS2762 is already in active mode, activity on PS has no effect other than the latching of its logic low level in the PS bit in the special feature register. The reading of a 0 in the PS bit should be immediately followed by writing a 1 to the PS bit to ensure that a subsequent low forced on the PS pin is latched into the PS bit. MEMORY The DS2762 has a 256-byte linear address space with registers for instrumentation, status, and control in the lower 32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining address space. All EEPROM memory is general purpose except addresses 30h, 31h, and 33h, which should be written with the default values for the protection register, status register, and current offset register, respectively. All SRAM memory is general purpose. When the MSB of any two-byte register is read, both the MSB and LSB are latched and held for the duration of the read data command to prevent updates during the read and ensure synchronization between the two register bytes. For consistent results, always read the MSB and the LSB of a two-byte register during the same read data command sequence. EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow the data to be verified by the host system before being copied to EEPROM. All reads and writes to/from EEPROM memory actually access the shadow RAM. In unlocked EEPROM blocks, the write data command updates shadow RAM. In locked EEPROM blocks, the write data command is ignored. The copy data command copies the contents of shadow RAM to EEPROM in an unlocked block of EEPROM but has no effect on locked blocks. The recall-data command copies the contents of a block of EEPROM to shadow RAM regardless of whether the block is locked or not.
Table 2. Memory Map
00 Protection Register R/W
01 Status Register R
07 EEPROM Register R/W
08 Special Feature Register R/W
10 Accumulated Current Register MSB R/W
11 Accumulated Current Register LSB R/W
18 Temperature Register MSB R
19 Temperature Register LSB R
80 SRAM (Optional Accumulated Current Interrupt
81 SRAM (Optional Accumulated Current Interrupt
82 SRAM (Optional Accumulated Current Interrupt
83 SRAM (Optional Accumulated Current Interrupt
84 SRAM (Optional Temperature Interrupt High
85 SRAM (Optional Temperature Interrupt Low
- Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.
protection register. The function of each bit is described in detail in the following paragraphs. Figure 10. Protection Register Format
OV— Overvoltage Flag. When set to 1, this bit indicates the battery pack has experienced an overvoltage condition. This bit must be reset by the host system. condition. This bit must be reset by the host system. direction overcurrent condition. This bit must be reset by the host system. direction overcurrent condition. This bit must be reset by the host system. CC— CC Pin Mirror. This read-only bit mirrors the state of the CC output pin. DC— DC Pin Mirror. This read-only bit mirrors the state of the DC output pin. Figure 11. Status Register Format of address 31h. The factory default is 0. address 31h. The factory default is 0. read-only. The factory default is 0. value should be set in bit 2 of address 31h. The factory default is 0.
effectively terminating the transaction. Figure 16. 1-Wire Bus Interface Circuitry The sections that follow describe each of these steps in detail. more details, see the 1-Wire Signaling section.
DS2762 High-Precision Li+ Battery Monitor With Alerts 20 of 25 NET ADDRESS COMMANDS Once the bus master has detected the presence of one or more slaves, it can issue one of the net address commands described in the following paragraphs. The name of each ROM command is followed by the 8-bit opcode for that command in square brackets. Figure 17 presents a transaction flowchart of the net address commands. Read Net Address [33h or 39h]. This command allows the bus master to read the DS2762’s 1-Wire net address. This command can only be used if there is a single slave on the bus. If more than one slave is present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The RNAOP bit in the status register selects the opcode for this command, with RNAOP = 0 indicating 33h, and RNAOP = 1 indicating 39h. Match Net Address [55h]. This command allows the bus master to specifically address one DS2762 on the 1-Wire bus. Only the addressed DS2762 responds to any subsequent function command. All other slave devices ignore the function command and wait for a reset pulse. This command can be used with one or more slave devices on the bus. Skip Net Address [CCh]. This command saves time when there is only one DS2762 on the bus by allowing the bus master to issue a function command without specifying the address of the slave. If more than one slave device is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at the same time. Search Net Address [F0h]. This command allows the bus master to use a process of elimination to identify the 1-Wire net addresses of all slave devices on the bus. The search process involves the repetition of a simple three- step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple three-step routine on each bit location of the net address. After one complete pass through all 64 bits, the bus master knows the address of one device. The remaining devices can then be identified on additional iterations of the process. See Chapter 5 of the Book of DS19xx iButton ® Standards for a comprehensive discussion of a net address search, including an actual example (www.maxim-ic.com/iButtonBook). SWAP [AAh]. SWAP is a ROM level command specifically intended to aid in distributed multiplexing applications and is described specifically with regards to power control using the 27xx series of products. The term power control refers to the ability of the DS2762 to control the flow of power into or out the battery pack using control pins DC and CC. The SWAP command is issued followed by the net address. The effect is to cause the addressed device to enable power to or from the system while simultaneously (break-before-make) deselecting and powering down (SLEEP) all other packs. This switching sequence is controlled by a timing pulse issued on the DQ line following the net address. The falling edge of the pulse is used to disable power with the rising edge enabling power flow by the selected device. The DS2762 recognizes a SWAP command, device address, and timing pulse only if the SWEN bit is set. FUNCTION COMMANDS After successfully completing one of the net address commands, the bus master can access the features of the DS2762 with any of the function commands described in the following paragraphs and summarized in Table 3. The name of each function is followed by the 8-bit opcode for that command in square brackets. Read Data [69h, XX]. This command reads data from the DS2762 starting at memory address XX. The LSb of the data in address XX is available to be read immediately after the MSb of the address has been entered. Because the address is automatically incremented after the MSb of each byte is received, the LSb of the data at address XX + 1 is available to be read immediately after the MSb of the data at address XX. If the bus master continues to read beyond address FFh, the DS2762 outputs logic 1 until a reset pulse occurs. Addresses labeled “Reserved” in the memory map contain undefined data. The read data command can be terminated by the bus master with a reset pulse at any bit boundary. iButton is a registered trademark of Dallas Semiconductor.
RAM rather than EEPROM. See the Memory section for more details. EEC, is 2ms typical and starts after the last address bit is transmitted. Table 3. Function Commands
Figure 17. Net Address Command Flow Chart
1 BYTE
6 BYTES
are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read data. The bus master initiates all these types of signaling except the presence pulse. PDH and then transmits the presence pulse for tPDL. Figure 18. 1-Wire Initialization Sequence A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a logic-low level. read-time slots must be t SLOT (60/g109s to 120/g109s) in duration with a 1 /g109s minimum recovery time, t REC, between cycles. See Figure 19 for more information.
DS2762 High-Precision Li+ Battery Monitor With Alerts Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Ma xim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specification s without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products /g183 Printed USA 25 of 25 SELECTOR GUIDE PART MARKING PACKAGE INFORMATION DS2762AE DS2762A TSSOP, External Sense Resistor, 4.275V V OV DS2762BE DS2762B TSSOP, External Sense Resistor, 4.35V V OV DS2762AE/T&R DS2762A DS2762AE on Tape-and-Reel DS2762BE/T&R DS2762B DS2762BE on Tape-and-Reel DS2762AE-025 2762A25 TSSOP, 25m/g87 Sense Resistor, 4.275V VOV DS2762BE-025 2762B25 TSSOP, 25m/g87 Sense Resistor, 4.35V VOV DS2762AE-025/T&R 2762A25 DS2762AE-025 in Tape-and-Reel DS2762BE-025/T&R 2762B25 DS2762BE-025 in Tape-and-Reel DS2762AX-025/T&R DS2762AR Flip-Chip, 25m/g87 Sense Resistor, Tape-and-Reel, 4.275V VOV DS2762BX-025/T&R DS2762BR Flip-Chip, 25m/g87 Sense Resistor, Tape-and-Reel, 4.35V VOV DS2762AX/T&R DS2762A Flip-Chip, External Sense Resistor, Tape-and-Reel, 4.275V V OV DS2762BX/T&R DS2762B Flip-Chip, External Sense Resistor, Tape-and-Reel, 4.35V V OV Note: Additional VOV options are available, contact Maxim/Dallas Semiconductor sales.
PACKAGE INFORMATION
(For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)