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REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 MX25U6435F DATASHEET

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 1. FEATURES 1.8V 64M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY GENERAL

  • Serial Peripheral Interface compatible -- Mode 0 and Mode 3
  • 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/O mode) structure
  • Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually
  • Single Power Supply Operation - 1.65 to 2.0 volt for read, erase, and program operations
  • Latch-up protected to 100mA from -1V to Vcc +1V
  • Low Vcc write inhibit is from 1.0V to 1.4V PERFORMANCE
  • High Performance - Fast read for SPI mode - 1 I/O: 104MHz with 8 dummy cycles - 2 I/O: 84MHz with 4 dummy cycles, equivalent to 168MHz - 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz - Fast read for QPI mode - 4 I/O: 84MHz with 2+2 dummy cycles, equivalent to 336MHz - 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz - Fast program time: 0.5ms(typ.) and 3ms(max.)/page (256-byte per page) - Byte program time: 12us (typical) - 8/16/32/64 byte W rap-Around Burst Read Mode - Fast erase time: 35ms (typ.)/sector (4K-byte per sector); 200ms(typ.)/block (32K-byte per block), 350ms(typ.) / block (64K-byte per block)
  • Low Power Consumption - Low active read current: 20mA(typ.) at 104MHz, 15mA(typ.) at 84MHz - Low active erase current: 18mA (typ.) at Sector Erase, Block Erase (32KB/64KB); 20mA at Chip Erase - Low active programming current: 20mA (typ.) - Standby current: 15uA (typ.)
  • Deep Power Down: 1.5uA(typ.)
  • T ypical 100,000 erase/program cycles
  • 20 years data retention SOFTWARE FEATURES
  • Input Data Format - 1-byte Command code
  • Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instruc - tions - Additional 4k-bit secured OTP for unique identifier
  • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector or block - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978

  • Status Register Feature
  • Command Reset
  • Program/Erase Suspend
  • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID
  • Support Serial Flash Discoverable Parameters (SFDP) mode HARDWARE FEATURES
  • SCLK Input - Serial clock input
  • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
  • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
  • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode
  • RESET#/SIO3 - Hardware Reset pin or Serial input & Output for 4 x I/O read mode
  • P ACKAGE -8-pin SOP (200mil) -8-land WSON (6x5mm) - All devices are RoHS Compliant and Halogen-free

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 2. GENERAL DESCRIPTION MX25U6435F is 64Mb bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in two or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. MX25U6435F feature a serial pe- ripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits in- put and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and Reset# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25U6435F MXSMIO (Serial Multi I/O) provides sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte), or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 30uA DC cur - rent. The MX25U6435F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.

Table 1. Additional Feature

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 3. PIN CONFIGURATIONS 4. PIN DESCRIPTION SYMBOL DESCRIPTION CS# Chip Select SI/SIO0 Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/ O read mode) SO/SIO1 Serial Data Output (for 1 x I/O)/ Serial Data Input & Output (for 2xI/O or 4xI/ O read mode) SCLK Clock Input WP#/SIO2 Write protection: connect to GND or Serial Data Input & Output (for 4xI/O read mode) RESET#/SIO3 Hardware Reset Pin Active low or Serial Data Input & Output (for 4xI/O read mode) VCC + 1.8V Power Supply GND Ground 8-LAND WSON (6x5mm) CS# SO/SIO1 WP#/SIO2 GND VCC RESET#/SIO3 SCLK SI/SIO0 8-PIN SOP (200mil) CS# SO/SIO1 WP#/SIO2 GND VCC RESET#/SIO3 SCLK SI/SIO0

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 5. BLOCK DIAGRAM Address Generator Memory Array Page Buffer Y-Decoder X-Decoder Data Register SRAM Buffer SI/SIO0 SCLK SO/SIO1 Clock Generator State Machine Mode Logic Sense Amplifier HV Generator Output Buffer CS# WP#/SIO2 Reset#/SIO3

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 6. DATA PROTECTION During power transition, there may be some false system level signals which result in inadvertent erasure or pro - gramming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command se - quences have completed successfully. In the following, there are several features to protect the system from the accidental write cycles during VCC power- up and power-down or from system noise.

  • Power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may pro - tect the Flash.
  • Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.
  • Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before is - suing other commands to change data.
  • Deep Power Down Mode: By entering deep power down mode, the flash device is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES) and softreset command.
  • Advanced Security Features: there are some protection and security features which protect content from inad - vertent write and hostile access. I. Block lock protection - The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as "Table 2. Protected Area Sizes", the protected areas are more flexible which may protect various area by setting value of BP0-BP3 bits. - The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Reg - ister Write Protect bit. - In f our I/O and QPI mode, the feature of HPM will be disabled.

Table 2. Protected Area Sizes

vice unique serial number - Which may be set by factory or system customer.

  • Security register bit 0 ind icates whether the chip is locked by factory or not.

register bit definition and "Table 3. 4K-bit Secured OTP Definition" for address range definition. OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition

Table 4. Memory Organization

  1. Before a command is issued, status register should be checked to ensure device is ready for the intended op -
  2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until

next CS# falling edge. In standby mode, SO pin of the device is High-Z.

  1. When correct command is inputted to this device, it enters active mode and remains in active mode until next
  2. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.

The difference of Serial mode 0 and mode 3 is shown as "Serial Modes Supported".

  1. For the following instruct ions: RDID, RDSR, RDSCUR, READ, FAST_READ, DREAD, 2READ, 4READ, QREAD,

otherwise, the instruction will be rejected and not executed.

  1. While a W rite Status Register, Program or Erase operation is in progress, access to the memory array is ne -

glected and will not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Modes Supported

Table 5. Command Set

  • The fast read command (0Bh) when under QPI mode, the dummy cycle is 4 clocks.

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 Register/Setting Commands Command (byte) WREN (write enable) WRDI (write disable) RDSR (read status register) WRSR (write status register) WPSEL (Write Protect Selection) EQIO (Enable QPI) Mode SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI 1st byte 06 (hex) 04 (hex) 05 (hex) 01 (hex) 68 (hex) 35 (hex) 2nd byte Values 3rd byte 4th byte 5th byte Action sets the (WEL) write enable latch bit resets the (WEL) write enable latch bit to read out the values of the status register to write new values of the status register to enter and enable individal block protect mode Entering the QPI mode Command (byte) RSTQIO (Reset QPI) PGM/ERS Suspend (Suspends Program/Erase) PGM/ERS Resume (Resumes Program/Erase) DP (Deep power down) RDP (Release from deep power down) SBL (Set Burst Length) Mode QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI 1st byte F5 (hex) B0 (hex) 30 (hex) B9 (hex) AB (hex) C0 (hex) 2nd byte Value 3rd byte 4th byte 5th byte Action Exiting the QPI mode enters deep power down mode release from deep power down mode to set Burst length

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 Command (byte) RDID (read identific- ation) RES (read electronic ID) REMS (read electronic manufacturer & device ID) QPIID (QPI ID Read) RDSFDP ENSO (enter secured OTP) EXSO (exit secured OTP) Mode SPI SPI/QPI SPI QPI SPI/QPI SPI/QPI SPI/QPI 1st byte 9F (hex) AB (hex) 90 (hex) AF (hex) 5A (hex) B1 (hex) C1 (hex) 2nd byte x x ADD1(8) 3rd byte x x ADD2(8) 4th byte x ADD (Note 2) ADD3(8) 5th byte Dummy(8) Action outputs JEDEC ID: 1-byte Manufacturer ID & 2-byte Device ID to read out 1-byte Device ID output the Manufacturer ID & Device ID ID in QPI interface Read SFDP mode to enter the 4K-bit secured OTP mode to exit the 4K- bit secured OTP mode COMMAND (byte) RDSCUR (read security register) WRSCUR (write security register) SBLK (single block lock SBULK (single block unlock) RDBLOCK (block protect read) GBLK (gang block lock) GBULK (gang block unlock) Mode SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI 1st byte 2B (hex) 2F (hex) 36 (hex) 39 (hex) 3C (hex) 7E (hex) 98 (hex) 2nd byte ADD1 ADD1 ADD1 3rd byte ADD2 ADD2 ADD2 4th byte ADD3 ADD3 ADD3 5th byte Action to read value of security register to set the lock- down bit as "1" (once lock- down, cannot be update) individual block (64K- byte) or sector (4K-byte) write protect individual block (64K-byte) or sector (4K- byte) unprotect read individual block or sector write protect status whole chip write protect whole chip unprotect ID/Security Commands

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SO/SIO1 which is different from 1 x I/O condition. Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first. Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hid - den mode. Note 4: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the reset operation will be disabled. Note 5: The number in parentheses after "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)" represents there are 8 clock cycles for the data in. Reset Commands COMMAND (byte) NOP (No Operation) RSTEN (Reset Enable) RST (Reset Memory) Release Read Enhanced Mode SPI/QPI SPI/QPI SPI/QPI SPI/QPI 1st byte 00 (hex) 66 (hex) 99 (hex) FF (hex) 2nd byte 3rd byte 4th byte 5th byte Action (Note 4) All these commands FFh, 00h, AAh or 55h will escape the performance mode

nix Manufacturer ID and Device ID are listed as "Table 6. ID Definitions". on SO→ to end RDID operation can drive CS# to high at any time during data out. Figure 10. Read Identification (RDID) Sequence (SPI mode only)

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 6. sign, please use RDID instruction. progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. Figure 11. Read Electronic Signature (RES) Sequence (SPI Mode)

3 Dummy Bytes

3 Dummy BytesCommand

Figure 12. Read Electronic Signature (RES) Sequence (QPI Mode) Figure 13. Release from Deep Power-down (RDP) Sequence (SPI Mode) Figure 14. Release from Deep Power-down (RDP) Sequence (QPI Mode)

JEDEC assigned manufacturer ID and the specific device ID. completed by driving CS# high. (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. (2) Instruction is either 90(hex). Figure 15. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)

2 Dummy Bytes

significant bit (MSB) first. memory type, and device ID data byte will be output continuously, until the CS# goes high. Table 6. ID Definitions

  • Issue RDSR to check BP[3:0].
  • If WPSEL = 1, issue RDBLOCK to check the block status.

Figure 18. Program/Erase flow with read array data

Figure 19. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)

  • Issue RDSR to check BP[3:0].
  • If WPSEL = 1, issue RDBLOCK to check the block status.

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 Status Register Note 1: see the "Table 2. Protected Area Sizes". bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SRWD (status register write protect) QE (Quad Enable) BP3 (level of protected block) BP2 (level of protected block) BP1 (level of protected block) BP0 (level of protected block) WEL (write enable latch) WIP (write in progress bit) 1=status register write disable 1=Quad Enable 0=not Quad Enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit volatile bit volatile bit Status Register The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write sta- tus register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored if it is ap - plied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/ erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs to be confirmed as 0. BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as defined in "Table 2. Protected Area Sizes" ) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default, which is un- protected. QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#, RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET# are disabled. In the other word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET will be disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to be "0".

BP0, is at software protected mode (SPM). been set. It is rejected to write the Status Register and not be executed. BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification. To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. use software protected mode via BP3, BP2, BP1, BP0. If the system enter QPI or set QE=1, the feature of HPM will be disabled. Table 7. Protection Modes

  1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in

"Table 2. Protected Area Sizes".

Figure 22. WRSR flow

Figure 23. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 Note: WP# must be kept high until the embedded operation finish.

SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. Figure 24. Read Data Bytes (READ) Sequence (SPI Mode only)

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 9-10. Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→ 3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_ READ operation can use CS# to high at any time during data out. Read on QPI Mode The sequence of issuing FAST_READ instruction in QPI mode is: CS# goes low→ sending FAST_READ instruction, 2 cycles→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QPI FAST_READ operation can use CS# to high at any time during data out. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im - pact on the Program/Erase/Write Status Register current cycle.

tion, the following data out will perform as 2-bit instead of previous 1-bit. on the Program/Erase/Write Status Register current cycle. Figure 27. Dual Read Mode Sequence (Command 3B)

tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. operation can use CS# to high at any time during data out. on the Program/Erase/Write Status Register current cycle. Figure 28. 2 x I/O Read Mode Sequence (SPI Mode only)

12 ADD Cycles

ing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit. use CS# to high at any time during data out. pact on the Program/Erase/Write Status Register current cycle. Figure 29. Quad Read Mode Sequence (Command 6B)

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 9-14. 4 x I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Reg- ister must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next higher address af - ter each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. 4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low → sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0 →2+4 dummy cycles →data out inter- leave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out. 4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence of issuing 4READ instruction QPI mode is: CS# goes low → sending 4READ instruction→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 & SIO0 → to end 4READ operation can use CS# to high at any time during data out. Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low →sending 4 READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy cycles →data out still CS# goes high → CS# goes low (reduce 4 Read instruction) →24-bit ran- dom access address. In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; like - wise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.

Figure 30. 4 x I/O Read Mode Sequence (SPI Mode)

6 ADD Cycles

  1. Hi-impedance is inhibited for the two clock cycles.
  2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.

Figure 31. 4 x I/O Read Mode Sequence (QPI Mode)

3 E D O M

Figure 32. W4READ (Quad Read with 4 dummy cycles) Sequence

4 Dummy

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 9-16. Performance Enhance Mode The device could waive the command cycle bits if the two cycle bits after address cycle toggles. Performance enhance mode is supported in both SPI and QPI mode. In QPI mode, “EBh” “0Bh” and SPI “EBh” “E7h” commands support enhance mode. The performance enhance mode is not supported in dual I/O mode. After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of the first clock as address instead of command cycle. To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue ”FFh” command to exit enhance mode.

Figure 35. 4 x I/O Read enhance performance Mode Sequence (SPI Mode)

  1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using

performance enhance recommend to keep 1 or 0 in performance enhance indicator.

  1. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF

Figure 36. 4 x I/O Read enhance performance Mode Sequence (QPI Mode)

6 Address cycles

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 9-22. Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. There will be no effort on the other data bytes of the same page. The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at least 1-byte on data on SI→ CS# goes high. The CS# must be kept low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be checked during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode.

SIO3 as address and data input, which can improve programmer performance and the effectiveness of application. SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high. Figure 49. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)

6 ADD cycles Data

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 9-25. Enter Secured OTP (ENSO) The ENSO instruction is for entering the additional 4K-bit secured OTP mode. The additional 4K-bit secured OTP is independent from main array, which may use to store unique serial number for system identifier. After entering the Secured OTP mode, and then follow standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down. The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once se- curity OTP is lock down, only read related commands are valid. 9-26. Exit Secured OTP (EXSO) The EXSO instruction is for exiting the additional 4K-bit secured OTP mode. The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP mode→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. 9-27. Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register data out on SO→ CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. The definition of the Security Register bits is as below: Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock. Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus - tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP area cannot be update any more. While it is in 4K-bit secured OTP mode, main array access is not allowed.

The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. Table 8. Security Register Definition

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 9-29. Write Protection Selection (WPSEL) There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0, flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once WPSEL is set to 1, there is no chance to recover WPSEL bit back to “0”. If the flash is under BP mode, the indi- vidual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode is disabled. Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is conducted. BP protection mode, WPSEL=0: ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7 of status register that can be set by WRSR command. Individual block protection mode, WPSEL=1: Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, the bit 7 in security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block meth- ods.Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0. Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits. The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual block protect mode → CS# goes high. WPSEL instruction function flow is as follows: 64KB 64KB 64KB 64KB BP3 BP2 BP1 BP0 SRWD WP# pin BP and SRWD if WPSEL=0 (1) BP3~BP0 is used to define the protection group region. (The protected area size see "Table 2. Protected Area Sizes") (2) “SRWD=1 and WP#=0” is used to protect BP3~BP0. In this case, SRWD and BP3~BP0 of status register bits can not be changed by WRSR

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 The individual block lock mode is effective after setting WPSEL=1 64KB 4KB 64KB 4KB SRAM SRAM SRAM 4KB 4KB SRAM Uniform 64KB blocks SRAM SRAM 4KB SRAM SBULK / SBLK / GBULK / GBLK / RDBLOCK … … … Bottom 4KBx16 Sectors TOP 4KBx16 Sectors

  • Power-Up: All SRAM bits=1 (all blocks are default protected). All array cannot be programmed/erased
  • SBLK/SBULK(36h/39h): - SBLK(36h): Set SRAM bit=1 (protect) : array can not be programmed/erased - SBULK(39h): Set SRAM bit=0 (unprotect): array can be programmed/erased - All top 4KBx16 sectors and bottom 4KBx16 sectors and other 64KB uniform blocks can be protected and unprotected by SRAM bits individually by SBLK/SBULK command set.
  • GBLK/GBULK(7Eh/98h): - GBLK(7Eh): Set all SRAM bits=1,whole chip is protected and cannot be programmed/erased. - GBULK(98h): Set all SRAM bits=0,whole chip is unprotected and can be programmed/erased. - All sectors and blocks SRAM bits of whole chip can be protected and unprotected at one time by GBLK/GBULK command set.
  • RDBLOCK(3Ch): - use RDBLOCK mode to check the SRAM bits status after SBULK /SBLK/GBULK/GBLK command set.

Figure 52. WPSEL Flow

Figure 53. Block Lock Flow sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state. This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK). The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction. must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.

Figure 54. Block Unlock Flow

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 9-31. Read Block Lock Status (RDBLOCK) This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of protection lock of a specified block (or sector), using AMAX-A16 (or AMAX-A12) address bits to assign a 64K bytes block (4K bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3-byte address to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. 9-32. Gang Block Lock/Unlock (GBLK/GBULK) These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable the lock protection block of the whole chip. The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction. The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction →CS# goes high. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 9-33. Program/ Erase Suspend/ Resume The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other operations. Details as follows. To enter the suspend/ resume mode: issuing B0h for suspend; 30h for resume (SPI/QPI all acceptable) Read security register bit2 (PSB) and bit3 (ESB) (please refer to "Table 8. Security Register Definition" ) to check suspend ready information. For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note "Figure 55. Suspend to Read/Program Latency", "Figure 56. Resume to Read Latency" and "Figure 57. Resume to Suspend Latency". Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. 9-34. Erase Suspend Erase suspend allows the interruption of all erase operations. After erase suspend, WEL bit will be clear, following commands can be accepted. (including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, 02h, 38h, B1h, C1h, B0h, 30h, 66h, 99h, 00h, 35h, F5h) After issuing erase suspend command, latency time is needed before issuing another command. For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note "Figure 55. Suspend to Read/Program Latency", "Figure 56. Resume to Read Latency" and "Figure 57. Resume to Suspend Latency". ESB bit (Erase Suspend Bit) indicates the status of Erase suspend operation. ESB bit is set to "1" when suspend command is issued during erase operation. When erase operation resumes, ESB bit is reset to "0". Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. When ESB bit is issued, the Write Enable Latch (WEL) bit will be reset. 9-35. Program Suspend Program suspend allows the interruption of all program operations. After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0Bh, BBh, EBh, E7h, 9Fh, AFh, 90h, 05h, 2Bh, B1h, C1h, 5Ah, 3Ch, 30h, 66h, 99h, C0h, 35h, F5h, 00h, ABh ) After issuing program suspend command, latency time is needed before issuing another command. For "Suspend to Read", "Resume to Read", "Resume to Suspend" timing specification please note "Figure 55. Suspend to Read/Program Latency", "Figure 56. Resume to Read Latency" and "Figure 57. Resume to Suspend Latency". PSB bit (Program Suspend Bit) indicates the status of Program suspend operation. PSB bit is set to "1" when suspend command is issued during program operation. When program operation resumes, PSB bit is reset to "0".

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 9-36. Write-Resume The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in Status register will be changed back to “0” The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30H) → drive CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed or not. The user may also wait the time lag of TSE, TBE, TPP for Sector-erase, Block-erase or Page-programming. WREN (command "06" is not required to issue before resume. Resume to another suspend operation requires latency time of 1ms. Please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resumed. To restart the write command, disable the "performance enhance mode" is required. After the "performance enhance mode" is disable, the write-resume command is effective. 9-37. No Operation (NOP) The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not affect any other command. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode. 9-38. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST) command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will be invalid. Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care" in SPI mode. If the Reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. The reset time is different depending on the last operation. Longer latency time is required to recover from a pro - gram operation than from other operations.

operation can use CS# to high at any time during data out. SFDP is a JEDEC Standard, JESD216. Figure 61. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence

24 BIT ADDRESS

Table 9. Signature and Parameter Identification Data Values

Table 10. Parameter Table (0): JEDEC Flash Parameter Tables

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 Description Comment Add (h) (Byte) DW Add (Bit) Data (h/b) (Note1) Data (h) (1-1-2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 3Ch 04:00 0 1000b 08h(1-1-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 07:05 000b (1-1-2) Fast Read Opcode 3Dh 15:08 3Bh 3Bh (1-2-2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 3Eh 20:16 0 0100b 04h(1-2-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 000b (1-2-2) Fast Read Opcode 3Fh 31:24 BBh BBh (2-2-2) Fast Read 0=not support 1=support 40h 00 0b FEh Unused 03:01 111b (4-4-4) Fast Read 0=not support 1=support 04 1b Unused 07:05 111b Unused 43h:41h 31:08 FFh FFh Unused 45h:44h 15:00 FFh FFh (2-2-2) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 46h 20:16 0 0000b 00h(2-2-2) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 000b (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh Unused 49h:48h 15:00 FFh FFh (4-4-4) Fast Read Number of Wait states 0 0000b: Wait states (Dummy Clocks) not support 4Ah 20:16 0 0100b 44h(4-4-4) Fast Read Number of Mode Bits 000b: Mode Bits not support 23:21 010b (4-4-4) Fast Read Opcode 4Bh 31:24 EBh EBh Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0x00b: this sector type doesn't exist 4Ch 07:00 0Ch 0Ch Sector Type 1 erase Opcode 4Dh 15:08 20h 20h Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist 4Eh 23:16 0Fh 0Fh Sector Type 2 erase Opcode 4Fh 31:24 52h 52h Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist 50h 07:00 10h 10h Sector Type 3 erase Opcode 51h 15:08 D8h D8h Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist 52h 23:16 00h 00h Sector Type 4 erase Opcode 53h 31:24 FFh FFh

Table 11. Parameter Table (1): Macronix Flash Parameter Tables

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 Note 1: h/b is hexadecimal or binary . Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: All unused and undefined area data is blank FFh

  • All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.

Figure 62. RESET Timing Table 12. Reset Timing

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 11. POWER-ON STATE The device is at below states when power-up: - Standby mode (please n ote it is not deep power-down mode) - W rite Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power- up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any command. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the "Figure 69. Power-up Timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend - ed. (generally around 0.1uF) - At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.

  1. ELECTRICAL SPECIFICATIONS

Figure 63. Maximum Negative Overshoot Waveform Figure 64. Maximum Positive Overshoot Waveform

  1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to

the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.

  1. Specifications contained within the following tables are subject to change.
  2. During voltage transitions, all pins may overshoot to VCC+1.0V or -1.0V for period up to 20ns.

Table 13. Absolute Maximum Ratings Table 14. Capacitance

Table 15. DC Characteristics

  1. T ypical values at VCC = 1.8V, T = 25 °C. These currents are valid for all product versions (package and speeds).
  2. T ypical value is calculated by simulation.

Table 16. AC Characteristics Symbol Alt. Parameter Min. Typ.

50 MHz

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 Notes: 1. tCH + tCL must be greater than or equal to 1/ Frequency. 2. Typical values given for TA=25°C. Not 100% tested. 3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 4. Test condition is shown as "Figure 65. Input Test Waveforms and Measurement Level" , "Figure 66. Output Load- ing". 5. When dummy cycle=4 (In both QPI & SPI mode), maximum clock rate=84MHz; when dummy cycle=6 (In both QPI & SPI mode), maximum clock rate=104MHz. 6. The maximum clock rate=33MHz when reading secured OTP area. 7. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to pro- gram the whole 256 bytes or only a few bytes between 1~256 bytes. 8. “n”=how many bytes to program. In the formula, while n=1, byte program time=12us.

  1. Sampled, not 100% tested .
  2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to

"Table 16. AC Characteristics". nored, the device will not operate correctly. selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 67. AC Timing at Device Power-Up

Figure 68. Power-Down Sequence During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.

Register contains 00h (all Status Register bits are 0). Figure 69. Power-up Timing Note: 1. These parameters are characterized only. Table 17. Power-Up Timing and VWI Threshold

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 14. ERASE AND PROGRAMMING PERFORMANCE Note: 1. T ypical erase assumes the following conditions: 25 °C, 1.8V, and all zero pattern. 2. Under worst conditions of 85°C and 1.65V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com - mand. 4. The maximum chip progra mming time is evaluated under the worst conditions of 0 °C, VCC=1.8V, and 100K cy- cle with 90% confidence level. 5. T ypical program assumes the following conditions: 25 °C, 1.8V, and checkerboard pattern. 15. LATCH-UP CHARACTERISTICS PARAMETER Min. Typ. (1) Max. (2) Unit Write Status Register Cycle Time 40 ms Sector Erase Cycle Time (4KB) 35 200 ms Block Erase Cycle Time (32KB) 0.2 1 s Block Erase Cycle Time (64KB) 0.35 2 s Chip Erase Cycle Time 50 75 s Byte Program Time (via page program command) 12 (5) 30 us Page Program Time 0.5 (5) 3 ms Erase/Program Cycle 100,000 cycles Min. Max. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V Current -100mA +100mA Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin at a time.

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 16. ORDERING INFORMATION PART NO. CLOCK (MHz) TEMPERATURE PACKAGE Remark MX25U6435FM2I-10G 104 -40°C~85°C 8-SOP (200mil) MX25U6435FZNI-10G 104 -40°C~85°C 8-WSON (6x5mm)

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 17. PART NAME DESCRIPTION MX 25 U 10ZN I G OPTION: G: RoHS Compliant and Halogen-free SPEED: 10: 104MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: M2: 8-SOP(200mil) ZN: 8-WSON DENSITY & MODE: 6435F: 64Mb TYPE: U: 1.8V DEVICE: 25: Serial Flash 6435F

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 18. PACKAGE INFORMATION

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978

REV. 1.2, OCT. 23, 2013 MX25U6435F P/N: PM1978 19. REVISION HISTORY Revision No. Description Page Date 0.01 1. Modified Chip Erase Cycle Time P78,83 AUG/25/2011 2. Modified tVSL(min.) from 500us to 800us P82 0.02 1. Changed title from "Advanced Information" to "Preliminary" P4 OCT/06/2011 2. Modified Write Protection Selection (WPSEL) description P59,60 3. Modified Power-up Timing P84 1.0 1. Modified tVSL(min.) in Power-Up Timing Table P84 FEB/03/2012 2. Modified valu e of tWHSL, tSHWL, tCHDX, tCHSH, tSHCH, P79,80 tSHSL and ISB1(max.) in CHARACTERISTICS Table 3. Added Reset# description for write/erase execution P33,49,50~53,58,75 1.1 1. Add DREAD function P7,14,17,39 SEP/25/2013 2. Add QREAD function P7,14,17,41 3. Update DREA D(1-1-2) / QREAD(1-1-4) in SFDP Table P72,73 4. Modified Data Retention value P4 5. Remove MX25U3235F All 6. Modified tVSL value P85 7. Modify accepted commands after Erase Suspend P66 8. Modified Pag e Program time P4,81,86 1.2 1. Updated Eras e time and Consumption current P4 OCT/23/2013 2. Updated ISB1, ISB2, ICC3 and ICC4 in DC Table P80 3. Updated tSE, tBE32, tBE and tCE in AC Table P81 4. Updated Eras e time P86

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